; -------------------------------------------------------------------------------- ; @Title: AM572x On-Chip Peripherals ; @Props: Released ; @Author: KMW ; @Changelog: 2019-03-05 KMW ; @Manufacturer: TI - Texas Instruments ; @Core: Cortex-A15, Cortex-M4, ARM9, C646X, PRU ; @Copyright: 1989-2019 Lauterbach GmbH, licensed for use with TRACE32 only ; -------------------------------------------------------------------------------- ; $Id: peram572x_sr1.per 17736 2024-04-08 09:26:07Z kwisniewski $ sif (!cpuis("AM572X-ICSS?")&&cpu()!="PRU") sif cpuis("AM572X") tree "Core Registers (Cortex-A15MPCore)" ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- width 10. tree "ID Registers" group.long c15:0x0++0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." textline " " bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,Reserved,Physical" bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,16 words,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x100++0x0 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Reserved,Reserved,Reserved,Reserved,ARMv7,?..." bitfld.long 0x0 24.--27. " CWG ,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 20.--23. " ERG ,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." textline " " bitfld.long 0x0 16.--19. " DMINLINE ,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,8 words,?..." endif rgroup.long c15:0x300++0x0 line.long 0x0 "TLBTR,TLB Type Register" bitfld.long 0x0 0. " NU ,Unified or Separate TLBs" "Unified,?..." rgroup.long c15:0x500++0x0 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 31. " MPERF ,Multiprocessing Extensions register format" "Not supported,Supported" bitfld.long 0x00 30. " U ,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" bitfld.long 0x00 24. " MT ,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" textline " " bitfld.long 0x00 8.--11. " CLUSTERID ,Value read in CLUSTERID configuration pins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " CPUID ,Value depends on the number of configured CPUs" "1,2,3,4" rgroup.long c15:0x400++0x0 line.long 0x0 "MIDR2,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x600++0x0 line.long 0x0 "REVIDR,Revision ID Register" rgroup.long c15:0x700++0x0 line.long 0x0 "MIDR3,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 1. " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,PXN,64-bit,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IS ,Indicates innermost shareability domain implemented" "Reserved,Implemented,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. " AR ,Auxiliary Register Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. " SL ,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. " OSS ,Outer Shareable Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Supported,?..." endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,Required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." endif rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. " PMS ,Physical memory size supported by processor caches" "Reserved,Reserved,40-bit,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Maintenance broadcast Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " BPM ,Invalidate Branch predictor Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache MVA Support" "Reserved,Supported,?..." if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Not supported,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,BKPT,?..." bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Supported,?..." endif rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " EXTI ,Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " EARI ,Exception A and R Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " EXIN ,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,MUL/MLA/MLS,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLWD,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,LDRD/STRD,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " TEEEI ,Thumb-EE Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,TBB/TBH,?..." bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,Memory System Locking Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " SPRI ,Synchronization Primitive instructions" "Supported,?..." textline " " bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,DMB/DSB/ISB,?..." bitfld.long 0x00 12.--15. " SMCI ,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb Execution Environment (Thumb-EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Support for Jazelle extension" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 16.--19. " GT ,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " VE ,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 24.--27. " PMM ,Performance Monitor Model Support" "Reserved,Reserved,ID_DFR0,?..." bitfld.long 0x00 20.--23. " MDM_MM ,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TM_MM ,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " CTM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..." textline " " bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,ARMv7.1/CP14,?..." if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented" bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented" textline " " bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented" textline " " bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 15. " [15] ,Instruction architecturally executed, condition code check pass, unaligned load or store" "Not implemented,Implemented" textline " " bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented" bitfld.long 0x00 13. " [13] ,Instruction architecturally executed, immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. " [12] ,Instruction architecturally executed, condition code check pass, software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented" textline " " bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. " [8] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 7. " [7] ,Instruction architecturally executed, condition code check pass, store" "Not implemented,Implemented" textline " " bitfld.long 0x00 6. " [6] ,Instruction architecturally executed, condition code check pass, load" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented" bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 31. " PMCEID0[31] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 30. " [30] ,Level 1 data memory access" "Not implemented,Implemented" bitfld.long 0x00 29. " [29] ,Level 1 data memory access" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Level 1 data memory access" "Not implemented,Implemented" textline " " bitfld.long 0x00 27. " [27] ,Branches or other change in program flow that could have been predicted by the branch prediction resources of the processor" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Branch mispredicted or not predicted" "Not implemented,Implemented" bitfld.long 0x00 25. " [25] ,Unaligned access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Unaligned access" "Not implemented,Implemented" textline " " bitfld.long 0x00 23. " [23] ,Branch speculatively executed - Procedure return" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Branch speculatively executed - Immediate branch" "Not implemented,Implemented" bitfld.long 0x00 21. " [21] ,Instruction speculatively executed - Software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Write to translation table register (TTBR0 or TTBR1)" "Not implemented,Implemented" textline " " bitfld.long 0x00 19. " [19] ,Change to ContextID retired" "Not implemented,Implemented" bitfld.long 0x00 18. " [18] ,Exception return architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 17. " [17] ,Exception taken. Counts the number of exceptions architecturally taken" "Not implemented,Implemented" bitfld.long 0x00 16. " [16] ,Instruction architecturally executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 15. " [15] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 14. " [14] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 13. " [13] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 12. " [12] ,Instruction architecturally executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 11. " [11] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 10. " [10] ,Instruction architecturally executed" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Store instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 8. " [8] ,Store instruction speculatively executed" "Not implemented,Implemented" textline " " bitfld.long 0x00 7. " [7] ,Load instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 6. " [6] ,Load instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Data read or write operation that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented" bitfld.long 0x00 4. " [4] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" textline " " bitfld.long 0x00 3. " [3] ,Data read or write operation that causes a cache access at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" bitfld.long 0x00 2. " [2] ,Data read or write operation that causes a refill at (at least) the lowest level of data or unified cache" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Instruction fetch that causes a TLB refill at (at least) the lowest level of TLB" "Not implemented,Implemented" bitfld.long 0x00 0. " [0] ,Instruction fetch that causes a refill at (at least) the lowest level of instruction or unified cache" "Not implemented,Implemented" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x6C9++0x0 line.long 0x00 "PMCEID0,Common Event Identification Register 0" bitfld.long 0x00 29. " PMCEID0[29] ,Bus cycle" "Not implemented,Implemented" bitfld.long 0x00 28. " [28] ,Instruction architecturally executed. Condition code check pass, write to TTBR" "Not implemented,Implemented" bitfld.long 0x00 27. " [27] ,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. " [26] ,Local memory error" "Not implemented,Implemented" textline " " bitfld.long 0x00 25. " [25] ,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. " [24] ,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. " [23] ,Level 2 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 22. " [22] ,Level 2 data cache access" "Not implemented,Implemented" textline " " bitfld.long 0x00 21. " [21] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 20. " [20] ,Level 1 instruction cache access" "Not implemented,Implemented" bitfld.long 0x00 19. " [19] ,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 14. " [14] ,Instruction architecturally executed, condition code check pass, procedure return" "Not implemented,Implemented" textline " " bitfld.long 0x00 11. " [11] ,Instruction architecturally executed, condition code check pass, write to CONTEXTIDR" "Not implemented,Implemented" bitfld.long 0x00 10. " [10] ,Instruction architecturally executed, condition code check pass, exception return" "Not implemented,Implemented" bitfld.long 0x00 9. " [9] ,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 5. " [5] ,Level 1 data TLB refill" "Not implemented,Implemented" textline " " bitfld.long 0x00 2. " [2] ,Level 1 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 1. " [1] ,Level 1 instruction cache refill" "Not implemented,Implemented" endif tree.end width 12. tree "System Control and Configuration" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" textline " " bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled" bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled" textline " " endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled" bitfld.long 0x00 3. " ASSE ,ACE STREX Signalling Enable" "Disabled,Enabled" bitfld.long 0x00 2. " L2PF ,Enable L2 prefetch" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " L1PF ,Enable L1 prefetch" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " SDEH ,Snoop-delayed exclusive handling" "Normal,Modified" bitfld.long 0x00 30. " FMCEA ,Force main clock processor enable active" "Not prevented,Prevented" bitfld.long 0x00 29. " FNVCEA ,Force NEON/VFP clock enable active" "Not prevented,Prevented" textline " " bitfld.long 0x00 27.--28. " WSNAT ,Write streaming no-allocate threshold" "12th,128th,512th,Disabled" bitfld.long 0x00 25.--26. " WSNL1AT ,Write streaming no L1-allocate threshold" "14th,64th,128th,Disabled" bitfld.long 0x00 24. " NCSE ,Non-cacheable streaming enhancement" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " FIORRTTSSAW ,Forces in-order requests to the same set and way" "Not forced,Forced" bitfld.long 0x00 22. " FIOLI ,Force in-order load issue" "Not forced,Forced" bitfld.long 0x00 21. " DL2TLBP ,Disabled L2 TLB prefetching" "No,Yes" textline " " bitfld.long 0x00 20. " DL2TBWIPAPAC ,Disable L2 TBW IPA PA cache" "No,Yes" bitfld.long 0x00 19. " DL2TBWS1WC ,Disable L2 TBW Stage 1 walk cache" "No,Yes" bitfld.long 0x00 18. " DL2TBWS1L2PAC ,Disable L2 TBW stage 1 L2 PA cache" "No,Yes" textline " " bitfld.long 0x00 17. " DL2TLBPO ,Disable L2 TLB Performance Optimization" "No,Yes" bitfld.long 0x00 16. " EFSOADLR ,Enables full Strongly-ordered and Device load replay" "Disabled,Enabled" bitfld.long 0x00 15. " FIIBEU ,Force in-order issue in branch execution unit" "Not forced,Forced" textline " " bitfld.long 0x00 14. " FLOIGCDPC ,Force limit of one instruction group commit/de-allocate per cycle" "Not forced,Limited" bitfld.long 0x00 13. " FACP14WCP15 ,Flush after CP14 and CP15 writes" "Normal,Flushed" bitfld.long 0x00 12. " FPCP14CP15 ,Force push of CP14 and CP15 registers" "Not forced,Pushed" textline " " bitfld.long 0x00 11. " FOISEG ,Force one instruction to start and end a group" "Not forced,Forced" bitfld.long 0x00 10. " FSAEIG ,Force serialization after each instruction group" "Not forced,Forced" bitfld.long 0x00 9. " DFRO ,Disable flag renaming optimization" "No,Yes" textline " " bitfld.long 0x00 8. " EWFIIANOPI ,Executes WFI instructions as NOP instructions" "Disabled,Enabled" bitfld.long 0x00 7. " EWFEIANOPI ,Executes WFE instructions as NOP instructions" "Disabled,Enabled" bitfld.long 0x00 6. " SMP ,Broadcast of cache and TLB maintenance operations enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EPLDIANOP ,Execute PLD and PLDW instructions as a NOP instruction" "Disabled,Enabled" bitfld.long 0x00 4. " DIP ,Disable indirect predictor" "No,Yes" bitfld.long 0x00 3. " DMBTB ,Disable micro-BTB" "No,Yes" textline " " bitfld.long 0x00 2. " LOLBDPF ,Limits to one loop buffer detect per flush" "Normal,Limited" bitfld.long 0x00 1. " DLB ,Disable loop buffer" "No,Yes" bitfld.long 0x00 0. " EIBTB ,Enable invalidate of BTB" "Disabled,Enabled" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x101++0x0 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 28. " DBDI ,Disable branch dual issue" "No,Yes" bitfld.long 0x00 15. " DDVM ,Disable Distributed Virtual Memory (DVM) transactions" "No,Yes" bitfld.long 0x00 13.--14. " L1PCTL ,L1 Data prefetch control" "Disabled,1 pre-fetch,2 pre-fetches,3 pre-fetches" textline " " bitfld.long 0x00 12. " L1RADIS ,L1 Data Cache read-allocate mode disable" "No,Yes" bitfld.long 0x00 11. " L2RADIS ,L2 Data Cache read-allocate mode disable" "No,Yes" bitfld.long 0x00 10. " DODMBS ,Disable optimised data memory barrier behaviour" "No,Yes" textline " " bitfld.long 0x00 6. " SMP ,Enables coherent requests to the processor" "Disabled,Enabled" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x140F++0x00 line.long 0x0 "ACTLR2,Auxiliary Control Register 2" bitfld.long 0x00 31. " ECRCG ,Enable CPU regional clock gates" "Disabled,Enabled" bitfld.long 0x00 0. " EDCCADCCI ,Execute data cache clean as data cache clean/invalidate" "Disabled,Enabled" textline " " else hgroup.long c15:0x140F++0x00 hide.long 0x0 "ACTLR2,Auxiliary Control Register 2" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of registers D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x0 22.--23. " CP11 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 20.--21. " CP10 ,Coprocessor access control" "Denied,Privileged,Reserved,Full" endif group.long c15:0x11++0x0 line.long 0x0 "SCR,Secure Configuration Register" bitfld.long 0x00 9. " SIF ,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. " HCE ,Hyp Call enable" "Undefined,Enabled" bitfld.long 0x00 7. " SCD ,Secure Monitor Call disable" "No,Yes" textline " " bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. " FW ,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" textline " " bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted" bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 17. " NS_L2ERR ,L2 internal asynchronous error and AXI asynchronous error writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" textline " " bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 18. " NS_SMP ,Determines if the SMP bit of the Auxiliary Control Register is writeable in Non-secure state" "Non-writeable,Writeable" bitfld.long 0x00 17. " NS_L2ERR ,Determines if the L2 Extended Control Register(L2ECTLR), is writeable in Non-secure state" "Non-writeable,Writeable" bitfld.long 0x00 16. " NS_ACTLR_PF_WRITE ,Determines if the ACTLR.L1PF and ACTLR.L2PF registers are writeable in Non-secure state" "Non-writeable,Writeable" textline " " bitfld.long 0x00 15. " NSASEDIS ,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 14. " NSD32DIS ,Disable the Non-secure use of D16-D31 of the VFP register file" "No,Yes" bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" textline " " bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" endif group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " VBADDR ,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " MVBADDR ,Monitor Vector Base Address" textline " " rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. " A ,External abort pending flag" "Not pending,Pending" bitfld.long 0x00 7. " I ,Interrupt pending flag" "Not pending,Pending" bitfld.long 0x00 6. " F ,Fast interrupt pending flag" "Not pending,Pending" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x400F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.tbyte 0x00 15.--31. 1. " PERIPHBASE[31:15] ,Periphbase[31:15]" hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]" else hgroup.long c15:0x400F++0x00 hide.long 0x00 "CBAR,Configuration Base Address Register" endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x1609))&0x3)==0x3) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 30. " PRM3 ,Disable processor 3 retention" "No,Yes" bitfld.long 0x00 28.--29. " PPS3 ,Processor 3 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes" textline " " bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" textline " " bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 7. " CPSMP[3] ,Copy of the ACTLR.SMP for processor 3" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x2) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 26. " PRM2 ,Disable processor 2 retention" "No,Yes" bitfld.long 0x00 24.--25. " PPS2 ,Processor 2 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" textline " " bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" textline " " bitfld.long 0x00 6. " CPSMP[2] ,Copy of the ACTLR.SMP for processor 2" "Disabled,Enabled" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x1) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 22. " PRM1 ,Disable processor 1 retention" "No,Yes" bitfld.long 0x00 20.--21. " PPS1 ,Processor 1 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" textline " " bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 5. " CPSMP[1] ,Copy of the ACTLR.SMP for processor 1" "Disabled,Enabled" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " elif (((d.l(c15:0x1609))&0x3)==0x0) group.long c15:0x1609++0x00 line.long 0x00 "SCUCTLR,SCU Control Register" bitfld.long 0x00 18. " PRM0 ,Disable processor 0 retention" "No,Yes" bitfld.long 0x00 16.--17. " PPS0 ,Processor 0 power status" "Normal,Not present,Retention,Powerdown" bitfld.long 0x00 4. " CPSMP[0] ,Copy of the ACTLR.SMP for processor 0" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " NP ,Number of processors" "1,2,3,4" textline " " endif group.long c15:0x410F++0x00 line.long 0x00 "FILASTARTR,Peripheral port start address register" hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_START_ADDR ,Start address of the peripheral port physical memory region" bitfld.long 0x00 0. " FILT_EN ,FLT_START_ADDR and FLT_END_ADDR are valid" "Invalid,Valid" group.long c15:0x420F++0x00 line.long 0x00 "FILAENDR,Peripheral port end address register" hexmask.long.tbyte 0x00 12.--31. 0x10 " FLT_END_ADDR ,End address of the peripheral port physical memory region" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") hgroup.long c15:0x1609++0x00 hide.long 0x00 "SCUCTLR,SCU Control Register" hgroup.long c15:0x410F++0x00 hide.long 0x00 "FILASTARTR,Peripheral port start address register" hgroup.long c15:0x420F++0x00 hide.long 0x00 "FILAENDR,Peripheral port end address register" endif tree.end width 12. tree "Memory Management Unit" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Alignment Fault Check enable" "Disabled,Enabled" bitfld.long 0x0 0. " M ,Address translation enable bit" "Disabled,Enabled" textline " " elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 20. " UWXN ,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x0 19. " WXN ,Write permission implies PL1 Execute Never" "Not forced,Forced" textline " " bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SW ,SWP/SWPB Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disabled,Enabled" textline " " endif if (((d.l(c15:0x0002))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address" bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0002))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Register 0" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB0_ADDR ,Translation table base 0 address" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" textline " " bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Register 0" hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" endif if (((d.l(c15:0x0102))&0x2)==0x2)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address" bitfld.long 0x00 5. " NOS ,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0102))&0x2)==0x0)&&(((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Register 1" hexmask.long.tbyte 0x00 14.--31. 0x40 " TTB1_ADDR ,Translation table base 1 address" bitfld.long 0x00 3.--4. " RGN ,Region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 2. " IMP ,Implementation defined" "Low,High" textline " " bitfld.long 0x00 1. " S ,Shareable bit" "Non-shareable,Shareable" bitfld.long 0x00 0. 6. " IRGN ,Inner region bits for Multiprocessing Extensions" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" elif (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Register 1" hexmask.quad.byte 0x00 48.--55. 1. " ASID ,ASID for the translation table base address" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" endif if (((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. " PD1 ,Translation table walk Disable bit for TTBR1" "No,Yes" bitfld.long 0x00 4. " PD0 ,Translation table walk Disable bit for TTBR0" "No,Yes" textline " " bitfld.long 0x00 0.--2. " N ,Indicate the width of the base address held in TTBR0" "16KB,8KB,4KB,2KB,1KB,512 bytes,256 bytes,128 bytes" else group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. " EAE ,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 30. " IMP ,IMPLEMENTATION DEFINED" "Low,High" bitfld.long 0x00 28.--29. " SH1 ,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" textline " " bitfld.long 0x00 26.--27. " ORGN1 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 24.--25. " IRGN1 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 23. " EPD1 ,Translation table walk disable for translations using TTBR1" "No,Yes" textline " " bitfld.long 0x00 22. " A1 ,Selects whether TTBR0 or TTBR1 defines the ASID" "TTBR0,TTBR1" bitfld.long 0x00 16.--18. " T1SZ ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using TTBR0" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" textline " " bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 7. " EPD0 ,Translation table walk disable for translations using TTBR0" "No,Yes" textline " " bitfld.long 0x00 0.--2. " T0SZ ,The Size offset of the TTBR0 addressed memory region" "0,1,2,3,4,5,6,7" endif textline " " group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown Abort,Reserved,Reserved,Reserved,Reserved,Reserved,Coprocessor Abort,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Fault Status" "Reserved,Alignment fault,Reserved,Reserved,Instruction cache maintenance fault,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort/First level,Permission fault/First level,Synchronous external abort/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk/First level,Reserved,Synchronous parity error on translation table walk/Second level,Reserved" endif elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/synchronous external,Permission/section,L2/synchronous external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." endif elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 13. " CM ,Cache maintenance fault" "Not aborted,Aborted" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " WNR ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." endif endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier" bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error" textline " " bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" else hgroup.long c15:0x0015++0x00 hide.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access flag fault/First level,Access flag fault/Second level,Access flag fault/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/First level,Synchronous external abort on translation table walk/Second level,Synchronous external abort on translation table walk/Third level,Synchronous parity error on memory access,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/First level,Synchronous parity error on memory access on translation table walk/Second level,Synchronous parity error on memory access on translation table walk/Third level,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug event,Access flag fault/First level,Reserved,Translation fault/First level,Access flag fault/Second level,Translation fault/Second level,Non-translation/synchronous external abort,Domain fault/First level,Reserved,Domain fault/Second level,Synchronous external abort on translation table walk/First level,Permission fault/First level,Synchronous external abort on translation table walk/Second level,Permission fault/Second level,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous parity error on memory access,Reserved,Reserved,Synchronous parity error on translation table walk,Reserved,Synchronous parity error on translation table walk,Reserved" endif elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") if (((d.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--5. " STATUS ,Generated Exception Type" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/First level,Translation fault/Second level,Translation fault/Third level,Reserved,Access fault flag/First level,Access fault flag/Second level,Access fault flag/Third level,Reserved,Permission fault/First level,Permission fault/Second level,Permission fault/Third level,Synchronous external abort,Reserved,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Non-translation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,?..." endif elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--5. " STATUS ,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Reserved,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug event,?..." else group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Type" "DECERR,SLVERR" bitfld.long 0x00 9. " LPAE ,Large physical address extension" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. 10. " FS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Reserved,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,TLB,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." endif endif group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" if (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x0) group.quad c15:0x0047++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. " ATTR ,Memory attributes for the returned PA" hexmask.quad 0x00 12.--39. 0x1000 " PA ,Physical Address" bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" textline " " bitfld.quad 0x00 9. " NS ,Non-secure" "Secure,Non-secure" bitfld.quad 0x00 7.--8. " SH ,Shareability attribute" "Non-shareable,Unpredictable,Outer Shareable,Inner Shareable" bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x80000000&&((d.q(c15:0x0047))&0x1)==0x1) group.quad c15:0x0047++0x01 line.quad 0x00 "PAR,Physical Address Register" bitfld.quad 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" bitfld.quad 0x00 9. " FSTAGE ,Translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. " S2WLK ,Stage 2 fault during a stage 1 translation table walk" "Not occurred,Occurred" textline " " bitfld.quad 0x00 1.--6. " FS ,Fault status field" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation fault/1st level,Translation fault/2nd level,Translation fault/3rd level,Reserved,Access flag fault/1st level,Access flag fault/2nd level,Access flag fault/3rd level,Reserved,Permission fault/1st level,Permission fault/2nd level,Permission fault/3rd level,Synchronous external abort,Asynchronous external abort,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/1st level,Synchronous external abort on translation table walk/2nd level,Synchronous external abort on translation table walk/3rd level,Synchronous parity error on memory access, Asynchronous parity error on memory access,Reserved,Reserved,Reserved,Synchronous parity error on memory access on translation table walk/1st lvl,Synchronous parity error on memory access on translation table walk/2nd lvl,Synchronous parity error on memory access on translation table walk/3rd lvl,Reserved,Alignment fault,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Domain fault/1st lvl,Domain fault/2nd lvl,Reserved" textline " " bitfld.quad 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x0) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" hexmask.long.tbyte 0x00 12.--31. 0x1000 " PA ,Physical Address" bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" bitfld.long 0x00 10. " NOS ,Not Outer Shareable attribute" "Outer shareable,Not outer shareable" textline " " bitfld.long 0x00 9. " NS ,Non-secure" "Secure,Non-secure" bitfld.long 0x00 7. " SH ,Shareability attribute" "Non-shareable,Shareable" bitfld.long 0x00 4.--6. " INNER ,Inner memory attributes" "Non-cacheable,Strongly-ordered,-,Device,-,Write-Back Write-Allocate,Write-Through,Write-Back no Write-Allocate" textline " " bitfld.long 0x00 2.--3. " OUTER ,Outer memory attributes" "Non-cacheable,Write-Back Write-Allocate,Write-Through no Write-Allocate,Write-Back no Write-Allocate" bitfld.long 0x00 1. " SS ,Supersection" "Not a Supersection,Supersection" bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " elif (((d.l(c15:0x202))&0x80000000)==0x00&&((d.q(c15:0x0047))&0x1)==0x1) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" bitfld.long 0x00 11. " LPAE ,Long-descriptor translation table format use" "Not used,Used" textline " " bitfld.long 0x00 1.--6. " FS ,Fault status" "Reserved,Alignment fault,Debug event,Access flag fault/1st lvl,Fault on instruction cache maintenance,Translation fault/1st lvl,Access flag fault/2nd lvl,Translation fault/2nd lvl,Synchronous external abort,Domain fault/1st lvl,Reserved,Domain fault/2nd lvl,Synchronous external abort on translation table walk/1st lvl,Permission fault/1st lvl,Synchronous external abort on translation table walk/2nd lvl,Permission fault/2nd lvl,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external abort,Reserved,Asynchronous parity error on memory access,Synchronous parity error on memory access,,,Synchronous parity error on translation table walk/1st lvl,Reserved,Synchronous parity error on translation table walk/2nd lvl,Reserved,?..." textline " " bitfld.long 0x00 0. " F ,Conversion completed successfully" "Successful,Unsuccessful" textline " " endif if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") hgroup.long c15:0x003A++0x00 hide.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" hgroup.long c15:0x013A++0x00 hide.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" endif else group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. " NOS7 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. " NOS6 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 29. " NOS5 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" textline " " bitfld.long 0x00 28. " NOS4 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 27. " NOS3 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. " NOS2 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" textline " " bitfld.long 0x00 25. " NOS1 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. " NOS0 ,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped" textline " " bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped" bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped" bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped" textline " " bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP" textline " " bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP" bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP" group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through no allocate,Write-back no allocate" textline " " endif if (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x400F++0x00 line.long 0x00 "CBAR,Configuration Base Address Register" hexmask.long.tbyte 0x00 15.--31. 0x80 " PERIPHBASE[31:15] ,Periphbase[31:15]" hexmask.long.byte 0x00 0.--7. 1. " PERIPHBASE[39:32] ,Periphbase[39:32]" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") hgroup.long c15:0x400F++0x00 hide.long 0x00 "CBAR,Configuration Base Address Register" endif textline " " if (((d.l(c15:0x202))&0x80000000)==0x80000000) group.long c15:0x10d++0x00 line.long 0x0 "CONTEXTIDR,Context ID Register" else group.long c15:0x10d++0x00 line.long 0x0 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,Process identifier" hexmask.long.byte 0x00 0.--7. 1. " ASID ,Address space identifier" endif group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,User Read/Write Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,User Read-Only Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,EL1 only Thread ID Register" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hyp Software Thread ID Register" tree.end width 15. tree "Virtualization Extensions" group.long c15:0x4000++0x00 line.long 0x0 "VPIDR,Virtualization Processor ID Register" group.long c15:0x4500++0x00 line.long 0x0 "VMPIDR,Virtualization Multiprocessor ID Register" group.long c15:0x4001++0x00 line.long 0x00 "HSCTLR,System Control Register" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 25. " EE ,Exception endianness" "Little,Big" bitfld.long 0x0 19. " WXN ,Write permission implies XN" "Not forced,Forced" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disabled,Enabled" bitfld.long 0x0 1. " A ,Strict Alignment" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " M ,Enable address translation" "Disabled,Enabled" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hyp Configuration Register" bitfld.long 0x00 27. " TGE ,Trap General Exceptions" "Disabled,Enabled" bitfld.long 0x00 26. " TVM ,Trap Virtual Memory Controls" "Disabled,Enabled" bitfld.long 0x00 25. " TTLB ,Trap TLB maintenance instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " TPU ,Trap Cache maintenance instructions to point of unification" "Disabled,Enabled" bitfld.long 0x00 23. " TPC ,Trap Data/Unified cache maintenance instructions to point of coherency" "Disabled,Enabled" bitfld.long 0x00 22. " TSW ,Trap Data/Unified cache Set/Way instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " TAC ,Trap Auxiliary Control Register Accesses" "Disabled,Enabled" bitfld.long 0x00 20. " TIDCP ,Trap Lockdown" "Disabled,Enabled" bitfld.long 0x00 19. " TSC ,Trap SMC" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " TID3 ,Trap ID Group 3" "Disabled,Enabled" bitfld.long 0x00 17. " TID2 ,Trap ID Group 2" "Disabled,Enabled" bitfld.long 0x00 16. " TID1 ,Trap ID Group 1" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " TID0 ,Trap ID Group 0" "Disabled,Enabled" bitfld.long 0x00 14. " TWE ,Trap WFE" "Disabled,Enabled" bitfld.long 0x00 13. " TWI ,Trap WFI" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " DC ,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. " BSU ,Barrier Shareability Upgrade" "No effect,Inner,Outer,Full system" bitfld.long 0x00 9. " FB ,Force Broadcast of TLB maintenance BPIALL and ICIALLU instructions" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " VA ,Virtual External Asynchronous Abort" "Not aborted,Aborted" bitfld.long 0x00 7. " VI ,Virtual IRQ interrupt" "No interrupt,Interrupt" bitfld.long 0x00 6. " VF ,Virtual FIQ interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " AMO ,A-bit Mask Override" "No override,Override" bitfld.long 0x00 4. " IMO ,I-bit Mask Override" "No override,Override" bitfld.long 0x00 3. " FMO ,F-bit Mask Override" "No override,Override" textline " " bitfld.long 0x00 2. " PTW ,Protected Table Walk" "Disabled,Enabled" bitfld.long 0x00 1. " SWIO ,Set/Way Invalidation Override" "No override,Override" bitfld.long 0x00 0. " VM ,Second Stage of Translation Enable" "Disabled,Enabled" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hyp Debug Control Register" bitfld.long 0x00 11. " TDRA ,Trap Debug ROM Access" "No effect,Valid" bitfld.long 0x00 10. " TDOSA ,Trap Debug OS-related register Access" "No effect,Valid" bitfld.long 0x00 9. " TDA ,Trap Debug Access" "No effect,Valid" textline " " bitfld.long 0x00 8. " TDE ,Trap Debug Exceptions" "No effect,Valid" bitfld.long 0x00 7. " HPME ,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.long 0x00 6. " TPM ,Trap Performance Monitors accesses" "No effect,Valid" textline " " bitfld.long 0x00 5. " TPMCR ,Trap Performance Monitor Control Register accesses" "No effect,Valid" bitfld.long 0x00 0.--4. " HPMN ,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hyp Coprocessor Trap Register" bitfld.long 0x0 31. " TCPAC ,Trap Coprocessor Access Control" "Not trapped,Trapped" bitfld.long 0x0 15. " TASE ,Trap Advanced SIMD extensions" "Not trapped,Trapped" bitfld.long 0x0 11. " TCP11 ,Trap coprocessor 11" "Not trapped,Trapped" textline " " bitfld.long 0x0 10. " TCP10 ,Trap coprocessor 10" "Not trapped,Trapped" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hyp Syndrome Register" bitfld.long 0x00 26.--31. " EC ,Exception class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hyp System Trap Register" bitfld.long 0x00 17. " TJDBX ,Trap Jazelle-DBX" "Disabled,Enabled" bitfld.long 0x00 16. " TTEE ,Trap ThumbEE" "Disabled,Enabled" bitfld.long 0x00 15. " T15 ,Trap to Hyp mode Non-secure priv 15" "Not trapped,Trapped" textline " " bitfld.long 0x00 13. " T13 ,Trap to Hyp mode Non-secure priv 13" "Not trapped,Trapped" bitfld.long 0x00 12. " T12 ,Trap to Hyp mode Non-secure priv 12" "Not trapped,Trapped" bitfld.long 0x00 11. " T11 ,Trap to Hyp mode Non-secure priv 11" "Not trapped,Trapped" textline " " bitfld.long 0x00 10. " T10 ,Trap to Hyp mode Non-secure priv 10" "Not trapped,Trapped" bitfld.long 0x00 9. " T9 ,Trap to Hyp mode Non-secure priv 9" "Not trapped,Trapped" bitfld.long 0x00 8. " T8 ,Trap to Hyp mode Non-secure priv 8" "Not trapped,Trapped" textline " " bitfld.long 0x00 7. " T7 ,Trap to Hyp mode Non-secure priv 7" "Not trapped,Trapped" bitfld.long 0x00 6. " T6 ,Trap to Hyp mode Non-secure priv 6" "Not trapped,Trapped" bitfld.long 0x00 5. " T5 ,Trap to Hyp mode Non-secure priv 5" "Not trapped,Trapped" textline " " bitfld.long 0x00 3. " T3 ,Trap to Hyp mode Non-secure priv 3" "Not trapped,Trapped" bitfld.long 0x00 2. " T2 ,Trap to Hyp mode Non-secure priv 2" "Not trapped,Trapped" bitfld.long 0x00 1. " T1 ,Trap to Hyp mode Non-secure priv 1" "Not trapped,Trapped" textline " " bitfld.long 0x00 0. " T0 ,Trap to Hyp mode Non-secure priv 0" "Not trapped,Trapped" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hyp Translation Table Base Register" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hyp Translation Control Register" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using HTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. " VMID ,VMID for the translation table" hexmask.quad 0x00 0.--39. 1. " BADDR ,Translation table base address" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. " SH0 ,Shareability attributes for the memory associated with the translation table walks using VTTBR" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. " ORGN0 ,Outer Cacheability attributes for the memory associated with the translation table walks using VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 8.--9. " IRGN0 ,Inner Cacheability attributes for the memory associated with the translation table walks VTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" textline " " bitfld.long 0x00 6.--7. " SL0 ,Starting Level for VTCR addressed region" "Second level,First level,Reserved,Reserved" bitfld.long 0x00 4. " S ,Sign extension bit" "0,1" bitfld.long 0x00 0.--3. " T0SZ ,The Size offset(four-bit signed integer) of the VTCR addressed region" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hyp Auxiliary Data Fault Status Syndrome Register" bitfld.long 0x00 31. " VALID ,L1 or L2 ECC double bit error indicator" "No error,Error" hexmask.long.byte 0x00 24.--30. 1. " RAMID ,RAM identifier" bitfld.long 0x00 23. " L2E ,L2 Error" "No error,Error" textline " " bitfld.long 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" endif group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hyp Data Fault Address Register" group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hyp Syndrome Register" bitfld.long 0x00 26.--31. " EC ,Exception class" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC,Trapped Jazelle instruction,Trapped BXJ,Reserved,Trapped MRRC,Reserved,Reserved,Reserved,Reserved,SVC,HVC,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,Reserved,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..." textline " " bitfld.long 0x00 25. " IL ,Instruction length" "16-bit,32-bit" hexmask.long 0x00 0.--24. 1. " ISS ,Instruction specific syndrome" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hyp Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hyp IPA Fault Address Register" hexmask.long 0x00 4.--31. 1. " FIPA ,Faulting IPA bits" textline " " hgroup.long c15:0x407++0x00 hide.long 0x00 "NOP,No Operation Register" in wgroup.long c15:0x17++0x00 line.long 0x00 "ICIALLUIS,Invalidate All Instruction Caches To PoU Inner Shareable Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x617++0x00 line.long 0x00 "BPIALLIS,Invalidate Entire Branch Predictor Array Inner Shareable Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x57++0x00 line.long 0x00 "ICIALLU,Invalidate Entire Instruction Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x157++0x00 line.long 0x00 "ICIMVAU,Invalidate Instruction Cache Line by VA to Point-of-Unification Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x457++0x00 line.long 0x00 "CP15ISB,Instruction Synchronization Barrier Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x657++0x00 line.long 0x00 "BPIALL,Invalidate Entire Branch Predictor Array (NOP) Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x757++0x00 line.long 0x00 "BPIMVA,Invalidate MVA From Branch Predictors Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.word 0x00 5.--15. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x167++0x00 line.long 0x00 "DCIMVAC,Invalidate Data Cache Line by VA to PoC Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x267++0x00 line.long 0x00 "DCISW,Invalidate Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x0087++0x00 line.long 0x00 "ATS1CPR,Stage 1 current state PL1 read" wgroup.long c15:0x0187++0x00 line.long 0x00 "ATS1CPW,Stage 1 current state PL1 write" wgroup.long c15:0x0287++0x00 line.long 0x00 "ATS1CUR,Stage 1 current state unprivileged (PL0) read" wgroup.long c15:0x0387++0x00 line.long 0x00 "ATS1CUW,Stage 1 current state unprivileged (PL0) write" wgroup.long c15:0x0487++0x00 line.long 0x00 "ATS12NSOPR,Stages 1 and 2 Non-secure PL1 read" wgroup.long c15:0x0587++0x00 line.long 0x00 "ATS12NSOPW,Stages 1 and 2 Non-secure PL1 write" wgroup.long c15:0x0687++0x00 line.long 0x00 "ATS12NSOUR,Stages 1 and 2 Non-secure unprivileged (PL0) read" wgroup.long c15:0x0787++0x00 line.long 0x00 "ATS12NSOUW,Stages 1 and 2 Non-secure unprivileged (PL0) write" wgroup.long c15:0x1a7++0x00 line.long 0x00 "DCCMVAC,Clean Data Cache Line to PoC by VA Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x2a7++0x00 line.long 0x00 "DCCSW,Clean Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" bitfld.long 0x00 1.--3. " LEVEL ,Cache level" "0,1,2,3,4,5,6,7" wgroup.long c15:0x4a7++0x00 line.long 0x00 "CP15DSB,Data Synchronization Barrier Register" hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean" wgroup.long c15:0x5a7++0x00 line.long 0x00 "CP15DMB,Data Memory Barrier Register" hexmask.long 0x00 5.--31. 0x20 " ADDRESS ,Address to invalidate or clean" wgroup.long c15:0x1b7++0x00 line.long 0x00 "DCCMVAU,Clean Data Or Unified Cache Line By VA To PoU Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x1e7++0x00 line.long 0x00 "DCCIMVAC,Clean and Invalidate Data Cache Line by VA to PoC Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x2e7++0x00 line.long 0x00 "DCCISW,Clean and Invalidate Data Cache Line by Set/Way Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" wgroup.long c15:0x4087++0x00 line.long 0x00 "ATS1HR,Address Translate Stage 1 Hyp mode Read" wgroup.long c15:0x4187++0x00 line.long 0x00 "ATS1HW,Address Translate Stage 1 Hyp mode Write" wgroup.long c15:0x0038++0x00 line.long 0x00 "TLBIALLIS,Invalidate entire TLB Inner Shareable" wgroup.long c15:0x0138++0x00 line.long 0x00 "TLBIMVAIS,Invalidate unified TLB entry by MVA Inner Shareable" wgroup.long c15:0x0238++0x00 line.long 0x00 "TLBIASIDIS,Invalidate unified TLB byASID match Inner Shareable" wgroup.long c15:0x0338++0x00 line.long 0x00 "TLBIMVAAIS,Invalidate unified TLB by MVA all ASID Inner Shareable" wgroup.long c15:0x0058++0x00 line.long 0x00 "ITLBIALL,Invalidate instruction TLB" wgroup.long c15:0x0158++0x00 line.long 0x00 "ITLBIMVA,Invalidate instruction TLB entry by MVA" wgroup.long c15:0x0258++0x00 line.long 0x00 "ITLBIASID,Invalidate instruction TLB by ASID match" wgroup.long c15:0x0068++0x00 line.long 0x00 "DTLBIALL,Invalidate data TLB" wgroup.long c15:0x0168++0x00 line.long 0x00 "DTLBIMVA,Invalidate data TLB entry by MVA" wgroup.long c15:0x0268++0x00 line.long 0x00 "DTLBIASID,Invalidate data TLB by ASID match" wgroup.long c15:0x0078++0x00 line.long 0x00 "TLBIALL,Invalidate unified TLB" wgroup.long c15:0x0178++0x00 line.long 0x00 "TLBIMVA,Invalidate unified TLB entry by MVA" wgroup.long c15:0x0278++0x00 line.long 0x00 "TLBIASID,Invalidate unified TLB byASID match" wgroup.long c15:0x0378++0x00 line.long 0x00 "TLBIMVAA,Invalidate unified TLB by MVA all ASID" wgroup.long c15:0x4038++0x00 line.long 0x00 "TLBIALLHIS,Invalidate entire Hyp unified TLB Inner Shareable" wgroup.long c15:0x4138++0x00 line.long 0x00 "TLBIMVAHIS,Invalidate Hyp unified TLB entry by MVA Inner Shareable" wgroup.long c15:0x4438++0x00 line.long 0x00 "TLBIALLNSNHIS,Invalidate entire Non-secure Non-Hyp unified TLB Inner Shareable" wgroup.long c15:0x4078++0x00 line.long 0x00 "TLBIALLH,Invalidate entire Hyp unified TLB" wgroup.long c15:0x4178++0x00 line.long 0x00 "TLBIMVAH,Invalidate Hyp unified TLB entry by MVA" wgroup.long c15:0x4478++0x00 line.long 0x00 "TLBIALLNSNH,Invalidate entire Non-secure Non-Hyp unified TLB" group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0" hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Attribute 3" hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Attribute 2" hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Attribute 1" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Attribute 0" group.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1" hexmask.long.byte 0x00 24.--31. 1. " ATTR7 ,Attribute 7" hexmask.long.byte 0x00 16.--23. 1. " ATTR6 ,Attribute 6" hexmask.long.byte 0x00 8.--15. 1. " ATTR5 ,Attribute 5" textline " " hexmask.long.byte 0x00 0.--7. 1. " ATTR4 ,Attribute 4" else hgroup.long c15:0x403A++0x00 hide.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0" hgroup.long c15:0x413A++0x00 hide.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1" endif group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hyp Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 " HVBADDR ,Hyp Vector Base Address" tree.end width 12. tree "Cache Control and Configuration" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..." bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,?..." textline " " bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,?..." bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,?..." bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,?..." bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,?..." textline " " bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x1100++0x0 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOUU ,Level of Unification Uniprocessor" "Reserved,Level 2,?..." bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 21.--23. " LOUIS ,Level of Unification Inner Shareable" "Reserved,Level 2,?..." textline " " bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "Not implemented,Reserved,Reserved,Reserved,Unified,?..." bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. " SETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,Reserved,16 words,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x1000++0x0 line.long 0x0 "CCSIDR,Current Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported" textline " " bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of Sets" hexmask.long.word 0x00 3.--12. 1. " ASSOC ,Associativity" textline " " bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "Reserved,8 words,16 words,?..." endif group.long c15:0x2000++0x0 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level of required cache" "Level 1,Level 2,?..." bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/Unified,Instruction" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") wgroup.long c15:0x10EF++0x00 line.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register" bitfld.long 0x00 1.--2. " LEVEL ,Cache level" "L1,L2,Reserved,Reserved" else hgroup.long c15:0x10EF++0x00 hide.long 0x00 "DCCIALL,Data Cache Clean and Invalidate All Register" endif tree "Level 1 memory system" width 10. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x000F++0x00 line.long 0x00 "IL1DATA0,Instruction L1 Data 0 Register" group.long c15:0x010F++0x00 line.long 0x00 "IL1DATA1,Instruction L1 Data 1 Register" group.long c15:0x020F++0x00 line.long 0x00 "IL1DATA2,Instruction L1 Data 2 Register" group.long c15:0x001F++0x00 line.long 0x00 "DL1DATA0,Data L1 Data 0 Register" group.long c15:0x011F++0x00 line.long 0x00 "DL1DATA1,Data L1 Data 1 Register" group.long c15:0x021F++0x00 line.long 0x00 "DL1DATA2,Data L1 Data 2 Register" group.long c15:0x031F++0x00 line.long 0x00 "DL1DATA3,Data L1 Data 3 Register" wgroup.long c15:0x004F++0x00 line.long 0x00 "RAMINDEX,RAM Index Register" hexmask.long.byte 0x00 24.--31. 1. " RAMID ,RAM identifier" bitfld.long 0x00 18.--21. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--17. 1. " IND ,Index" textline " " group.quad c15:0x100F0++0x01 line.quad 0x00 "CPUMERRSR,CPU Memory Error Syndrome Register" bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count" hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count" bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid" textline " " hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier" bitfld.quad 0x00 18.--22. " B/W ,Bank/Way" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c15:0x300F++0x0 line.long 0x00 "CDBGDR0,Data Register 0" rgroup.long c15:0x310F++0x0 line.long 0x00 "CDBGDR1,Data Register 1" rgroup.long c15:0x320F++0x0 line.long 0x00 "CDBGDR2,Data Register 2" wgroup.long c15:0x302F++0x0 line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x312F++0x0 line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register" bitfld.long 0x00 31. " CW ,Cache Way" "Low,High" hexmask.long 0x00 5.--30. 1. " SI ,Set index" bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x304F++0x0 line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.tbyte 0x00 6.--29. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CWDO ,Cache word data offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 31. " CW ,Cache Way" "Low,High" hexmask.long 0x00 5.--30. 1. " SI ,Set index" bitfld.long 0x00 2.--4. " CDEO ,Cache data element offset" "0,1,2,3,4,5,6,7" wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 31. " TLB_WAY ,TLB Way" "Low,High" hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c15:0x300F++0x0 line.long 0x00 "CDBGDR0,Data Register 0" bitfld.long 0x00 31. " PMOESID ,Partial MOESI state / Dirty" "Low,High" bitfld.long 0x00 30. " POMA ,Partial Outer memory attribute" "Low,High" bitfld.long 0x00 29. " PMOESIE ,Partial MOESI state / Exclusive" "Low,High" textline " " bitfld.long 0x00 28. " PMOESIV ,Partial MOESI state / Valid" "Low,High" bitfld.long 0x00 27. " NS ,Non-Secure state" "Low,High" hexmask.long 0x00 0.--26. 1. " TA ,Tag Address" rgroup.long c15:0x310F++0x0 line.long 0x00 "CDBGDR1,Data Register 1" bitfld.long 0x00 0. " PMOESID ,Partial MOESI state / Globally shared" "Low,High" rgroup.long c15:0x320F++0x0 line.long 0x00 "CDBGDR2,Data Register 2" wgroup.long c15:0x302F++0x0 line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" wgroup.long c15:0x312F++0x0 line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long 0x00 6.--30. 1. " SI ,Set index" wgroup.long c15:0x304F++0x0 line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" if (((d.l(c15:0x1000))&0xFFFE000)==0x1DE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--12. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x1) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.byte 0x00 6.--13. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FE000&&((d.l(c15:0x2000))&0x3)==0x2) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--15. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--16. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x7FE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--17. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0xFFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--18. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x1FFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--19. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" elif (((d.l(c15:0x1000))&0xFFFE000)==0x3FFE000) wgroup.long c15:0x314F++0x0 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" bitfld.long 0x00 30.--31. " CW ,Cache Way" "0,1,2,3" hexmask.long.word 0x00 6.--20. 1. " SI ,Set index" bitfld.long 0x00 3.--5. " CDDO ,Cache doubleword data offset" "0,1,2,3,4,5,6,7" else hgroup.long c15:0x314F++0x0 hide.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" endif if (((d.l(c15:0x324F))&0x100)==0x100) wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1" else wgroup.long c15:0x324F++0x0 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" bitfld.long 0x00 30.--31. " TLB_WAY ,TLB Way" "0,1,2,3" bitfld.long 0x00 8. " TYPE ,Type" "RAM0,RAM1" hexmask.long.byte 0x00 0.--7. 1. " TLB_IND ,TLB index" endif endif tree.end tree "Level 2 memory system" width 11. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes" bitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4" bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present" textline " " bitfld.long 0x00 21. " ECCPE ,ECC and parity enable" "Disabled,Enabled" bitfld.long 0x00 12. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 10.--11. " DRAMSLICE ,Data RAM slice" "0,1,2,Invalid" textline " " bitfld.long 0x00 9. " TRAMS ,L2 Tag RAM setup" "0 cycle,1 cycle" bitfld.long 0x00 6.--8. " TRAML ,L2 Tag RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,5 cycles,5 cycles,5 cycles" bitfld.long 0x00 5. " DRAMS ,L2 Data RAM setup" "0 cycle,1 cycle" textline " " bitfld.long 0x00 0.--2. " DRAML ,L2 Data RAM latency" "2 cycles,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" bitfld.long 0x00 24.--25. " NCPU ,Number of CPU" "1,2,3,4" bitfld.long 0x00 23. " IE ,Interrupt Controller" "Not present,Present" bitfld.long 0x00 0. " DRAML ,L2 data RAM latency" "2 cycles,3 cycles" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1209++0x0 line.long 0x00 "L2CTLR,L2 Control Register" rbitfld.long 0x00 31. " L2RSTDISABLE ,L2 hardware reset disable pin monitor" "No,Yes" bitfld.long 0x00 27.--30. " IWINC ,Controls index incrementation method" "1.,1.,3.,7.,15.,31.,63.,127.,255.,511.,1023.,2047.,4095.,8191.,8191.,8191." rbitfld.long 0x00 24.--25. " NCPU , Number of CPU" "1,2,3,4" bitfld.long 0x00 20. " SFEN , Snoop Filter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " L2ECCD ,L2 ECC Disable" "No,Yes" bitfld.long 0x00 18. " L2CD ,L2 cache disable" "No,Yes" bitfld.long 0x00 15.--17. " TRAMSL ,Tag RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 12.--14. " TRAMRL ,Tag RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" textline " " bitfld.long 0x00 9.--11. " TRAMWL ,Tag RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 6.--8. " DRAMSL ,Data RAM setup latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 3.--5. " DRAMRL ,Data RAM read latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" bitfld.long 0x00 0.--2. " DRAMWL ,Data RAM write latency" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. " L2INTASYNCERR ,L2 internal asynchronous error" "No error,Error" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" group.long c15:0x100F++0x00 line.long 0x00 "L2ACTLR,L2 Auxiliary Control Register" bitfld.long 0x00 28. " FL2TBCEA ,Forces L2 tag bank clock enable active" "Not forced,Forced" bitfld.long 0x00 27. " FL2LCEA ,Forces L2 logic clock enable active" "Not forced,Forced" bitfld.long 0x00 26. " EL2GTRCG ,Enables L2 GIC and Timer regional clock gates" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " ERTSI ,Enables replay threshold single issue" "Disabled,Enabled" bitfld.long 0x00 15. " ECWRM ,Enable CPU WFI retention mode" "Disabled,Enabled" bitfld.long 0x00 14. " EUCE ,Enables UniqueClean evictions with data" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DSCDT ,Disables SharedClean data transfers" "No,Yes" bitfld.long 0x00 12. " DWCWBE ,Disable multiple outstanding WriteClean/WriteBack/Evicts using the same AWID" "No,Yes" bitfld.long 0x00 11. " DDSB ,Disables DSB with no DVM synchronization" "No,Yes" textline " " bitfld.long 0x00 10. " DNSDAR ,Disables non-secure debug array read" "No,Yes" bitfld.long 0x00 9. " EPF ,Enable use of Prefetch bit in L2 cache replacement algorithm" "Disabled,Enabled" bitfld.long 0x00 8. " DDVMCMOMB ,Disables Distributed Virtual Memory (DVM) transactions and cache maintenance operation message broadcast" "No,Yes" textline " " bitfld.long 0x00 7. " EHDT ,Enables hazard detect timeout" "Disabled,Enabled" bitfld.long 0x00 6. " DSTFM ,Disables shared transactions from master" "No,Yes" bitfld.long 0x00 4. " DWUAWLUTFM ,Disables WriteUnique and WriteLineUnique transactions from master" "No,Yes" textline " " bitfld.long 0x00 3. " DCEPTE ,Disables clean/evict push to external" "No,Yes" bitfld.long 0x00 2. " LTORPTB ,Limit to one request per tag bank" "Disabled,Enabled" bitfld.long 0x00 1. " EARTT ,Enable arbitration replay threshold timeout" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DPF ,Disable prefetch forwarding" "No,Yes" group.long c15:0x130F++0x00 line.long 0x00 "L2PFR,L2 Prefetch Control Register" bitfld.long 0x00 12. " DDTOLSPR ,Disable dynamic throttling of load/store prefetch requests" "No,Yes" bitfld.long 0x00 11. " EPRFRUT ,Enable prefetch request from ReadUnique transactions" "Disabled,Enabled" bitfld.long 0x00 10. " DTWDAP ,Disable table walk descriptor access prefetch" "No,Yes" textline " " bitfld.long 0x00 7.--8. " L2IFPD ,L2 instruction fetch prefetch distance" "0 lines,1 line,2 lines,3 lines" bitfld.long 0x00 4.--5. " L2LSDPD ,L2 load/store data prefetch distance" "0 lines,2 lines,4 lines,8 lines" textline " " group.quad c15:0x110F0++0x01 line.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" bitfld.quad 0x00 63. " FATAL ,Fatal bit" "0,1" hexmask.quad.byte 0x00 40.--47. 1. " OEC ,Other error count" hexmask.quad.byte 0x00 32.--39. 1. " REC ,Repeat error count" bitfld.quad 0x00 31. " VALID ,Valid bit" "Not valid,Valid" textline " " hexmask.quad.byte 0x00 24.--30. 1. " RAMID ,RAM Identifier" bitfld.quad 0x00 18.--21. " C/W ,CPUID/Way" "CPU0 tag way 0,CPU0 tag way 1,CPU1 tag way 0,CPU1 tag way 1,CPU2 tag way 0,CPU2 tag way 1,CPU3 tag way 0,CPU3 tag way 1,?..." hexmask.quad.tbyte 0x00 0.--17. 1. " IND ,Index" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" hgroup.quad c15:0x110F0++0x01 hide.quad 0x00 "L2MERRSR,L2 Memory Error Syndrome Register" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c15:0x1309++0x0 line.long 0x00 "L2ECTLR,L2 Extended Control Register" bitfld.long 0x00 30. " ECCUNERR ,ECC uncorrectable error " "No error,Error" bitfld.long 0x00 29. " AXIASYNCERR ,AXI asynchronous error" "No error,Error" bitfld.long 0x00 0. " L2DRC ,Disable L2 retention" "No,Yes" rgroup.long c15:0x1609++0x00 line.long 0x00 "L2MRERRSR,L2 Memory Error Syndrome Register" bitfld.long 0x00 31. " FATAL ,Fatal bit" "0,1" bitfld.long 0x00 25.--30. " OEC ,Other error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 19.--24. " REC ,Repeat error count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 6.--18. 1. " ERRLIND ,Index Error Location" textline " " bitfld.long 0x00 2.--5. " ERRLWAY ,Way Error Location" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " RAMID ,RAM Identifier" "TAG,DATA" bitfld.long 0x00 0. " VALID ,Valid bit" "Not valid,Valid" endif tree.end tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x0 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. " X ,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" textline " " bitfld.long 0x00 2. " C ,Clock Counter Reset" "No reset,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. " E ,All Counters Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMNCNTENSET,Count Enable Set Register " bitfld.long 0x00 5. " P5 ,Event Counter 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event Counter 4 enable bit" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,Event Counter 3 enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,Event Counter 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event Counter 1 enable bit" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event Counter 0 enable bit" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x00 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 5. " P5 ,Event Counter 5 clear bit" "Disabled,Enabled" eventfld.long 0x00 4. " P4 ,Event Counter 4 clear bit" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Event Counter 3 clear bit" "Disabled,Enabled" textline " " eventfld.long 0x00 2. " P2 ,Event Counter 2 clear bit" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Event Counter 1 clear bit" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Event Counter 0 clear bit" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x00 "PMOVSR,Performance Monitor Overflow Status Register" eventfld.long 0x00 5. " P5 ,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. " P4 ,PMN4 overflow" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflow" "No overflow,Overflow" textline " " eventfld.long 0x00 2. " P2 ,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflow" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflow" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x00 "PMSWINC,Performance Monitor Software Increment" bitfld.long 0x00 5. " P5 ,Increment PMN5" "No action,Increment" bitfld.long 0x00 4. " P4 ,Increment PMN4" "No action,Increment" bitfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" textline " " bitfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" bitfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" bitfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Monitor Select Register" bitfld.long 0x00 0.--4. " SEL ,Current event counter select" "0,1,2,3,4,5,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Performance Monitor Cycle Count Register" group.long c15:0x1d9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitor Event Type Register" bitfld.long 0x00 31. " P ,Execution at PL1 events counting disable" "No,Yes" bitfld.long 0x00 30. " U ,Execution at PL0 events counting disable" "No,Yes" bitfld.long 0x00 29. " NSK ,Execution in Non-secure state at PL1 events counting disable" "No,Yes" bitfld.long 0x00 28. " NSU ,Execution in Non-secure state at PL0 events counting disable" "No,Yes" textline " " bitfld.long 0x00 27. " NSH ,Execution in Non-secure state at PL2 events counting enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--7. 1. " EVTCOUNT ,Event to count" group.long c15:0x2d9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitor Event Count Register" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,Performance Monitor User Enable Register" bitfld.long 0x00 0. " EN ,User mode access enable" "Disabled,Enabled" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Performance Monitor Interrupt Enable Set" bitfld.long 0x00 5. " P5 ,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. " P3 ,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " P2 ,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitor Interrupt Enable Clear" eventfld.long 0x00 5. " P5 ,Overflow Interrupt Clear" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " P4 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Overflow Interrupt Clear" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " P1 ,Overflow Interrupt Clear" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Overflow Interrupt Clear" "Disabled,Enabled" group.long c15:0x3e9++0x00 line.long 0x00 "PMOVSSET,Performance Monitor Overflow Flag Status Set Register" bitfld.long 0x00 31. " C ,PMCCNTR overflow bit" "Not overflowed,Overflowed" bitfld.long 0x00 30. " P30 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 29. " P29 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 28. " P28 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " P27 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 26. " P26 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 25. " P25 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 24. " P24 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " P23 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 22. " P22 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 21. " P21 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 20. " P20 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " P19 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 18. " P18 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 17. " P17 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 16. " P16 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " P15 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 14. " P14 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 13. " P13 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 12. " P12 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " P11 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 10. " P10 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 9. " P9 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 8. " P8 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " P7 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 6. " P6 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 5. " P5 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 4. " P4 ,Event Counter Overflow" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " P3 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 2. " P2 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 1. " P1 ,Event Counter Overflow" "Disabled,Enabled" bitfld.long 0x00 0. " P0 ,Event Counter Overflow" "Disabled,Enabled" tree.end width 12. tree "System Timer Register" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. " PL0PTEN ,Controls whether the physical timer registers are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 8. " PL0VTEN ,Controls whether the virtual timer registers are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. " PL0VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" textline " " bitfld.long 0x00 0. " PL0PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" textline "" group.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter PL1 Physical Compare Value Register" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter PL1 Physical Timer Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter PL1 Physical Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" textline "" group.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter PL1 Virtual Compare Value Register" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter PL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter PL1 Virtual Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" textline "" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. " EVNTI ,Selects which bit of CNTPCTis the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " EVNTDIR ,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" bitfld.long 0x00 2. " EVNTEN ,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PL1VCTEN ,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" bitfld.long 0x00 0. " PL1PCTEN ,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from PL0 modes" "Not accessible,Accessible" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure PL2 Physical Compare Value Register" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure PL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure PL2 Physical Timer Control Register" bitfld.long 0x00 2. " ISTATUS ,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. " IMASK ,Timer interrupt mask bit" "Not masked,Masked" bitfld.long 0x00 0. " ENABLE ,Enables the timer" "Disabled,Enabled" tree.end width 11. width 15. tree "Debug Registers" rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Supported,Not supported" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Not implemented,Implemented" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Not implemented,Implemented" hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" textline " " hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") wgroup.long c14:6.++0x0 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" wgroup.long c14:5.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c14:195.))&0x1)==0x1) group.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." rbitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" rbitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " rbitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" else rgroup.long c14:1.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (Internal View)" rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" rbitfld.long 0x00 18. " NS ,Non-secure state status" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "No exception,Exception" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" endif wgroup.long c14:5.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit/Receive Register (Internal View)" endif group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. " NSF ,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. " NSI ,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. " NSD ,Data Abort vector catch in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " NSP ,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. " NSS ,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. " NSU ,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " NSHF ,FIQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 22. " NSHI ,IRQ interrupt exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 21. " NSHE ,Hyp Trap or Hyp mode entry exception vector catch enable in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " NSHD ,Data Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 19. " NSHP ,Prefetch Abort, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 18. " NSHC ,Hypervisor Call. from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " NSHU ,Undefined Instruction, from Hyp mode exception vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 15. " MF ,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. " MI ,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " MD ,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 11. " MP ,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. " MS ,SMC vector catch enable in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SF ,FIQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 6. " SI ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " SD ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SP ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SS ,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. " SU ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " R ,Reset vector catch enable" "Disabled,Enabled" group.long c14:9.++0x0 line.long 0x00 "DBGECR,Debug Event Catch Register" bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled" group.long c14:32.++0x0 line.long 0x00 "DBGDTRRX,Debug Receive Register (External View)" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Debug Instruction Transfer Register" rgroup.long c14:33.++0x0 line.long 0x00 "DBGPCSR,Program Counter Sampling Register" hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value" bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,Reserved,Thumb" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault Status" "Not caused,Caused" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" bitfld.long 0x00 25. " PIPEADC ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " DBGNOPWRDWN ,Debug no power-down" "Low,High" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" elif (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c14:195.))&0x1)==0x1) group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " bitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "Low,High" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" else group.long c14:34.++0x0 line.long 0x00 "DBGDSCR,Debug Status and Control Register (External View)" rbitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" rbitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" rbitfld.long 0x00 27. " RXFULL_L ,Latched RXFULL bit" "Not latched,Latched" textline " " rbitfld.long 0x00 26. " TXFULL_L ,Latched TXFULL bit" "Not latched,Latched" rbitfld.long 0x00 25. " PIPEADV ,Sticky Pipeline Advance bit" "Not idle,Idle" rbitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not complete,Complete" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC acces mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Discarded" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " rbitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "Enabled,Disabled" rbitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "Enabled,Disabled" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "Enabled,Disabled" textline " " rbitfld.long 0x00 11. " INTDIS ,Interrupt disable" "Enabled,Disabled" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" bitfld.long 0x00 9. " FS ,Fault status" "Low,High" textline " " rbitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" rbitfld.long 0x00 7. " ADABORT_L ,Sticky Asynchronous Abort" "Not occurred,Occurred" rbitfld.long 0x00 6. " SDABORT_L ,Sticky Synchronous Data Abort" "Not occurred,Occurred" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Asynchronous Watchpoint,BKPT Instruction,External Debug Request,Vector Catch,Reserved,Reserved,OS Unlock Catch,Reserved,Synchronous Watchpoint,?..." rbitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" rbitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" endif endif wgroup.long c14:35.++0x0 line.long 0x00 "DBGDTRTX,Debug Transmit Register (External View)" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RRQ ,Restart request" "No effect,Restart" bitfld.long 0x00 0. " HRQ ,Halt request" "No effect,Halt" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CBRRQ ,CBRRQ" "Low,High" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" textline " " bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") group.long c14:37.++0x0 line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register" bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset" bitfld.long 0x00 2. " DECRR ,Debug extend core reset request" "No request,Request" bitfld.long 0x00 1. " DPDO ,Debug power-down override" "Disabled,Enabled" bitfld.long 0x00 0. " DCSC ,Debug clock stop control" "Stopped,Running" textline " " elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:37.++0x0 line.long 0x00 "DBGEACR,Debug External Auxiliary Control Register" bitfld.long 0x00 3. " CDRS ,Core debug reset status" "No reset,Reset" endif rgroup.long c14:40.++0x0 line.long 0x00 "DBGPCSR,Program Counter Sampling Register" hexmask.long 0x00 2.--31. 1. " PCS ,Program Counter sample value" bitfld.long 0x00 0.--1. " T ,Meaning of PC sample value" "ARM,Thumb,?..." rgroup.long c14:41.++0x0 line.long 0x00 "DBGCIDSR,DBGCIDSR" if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c14:42.++0x0 line.long 0x00 "DBGVIDSR,Virtualization ID Sampling Register" bitfld.long 0x00 31. " NS ,NS state sample" "Secure,Non-secure" bitfld.long 0x00 30. " H ,Hyp mode sample" "Not associated,Associated" hexmask.long.byte 0x00 0.--7. 1. " VMID ,VMID sample" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:42.++0x0 line.long 0x00 "DBGVIDSR,DBGVIDSR" endif width 15. if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") textline " " wgroup.long c14:958.++0x0 line.long 0x00 "DBGITOCTRL,Debug Integration Output Control Register" bitfld.long 0x00 3. " NPMUIRQ ,Drives the nPMUIRQ output" "Low,High" bitfld.long 0x00 2. " CTI_PMUIRQ ,Drives the internal signal equivalent to PMUIRQ that goes from the Performance Monitor Unit (PMU) to the Cross Trigger Interface (CTI)" "Low,High" bitfld.long 0x00 1. " CTI_DBGRESTARTED ,Drives the internal signal that goes from the Debug unit to the CTI to acknowledge success of a debug restart command" "Low,High" bitfld.long 0x00 0. " CTI_DBGTRIGGER ,Drives the internal signal equivalent to DBGTRIGGER that goes from the Debug unit to the CTI" "Low,High" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") textline " " wgroup.long c14:958.++0x0 line.long 0x00 "DBGITMISCOUT,Integration Miscellaneous Signals Output Register" bitfld.long 0x00 9. " DBGRESTARTED ,Value of the DBGRESTARTED output pin" "Low,High" bitfld.long 0x00 4. " PMUIRQ ,Value of PMUIRQ output pin" "Low,High" bitfld.long 0x00 0. " DBGACK ,Value of the DBGACK output pin" "Low,High" endif if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE") rgroup.long c14:959.++0x0 line.long 0x00 "DBGITISR,Debug Integration Input Status Register" bitfld.long 0x00 3. " DBGSWENABLE ,Reads the state of the DBGSWENABLE input" "Low,High" bitfld.long 0x00 2. " CTI_DBGRESTART ,CTI debug restart" "Low,High" bitfld.long 0x00 1. " CTI_EDBGRQ ,CTI debug request" "Low,High" bitfld.long 0x00 0. " EDBGRQ ,Reads the state of the EDBGRQ input" "Low,High" elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") textline " " rgroup.long c14:959.++0x0 line.long 0x00 "DBGITMISCIN,Integration Miscellaneous Signals Input Register" bitfld.long 0x00 2. " NFIQ ,Read value of nFIQ input pin" "Low,High" bitfld.long 0x00 1. " NIRQ ,Read value of nIRQ input pin" "Low,High" bitfld.long 0x00 0. " EDBGRQ ,Read value of EDBGRQ input pin" "Low,High" endif if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") if (((d.l(c15:0x202))&0x80000000)==0x80000000) rgroup.quad c14:128.++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.quad 0x0 12.--39. 0x1000 " ROMADDR ,ROM physical address" bitfld.quad 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid" rgroup.quad c14:256.++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" hexmask.quad 0x0 12.--39. 0x1000 " SELFOFFSET ,Debug bus self-address offset value" bitfld.quad 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid" else rgroup.long c14:128.++0x0 line.long 0x0 "DBGDRAR,Debug ROM Address Register" hexmask.long 0x0 12.--31. 0x1000 " ROMADDR ,ROM physical address" bitfld.long 0x0 0.--1. " VALID ,ROM table address valid" "Not valid,Reserved,Reserved,Valid" rgroup.long c14:256.++0x0 line.long 0x0 "DBGDSAR,Debug Self Address Offset Register" hexmask.long 0x0 12.--31. 0x1000 " SELFOFFSET ,Debug bus self-address offset value" bitfld.long 0x0 0.--1. " VALID ,Debug self address offset valid" "Not valid,Reserved,Reserved,Valid" endif group.long c14:195.++0x00 line.long 0x00 "DBGOSDLR,OS Double Lock Register" bitfld.long 0x00 0. " DLK ,OS Double Lock control bit" "Unlocked,Locked" else hgroup.quad c14:128.++0x1 hide.quad 0x0 "DBGDRAR,Debug ROM Address Register" hgroup.quad c14:256.++0x1 hide.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" hgroup.long c14:195.++0x00 hide.long 0x00 "DBGOSDLR,OS Double Lock Register" endif wgroup.long c14:192.++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:193.++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " OSLK ,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. " OSLM ,OS Lock Model implemented Bit" "Reserved,Reserved,W/o DBGOSSRR,?..." group.long c14:196.++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 3. " COREPURQ ,Core Power Up Request" "Low,High" bitfld.long 0x00 2. " HCWR ,Hold Core Warm Reset" "No reset,Reset" bitfld.long 0x00 1. " CWRR ,Core Warm Reset Request" "Not requested,Requested" textline " " bitfld.long 0x00 0. " CORENPDRQ ,Core No Power down Request" "Low,High" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 6. " DLK ,OS Double Lock status" "Low,High" bitfld.long 0x00 5. " OSLK ,OS Lock status" "Low,High" bitfld.long 0x00 4. " HALTED ,Halted" "Low,High" textline " " bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Low,High" bitfld.long 0x00 2. " RS ,Reset Status" "Low,High" bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Low,High" textline " " bitfld.long 0x00 0. " PU ,Power-up Status" "Low,High" tree "Processor ID registers" rgroup.long c14:(832.+0.)++0x00 line.long 0x00 "PIDR0,Processor ID register 0" rgroup.long c14:(832.+1.)++0x00 line.long 0x00 "PIDR1,Processor ID register 1" rgroup.long c14:(832.+2.)++0x00 line.long 0x00 "PIDR2,Processor ID register 2" rgroup.long c14:(832.+3.)++0x00 line.long 0x00 "PIDR3,Processor ID register 3" rgroup.long c14:(832.+4.)++0x00 line.long 0x00 "PIDR4,Processor ID register 4" rgroup.long c14:(832.+5.)++0x00 line.long 0x00 "PIDR5,Processor ID register 5" rgroup.long c14:(832.+6.)++0x00 line.long 0x00 "PIDR6,Processor ID register 6" rgroup.long c14:(832.+7.)++0x00 line.long 0x00 "PIDR7,Processor ID register 7" rgroup.long c14:(832.+8.)++0x00 line.long 0x00 "PIDR8,Processor ID register 8" rgroup.long c14:(832.+9.)++0x00 line.long 0x00 "PIDR9,Processor ID register 9" rgroup.long c14:(832.+10.)++0x00 line.long 0x00 "PIDR10,Processor ID register 10" rgroup.long c14:(832.+11.)++0x00 line.long 0x00 "PIDR11,Processor ID register 11" rgroup.long c14:(832.+12.)++0x00 line.long 0x00 "PIDR12,Processor ID register 12" rgroup.long c14:(832.+13.)++0x00 line.long 0x00 "PIDR13,Processor ID register 13" rgroup.long c14:(832.+14.)++0x00 line.long 0x00 "PIDR14,Processor ID register 14" rgroup.long c14:(832.+15.)++0x00 line.long 0x00 "PIDR15,Processor ID register 15" rgroup.long c14:(832.+16.)++0x00 line.long 0x00 "PIDR16,Processor ID register 16" rgroup.long c14:(832.+17.)++0x00 line.long 0x00 "PIDR17,Processor ID register 17" rgroup.long c14:(832.+18.)++0x00 line.long 0x00 "PIDR18,Processor ID register 18" rgroup.long c14:(832.+19.)++0x00 line.long 0x00 "PIDR19,Processor ID register 19" rgroup.long c14:(832.+20.)++0x00 line.long 0x00 "PIDR20,Processor ID register 20" rgroup.long c14:(832.+21.)++0x00 line.long 0x00 "PIDR21,Processor ID register 21" rgroup.long c14:(832.+22.)++0x00 line.long 0x00 "PIDR22,Processor ID register 22" rgroup.long c14:(832.+23.)++0x00 line.long 0x00 "PIDR23,Processor ID register 23" rgroup.long c14:(832.+24.)++0x00 line.long 0x00 "PIDR24,Processor ID register 24" rgroup.long c14:(832.+25.)++0x00 line.long 0x00 "PIDR25,Processor ID register 25" rgroup.long c14:(832.+26.)++0x00 line.long 0x00 "PIDR26,Processor ID register 26" rgroup.long c14:(832.+27.)++0x00 line.long 0x00 "PIDR27,Processor ID register 27" rgroup.long c14:(832.+28.)++0x00 line.long 0x00 "PIDR28,Processor ID register 28" rgroup.long c14:(832.+29.)++0x00 line.long 0x00 "PIDR29,Processor ID register 29" rgroup.long c14:(832.+30.)++0x00 line.long 0x00 "PIDR30,Processor ID register 30" rgroup.long c14:(832.+31.)++0x00 line.long 0x00 "PIDR31,Processor ID register 31" rgroup.long c14:(832.+32.)++0x00 line.long 0x00 "PIDR32,Processor ID register 32" rgroup.long c14:(832.+33.)++0x00 line.long 0x00 "PIDR33,Processor ID register 33" rgroup.long c14:(832.+34.)++0x00 line.long 0x00 "PIDR34,Processor ID register 34" rgroup.long c14:(832.+35.)++0x00 line.long 0x00 "PIDR35,Processor ID register 35" rgroup.long c14:(832.+36.)++0x00 line.long 0x00 "PIDR36,Processor ID register 36" rgroup.long c14:(832.+37.)++0x00 line.long 0x00 "PIDR37,Processor ID register 37" rgroup.long c14:(832.+38.)++0x00 line.long 0x00 "PIDR38,Processor ID register 38" rgroup.long c14:(832.+39.)++0x00 line.long 0x00 "PIDR39,Processor ID register 39" rgroup.long c14:(832.+40.)++0x00 line.long 0x00 "PIDR40,Processor ID register 40" rgroup.long c14:(832.+41.)++0x00 line.long 0x00 "PIDR41,Processor ID register 41" rgroup.long c14:(832.+42.)++0x00 line.long 0x00 "PIDR42,Processor ID register 42" rgroup.long c14:(832.+43.)++0x00 line.long 0x00 "PIDR43,Processor ID register 43" rgroup.long c14:(832.+44.)++0x00 line.long 0x00 "PIDR44,Processor ID register 44" rgroup.long c14:(832.+45.)++0x00 line.long 0x00 "PIDR45,Processor ID register 45" rgroup.long c14:(832.+46.)++0x00 line.long 0x00 "PIDR46,Processor ID register 46" rgroup.long c14:(832.+47.)++0x00 line.long 0x00 "PIDR47,Processor ID register 47" rgroup.long c14:(832.+48.)++0x00 line.long 0x00 "PIDR48,Processor ID register 48" rgroup.long c14:(832.+49.)++0x00 line.long 0x00 "PIDR49,Processor ID register 49" rgroup.long c14:(832.+50.)++0x00 line.long 0x00 "PIDR50,Processor ID register 50" rgroup.long c14:(832.+51.)++0x00 line.long 0x00 "PIDR51,Processor ID register 51" rgroup.long c14:(832.+52.)++0x00 line.long 0x00 "PIDR52,Processor ID register 52" rgroup.long c14:(832.+53.)++0x00 line.long 0x00 "PIDR53,Processor ID register 53" rgroup.long c14:(832.+54.)++0x00 line.long 0x00 "PIDR54,Processor ID register 54" rgroup.long c14:(832.+55.)++0x00 line.long 0x00 "PIDR55,Processor ID register 55" rgroup.long c14:(832.+56.)++0x00 line.long 0x00 "PIDR56,Processor ID register 56" rgroup.long c14:(832.+57.)++0x00 line.long 0x00 "PIDR57,Processor ID register 57" rgroup.long c14:(832.+58.)++0x00 line.long 0x00 "PIDR58,Processor ID register 58" rgroup.long c14:(832.+59.)++0x00 line.long 0x00 "PIDR59,Processor ID register 59" rgroup.long c14:(832.+60.)++0x00 line.long 0x00 "PIDR60,Processor ID register 60" rgroup.long c14:(832.+61.)++0x00 line.long 0x00 "PIDR61,Processor ID register 61" rgroup.long c14:(832.+62.)++0x00 line.long 0x00 "PIDR62,Processor ID register 62" rgroup.long c14:(832.+63.)++0x00 line.long 0x00 "PIDR63,Processor ID register 63" tree.end tree "Coresight Management Registers" group.long c14:960.++0x0 line.long 0x00 "DBGITCTRL,Debug Integration Mode Control Register" bitfld.long 0x00 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group.long c14:1000.++0x0 line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Set" "Not set,Set" textline " " bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Set" "Not set,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Set" "Not set,Set" group.long c14:1001.++0x0 line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. " CT5 ,Claim Tag 5 Clear" "Not cleared,Cleared" textline " " bitfld.long 0x0 4. " CT4 ,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. " CT3 ,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2 Clear" "Not cleared,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0 Clear" "Not cleared,Cleared" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit" bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked" bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented" textline " " rgroup.long c14:1006.++0x0 line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register" bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented" bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled" bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented" textline " " bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled" bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented" bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled" textline " " if (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") rgroup.long c14:1009.++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Depends on instr set state,No offset,?..." elif (corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") rgroup.long c14:1009.++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" bitfld.long 0x00 0.--3. " PCSROFFSET ,Defines the offset applied to DBGPCSR samples" "Reserved,No offset,?..." endif textline " " rgroup.long c14:1010.++0x0 line.long 0x0 "DBGDEVID0,Debug Device ID Register 0" bitfld.long 0x0 24.--27. " AR ,Debug External Auxiliary Control Register support status" "Reserved,Supported,?..." bitfld.long 0x0 20.--23. " DL ,Support for Debug OS Double Lock Register" "Reserved,Supported,?..." bitfld.long 0x0 16.--19. " VE ,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..." textline " " bitfld.long 0x0 12.--15. " VC ,Form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x0 8.--11. " BPAM ,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.long 0x0 4.--7. " WPAM ,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." textline " " bitfld.long 0x0 0.--3. " PCS ,Level of support for Program Counter sampling using debug registers 40 and 41" "Reserved,Reserved,Reserved,Implemented,?..." textline " " rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Debug Device Type Register" bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c14:1016.++0x00 line.long 0x00 "DBGPID0,Debug Peripheral ID 0" hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]" rgroup.long c14:1017.++0x00 line.long 0x00 "DBGPID1,Debug Peripheral ID 1" hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]" hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]" rgroup.long c14:1018.++0x00 line.long 0x00 "DBGPID2,Debug Peripheral ID 2" hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision" bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled" hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]" rgroup.long c14:1019.++0x00 line.long 0x00 "DBGPID3,Debug Peripheral ID 3" hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision" hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified" rgroup.long c14:1012.++0x00 line.long 0x00 "DBGPID4,Debug Peripheral ID 4" hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code" rgroup.long c14:1020.++0x00 line.long 0x00 "DBGCID0,Debug Component ID 0" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0" rgroup.long c14:1021.++0x00 line.long 0x00 "DBGCID1,Debug Component ID 1" hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class" hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1" rgroup.long c14:1022.++0x00 line.long 0x00 "DBGCID2,Debug Component ID 2" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2" rgroup.long c14:1023.++0x00 line.long 0x00 "DBGCID3,Debug Component ID 3" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3" tree.end tree.end width 10. tree "Breakpoint Registers" if ((d.l(c14:80.+0.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+0.)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+0.)++0x0 line.long 0x00 "DBGBVR0,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+0.)++0x0 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+1.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+1.)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+1.)++0x0 line.long 0x00 "DBGBVR1,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+1.)++0x0 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+2.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+2.)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+2.)++0x0 line.long 0x00 "DBGBVR2,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+2.)++0x0 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+3.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+3.)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+3.)++0x0 line.long 0x00 "DBGBVR3,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+3.)++0x0 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+4.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+4.)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+4.)++0x0 line.long 0x00 "DBGBVR4,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+4.)++0x0 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" if ((d.l(c14:80.+5.)&0x500000)==(0x500000||0x400000||0x100000||0x0)) group.long c14:(64.+5.)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register(Address comparison)" hexmask.long 0x00 2.--31. 0x4 " INSTADDR ,Address value for comparison. Bits 2-31" else group.long c14:(64.+5.)++0x0 line.long 0x00 "DBGBVR5,Breakpoint Value Register(Context matching)" endif group.long c14:(80.+5.)++0x0 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 20.--23. " BT ,Breakpoint Type. Match - m / Mismatch - mm" "Unlinked instr addr m,Linked instr addr m,Unlinked Context ID m,Linked Context ID m,Unlinked instr addr mm,Linked instr addr mm,Reserved,Reserved,Unlinked VMID m,Linked VMID m,Unlinked VMID/Context ID m,Linked VMID/Context ID m,?..." bitfld.long 0x00 16.--19. " LBN ,Linked Breakpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " SSC ,Security state control" "Both,Non-secure,Secure,Non-secure" textline " " bitfld.long 0x00 13. " HMC ,Hyp mode control bit" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x00 1.--2. " PMC ,Privileged mode control" "User/System/Supervisor/Hyp,PL1/Hyp,User only,Any mode" bitfld.long 0x00 0. " E ,Breakpoint enable" "Disabled,Enabled" group.long c14:148.++0x0 line.long 0x00 "DBGBXVR0,Debug Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value" group.long c14:149.++0x0 line.long 0x00 "DBGBXVR1,Debug Breakpoint Extended Value Register" hexmask.long.byte 0x00 0.--7. 1. " VMID , VMID value" tree.end width 10. tree "Watchpoint Control Registers" group.long c14:(96.+0.)++0x00 line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+0.)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+0.)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+1.)++0x00 line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+1.)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+1.)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+2.)++0x00 line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+2.)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+2.)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif group.long c14:(96.+3.)++0x00 line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 " DA ,Data address" if (corename()=="CORTEXA17"||corename()=="CORTEXA17MPCORE") group.long c14:(112.+3.)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. " Mask ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Unlinked data addr match,Linked data addr match" bitfld.long 0x0 16.--19. " LBN ,Linked breakpoint number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,Non-secure" bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "0,1" bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Hyp,Privileged,Unprivileged,Any" bitfld.long 0x0 0. " E ,Watchpoint enable" "Disabled,Enabled" elif (corename()=="CORTEXA15"||corename()=="CORTEXA15MPCORE"||corename()=="CORTEXA7"||corename()=="CORTEXA7MPCORE") group.long c14:(112.+3.)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x0 24.--28. " MASK ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " WT ,Watchpoint Type" "Disabled,Enabled" bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" textline " " bitfld.long 0x0 14.--15. " SSC ,Secure state control" "Both,Non-secure,Secure,?..." bitfld.long 0x0 13. " HMC ,Hyp Mode Control" "Disabled,Enabled" bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " LSC ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged Access control" "Reserved,Match privileged accesses,Match unprivileged accesses,Match all accesses" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" endif tree.end width 0xb base AD:(data.long(c15:0x400F)&0xffff8000) tree "Interrupt Controller" width 17. group.long 0x1000++0x03 "Interrupt Controller Distributor" line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global Interrupt Enable" "Disabled,Enabled" rgroup.long 0x1004++0x03 line.long 0x00 "GICD_ICTR,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "No effect,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "up to 32/0 external,up to 64/32 external,up to 96/64 external,up to 128/96 external,up to 160/128 external,up to 192/160 external,up to 224/192 external,up to 256/224 external,?..." rgroup.long 0x1008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identfication Register" hexmask.long.byte 0x00 24.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" tree "Group Registers" group.long 0x1080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" group.long 0x1084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" group.long 0x1088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" group.long 0x108C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" group.long 0x1090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" group.long 0x1094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" group.long 0x1098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" group.long 0x109C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" tree.end tree "Set-Enable Registers" group.long 0x1100++0x03 line.long 0x0 "GICD_ISER0,Interrupt Set Enable Register 0" bitfld.long 0x00 31. " SEB31 ,Set Enable Bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " SEB30 ,Set Enable Bit 30" "Disabled,Enabled" bitfld.long 0x00 29. " SEB29 ,Set Enable Bit 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB28 ,Set Enable Bit 28" "Disabled,Enabled" bitfld.long 0x00 27. " SEB27 ,Set Enable Bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " SEB26 ,Set Enable Bit 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB25 ,Set Enable Bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " SEB24 ,Set Enable Bit 24" "Disabled,Enabled" bitfld.long 0x00 23. " SEB23 ,Set Enable Bit 23" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB22 ,Set Enable Bit 22" "Disabled,Enabled" bitfld.long 0x00 21. " SEB21 ,Set Enable Bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " SEB20 ,Set Enable Bit 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB19 ,Set Enable Bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " SEB18 ,Set Enable Bit 18" "Disabled,Enabled" bitfld.long 0x00 17. " SEB17 ,Set Enable Bit 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB16 ,Set Enable Bit 16" "Disabled,Enabled" bitfld.long 0x00 15. " SEB15 ,Set Enable Bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " SEB14 ,Set Enable Bit 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB13 ,Set Enable Bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " SEB12 ,Set Enable Bit 12" "Disabled,Enabled" bitfld.long 0x00 11. " SEB11 ,Set Enable Bit 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB10 ,Set Enable Bit 10" "Disabled,Enabled" bitfld.long 0x00 9. " SEB9 ,Set Enable Bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " SEB8 ,Set Enable Bit 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB7 ,Set Enable Bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " SEB6 ,Set Enable Bit 6" "Disabled,Enabled" bitfld.long 0x00 5. " SEB5 ,Set Enable Bit 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB4 ,Set Enable Bit 4" "Disabled,Enabled" bitfld.long 0x00 3. " SEB3 ,Set Enable Bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " SEB2 ,Set Enable Bit 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB1 ,Set Enable Bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " SEB0 ,Set Enable Bit 0" "Disabled,Enabled" group.long 0x1104++0x03 line.long 0x0 "GICD_ISER1,Interrupt Set Enable Register 1" bitfld.long 0x00 31. " SEB63 ,Set Enable Bit 63" "Disabled,Enabled" bitfld.long 0x00 30. " SEB62 ,Set Enable Bit 62" "Disabled,Enabled" bitfld.long 0x00 29. " SEB61 ,Set Enable Bit 61" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB60 ,Set Enable Bit 60" "Disabled,Enabled" bitfld.long 0x00 27. " SEB59 ,Set Enable Bit 59" "Disabled,Enabled" bitfld.long 0x00 26. " SEB58 ,Set Enable Bit 58" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB57 ,Set Enable Bit 57" "Disabled,Enabled" bitfld.long 0x00 24. " SEB56 ,Set Enable Bit 56" "Disabled,Enabled" bitfld.long 0x00 23. " SEB55 ,Set Enable Bit 55" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB54 ,Set Enable Bit 54" "Disabled,Enabled" bitfld.long 0x00 21. " SEB53 ,Set Enable Bit 53" "Disabled,Enabled" bitfld.long 0x00 20. " SEB52 ,Set Enable Bit 52" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB51 ,Set Enable Bit 51" "Disabled,Enabled" bitfld.long 0x00 18. " SEB50 ,Set Enable Bit 50" "Disabled,Enabled" bitfld.long 0x00 17. " SEB49 ,Set Enable Bit 49" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB48 ,Set Enable Bit 48" "Disabled,Enabled" bitfld.long 0x00 15. " SEB47 ,Set Enable Bit 47" "Disabled,Enabled" bitfld.long 0x00 14. " SEB46 ,Set Enable Bit 46" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB45 ,Set Enable Bit 45" "Disabled,Enabled" bitfld.long 0x00 12. " SEB44 ,Set Enable Bit 44" "Disabled,Enabled" bitfld.long 0x00 11. " SEB43 ,Set Enable Bit 43" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB42 ,Set Enable Bit 42" "Disabled,Enabled" bitfld.long 0x00 9. " SEB41 ,Set Enable Bit 41" "Disabled,Enabled" bitfld.long 0x00 8. " SEB40 ,Set Enable Bit 40" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB39 ,Set Enable Bit 39" "Disabled,Enabled" bitfld.long 0x00 6. " SEB38 ,Set Enable Bit 38" "Disabled,Enabled" bitfld.long 0x00 5. " SEB37 ,Set Enable Bit 37" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB36 ,Set Enable Bit 36" "Disabled,Enabled" bitfld.long 0x00 3. " SEB35 ,Set Enable Bit 35" "Disabled,Enabled" bitfld.long 0x00 2. " SEB34 ,Set Enable Bit 34" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB33 ,Set Enable Bit 33" "Disabled,Enabled" bitfld.long 0x00 0. " SEB32 ,Set Enable Bit 32" "Disabled,Enabled" group.long 0x1108++0x03 line.long 0x0 "GICD_ISER2,Interrupt Set Enable Register 2" bitfld.long 0x00 31. " SEB95 ,Set Enable Bit 95" "Disabled,Enabled" bitfld.long 0x00 30. " SEB94 ,Set Enable Bit 94" "Disabled,Enabled" bitfld.long 0x00 29. " SEB93 ,Set Enable Bit 93" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB92 ,Set Enable Bit 92" "Disabled,Enabled" bitfld.long 0x00 27. " SEB91 ,Set Enable Bit 91" "Disabled,Enabled" bitfld.long 0x00 26. " SEB90 ,Set Enable Bit 90" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB89 ,Set Enable Bit 89" "Disabled,Enabled" bitfld.long 0x00 24. " SEB88 ,Set Enable Bit 88" "Disabled,Enabled" bitfld.long 0x00 23. " SEB87 ,Set Enable Bit 87" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB86 ,Set Enable Bit 86" "Disabled,Enabled" bitfld.long 0x00 21. " SEB85 ,Set Enable Bit 85" "Disabled,Enabled" bitfld.long 0x00 20. " SEB84 ,Set Enable Bit 84" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB83 ,Set Enable Bit 83" "Disabled,Enabled" bitfld.long 0x00 18. " SEB82 ,Set Enable Bit 82" "Disabled,Enabled" bitfld.long 0x00 17. " SEB81 ,Set Enable Bit 81" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB80 ,Set Enable Bit 80" "Disabled,Enabled" bitfld.long 0x00 15. " SEB79 ,Set Enable Bit 79" "Disabled,Enabled" bitfld.long 0x00 14. " SEB78 ,Set Enable Bit 78" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB77 ,Set Enable Bit 77" "Disabled,Enabled" bitfld.long 0x00 12. " SEB76 ,Set Enable Bit 76" "Disabled,Enabled" bitfld.long 0x00 11. " SEB75 ,Set Enable Bit 75" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB74 ,Set Enable Bit 74" "Disabled,Enabled" bitfld.long 0x00 9. " SEB73 ,Set Enable Bit 73" "Disabled,Enabled" bitfld.long 0x00 8. " SEB72 ,Set Enable Bit 72" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB71 ,Set Enable Bit 71" "Disabled,Enabled" bitfld.long 0x00 6. " SEB70 ,Set Enable Bit 70" "Disabled,Enabled" bitfld.long 0x00 5. " SEB69 ,Set Enable Bit 69" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB68 ,Set Enable Bit 68" "Disabled,Enabled" bitfld.long 0x00 3. " SEB67 ,Set Enable Bit 67" "Disabled,Enabled" bitfld.long 0x00 2. " SEB66 ,Set Enable Bit 66" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB65 ,Set Enable Bit 65" "Disabled,Enabled" bitfld.long 0x00 0. " SEB64 ,Set Enable Bit 64" "Disabled,Enabled" group.long 0x110C++0x03 line.long 0x0 "GICD_ISER3,Interrupt Set Enable Register 3" bitfld.long 0x00 31. " SEB127 ,Set Enable Bit 127" "Disabled,Enabled" bitfld.long 0x00 30. " SEB126 ,Set Enable Bit 126" "Disabled,Enabled" bitfld.long 0x00 29. " SEB125 ,Set Enable Bit 125" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB124 ,Set Enable Bit 124" "Disabled,Enabled" bitfld.long 0x00 27. " SEB123 ,Set Enable Bit 123" "Disabled,Enabled" bitfld.long 0x00 26. " SEB122 ,Set Enable Bit 122" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB121 ,Set Enable Bit 121" "Disabled,Enabled" bitfld.long 0x00 24. " SEB120 ,Set Enable Bit 120" "Disabled,Enabled" bitfld.long 0x00 23. " SEB119 ,Set Enable Bit 119" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB118 ,Set Enable Bit 118" "Disabled,Enabled" bitfld.long 0x00 21. " SEB117 ,Set Enable Bit 117" "Disabled,Enabled" bitfld.long 0x00 20. " SEB116 ,Set Enable Bit 116" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB115 ,Set Enable Bit 115" "Disabled,Enabled" bitfld.long 0x00 18. " SEB114 ,Set Enable Bit 114" "Disabled,Enabled" bitfld.long 0x00 17. " SEB113 ,Set Enable Bit 113" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB112 ,Set Enable Bit 112" "Disabled,Enabled" bitfld.long 0x00 15. " SEB111 ,Set Enable Bit 111" "Disabled,Enabled" bitfld.long 0x00 14. " SEB110 ,Set Enable Bit 110" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB109 ,Set Enable Bit 109" "Disabled,Enabled" bitfld.long 0x00 12. " SEB108 ,Set Enable Bit 108" "Disabled,Enabled" bitfld.long 0x00 11. " SEB107 ,Set Enable Bit 107" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB106 ,Set Enable Bit 106" "Disabled,Enabled" bitfld.long 0x00 9. " SEB105 ,Set Enable Bit 105" "Disabled,Enabled" bitfld.long 0x00 8. " SEB104 ,Set Enable Bit 104" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB103 ,Set Enable Bit 103" "Disabled,Enabled" bitfld.long 0x00 6. " SEB102 ,Set Enable Bit 102" "Disabled,Enabled" bitfld.long 0x00 5. " SEB101 ,Set Enable Bit 101" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB100 ,Set Enable Bit 100" "Disabled,Enabled" bitfld.long 0x00 3. " SEB99 ,Set Enable Bit 99" "Disabled,Enabled" bitfld.long 0x00 2. " SEB98 ,Set Enable Bit 98" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB97 ,Set Enable Bit 97" "Disabled,Enabled" bitfld.long 0x00 0. " SEB96 ,Set Enable Bit 96" "Disabled,Enabled" group.long 0x1110++0x03 line.long 0x0 "GICD_ISER4,Interrupt Set Enable Register 4" bitfld.long 0x00 31. " SEB159 ,Set Enable Bit 159" "Disabled,Enabled" bitfld.long 0x00 30. " SEB158 ,Set Enable Bit 158" "Disabled,Enabled" bitfld.long 0x00 29. " SEB157 ,Set Enable Bit 157" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB156 ,Set Enable Bit 156" "Disabled,Enabled" bitfld.long 0x00 27. " SEB155 ,Set Enable Bit 155" "Disabled,Enabled" bitfld.long 0x00 26. " SEB154 ,Set Enable Bit 154" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB153 ,Set Enable Bit 153" "Disabled,Enabled" bitfld.long 0x00 24. " SEB152 ,Set Enable Bit 152" "Disabled,Enabled" bitfld.long 0x00 23. " SEB151 ,Set Enable Bit 151" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB150 ,Set Enable Bit 150" "Disabled,Enabled" bitfld.long 0x00 21. " SEB149 ,Set Enable Bit 149" "Disabled,Enabled" bitfld.long 0x00 20. " SEB148 ,Set Enable Bit 148" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB147 ,Set Enable Bit 147" "Disabled,Enabled" bitfld.long 0x00 18. " SEB146 ,Set Enable Bit 146" "Disabled,Enabled" bitfld.long 0x00 17. " SEB145 ,Set Enable Bit 145" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB144 ,Set Enable Bit 144" "Disabled,Enabled" bitfld.long 0x00 15. " SEB143 ,Set Enable Bit 143" "Disabled,Enabled" bitfld.long 0x00 14. " SEB142 ,Set Enable Bit 142" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB141 ,Set Enable Bit 141" "Disabled,Enabled" bitfld.long 0x00 12. " SEB140 ,Set Enable Bit 140" "Disabled,Enabled" bitfld.long 0x00 11. " SEB139 ,Set Enable Bit 139" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB138 ,Set Enable Bit 138" "Disabled,Enabled" bitfld.long 0x00 9. " SEB137 ,Set Enable Bit 137" "Disabled,Enabled" bitfld.long 0x00 8. " SEB136 ,Set Enable Bit 136" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB135 ,Set Enable Bit 135" "Disabled,Enabled" bitfld.long 0x00 6. " SEB134 ,Set Enable Bit 134" "Disabled,Enabled" bitfld.long 0x00 5. " SEB133 ,Set Enable Bit 133" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB132 ,Set Enable Bit 132" "Disabled,Enabled" bitfld.long 0x00 3. " SEB131 ,Set Enable Bit 131" "Disabled,Enabled" bitfld.long 0x00 2. " SEB130 ,Set Enable Bit 130" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB129 ,Set Enable Bit 129" "Disabled,Enabled" bitfld.long 0x00 0. " SEB128 ,Set Enable Bit 128" "Disabled,Enabled" group.long 0x1114++0x03 line.long 0x0 "GICD_ISER5,Interrupt Set Enable Register 5" bitfld.long 0x00 31. " SEB191 ,Set Enable Bit 191" "Disabled,Enabled" bitfld.long 0x00 30. " SEB190 ,Set Enable Bit 190" "Disabled,Enabled" bitfld.long 0x00 29. " SEB189 ,Set Enable Bit 189" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB188 ,Set Enable Bit 188" "Disabled,Enabled" bitfld.long 0x00 27. " SEB187 ,Set Enable Bit 187" "Disabled,Enabled" bitfld.long 0x00 26. " SEB186 ,Set Enable Bit 186" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB185 ,Set Enable Bit 185" "Disabled,Enabled" bitfld.long 0x00 24. " SEB184 ,Set Enable Bit 184" "Disabled,Enabled" bitfld.long 0x00 23. " SEB183 ,Set Enable Bit 183" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB182 ,Set Enable Bit 182" "Disabled,Enabled" bitfld.long 0x00 21. " SEB181 ,Set Enable Bit 181" "Disabled,Enabled" bitfld.long 0x00 20. " SEB180 ,Set Enable Bit 180" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB179 ,Set Enable Bit 179" "Disabled,Enabled" bitfld.long 0x00 18. " SEB178 ,Set Enable Bit 178" "Disabled,Enabled" bitfld.long 0x00 17. " SEB177 ,Set Enable Bit 177" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB176 ,Set Enable Bit 176" "Disabled,Enabled" bitfld.long 0x00 15. " SEB175 ,Set Enable Bit 175" "Disabled,Enabled" bitfld.long 0x00 14. " SEB174 ,Set Enable Bit 174" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB173 ,Set Enable Bit 173" "Disabled,Enabled" bitfld.long 0x00 12. " SEB172 ,Set Enable Bit 172" "Disabled,Enabled" bitfld.long 0x00 11. " SEB171 ,Set Enable Bit 171" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB170 ,Set Enable Bit 170" "Disabled,Enabled" bitfld.long 0x00 9. " SEB169 ,Set Enable Bit 169" "Disabled,Enabled" bitfld.long 0x00 8. " SEB168 ,Set Enable Bit 168" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB167 ,Set Enable Bit 167" "Disabled,Enabled" bitfld.long 0x00 6. " SEB166 ,Set Enable Bit 166" "Disabled,Enabled" bitfld.long 0x00 5. " SEB165 ,Set Enable Bit 165" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB164 ,Set Enable Bit 164" "Disabled,Enabled" bitfld.long 0x00 3. " SEB163 ,Set Enable Bit 163" "Disabled,Enabled" bitfld.long 0x00 2. " SEB162 ,Set Enable Bit 162" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB161 ,Set Enable Bit 161" "Disabled,Enabled" bitfld.long 0x00 0. " SEB160 ,Set Enable Bit 160" "Disabled,Enabled" group.long 0x1118++0x03 line.long 0x0 "GICD_ISER6,Interrupt Set Enable Register 6" bitfld.long 0x00 31. " SEB223 ,Set Enable Bit 223" "Disabled,Enabled" bitfld.long 0x00 30. " SEB222 ,Set Enable Bit 222" "Disabled,Enabled" bitfld.long 0x00 29. " SEB221 ,Set Enable Bit 221" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB220 ,Set Enable Bit 220" "Disabled,Enabled" bitfld.long 0x00 27. " SEB219 ,Set Enable Bit 219" "Disabled,Enabled" bitfld.long 0x00 26. " SEB218 ,Set Enable Bit 218" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB217 ,Set Enable Bit 217" "Disabled,Enabled" bitfld.long 0x00 24. " SEB216 ,Set Enable Bit 216" "Disabled,Enabled" bitfld.long 0x00 23. " SEB215 ,Set Enable Bit 215" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB214 ,Set Enable Bit 214" "Disabled,Enabled" bitfld.long 0x00 21. " SEB213 ,Set Enable Bit 213" "Disabled,Enabled" bitfld.long 0x00 20. " SEB212 ,Set Enable Bit 212" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB211 ,Set Enable Bit 211" "Disabled,Enabled" bitfld.long 0x00 18. " SEB210 ,Set Enable Bit 210" "Disabled,Enabled" bitfld.long 0x00 17. " SEB209 ,Set Enable Bit 209" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB208 ,Set Enable Bit 208" "Disabled,Enabled" bitfld.long 0x00 15. " SEB207 ,Set Enable Bit 207" "Disabled,Enabled" bitfld.long 0x00 14. " SEB206 ,Set Enable Bit 206" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB205 ,Set Enable Bit 205" "Disabled,Enabled" bitfld.long 0x00 12. " SEB204 ,Set Enable Bit 204" "Disabled,Enabled" bitfld.long 0x00 11. " SEB203 ,Set Enable Bit 203" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB202 ,Set Enable Bit 202" "Disabled,Enabled" bitfld.long 0x00 9. " SEB201 ,Set Enable Bit 201" "Disabled,Enabled" bitfld.long 0x00 8. " SEB200 ,Set Enable Bit 200" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB199 ,Set Enable Bit 199" "Disabled,Enabled" bitfld.long 0x00 6. " SEB198 ,Set Enable Bit 198" "Disabled,Enabled" bitfld.long 0x00 5. " SEB197 ,Set Enable Bit 197" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB196 ,Set Enable Bit 196" "Disabled,Enabled" bitfld.long 0x00 3. " SEB195 ,Set Enable Bit 195" "Disabled,Enabled" bitfld.long 0x00 2. " SEB194 ,Set Enable Bit 194" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB193 ,Set Enable Bit 193" "Disabled,Enabled" bitfld.long 0x00 0. " SEB192 ,Set Enable Bit 192" "Disabled,Enabled" group.long 0x111C++0x03 line.long 0x0 "GICD_ISER7,Interrupt Set Enable Register 7" bitfld.long 0x00 31. " SEB255 ,Set Enable Bit 255" "Disabled,Enabled" bitfld.long 0x00 30. " SEB254 ,Set Enable Bit 254" "Disabled,Enabled" bitfld.long 0x00 29. " SEB253 ,Set Enable Bit 253" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " SEB252 ,Set Enable Bit 252" "Disabled,Enabled" bitfld.long 0x00 27. " SEB251 ,Set Enable Bit 251" "Disabled,Enabled" bitfld.long 0x00 26. " SEB250 ,Set Enable Bit 250" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SEB249 ,Set Enable Bit 249" "Disabled,Enabled" bitfld.long 0x00 24. " SEB248 ,Set Enable Bit 248" "Disabled,Enabled" bitfld.long 0x00 23. " SEB247 ,Set Enable Bit 247" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SEB246 ,Set Enable Bit 246" "Disabled,Enabled" bitfld.long 0x00 21. " SEB245 ,Set Enable Bit 245" "Disabled,Enabled" bitfld.long 0x00 20. " SEB244 ,Set Enable Bit 244" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " SEB243 ,Set Enable Bit 243" "Disabled,Enabled" bitfld.long 0x00 18. " SEB242 ,Set Enable Bit 242" "Disabled,Enabled" bitfld.long 0x00 17. " SEB241 ,Set Enable Bit 241" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " SEB240 ,Set Enable Bit 240" "Disabled,Enabled" bitfld.long 0x00 15. " SEB239 ,Set Enable Bit 239" "Disabled,Enabled" bitfld.long 0x00 14. " SEB238 ,Set Enable Bit 238" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " SEB237 ,Set Enable Bit 237" "Disabled,Enabled" bitfld.long 0x00 12. " SEB236 ,Set Enable Bit 236" "Disabled,Enabled" bitfld.long 0x00 11. " SEB235 ,Set Enable Bit 235" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " SEB234 ,Set Enable Bit 234" "Disabled,Enabled" bitfld.long 0x00 9. " SEB233 ,Set Enable Bit 233" "Disabled,Enabled" bitfld.long 0x00 8. " SEB232 ,Set Enable Bit 232" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SEB231 ,Set Enable Bit 231" "Disabled,Enabled" bitfld.long 0x00 6. " SEB230 ,Set Enable Bit 230" "Disabled,Enabled" bitfld.long 0x00 5. " SEB229 ,Set Enable Bit 229" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " SEB228 ,Set Enable Bit 228" "Disabled,Enabled" bitfld.long 0x00 3. " SEB227 ,Set Enable Bit 227" "Disabled,Enabled" bitfld.long 0x00 2. " SEB226 ,Set Enable Bit 226" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " SEB225 ,Set Enable Bit 225" "Disabled,Enabled" bitfld.long 0x00 0. " SEB224 ,Set Enable Bit 224" "Disabled,Enabled" tree.end tree "Clear-Enable Registers" group.long 0x1180++0x03 line.long 0x0 "GICD_ICER0,Interrupt Clear Enable Register 0" eventfld.long 0x00 31. " CEB31 ,Clear Enable Bit 31" "Disabled,Enabled" eventfld.long 0x00 30. " CEB30 ,Clear Enable Bit 30" "Disabled,Enabled" eventfld.long 0x00 29. " CEB29 ,Clear Enable Bit 29" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB28 ,Clear Enable Bit 28" "Disabled,Enabled" eventfld.long 0x00 27. " CEB27 ,Clear Enable Bit 27" "Disabled,Enabled" eventfld.long 0x00 26. " CEB26 ,Clear Enable Bit 26" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB25 ,Clear Enable Bit 25" "Disabled,Enabled" eventfld.long 0x00 24. " CEB24 ,Clear Enable Bit 24" "Disabled,Enabled" eventfld.long 0x00 23. " CEB23 ,Clear Enable Bit 23" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB22 ,Clear Enable Bit 22" "Disabled,Enabled" eventfld.long 0x00 21. " CEB21 ,Clear Enable Bit 21" "Disabled,Enabled" eventfld.long 0x00 20. " CEB20 ,Clear Enable Bit 20" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB19 ,Clear Enable Bit 19" "Disabled,Enabled" eventfld.long 0x00 18. " CEB18 ,Clear Enable Bit 18" "Disabled,Enabled" eventfld.long 0x00 17. " CEB17 ,Clear Enable Bit 17" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB16 ,Clear Enable Bit 16" "Disabled,Enabled" eventfld.long 0x00 15. " CEB15 ,Clear Enable Bit 15" "Disabled,Enabled" eventfld.long 0x00 14. " CEB14 ,Clear Enable Bit 14" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB13 ,Clear Enable Bit 13" "Disabled,Enabled" eventfld.long 0x00 12. " CEB12 ,Clear Enable Bit 12" "Disabled,Enabled" eventfld.long 0x00 11. " CEB11 ,Clear Enable Bit 11" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB10 ,Clear Enable Bit 10" "Disabled,Enabled" eventfld.long 0x00 9. " CEB9 ,Clear Enable Bit 9" "Disabled,Enabled" eventfld.long 0x00 8. " CEB8 ,Clear Enable Bit 8" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB7 ,Clear Enable Bit 7" "Disabled,Enabled" eventfld.long 0x00 6. " CEB6 ,Clear Enable Bit 6" "Disabled,Enabled" eventfld.long 0x00 5. " CEB5 ,Clear Enable Bit 5" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB4 ,Clear Enable Bit 4" "Disabled,Enabled" eventfld.long 0x00 3. " CEB3 ,Clear Enable Bit 3" "Disabled,Enabled" eventfld.long 0x00 2. " CEB2 ,Clear Enable Bit 2" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB1 ,Clear Enable Bit 1" "Disabled,Enabled" eventfld.long 0x00 0. " CEB0 ,Clear Enable Bit 0" "Disabled,Enabled" group.long 0x1184++0x03 line.long 0x0 "GICD_ICER1,Interrupt Clear Enable Register 1" eventfld.long 0x00 31. " CEB63 ,Clear Enable Bit 63" "Disabled,Enabled" eventfld.long 0x00 30. " CEB62 ,Clear Enable Bit 62" "Disabled,Enabled" eventfld.long 0x00 29. " CEB61 ,Clear Enable Bit 61" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB60 ,Clear Enable Bit 60" "Disabled,Enabled" eventfld.long 0x00 27. " CEB59 ,Clear Enable Bit 59" "Disabled,Enabled" eventfld.long 0x00 26. " CEB58 ,Clear Enable Bit 58" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB57 ,Clear Enable Bit 57" "Disabled,Enabled" eventfld.long 0x00 24. " CEB56 ,Clear Enable Bit 56" "Disabled,Enabled" eventfld.long 0x00 23. " CEB55 ,Clear Enable Bit 55" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB54 ,Clear Enable Bit 54" "Disabled,Enabled" eventfld.long 0x00 21. " CEB53 ,Clear Enable Bit 53" "Disabled,Enabled" eventfld.long 0x00 20. " CEB52 ,Clear Enable Bit 52" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB51 ,Clear Enable Bit 51" "Disabled,Enabled" eventfld.long 0x00 18. " CEB50 ,Clear Enable Bit 50" "Disabled,Enabled" eventfld.long 0x00 17. " CEB49 ,Clear Enable Bit 49" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB48 ,Clear Enable Bit 48" "Disabled,Enabled" eventfld.long 0x00 15. " CEB47 ,Clear Enable Bit 47" "Disabled,Enabled" eventfld.long 0x00 14. " CEB46 ,Clear Enable Bit 46" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB45 ,Clear Enable Bit 45" "Disabled,Enabled" eventfld.long 0x00 12. " CEB44 ,Clear Enable Bit 44" "Disabled,Enabled" eventfld.long 0x00 11. " CEB43 ,Clear Enable Bit 43" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB42 ,Clear Enable Bit 42" "Disabled,Enabled" eventfld.long 0x00 9. " CEB41 ,Clear Enable Bit 41" "Disabled,Enabled" eventfld.long 0x00 8. " CEB40 ,Clear Enable Bit 40" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB39 ,Clear Enable Bit 39" "Disabled,Enabled" eventfld.long 0x00 6. " CEB38 ,Clear Enable Bit 38" "Disabled,Enabled" eventfld.long 0x00 5. " CEB37 ,Clear Enable Bit 37" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB36 ,Clear Enable Bit 36" "Disabled,Enabled" eventfld.long 0x00 3. " CEB35 ,Clear Enable Bit 35" "Disabled,Enabled" eventfld.long 0x00 2. " CEB34 ,Clear Enable Bit 34" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB33 ,Clear Enable Bit 33" "Disabled,Enabled" eventfld.long 0x00 0. " CEB32 ,Clear Enable Bit 32" "Disabled,Enabled" group.long 0x1188++0x03 line.long 0x0 "GICD_ICER2,Interrupt Clear Enable Register 2" eventfld.long 0x00 31. " CEB95 ,Clear Enable Bit 95" "Disabled,Enabled" eventfld.long 0x00 30. " CEB94 ,Clear Enable Bit 94" "Disabled,Enabled" eventfld.long 0x00 29. " CEB93 ,Clear Enable Bit 93" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB92 ,Clear Enable Bit 92" "Disabled,Enabled" eventfld.long 0x00 27. " CEB91 ,Clear Enable Bit 91" "Disabled,Enabled" eventfld.long 0x00 26. " CEB90 ,Clear Enable Bit 90" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB89 ,Clear Enable Bit 89" "Disabled,Enabled" eventfld.long 0x00 24. " CEB88 ,Clear Enable Bit 88" "Disabled,Enabled" eventfld.long 0x00 23. " CEB87 ,Clear Enable Bit 87" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB86 ,Clear Enable Bit 86" "Disabled,Enabled" eventfld.long 0x00 21. " CEB85 ,Clear Enable Bit 85" "Disabled,Enabled" eventfld.long 0x00 20. " CEB84 ,Clear Enable Bit 84" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB83 ,Clear Enable Bit 83" "Disabled,Enabled" eventfld.long 0x00 18. " CEB82 ,Clear Enable Bit 82" "Disabled,Enabled" eventfld.long 0x00 17. " CEB81 ,Clear Enable Bit 81" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB80 ,Clear Enable Bit 80" "Disabled,Enabled" eventfld.long 0x00 15. " CEB79 ,Clear Enable Bit 79" "Disabled,Enabled" eventfld.long 0x00 14. " CEB78 ,Clear Enable Bit 78" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB77 ,Clear Enable Bit 77" "Disabled,Enabled" eventfld.long 0x00 12. " CEB76 ,Clear Enable Bit 76" "Disabled,Enabled" eventfld.long 0x00 11. " CEB75 ,Clear Enable Bit 75" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB74 ,Clear Enable Bit 74" "Disabled,Enabled" eventfld.long 0x00 9. " CEB73 ,Clear Enable Bit 73" "Disabled,Enabled" eventfld.long 0x00 8. " CEB72 ,Clear Enable Bit 72" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB71 ,Clear Enable Bit 71" "Disabled,Enabled" eventfld.long 0x00 6. " CEB70 ,Clear Enable Bit 70" "Disabled,Enabled" eventfld.long 0x00 5. " CEB69 ,Clear Enable Bit 69" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB68 ,Clear Enable Bit 68" "Disabled,Enabled" eventfld.long 0x00 3. " CEB67 ,Clear Enable Bit 67" "Disabled,Enabled" eventfld.long 0x00 2. " CEB66 ,Clear Enable Bit 66" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB65 ,Clear Enable Bit 65" "Disabled,Enabled" eventfld.long 0x00 0. " CEB64 ,Clear Enable Bit 64" "Disabled,Enabled" group.long 0x118C++0x03 line.long 0x0 "GICD_ICER3,Interrupt Clear Enable Register 3" eventfld.long 0x00 31. " CEB127 ,Clear Enable Bit 127" "Disabled,Enabled" eventfld.long 0x00 30. " CEB126 ,Clear Enable Bit 126" "Disabled,Enabled" eventfld.long 0x00 29. " CEB125 ,Clear Enable Bit 125" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB124 ,Clear Enable Bit 124" "Disabled,Enabled" eventfld.long 0x00 27. " CEB123 ,Clear Enable Bit 123" "Disabled,Enabled" eventfld.long 0x00 26. " CEB122 ,Clear Enable Bit 122" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB121 ,Clear Enable Bit 121" "Disabled,Enabled" eventfld.long 0x00 24. " CEB120 ,Clear Enable Bit 120" "Disabled,Enabled" eventfld.long 0x00 23. " CEB119 ,Clear Enable Bit 119" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB118 ,Clear Enable Bit 118" "Disabled,Enabled" eventfld.long 0x00 21. " CEB117 ,Clear Enable Bit 117" "Disabled,Enabled" eventfld.long 0x00 20. " CEB116 ,Clear Enable Bit 116" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB115 ,Clear Enable Bit 115" "Disabled,Enabled" eventfld.long 0x00 18. " CEB114 ,Clear Enable Bit 114" "Disabled,Enabled" eventfld.long 0x00 17. " CEB113 ,Clear Enable Bit 113" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB112 ,Clear Enable Bit 112" "Disabled,Enabled" eventfld.long 0x00 15. " CEB111 ,Clear Enable Bit 111" "Disabled,Enabled" eventfld.long 0x00 14. " CEB110 ,Clear Enable Bit 110" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB109 ,Clear Enable Bit 109" "Disabled,Enabled" eventfld.long 0x00 12. " CEB108 ,Clear Enable Bit 108" "Disabled,Enabled" eventfld.long 0x00 11. " CEB107 ,Clear Enable Bit 107" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB106 ,Clear Enable Bit 106" "Disabled,Enabled" eventfld.long 0x00 9. " CEB105 ,Clear Enable Bit 105" "Disabled,Enabled" eventfld.long 0x00 8. " CEB104 ,Clear Enable Bit 104" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB103 ,Clear Enable Bit 103" "Disabled,Enabled" eventfld.long 0x00 6. " CEB102 ,Clear Enable Bit 102" "Disabled,Enabled" eventfld.long 0x00 5. " CEB101 ,Clear Enable Bit 101" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB100 ,Clear Enable Bit 100" "Disabled,Enabled" eventfld.long 0x00 3. " CEB99 ,Clear Enable Bit 99" "Disabled,Enabled" eventfld.long 0x00 2. " CEB98 ,Clear Enable Bit 98" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB97 ,Clear Enable Bit 97" "Disabled,Enabled" eventfld.long 0x00 0. " CEB96 ,Clear Enable Bit 96" "Disabled,Enabled" group.long 0x1190++0x03 line.long 0x0 "GICD_ICER4,Interrupt Clear Enable Register 4" eventfld.long 0x00 31. " CEB159 ,Clear Enable Bit 159" "Disabled,Enabled" eventfld.long 0x00 30. " CEB158 ,Clear Enable Bit 158" "Disabled,Enabled" eventfld.long 0x00 29. " CEB157 ,Clear Enable Bit 157" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB156 ,Clear Enable Bit 156" "Disabled,Enabled" eventfld.long 0x00 27. " CEB155 ,Clear Enable Bit 155" "Disabled,Enabled" eventfld.long 0x00 26. " CEB154 ,Clear Enable Bit 154" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB153 ,Clear Enable Bit 153" "Disabled,Enabled" eventfld.long 0x00 24. " CEB152 ,Clear Enable Bit 152" "Disabled,Enabled" eventfld.long 0x00 23. " CEB151 ,Clear Enable Bit 151" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB150 ,Clear Enable Bit 150" "Disabled,Enabled" eventfld.long 0x00 21. " CEB149 ,Clear Enable Bit 149" "Disabled,Enabled" eventfld.long 0x00 20. " CEB148 ,Clear Enable Bit 148" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB147 ,Clear Enable Bit 147" "Disabled,Enabled" eventfld.long 0x00 18. " CEB146 ,Clear Enable Bit 146" "Disabled,Enabled" eventfld.long 0x00 17. " CEB145 ,Clear Enable Bit 145" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB144 ,Clear Enable Bit 144" "Disabled,Enabled" eventfld.long 0x00 15. " CEB143 ,Clear Enable Bit 143" "Disabled,Enabled" eventfld.long 0x00 14. " CEB142 ,Clear Enable Bit 142" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB141 ,Clear Enable Bit 141" "Disabled,Enabled" eventfld.long 0x00 12. " CEB140 ,Clear Enable Bit 140" "Disabled,Enabled" eventfld.long 0x00 11. " CEB139 ,Clear Enable Bit 139" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB138 ,Clear Enable Bit 138" "Disabled,Enabled" eventfld.long 0x00 9. " CEB137 ,Clear Enable Bit 137" "Disabled,Enabled" eventfld.long 0x00 8. " CEB136 ,Clear Enable Bit 136" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB135 ,Clear Enable Bit 135" "Disabled,Enabled" eventfld.long 0x00 6. " CEB134 ,Clear Enable Bit 134" "Disabled,Enabled" eventfld.long 0x00 5. " CEB133 ,Clear Enable Bit 133" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB132 ,Clear Enable Bit 132" "Disabled,Enabled" eventfld.long 0x00 3. " CEB131 ,Clear Enable Bit 131" "Disabled,Enabled" eventfld.long 0x00 2. " CEB130 ,Clear Enable Bit 130" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB129 ,Clear Enable Bit 129" "Disabled,Enabled" eventfld.long 0x00 0. " CEB128 ,Clear Enable Bit 128" "Disabled,Enabled" group.long 0x1194++0x03 line.long 0x0 "GICD_ICER5,Interrupt Clear Enable Register 5" eventfld.long 0x00 31. " CEB191 ,Clear Enable Bit 191" "Disabled,Enabled" eventfld.long 0x00 30. " CEB190 ,Clear Enable Bit 190" "Disabled,Enabled" eventfld.long 0x00 29. " CEB189 ,Clear Enable Bit 189" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB188 ,Clear Enable Bit 188" "Disabled,Enabled" eventfld.long 0x00 27. " CEB187 ,Clear Enable Bit 187" "Disabled,Enabled" eventfld.long 0x00 26. " CEB186 ,Clear Enable Bit 186" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB185 ,Clear Enable Bit 185" "Disabled,Enabled" eventfld.long 0x00 24. " CEB184 ,Clear Enable Bit 184" "Disabled,Enabled" eventfld.long 0x00 23. " CEB183 ,Clear Enable Bit 183" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB182 ,Clear Enable Bit 182" "Disabled,Enabled" eventfld.long 0x00 21. " CEB181 ,Clear Enable Bit 181" "Disabled,Enabled" eventfld.long 0x00 20. " CEB180 ,Clear Enable Bit 180" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB179 ,Clear Enable Bit 179" "Disabled,Enabled" eventfld.long 0x00 18. " CEB178 ,Clear Enable Bit 178" "Disabled,Enabled" eventfld.long 0x00 17. " CEB177 ,Clear Enable Bit 177" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB176 ,Clear Enable Bit 176" "Disabled,Enabled" eventfld.long 0x00 15. " CEB175 ,Clear Enable Bit 175" "Disabled,Enabled" eventfld.long 0x00 14. " CEB174 ,Clear Enable Bit 174" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB173 ,Clear Enable Bit 173" "Disabled,Enabled" eventfld.long 0x00 12. " CEB172 ,Clear Enable Bit 172" "Disabled,Enabled" eventfld.long 0x00 11. " CEB171 ,Clear Enable Bit 171" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB170 ,Clear Enable Bit 170" "Disabled,Enabled" eventfld.long 0x00 9. " CEB169 ,Clear Enable Bit 169" "Disabled,Enabled" eventfld.long 0x00 8. " CEB168 ,Clear Enable Bit 168" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB167 ,Clear Enable Bit 167" "Disabled,Enabled" eventfld.long 0x00 6. " CEB166 ,Clear Enable Bit 166" "Disabled,Enabled" eventfld.long 0x00 5. " CEB165 ,Clear Enable Bit 165" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB164 ,Clear Enable Bit 164" "Disabled,Enabled" eventfld.long 0x00 3. " CEB163 ,Clear Enable Bit 163" "Disabled,Enabled" eventfld.long 0x00 2. " CEB162 ,Clear Enable Bit 162" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB161 ,Clear Enable Bit 161" "Disabled,Enabled" eventfld.long 0x00 0. " CEB160 ,Clear Enable Bit 160" "Disabled,Enabled" group.long 0x1198++0x03 line.long 0x0 "GICD_ICER6,Interrupt Clear Enable Register 6" eventfld.long 0x00 31. " CEB223 ,Clear Enable Bit 223" "Disabled,Enabled" eventfld.long 0x00 30. " CEB222 ,Clear Enable Bit 222" "Disabled,Enabled" eventfld.long 0x00 29. " CEB221 ,Clear Enable Bit 221" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB220 ,Clear Enable Bit 220" "Disabled,Enabled" eventfld.long 0x00 27. " CEB219 ,Clear Enable Bit 219" "Disabled,Enabled" eventfld.long 0x00 26. " CEB218 ,Clear Enable Bit 218" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB217 ,Clear Enable Bit 217" "Disabled,Enabled" eventfld.long 0x00 24. " CEB216 ,Clear Enable Bit 216" "Disabled,Enabled" eventfld.long 0x00 23. " CEB215 ,Clear Enable Bit 215" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB214 ,Clear Enable Bit 214" "Disabled,Enabled" eventfld.long 0x00 21. " CEB213 ,Clear Enable Bit 213" "Disabled,Enabled" eventfld.long 0x00 20. " CEB212 ,Clear Enable Bit 212" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB211 ,Clear Enable Bit 211" "Disabled,Enabled" eventfld.long 0x00 18. " CEB210 ,Clear Enable Bit 210" "Disabled,Enabled" eventfld.long 0x00 17. " CEB209 ,Clear Enable Bit 209" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB208 ,Clear Enable Bit 208" "Disabled,Enabled" eventfld.long 0x00 15. " CEB207 ,Clear Enable Bit 207" "Disabled,Enabled" eventfld.long 0x00 14. " CEB206 ,Clear Enable Bit 206" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB205 ,Clear Enable Bit 205" "Disabled,Enabled" eventfld.long 0x00 12. " CEB204 ,Clear Enable Bit 204" "Disabled,Enabled" eventfld.long 0x00 11. " CEB203 ,Clear Enable Bit 203" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB202 ,Clear Enable Bit 202" "Disabled,Enabled" eventfld.long 0x00 9. " CEB201 ,Clear Enable Bit 201" "Disabled,Enabled" eventfld.long 0x00 8. " CEB200 ,Clear Enable Bit 200" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB199 ,Clear Enable Bit 199" "Disabled,Enabled" eventfld.long 0x00 6. " CEB198 ,Clear Enable Bit 198" "Disabled,Enabled" eventfld.long 0x00 5. " CEB197 ,Clear Enable Bit 197" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB196 ,Clear Enable Bit 196" "Disabled,Enabled" eventfld.long 0x00 3. " CEB195 ,Clear Enable Bit 195" "Disabled,Enabled" eventfld.long 0x00 2. " CEB194 ,Clear Enable Bit 194" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB193 ,Clear Enable Bit 193" "Disabled,Enabled" eventfld.long 0x00 0. " CEB192 ,Clear Enable Bit 192" "Disabled,Enabled" group.long 0x119C++0x03 line.long 0x0 "GICD_ICER7,Interrupt Clear Enable Register 7" eventfld.long 0x00 31. " CEB255 ,Clear Enable Bit 255" "Disabled,Enabled" eventfld.long 0x00 30. " CEB254 ,Clear Enable Bit 254" "Disabled,Enabled" eventfld.long 0x00 29. " CEB253 ,Clear Enable Bit 253" "Disabled,Enabled" textline " " eventfld.long 0x00 28. " CEB252 ,Clear Enable Bit 252" "Disabled,Enabled" eventfld.long 0x00 27. " CEB251 ,Clear Enable Bit 251" "Disabled,Enabled" eventfld.long 0x00 26. " CEB250 ,Clear Enable Bit 250" "Disabled,Enabled" textline " " eventfld.long 0x00 25. " CEB249 ,Clear Enable Bit 249" "Disabled,Enabled" eventfld.long 0x00 24. " CEB248 ,Clear Enable Bit 248" "Disabled,Enabled" eventfld.long 0x00 23. " CEB247 ,Clear Enable Bit 247" "Disabled,Enabled" textline " " eventfld.long 0x00 22. " CEB246 ,Clear Enable Bit 246" "Disabled,Enabled" eventfld.long 0x00 21. " CEB245 ,Clear Enable Bit 245" "Disabled,Enabled" eventfld.long 0x00 20. " CEB244 ,Clear Enable Bit 244" "Disabled,Enabled" textline " " eventfld.long 0x00 19. " CEB243 ,Clear Enable Bit 243" "Disabled,Enabled" eventfld.long 0x00 18. " CEB242 ,Clear Enable Bit 242" "Disabled,Enabled" eventfld.long 0x00 17. " CEB241 ,Clear Enable Bit 241" "Disabled,Enabled" textline " " eventfld.long 0x00 16. " CEB240 ,Clear Enable Bit 240" "Disabled,Enabled" eventfld.long 0x00 15. " CEB239 ,Clear Enable Bit 239" "Disabled,Enabled" eventfld.long 0x00 14. " CEB238 ,Clear Enable Bit 238" "Disabled,Enabled" textline " " eventfld.long 0x00 13. " CEB237 ,Clear Enable Bit 237" "Disabled,Enabled" eventfld.long 0x00 12. " CEB236 ,Clear Enable Bit 236" "Disabled,Enabled" eventfld.long 0x00 11. " CEB235 ,Clear Enable Bit 235" "Disabled,Enabled" textline " " eventfld.long 0x00 10. " CEB234 ,Clear Enable Bit 234" "Disabled,Enabled" eventfld.long 0x00 9. " CEB233 ,Clear Enable Bit 233" "Disabled,Enabled" eventfld.long 0x00 8. " CEB232 ,Clear Enable Bit 232" "Disabled,Enabled" textline " " eventfld.long 0x00 7. " CEB231 ,Clear Enable Bit 231" "Disabled,Enabled" eventfld.long 0x00 6. " CEB230 ,Clear Enable Bit 230" "Disabled,Enabled" eventfld.long 0x00 5. " CEB229 ,Clear Enable Bit 229" "Disabled,Enabled" textline " " eventfld.long 0x00 4. " CEB228 ,Clear Enable Bit 228" "Disabled,Enabled" eventfld.long 0x00 3. " CEB227 ,Clear Enable Bit 227" "Disabled,Enabled" eventfld.long 0x00 2. " CEB226 ,Clear Enable Bit 226" "Disabled,Enabled" textline " " eventfld.long 0x00 1. " CEB225 ,Clear Enable Bit 225" "Disabled,Enabled" eventfld.long 0x00 0. " CEB224 ,Clear Enable Bit 224" "Disabled,Enabled" tree.end tree "Set-Pending Registers" group.long 0x1200++0x03 line.long 0x0 "GICD_ISPR0,Interrupt Set Pending Register 0" bitfld.long 0x00 31. " SPB31 ,Set Pending Bit 31" "Not pending,Pending" bitfld.long 0x00 30. " SPB30 ,Set Pending Bit 30" "Not pending,Pending" bitfld.long 0x00 29. " SPB29 ,Set Pending Bit 29" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB28 ,Set Pending Bit 28" "Not pending,Pending" bitfld.long 0x00 27. " SPB27 ,Set Pending Bit 27" "Not pending,Pending" bitfld.long 0x00 26. " SPB26 ,Set Pending Bit 26" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB25 ,Set Pending Bit 25" "Not pending,Pending" bitfld.long 0x00 24. " SPB24 ,Set Pending Bit 24" "Not pending,Pending" bitfld.long 0x00 23. " SPB23 ,Set Pending Bit 23" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB22 ,Set Pending Bit 22" "Not pending,Pending" bitfld.long 0x00 21. " SPB21 ,Set Pending Bit 21" "Not pending,Pending" bitfld.long 0x00 20. " SPB20 ,Set Pending Bit 20" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB19 ,Set Pending Bit 19" "Not pending,Pending" bitfld.long 0x00 18. " SPB18 ,Set Pending Bit 18" "Not pending,Pending" bitfld.long 0x00 17. " SPB17 ,Set Pending Bit 17" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB16 ,Set Pending Bit 16" "Not pending,Pending" bitfld.long 0x00 15. " SPB15 ,Set Pending Bit 15" "Not pending,Pending" bitfld.long 0x00 14. " SPB14 ,Set Pending Bit 14" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB13 ,Set Pending Bit 13" "Not pending,Pending" bitfld.long 0x00 12. " SPB12 ,Set Pending Bit 12" "Not pending,Pending" bitfld.long 0x00 11. " SPB11 ,Set Pending Bit 11" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB10 ,Set Pending Bit 10" "Not pending,Pending" bitfld.long 0x00 9. " SPB9 ,Set Pending Bit 9" "Not pending,Pending" bitfld.long 0x00 8. " SPB8 ,Set Pending Bit 8" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB7 ,Set Pending Bit 7" "Not pending,Pending" bitfld.long 0x00 6. " SPB6 ,Set Pending Bit 6" "Not pending,Pending" bitfld.long 0x00 5. " SPB5 ,Set Pending Bit 5" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB4 ,Set Pending Bit 4" "Not pending,Pending" bitfld.long 0x00 3. " SPB3 ,Set Pending Bit 3" "Not pending,Pending" bitfld.long 0x00 2. " SPB2 ,Set Pending Bit 2" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB1 ,Set Pending Bit 1" "Not pending,Pending" bitfld.long 0x00 0. " SPB0 ,Set Pending Bit 0" "Not pending,Pending" group.long 0x1204++0x03 line.long 0x0 "GICD_ISPR1,Interrupt Set Pending Register 1" bitfld.long 0x00 31. " SPB63 ,Set Pending Bit 63" "Not pending,Pending" bitfld.long 0x00 30. " SPB62 ,Set Pending Bit 62" "Not pending,Pending" bitfld.long 0x00 29. " SPB61 ,Set Pending Bit 61" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB60 ,Set Pending Bit 60" "Not pending,Pending" bitfld.long 0x00 27. " SPB59 ,Set Pending Bit 59" "Not pending,Pending" bitfld.long 0x00 26. " SPB58 ,Set Pending Bit 58" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB57 ,Set Pending Bit 57" "Not pending,Pending" bitfld.long 0x00 24. " SPB56 ,Set Pending Bit 56" "Not pending,Pending" bitfld.long 0x00 23. " SPB55 ,Set Pending Bit 55" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB54 ,Set Pending Bit 54" "Not pending,Pending" bitfld.long 0x00 21. " SPB53 ,Set Pending Bit 53" "Not pending,Pending" bitfld.long 0x00 20. " SPB52 ,Set Pending Bit 52" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB51 ,Set Pending Bit 51" "Not pending,Pending" bitfld.long 0x00 18. " SPB50 ,Set Pending Bit 50" "Not pending,Pending" bitfld.long 0x00 17. " SPB49 ,Set Pending Bit 49" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB48 ,Set Pending Bit 48" "Not pending,Pending" bitfld.long 0x00 15. " SPB47 ,Set Pending Bit 47" "Not pending,Pending" bitfld.long 0x00 14. " SPB46 ,Set Pending Bit 46" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB45 ,Set Pending Bit 45" "Not pending,Pending" bitfld.long 0x00 12. " SPB44 ,Set Pending Bit 44" "Not pending,Pending" bitfld.long 0x00 11. " SPB43 ,Set Pending Bit 43" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB42 ,Set Pending Bit 42" "Not pending,Pending" bitfld.long 0x00 9. " SPB41 ,Set Pending Bit 41" "Not pending,Pending" bitfld.long 0x00 8. " SPB40 ,Set Pending Bit 40" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB39 ,Set Pending Bit 39" "Not pending,Pending" bitfld.long 0x00 6. " SPB38 ,Set Pending Bit 38" "Not pending,Pending" bitfld.long 0x00 5. " SPB37 ,Set Pending Bit 37" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB36 ,Set Pending Bit 36" "Not pending,Pending" bitfld.long 0x00 3. " SPB35 ,Set Pending Bit 35" "Not pending,Pending" bitfld.long 0x00 2. " SPB34 ,Set Pending Bit 34" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB33 ,Set Pending Bit 33" "Not pending,Pending" bitfld.long 0x00 0. " SPB32 ,Set Pending Bit 32" "Not pending,Pending" group.long 0x1208++0x03 line.long 0x0 "GICD_ISPR2,Interrupt Set Pending Register 2" bitfld.long 0x00 31. " SPB95 ,Set Pending Bit 95" "Not pending,Pending" bitfld.long 0x00 30. " SPB94 ,Set Pending Bit 94" "Not pending,Pending" bitfld.long 0x00 29. " SPB93 ,Set Pending Bit 93" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB92 ,Set Pending Bit 92" "Not pending,Pending" bitfld.long 0x00 27. " SPB91 ,Set Pending Bit 91" "Not pending,Pending" bitfld.long 0x00 26. " SPB90 ,Set Pending Bit 90" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB89 ,Set Pending Bit 89" "Not pending,Pending" bitfld.long 0x00 24. " SPB88 ,Set Pending Bit 88" "Not pending,Pending" bitfld.long 0x00 23. " SPB87 ,Set Pending Bit 87" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB86 ,Set Pending Bit 86" "Not pending,Pending" bitfld.long 0x00 21. " SPB85 ,Set Pending Bit 85" "Not pending,Pending" bitfld.long 0x00 20. " SPB84 ,Set Pending Bit 84" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB83 ,Set Pending Bit 83" "Not pending,Pending" bitfld.long 0x00 18. " SPB82 ,Set Pending Bit 82" "Not pending,Pending" bitfld.long 0x00 17. " SPB81 ,Set Pending Bit 81" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB80 ,Set Pending Bit 80" "Not pending,Pending" bitfld.long 0x00 15. " SPB79 ,Set Pending Bit 79" "Not pending,Pending" bitfld.long 0x00 14. " SPB78 ,Set Pending Bit 78" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB77 ,Set Pending Bit 77" "Not pending,Pending" bitfld.long 0x00 12. " SPB76 ,Set Pending Bit 76" "Not pending,Pending" bitfld.long 0x00 11. " SPB75 ,Set Pending Bit 75" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB74 ,Set Pending Bit 74" "Not pending,Pending" bitfld.long 0x00 9. " SPB73 ,Set Pending Bit 73" "Not pending,Pending" bitfld.long 0x00 8. " SPB72 ,Set Pending Bit 72" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB71 ,Set Pending Bit 71" "Not pending,Pending" bitfld.long 0x00 6. " SPB70 ,Set Pending Bit 70" "Not pending,Pending" bitfld.long 0x00 5. " SPB69 ,Set Pending Bit 69" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB68 ,Set Pending Bit 68" "Not pending,Pending" bitfld.long 0x00 3. " SPB67 ,Set Pending Bit 67" "Not pending,Pending" bitfld.long 0x00 2. " SPB66 ,Set Pending Bit 66" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB65 ,Set Pending Bit 65" "Not pending,Pending" bitfld.long 0x00 0. " SPB64 ,Set Pending Bit 64" "Not pending,Pending" group.long 0x120C++0x03 line.long 0x0 "GICD_ISPR3,Interrupt Set Pending Register 3" bitfld.long 0x00 31. " SPB127 ,Set Pending Bit 127" "Not pending,Pending" bitfld.long 0x00 30. " SPB126 ,Set Pending Bit 126" "Not pending,Pending" bitfld.long 0x00 29. " SPB125 ,Set Pending Bit 125" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB124 ,Set Pending Bit 124" "Not pending,Pending" bitfld.long 0x00 27. " SPB123 ,Set Pending Bit 123" "Not pending,Pending" bitfld.long 0x00 26. " SPB122 ,Set Pending Bit 122" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB121 ,Set Pending Bit 121" "Not pending,Pending" bitfld.long 0x00 24. " SPB120 ,Set Pending Bit 120" "Not pending,Pending" bitfld.long 0x00 23. " SPB119 ,Set Pending Bit 119" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB118 ,Set Pending Bit 118" "Not pending,Pending" bitfld.long 0x00 21. " SPB117 ,Set Pending Bit 117" "Not pending,Pending" bitfld.long 0x00 20. " SPB116 ,Set Pending Bit 116" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB115 ,Set Pending Bit 115" "Not pending,Pending" bitfld.long 0x00 18. " SPB114 ,Set Pending Bit 114" "Not pending,Pending" bitfld.long 0x00 17. " SPB113 ,Set Pending Bit 113" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB112 ,Set Pending Bit 112" "Not pending,Pending" bitfld.long 0x00 15. " SPB111 ,Set Pending Bit 111" "Not pending,Pending" bitfld.long 0x00 14. " SPB110 ,Set Pending Bit 110" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB109 ,Set Pending Bit 109" "Not pending,Pending" bitfld.long 0x00 12. " SPB108 ,Set Pending Bit 108" "Not pending,Pending" bitfld.long 0x00 11. " SPB107 ,Set Pending Bit 107" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB106 ,Set Pending Bit 106" "Not pending,Pending" bitfld.long 0x00 9. " SPB105 ,Set Pending Bit 105" "Not pending,Pending" bitfld.long 0x00 8. " SPB104 ,Set Pending Bit 104" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB103 ,Set Pending Bit 103" "Not pending,Pending" bitfld.long 0x00 6. " SPB102 ,Set Pending Bit 102" "Not pending,Pending" bitfld.long 0x00 5. " SPB101 ,Set Pending Bit 101" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB100 ,Set Pending Bit 100" "Not pending,Pending" bitfld.long 0x00 3. " SPB99 ,Set Pending Bit 99" "Not pending,Pending" bitfld.long 0x00 2. " SPB98 ,Set Pending Bit 98" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB97 ,Set Pending Bit 97" "Not pending,Pending" bitfld.long 0x00 0. " SPB96 ,Set Pending Bit 96" "Not pending,Pending" group.long 0x1210++0x03 line.long 0x0 "GICD_ISPR4,Interrupt Set Pending Register 4" bitfld.long 0x00 31. " SPB159 ,Set Pending Bit 159" "Not pending,Pending" bitfld.long 0x00 30. " SPB158 ,Set Pending Bit 158" "Not pending,Pending" bitfld.long 0x00 29. " SPB157 ,Set Pending Bit 157" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB156 ,Set Pending Bit 156" "Not pending,Pending" bitfld.long 0x00 27. " SPB155 ,Set Pending Bit 155" "Not pending,Pending" bitfld.long 0x00 26. " SPB154 ,Set Pending Bit 154" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB153 ,Set Pending Bit 153" "Not pending,Pending" bitfld.long 0x00 24. " SPB152 ,Set Pending Bit 152" "Not pending,Pending" bitfld.long 0x00 23. " SPB151 ,Set Pending Bit 151" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB150 ,Set Pending Bit 150" "Not pending,Pending" bitfld.long 0x00 21. " SPB149 ,Set Pending Bit 149" "Not pending,Pending" bitfld.long 0x00 20. " SPB148 ,Set Pending Bit 148" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB147 ,Set Pending Bit 147" "Not pending,Pending" bitfld.long 0x00 18. " SPB146 ,Set Pending Bit 146" "Not pending,Pending" bitfld.long 0x00 17. " SPB145 ,Set Pending Bit 145" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB144 ,Set Pending Bit 144" "Not pending,Pending" bitfld.long 0x00 15. " SPB143 ,Set Pending Bit 143" "Not pending,Pending" bitfld.long 0x00 14. " SPB142 ,Set Pending Bit 142" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB141 ,Set Pending Bit 141" "Not pending,Pending" bitfld.long 0x00 12. " SPB140 ,Set Pending Bit 140" "Not pending,Pending" bitfld.long 0x00 11. " SPB139 ,Set Pending Bit 139" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB138 ,Set Pending Bit 138" "Not pending,Pending" bitfld.long 0x00 9. " SPB137 ,Set Pending Bit 137" "Not pending,Pending" bitfld.long 0x00 8. " SPB136 ,Set Pending Bit 136" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB135 ,Set Pending Bit 135" "Not pending,Pending" bitfld.long 0x00 6. " SPB134 ,Set Pending Bit 134" "Not pending,Pending" bitfld.long 0x00 5. " SPB133 ,Set Pending Bit 133" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB132 ,Set Pending Bit 132" "Not pending,Pending" bitfld.long 0x00 3. " SPB131 ,Set Pending Bit 131" "Not pending,Pending" bitfld.long 0x00 2. " SPB130 ,Set Pending Bit 130" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB129 ,Set Pending Bit 129" "Not pending,Pending" bitfld.long 0x00 0. " SPB128 ,Set Pending Bit 128" "Not pending,Pending" group.long 0x1214++0x03 line.long 0x0 "GICD_ISPR5,Interrupt Set Pending Register 5" bitfld.long 0x00 31. " SPB191 ,Set Pending Bit 191" "Not pending,Pending" bitfld.long 0x00 30. " SPB190 ,Set Pending Bit 190" "Not pending,Pending" bitfld.long 0x00 29. " SPB189 ,Set Pending Bit 189" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB188 ,Set Pending Bit 188" "Not pending,Pending" bitfld.long 0x00 27. " SPB187 ,Set Pending Bit 187" "Not pending,Pending" bitfld.long 0x00 26. " SPB186 ,Set Pending Bit 186" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB185 ,Set Pending Bit 185" "Not pending,Pending" bitfld.long 0x00 24. " SPB184 ,Set Pending Bit 184" "Not pending,Pending" bitfld.long 0x00 23. " SPB183 ,Set Pending Bit 183" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB182 ,Set Pending Bit 182" "Not pending,Pending" bitfld.long 0x00 21. " SPB181 ,Set Pending Bit 181" "Not pending,Pending" bitfld.long 0x00 20. " SPB180 ,Set Pending Bit 180" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB179 ,Set Pending Bit 179" "Not pending,Pending" bitfld.long 0x00 18. " SPB178 ,Set Pending Bit 178" "Not pending,Pending" bitfld.long 0x00 17. " SPB177 ,Set Pending Bit 177" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB176 ,Set Pending Bit 176" "Not pending,Pending" bitfld.long 0x00 15. " SPB175 ,Set Pending Bit 175" "Not pending,Pending" bitfld.long 0x00 14. " SPB174 ,Set Pending Bit 174" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB173 ,Set Pending Bit 173" "Not pending,Pending" bitfld.long 0x00 12. " SPB172 ,Set Pending Bit 172" "Not pending,Pending" bitfld.long 0x00 11. " SPB171 ,Set Pending Bit 171" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB170 ,Set Pending Bit 170" "Not pending,Pending" bitfld.long 0x00 9. " SPB169 ,Set Pending Bit 169" "Not pending,Pending" bitfld.long 0x00 8. " SPB168 ,Set Pending Bit 168" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB167 ,Set Pending Bit 167" "Not pending,Pending" bitfld.long 0x00 6. " SPB166 ,Set Pending Bit 166" "Not pending,Pending" bitfld.long 0x00 5. " SPB165 ,Set Pending Bit 165" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB164 ,Set Pending Bit 164" "Not pending,Pending" bitfld.long 0x00 3. " SPB163 ,Set Pending Bit 163" "Not pending,Pending" bitfld.long 0x00 2. " SPB162 ,Set Pending Bit 162" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB161 ,Set Pending Bit 161" "Not pending,Pending" bitfld.long 0x00 0. " SPB160 ,Set Pending Bit 160" "Not pending,Pending" group.long 0x1218++0x03 line.long 0x0 "GICD_ISPR6,Interrupt Set Pending Register 6" bitfld.long 0x00 31. " SPB223 ,Set Pending Bit 223" "Not pending,Pending" bitfld.long 0x00 30. " SPB222 ,Set Pending Bit 222" "Not pending,Pending" bitfld.long 0x00 29. " SPB221 ,Set Pending Bit 221" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB220 ,Set Pending Bit 220" "Not pending,Pending" bitfld.long 0x00 27. " SPB219 ,Set Pending Bit 219" "Not pending,Pending" bitfld.long 0x00 26. " SPB218 ,Set Pending Bit 218" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB217 ,Set Pending Bit 217" "Not pending,Pending" bitfld.long 0x00 24. " SPB216 ,Set Pending Bit 216" "Not pending,Pending" bitfld.long 0x00 23. " SPB215 ,Set Pending Bit 215" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB214 ,Set Pending Bit 214" "Not pending,Pending" bitfld.long 0x00 21. " SPB213 ,Set Pending Bit 213" "Not pending,Pending" bitfld.long 0x00 20. " SPB212 ,Set Pending Bit 212" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB211 ,Set Pending Bit 211" "Not pending,Pending" bitfld.long 0x00 18. " SPB210 ,Set Pending Bit 210" "Not pending,Pending" bitfld.long 0x00 17. " SPB209 ,Set Pending Bit 209" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB208 ,Set Pending Bit 208" "Not pending,Pending" bitfld.long 0x00 15. " SPB207 ,Set Pending Bit 207" "Not pending,Pending" bitfld.long 0x00 14. " SPB206 ,Set Pending Bit 206" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB205 ,Set Pending Bit 205" "Not pending,Pending" bitfld.long 0x00 12. " SPB204 ,Set Pending Bit 204" "Not pending,Pending" bitfld.long 0x00 11. " SPB203 ,Set Pending Bit 203" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB202 ,Set Pending Bit 202" "Not pending,Pending" bitfld.long 0x00 9. " SPB201 ,Set Pending Bit 201" "Not pending,Pending" bitfld.long 0x00 8. " SPB200 ,Set Pending Bit 200" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB199 ,Set Pending Bit 199" "Not pending,Pending" bitfld.long 0x00 6. " SPB198 ,Set Pending Bit 198" "Not pending,Pending" bitfld.long 0x00 5. " SPB197 ,Set Pending Bit 197" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB196 ,Set Pending Bit 196" "Not pending,Pending" bitfld.long 0x00 3. " SPB195 ,Set Pending Bit 195" "Not pending,Pending" bitfld.long 0x00 2. " SPB194 ,Set Pending Bit 194" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB193 ,Set Pending Bit 193" "Not pending,Pending" bitfld.long 0x00 0. " SPB192 ,Set Pending Bit 192" "Not pending,Pending" group.long 0x121C++0x03 line.long 0x0 "GICD_ISPR7,Interrupt Set Pending Register 7" bitfld.long 0x00 31. " SPB255 ,Set Pending Bit 255" "Not pending,Pending" bitfld.long 0x00 30. " SPB254 ,Set Pending Bit 254" "Not pending,Pending" bitfld.long 0x00 29. " SPB253 ,Set Pending Bit 253" "Not pending,Pending" textline " " bitfld.long 0x00 28. " SPB252 ,Set Pending Bit 252" "Not pending,Pending" bitfld.long 0x00 27. " SPB251 ,Set Pending Bit 251" "Not pending,Pending" bitfld.long 0x00 26. " SPB250 ,Set Pending Bit 250" "Not pending,Pending" textline " " bitfld.long 0x00 25. " SPB249 ,Set Pending Bit 249" "Not pending,Pending" bitfld.long 0x00 24. " SPB248 ,Set Pending Bit 248" "Not pending,Pending" bitfld.long 0x00 23. " SPB247 ,Set Pending Bit 247" "Not pending,Pending" textline " " bitfld.long 0x00 22. " SPB246 ,Set Pending Bit 246" "Not pending,Pending" bitfld.long 0x00 21. " SPB245 ,Set Pending Bit 245" "Not pending,Pending" bitfld.long 0x00 20. " SPB244 ,Set Pending Bit 244" "Not pending,Pending" textline " " bitfld.long 0x00 19. " SPB243 ,Set Pending Bit 243" "Not pending,Pending" bitfld.long 0x00 18. " SPB242 ,Set Pending Bit 242" "Not pending,Pending" bitfld.long 0x00 17. " SPB241 ,Set Pending Bit 241" "Not pending,Pending" textline " " bitfld.long 0x00 16. " SPB240 ,Set Pending Bit 240" "Not pending,Pending" bitfld.long 0x00 15. " SPB239 ,Set Pending Bit 239" "Not pending,Pending" bitfld.long 0x00 14. " SPB238 ,Set Pending Bit 238" "Not pending,Pending" textline " " bitfld.long 0x00 13. " SPB237 ,Set Pending Bit 237" "Not pending,Pending" bitfld.long 0x00 12. " SPB236 ,Set Pending Bit 236" "Not pending,Pending" bitfld.long 0x00 11. " SPB235 ,Set Pending Bit 235" "Not pending,Pending" textline " " bitfld.long 0x00 10. " SPB234 ,Set Pending Bit 234" "Not pending,Pending" bitfld.long 0x00 9. " SPB233 ,Set Pending Bit 233" "Not pending,Pending" bitfld.long 0x00 8. " SPB232 ,Set Pending Bit 232" "Not pending,Pending" textline " " bitfld.long 0x00 7. " SPB231 ,Set Pending Bit 231" "Not pending,Pending" bitfld.long 0x00 6. " SPB230 ,Set Pending Bit 230" "Not pending,Pending" bitfld.long 0x00 5. " SPB229 ,Set Pending Bit 229" "Not pending,Pending" textline " " bitfld.long 0x00 4. " SPB228 ,Set Pending Bit 228" "Not pending,Pending" bitfld.long 0x00 3. " SPB227 ,Set Pending Bit 227" "Not pending,Pending" bitfld.long 0x00 2. " SPB226 ,Set Pending Bit 226" "Not pending,Pending" textline " " bitfld.long 0x00 1. " SPB225 ,Set Pending Bit 225" "Not pending,Pending" bitfld.long 0x00 0. " SPB224 ,Set Pending Bit 224" "Not pending,Pending" textline " " tree.end tree "Clear-Pending Registers" group.long 0x1280++0x03 line.long 0x0 "GICD_ICPR0,Interrupt Clear Pending Register 0" eventfld.long 0x00 31. " CPB31 ,Clear Pending Bit 31" "Not pending,Pending" eventfld.long 0x00 30. " CPB30 ,Clear Pending Bit 30" "Not pending,Pending" eventfld.long 0x00 29. " CPB29 ,Clear Pending Bit 29" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB28 ,Clear Pending Bit 28" "Not pending,Pending" eventfld.long 0x00 27. " CPB27 ,Clear Pending Bit 27" "Not pending,Pending" eventfld.long 0x00 26. " CPB26 ,Clear Pending Bit 26" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB25 ,Clear Pending Bit 25" "Not pending,Pending" eventfld.long 0x00 24. " CPB24 ,Clear Pending Bit 24" "Not pending,Pending" eventfld.long 0x00 23. " CPB23 ,Clear Pending Bit 23" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB22 ,Clear Pending Bit 22" "Not pending,Pending" eventfld.long 0x00 21. " CPB21 ,Clear Pending Bit 21" "Not pending,Pending" eventfld.long 0x00 20. " CPB20 ,Clear Pending Bit 20" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB19 ,Clear Pending Bit 19" "Not pending,Pending" eventfld.long 0x00 18. " CPB18 ,Clear Pending Bit 18" "Not pending,Pending" eventfld.long 0x00 17. " CPB17 ,Clear Pending Bit 17" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB16 ,Clear Pending Bit 16" "Not pending,Pending" eventfld.long 0x00 15. " CPB15 ,Clear Pending Bit 15" "Not pending,Pending" eventfld.long 0x00 14. " CPB14 ,Clear Pending Bit 14" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB13 ,Clear Pending Bit 13" "Not pending,Pending" eventfld.long 0x00 12. " CPB12 ,Clear Pending Bit 12" "Not pending,Pending" eventfld.long 0x00 11. " CPB11 ,Clear Pending Bit 11" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB10 ,Clear Pending Bit 10" "Not pending,Pending" eventfld.long 0x00 9. " CPB9 ,Clear Pending Bit 9" "Not pending,Pending" eventfld.long 0x00 8. " CPB8 ,Clear Pending Bit 8" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB7 ,Clear Pending Bit 7" "Not pending,Pending" eventfld.long 0x00 6. " CPB6 ,Clear Pending Bit 6" "Not pending,Pending" eventfld.long 0x00 5. " CPB5 ,Clear Pending Bit 5" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB4 ,Clear Pending Bit 4" "Not pending,Pending" eventfld.long 0x00 3. " CPB3 ,Clear Pending Bit 3" "Not pending,Pending" eventfld.long 0x00 2. " CPB2 ,Clear Pending Bit 2" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB1 ,Clear Pending Bit 1" "Not pending,Pending" eventfld.long 0x00 0. " CPB0 ,Clear Pending Bit 0" "Not pending,Pending" group.long 0x1284++0x03 line.long 0x0 "GICD_ICPR1,Interrupt Clear Pending Register 1" eventfld.long 0x00 31. " CPB63 ,Clear Pending Bit 63" "Not pending,Pending" eventfld.long 0x00 30. " CPB62 ,Clear Pending Bit 62" "Not pending,Pending" eventfld.long 0x00 29. " CPB61 ,Clear Pending Bit 61" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB60 ,Clear Pending Bit 60" "Not pending,Pending" eventfld.long 0x00 27. " CPB59 ,Clear Pending Bit 59" "Not pending,Pending" eventfld.long 0x00 26. " CPB58 ,Clear Pending Bit 58" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB57 ,Clear Pending Bit 57" "Not pending,Pending" eventfld.long 0x00 24. " CPB56 ,Clear Pending Bit 56" "Not pending,Pending" eventfld.long 0x00 23. " CPB55 ,Clear Pending Bit 55" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB54 ,Clear Pending Bit 54" "Not pending,Pending" eventfld.long 0x00 21. " CPB53 ,Clear Pending Bit 53" "Not pending,Pending" eventfld.long 0x00 20. " CPB52 ,Clear Pending Bit 52" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB51 ,Clear Pending Bit 51" "Not pending,Pending" eventfld.long 0x00 18. " CPB50 ,Clear Pending Bit 50" "Not pending,Pending" eventfld.long 0x00 17. " CPB49 ,Clear Pending Bit 49" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB48 ,Clear Pending Bit 48" "Not pending,Pending" eventfld.long 0x00 15. " CPB47 ,Clear Pending Bit 47" "Not pending,Pending" eventfld.long 0x00 14. " CPB46 ,Clear Pending Bit 46" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB45 ,Clear Pending Bit 45" "Not pending,Pending" eventfld.long 0x00 12. " CPB44 ,Clear Pending Bit 44" "Not pending,Pending" eventfld.long 0x00 11. " CPB43 ,Clear Pending Bit 43" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB42 ,Clear Pending Bit 42" "Not pending,Pending" eventfld.long 0x00 9. " CPB41 ,Clear Pending Bit 41" "Not pending,Pending" eventfld.long 0x00 8. " CPB40 ,Clear Pending Bit 40" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB39 ,Clear Pending Bit 39" "Not pending,Pending" eventfld.long 0x00 6. " CPB38 ,Clear Pending Bit 38" "Not pending,Pending" eventfld.long 0x00 5. " CPB37 ,Clear Pending Bit 37" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB36 ,Clear Pending Bit 36" "Not pending,Pending" eventfld.long 0x00 3. " CPB35 ,Clear Pending Bit 35" "Not pending,Pending" eventfld.long 0x00 2. " CPB34 ,Clear Pending Bit 34" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB33 ,Clear Pending Bit 33" "Not pending,Pending" eventfld.long 0x00 0. " CPB32 ,Clear Pending Bit 32" "Not pending,Pending" group.long 0x1288++0x03 line.long 0x0 "GICD_ICPR2,Interrupt Clear Pending Register 2" eventfld.long 0x00 31. " CPB95 ,Clear Pending Bit 95" "Not pending,Pending" eventfld.long 0x00 30. " CPB94 ,Clear Pending Bit 94" "Not pending,Pending" eventfld.long 0x00 29. " CPB93 ,Clear Pending Bit 93" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB92 ,Clear Pending Bit 92" "Not pending,Pending" eventfld.long 0x00 27. " CPB91 ,Clear Pending Bit 91" "Not pending,Pending" eventfld.long 0x00 26. " CPB90 ,Clear Pending Bit 90" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB89 ,Clear Pending Bit 89" "Not pending,Pending" eventfld.long 0x00 24. " CPB88 ,Clear Pending Bit 88" "Not pending,Pending" eventfld.long 0x00 23. " CPB87 ,Clear Pending Bit 87" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB86 ,Clear Pending Bit 86" "Not pending,Pending" eventfld.long 0x00 21. " CPB85 ,Clear Pending Bit 85" "Not pending,Pending" eventfld.long 0x00 20. " CPB84 ,Clear Pending Bit 84" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB83 ,Clear Pending Bit 83" "Not pending,Pending" eventfld.long 0x00 18. " CPB82 ,Clear Pending Bit 82" "Not pending,Pending" eventfld.long 0x00 17. " CPB81 ,Clear Pending Bit 81" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB80 ,Clear Pending Bit 80" "Not pending,Pending" eventfld.long 0x00 15. " CPB79 ,Clear Pending Bit 79" "Not pending,Pending" eventfld.long 0x00 14. " CPB78 ,Clear Pending Bit 78" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB77 ,Clear Pending Bit 77" "Not pending,Pending" eventfld.long 0x00 12. " CPB76 ,Clear Pending Bit 76" "Not pending,Pending" eventfld.long 0x00 11. " CPB75 ,Clear Pending Bit 75" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB74 ,Clear Pending Bit 74" "Not pending,Pending" eventfld.long 0x00 9. " CPB73 ,Clear Pending Bit 73" "Not pending,Pending" eventfld.long 0x00 8. " CPB72 ,Clear Pending Bit 72" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB71 ,Clear Pending Bit 71" "Not pending,Pending" eventfld.long 0x00 6. " CPB70 ,Clear Pending Bit 70" "Not pending,Pending" eventfld.long 0x00 5. " CPB69 ,Clear Pending Bit 69" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB68 ,Clear Pending Bit 68" "Not pending,Pending" eventfld.long 0x00 3. " CPB67 ,Clear Pending Bit 67" "Not pending,Pending" eventfld.long 0x00 2. " CPB66 ,Clear Pending Bit 66" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB65 ,Clear Pending Bit 65" "Not pending,Pending" eventfld.long 0x00 0. " CPB64 ,Clear Pending Bit 64" "Not pending,Pending" group.long 0x128C++0x03 line.long 0x0 "GICD_ICPR3,Interrupt Clear Pending Register 3" eventfld.long 0x00 31. " CPB127 ,Clear Pending Bit 127" "Not pending,Pending" eventfld.long 0x00 30. " CPB126 ,Clear Pending Bit 126" "Not pending,Pending" eventfld.long 0x00 29. " CPB125 ,Clear Pending Bit 125" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB124 ,Clear Pending Bit 124" "Not pending,Pending" eventfld.long 0x00 27. " CPB123 ,Clear Pending Bit 123" "Not pending,Pending" eventfld.long 0x00 26. " CPB122 ,Clear Pending Bit 122" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB121 ,Clear Pending Bit 121" "Not pending,Pending" eventfld.long 0x00 24. " CPB120 ,Clear Pending Bit 120" "Not pending,Pending" eventfld.long 0x00 23. " CPB119 ,Clear Pending Bit 119" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB118 ,Clear Pending Bit 118" "Not pending,Pending" eventfld.long 0x00 21. " CPB117 ,Clear Pending Bit 117" "Not pending,Pending" eventfld.long 0x00 20. " CPB116 ,Clear Pending Bit 116" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB115 ,Clear Pending Bit 115" "Not pending,Pending" eventfld.long 0x00 18. " CPB114 ,Clear Pending Bit 114" "Not pending,Pending" eventfld.long 0x00 17. " CPB113 ,Clear Pending Bit 113" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB112 ,Clear Pending Bit 112" "Not pending,Pending" eventfld.long 0x00 15. " CPB111 ,Clear Pending Bit 111" "Not pending,Pending" eventfld.long 0x00 14. " CPB110 ,Clear Pending Bit 110" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB109 ,Clear Pending Bit 109" "Not pending,Pending" eventfld.long 0x00 12. " CPB108 ,Clear Pending Bit 108" "Not pending,Pending" eventfld.long 0x00 11. " CPB107 ,Clear Pending Bit 107" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB106 ,Clear Pending Bit 106" "Not pending,Pending" eventfld.long 0x00 9. " CPB105 ,Clear Pending Bit 105" "Not pending,Pending" eventfld.long 0x00 8. " CPB104 ,Clear Pending Bit 104" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB103 ,Clear Pending Bit 103" "Not pending,Pending" eventfld.long 0x00 6. " CPB102 ,Clear Pending Bit 102" "Not pending,Pending" eventfld.long 0x00 5. " CPB101 ,Clear Pending Bit 101" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB100 ,Clear Pending Bit 100" "Not pending,Pending" eventfld.long 0x00 3. " CPB99 ,Clear Pending Bit 99" "Not pending,Pending" eventfld.long 0x00 2. " CPB98 ,Clear Pending Bit 98" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB97 ,Clear Pending Bit 97" "Not pending,Pending" eventfld.long 0x00 0. " CPB96 ,Clear Pending Bit 96" "Not pending,Pending" group.long 0x1290++0x03 line.long 0x0 "GICD_ICPR4,Interrupt Clear Pending Register 4" eventfld.long 0x00 31. " CPB159 ,Clear Pending Bit 159" "Not pending,Pending" eventfld.long 0x00 30. " CPB158 ,Clear Pending Bit 158" "Not pending,Pending" eventfld.long 0x00 29. " CPB157 ,Clear Pending Bit 157" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB156 ,Clear Pending Bit 156" "Not pending,Pending" eventfld.long 0x00 27. " CPB155 ,Clear Pending Bit 155" "Not pending,Pending" eventfld.long 0x00 26. " CPB154 ,Clear Pending Bit 154" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB153 ,Clear Pending Bit 153" "Not pending,Pending" eventfld.long 0x00 24. " CPB152 ,Clear Pending Bit 152" "Not pending,Pending" eventfld.long 0x00 23. " CPB151 ,Clear Pending Bit 151" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB150 ,Clear Pending Bit 150" "Not pending,Pending" eventfld.long 0x00 21. " CPB149 ,Clear Pending Bit 149" "Not pending,Pending" eventfld.long 0x00 20. " CPB148 ,Clear Pending Bit 148" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB147 ,Clear Pending Bit 147" "Not pending,Pending" eventfld.long 0x00 18. " CPB146 ,Clear Pending Bit 146" "Not pending,Pending" eventfld.long 0x00 17. " CPB145 ,Clear Pending Bit 145" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB144 ,Clear Pending Bit 144" "Not pending,Pending" eventfld.long 0x00 15. " CPB143 ,Clear Pending Bit 143" "Not pending,Pending" eventfld.long 0x00 14. " CPB142 ,Clear Pending Bit 142" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB141 ,Clear Pending Bit 141" "Not pending,Pending" eventfld.long 0x00 12. " CPB140 ,Clear Pending Bit 140" "Not pending,Pending" eventfld.long 0x00 11. " CPB139 ,Clear Pending Bit 139" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB138 ,Clear Pending Bit 138" "Not pending,Pending" eventfld.long 0x00 9. " CPB137 ,Clear Pending Bit 137" "Not pending,Pending" eventfld.long 0x00 8. " CPB136 ,Clear Pending Bit 136" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB135 ,Clear Pending Bit 135" "Not pending,Pending" eventfld.long 0x00 6. " CPB134 ,Clear Pending Bit 134" "Not pending,Pending" eventfld.long 0x00 5. " CPB133 ,Clear Pending Bit 133" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB132 ,Clear Pending Bit 132" "Not pending,Pending" eventfld.long 0x00 3. " CPB131 ,Clear Pending Bit 131" "Not pending,Pending" eventfld.long 0x00 2. " CPB130 ,Clear Pending Bit 130" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB129 ,Clear Pending Bit 129" "Not pending,Pending" eventfld.long 0x00 0. " CPB128 ,Clear Pending Bit 128" "Not pending,Pending" group.long 0x1294++0x03 line.long 0x0 "GICD_ICPR5,Interrupt Clear Pending Register 5" eventfld.long 0x00 31. " CPB191 ,Clear Pending Bit 191" "Not pending,Pending" eventfld.long 0x00 30. " CPB190 ,Clear Pending Bit 190" "Not pending,Pending" eventfld.long 0x00 29. " CPB189 ,Clear Pending Bit 189" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB188 ,Clear Pending Bit 188" "Not pending,Pending" eventfld.long 0x00 27. " CPB187 ,Clear Pending Bit 187" "Not pending,Pending" eventfld.long 0x00 26. " CPB186 ,Clear Pending Bit 186" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB185 ,Clear Pending Bit 185" "Not pending,Pending" eventfld.long 0x00 24. " CPB184 ,Clear Pending Bit 184" "Not pending,Pending" eventfld.long 0x00 23. " CPB183 ,Clear Pending Bit 183" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB182 ,Clear Pending Bit 182" "Not pending,Pending" eventfld.long 0x00 21. " CPB181 ,Clear Pending Bit 181" "Not pending,Pending" eventfld.long 0x00 20. " CPB180 ,Clear Pending Bit 180" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB179 ,Clear Pending Bit 179" "Not pending,Pending" eventfld.long 0x00 18. " CPB178 ,Clear Pending Bit 178" "Not pending,Pending" eventfld.long 0x00 17. " CPB177 ,Clear Pending Bit 177" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB176 ,Clear Pending Bit 176" "Not pending,Pending" eventfld.long 0x00 15. " CPB175 ,Clear Pending Bit 175" "Not pending,Pending" eventfld.long 0x00 14. " CPB174 ,Clear Pending Bit 174" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB173 ,Clear Pending Bit 173" "Not pending,Pending" eventfld.long 0x00 12. " CPB172 ,Clear Pending Bit 172" "Not pending,Pending" eventfld.long 0x00 11. " CPB171 ,Clear Pending Bit 171" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB170 ,Clear Pending Bit 170" "Not pending,Pending" eventfld.long 0x00 9. " CPB169 ,Clear Pending Bit 169" "Not pending,Pending" eventfld.long 0x00 8. " CPB168 ,Clear Pending Bit 168" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB167 ,Clear Pending Bit 167" "Not pending,Pending" eventfld.long 0x00 6. " CPB166 ,Clear Pending Bit 166" "Not pending,Pending" eventfld.long 0x00 5. " CPB165 ,Clear Pending Bit 165" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB164 ,Clear Pending Bit 164" "Not pending,Pending" eventfld.long 0x00 3. " CPB163 ,Clear Pending Bit 163" "Not pending,Pending" eventfld.long 0x00 2. " CPB162 ,Clear Pending Bit 162" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB161 ,Clear Pending Bit 161" "Not pending,Pending" eventfld.long 0x00 0. " CPB160 ,Clear Pending Bit 160" "Not pending,Pending" group.long 0x1298++0x03 line.long 0x0 "GICD_ICPR6,Interrupt Clear Pending Register 6" eventfld.long 0x00 31. " CPB223 ,Clear Pending Bit 223" "Not pending,Pending" eventfld.long 0x00 30. " CPB222 ,Clear Pending Bit 222" "Not pending,Pending" eventfld.long 0x00 29. " CPB221 ,Clear Pending Bit 221" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB220 ,Clear Pending Bit 220" "Not pending,Pending" eventfld.long 0x00 27. " CPB219 ,Clear Pending Bit 219" "Not pending,Pending" eventfld.long 0x00 26. " CPB218 ,Clear Pending Bit 218" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB217 ,Clear Pending Bit 217" "Not pending,Pending" eventfld.long 0x00 24. " CPB216 ,Clear Pending Bit 216" "Not pending,Pending" eventfld.long 0x00 23. " CPB215 ,Clear Pending Bit 215" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB214 ,Clear Pending Bit 214" "Not pending,Pending" eventfld.long 0x00 21. " CPB213 ,Clear Pending Bit 213" "Not pending,Pending" eventfld.long 0x00 20. " CPB212 ,Clear Pending Bit 212" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB211 ,Clear Pending Bit 211" "Not pending,Pending" eventfld.long 0x00 18. " CPB210 ,Clear Pending Bit 210" "Not pending,Pending" eventfld.long 0x00 17. " CPB209 ,Clear Pending Bit 209" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB208 ,Clear Pending Bit 208" "Not pending,Pending" eventfld.long 0x00 15. " CPB207 ,Clear Pending Bit 207" "Not pending,Pending" eventfld.long 0x00 14. " CPB206 ,Clear Pending Bit 206" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB205 ,Clear Pending Bit 205" "Not pending,Pending" eventfld.long 0x00 12. " CPB204 ,Clear Pending Bit 204" "Not pending,Pending" eventfld.long 0x00 11. " CPB203 ,Clear Pending Bit 203" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB202 ,Clear Pending Bit 202" "Not pending,Pending" eventfld.long 0x00 9. " CPB201 ,Clear Pending Bit 201" "Not pending,Pending" eventfld.long 0x00 8. " CPB200 ,Clear Pending Bit 200" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB199 ,Clear Pending Bit 199" "Not pending,Pending" eventfld.long 0x00 6. " CPB198 ,Clear Pending Bit 198" "Not pending,Pending" eventfld.long 0x00 5. " CPB197 ,Clear Pending Bit 197" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB196 ,Clear Pending Bit 196" "Not pending,Pending" eventfld.long 0x00 3. " CPB195 ,Clear Pending Bit 195" "Not pending,Pending" eventfld.long 0x00 2. " CPB194 ,Clear Pending Bit 194" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB193 ,Clear Pending Bit 193" "Not pending,Pending" eventfld.long 0x00 0. " CPB192 ,Clear Pending Bit 192" "Not pending,Pending" group.long 0x129C++0x03 line.long 0x0 "GICD_ICPR7,Interrupt Clear Pending Register 7" eventfld.long 0x00 31. " CPB255 ,Clear Pending Bit 255" "Not pending,Pending" eventfld.long 0x00 30. " CPB254 ,Clear Pending Bit 254" "Not pending,Pending" eventfld.long 0x00 29. " CPB253 ,Clear Pending Bit 253" "Not pending,Pending" textline " " eventfld.long 0x00 28. " CPB252 ,Clear Pending Bit 252" "Not pending,Pending" eventfld.long 0x00 27. " CPB251 ,Clear Pending Bit 251" "Not pending,Pending" eventfld.long 0x00 26. " CPB250 ,Clear Pending Bit 250" "Not pending,Pending" textline " " eventfld.long 0x00 25. " CPB249 ,Clear Pending Bit 249" "Not pending,Pending" eventfld.long 0x00 24. " CPB248 ,Clear Pending Bit 248" "Not pending,Pending" eventfld.long 0x00 23. " CPB247 ,Clear Pending Bit 247" "Not pending,Pending" textline " " eventfld.long 0x00 22. " CPB246 ,Clear Pending Bit 246" "Not pending,Pending" eventfld.long 0x00 21. " CPB245 ,Clear Pending Bit 245" "Not pending,Pending" eventfld.long 0x00 20. " CPB244 ,Clear Pending Bit 244" "Not pending,Pending" textline " " eventfld.long 0x00 19. " CPB243 ,Clear Pending Bit 243" "Not pending,Pending" eventfld.long 0x00 18. " CPB242 ,Clear Pending Bit 242" "Not pending,Pending" eventfld.long 0x00 17. " CPB241 ,Clear Pending Bit 241" "Not pending,Pending" textline " " eventfld.long 0x00 16. " CPB240 ,Clear Pending Bit 240" "Not pending,Pending" eventfld.long 0x00 15. " CPB239 ,Clear Pending Bit 239" "Not pending,Pending" eventfld.long 0x00 14. " CPB238 ,Clear Pending Bit 238" "Not pending,Pending" textline " " eventfld.long 0x00 13. " CPB237 ,Clear Pending Bit 237" "Not pending,Pending" eventfld.long 0x00 12. " CPB236 ,Clear Pending Bit 236" "Not pending,Pending" eventfld.long 0x00 11. " CPB235 ,Clear Pending Bit 235" "Not pending,Pending" textline " " eventfld.long 0x00 10. " CPB234 ,Clear Pending Bit 234" "Not pending,Pending" eventfld.long 0x00 9. " CPB233 ,Clear Pending Bit 233" "Not pending,Pending" eventfld.long 0x00 8. " CPB232 ,Clear Pending Bit 232" "Not pending,Pending" textline " " eventfld.long 0x00 7. " CPB231 ,Clear Pending Bit 231" "Not pending,Pending" eventfld.long 0x00 6. " CPB230 ,Clear Pending Bit 230" "Not pending,Pending" eventfld.long 0x00 5. " CPB229 ,Clear Pending Bit 229" "Not pending,Pending" textline " " eventfld.long 0x00 4. " CPB228 ,Clear Pending Bit 228" "Not pending,Pending" eventfld.long 0x00 3. " CPB227 ,Clear Pending Bit 227" "Not pending,Pending" eventfld.long 0x00 2. " CPB226 ,Clear Pending Bit 226" "Not pending,Pending" textline " " eventfld.long 0x00 1. " CPB225 ,Clear Pending Bit 225" "Not pending,Pending" eventfld.long 0x00 0. " CPB224 ,Clear Pending Bit 224" "Not pending,Pending" textline " " tree.end tree "Set/Clear Active Registers" group.long 0x1300++0x03 line.long 0x0 "GICD_ISACTIVER0,Interrupt Set Active Register 0" group.long 0x1304++0x03 line.long 0x0 "GICD_ISACTIVER1,Interrupt Set Active Register 1" group.long 0x1308++0x03 line.long 0x0 "GICD_ISACTIVER2,Interrupt Set Active Register 2" group.long 0x130C++0x03 line.long 0x0 "GICD_ISACTIVER3,Interrupt Set Active Register 3" group.long 0x1310++0x03 line.long 0x0 "GICD_ISACTIVER4,Interrupt Set Active Register 4" group.long 0x1314++0x03 line.long 0x0 "GICD_ISACTIVER5,Interrupt Set Active Register 5" group.long 0x1318++0x03 line.long 0x0 "GICD_ISACTIVER6,Interrupt Set Active Register 6" group.long 0x131C++0x03 line.long 0x0 "GICD_ISACTIVER7,Interrupt Set Active Register 7" textline " " group.long 0x1380++0x03 line.long 0x0 "GICD_ICACTIVER0,Interrupt Clear Active Register 0" group.long 0x1384++0x03 line.long 0x0 "GICD_ICACTIVER1,Interrupt Clear Active Register 1" group.long 0x1388++0x03 line.long 0x0 "GICD_ICACTIVER2,Interrupt Clear Active Register 2" group.long 0x138C++0x03 line.long 0x0 "GICD_ICACTIVER3,Interrupt Clear Active Register 3" group.long 0x1390++0x03 line.long 0x0 "GICD_ICACTIVER4,Interrupt Clear Active Register 4" group.long 0x1394++0x03 line.long 0x0 "GICD_ICACTIVER5,Interrupt Clear Active Register 5" group.long 0x1398++0x03 line.long 0x0 "GICD_ICACTIVER6,Interrupt Clear Active Register 6" group.long 0x139C++0x03 line.long 0x0 "GICD_ICACTIVER7,Interrupt Clear Active Register 7" textline " " tree.end tree "Priority Registers" group.long 0x1400++0x03 line.long 0x0 "GICD_IPR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1404++0x03 line.long 0x0 "GICD_IPR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1408++0x03 line.long 0x0 "GICD_IPR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x140C++0x03 line.long 0x0 "GICD_IPR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1410++0x03 line.long 0x0 "GICD_IPR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1414++0x03 line.long 0x0 "GICD_IPR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1418++0x03 line.long 0x0 "GICD_IPR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x141C++0x03 line.long 0x0 "GICD_IPR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1420++0x03 line.long 0x0 "GICD_IPR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1424++0x03 line.long 0x0 "GICD_IPR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1428++0x03 line.long 0x0 "GICD_IPR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x142C++0x03 line.long 0x0 "GICD_IPR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1430++0x03 line.long 0x0 "GICD_IPR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1434++0x03 line.long 0x0 "GICD_IPR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1438++0x03 line.long 0x0 "GICD_IPR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x143C++0x03 line.long 0x0 "GICD_IPR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1440++0x03 line.long 0x0 "GICD_IPR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1444++0x03 line.long 0x0 "GICD_IPR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1448++0x03 line.long 0x0 "GICD_IPR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x144C++0x03 line.long 0x0 "GICD_IPR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1450++0x03 line.long 0x0 "GICD_IPR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1454++0x03 line.long 0x0 "GICD_IPR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1458++0x03 line.long 0x0 "GICD_IPR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x145C++0x03 line.long 0x0 "GICD_IPR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1460++0x03 line.long 0x0 "GICD_IPR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1464++0x03 line.long 0x0 "GICD_IPR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1468++0x03 line.long 0x0 "GICD_IPR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x146C++0x03 line.long 0x0 "GICD_IPR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1470++0x03 line.long 0x0 "GICD_IPR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1474++0x03 line.long 0x0 "GICD_IPR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1478++0x03 line.long 0x0 "GICD_IPR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x147C++0x03 line.long 0x0 "GICD_IPR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1480++0x03 line.long 0x0 "GICD_IPR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1484++0x03 line.long 0x0 "GICD_IPR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1488++0x03 line.long 0x0 "GICD_IPR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x148C++0x03 line.long 0x0 "GICD_IPR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1490++0x03 line.long 0x0 "GICD_IPR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1494++0x03 line.long 0x0 "GICD_IPR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x1498++0x03 line.long 0x0 "GICD_IPR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x149C++0x03 line.long 0x0 "GICD_IPR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14A0++0x03 line.long 0x0 "GICD_IPR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14A4++0x03 line.long 0x0 "GICD_IPR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14A8++0x03 line.long 0x0 "GICD_IPR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14AC++0x03 line.long 0x0 "GICD_IPR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14B0++0x03 line.long 0x0 "GICD_IPR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14B4++0x03 line.long 0x0 "GICD_IPR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14B8++0x03 line.long 0x0 "GICD_IPR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14BC++0x03 line.long 0x0 "GICD_IPR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14C0++0x03 line.long 0x0 "GICD_IPR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14C4++0x03 line.long 0x0 "GICD_IPR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14C8++0x03 line.long 0x0 "GICD_IPR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14CC++0x03 line.long 0x0 "GICD_IPR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14D0++0x03 line.long 0x0 "GICD_IPR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14D4++0x03 line.long 0x0 "GICD_IPR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14D8++0x03 line.long 0x0 "GICD_IPR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14DC++0x03 line.long 0x0 "GICD_IPR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14E0++0x03 line.long 0x0 "GICD_IPR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14E4++0x03 line.long 0x0 "GICD_IPR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14E8++0x03 line.long 0x0 "GICD_IPR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14EC++0x03 line.long 0x0 "GICD_IPR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14F0++0x03 line.long 0x0 "GICD_IPR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14F4++0x03 line.long 0x0 "GICD_IPR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14F8++0x03 line.long 0x0 "GICD_IPR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" group.long 0x14FC++0x03 line.long 0x0 "GICD_IPR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " PBO3 ,Priority Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " PBO2 ,Priority Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " PBO1 ,Priority Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " PBO0 ,Priority Byte Offset 0" textline " " tree.end tree "Processor Targets Registers" rgroup.long 0x1800++0x03 line.long 0x0 "GICD_IPTR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x1804++0x03 line.long 0x0 "GICD_IPTR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x1808++0x03 line.long 0x0 "GICD_IPTR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x180C++0x03 line.long 0x0 "GICD_IPTR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x1810++0x03 line.long 0x0 "GICD_IPTR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x1814++0x03 line.long 0x0 "GICD_IPTR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x1818++0x03 line.long 0x0 "GICD_IPTR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" rgroup.long 0x181C++0x03 line.long 0x0 "GICD_IPTR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1820++0x03 line.long 0x0 "GICD_IPTR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1824++0x03 line.long 0x0 "GICD_IPTR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1828++0x03 line.long 0x0 "GICD_IPTR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x182C++0x03 line.long 0x0 "GICD_IPTR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1830++0x03 line.long 0x0 "GICD_IPTR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1834++0x03 line.long 0x0 "GICD_IPTR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1838++0x03 line.long 0x0 "GICD_IPTR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x183C++0x03 line.long 0x0 "GICD_IPTR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1840++0x03 line.long 0x0 "GICD_IPTR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1844++0x03 line.long 0x0 "GICD_IPTR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1848++0x03 line.long 0x0 "GICD_IPTR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x184C++0x03 line.long 0x0 "GICD_IPTR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1850++0x03 line.long 0x0 "GICD_IPTR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1854++0x03 line.long 0x0 "GICD_IPTR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1858++0x03 line.long 0x0 "GICD_IPTR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x185C++0x03 line.long 0x0 "GICD_IPTR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1860++0x03 line.long 0x0 "GICD_IPTR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1864++0x03 line.long 0x0 "GICD_IPTR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1868++0x03 line.long 0x0 "GICD_IPTR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x186C++0x03 line.long 0x0 "GICD_IPTR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1870++0x03 line.long 0x0 "GICD_IPTR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1874++0x03 line.long 0x0 "GICD_IPTR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1878++0x03 line.long 0x0 "GICD_IPTR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x187C++0x03 line.long 0x0 "GICD_IPTR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1880++0x03 line.long 0x0 "GICD_IPTR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1884++0x03 line.long 0x0 "GICD_IPTR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1888++0x03 line.long 0x0 "GICD_IPTR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x188C++0x03 line.long 0x0 "GICD_IPTR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1890++0x03 line.long 0x0 "GICD_IPTR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1894++0x03 line.long 0x0 "GICD_IPTR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x1898++0x03 line.long 0x0 "GICD_IPTR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x189C++0x03 line.long 0x0 "GICD_IPTR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18A0++0x03 line.long 0x0 "GICD_IPTR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18A4++0x03 line.long 0x0 "GICD_IPTR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18A8++0x03 line.long 0x0 "GICD_IPTR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18AC++0x03 line.long 0x0 "GICD_IPTR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18B0++0x03 line.long 0x0 "GICD_IPTR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18B4++0x03 line.long 0x0 "GICD_IPTR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18B8++0x03 line.long 0x0 "GICD_IPTR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18BC++0x03 line.long 0x0 "GICD_IPTR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18C0++0x03 line.long 0x0 "GICD_IPTR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18C4++0x03 line.long 0x0 "GICD_IPTR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18C8++0x03 line.long 0x0 "GICD_IPTR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18CC++0x03 line.long 0x0 "GICD_IPTR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18D0++0x03 line.long 0x0 "GICD_IPTR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18D4++0x03 line.long 0x0 "GICD_IPTR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18D8++0x03 line.long 0x0 "GICD_IPTR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18DC++0x03 line.long 0x0 "GICD_IPTR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18E0++0x03 line.long 0x0 "GICD_IPTR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18E4++0x03 line.long 0x0 "GICD_IPTR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18E8++0x03 line.long 0x0 "GICD_IPTR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18EC++0x03 line.long 0x0 "GICD_IPTR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18F0++0x03 line.long 0x0 "GICD_IPTR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18F4++0x03 line.long 0x0 "GICD_IPTR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18F8++0x03 line.long 0x0 "GICD_IPTR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" group.long 0x18FC++0x03 line.long 0x0 "GICD_IPTR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0" textline " " tree.end tree "Configuration Registers" rgroup.long 0x1C00++0x03 line.long 0x00 "GICD_ICFR0,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" rgroup.long 0x1C04++0x03 line.long 0x00 "GICD_ICFR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C08++0x03 line.long 0x00 "GICD_ICFR2,Interrupt Configuration Register 0x1C08" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C0C++0x03 line.long 0x00 "GICD_ICFR3,Interrupt Configuration Register 0x1C0C" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C10++0x03 line.long 0x00 "GICD_ICFR4,Interrupt Configuration Register 0x1C10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C14++0x03 line.long 0x00 "GICD_ICFR5,Interrupt Configuration Register 0x1C14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C18++0x03 line.long 0x00 "GICD_ICFR6,Interrupt Configuration Register 0x1C18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C1C++0x03 line.long 0x00 "GICD_ICFR7,Interrupt Configuration Register 0x1C1C" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C20++0x03 line.long 0x00 "GICD_ICFR8,Interrupt Configuration Register 0x1C20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C24++0x03 line.long 0x00 "GICD_ICFR9,Interrupt Configuration Register 0x1C24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C28++0x03 line.long 0x00 "GICD_ICFR10,Interrupt Configuration Register 0x1C28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C2C++0x03 line.long 0x00 "GICD_ICFR11,Interrupt Configuration Register 0x1C2C" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C30++0x03 line.long 0x00 "GICD_ICFR12,Interrupt Configuration Register 0x1C30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C34++0x03 line.long 0x00 "GICD_ICFR13,Interrupt Configuration Register 0x1C34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C38++0x03 line.long 0x00 "GICD_ICFR14,Interrupt Configuration Register 0x1C38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " group.long 0x1C3C++0x03 line.long 0x00 "GICD_ICFR15,Interrupt Configuration Register 0x1C3C" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Edge,Level" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Edge,Level" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Edge,Level" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Edge,Level" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Edge,Level" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Edge,Level" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Edge,Level" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Edge,Level" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Edge,Level" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Edge,Level" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Edge,Level" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Edge,Level" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Edge,Level" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Edge,Level" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Edge,Level" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Edge,Level" textline " " tree.end width 17. tree "Private/Shared Peripheral Interrupt Status Registers" rgroup.long 0x1D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI3S ,nIRQ pin status" "No interrupt,Interrupt" bitfld.long 0x00 14. " PPI2S ,Non-secure Physical Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " PPI1S ,Secure Physical Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 12. " PPI0S ,nFIQ pin status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PPI4S ,Virtual Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 10. " PPI5S ,Hypervisor Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " PPI6S ,Virtual Maintenance Status" "No interrupt,Interrupt" rgroup.long 0x1D04++0x03 line.long 0x00 "GICD_SPISR0,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[31] ,IRQS[31] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[30] ,IRQS[30] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[29] ,IRQS[29] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[28] ,IRQS[28] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[27] ,IRQS[27] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[26] ,IRQS[26] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[25] ,IRQS[25] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[24] ,IRQS[24] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[23] ,IRQS[23] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[22] ,IRQS[22] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[21] ,IRQS[21] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[20] ,IRQS[20] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[19] ,IRQS[19] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[18] ,IRQS[18] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[17] ,IRQS[17] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[16] ,IRQS[16] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[15] ,IRQS[15] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[14] ,IRQS[14] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[13] ,IRQS[13] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[12] ,IRQS[12] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[11] ,IRQS[11] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[10] ,IRQS[10] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[9] ,IRQS[9] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[8] ,IRQS[8] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[7] ,IRQS[7] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[6] ,IRQS[6] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[5] ,IRQS[5] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[4] ,IRQS[4] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[3] ,IRQS[3] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[2] ,IRQS[2] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[1] ,IRQS[1] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[0] ,IRQS[0] status" "No interrupt,Interrupt" rgroup.long 0x1D08++0x03 line.long 0x00 "GICD_SPISR1,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[63] ,IRQS[63] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[62] ,IRQS[62] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[61] ,IRQS[61] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[60] ,IRQS[60] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[59] ,IRQS[59] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[58] ,IRQS[58] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[57] ,IRQS[57] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[56] ,IRQS[56] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[55] ,IRQS[55] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[54] ,IRQS[54] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[53] ,IRQS[53] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[52] ,IRQS[52] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[51] ,IRQS[51] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[50] ,IRQS[50] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[49] ,IRQS[49] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[48] ,IRQS[48] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[47] ,IRQS[47] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[46] ,IRQS[46] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[45] ,IRQS[45] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[44] ,IRQS[44] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[43] ,IRQS[43] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[42] ,IRQS[42] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[41] ,IRQS[41] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[40] ,IRQS[40] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[39] ,IRQS[39] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[38] ,IRQS[38] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[37] ,IRQS[37] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[36] ,IRQS[36] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[35] ,IRQS[35] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[34] ,IRQS[34] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[33] ,IRQS[33] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[32] ,IRQS[32] status" "No interrupt,Interrupt" rgroup.long 0x1D0C++0x03 line.long 0x00 "GICD_SPISR2,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[95] ,IRQS[95] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[94] ,IRQS[94] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[93] ,IRQS[93] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[92] ,IRQS[92] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[91] ,IRQS[91] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[90] ,IRQS[90] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[89] ,IRQS[89] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[88] ,IRQS[88] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[87] ,IRQS[87] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[86] ,IRQS[86] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[85] ,IRQS[85] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[84] ,IRQS[84] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[83] ,IRQS[83] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[82] ,IRQS[82] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[81] ,IRQS[81] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[80] ,IRQS[80] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[79] ,IRQS[79] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[78] ,IRQS[78] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[77] ,IRQS[77] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[76] ,IRQS[76] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[75] ,IRQS[75] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[74] ,IRQS[74] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[73] ,IRQS[73] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[72] ,IRQS[72] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[71] ,IRQS[71] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[70] ,IRQS[70] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[69] ,IRQS[69] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[68] ,IRQS[68] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[67] ,IRQS[67] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[66] ,IRQS[66] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[65] ,IRQS[65] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[64] ,IRQS[64] status" "No interrupt,Interrupt" rgroup.long 0x1D10++0x03 line.long 0x00 "GICD_SPISR3,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[127] ,IRQS[127] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[126] ,IRQS[126] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[125] ,IRQS[125] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[124] ,IRQS[124] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[123] ,IRQS[123] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[122] ,IRQS[122] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[121] ,IRQS[121] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[120] ,IRQS[120] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[119] ,IRQS[119] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[118] ,IRQS[118] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[117] ,IRQS[117] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[116] ,IRQS[116] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[115] ,IRQS[115] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[114] ,IRQS[114] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[113] ,IRQS[113] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[112] ,IRQS[112] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[111] ,IRQS[111] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[110] ,IRQS[110] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[109] ,IRQS[109] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[108] ,IRQS[108] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[107] ,IRQS[107] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[106] ,IRQS[106] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[105] ,IRQS[105] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[104] ,IRQS[104] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[103] ,IRQS[103] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[102] ,IRQS[102] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[101] ,IRQS[101] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[100] ,IRQS[100] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[99] ,IRQS[99] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[98] ,IRQS[98] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[97] ,IRQS[97] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[96] ,IRQS[96] status" "No interrupt,Interrupt" rgroup.long 0x1D14++0x03 line.long 0x00 "GICD_SPISR4,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[159] ,IRQS[159] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[158] ,IRQS[158] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[157] ,IRQS[157] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[156] ,IRQS[156] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[155] ,IRQS[155] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[154] ,IRQS[154] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[153] ,IRQS[153] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[152] ,IRQS[152] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[151] ,IRQS[151] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[150] ,IRQS[150] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[149] ,IRQS[149] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[148] ,IRQS[148] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[147] ,IRQS[147] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[146] ,IRQS[146] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[145] ,IRQS[145] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[144] ,IRQS[144] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[143] ,IRQS[143] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[142] ,IRQS[142] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[141] ,IRQS[141] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[140] ,IRQS[140] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[139] ,IRQS[139] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[138] ,IRQS[138] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[137] ,IRQS[137] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[136] ,IRQS[136] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[135] ,IRQS[135] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[134] ,IRQS[134] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[133] ,IRQS[133] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[132] ,IRQS[132] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[131] ,IRQS[131] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[130] ,IRQS[130] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[129] ,IRQS[129] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[128] ,IRQS[128] status" "No interrupt,Interrupt" rgroup.long 0x1D18++0x03 line.long 0x00 "GICD_SPISR5,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[191] ,IRQS[191] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[190] ,IRQS[190] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[189] ,IRQS[189] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[188] ,IRQS[188] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[187] ,IRQS[187] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[186] ,IRQS[186] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[185] ,IRQS[185] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[184] ,IRQS[184] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[183] ,IRQS[183] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[182] ,IRQS[182] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[181] ,IRQS[181] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[180] ,IRQS[180] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[179] ,IRQS[179] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[178] ,IRQS[178] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[177] ,IRQS[177] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[176] ,IRQS[176] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[175] ,IRQS[175] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[174] ,IRQS[174] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[173] ,IRQS[173] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[172] ,IRQS[172] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[171] ,IRQS[171] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[170] ,IRQS[170] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[169] ,IRQS[169] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[168] ,IRQS[168] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[167] ,IRQS[167] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[166] ,IRQS[166] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[165] ,IRQS[165] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[164] ,IRQS[164] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[163] ,IRQS[163] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[162] ,IRQS[162] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[161] ,IRQS[161] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[160] ,IRQS[160] status" "No interrupt,Interrupt" rgroup.long 0x1D1C++0x03 line.long 0x00 "GICD_SPISR6,Shared Peripheral Interrupt Status Register" bitfld.long 0x00 31. " IRQS[223] ,IRQS[223] status" "No interrupt,Interrupt" bitfld.long 0x00 30. " IRQS[222] ,IRQS[222] status" "No interrupt,Interrupt" bitfld.long 0x00 29. " IRQS[221] ,IRQS[221] status" "No interrupt,Interrupt" bitfld.long 0x00 28. " IRQS[220] ,IRQS[220] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " IRQS[219] ,IRQS[219] status" "No interrupt,Interrupt" bitfld.long 0x00 26. " IRQS[218] ,IRQS[218] status" "No interrupt,Interrupt" bitfld.long 0x00 25. " IRQS[217] ,IRQS[217] status" "No interrupt,Interrupt" bitfld.long 0x00 24. " IRQS[216] ,IRQS[216] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " IRQS[215] ,IRQS[215] status" "No interrupt,Interrupt" bitfld.long 0x00 22. " IRQS[214] ,IRQS[214] status" "No interrupt,Interrupt" bitfld.long 0x00 21. " IRQS[213] ,IRQS[213] status" "No interrupt,Interrupt" bitfld.long 0x00 20. " IRQS[212] ,IRQS[212] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " IRQS[211] ,IRQS[211] status" "No interrupt,Interrupt" bitfld.long 0x00 18. " IRQS[210] ,IRQS[210] status" "No interrupt,Interrupt" bitfld.long 0x00 17. " IRQS[209] ,IRQS[209] status" "No interrupt,Interrupt" bitfld.long 0x00 16. " IRQS[208] ,IRQS[208] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " IRQS[207] ,IRQS[207] status" "No interrupt,Interrupt" bitfld.long 0x00 14. " IRQS[206] ,IRQS[206] status" "No interrupt,Interrupt" bitfld.long 0x00 13. " IRQS[205] ,IRQS[205] status" "No interrupt,Interrupt" bitfld.long 0x00 12. " IRQS[204] ,IRQS[204] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " IRQS[203] ,IRQS[203] status" "No interrupt,Interrupt" bitfld.long 0x00 10. " IRQS[202] ,IRQS[202] status" "No interrupt,Interrupt" bitfld.long 0x00 9. " IRQS[201] ,IRQS[201] status" "No interrupt,Interrupt" bitfld.long 0x00 8. " IRQS[200] ,IRQS[200] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " IRQS[199] ,IRQS[199] status" "No interrupt,Interrupt" bitfld.long 0x00 6. " IRQS[198] ,IRQS[198] status" "No interrupt,Interrupt" bitfld.long 0x00 5. " IRQS[197] ,IRQS[197] status" "No interrupt,Interrupt" bitfld.long 0x00 4. " IRQS[196] ,IRQS[196] status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " IRQS[195] ,IRQS[195] status" "No interrupt,Interrupt" bitfld.long 0x00 2. " IRQS[194] ,IRQS[194] status" "No interrupt,Interrupt" bitfld.long 0x00 1. " IRQS[193] ,IRQS[193] status" "No interrupt,Interrupt" bitfld.long 0x00 0. " IRQS[192] ,IRQS[192] status" "No interrupt,Interrupt" tree.end textline " " width 17. wgroup.long 0x1F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "Send to specified,Send to all,Send to interrupt,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" bitfld.long 0x00 15. " SATT ,SATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1F10++0x03 line.long 0x00 "GICD_CPENDSGIR0,SGI Clear Pending Registers" group.long 0x1F14++0x03 line.long 0x00 "GICD_CPENDSGIR1,SGI Clear Pending Registers" group.long 0x1F18++0x03 line.long 0x00 "GICD_CPENDSGIR2,SGI Clear Pending Registers" group.long 0x1F1C++0x03 line.long 0x00 "GICD_CPENDSGIR3,SGI Clear Pending Registers" textline " " group.long 0x1F20++0x03 line.long 0x00 "GICD_SPENDSGIR0,SGI Set Pending Registers" group.long 0x1F24++0x03 line.long 0x00 "GICD_SPENDSGIR1,SGI Set Pending Registers" group.long 0x1F28++0x03 line.long 0x00 "GICD_SPENDSGIR2,SGI Set Pending Registers" group.long 0x1F2C++0x03 line.long 0x00 "GICD_SPENDSGIR3,SGI Set Pending Registers" textline " " rgroup.long 0x1FE0++0x03 "Peripheral/Component ID Registers" line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " DEVID ,DevID field" rgroup.long 0x1FE4++0x03 line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.long 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " DEVID ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1FE8++0x03 line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.long 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. " UJEPCODE ,UsesJEPcode field" "Low,High" bitfld.long 0x00 0.--2. " DEVID ,DevID field" "0,1,2,3,4,5,6,7" rgroup.long 0x1FEC++0x03 line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.long 0x00 4.--7. " REVID ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1FD0++0x03 line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.long 0x00 0.--3. " CC ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0x1FD4++0x03 hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register" hgroup.long 0x1FD8++0x03 hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register" hgroup.long 0x1FDC++0x03 hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register" textline " " rgroup.long 0x1FF0++0x03 line.long 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0x1FF4++0x03 line.long 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0x1FF8++0x03 line.long 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.long 0x1FFC++0x03 line.long 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.long.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " width 17. group.long 0x2000++0x03 "Interrupt Controller Physical CPU Interface" line.long 0x00 "GICC_ICR,CPU Interface Control Register" bitfld.long 0x00 4. " SBPR ,Secure/Non-secure Binary Point Register for preemption control" "SBPR for Secure/Non-SBPR for Non-Secure,SBPR for Both" textline " " bitfld.long 0x00 3. " FIQEN ,Indicates using of FIQ or IRQ signal for interrupts" "IRQ,FIQ" bitfld.long 0x00 2. " ACKCTL ,Interrupt acknowledge control" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 1. " ENABLENS ,Global Enable for signalling of Non-secure interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLES ,Global Enable for signalling of Secure interrupts" "Disabled,Enabled" group.long 0x2004++0x03 line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface" group.long 0x2008++0x03 line.long 0x00 "GICC_BPR,Binary Point Register" bitfld.long 0x00 0.--2. " BP ,Binary point" "0,1,2,3,4,5,6,7" hgroup.long 0x200C++0x03 hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register" in wgroup.long 0x2010++0x03 line.long 0x00 "GICC_EOIR,End Of Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " EOIINTID ,ACKINTID value from the corresponding ICCIAR access" rgroup.long 0x2014++0x03 line.long 0x00 "GICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt" rgroup.long 0x2018++0x03 line.long 0x00 "GICC_HPIR,Highest Pending Interrupt Register" bitfld.long 0x00 10.--12. " CPUID ,CPU ID" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--9. 1. " PENDINTID ,Interrupt ID of the highest priority pending interrupt" group.long 0x201C++0x03 line.long 0x00 "GICC_ABPR,Aliased Binary Point Register" group.long 0x20D0++0x03 line.long 0x00 "GICC_APR0,Active Priorities Register" group.long 0x20E0++0x03 line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register" rgroup.long 0x20FC++0x03 line.long 0x00 "GICC_IIDR,CPU and Virtual CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x3000++0x03 line.long 0x00 "GICC_DIR,Deactivate Interrupt Register" width 17. group.long 0x4000++0x03 "Interrupt Controller Virtual CPU Interface (Hypervisor view)" line.long 0x00 "GICH_HCR,Hypervisor Control Register" rgroup.long 0x4004++0x03 line.long 0x00 "GICH_VTR,VGIC Type Register" bitfld.long 0x00 29.--31. " PRIBITS ,Number of priority bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRI levels,?..." textline " " bitfld.long 0x00 26.--28. " PREBITS ,Number of pre-emption bits" "Reserved,Reserved,Reserved,Reserved,5 bits 32 PRE levels,?..." textline " " bitfld.long 0x00 0.--5. " LISTREGS ,List regs number" "Reserved,Reserved,Reserved,4 lists,?..." group.long 0x40F0++0x03 line.long 0x00 "GICH_APR0,Active Priorities Register" group.long 0x4100++0x03 line.long 0x00 "GICH_LR0,List Register 0" group.long 0x4104++0x03 line.long 0x00 "GICH_LR1,List Register 1" group.long 0x4108++0x03 line.long 0x00 "GICH_LR2,List Register 2" group.long 0x410C++0x03 line.long 0x00 "GICH_LR3,List Register 3" group.long 0x6000++0x03 "Interrupt Controller Virtual CPU Interface (Virtual Machine View)" line.long 0x00 "GICV_CTLR,VM Control Register" group.long 0x6004++0x03 line.long 0x00 "GICV_PMR,VM Priority Mask Register" group.long 0x6008++0x03 line.long 0x00 "GICV_BPR,VM Binary Point Register" hgroup.long 0x600C++0x03 hide.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register" in wgroup.long 0x6010++0x03 line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register" rgroup.long 0x6014++0x03 line.long 0x00 "GICV_RPR,VM Running Priority Register" rgroup.long 0x6018++0x03 line.long 0x00 "GICV_HPIR,VM Highest Pending Interrupt Register" group.long 0x601C++0x03 line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register" group.long 0x60D0++0x03 line.long 0x00 "GICV_APR0,VM Active Priority Register" group.long 0x60E0++0x03 line.long 0x00 "GICV_NSAPR0,VM Non-Secure Active Priority Register" rgroup.long 0x60FC++0x03 line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register" hexmask.long.word 0x00 20.--31. 1. " PRODID ,Product ID" bitfld.long 0x00 12.--15. " REV ,Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" wgroup.long 0x7000++0x03 line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register" tree.end tree.end elif cpuis("AM572XIPU*") tree.close "Core Registers (Cortex-M4)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end elif cpuis("AM572XIVA?") tree "Core Registers (ARM966)" width 8. tree "ID Registers" rgroup c15:0x0000--0x0000 line.long 0x0 "MIDR,Identity Code" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer" hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision" hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision" tree.end tree "System Configuration and Control" width 8. group c15:0x1--0x1 line.long 0x0 "CR,Control Register" bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable" bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction SRAM Enable" "Disable,Enable" bitfld.long 0x0 7. " B ,Endianism" "Little,Big" bitfld.long 0x0 3. " W ,Write Buffer" "Disable,Enable" bitfld.long 0x0 2. " D ,Data SRAM Enable" "Disable,Enable" tree.end tree "ICEbreaker" width 8. group ice:0x0--0x5 "Debug Control" line.long 0x0 "DBGCTRL,Debug Control Register" bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled" bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled" textline " " bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled" bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled" bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x4 "DBGSTAT,Debug Status Register" bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,1" bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1" bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled" bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x8 "VECTOR,Vector Catch Register" bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena" bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena" bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena" bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena" bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena" bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena" bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena" line.long 0x10 "COMCTRL,Debug Communication Control Register" bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend" bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend" line.long 0x14 "COMDATA,Debug Communication Data Register" group ice:0x8--0x0d "Watchpoint 0" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" group ice:0x10--0x15 "Watchpoint 1" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" tree.end tree.end elif cpuis("AM572XDSP?") AUTOINDENT.PUSH AUTOINDENT.OFF tree "Core Registers (c66x)" config 16. 8. width 0x0b tree.open "Cache" tree "L1P Cache" base d:0x01840000 width 9. group.long 0x20++0x7 "L1P Cache Control Registers" line.long 0x00 "L1PCFG,L1P Configuration Register" bitfld.long 0x00 0.--2. " L1PMODE ,Size of the L1P cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal" line.long 0x04 "L1PCC,L1P Cache Control Register" bitfld.long 0x04 16. " POPER ,Holds the previous value of the OPER field" "0,1" bitfld.long 0x04 0. " OPER ,Controls the L1P freeze mode" "Disabled,Enabled" wgroup.long 0x4020++0x3 line.long 0x00 "L1PIBAR,L1P Invalidate Base Address Register" hexmask.long 0x00 0.--31. 1. " L1PIBAR ,32-bit base address for block invalidation" group.long 0x4024++0x3 line.long 0x00 "L1PIWC,L1P Invalidate Word Count" hexmask.long.word 0x00 0.--15. 1. " L1PIWC ,Word count for block invalidation" group.long 0x5028++0x3 line.long 0x00 "L1PINV,L1P Invalidate Register" bitfld.long 0x00 0. " I ,Controls the global invalidation of L1P cache" "Normal,Invalidate" //width 13. //wgroup.long 0xD00++0x13 "Memory Protection Lock Registers" // line.long 0x00 "L1PMPLK0,Memory Protection Lock Register 0" // hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0" // line.long 0x04 "L1PMPLK1,Memory Protection Lock Register 1" // hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32" // line.long 0x08 "L1PMPLK2,Memory Protection Lock Register 2" // hexmask.long 0x08 0.--31. 1. " LB ,Lock Bits 95:64" // line.long 0x0c "L1PMPLK3,Memory Protection Lock Register 3" // hexmask.long 0x0c 0.--31. 1. " LB ,Lock Bits 127:96" // line.long 0x10 "L1PMPLKCMD,Memory Protection Lock Command Register" // bitfld.long 0x10 2. " KEYR ,Reset status" "No effect,Reset" // bitfld.long 0x10 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked" // bitfld.long 0x10 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked" //rgroup.long 0xD14++0x3 // line.long 0x00 "L1PMPLKSTAT,Memory Protection Lock Status Register" // bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged" base d:0x0184a000 width 12. tree "Memory Page Protection Attribute Registers" group.long 0x640++0x3f line.long 0x0 "L1PMPPA16,Level 1 Memory Page Protection Attribute Register 16" bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x0 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x0 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x0 2. " UR ,User read access type" "Normal,User" bitfld.long 0x0 1. " UW ,User write access type" "Normal,User" bitfld.long 0x0 0. " UX ,User execute access type" "Normal,User" line.long 0x4 "L1PMPPA17,Level 1 Memory Page Protection Attribute Register 17" bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x4 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4 1. " UW ,User write access type" "Normal,User" bitfld.long 0x4 0. " UX ,User execute access type" "Normal,User" line.long 0x8 "L1PMPPA18,Level 1 Memory Page Protection Attribute Register 18" bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x8 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x8 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x8 2. " UR ,User read access type" "Normal,User" bitfld.long 0x8 1. " UW ,User write access type" "Normal,User" bitfld.long 0x8 0. " UX ,User execute access type" "Normal,User" line.long 0xC "L1PMPPA19,Level 1 Memory Page Protection Attribute Register 19" bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0xC 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0xC 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0xC 2. " UR ,User read access type" "Normal,User" bitfld.long 0xC 1. " UW ,User write access type" "Normal,User" bitfld.long 0xC 0. " UX ,User execute access type" "Normal,User" line.long 0x10 "L1PMPPA20,Level 1 Memory Page Protection Attribute Register 20" bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x10 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x10 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x10 2. " UR ,User read access type" "Normal,User" bitfld.long 0x10 1. " UW ,User write access type" "Normal,User" bitfld.long 0x10 0. " UX ,User execute access type" "Normal,User" line.long 0x14 "L1PMPPA21,Level 1 Memory Page Protection Attribute Register 21" bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x14 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x14 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x14 2. " UR ,User read access type" "Normal,User" bitfld.long 0x14 1. " UW ,User write access type" "Normal,User" bitfld.long 0x14 0. " UX ,User execute access type" "Normal,User" line.long 0x18 "L1PMPPA22,Level 1 Memory Page Protection Attribute Register 22" bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x18 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x18 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x18 2. " UR ,User read access type" "Normal,User" bitfld.long 0x18 1. " UW ,User write access type" "Normal,User" bitfld.long 0x18 0. " UX ,User execute access type" "Normal,User" line.long 0x1C "L1PMPPA23,Level 1 Memory Page Protection Attribute Register 23" bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x1C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x1C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x1C 0. " UX ,User execute access type" "Normal,User" line.long 0x20 "L1PMPPA24,Level 1 Memory Page Protection Attribute Register 24" bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x20 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x20 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x20 2. " UR ,User read access type" "Normal,User" bitfld.long 0x20 1. " UW ,User write access type" "Normal,User" bitfld.long 0x20 0. " UX ,User execute access type" "Normal,User" line.long 0x24 "L1PMPPA25,Level 1 Memory Page Protection Attribute Register 25" bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x24 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x24 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x24 2. " UR ,User read access type" "Normal,User" bitfld.long 0x24 1. " UW ,User write access type" "Normal,User" bitfld.long 0x24 0. " UX ,User execute access type" "Normal,User" line.long 0x28 "L1PMPPA26,Level 1 Memory Page Protection Attribute Register 26" bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x28 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x28 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x28 2. " UR ,User read access type" "Normal,User" bitfld.long 0x28 1. " UW ,User write access type" "Normal,User" bitfld.long 0x28 0. " UX ,User execute access type" "Normal,User" line.long 0x2C "L1PMPPA27,Level 1 Memory Page Protection Attribute Register 27" bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x2C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x2C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x2C 0. " UX ,User execute access type" "Normal,User" line.long 0x30 "L1PMPPA28,Level 1 Memory Page Protection Attribute Register 28" bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x30 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x30 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x30 2. " UR ,User read access type" "Normal,User" bitfld.long 0x30 1. " UW ,User write access type" "Normal,User" bitfld.long 0x30 0. " UX ,User execute access type" "Normal,User" line.long 0x34 "L1PMPPA29,Level 1 Memory Page Protection Attribute Register 29" bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x34 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x34 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x34 2. " UR ,User read access type" "Normal,User" bitfld.long 0x34 1. " UW ,User write access type" "Normal,User" bitfld.long 0x34 0. " UX ,User execute access type" "Normal,User" line.long 0x38 "L1PMPPA30,Level 1 Memory Page Protection Attribute Register 30" bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x38 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x38 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x38 2. " UR ,User read access type" "Normal,User" bitfld.long 0x38 1. " UW ,User write access type" "Normal,User" bitfld.long 0x38 0. " UX ,User execute access type" "Normal,User" line.long 0x3C "L1PMPPA31,Level 1 Memory Page Protection Attribute Register 31" bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3" "Denied,Granted" textline " " bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x3C 9. " AIDX ,Controls access from ID>=6" "Denied,Granted" bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x3C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x3C 0. " UX ,User execute access type" "Normal,User" tree.end width 11. rgroup.long 0x400++0x7 "Memory Protection Fault Registers" line.long 0x00 "L1PMPFAR,L1P Memory Protection Fault Address" hexmask.long 0x00 0.--31. 1. " FA ,Fault Address" line.long 0x04 "L1PMPFSR,L1P Memory Protection Fault Set Register" hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of faulting requestor" bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Local" bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor" textline " " bitfld.long 0x04 2. " UR ,User read access type" "Normal,User" bitfld.long 0x04 1. " UW ,User write access type" "Normal,User" group.long 0x408++0x3 line.long 0x00 "L1PMPFCLR,L1P Memory Protection Fault Clear" bitfld.long 0x00 0. " MPFCLR ,Command to clear the L1DMPFAR and L1DMPFCR" "No effect,Clear" AUTOINDENT.ON right tree rgroup.long 0x6404++0x3 "Error Detection Registers" line.long 0x0 "L1PEDSTAT,L1P Error Detection Status Register" bitfld.long 0x0 6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True" bitfld.long 0x0 5. "PERR,Program fetch resulted in parity check error" "False,True" bitfld.long 0x0 3. "SUSP,Error detection logic is suspended" "False,True" bitfld.long 0x0 2. "DIS,Error detection logic is disabled" "False,True" bitfld.long 0x0 0. "EN,Error detection logic is enabled" "False,True" group.long 0x6408++0x3 line.long 0x0 "L1PEDCMD, L1P Error Detection Command Register" bitfld.long 0x0 6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear" bitfld.long 0x0 5. "PCLR,Clears the program fetch parity error status" "No effect,Clear" bitfld.long 0x0 3. "SUSP,Suspends the error detection logic" "No effect,Suspend" bitfld.long 0x0 2. "DIS,Disables the error detection logic" "No effect,Disable" bitfld.long 0x0 0. "EN,Enables the error detection logic" "No effect,Enable" rgroup.long 0x640C++0x3 line.long 0x0 "L1PEDADDR, L1P Error Detection Address Register" hexmask.long.long 0x0 5.--31. 32. "ADDR,Contains the upper 27 bit of error location" bitfld.long 0x0 0. "RAM,Location where error was detected" "L1P cache,L1P RAM" AUTOINDENT.OFF width 0xb tree.end tree "L1D Cache" base d:0x01840000 width 10. group.long 0x40++0x7 "L1D Cache Control Registers" line.long 0x00 "L1DCFG,L1D Cache Configuration" bitfld.long 0x00 0.--2. " L1DMODE ,Size of the L1D cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal" line.long 0x04 "L1DCC,L1D Cache Control Register" bitfld.long 0x04 16. " POPER ,Holds the previous value of the OPER field" "0,1" bitfld.long 0x04 0. " OPER ,Controls the L1D freeze mode" "Disabled,Enabled" wgroup.long 0x4030++0x3 line.long 0x00 "L1DWIBAR,L1D Writeback-Invalidated Base Address" hexmask.long 0x00 0.--31. 1. " L1DWIBAR ,L1D Writeback-Invalidated Base Address" group.long 0x4034++0x3 line.long 0x00 "L1DWIWC,L1D Writeback-Invalidated Word Count" hexmask.long.word 0x00 0.--15. 1. " L1DWIWC ,L1D Writeback-Invalidated Word Count" wgroup.long 0x4040++0x3 line.long 0x00 "L1DWBAR,L1D Writeback Base Address" hexmask.long 0x00 0.--31. 1. " L1DWBAR ,L1D Writeback Base Address" group.long 0x4044++0x3 line.long 0x00 "L1DWWC,L1D Writeback Word Count" hexmask.long.word 0x00 0.--15. 1. " L1DWWC ,L1D Writeback Word Count" wgroup.long 0x4048++0x3 line.long 0x00 "L1DIBAR,L1D Invalidate Base Address" hexmask.long 0x00 0.--31. 1. " L1DIBAR ,L1D Invalidate Base Address" group.long 0x404c++0x3 line.long 0x00 "L1DIWC,L1D Invalidate Word Count" hexmask.long.word 0x00 0.--15. 1. " L1DIWC ,L1D Invalidate Word Count" group.long 0x5048++0x3 line.long 0x00 "L1DINV,L1D Invalidate Register" bitfld.long 0x00 0. " I ,Controls the global invalidation of L1D cache" "Normal,Invalidate" group.long 0x5040++0x3 line.long 0x00 "L1DWB,L1P Writeback Register" bitfld.long 0x00 0. " C ,Controls the global writeback operation of L1D cache" "Normal,Write back" group.long 0x5044++0x3 line.long 0x00 "L1DWBINV,L1D Writeback-Invalidate Register" bitfld.long 0x00 0. " C ,Controls the global writeback-invalidate operation of L1D cache" "Normal,Invalidate" width 11. base d:0x0184a000 tree "Memory Protection Attribute Registers" group.long 0xe40++0x3f line.long 0x0 "MPPA16,Memory Protection Attribute Register" bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x0 2. " UR ,User read access type" "Normal,User" bitfld.long 0x0 1. " UW ,User write access type" "Normal,User" line.long 0x4 "MPPA17,Memory Protection Attribute Register" bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x4 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4 1. " UW ,User write access type" "Normal,User" line.long 0x8 "MPPA18,Memory Protection Attribute Register" bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x8 2. " UR ,User read access type" "Normal,User" bitfld.long 0x8 1. " UW ,User write access type" "Normal,User" line.long 0xC "MPPA19,Memory Protection Attribute Register" bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0xC 2. " UR ,User read access type" "Normal,User" bitfld.long 0xC 1. " UW ,User write access type" "Normal,User" line.long 0x10 "MPPA20,Memory Protection Attribute Register" bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x10 2. " UR ,User read access type" "Normal,User" bitfld.long 0x10 1. " UW ,User write access type" "Normal,User" line.long 0x14 "MPPA21,Memory Protection Attribute Register" bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x14 2. " UR ,User read access type" "Normal,User" bitfld.long 0x14 1. " UW ,User write access type" "Normal,User" line.long 0x18 "MPPA22,Memory Protection Attribute Register" bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x18 2. " UR ,User read access type" "Normal,User" bitfld.long 0x18 1. " UW ,User write access type" "Normal,User" line.long 0x1C "MPPA23,Memory Protection Attribute Register" bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User" line.long 0x20 "MPPA24,Memory Protection Attribute Register" bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x20 2. " UR ,User read access type" "Normal,User" bitfld.long 0x20 1. " UW ,User write access type" "Normal,User" line.long 0x24 "MPPA25,Memory Protection Attribute Register" bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x24 2. " UR ,User read access type" "Normal,User" bitfld.long 0x24 1. " UW ,User write access type" "Normal,User" line.long 0x28 "MPPA26,Memory Protection Attribute Register" bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x28 2. " UR ,User read access type" "Normal,User" bitfld.long 0x28 1. " UW ,User write access type" "Normal,User" line.long 0x2C "MPPA27,Memory Protection Attribute Register" bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User" line.long 0x30 "MPPA28,Memory Protection Attribute Register" bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x30 2. " UR ,User read access type" "Normal,User" bitfld.long 0x30 1. " UW ,User write access type" "Normal,User" line.long 0x34 "MPPA29,Memory Protection Attribute Register" bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x34 2. " UR ,User read access type" "Normal,User" bitfld.long 0x34 1. " UW ,User write access type" "Normal,User" line.long 0x38 "MPPA30,Memory Protection Attribute Register" bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x38 2. " UR ,User read access type" "Normal,User" bitfld.long 0x38 1. " UW ,User write access type" "Normal,User" line.long 0x3C "MPPA31,Memory Protection Attribute Register" bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User" tree.end base d:0x0184a000 width 10. rgroup.long 0xc00++0x7 "Memory Protection Fault Registers" line.long 0x00 "L1DMPFAR,Memory Protection Fault Address Register" hexmask.long 0x00 0.--31. 1. " FA ,Fault Address" line.long 0x04 "L1DMPFSR,Memory Protection Fault Set Register" hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of ID of faulting requestor" bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Supervisor" bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x04 2. " UR ,User read access type" "Normal,User" bitfld.long 0x04 1. " UW ,User write access type" "Normal,User" group.long 0xc08++0x3 line.long 0x00 "L1DMPFCR,Memory Protection Fault Clear Register" eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Cleared" width 13. wgroup.long 0xd00++0xf "Memory Protection Lock Registers" line.long 0x00 "L1DMPLK0,Level 1 Data Memory Protection Lock Register 0" hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0" line.long 0x04 "L1DMPLK1,Level 1 Data Memory Protection Lock Register 1" hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32" line.long 0x08 "L1DMPLK2,Level 1 Data Memory Protection Lock Register 2" line.long 0x0c "L1DMPLK3,Level 1 Data Memory Protection Lock Register 3" wgroup.long 0xd10++0x3 line.long 0x00 "L1DMPLKCMD,Level 1 Data Memory Protection Lock Command Register" bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset" bitfld.long 0x00 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked" bitfld.long 0x00 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked" rgroup.long 0xd14++0x3 line.long 0x00 "L1DMPLKSTAT,Level 1 Data Memory Protection Lock Status Register" bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged" width 0xb tree.end tree "L2 Cache" base d:0x01840000 width 9. group.long 0x00++0x3 "L2 Cache Control Registers" line.long 0x00 "L2CFG,L2 Configuration Register" hexmask.long.byte 0x00 24.--27. 1. " NUM_MM ,Number of megamodules minus one" hexmask.long.byte 0x00 16.--19. 1. " MMID ,Contains the Megamodule ID number" bitfld.long 0x00 9. " IP ,L1P global invalidate bit" "Normal,Invalidate" textline " " bitfld.long 0x00 8. " ID ,L1D global invalidate bit" "Normal,Invalidate" bitfld.long 0x00 3. " L2CC ,Freeze mode" "Normal,Frozen" bitfld.long 0x00 0.--2. " L2MODE ,Size of L2 cache" "Disabled,32K,64K,128K,256K,512K,1024K,Maximum" wgroup.long 0x4000++0x3 line.long 0x00 "L2WBAR,L2 Writeback Base Address Register" hexmask.long 0x00 0.--31. 1. " L2WBAR ,L2 Writeback Base Address" group.long 0x4004++0x3 line.long 0x00 "L2WWC,L2 Writeback Word Count Register" hexmask.long.word 0x00 0.--15. 1. " L2WWC ,L2 Writeback Word Count" wgroup.long 0x4010++0x3 line.long 0x00 "L2WIBAR,L2 Writeback-Invalidate Base Address" hexmask.long 0x00 0.--31. 1. " L2WIBAR ,L2 Writeback Invalidate Base Address" group.long 0x4014++0x3 line.long 0x00 "L2WIWC,L2 Writeback Invalidate Word Count Register" hexmask.long.word 0x00 0.--15. 1. " L2WIWC ,L2 Writeback Invalidate Word Count" wgroup.long 0x4018++0x3 line.long 0x00 "L2IBAR,L2 Invalidate Base Address Register" hexmask.long 0x00 0.--31. 1. " L2IBAR ,L2 Invalidate Base Address" group.long 0x401c++0x3 line.long 0x00 "L2IWC,L2 Invalidate Word Count Register" hexmask.long.word 0x00 0.--15. 1. " L2IWC ,L2 Invalidate Word Count" group.long 0x5000++0xb line.long 0x00 "L2WB,L2 Writeback Register" bitfld.long 0x00 0. " C ,Controls the global writeback operation of L2 cache" "Normal,Writeback" line.long 0x04 "L2WBINV,L2 Writeback-Invalidate Register" bitfld.long 0x04 0. " C ,Controls the global writeback-invalidate operation of L2 cache" "Normal,Writeback" line.long 0x08 "L2INV,L2 Invalidate Register" bitfld.long 0x08 0. " I ,Controls the global invalidation of L2 cache" "Normal,Invalidate" tree "Memory Attribute Registers" width 8. base d:0x01848000 rgroup.long 0x00++0x2f line.long 0x0 "MAR0,Memory Attribute Register 0" bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x4 "MAR1,Memory Attribute Register 1" bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x8 "MAR2,Memory Attribute Register 2" bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC "MAR3,Memory Attribute Register 3" bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x10 "MAR4,Memory Attribute Register 4" bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x10 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x14 "MAR5,Memory Attribute Register 5" bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x14 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x18 "MAR6,Memory Attribute Register 6" bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x18 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C "MAR7,Memory Attribute Register 7" bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x20 "MAR8,Memory Attribute Register 8" bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x20 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x24 "MAR9,Memory Attribute Register 9" bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x24 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x28 "MAR10,Memory Attribute Register 10" bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x28 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C "MAR11,Memory Attribute Register 11" bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" group.long 0x30++0x3cf line.long 0x0 "MAR12,Memory Attribute Register 12" bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x4 "MAR13,Memory Attribute Register 13" bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x8 "MAR14,Memory Attribute Register 14" bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC "MAR15,Memory Attribute Register 15" bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x10 "MAR16,Memory Attribute Register 16" bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x10 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x14 "MAR17,Memory Attribute Register 17" bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x14 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x18 "MAR18,Memory Attribute Register 18" bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x18 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C "MAR19,Memory Attribute Register 19" bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x20 "MAR20,Memory Attribute Register 20" bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x20 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x24 "MAR21,Memory Attribute Register 21" bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x24 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x28 "MAR22,Memory Attribute Register 22" bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x28 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C "MAR23,Memory Attribute Register 23" bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x30 "MAR24,Memory Attribute Register 24" bitfld.long 0x30 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x30 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x34 "MAR25,Memory Attribute Register 25" bitfld.long 0x34 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x34 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x38 "MAR26,Memory Attribute Register 26" bitfld.long 0x38 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x38 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C "MAR27,Memory Attribute Register 27" bitfld.long 0x3C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x40 "MAR28,Memory Attribute Register 28" bitfld.long 0x40 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x40 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x44 "MAR29,Memory Attribute Register 29" bitfld.long 0x44 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x44 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x48 "MAR30,Memory Attribute Register 30" bitfld.long 0x48 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x48 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x4C "MAR31,Memory Attribute Register 31" bitfld.long 0x4C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x4C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x50 "MAR32,Memory Attribute Register 32" bitfld.long 0x50 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x50 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x54 "MAR33,Memory Attribute Register 33" bitfld.long 0x54 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x54 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x58 "MAR34,Memory Attribute Register 34" bitfld.long 0x58 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x58 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x5C "MAR35,Memory Attribute Register 35" bitfld.long 0x5C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x5C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x60 "MAR36,Memory Attribute Register 36" bitfld.long 0x60 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x60 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x64 "MAR37,Memory Attribute Register 37" bitfld.long 0x64 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x64 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x68 "MAR38,Memory Attribute Register 38" bitfld.long 0x68 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x68 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x6C "MAR39,Memory Attribute Register 39" bitfld.long 0x6C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x6C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x70 "MAR40,Memory Attribute Register 40" bitfld.long 0x70 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x70 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x74 "MAR41,Memory Attribute Register 41" bitfld.long 0x74 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x74 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x78 "MAR42,Memory Attribute Register 42" bitfld.long 0x78 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x78 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x7C "MAR43,Memory Attribute Register 43" bitfld.long 0x7C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x7C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x80 "MAR44,Memory Attribute Register 44" bitfld.long 0x80 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x80 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x84 "MAR45,Memory Attribute Register 45" bitfld.long 0x84 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x84 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x88 "MAR46,Memory Attribute Register 46" bitfld.long 0x88 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x88 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x8C "MAR47,Memory Attribute Register 47" bitfld.long 0x8C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x8C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x90 "MAR48,Memory Attribute Register 48" bitfld.long 0x90 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x90 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x94 "MAR49,Memory Attribute Register 49" bitfld.long 0x94 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x94 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x98 "MAR50,Memory Attribute Register 50" bitfld.long 0x98 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x98 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x9C "MAR51,Memory Attribute Register 51" bitfld.long 0x9C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x9C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xA0 "MAR52,Memory Attribute Register 52" bitfld.long 0xA0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xA0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xA4 "MAR53,Memory Attribute Register 53" bitfld.long 0xA4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xA4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xA8 "MAR54,Memory Attribute Register 54" bitfld.long 0xA8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xA8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xAC "MAR55,Memory Attribute Register 55" bitfld.long 0xAC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xAC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xB0 "MAR56,Memory Attribute Register 56" bitfld.long 0xB0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xB0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xB4 "MAR57,Memory Attribute Register 57" bitfld.long 0xB4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xB4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xB8 "MAR58,Memory Attribute Register 58" bitfld.long 0xB8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xB8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xBC "MAR59,Memory Attribute Register 59" bitfld.long 0xBC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xBC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC0 "MAR60,Memory Attribute Register 60" bitfld.long 0xC0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC4 "MAR61,Memory Attribute Register 61" bitfld.long 0xC4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xC8 "MAR62,Memory Attribute Register 62" bitfld.long 0xC8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xC8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xCC "MAR63,Memory Attribute Register 63" bitfld.long 0xCC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xCC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xD0 "MAR64,Memory Attribute Register 64" bitfld.long 0xD0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xD0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xD4 "MAR65,Memory Attribute Register 65" bitfld.long 0xD4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xD4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xD8 "MAR66,Memory Attribute Register 66" bitfld.long 0xD8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xD8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xDC "MAR67,Memory Attribute Register 67" bitfld.long 0xDC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xDC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xE0 "MAR68,Memory Attribute Register 68" bitfld.long 0xE0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xE0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xE4 "MAR69,Memory Attribute Register 69" bitfld.long 0xE4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xE4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xE8 "MAR70,Memory Attribute Register 70" bitfld.long 0xE8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xE8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xEC "MAR71,Memory Attribute Register 71" bitfld.long 0xEC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xEC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xF0 "MAR72,Memory Attribute Register 72" bitfld.long 0xF0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xF0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xF4 "MAR73,Memory Attribute Register 73" bitfld.long 0xF4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xF4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xF8 "MAR74,Memory Attribute Register 74" bitfld.long 0xF8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xF8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0xFC "MAR75,Memory Attribute Register 75" bitfld.long 0xFC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0xFC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x100 "MAR76,Memory Attribute Register 76" bitfld.long 0x100 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x100 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x104 "MAR77,Memory Attribute Register 77" bitfld.long 0x104 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x104 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x108 "MAR78,Memory Attribute Register 78" bitfld.long 0x108 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x108 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x10C "MAR79,Memory Attribute Register 79" bitfld.long 0x10C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x10C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x110 "MAR80,Memory Attribute Register 80" bitfld.long 0x110 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x110 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x114 "MAR81,Memory Attribute Register 81" bitfld.long 0x114 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x114 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x118 "MAR82,Memory Attribute Register 82" bitfld.long 0x118 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x118 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x11C "MAR83,Memory Attribute Register 83" bitfld.long 0x11C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x11C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x120 "MAR84,Memory Attribute Register 84" bitfld.long 0x120 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x120 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x124 "MAR85,Memory Attribute Register 85" bitfld.long 0x124 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x124 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x128 "MAR86,Memory Attribute Register 86" bitfld.long 0x128 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x128 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x12C "MAR87,Memory Attribute Register 87" bitfld.long 0x12C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x12C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x130 "MAR88,Memory Attribute Register 88" bitfld.long 0x130 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x130 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x134 "MAR89,Memory Attribute Register 89" bitfld.long 0x134 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x134 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x138 "MAR90,Memory Attribute Register 90" bitfld.long 0x138 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x138 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x13C "MAR91,Memory Attribute Register 91" bitfld.long 0x13C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x13C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x140 "MAR92,Memory Attribute Register 92" bitfld.long 0x140 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x140 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x144 "MAR93,Memory Attribute Register 93" bitfld.long 0x144 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x144 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x148 "MAR94,Memory Attribute Register 94" bitfld.long 0x148 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x148 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x14C "MAR95,Memory Attribute Register 95" bitfld.long 0x14C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x14C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x150 "MAR96,Memory Attribute Register 96" bitfld.long 0x150 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x150 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x154 "MAR97,Memory Attribute Register 97" bitfld.long 0x154 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x154 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x158 "MAR98,Memory Attribute Register 98" bitfld.long 0x158 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x158 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x15C "MAR99,Memory Attribute Register 99" bitfld.long 0x15C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x15C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x160 "MAR100,Memory Attribute Register 100" bitfld.long 0x160 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x160 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x164 "MAR101,Memory Attribute Register 101" bitfld.long 0x164 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x164 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x168 "MAR102,Memory Attribute Register 102" bitfld.long 0x168 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x168 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x16C "MAR103,Memory Attribute Register 103" bitfld.long 0x16C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x16C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x170 "MAR104,Memory Attribute Register 104" bitfld.long 0x170 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x170 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x174 "MAR105,Memory Attribute Register 105" bitfld.long 0x174 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x174 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x178 "MAR106,Memory Attribute Register 106" bitfld.long 0x178 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x178 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x17C "MAR107,Memory Attribute Register 107" bitfld.long 0x17C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x17C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x180 "MAR108,Memory Attribute Register 108" bitfld.long 0x180 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x180 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x184 "MAR109,Memory Attribute Register 109" bitfld.long 0x184 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x184 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x188 "MAR110,Memory Attribute Register 110" bitfld.long 0x188 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x188 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x18C "MAR111,Memory Attribute Register 111" bitfld.long 0x18C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x18C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x190 "MAR112,Memory Attribute Register 112" bitfld.long 0x190 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x190 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x194 "MAR113,Memory Attribute Register 113" bitfld.long 0x194 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x194 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x198 "MAR114,Memory Attribute Register 114" bitfld.long 0x198 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x198 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x19C "MAR115,Memory Attribute Register 115" bitfld.long 0x19C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x19C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1A0 "MAR116,Memory Attribute Register 116" bitfld.long 0x1A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1A4 "MAR117,Memory Attribute Register 117" bitfld.long 0x1A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1A8 "MAR118,Memory Attribute Register 118" bitfld.long 0x1A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1AC "MAR119,Memory Attribute Register 119" bitfld.long 0x1AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1B0 "MAR120,Memory Attribute Register 120" bitfld.long 0x1B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1B4 "MAR121,Memory Attribute Register 121" bitfld.long 0x1B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1B8 "MAR122,Memory Attribute Register 122" bitfld.long 0x1B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1BC "MAR123,Memory Attribute Register 123" bitfld.long 0x1BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C0 "MAR124,Memory Attribute Register 124" bitfld.long 0x1C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C4 "MAR125,Memory Attribute Register 125" bitfld.long 0x1C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1C8 "MAR126,Memory Attribute Register 126" bitfld.long 0x1C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1CC "MAR127,Memory Attribute Register 127" bitfld.long 0x1CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1D0 "MAR128,Memory Attribute Register 128" bitfld.long 0x1D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1D0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1D4 "MAR129,Memory Attribute Register 129" bitfld.long 0x1D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1D4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1D8 "MAR130,Memory Attribute Register 130" bitfld.long 0x1D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1D8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1DC "MAR131,Memory Attribute Register 131" bitfld.long 0x1DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1DC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1E0 "MAR132,Memory Attribute Register 132" bitfld.long 0x1E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1E0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1E4 "MAR133,Memory Attribute Register 133" bitfld.long 0x1E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1E4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1E8 "MAR134,Memory Attribute Register 134" bitfld.long 0x1E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1E8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1EC "MAR135,Memory Attribute Register 135" bitfld.long 0x1EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1EC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1F0 "MAR136,Memory Attribute Register 136" bitfld.long 0x1F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1F0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1F4 "MAR137,Memory Attribute Register 137" bitfld.long 0x1F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1F4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1F8 "MAR138,Memory Attribute Register 138" bitfld.long 0x1F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1F8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x1FC "MAR139,Memory Attribute Register 139" bitfld.long 0x1FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x1FC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x200 "MAR140,Memory Attribute Register 140" bitfld.long 0x200 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x200 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x204 "MAR141,Memory Attribute Register 141" bitfld.long 0x204 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x204 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x208 "MAR142,Memory Attribute Register 142" bitfld.long 0x208 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x208 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x20C "MAR143,Memory Attribute Register 143" bitfld.long 0x20C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x20C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x210 "MAR144,Memory Attribute Register 144" bitfld.long 0x210 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x210 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x214 "MAR145,Memory Attribute Register 145" bitfld.long 0x214 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x214 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x218 "MAR146,Memory Attribute Register 146" bitfld.long 0x218 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x218 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x21C "MAR147,Memory Attribute Register 147" bitfld.long 0x21C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x21C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x220 "MAR148,Memory Attribute Register 148" bitfld.long 0x220 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x220 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x224 "MAR149,Memory Attribute Register 149" bitfld.long 0x224 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x224 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x228 "MAR150,Memory Attribute Register 150" bitfld.long 0x228 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x228 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x22C "MAR151,Memory Attribute Register 151" bitfld.long 0x22C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x22C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x230 "MAR152,Memory Attribute Register 152" bitfld.long 0x230 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x230 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x234 "MAR153,Memory Attribute Register 153" bitfld.long 0x234 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x234 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x238 "MAR154,Memory Attribute Register 154" bitfld.long 0x238 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x238 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x23C "MAR155,Memory Attribute Register 155" bitfld.long 0x23C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x23C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x240 "MAR156,Memory Attribute Register 156" bitfld.long 0x240 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x240 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x244 "MAR157,Memory Attribute Register 157" bitfld.long 0x244 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x244 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x248 "MAR158,Memory Attribute Register 158" bitfld.long 0x248 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x248 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x24C "MAR159,Memory Attribute Register 159" bitfld.long 0x24C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x24C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x250 "MAR160,Memory Attribute Register 160" bitfld.long 0x250 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x250 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x254 "MAR161,Memory Attribute Register 161" bitfld.long 0x254 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x254 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x258 "MAR162,Memory Attribute Register 162" bitfld.long 0x258 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x258 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x25C "MAR163,Memory Attribute Register 163" bitfld.long 0x25C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x25C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x260 "MAR164,Memory Attribute Register 164" bitfld.long 0x260 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x260 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x264 "MAR165,Memory Attribute Register 165" bitfld.long 0x264 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x264 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x268 "MAR166,Memory Attribute Register 166" bitfld.long 0x268 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x268 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x26C "MAR167,Memory Attribute Register 167" bitfld.long 0x26C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x26C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x270 "MAR168,Memory Attribute Register 168" bitfld.long 0x270 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x270 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x274 "MAR169,Memory Attribute Register 169" bitfld.long 0x274 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x274 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x278 "MAR170,Memory Attribute Register 170" bitfld.long 0x278 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x278 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x27C "MAR171,Memory Attribute Register 171" bitfld.long 0x27C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x27C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x280 "MAR172,Memory Attribute Register 172" bitfld.long 0x280 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x280 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x284 "MAR173,Memory Attribute Register 173" bitfld.long 0x284 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x284 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x288 "MAR174,Memory Attribute Register 174" bitfld.long 0x288 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x288 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x28C "MAR175,Memory Attribute Register 175" bitfld.long 0x28C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x28C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x290 "MAR176,Memory Attribute Register 176" bitfld.long 0x290 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x290 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x294 "MAR177,Memory Attribute Register 177" bitfld.long 0x294 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x294 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x298 "MAR178,Memory Attribute Register 178" bitfld.long 0x298 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x298 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x29C "MAR179,Memory Attribute Register 179" bitfld.long 0x29C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x29C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2A0 "MAR180,Memory Attribute Register 180" bitfld.long 0x2A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2A4 "MAR181,Memory Attribute Register 181" bitfld.long 0x2A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2A8 "MAR182,Memory Attribute Register 182" bitfld.long 0x2A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2AC "MAR183,Memory Attribute Register 183" bitfld.long 0x2AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2B0 "MAR184,Memory Attribute Register 184" bitfld.long 0x2B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2B4 "MAR185,Memory Attribute Register 185" bitfld.long 0x2B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2B8 "MAR186,Memory Attribute Register 186" bitfld.long 0x2B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2BC "MAR187,Memory Attribute Register 187" bitfld.long 0x2BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C0 "MAR188,Memory Attribute Register 188" bitfld.long 0x2C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C4 "MAR189,Memory Attribute Register 189" bitfld.long 0x2C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2C8 "MAR190,Memory Attribute Register 190" bitfld.long 0x2C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2CC "MAR191,Memory Attribute Register 191" bitfld.long 0x2CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2D0 "MAR192,Memory Attribute Register 192" bitfld.long 0x2D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2D0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2D4 "MAR193,Memory Attribute Register 193" bitfld.long 0x2D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2D4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2D8 "MAR194,Memory Attribute Register 194" bitfld.long 0x2D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2D8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2DC "MAR195,Memory Attribute Register 195" bitfld.long 0x2DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2DC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2E0 "MAR196,Memory Attribute Register 196" bitfld.long 0x2E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2E0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2E4 "MAR197,Memory Attribute Register 197" bitfld.long 0x2E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2E4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2E8 "MAR198,Memory Attribute Register 198" bitfld.long 0x2E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2E8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2EC "MAR199,Memory Attribute Register 199" bitfld.long 0x2EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2EC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2F0 "MAR200,Memory Attribute Register 200" bitfld.long 0x2F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2F0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2F4 "MAR201,Memory Attribute Register 201" bitfld.long 0x2F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2F4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2F8 "MAR202,Memory Attribute Register 202" bitfld.long 0x2F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2F8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x2FC "MAR203,Memory Attribute Register 203" bitfld.long 0x2FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x2FC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x300 "MAR204,Memory Attribute Register 204" bitfld.long 0x300 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x300 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x304 "MAR205,Memory Attribute Register 205" bitfld.long 0x304 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x304 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x308 "MAR206,Memory Attribute Register 206" bitfld.long 0x308 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x308 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x30C "MAR207,Memory Attribute Register 207" bitfld.long 0x30C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x30C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x310 "MAR208,Memory Attribute Register 208" bitfld.long 0x310 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x310 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x314 "MAR209,Memory Attribute Register 209" bitfld.long 0x314 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x314 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x318 "MAR210,Memory Attribute Register 210" bitfld.long 0x318 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x318 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x31C "MAR211,Memory Attribute Register 211" bitfld.long 0x31C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x31C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x320 "MAR212,Memory Attribute Register 212" bitfld.long 0x320 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x320 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x324 "MAR213,Memory Attribute Register 213" bitfld.long 0x324 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x324 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x328 "MAR214,Memory Attribute Register 214" bitfld.long 0x328 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x328 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x32C "MAR215,Memory Attribute Register 215" bitfld.long 0x32C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x32C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x330 "MAR216,Memory Attribute Register 216" bitfld.long 0x330 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x330 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x334 "MAR217,Memory Attribute Register 217" bitfld.long 0x334 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x334 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x338 "MAR218,Memory Attribute Register 218" bitfld.long 0x338 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x338 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x33C "MAR219,Memory Attribute Register 219" bitfld.long 0x33C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x33C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x340 "MAR220,Memory Attribute Register 220" bitfld.long 0x340 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x340 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x344 "MAR221,Memory Attribute Register 221" bitfld.long 0x344 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x344 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x348 "MAR222,Memory Attribute Register 222" bitfld.long 0x348 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x348 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x34C "MAR223,Memory Attribute Register 223" bitfld.long 0x34C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x34C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x350 "MAR224,Memory Attribute Register 224" bitfld.long 0x350 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x350 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x354 "MAR225,Memory Attribute Register 225" bitfld.long 0x354 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x354 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x358 "MAR226,Memory Attribute Register 226" bitfld.long 0x358 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x358 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x35C "MAR227,Memory Attribute Register 227" bitfld.long 0x35C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x35C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x360 "MAR228,Memory Attribute Register 228" bitfld.long 0x360 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x360 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x364 "MAR229,Memory Attribute Register 229" bitfld.long 0x364 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x364 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x368 "MAR230,Memory Attribute Register 230" bitfld.long 0x368 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x368 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x36C "MAR231,Memory Attribute Register 231" bitfld.long 0x36C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x36C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x370 "MAR232,Memory Attribute Register 232" bitfld.long 0x370 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x370 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x374 "MAR233,Memory Attribute Register 233" bitfld.long 0x374 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x374 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x378 "MAR234,Memory Attribute Register 234" bitfld.long 0x378 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x378 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x37C "MAR235,Memory Attribute Register 235" bitfld.long 0x37C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x37C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x380 "MAR236,Memory Attribute Register 236" bitfld.long 0x380 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x380 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x384 "MAR237,Memory Attribute Register 237" bitfld.long 0x384 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x384 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x388 "MAR238,Memory Attribute Register 238" bitfld.long 0x388 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x388 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x38C "MAR239,Memory Attribute Register 239" bitfld.long 0x38C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x38C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x390 "MAR240,Memory Attribute Register 240" bitfld.long 0x390 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x390 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x394 "MAR241,Memory Attribute Register 241" bitfld.long 0x394 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x394 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x398 "MAR242,Memory Attribute Register 242" bitfld.long 0x398 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x398 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x39C "MAR243,Memory Attribute Register 243" bitfld.long 0x39C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x39C 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3A0 "MAR244,Memory Attribute Register 244" bitfld.long 0x3A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3A0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3A4 "MAR245,Memory Attribute Register 245" bitfld.long 0x3A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3A4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3A8 "MAR246,Memory Attribute Register 246" bitfld.long 0x3A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3A8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3AC "MAR247,Memory Attribute Register 247" bitfld.long 0x3AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3AC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3B0 "MAR248,Memory Attribute Register 248" bitfld.long 0x3B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3B0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3B4 "MAR249,Memory Attribute Register 249" bitfld.long 0x3B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3B4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3B8 "MAR250,Memory Attribute Register 250" bitfld.long 0x3B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3B8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3BC "MAR251,Memory Attribute Register 251" bitfld.long 0x3BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3BC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C0 "MAR252,Memory Attribute Register 252" bitfld.long 0x3C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C0 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C4 "MAR253,Memory Attribute Register 253" bitfld.long 0x3C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C4 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3C8 "MAR254,Memory Attribute Register 254" bitfld.long 0x3C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3C8 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" line.long 0x3CC "MAR255,Memory Attribute Register 255" bitfld.long 0x3CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable" bitfld.long 0x3CC 0. " PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable" tree.end width 10. base d:0x0184a000 tree "Memory Protection Page Attribute Registers" group.long 0x200++0x7f line.long 0x0 "L2MPPA0,Level 2 Memory Protection Page Attribute Register 0" bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x0 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x0 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x0 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x0 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x0 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x0 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x0 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x0 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x0 2. " UR ,User read access type" "Normal,User" bitfld.long 0x0 1. " UW ,User write access type" "Normal,User" bitfld.long 0x0 0. " UX ,User execute access type" "Normal,User" line.long 0x4 "L2MPPA1,Level 2 Memory Protection Page Attribute Register 1" bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x4 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x4 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x4 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4 1. " UW ,User write access type" "Normal,User" bitfld.long 0x4 0. " UX ,User execute access type" "Normal,User" line.long 0x8 "L2MPPA2,Level 2 Memory Protection Page Attribute Register 2" bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x8 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x8 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x8 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x8 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x8 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x8 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x8 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x8 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x8 2. " UR ,User read access type" "Normal,User" bitfld.long 0x8 1. " UW ,User write access type" "Normal,User" bitfld.long 0x8 0. " UX ,User execute access type" "Normal,User" line.long 0xC "L2MPPA3,Level 2 Memory Protection Page Attribute Register 3" bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0xC 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0xC 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0xC 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0xC 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0xC 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0xC 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0xC 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0xC 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0xC 2. " UR ,User read access type" "Normal,User" bitfld.long 0xC 1. " UW ,User write access type" "Normal,User" bitfld.long 0xC 0. " UX ,User execute access type" "Normal,User" line.long 0x10 "L2MPPA4,Level 2 Memory Protection Page Attribute Register 4" bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x10 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x10 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x10 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x10 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x10 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x10 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x10 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x10 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x10 2. " UR ,User read access type" "Normal,User" bitfld.long 0x10 1. " UW ,User write access type" "Normal,User" bitfld.long 0x10 0. " UX ,User execute access type" "Normal,User" line.long 0x14 "L2MPPA5,Level 2 Memory Protection Page Attribute Register 5" bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x14 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x14 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x14 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x14 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x14 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x14 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x14 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x14 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x14 2. " UR ,User read access type" "Normal,User" bitfld.long 0x14 1. " UW ,User write access type" "Normal,User" bitfld.long 0x14 0. " UX ,User execute access type" "Normal,User" line.long 0x18 "L2MPPA6,Level 2 Memory Protection Page Attribute Register 6" bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x18 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x18 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x18 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x18 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x18 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x18 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x18 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x18 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x18 2. " UR ,User read access type" "Normal,User" bitfld.long 0x18 1. " UW ,User write access type" "Normal,User" bitfld.long 0x18 0. " UX ,User execute access type" "Normal,User" line.long 0x1C "L2MPPA7,Level 2 Memory Protection Page Attribute Register 7" bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x1C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x1C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x1C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x1C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x1C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x1C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x1C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x1C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x1C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x1C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x1C 0. " UX ,User execute access type" "Normal,User" line.long 0x20 "L2MPPA8,Level 2 Memory Protection Page Attribute Register 8" bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x20 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x20 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x20 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x20 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x20 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x20 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x20 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x20 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x20 2. " UR ,User read access type" "Normal,User" bitfld.long 0x20 1. " UW ,User write access type" "Normal,User" bitfld.long 0x20 0. " UX ,User execute access type" "Normal,User" line.long 0x24 "L2MPPA9,Level 2 Memory Protection Page Attribute Register 9" bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x24 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x24 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x24 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x24 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x24 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x24 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x24 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x24 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x24 2. " UR ,User read access type" "Normal,User" bitfld.long 0x24 1. " UW ,User write access type" "Normal,User" bitfld.long 0x24 0. " UX ,User execute access type" "Normal,User" line.long 0x28 "L2MPPA10,Level 2 Memory Protection Page Attribute Register 10" bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x28 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x28 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x28 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x28 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x28 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x28 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x28 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x28 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x28 2. " UR ,User read access type" "Normal,User" bitfld.long 0x28 1. " UW ,User write access type" "Normal,User" bitfld.long 0x28 0. " UX ,User execute access type" "Normal,User" line.long 0x2C "L2MPPA11,Level 2 Memory Protection Page Attribute Register 11" bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x2C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x2C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x2C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x2C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x2C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x2C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x2C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x2C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x2C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x2C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x2C 0. " UX ,User execute access type" "Normal,User" line.long 0x30 "L2MPPA12,Level 2 Memory Protection Page Attribute Register 12" bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x30 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x30 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x30 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x30 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x30 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x30 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x30 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x30 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x30 2. " UR ,User read access type" "Normal,User" bitfld.long 0x30 1. " UW ,User write access type" "Normal,User" bitfld.long 0x30 0. " UX ,User execute access type" "Normal,User" line.long 0x34 "L2MPPA13,Level 2 Memory Protection Page Attribute Register 13" bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x34 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x34 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x34 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x34 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x34 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x34 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x34 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x34 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x34 2. " UR ,User read access type" "Normal,User" bitfld.long 0x34 1. " UW ,User write access type" "Normal,User" bitfld.long 0x34 0. " UX ,User execute access type" "Normal,User" line.long 0x38 "L2MPPA14,Level 2 Memory Protection Page Attribute Register 14" bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x38 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x38 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x38 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x38 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x38 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x38 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x38 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x38 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x38 2. " UR ,User read access type" "Normal,User" bitfld.long 0x38 1. " UW ,User write access type" "Normal,User" bitfld.long 0x38 0. " UX ,User execute access type" "Normal,User" line.long 0x3C "L2MPPA15,Level 2 Memory Protection Page Attribute Register 15" bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x3C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x3C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x3C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x3C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x3C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x3C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x3C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x3C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x3C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x3C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x3C 0. " UX ,User execute access type" "Normal,User" line.long 0x40 "L2MPPA16,Level 2 Memory Protection Page Attribute Register 16" bitfld.long 0x40 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x40 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x40 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x40 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x40 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x40 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x40 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x40 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x40 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x40 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x40 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x40 2. " UR ,User read access type" "Normal,User" bitfld.long 0x40 1. " UW ,User write access type" "Normal,User" bitfld.long 0x40 0. " UX ,User execute access type" "Normal,User" line.long 0x44 "L2MPPA17,Level 2 Memory Protection Page Attribute Register 17" bitfld.long 0x44 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x44 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x44 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x44 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x44 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x44 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x44 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x44 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x44 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x44 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x44 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x44 2. " UR ,User read access type" "Normal,User" bitfld.long 0x44 1. " UW ,User write access type" "Normal,User" bitfld.long 0x44 0. " UX ,User execute access type" "Normal,User" line.long 0x48 "L2MPPA18,Level 2 Memory Protection Page Attribute Register 18" bitfld.long 0x48 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x48 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x48 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x48 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x48 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x48 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x48 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x48 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x48 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x48 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x48 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x48 2. " UR ,User read access type" "Normal,User" bitfld.long 0x48 1. " UW ,User write access type" "Normal,User" bitfld.long 0x48 0. " UX ,User execute access type" "Normal,User" line.long 0x4C "L2MPPA19,Level 2 Memory Protection Page Attribute Register 19" bitfld.long 0x4C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x4C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x4C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x4C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x4C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x4C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x4C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x4C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x4C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x4C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x4C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x4C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x4C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x4C 0. " UX ,User execute access type" "Normal,User" line.long 0x50 "L2MPPA20,Level 2 Memory Protection Page Attribute Register 20" bitfld.long 0x50 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x50 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x50 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x50 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x50 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x50 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x50 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x50 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x50 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x50 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x50 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x50 2. " UR ,User read access type" "Normal,User" bitfld.long 0x50 1. " UW ,User write access type" "Normal,User" bitfld.long 0x50 0. " UX ,User execute access type" "Normal,User" line.long 0x54 "L2MPPA21,Level 2 Memory Protection Page Attribute Register 21" bitfld.long 0x54 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x54 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x54 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x54 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x54 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x54 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x54 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x54 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x54 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x54 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x54 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x54 2. " UR ,User read access type" "Normal,User" bitfld.long 0x54 1. " UW ,User write access type" "Normal,User" bitfld.long 0x54 0. " UX ,User execute access type" "Normal,User" line.long 0x58 "L2MPPA22,Level 2 Memory Protection Page Attribute Register 22" bitfld.long 0x58 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x58 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x58 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x58 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x58 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x58 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x58 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x58 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x58 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x58 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x58 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x58 2. " UR ,User read access type" "Normal,User" bitfld.long 0x58 1. " UW ,User write access type" "Normal,User" bitfld.long 0x58 0. " UX ,User execute access type" "Normal,User" line.long 0x5C "L2MPPA23,Level 2 Memory Protection Page Attribute Register 23" bitfld.long 0x5C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x5C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x5C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x5C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x5C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x5C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x5C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x5C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x5C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x5C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x5C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x5C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x5C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x5C 0. " UX ,User execute access type" "Normal,User" line.long 0x60 "L2MPPA24,Level 2 Memory Protection Page Attribute Register 24" bitfld.long 0x60 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x60 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x60 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x60 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x60 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x60 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x60 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x60 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x60 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x60 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x60 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x60 2. " UR ,User read access type" "Normal,User" bitfld.long 0x60 1. " UW ,User write access type" "Normal,User" bitfld.long 0x60 0. " UX ,User execute access type" "Normal,User" line.long 0x64 "L2MPPA25,Level 2 Memory Protection Page Attribute Register 25" bitfld.long 0x64 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x64 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x64 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x64 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x64 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x64 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x64 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x64 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x64 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x64 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x64 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x64 2. " UR ,User read access type" "Normal,User" bitfld.long 0x64 1. " UW ,User write access type" "Normal,User" bitfld.long 0x64 0. " UX ,User execute access type" "Normal,User" line.long 0x68 "L2MPPA26,Level 2 Memory Protection Page Attribute Register 26" bitfld.long 0x68 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x68 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x68 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x68 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x68 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x68 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x68 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x68 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x68 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x68 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x68 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x68 2. " UR ,User read access type" "Normal,User" bitfld.long 0x68 1. " UW ,User write access type" "Normal,User" bitfld.long 0x68 0. " UX ,User execute access type" "Normal,User" line.long 0x6C "L2MPPA27,Level 2 Memory Protection Page Attribute Register 27" bitfld.long 0x6C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x6C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x6C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x6C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x6C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x6C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x6C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x6C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x6C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x6C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x6C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x6C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x6C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x6C 0. " UX ,User execute access type" "Normal,User" line.long 0x70 "L2MPPA28,Level 2 Memory Protection Page Attribute Register 28" bitfld.long 0x70 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x70 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x70 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x70 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x70 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x70 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x70 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x70 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x70 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x70 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x70 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x70 2. " UR ,User read access type" "Normal,User" bitfld.long 0x70 1. " UW ,User write access type" "Normal,User" bitfld.long 0x70 0. " UX ,User execute access type" "Normal,User" line.long 0x74 "L2MPPA29,Level 2 Memory Protection Page Attribute Register 29" bitfld.long 0x74 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x74 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x74 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x74 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x74 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x74 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x74 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x74 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x74 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x74 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x74 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x74 2. " UR ,User read access type" "Normal,User" bitfld.long 0x74 1. " UW ,User write access type" "Normal,User" bitfld.long 0x74 0. " UX ,User execute access type" "Normal,User" line.long 0x78 "L2MPPA30,Level 2 Memory Protection Page Attribute Register 30" bitfld.long 0x78 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x78 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x78 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x78 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x78 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x78 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x78 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x78 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x78 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x78 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x78 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x78 2. " UR ,User read access type" "Normal,User" bitfld.long 0x78 1. " UW ,User write access type" "Normal,User" bitfld.long 0x78 0. " UX ,User execute access type" "Normal,User" line.long 0x7C "L2MPPA31,Level 2 Memory Protection Page Attribute Register 31" bitfld.long 0x7C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted" bitfld.long 0x7C 14. " AID4 ,Controls access from ID = 4" "Denied,Granted" bitfld.long 0x7C 13. " AID3 ,Controls access from ID = 3 " "Denied,Granted" textline " " bitfld.long 0x7C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted" bitfld.long 0x7C 11. " AID1 ,Controls access from ID = 1" "Denied,Granted" bitfld.long 0x7C 10. " AID0 ,Controls access from ID = 0" "Denied,Granted" textline " " bitfld.long 0x7C 9. " AIDX ,Controls ID >=6" "Denied,Granted" bitfld.long 0x7C 8. " LOCAL ,Controls access from CPU to local memories" "Denied,Granted" textline " " bitfld.long 0x7C 5. " SR ,Supervisor read access type" "Normal,Supervisor" bitfld.long 0x7C 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x7C 3. " SX ,Supervisor execute access type" "Normal,Supervisor" textline " " bitfld.long 0x7C 2. " UR ,User read access type" "Normal,User" bitfld.long 0x7C 1. " UW ,User write access type" "Normal,User" bitfld.long 0x7C 0. " UX ,User execute access type" "Normal,User" tree.end width 9. rgroup.long 0x000++0x7 "Memory Protection Fault Registers" line.long 0x00 "L2MPFAR,Level 2 Memory Protection Fault Address Register" hexmask.long 0x00 0.--31. 1. " FA ,Fault Address" line.long 0x04 "L2MPFSR,Level 2 Memory Protection Fault Set Register" hexmask.long.byte 0x04 9.--15. 1. " FID ,Bit 6:0 of ID of faulting requestor" bitfld.long 0x04 8. " LOCAL ,Local access" "Normal,Supervisor" bitfld.long 0x04 5. " SR ,Supervisor read access type" "Normal,Supervisor" textline " " bitfld.long 0x04 4. " SW ,Supervisor write access type" "Normal,Supervisor" bitfld.long 0x04 2. " UR ,User read access type" "Normal,User" bitfld.long 0x04 1. " UW ,User write access type" "Normal,User" group.long 0x008++0x3 line.long 0x00 "L2MPFCR,Level 2 Memory Protection Fault Clear Register" eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Clear" width 12. wgroup.long 0x100++0xf "Memory Protection Lock Registers" line.long 0x00 "L2MPLK0,Level 2 Memory Protection Lock 0" hexmask.long 0x00 0.--31. 1. " LB ,Lock Bits 31:0" line.long 0x04 "L2MPLK1,Level 2 Memory Protection Lock 1" hexmask.long 0x04 0.--31. 1. " LB ,Lock Bits 63:32" line.long 0x08 "L2MPLK2,Level 2 Memory Protection Lock 2" hexmask.long 0x08 0.--31. 1. " LB ,Lock Bits 95:64" line.long 0x0c "L2MPLK3,Level 2 Memory Protection Lock 3" hexmask.long 0x0c 0.--31. 1. " LB ,Lock Bits 127:96" wgroup.long 0x110++0x3 line.long 0x00 "L2MPLKCMD,Level 2 Memory Protection Lock Command Register" bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset" bitfld.long 0x00 1. " LOCK ,Interface to complete a lock sequence" "No effect,Locked" bitfld.long 0x00 0. " UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked" rgroup.long 0x114++0x3 line.long 0x00 "L2MPLKSTAT,Level 2 Memory Protection Lock Status Register" bitfld.long 0x00 0. " LK ,Indicates the lock's current status" "Disengaged,Engaged" AUTOINDENT.ON right tree base d:0x01846000 rgroup.long 0x4++0x3 "Error Detection Registers" line.long 0x0 "L2EDSTAT,L2 Error Detection Status Register" decmask.long.byte 0x0 16.--23. "BITPOS,Single Bit error position" bitfld.long 0x0 8.--9. "NERR" "Single Bit error,Double Bit error,,Error in parity value" newline bitfld.long 0x0 7. "VERR,Error occurred on L2 victims" "False,True" bitfld.long 0x0 6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True" bitfld.long 0x0 5. "PERR,Program fetch resulted in parity check error" "False,True" newline bitfld.long 0x0 3. "SUSP,Error detection logic is suspended" "False,True" bitfld.long 0x0 2. "DIS,Error detection logic is disabled" "False,True" bitfld.long 0x0 0. "EN,Error detection logic is enabled" "False,True" group.long 0x8++0x3 line.long 0x0 "L2EDCMD, L2 Error Detection Command Register" bitfld.long 0x0 7. "VCLR,Clears the victim parity error status" "No effect,Clear" bitfld.long 0x0 6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear" bitfld.long 0x0 5. "PCLR,Clears the program fetch parity error status" "No effect,Clear" bitfld.long 0x0 4. "DCLR,Clears the data fetch parity error status" "No effect,Clear" newline bitfld.long 0x0 3. "SUSP,Suspends the error detection logic" "No effect,Suspend" bitfld.long 0x0 2. "DIS,Disables the error detection logic" "No effect,Disable" bitfld.long 0x0 0. "EN,Enables the error detection logic" "No effect,Enable" rgroup.long 0xC++0x3 line.long 0x0 "L2EDADDR,L2 Error Detection Address Register" hexmask.long.long 0x0 5.--31. 32. "ADDR,Address of parity error (5 LSBs assumed to be 00000b)" bitfld.long 0x0 8.--9. "L2WAY,Error detected in Way" "Way 0,Way 1,Way 2,Way 3" bitfld.long 0x0 0. "RAM,Location where error was detected" "L2,RAM" rgroup.long 0x18++0x3 line.long 0x0 "L2EDCPEC,L2 Error Detection Correctable Parity Error Counter Register" hexmask.long.byte 0x0 0.--7. "CNT,Counter value" rgroup.long 0x1C++0x3 line.long 0x0 "L2EDNPEC,L2 Error Detection Non-correctable Parity Error Counter Register" hexmask.long.byte 0x0 0.--7. "CNT,Counter value" group.long 0x30++0x3 line.long 0x0 "L2EDCEN,L2 Error Detection and Correction Enable Register" bitfld.long 0x0 0. "SDMAEN,EDC on SDMA read from L2 RAM" "Disabled,Enabled" bitfld.long 0x0 0. "PL2SEN,EDC on L1P memory controller read from L2 RAM" "Disabled,Enabled" bitfld.long 0x0 0. "DL2SEN,EDC on L1D memory controller read from L2 RAM" "Disabled,Enabled" bitfld.long 0x0 0. "PL2CEN,EDC on L1P memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled" bitfld.long 0x0 0. "DL2CEN,EDC on L1D memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled" AUTOINDENT.OFF width 0xb tree.end tree.end tree "IDMA (Internal Direct Memory Access Controller)" width 14. base d:0x01820000 rgroup.long 0x00++0x3 "Channel 0" line.long 0x00 "IDMA0_STAT,IDMA Channel 0 Status Register" bitfld.long 0x00 1. " PEND ,Pending transfer" "Not pending,Pending" bitfld.long 0x00 0. " ACTV ,Active transfer" "Not active,Active" group.long 0x04++0xf line.long 0x00 "IDMA0_MASK,IDMA Channel 0 Mask Register" bitfld.long 0x00 31. " M31 ,Mask bit 31" "Not masked,Masked" bitfld.long 0x00 30. " M30 ,Mask bit 30" "Not masked,Masked" bitfld.long 0x00 29. " M29 ,Mask bit 29" "Not masked,Masked" textline " " bitfld.long 0x00 28. " M28 ,Mask bit 28" "Not masked,Masked" bitfld.long 0x00 27. " M27 ,Mask bit 27" "Not masked,Masked" bitfld.long 0x00 26. " M26 ,Mask bit 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " M25 ,Mask bit 25" "Not masked,Masked" bitfld.long 0x00 24. " M24 ,Mask bit 24" "Not masked,Masked" bitfld.long 0x00 23. " M23 ,Mask bit 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " M22 ,Mask bit 22" "Not masked,Masked" bitfld.long 0x00 21. " M21 ,Mask bit 21" "Not masked,Masked" bitfld.long 0x00 20. " M20 ,Mask bit 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " M19 ,Mask bit 19" "Not masked,Masked" bitfld.long 0x00 18. " M18 ,Mask bit 18" "Not masked,Masked" bitfld.long 0x00 17. " M17 ,Mask bit 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " M16 ,Mask bit 16" "Not masked,Masked" bitfld.long 0x00 15. " M15 ,Mask bit 15" "Not masked,Masked" bitfld.long 0x00 14. " M14 ,Mask bit 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " M13 ,Mask bit 13" "Not masked,Masked" bitfld.long 0x00 12. " M12 ,Mask bit 12" "Not masked,Masked" bitfld.long 0x00 11. " M11 ,Mask bit 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " M10 ,Mask bit 10" "Not masked,Masked" bitfld.long 0x00 9. " M9 ,Mask bit 9" "Not masked,Masked" bitfld.long 0x00 8. " M8 ,Mask bit 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " M7 ,Mask bit 7" "Not masked,Masked" bitfld.long 0x00 6. " M6 ,Mask bit 6" "Not masked,Masked" bitfld.long 0x00 5. " M5 ,Mask bit 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " M4 ,Mask bit 4" "Not masked,Masked" bitfld.long 0x00 3. " M3 ,Mask bit 3" "Not masked,Masked" bitfld.long 0x00 2. " M2 ,Mask bit 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " M1 ,Mask bit 1" "Not masked,Masked" bitfld.long 0x00 0. " M0 ,Mask bit 0" "Not masked,Masked" line.long 0x04 "IDMA0_SOURCE,IDMA Channel 0 Source Address Register" hexmask.long 0x04 5.--31. 0x20 " SOURCEADDR ,Source address" line.long 0x08 "IDMA0_DEST,IDMA Channel 0 Destination Address Register" hexmask.long 0x08 5.--31. 0x20 " DESTADDR ,Destination address" line.long 0x0c "IDMA0_COUNT,IDMA Channel 0 Count Register" bitfld.long 0x0c 28. " INT ,CPU interrupt enable" "Disabled,Enabled" bitfld.long 0x0c 0.--3. " COUNT ,4-bit block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" rgroup.long 0x100++0x3 "Channel 1" line.long 0x00 "IDMA1_STAT,IDMA Channel 1 Status Register" bitfld.long 0x00 1. " PEND ,Pending transfer" "Not pending,Pending" bitfld.long 0x00 0. " ACTV ,Active transfer" "Not active,Active" group.long 0x108++0xb line.long 0x00 "IDMA1_SOURCE,IDMA Channel 1 Source Address Register" hexmask.long 0x00 0.--31. 1. " SOURCEADDR ,Source address" line.long 0x04 "IDMA1_DEST,IDMA Channel 1 Destination Address Register" hexmask.long 0x04 2.--31. 0x4 " DESTADDR ,Destination address" line.long 0x08 "IDMA1_COUNT,IDMA Channel 1 Count Register" bitfld.long 0x08 29.--31. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest" bitfld.long 0x08 28. " INT ,CPU interrupt enable" "Disabled,Enabled" bitfld.long 0x08 16. " FILL ,Block fill" "0,1" textline " " hexmask.long.word 0x08 0.--15. 1. " COUNT ,Byte count" width 0xb tree.end tree "XMC (Extended Memory Controller)" width 14. AUTOINDENT.ON right tree base d:0x08000000 group.long 0x00++0x7F "XMC MPAX Segment Registers" line.long 0x0 "XMPAXL0,MPAX segment 0 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x0 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x0 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x0 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x0 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x0 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x0 0. "UX,User mode may execute from segment" "False,True" line.long 0x0+0x4 "XMPAXH0,MPAX segment 0 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x0 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x8 "XMPAXL1,MPAX segment 1 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x8 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x8 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x8 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x8 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x8 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x8 0. "UX,User mode may execute from segment" "False,True" line.long 0x8+0x4 "XMPAXH1,MPAX segment 1 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x8 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x10 "XMPAXL2,MPAX segment 2 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x10 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x10 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x10 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x10 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x10 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x10 0. "UX,User mode may execute from segment" "False,True" line.long 0x10+0x4 "XMPAXH2,MPAX segment 2 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x10 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x18 "XMPAXL3,MPAX segment 3 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x18 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x18 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x18 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x18 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x18 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x18 0. "UX,User mode may execute from segment" "False,True" line.long 0x18+0x4 "XMPAXH3,MPAX segment 3 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x18 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x20 "XMPAXL4,MPAX segment 4 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x20 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x20 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x20 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x20 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x20 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x20 0. "UX,User mode may execute from segment" "False,True" line.long 0x20+0x4 "XMPAXH4,MPAX segment 4 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x20 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x28 "XMPAXL5,MPAX segment 5 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x28 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x28 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x28 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x28 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x28 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x28 0. "UX,User mode may execute from segment" "False,True" line.long 0x28+0x4 "XMPAXH5,MPAX segment 5 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x28 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x30 "XMPAXL6,MPAX segment 6 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x30 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x30 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x30 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x30 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x30 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x30 0. "UX,User mode may execute from segment" "False,True" line.long 0x30+0x4 "XMPAXH6,MPAX segment 6 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x30 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x38 "XMPAXL7,MPAX segment 7 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x38 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x38 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x38 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x38 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x38 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x38 0. "UX,User mode may execute from segment" "False,True" line.long 0x38+0x4 "XMPAXH7,MPAX segment 7 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x38 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x40 "XMPAXL8,MPAX segment 8 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x40 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x40 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x40 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x40 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x40 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x40 0. "UX,User mode may execute from segment" "False,True" line.long 0x40+0x4 "XMPAXH8,MPAX segment 8 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x40 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x48 "XMPAXL9,MPAX segment 9 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x48 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x48 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x48 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x48 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x48 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x48 0. "UX,User mode may execute from segment" "False,True" line.long 0x48+0x4 "XMPAXH9,MPAX segment 9 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x48 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x50 "XMPAXL10,MPAX segment 10 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x50 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x50 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x50 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x50 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x50 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x50 0. "UX,User mode may execute from segment" "False,True" line.long 0x50+0x4 "XMPAXH10,MPAX segment 10 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x50 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x58 "XMPAXL11,MPAX segment 11 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x58 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x58 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x58 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x58 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x58 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x58 0. "UX,User mode may execute from segment" "False,True" line.long 0x58+0x4 "XMPAXH11,MPAX segment 11 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x58 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x60 "XMPAXL12,MPAX segment 12 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x60 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x60 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x60 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x60 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x60 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x60 0. "UX,User mode may execute from segment" "False,True" line.long 0x60+0x4 "XMPAXH12,MPAX segment 12 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x60 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x68 "XMPAXL13,MPAX segment 13 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x68 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x68 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x68 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x68 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x68 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x68 0. "UX,User mode may execute from segment" "False,True" line.long 0x68+0x4 "XMPAXH13,MPAX segment 13 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x68 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x70 "XMPAXL14,MPAX segment 14 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x70 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x70 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x70 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x70 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x70 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x70 0. "UX,User mode may execute from segment" "False,True" line.long 0x70+0x4 "XMPAXH14,MPAX segment 14 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x70 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" line.long 0x78 "XMPAXL15,MPAX segment 15 low register" hexmask.long 0x0 8.--31. "RADDR,Bits that replace and extend the upper address bits matched by BADDR" bitfld.long 0x78 5. "SR,Supervisor mode may read from segment" "False,True" bitfld.long 0x78 4. "SW,Supervisor mode may write to segment" "False,True" bitfld.long 0x78 3. "SX,Supervisor mode may execute from segment" "False,True" bitfld.long 0x78 2. "UR,User mode may read from segment" "False,True" bitfld.long 0x78 1. "UW,User mode may write to segment" "False,True" bitfld.long 0x78 0. "UX,User mode may execute from segment" "False,True" line.long 0x78+0x4 "XMPAXH15,MPAX segment 15 high register" hexmask.long 0x0 12.--31. "BADDR,Base Address" bitfld.long 0x78 0.--4. "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" textline "" rgroup.long 0x200++0x3 "Memory Protection Fault Reporting Registers" line.long 0. "XMPFAR,Memory Protection Fault Address Register" hexmask.long 0x0 0.--31. "Fault Address,Fault Address" rgroup.long 0x204++0x3 line.long 0. "XMPFSR,Memory Protection Fault Status Register" bitfld.long 0. 8. "LOCAL,Access was a LOCAL access" "False,True" bitfld.long 0. 5. "SR,When set, indicates a supervisor read request" "False,True" bitfld.long 0. 4. "SW,When set, indicates a supervisor write request" "False,True" bitfld.long 0. 3. "SX,When set, indicates a supervisor program fetch request" "False,True" bitfld.long 0. 2. "UR,When set, indicates a user read request" "False,True" bitfld.long 0. 1. "UW,When set, indicates a user write request" "False,True" bitfld.long 0. 0. "UX,When set, indicates a user program fetch request" "False,True" group.long 0x208++0x3 line.long 0. "XMPFCR,Memory Protection Fault Clear Register" bitfld.long 0. 0. "MPFCLR,Clear fault" "No effect,Clear" group.long 0x280++0x3 "Prefetch Priority Register" line.long 0. "MDMAARBX,MDMA Arbitration Priority Register" bitfld.long 0. 16.--18. "PRI,Priority" "0 (highest),1,2,3,4,5,6,7 (lowest)" rgroup.long 0x300++0x3 "Prefetch Buffer Registers" line.long 0. "XPFCMD,Prefetch Command Register" bitfld.long 0. 4. "ACRST,Analysis Counter Reset" "No effect,Reset" hexmask.long.byte 0. 2.--3. "ACEN,Analysis Counter Enable" bitfld.long 0. 1. "ACENL,Analysis Counter ENable (ACEN) Load" "False,True" bitfld.long 0. 0. "INV,Invalidate prefetch buffer contents" "No effect,Invalidate" rgroup.long 0x304++0x3 "Prefetch Buffer Performance Analysis Registers" line.long 0. "XPFACS,Prefetch Analysis Counter Status" rgroup.long 0x310++0xF line.long 0x0 "XPFAC0,Prefetch Analysis Counter 0" line.long 0x4 "XPFAC1,Prefetch Analysis Counter 1" line.long 0x8 "XPFAC2,Prefetch Analysis Counter 2" line.long 0xC "XPFAC3,Prefetch Analysis Counter 3" rgroup.long 0x400++0x1F line.long 0x0 "XPFADDR0,Prefetch Address for Slot 0" line.long 0x4 "XPFADDR1,Prefetch Address for Slot 1" line.long 0x8 "XPFADDR2,Prefetch Address for Slot 2" line.long 0xC "XPFADDR3,Prefetch Address for Slot 3" line.long 0x10 "XPFADDR4,Prefetch Address for Slot 4" line.long 0x14 "XPFADDR5,Prefetch Address for Slot 5" line.long 0x18 "XPFADDR6,Prefetch Address for Slot 6" line.long 0x1C "XPFADDR7,Prefetch Address for Slot 7" AUTOINDENT.OFF width 0xb tree.end tree "Bandwith Management" width 13. base d:0x01841000 group.long 0x40++0xf "L1D" line.long 0x00 "CPUARBD,L1D CPU Arbitration Control Register" bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x04 "IDMAARBD,L1D IDMA Arbitration Control Register" bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x08 "SDMAARBD,L1D Slave DMA Arbitration Control Register" bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x0c "UCARBD,L1D User Coherence Arbitration Control Register" bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." width 13. group.long 0x00++0xf "L2" line.long 0x00 "CPUARBU,L2D CPU Arbitration Control Register" bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x04 "IDMAARBU,L1D IDMA Arbitration Control Register" bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x08 "SDMAARBU,L1D Slave DMA Arbitration Control Register" bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x0c "UCARBU,L1D User Coherence Arbitration Control Register" bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." width 13. base d:0x01820000 group.long 0x200++0xf "EMC" line.long 0x00 "CPUARBE,EMC CPU Arbitration Control Register" bitfld.long 0x00 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" bitfld.long 0x00 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x04 "IDMAARBE,EMC IDMA Arbitration Control Register" bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x08 "SDMAARBE,EMC Slave DMA Arbitration Control Register" bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..." line.long 0x0c "MDMAARBE,EMC Master DMA Arbitration Control Register" bitfld.long 0x0c 16.--18. " PRI ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest" width 0xb tree.end tree "Interrupt Controller" width 11. base d:0x01800000 group.long 0x00++0xf line.long 0x00 "EVTFLAG0,Event Flag Register 0" setclrfld.long 0x00 14. 0x20 14. 0x40 14. " EF14_set/clr ,State of event EVT14" "Not occurred,Occurred" setclrfld.long 0x00 13. 0x20 13. 0x40 13. " EF13_set/clr ,State of event EVT13" "Not occurred,Occurred" textline " " setclrfld.long 0x00 12. 0x20 12. 0x40 12. " EF12_set/clr ,State of event EVT12" "Not occurred,Occurred" setclrfld.long 0x00 11. 0x20 11. 0x40 11. " EF11_set/clr ,State of event EVT11" "Not occurred,Occurred" textline " " setclrfld.long 0x00 9. 0x20 9. 0x40 9. " EF9_set/clr ,State of event EVT9" "Not occurred,Occurred" setclrfld.long 0x00 8. 0x20 8. 0x40 8. " EF8_set/clr ,State of event EVT8" "Not occurred,Occurred" textline " " setclrfld.long 0x00 7. 0x20 7. 0x40 7. " EF7_set/clr ,State of event EVT7" "Not occurred,Occurred" setclrfld.long 0x00 6. 0x20 6. 0x40 6. " EF6_set/clr ,State of event EVT6" "Not occurred,Occurred" textline " " setclrfld.long 0x00 5. 0x20 5. 0x40 5. " EF5_set/clr ,State of event EVT5" "Not occurred,Occurred" setclrfld.long 0x00 4. 0x20 4. 0x40 4. " EF4_set/clr ,State of event EVT4" "Not occurred,Occurred" textline " " setclrfld.long 0x00 3. 0x20 3. 0x40 3. " EF3_set/clr ,State of event EVT3" "Not occurred,Occurred" setclrfld.long 0x00 2. 0x20 2. 0x40 2. " EF2_set/clr ,State of event EVT2" "Not occurred,Occurred" textline " " setclrfld.long 0x00 1. 0x20 1. 0x40 1. " EF1_set/clr ,State of event EVT1" "Not occurred,Occurred" setclrfld.long 0x00 0. 0x20 0. 0x40 0. " EF0_set/clr ,State of event EVT0" "Not occurred,Occurred" line.long 0x04 "EVTFLAG1,Event Flag Register 1" setclrfld.long 0x04 28. 0x24 28. 0x44 28. " EF60_set/clr ,State of event EVT60" "Not occurred,Occurred" setclrfld.long 0x04 27. 0x24 27. 0x44 27. " EF59_set/clr ,State of event EVT59" "Not occurred,Occurred" textline " " setclrfld.long 0x04 24. 0x24 24. 0x44 24. " EF56_set/clr ,State of event EVT56" "Not occurred,Occurred" setclrfld.long 0x04 23. 0x24 23. 0x44 23. " EF55_set/clr ,State of event EVT55" "Not occurred,Occurred" textline " " setclrfld.long 0x04 22. 0x24 22. 0x44 22. " EF54_set/clr ,State of event EVT54" "Not occurred,Occurred" setclrfld.long 0x04 21. 0x24 21. 0x44 21. " EF53_set/clr ,State of event EVT53" "Not occurred,Occurred" textline " " setclrfld.long 0x04 19. 0x24 19. 0x44 19. " EF51_set/clr ,State of event EVT51" "Not occurred,Occurred" setclrfld.long 0x04 18. 0x24 18. 0x44 18. " EF50_set/clr ,State of event EVT50" "Not occurred,Occurred" textline " " setclrfld.long 0x04 17. 0x24 17. 0x44 17. " EF49_set/clr ,State of event EVT49" "Not occurred,Occurred" setclrfld.long 0x04 16. 0x24 16. 0x44 16. " EF48_set/clr ,State of event EVT48" "Not occurred,Occurred" textline " " setclrfld.long 0x04 15. 0x24 15. 0x44 15. " EF47_set/clr ,State of event EVT47" "Not occurred,Occurred" setclrfld.long 0x04 11. 0x24 11. 0x44 11. " EF43_set/clr ,State of event EVT43" "Not occurred,Occurred" textline " " setclrfld.long 0x04 9. 0x24 9. 0x44 9. " EF41_set/clr ,State of event EVT41" "Not occurred,Occurred" setclrfld.long 0x04 8. 0x24 8. 0x44 8. " EF40_set/clr ,State of event EVT40" "Not occurred,Occurred" textline " " setclrfld.long 0x04 7. 0x24 7. 0x44 7. " EF39_set/clr ,State of event EVT39" "Not occurred,Occurred" setclrfld.long 0x04 6. 0x24 6. 0x44 6. " EF38_set/clr ,State of event EVT38" "Not occurred,Occurred" textline " " setclrfld.long 0x04 5. 0x24 5. 0x44 5. " EF37_set/clr ,State of event EVT37" "Not occurred,Occurred" setclrfld.long 0x04 4. 0x24 4. 0x44 4. " EF36_set/clr ,State of event EVT36" "Not occurred,Occurred" textline " " setclrfld.long 0x04 3. 0x24 3. 0x44 3. " EF35_set/clr ,State of event EVT35" "Not occurred,Occurred" setclrfld.long 0x04 2. 0x24 2. 0x44 2. " EF34_set/clr ,State of event EVT34" "Not occurred,Occurred" line.long 0x08 "EVTFLAG2,Event Flag Register 2" setclrfld.long 0x08 21. 0x28 21. 0x48 21. " EF85_set/clr ,State of event EVT85" "Not occurred,Occurred" setclrfld.long 0x08 20. 0x28 20. 0x48 20. " EF84_set/clr ,State of event EVT84" "Not occurred,Occurred" textline " " setclrfld.long 0x08 19. 0x28 19. 0x48 19. " EF83_set/clr ,State of event EVT83" "Not occurred,Occurred" setclrfld.long 0x08 18. 0x28 18. 0x48 18. " EF82_set/clr ,State of event EVT82" "Not occurred,Occurred" textline " " setclrfld.long 0x08 17. 0x28 17. 0x48 17. " EF81_set/clr ,State of event EVT81" "Not occurred,Occurred" setclrfld.long 0x08 16. 0x28 16. 0x48 16. " EF80_set/clr ,State of event EVT80" "Not occurred,Occurred" textline " " setclrfld.long 0x08 14. 0x28 14. 0x48 14. " EF78_set/clr ,State of event EVT78" "Not occurred,Occurred" setclrfld.long 0x08 13. 0x28 13. 0x48 13. " EF77_set/clr ,State of event EVT77" "Not occurred,Occurred" textline " " setclrfld.long 0x08 12. 0x28 12. 0x48 12. " EF76_set/clr ,State of event EVT76" "Not occurred,Occurred" setclrfld.long 0x08 11. 0x28 11. 0x48 11. " EF75_set/clr ,State of event EVT75" "Not occurred,Occurred" textline " " setclrfld.long 0x08 10. 0x28 10. 0x48 10. " EF74_set/clr ,State of event EVT74" "Not occurred,Occurred" setclrfld.long 0x08 9. 0x28 9. 0x48 9. " EF73_set/clr ,State of event EVT73" "Not occurred,Occurred" textline " " setclrfld.long 0x08 8. 0x28 8. 0x48 8. " EF72_set/clr ,State of event EVT72" "Not occurred,Occurred" setclrfld.long 0x08 7. 0x28 7. 0x48 7. " EF71_set/clr ,State of event EVT71" "Not occurred,Occurred" textline " " setclrfld.long 0x08 6. 0x28 6. 0x48 6. " EF70_set/clr ,State of event EVT70" "Not occurred,Occurred" setclrfld.long 0x08 5. 0x28 5. 0x48 5. " EF69_set/clr ,State of event EVT69" "Not occurred,Occurred" textline " " setclrfld.long 0x08 4. 0x28 4. 0x48 4. " EF68_set/clr ,State of event EVT68" "Not occurred,Occurred" setclrfld.long 0x08 3. 0x28 3. 0x48 3. " EF67_set/clr ,State of event EVT67" "Not occurred,Occurred" textline " " setclrfld.long 0x08 2. 0x28 2. 0x48 2. " EF66_set/clr ,State of event EVT66" "Not occurred,Occurred" setclrfld.long 0x08 1. 0x28 1. 0x48 1. " EF65_set/clr ,State of event EVT65" "Not occurred,Occurred" textline " " setclrfld.long 0x08 0. 0x28 0. 0x48 0. " EF64_set/clr ,State of event EVT64" "Not occurred,Occurred" line.long 0x0c "EVTFLAG3,Event Flag Register 3" setclrfld.long 0x0c 31. 0x2c 31. 0x4c 31. " EF127_set/clr ,State of event EVT127" "Not occurred,Occurred" setclrfld.long 0x0c 30. 0x2c 30. 0x4c 30. " EF126_set/clr ,State of event EVT126" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 29. 0x2c 29. 0x4c 29. " EF125_set/clr ,State of event EVT125" "Not occurred,Occurred" setclrfld.long 0x0c 28. 0x2c 28. 0x4c 28. " EF124_set/clr ,State of event EVT124" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 27. 0x2c 27. 0x4c 27. " EF123_set/clr ,State of event EVT123" "Not occurred,Occurred" setclrfld.long 0x0c 26. 0x2c 26. 0x4c 26. " EF122_set/clr ,State of event EVT122" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 25. 0x2c 25. 0x4c 25. " EF121_set/clr ,State of event EVT121" "Not occurred,Occurred" setclrfld.long 0x0c 24. 0x2c 24. 0x4c 24. " EF120_set/clr ,State of event EVT120" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 23. 0x2c 23. 0x4c 23. " EF119_set/clr ,State of event EVT119" "Not occurred,Occurred" setclrfld.long 0x0c 22. 0x2c 22. 0x4c 22. " EF118_set/clr ,State of event EVT118" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 21. 0x2c 21. 0x4c 21. " EF117_set/clr ,State of event EVT117" "Not occurred,Occurred" setclrfld.long 0x0c 20. 0x2c 20. 0x4c 20. " EF116_set/clr ,State of event EVT116" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 17. 0x2c 17. 0x4c 17. " EF113_set/clr ,State of event EVT113" "Not occurred,Occurred" setclrfld.long 0x0c 1. 0x2c 1. 0x4c 1. " EF97_set/clr ,State of event EVT97" "Not occurred,Occurred" textline " " setclrfld.long 0x0c 0. 0x2c 0. 0x4c 0. " EF96_set/clr ,State of event EVT96" "Not occurred,Occurred" width 11. group.long 0x80++0xf line.long 0x00 "EVTMASK0,Event Mask Register 0" bitfld.long 0x00 14. " EM14 ,Disables event EVT14 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 13. " EM13 ,Disables event EVT13 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 12. " EM12 ,Disables event EVT12 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 11. " EM11 ,Disables event EVT11 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 9. " EM9 ,Disables event EVT9 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 8. " EM8 ,Disables event EVT8 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 7. " EM7 ,Disables event EVT7 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 6. " EM6 ,Disables event EVT6 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 5. " EM5 ,Disables event EVT5 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 4. " EM4 ,Disables event EVT4 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 3. " EM3 ,Disables event EVT3 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 2. " EM2 ,Disables event EVT2 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x00 1. " EM1 ,Disables event EVT1 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x00 0. " EM0 ,Disables event EVT0 from being used as input to the event combiner" "Combined,Disabled" line.long 0x04 "EVTMASK1,Event Mask Register 1" bitfld.long 0x04 28. " EM60 ,Disables event EVT60 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 27. " EM59 ,Disables event EVT59 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 24. " EM56 ,Disables event EVT56 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 23. " EM55 ,Disables event EVT55 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 22. " EM54 ,Disables event EVT54 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 21. " EM53 ,Disables event EVT53 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 19. " EM51 ,Disables event EVT51 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 18. " EM50 ,Disables event EVT50 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 17. " EM49 ,Disables event EVT49 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 16. " EM48 ,Disables event EVT48 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 15. " EM47 ,Disables event EVT47 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 11. " EM43 ,Disables event EVT43 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 9. " EM41 ,Disables event EVT41 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 8. " EM40 ,Disables event EVT40 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 7. " EM39 ,Disables event EVT39 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 6. " EM38 ,Disables event EVT38 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 5. " EM37 ,Disables event EVT37 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 4. " EM36 ,Disables event EVT36 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x04 3. " EM35 ,Disables event EVT35 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x04 2. " EM34 ,Disables event EVT34 from being used as input to the event combiner" "Combined,Disabled" line.long 0x08 "EVTMASK2,Event Mask Register 2" bitfld.long 0x08 21. " EM85 ,Disables event EVT85 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 20. " EM84 ,Disables event EVT84 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 19. " EM83 ,Disables event EVT83 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 18. " EM82 ,Disables event EVT82 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 17. " EM81 ,Disables event EVT81 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 16. " EM80 ,Disables event EVT80 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 14. " EM78 ,Disables event EVT78 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 13. " EM77 ,Disables event EVT77 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 12. " EM76 ,Disables event EVT76 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 11. " EM75 ,Disables event EVT75 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 10. " EM74 ,Disables event EVT74 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 9. " EM73 ,Disables event EVT73 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 8. " EM72 ,Disables event EVT72 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 7. " EM71 ,Disables event EVT71 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 6. " EM70 ,Disables event EVT70 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 5. " EM69 ,Disables event EVT69 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 4. " EM68 ,Disables event EVT68 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 3. " EM67 ,Disables event EVT67 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x08 2. " EM66 ,Disables event EVT66 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 1. " EM65 ,Disables event EVT65 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x08 0. " EM64 ,Disables event EVT64 from being used as input to the event combiner" "Combined,Disabled" line.long 0x0c "EVTMASK3,Event Mask Register 3" bitfld.long 0x0c 31. " EM127 ,Disables event EVT127 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 30. " EM126 ,Disables event EVT126 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 29. " EM125 ,Disables event EVT125 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 28. " EM124 ,Disables event EVT124 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 27. " EM123 ,Disables event EVT123 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 26. " EM122 ,Disables event EVT122 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 25. " EM121 ,Disables event EVT121 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 24. " EM120 ,Disables event EVT120 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 23. " EM119 ,Disables event EVT119 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 22. " EM118 ,Disables event EVT118 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 21. " EM117 ,Disables event EVT117 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 20. " EM116 ,Disables event EVT116 from being used as input to the event combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 17. " EM113 ,Disables event EVT113 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 1. " EM97 ,Disables event EVT97 from being used as input to the event combiner" "Combined,Disabled" bitfld.long 0x0c 0. " EM96 ,Disables event EVT96 from being used as input to the event combiner" "Combined,Disabled" group.long 0xc0++0xf line.long 0x00 "EXPMASK0,Exception Mask Register 0" bitfld.long 0x00 14. " XM14 ,Event EVT14 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 13. " XM13 ,Event EVT13 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 12. " XM12 ,Event EVT12 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 11. " XM11 ,Event EVT11 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 9. " XM9 ,Event EVT9 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 8. " XM8 ,Event EVT8 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 7. " XM7 ,Event EVT7 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 6. " XM6 ,Event EVT6 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 5. " XM5 ,Event EVT5 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 4. " XM4 ,Event EVT4 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 3. " XM3 ,Event EVT3 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 2. " XM2 ,Event EVT2 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x00 1. " XM1 ,Event EVT1 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x00 0. " XM0 ,Event EVT0 disabled from being used in the exception combiner" "Combined,Disabled" line.long 0x04 "EXPMASK1,Exception Mask Register 1" bitfld.long 0x04 28. " XM60 ,Event EVT60 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 27. " XM59 ,Event EVT59 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 24. " XM56 ,Event EVT56 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 23. " XM55 ,Event EVT55 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 22. " XM54 ,Event EVT54 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 21. " XM53 ,Event EVT53 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 19. " XM51 ,Event EVT51 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 18. " XM50 ,Event EVT50 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 17. " XM49 ,Event EVT49 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 16. " XM48 ,Event EVT48 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 15. " XM47 ,Event EVT47 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 11. " XM43 ,Event EVT43 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 9. " XM41 ,Event EVT41 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 8. " XM40 ,Event EVT40 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 7. " XM39 ,Event EVT39 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 6. " XM38 ,Event EVT38 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 5. " XM37 ,Event EVT37 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 4. " XM36 ,Event EVT36 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x04 3. " XM35 ,Event EVT35 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x04 2. " XM34 ,Event EVT34 disabled from being used in the exception combiner" "Combined,Disabled" line.long 0x08 "EXPMASK2,Exception Mask Register 2" bitfld.long 0x08 21. " XM85 ,Event EVT85 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 20. " XM84 ,Event EVT84 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 19. " XM83 ,Event EVT83 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 18. " XM82 ,Event EVT82 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 17. " XM81 ,Event EVT81 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 16. " XM80 ,Event EVT80 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 14. " XM78 ,Event EVT78 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 13. " XM77 ,Event EVT77 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 12. " XM76 ,Event EVT76 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 11. " XM75 ,Event EVT75 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 10. " XM74 ,Event EVT74 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 9. " XM73 ,Event EVT73 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 8. " XM72 ,Event EVT72 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 7. " XM71 ,Event EVT71 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 6. " XM70 ,Event EVT70 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 5. " XM69 ,Event EVT69 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 4. " XM68 ,Event EVT68 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 3. " XM67 ,Event EVT67 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x08 2. " XM66 ,Event EVT66 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 1. " XM65 ,Event EVT65 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x08 0. " XM64 ,Event EVT64 disabled from being used in the exception combiner" "Combined,Disabled" line.long 0x0c "EXPMASK3,Exception Mask Register 3" bitfld.long 0x0c 31. " XM127 ,Event EVT127 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 30. " XM126 ,Event EVT126 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 29. " XM125 ,Event EVT125 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 28. " XM124 ,Event EVT124 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 27. " XM123 ,Event EVT123 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 26. " XM122 ,Event EVT122 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 25. " XM121 ,Event EVT121 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 24. " XM120 ,Event EVT120 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 23. " XM119 ,Event EVT119 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 22. " XM118 ,Event EVT118 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 21. " XM117 ,Event EVT117 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 20. " XM116 ,Event EVT116 disabled from being used in the exception combiner" "Combined,Disabled" textline " " bitfld.long 0x0c 17. " XM113 ,Event EVT113 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 1. " XM97 ,Event EVT97 disabled from being used in the exception combiner" "Combined,Disabled" bitfld.long 0x0c 0. " XM96 ,Event EVT96 disabled from being used in the exception combiner" "Combined,Disabled" width 11. rgroup.long 0xa0++0xf line.long 0x00 "MEVTFLAG0,Masked Event Flag Register 0" hexmask.long 0x00 0.--31. 1. " MEF[31:0] ,Displays content of EF when EM=0" line.long 0x04 "MEVTFLAG1,Masked Event Flag Register 1" hexmask.long 0x04 0.--31. 1. " MEF[63:32] ,Displays content of EF when EM=0" line.long 0x08 "MEVTFLAG2,Masked Event Flag Register 2" hexmask.long 0x08 0.--31. 1. " MEF[95:64] ,Displays content of EF when EM=0" line.long 0x0c "MEVTFLAG3,Masked Event Flag Register 3" hexmask.long 0x0c 0.--31. 1. " MEF[127:96] ,Displays content of EF when EM=0" rgroup.long 0xe0++0xf line.long 0x00 "MEXPFLAG0,Masked Exception Flag Register 0" line.long 0x04 "MEXPFLAG1,Masked ExceptionFlag Register 1" line.long 0x08 "MEXPFLAG2,Masked Exception Flag Register 2" line.long 0x0c "MEXPFLAG3,Masked Exception Flag Register 3" width 11. group.long 0x104++0xb line.long 0x00 "INTMUX1,Interrupt Mux Register 1" hexmask.long.byte 0x00 24.--30. 1. " INTSEL7 ,Number of the event that maps to CPUINT7" hexmask.long.byte 0x00 16.--22. 1. " INTSEL6 ,Number of the event that maps to CPUINT6" hexmask.long.byte 0x00 8.--14. 1. " INTSEL5 ,Number of the event that maps to CPUINT5" hexmask.long.byte 0x00 0.--6. 1. " INTSEL4 ,Number of the event that maps to CPUINT4" line.long 0x04 "INTMUX2,Interrupt Mux Register 2" hexmask.long.byte 0x04 24.--30. 1. " INTSEL11 ,Number of the event that maps to CPUINT11" hexmask.long.byte 0x04 16.--22. 1. " INTSEL10 ,Number of the event that maps to CPUINT10" hexmask.long.byte 0x04 8.--14. 1. " INTSEL9 ,Number of the event that maps to CPUINT9" hexmask.long.byte 0x04 0.--6. 1. " INTSEL8 ,Number of the event that maps to CPUINT8" line.long 0x08 "INTMUX3,Interrupt Mux Register 3" hexmask.long.byte 0x08 24.--30. 1. " INTSEL15 ,Number of the event that maps to CPUINT15" hexmask.long.byte 0x08 16.--22. 1. " INTSEL14 ,Number of the event that maps to CPUINT14" hexmask.long.byte 0x08 8.--14. 1. " INTSEL13 ,Number of the event that maps to CPUINT13" hexmask.long.byte 0x08 0.--6. 1. " INTSEL12 ,Number of the event that maps to CPUINT12" rgroup.long 0x180++0x3 line.long 0x00 "INTXSTAT,Interrupt Exception Status Register" hexmask.long.byte 0x00 24.--31. 1. " SYSINT ,System Event number" hexmask.long.byte 0x00 16.--23. 1. " CPUINT ,CPU interrupt number" bitfld.long 0x00 0. " DROP ,Dropped event flag" "No event dropped,Event dropped" width 11. wgroup.long 0x184++0x3 line.long 0x00 "INTXCLR,Interrupt Exception Clear Register" bitfld.long 0x00 0. " CLEAR ,Clears the interrupt exception status" "No effect,Cleared" rgroup.long 0x188++0x3 line.long 0x00 "INTDMASK,Dropped Interrupt Mask Register" bitfld.long 0x00 15. " IDM15 ,Disables CPUINT15 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 14. " IDM14 ,Disables CPUINT14 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 13. " IDM13 ,Disables CPUINT13 from being detected by the drop detection hardware" "No effect,Ignored" textline " " bitfld.long 0x00 12. " IDM12 ,Disables CPUINT12 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 11. " IDM11 ,Disables CPUINT11 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 10. " IDM10 ,Disables CPUINT10 from being detected by the drop detection hardware" "No effect,Ignored" textline " " bitfld.long 0x00 9. " IDM9 ,Disables CPUINT9 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 8. " IDM8 ,Disables CPUINT8 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 7. " IDM7 ,Disables CPUINT7 from being detected by the drop detection hardware" "No effect,Ignored" textline " " bitfld.long 0x00 6. " IDM6 ,Disables CPUINT6 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 5. " IDM5 ,Disables CPUINT5 from being detected by the drop detection hardware" "No effect,Ignored" bitfld.long 0x00 4. " IDM4 ,Disables CPUINT4 from being detected by the drop detection hardware" "No effect,Ignored" width 11. group.long 0x140++0x07 line.long 0x00 "AEGMUX0,Advanced Event Generator Mux Registers" hexmask.long.byte 0x00 24.--31. 1. " AEGSEL3 ,Advanced Event Generator Select" hexmask.long.byte 0x00 16.--23. 1. " AEGSEL2 ,Advanced Event Generator Select" hexmask.long.byte 0x00 8.--15. 1. " AEGSEL1 ,Advanced Event Generator Select" hexmask.long.byte 0x00 0.--7. 1. " AEGSEL0 ,Advanced Event Generator Select" line.long 0x04 "AEGMUX1,Advanced Event Generator Mux Registers" hexmask.long.byte 0x04 24.--31. 1. " AEGSEL7 ,Advanced Event Generator Select" hexmask.long.byte 0x04 16.--23. 1. " AEGSEL6 ,Advanced Event Generator Select" hexmask.long.byte 0x04 8.--15. 1. " AEGSEL5 ,Advanced Event Generator Select" hexmask.long.byte 0x04 0.--7. 1. " AEGSEL4 ,Advanced Event Generator Select" width 0xb tree.end tree "Power-Down Controller" width 8. base d:0x01810000 group.long 0x00++0x3 line.long 0x00 "PDCCMD,Power-Down Controller Command Register" bitfld.long 0x00 16. " MEGPD ,Power-down during IDLE" "Normal,Sleep mode" width 0xb tree.end tree.end AUTOINDENT.POP endif tree "IPU1_UNICACHE_CFG" base ad:0x55080000 width 15. group.byte 0x4++0x3 line.long 0x0 "CACHE_CONFIG,Configuration Register" bitfld.long 0x0 0. " CACHE_LOCK ,Unicache lock. Once this bit is set only debugger or hardware reset can clear." "0,1" bitfld.long 0x0 1. " BYPASS ,Bypass cache" "0,1" textline " " bitfld.long 0x0 2. " LOCK_INT ,Lock access to interrupt registers" "0,1" bitfld.long 0x0 3. " LOCK_PORT ,Lock access to interface registers" "0,1" textline " " bitfld.long 0x0 4. " LOCK_MAIN ,Lock access to maintenance registers" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "CACHE_INT,Interrupt Register" bitfld.long 0x0 0. " CONFIG ,Configuration error" "0,1" bitfld.long 0x0 1. " PAGEFAULT ,Unicache MMU page fault" "0,1" textline " " bitfld.long 0x0 2. " MAINT ,Maintenance is completed" "0,1" bitfld.long 0x0 3. " WRITE ,Interface write response error" "0,1" textline " " bitfld.long 0x0 4. " READ ,Interface read response error" "0,1" bitfld.long 0x0 5.--8. " PORT ,Slave interface number that has recorded an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved." group.byte 0xC++0x3 line.long 0x0 "CACHE_OCP,Interface Configuration Register" bitfld.long 0x0 0. " WRAP ,OCP wrap mode (critical word first)" "0,1" bitfld.long 0x0 1. " WRBUFFER ,Write throughs and write back no allocate are buffered" "0,1" textline " " bitfld.long 0x0 2. " WRALLOCATE ,Follow write allocate sideband signals" "0,1" bitfld.long 0x0 3. " CACHED ,Follow cacheable sideband signals" "0,1" textline " " bitfld.long 0x0 4. " PREFETCH ,Always prefetch data" "0,1" bitfld.long 0x0 5. " CLEANBUF ,Clean write and prefetch buffers in cache" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved." group.byte 0x10++0x3 line.long 0x0 "CACHE_MAINT,Maintenance Configuration Register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved." group.byte 0x14++0x3 line.long 0x0 "CACHE_MTSTART,Maintenance Start Configuration Register" hexmask.long 0x0 0.--31. 1. " START_ADDR ,Start address of maintenance operations, reset to 0x0000 0000 when finished" group.byte 0x18++0x3 line.long 0x0 "CACHE_MTEND,Maintenance End Configuration Register" hexmask.long 0x0 0.--31. 1. " END_ADDR ,End address of maintenance operations, reset to 0x0000 0000 when finished" group.byte 0x1C++0x3 line.long 0x0 "CACHE_CTADDR,Cache Test Address Register" hexmask.long 0x0 0.--31. 1. " ADDRESS ,Address of cache visibility when readCACHE_CTDATA register, autoincrements" group.byte 0x20++0x3 line.long 0x0 "CACHE_CTDATA,Cache Test Data Register" hexmask.long 0x0 0.--31. 1. " DATA ,Cache data at address ofCACHE_CTADDR register, CACHE_CTADDR autoincrements each time CACHE_CTDATA is read" width 0x0B tree.end tree "IPU1_UNICACHE_SCTM" base ad:0x55080400 width 25. group.byte 0x0++0x3 line.long 0x0 "CACHE_SCTM_CTCNTL,CACHE_SCTM_CTCNTL" bitfld.long 0x0 0. " ENBL ,SCTM global enable" "0,1" bitfld.long 0x0 1.--2. " IDLEMODE ,Idle mode control" "0,1,2,3" textline " " bitfld.long 0x0 3.--6. " REVISION ,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 7.--12. " NUMCNTR ,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 13.--17. " NUMTIMR ,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 18.--25. 1. " NUMINPT ,Number of event input signals" textline " " bitfld.long 0x0 26.--31. " NUMSTM ,Number of timers that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x40++0x3 line.long 0x0 "CACHE_SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" hexmask.long 0x0 0.--31. 1. " INTERVAL ,Interval match value for the timers in the SCTM" group.byte 0x44++0x3 line.long 0x0 "CACHE_SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" hexmask.long 0x0 0.--31. 1. " INTERVAL ,Interval match value for the timers in the SCTM" group.byte 0x7C++0x3 line.long 0x0 "CACHE_SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x0 0.--2. " NUMEVT ,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved." group.byte 0xF0++0x3 line.long 0x0 "CACHE_SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x0 0.--7. 1. " ENABLE ,The counter enable bit field" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0xF8++0x3 line.long 0x0 "CACHE_SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x0 0.--7. 1. " RESET ,The counter reset bit field" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0x100++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WT_i_0,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WT: with timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "0,1" bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "0,1" textline " " bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match" "0,1" bitfld.long 0x0 11.--15. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection1-31: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x104++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WT_i_1,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WT: with timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "0,1" bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "0,1" textline " " bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match" "0,1" bitfld.long 0x0 11.--15. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection1-31: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x108++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_0,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x10C++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_1,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x110++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_2,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x114++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_3,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x118++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_4,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x11C++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_5,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x180++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x184++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x188++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x18C++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x190++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x194++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x198++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x19C++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" width 0x0B tree.end tree "IPU1_UNICACHE_MMU" base ad:0x55080800 width 28. group.byte 0x0++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_0,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x4++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_1,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x8++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_2,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0xC++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_3,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x20++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_0,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x24++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_1,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x28++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_2,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x2C++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_3,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x40++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_0,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_1,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_2,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_3,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_0,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0x64++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_1,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0xA0++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_0,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xA4++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_1,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xE0++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_0,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_1,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_0,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x124++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_1,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x128++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_2,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x12C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_3,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x130++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_4,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x134++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_5,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x138++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_6,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x13C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_7,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x140++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_8,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x144++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_9,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x1A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_0,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_1,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_2,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_3,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_4,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_5,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_6,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_7,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_8,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_9,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x220++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_0,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x224++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_1,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_2,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x22C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_3,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_4,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x234++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_5,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_6,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_7,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_8,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_9,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x2A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_0,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_1,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_2,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_3,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_4,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_5,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_6,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_7,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_8,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_9,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x4A8++0x3 line.long 0x0 "CACHE_MMU_MAINT,Maintenance configuration register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " HOST_INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " bitfld.long 0x0 6. " CPU_INTERRUPT ,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "0,1" bitfld.long 0x0 7. " L1_CACHE1 ,Do maintenance operation in L1 cache" "0,1" textline " " bitfld.long 0x0 8.--9. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 10. " G_FLUSH ,Global flush bit" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "CACHE_MMU_MTSTART,Maintenance start configuration register" hexmask.long 0x0 0.--31. 1. " BEGIN_ADDRESS ,Start address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B0++0x3 line.long 0x0 "CACHE_MMU_MTEND,Maintenance end configuration register" hexmask.long 0x0 0.--31. 1. " END_ADDRESS ,End address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B4++0x3 line.long 0x0 "CACHE_MMU_MAINTST,Maintenance status register" bitfld.long 0x0 0. " STATUS ,Status bit" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved." group.byte 0x4B8++0x3 line.long 0x0 "CACHE_MMU_MMUCONFIG,MMU configuration register" bitfld.long 0x0 0. " MMU_LOCK ,MMU lock. Once this bit is set only a global flush, debugger, or hardware reset can clear." "0,1" bitfld.long 0x0 1. " PRIVILEGE ,Privilege bit. Once this bit is set, only global flush, debugger, or hardware reset can clear." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved." width 0x0B tree.end tree "IPU1_WUGEN" base ad:0x55081000 width 24. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_CTRL_REG,The register is used by one CPU to interrupt the other, thus used as a handshake between the two CPUs 0x0: Interrupt is cleared; 0x1: Interrupt is set." bitfld.long 0x0 0. " INT_CORTEX_1 ,Interrupt to IPUx_C0" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " INT_CORTEX_2 ,Interrupt to IPUx_C1" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "STANDBY_CORE_SYSCONFIG,Standby protocol" bitfld.long 0x0 0.--1. " STANDBYMODE ,0x0: Force-standby mode" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "IDLE_CORE_SYSCONFIG,Idle protocol" bitfld.long 0x0 0.--1. " IDLEMODE ,0x0: Force-idle mode" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "WUGEN_MEVT0,This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request: 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x0 0. " MIRQ0 ,Interrupt Mask bit 0" "0,1" bitfld.long 0x0 1. " MIRQ1 ,Interrupt Mask bit 1" "0,1" textline " " bitfld.long 0x0 2. " MIRQ2 ,Interrupt Mask bit 2" "0,1" bitfld.long 0x0 3. " MIRQ3 ,Interrupt Mask bit 3" "0,1" textline " " bitfld.long 0x0 4. " MIRQ4 ,Interrupt Mask bit 4" "0,1" bitfld.long 0x0 5. " MIRQ5 ,Interrupt Mask bit 5" "0,1" textline " " bitfld.long 0x0 6. " MIRQ6 ,Interrupt Mask bit 6" "0,1" bitfld.long 0x0 7. " MIRQ7 ,Interrupt Mask bit 7" "0,1" textline " " bitfld.long 0x0 8. " MIRQ8 ,Interrupt Mask bit 8" "0,1" bitfld.long 0x0 9. " MIRQ9 ,Interrupt Mask bit 9" "0,1" textline " " bitfld.long 0x0 10. " MIRQ10 ,Interrupt Mask bit 10" "0,1" bitfld.long 0x0 11. " MIRQ11 ,Interrupt Mask bit 11" "0,1" textline " " bitfld.long 0x0 12. " MIRQ12 ,Interrupt Mask bit 12" "0,1" bitfld.long 0x0 13. " MIRQ13 ,Interrupt Mask bit 13" "0,1" textline " " bitfld.long 0x0 14. " MIRQ14 ,Interrupt Mask bit 14" "0,1" bitfld.long 0x0 15. " MIRQ15 ,Interrupt Mask bit 15" "0,1" textline " " bitfld.long 0x0 16. " MIRQ16 ,Interrupt Mask bit 16" "0,1" bitfld.long 0x0 17. " MIRQ17 ,Interrupt Mask bit 17" "0,1" textline " " bitfld.long 0x0 18. " MIRQ18 ,Interrupt Mask bit 18" "0,1" bitfld.long 0x0 19. " MIRQ19 ,Interrupt Mask bit 19" "0,1" textline " " bitfld.long 0x0 20. " MIRQ20 ,Interrupt Mask bit 20" "0,1" bitfld.long 0x0 21. " MIRQ21 ,Interrupt Mask bit 21" "0,1" textline " " bitfld.long 0x0 22. " MIRQ22 ,Interrupt Mask bit 22" "0,1" bitfld.long 0x0 23. " MIRQ23 ,Interrupt Mask bit 23" "0,1" textline " " bitfld.long 0x0 24. " MIRQ24 ,Interrupt Mask bit 24" "0,1" bitfld.long 0x0 25. " MIRQ25 ,Interrupt Mask bit 25" "0,1" textline " " bitfld.long 0x0 26. " MIRQ26 ,Interrupt Mask bit 26" "0,1" bitfld.long 0x0 27. " MIRQ27 ,Interrupt Mask bit 27" "0,1" textline " " bitfld.long 0x0 28. " MIRQ28 ,Interrupt Mask bit 28" "0,1" bitfld.long 0x0 29. " MIRQ29 ,Interrupt Mask bit 29" "0,1" textline " " bitfld.long 0x0 30. " MIRQ30 ,Interrupt Mask bit 30" "0,1" bitfld.long 0x0 31. " MIRQ31 ,Interrupt Mask bit 31" "0,1" group.byte 0x10++0x3 line.long 0x0 "WUGEN_MEVT1,This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request: 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x0 0. " MIRQ32 ,Interrupt Mask bit 32" "0,1" bitfld.long 0x0 1. " MIRQ33 ,Interrupt Mask bit 33" "0,1" textline " " bitfld.long 0x0 2. " MIRQ34 ,Interrupt Mask bit 34" "0,1" bitfld.long 0x0 3. " MIRQ35 ,Interrupt Mask bit 35" "0,1" textline " " bitfld.long 0x0 4. " MIRQ36 ,Interrupt Mask bit 36" "0,1" bitfld.long 0x0 5. " MIRQ37 ,Interrupt Mask bit 37" "0,1" textline " " bitfld.long 0x0 6. " MIRQ38 ,Interrupt Mask bit 38" "0,1" bitfld.long 0x0 7. " MIRQ39 ,Interrupt Mask bit 39" "0,1" textline " " bitfld.long 0x0 8. " MIRQ40 ,Interrupt Mask bit 40" "0,1" bitfld.long 0x0 9. " MIRQ41 ,Interrupt Mask bit 41" "0,1" textline " " bitfld.long 0x0 10. " MIRQ42 ,Interrupt Mask bit 42" "0,1" bitfld.long 0x0 11. " MIRQ43 ,Interrupt Mask bit 43" "0,1" textline " " bitfld.long 0x0 12. " MIRQ44 ,Interrupt Mask bit 44" "0,1" bitfld.long 0x0 13. " MIRQ45 ,Interrupt Mask bit 45" "0,1" textline " " bitfld.long 0x0 14. " MIRQ46 ,Interrupt Mask bit 46" "0,1" bitfld.long 0x0 15. " MIRQ47 ,Interrupt Mask bit 47" "0,1" textline " " bitfld.long 0x0 16. " MIRQ48 ,Interrupt Mask bit 48" "0,1" bitfld.long 0x0 17. " MIRQ49 ,Interrupt Mask bit 49" "0,1" textline " " bitfld.long 0x0 18. " MIRQ50 ,Interrupt Mask bit 50" "0,1" bitfld.long 0x0 19. " MIRQ51 ,Interrupt Mask bit 51" "0,1" textline " " bitfld.long 0x0 20. " MIRQ52 ,Interrupt Mask bit 52" "0,1" bitfld.long 0x0 21. " MIRQ53 ,Interrupt Mask bit 53" "0,1" textline " " bitfld.long 0x0 22. " MIRQ54 ,Interrupt Mask bit 54" "0,1" bitfld.long 0x0 23. " MIRQ55 ,Interrupt Mask bit 55" "0,1" textline " " bitfld.long 0x0 24. " MIRQ56 ,Interrupt Mask bit 56" "0,1" bitfld.long 0x0 25. " MIRQ57 ,Interrupt Mask bit 57" "0,1" textline " " bitfld.long 0x0 26. " MIRQ58 ,Interrupt Mask bit 58" "0,1" bitfld.long 0x0 27. " MIRQ59 ,Interrupt Mask bit 59" "0,1" textline " " bitfld.long 0x0 28. " MIRQ60 ,Interrupt Mask bit 60" "0,1" bitfld.long 0x0 29. " MIRQ61 ,Interrupt Mask bit 61" "0,1" textline " " bitfld.long 0x0 30. " MIRQ62 ,Interrupt Mask bit 62" "0,1" bitfld.long 0x0 31. " MIRQ63 ,Interrupt Mask bit 63" "0,1" width 0x0B tree.end tree "IPU1_MMU" base ad:0x55082000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "IPU1_UNICACHE_CFG_L3_MAIN" base ad:0x58880000 width 15. group.byte 0x4++0x3 line.long 0x0 "CACHE_CONFIG,Configuration Register" bitfld.long 0x0 0. " CACHE_LOCK ,Unicache lock. Once this bit is set only debugger or hardware reset can clear." "0,1" bitfld.long 0x0 1. " BYPASS ,Bypass cache" "0,1" textline " " bitfld.long 0x0 2. " LOCK_INT ,Lock access to interrupt registers" "0,1" bitfld.long 0x0 3. " LOCK_PORT ,Lock access to interface registers" "0,1" textline " " bitfld.long 0x0 4. " LOCK_MAIN ,Lock access to maintenance registers" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "CACHE_INT,Interrupt Register" bitfld.long 0x0 0. " CONFIG ,Configuration error" "0,1" bitfld.long 0x0 1. " PAGEFAULT ,Unicache MMU page fault" "0,1" textline " " bitfld.long 0x0 2. " MAINT ,Maintenance is completed" "0,1" bitfld.long 0x0 3. " WRITE ,Interface write response error" "0,1" textline " " bitfld.long 0x0 4. " READ ,Interface read response error" "0,1" bitfld.long 0x0 5.--8. " PORT ,Slave interface number that has recorded an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved." group.byte 0xC++0x3 line.long 0x0 "CACHE_OCP,Interface Configuration Register" bitfld.long 0x0 0. " WRAP ,OCP wrap mode (critical word first)" "0,1" bitfld.long 0x0 1. " WRBUFFER ,Write throughs and write back no allocate are buffered" "0,1" textline " " bitfld.long 0x0 2. " WRALLOCATE ,Follow write allocate sideband signals" "0,1" bitfld.long 0x0 3. " CACHED ,Follow cacheable sideband signals" "0,1" textline " " bitfld.long 0x0 4. " PREFETCH ,Always prefetch data" "0,1" bitfld.long 0x0 5. " CLEANBUF ,Clean write and prefetch buffers in cache" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved." group.byte 0x10++0x3 line.long 0x0 "CACHE_MAINT,Maintenance Configuration Register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved." group.byte 0x14++0x3 line.long 0x0 "CACHE_MTSTART,Maintenance Start Configuration Register" hexmask.long 0x0 0.--31. 1. " START_ADDR ,Start address of maintenance operations, reset to 0x0000 0000 when finished" group.byte 0x18++0x3 line.long 0x0 "CACHE_MTEND,Maintenance End Configuration Register" hexmask.long 0x0 0.--31. 1. " END_ADDR ,End address of maintenance operations, reset to 0x0000 0000 when finished" group.byte 0x1C++0x3 line.long 0x0 "CACHE_CTADDR,Cache Test Address Register" hexmask.long 0x0 0.--31. 1. " ADDRESS ,Address of cache visibility when readCACHE_CTDATA register, autoincrements" group.byte 0x20++0x3 line.long 0x0 "CACHE_CTDATA,Cache Test Data Register" hexmask.long 0x0 0.--31. 1. " DATA ,Cache data at address ofCACHE_CTADDR register, CACHE_CTADDR autoincrements each time CACHE_CTDATA is read" width 0x0B tree.end tree "IPU1_UNICACHE_SCTM_L3_MAIN" base ad:0x58880400 width 25. group.byte 0x0++0x3 line.long 0x0 "CACHE_SCTM_CTCNTL,CACHE_SCTM_CTCNTL" bitfld.long 0x0 0. " ENBL ,SCTM global enable" "0,1" bitfld.long 0x0 1.--2. " IDLEMODE ,Idle mode control" "0,1,2,3" textline " " bitfld.long 0x0 3.--6. " REVISION ,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 7.--12. " NUMCNTR ,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 13.--17. " NUMTIMR ,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 18.--25. 1. " NUMINPT ,Number of event input signals" textline " " bitfld.long 0x0 26.--31. " NUMSTM ,Number of timers that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x40++0x3 line.long 0x0 "CACHE_SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" hexmask.long 0x0 0.--31. 1. " INTERVAL ,Interval match value for the timers in the SCTM" group.byte 0x44++0x3 line.long 0x0 "CACHE_SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" hexmask.long 0x0 0.--31. 1. " INTERVAL ,Interval match value for the timers in the SCTM" group.byte 0x7C++0x3 line.long 0x0 "CACHE_SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x0 0.--2. " NUMEVT ,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved." group.byte 0xF0++0x3 line.long 0x0 "CACHE_SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x0 0.--7. 1. " ENABLE ,The counter enable bit field" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0xF8++0x3 line.long 0x0 "CACHE_SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x0 0.--7. 1. " RESET ,The counter reset bit field" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0x100++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WT_i_0,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WT: with timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "0,1" bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "0,1" textline " " bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match" "0,1" bitfld.long 0x0 11.--15. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection1-31: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x104++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WT_i_1,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WT: with timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "0,1" bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "0,1" textline " " bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match" "0,1" bitfld.long 0x0 11.--15. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection1-31: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x108++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_0,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x10C++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_1,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x110++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_2,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x114++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_3,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x118++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_4,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x11C++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_5,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x180++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x184++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x188++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x18C++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x190++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x194++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x198++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x19C++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" width 0x0B tree.end tree "IPU1_UNICACHE_MMU_L3_MAIN" base ad:0x58880800 width 28. group.byte 0x0++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_0,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x4++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_1,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x8++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_2,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0xC++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_3,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x20++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_0,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x24++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_1,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x28++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_2,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x2C++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_3,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x40++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_0,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_1,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_2,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_3,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_0,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0x64++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_1,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0xA0++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_0,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xA4++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_1,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xE0++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_0,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_1,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_0,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x124++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_1,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x128++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_2,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x12C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_3,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x130++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_4,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x134++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_5,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x138++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_6,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x13C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_7,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x140++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_8,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x144++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_9,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x1A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_0,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_1,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_2,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_3,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_4,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_5,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_6,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_7,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_8,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_9,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x220++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_0,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x224++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_1,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_2,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x22C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_3,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_4,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x234++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_5,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_6,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_7,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_8,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_9,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x2A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_0,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_1,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_2,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_3,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_4,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_5,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_6,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_7,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_8,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_9,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x4A8++0x3 line.long 0x0 "CACHE_MMU_MAINT,Maintenance configuration register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " HOST_INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " bitfld.long 0x0 6. " CPU_INTERRUPT ,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "0,1" bitfld.long 0x0 7. " L1_CACHE1 ,Do maintenance operation in L1 cache" "0,1" textline " " bitfld.long 0x0 8.--9. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 10. " G_FLUSH ,Global flush bit" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "CACHE_MMU_MTSTART,Maintenance start configuration register" hexmask.long 0x0 0.--31. 1. " BEGIN_ADDRESS ,Start address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B0++0x3 line.long 0x0 "CACHE_MMU_MTEND,Maintenance end configuration register" hexmask.long 0x0 0.--31. 1. " END_ADDRESS ,End address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B4++0x3 line.long 0x0 "CACHE_MMU_MAINTST,Maintenance status register" bitfld.long 0x0 0. " STATUS ,Status bit" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved." group.byte 0x4B8++0x3 line.long 0x0 "CACHE_MMU_MMUCONFIG,MMU configuration register" bitfld.long 0x0 0. " MMU_LOCK ,MMU lock. Once this bit is set only a global flush, debugger, or hardware reset can clear." "0,1" bitfld.long 0x0 1. " PRIVILEGE ,Privilege bit. Once this bit is set, only global flush, debugger, or hardware reset can clear." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved." width 0x0B tree.end tree "IPU1_WUGEN_L3_MAIN" base ad:0x55081000 width 24. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_CTRL_REG,The register is used by one CPU to interrupt the other, thus used as a handshake between the two CPUs 0x0: Interrupt is cleared; 0x1: Interrupt is set." bitfld.long 0x0 0. " INT_CORTEX_1 ,Interrupt to IPUx_C0" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " INT_CORTEX_2 ,Interrupt to IPUx_C1" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "STANDBY_CORE_SYSCONFIG,Standby protocol" bitfld.long 0x0 0.--1. " STANDBYMODE ,0x0: Force-standby mode" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "IDLE_CORE_SYSCONFIG,Idle protocol" bitfld.long 0x0 0.--1. " IDLEMODE ,0x0: Force-idle mode" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "WUGEN_MEVT0,This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request: 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x0 0. " MIRQ0 ,Interrupt Mask bit 0" "0,1" bitfld.long 0x0 1. " MIRQ1 ,Interrupt Mask bit 1" "0,1" textline " " bitfld.long 0x0 2. " MIRQ2 ,Interrupt Mask bit 2" "0,1" bitfld.long 0x0 3. " MIRQ3 ,Interrupt Mask bit 3" "0,1" textline " " bitfld.long 0x0 4. " MIRQ4 ,Interrupt Mask bit 4" "0,1" bitfld.long 0x0 5. " MIRQ5 ,Interrupt Mask bit 5" "0,1" textline " " bitfld.long 0x0 6. " MIRQ6 ,Interrupt Mask bit 6" "0,1" bitfld.long 0x0 7. " MIRQ7 ,Interrupt Mask bit 7" "0,1" textline " " bitfld.long 0x0 8. " MIRQ8 ,Interrupt Mask bit 8" "0,1" bitfld.long 0x0 9. " MIRQ9 ,Interrupt Mask bit 9" "0,1" textline " " bitfld.long 0x0 10. " MIRQ10 ,Interrupt Mask bit 10" "0,1" bitfld.long 0x0 11. " MIRQ11 ,Interrupt Mask bit 11" "0,1" textline " " bitfld.long 0x0 12. " MIRQ12 ,Interrupt Mask bit 12" "0,1" bitfld.long 0x0 13. " MIRQ13 ,Interrupt Mask bit 13" "0,1" textline " " bitfld.long 0x0 14. " MIRQ14 ,Interrupt Mask bit 14" "0,1" bitfld.long 0x0 15. " MIRQ15 ,Interrupt Mask bit 15" "0,1" textline " " bitfld.long 0x0 16. " MIRQ16 ,Interrupt Mask bit 16" "0,1" bitfld.long 0x0 17. " MIRQ17 ,Interrupt Mask bit 17" "0,1" textline " " bitfld.long 0x0 18. " MIRQ18 ,Interrupt Mask bit 18" "0,1" bitfld.long 0x0 19. " MIRQ19 ,Interrupt Mask bit 19" "0,1" textline " " bitfld.long 0x0 20. " MIRQ20 ,Interrupt Mask bit 20" "0,1" bitfld.long 0x0 21. " MIRQ21 ,Interrupt Mask bit 21" "0,1" textline " " bitfld.long 0x0 22. " MIRQ22 ,Interrupt Mask bit 22" "0,1" bitfld.long 0x0 23. " MIRQ23 ,Interrupt Mask bit 23" "0,1" textline " " bitfld.long 0x0 24. " MIRQ24 ,Interrupt Mask bit 24" "0,1" bitfld.long 0x0 25. " MIRQ25 ,Interrupt Mask bit 25" "0,1" textline " " bitfld.long 0x0 26. " MIRQ26 ,Interrupt Mask bit 26" "0,1" bitfld.long 0x0 27. " MIRQ27 ,Interrupt Mask bit 27" "0,1" textline " " bitfld.long 0x0 28. " MIRQ28 ,Interrupt Mask bit 28" "0,1" bitfld.long 0x0 29. " MIRQ29 ,Interrupt Mask bit 29" "0,1" textline " " bitfld.long 0x0 30. " MIRQ30 ,Interrupt Mask bit 30" "0,1" bitfld.long 0x0 31. " MIRQ31 ,Interrupt Mask bit 31" "0,1" group.byte 0x10++0x3 line.long 0x0 "WUGEN_MEVT1,This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request: 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x0 0. " MIRQ32 ,Interrupt Mask bit 32" "0,1" bitfld.long 0x0 1. " MIRQ33 ,Interrupt Mask bit 33" "0,1" textline " " bitfld.long 0x0 2. " MIRQ34 ,Interrupt Mask bit 34" "0,1" bitfld.long 0x0 3. " MIRQ35 ,Interrupt Mask bit 35" "0,1" textline " " bitfld.long 0x0 4. " MIRQ36 ,Interrupt Mask bit 36" "0,1" bitfld.long 0x0 5. " MIRQ37 ,Interrupt Mask bit 37" "0,1" textline " " bitfld.long 0x0 6. " MIRQ38 ,Interrupt Mask bit 38" "0,1" bitfld.long 0x0 7. " MIRQ39 ,Interrupt Mask bit 39" "0,1" textline " " bitfld.long 0x0 8. " MIRQ40 ,Interrupt Mask bit 40" "0,1" bitfld.long 0x0 9. " MIRQ41 ,Interrupt Mask bit 41" "0,1" textline " " bitfld.long 0x0 10. " MIRQ42 ,Interrupt Mask bit 42" "0,1" bitfld.long 0x0 11. " MIRQ43 ,Interrupt Mask bit 43" "0,1" textline " " bitfld.long 0x0 12. " MIRQ44 ,Interrupt Mask bit 44" "0,1" bitfld.long 0x0 13. " MIRQ45 ,Interrupt Mask bit 45" "0,1" textline " " bitfld.long 0x0 14. " MIRQ46 ,Interrupt Mask bit 46" "0,1" bitfld.long 0x0 15. " MIRQ47 ,Interrupt Mask bit 47" "0,1" textline " " bitfld.long 0x0 16. " MIRQ48 ,Interrupt Mask bit 48" "0,1" bitfld.long 0x0 17. " MIRQ49 ,Interrupt Mask bit 49" "0,1" textline " " bitfld.long 0x0 18. " MIRQ50 ,Interrupt Mask bit 50" "0,1" bitfld.long 0x0 19. " MIRQ51 ,Interrupt Mask bit 51" "0,1" textline " " bitfld.long 0x0 20. " MIRQ52 ,Interrupt Mask bit 52" "0,1" bitfld.long 0x0 21. " MIRQ53 ,Interrupt Mask bit 53" "0,1" textline " " bitfld.long 0x0 22. " MIRQ54 ,Interrupt Mask bit 54" "0,1" bitfld.long 0x0 23. " MIRQ55 ,Interrupt Mask bit 55" "0,1" textline " " bitfld.long 0x0 24. " MIRQ56 ,Interrupt Mask bit 56" "0,1" bitfld.long 0x0 25. " MIRQ57 ,Interrupt Mask bit 57" "0,1" textline " " bitfld.long 0x0 26. " MIRQ58 ,Interrupt Mask bit 58" "0,1" bitfld.long 0x0 27. " MIRQ59 ,Interrupt Mask bit 59" "0,1" textline " " bitfld.long 0x0 28. " MIRQ60 ,Interrupt Mask bit 60" "0,1" bitfld.long 0x0 29. " MIRQ61 ,Interrupt Mask bit 61" "0,1" textline " " bitfld.long 0x0 30. " MIRQ62 ,Interrupt Mask bit 62" "0,1" bitfld.long 0x0 31. " MIRQ63 ,Interrupt Mask bit 63" "0,1" width 0x0B tree.end tree "IPU1_MMU_L3_MAIN" base ad:0x58882000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "IPU1_Cx_RW_TABLE" base ad:0xE00FE000 width 18. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_RW_PID1,Peripheral Identification register allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD1 ,IPUx_ROM memory address" group.byte 0x4++0x3 line.long 0x0 "CORTEXM4_RW_PID2,Peripheral Identification register  allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD2 ,IPUx_ROM memory address" width 0x0B tree.end tree "IPU2_UNICACHE_MMU" base ad:0x55080800 width 28. group.byte 0x0++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_0,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x4++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_1,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x8++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_2,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0xC++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_3,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x20++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_0,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x24++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_1,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x28++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_2,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x2C++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_3,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x40++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_0,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_1,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_2,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_3,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_0,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0x64++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_1,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0xA0++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_0,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xA4++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_1,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xE0++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_0,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_1,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_0,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x124++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_1,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x128++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_2,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x12C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_3,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x130++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_4,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x134++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_5,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x138++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_6,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x13C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_7,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x140++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_8,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x144++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_9,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x1A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_0,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_1,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_2,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_3,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_4,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_5,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_6,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_7,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_8,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_9,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x220++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_0,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x224++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_1,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_2,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x22C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_3,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_4,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x234++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_5,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_6,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_7,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_8,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_9,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x2A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_0,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_1,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_2,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_3,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_4,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_5,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_6,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_7,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_8,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_9,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x4A8++0x3 line.long 0x0 "CACHE_MMU_MAINT,Maintenance configuration register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " HOST_INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " bitfld.long 0x0 6. " CPU_INTERRUPT ,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "0,1" bitfld.long 0x0 7. " L1_CACHE1 ,Do maintenance operation in L1 cache" "0,1" textline " " bitfld.long 0x0 8.--9. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 10. " G_FLUSH ,Global flush bit" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "CACHE_MMU_MTSTART,Maintenance start configuration register" hexmask.long 0x0 0.--31. 1. " BEGIN_ADDRESS ,Start address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B0++0x3 line.long 0x0 "CACHE_MMU_MTEND,Maintenance end configuration register" hexmask.long 0x0 0.--31. 1. " END_ADDRESS ,End address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B4++0x3 line.long 0x0 "CACHE_MMU_MAINTST,Maintenance status register" bitfld.long 0x0 0. " STATUS ,Status bit" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved." group.byte 0x4B8++0x3 line.long 0x0 "CACHE_MMU_MMUCONFIG,MMU configuration register" bitfld.long 0x0 0. " MMU_LOCK ,MMU lock. Once this bit is set only a global flush, debugger, or hardware reset can clear." "0,1" bitfld.long 0x0 1. " PRIVILEGE ,Privilege bit. Once this bit is set, only global flush, debugger, or hardware reset can clear." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved." width 0x0B tree.end tree "IPU2_MMU" base ad:0x55082000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "IPU2_UNICACHE_CFG_L3_MAIN" base ad:0x55080000 width 15. group.byte 0x4++0x3 line.long 0x0 "CACHE_CONFIG,Configuration Register" bitfld.long 0x0 0. " CACHE_LOCK ,Unicache lock. Once this bit is set only debugger or hardware reset can clear." "0,1" bitfld.long 0x0 1. " BYPASS ,Bypass cache" "0,1" textline " " bitfld.long 0x0 2. " LOCK_INT ,Lock access to interrupt registers" "0,1" bitfld.long 0x0 3. " LOCK_PORT ,Lock access to interface registers" "0,1" textline " " bitfld.long 0x0 4. " LOCK_MAIN ,Lock access to maintenance registers" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "CACHE_INT,Interrupt Register" bitfld.long 0x0 0. " CONFIG ,Configuration error" "0,1" bitfld.long 0x0 1. " PAGEFAULT ,Unicache MMU page fault" "0,1" textline " " bitfld.long 0x0 2. " MAINT ,Maintenance is completed" "0,1" bitfld.long 0x0 3. " WRITE ,Interface write response error" "0,1" textline " " bitfld.long 0x0 4. " READ ,Interface read response error" "0,1" bitfld.long 0x0 5.--8. " PORT ,Slave interface number that has recorded an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved." group.byte 0xC++0x3 line.long 0x0 "CACHE_OCP,Interface Configuration Register" bitfld.long 0x0 0. " WRAP ,OCP wrap mode (critical word first)" "0,1" bitfld.long 0x0 1. " WRBUFFER ,Write throughs and write back no allocate are buffered" "0,1" textline " " bitfld.long 0x0 2. " WRALLOCATE ,Follow write allocate sideband signals" "0,1" bitfld.long 0x0 3. " CACHED ,Follow cacheable sideband signals" "0,1" textline " " bitfld.long 0x0 4. " PREFETCH ,Always prefetch data" "0,1" bitfld.long 0x0 5. " CLEANBUF ,Clean write and prefetch buffers in cache" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved." group.byte 0x10++0x3 line.long 0x0 "CACHE_MAINT,Maintenance Configuration Register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved." group.byte 0x14++0x3 line.long 0x0 "CACHE_MTSTART,Maintenance Start Configuration Register" hexmask.long 0x0 0.--31. 1. " START_ADDR ,Start address of maintenance operations, reset to 0x0000 0000 when finished" group.byte 0x18++0x3 line.long 0x0 "CACHE_MTEND,Maintenance End Configuration Register" hexmask.long 0x0 0.--31. 1. " END_ADDR ,End address of maintenance operations, reset to 0x0000 0000 when finished" group.byte 0x1C++0x3 line.long 0x0 "CACHE_CTADDR,Cache Test Address Register" hexmask.long 0x0 0.--31. 1. " ADDRESS ,Address of cache visibility when readCACHE_CTDATA register, autoincrements" group.byte 0x20++0x3 line.long 0x0 "CACHE_CTDATA,Cache Test Data Register" hexmask.long 0x0 0.--31. 1. " DATA ,Cache data at address ofCACHE_CTADDR register, CACHE_CTADDR autoincrements each time CACHE_CTDATA is read" width 0x0B tree.end tree "IPU2_UNICACHE_SCTM_L3_MAIN" base ad:0x55080400 width 25. group.byte 0x0++0x3 line.long 0x0 "CACHE_SCTM_CTCNTL,CACHE_SCTM_CTCNTL" bitfld.long 0x0 0. " ENBL ,SCTM global enable" "0,1" bitfld.long 0x0 1.--2. " IDLEMODE ,Idle mode control" "0,1,2,3" textline " " bitfld.long 0x0 3.--6. " REVISION ,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 7.--12. " NUMCNTR ,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 13.--17. " NUMTIMR ,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 18.--25. 1. " NUMINPT ,Number of event input signals" textline " " bitfld.long 0x0 26.--31. " NUMSTM ,Number of timers that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x40++0x3 line.long 0x0 "CACHE_SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" hexmask.long 0x0 0.--31. 1. " INTERVAL ,Interval match value for the timers in the SCTM" group.byte 0x44++0x3 line.long 0x0 "CACHE_SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" hexmask.long 0x0 0.--31. 1. " INTERVAL ,Interval match value for the timers in the SCTM" group.byte 0x7C++0x3 line.long 0x0 "CACHE_SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x0 0.--2. " NUMEVT ,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved." group.byte 0xF0++0x3 line.long 0x0 "CACHE_SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x0 0.--7. 1. " ENABLE ,The counter enable bit field" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0xF8++0x3 line.long 0x0 "CACHE_SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x0 0.--7. 1. " RESET ,The counter reset bit field" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0x100++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WT_i_0,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WT: with timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "0,1" bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "0,1" textline " " bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match" "0,1" bitfld.long 0x0 11.--15. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection1-31: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x104++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WT_i_1,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WT: with timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "0,1" bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "0,1" textline " " bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match" "0,1" bitfld.long 0x0 11.--15. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection1-31: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x108++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_0,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x10C++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_1,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x110++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_2,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x114++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_3,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x118++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_4,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x11C++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_5,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x180++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x184++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x188++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x18C++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x190++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x194++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x198++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x19C++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" width 0x0B tree.end tree "IPU2_UNICACHE_MMU_L3_MAIN" base ad:0x55080800 width 28. group.byte 0x0++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_0,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x4++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_1,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x8++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_2,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0xC++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_3,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x20++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_0,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x24++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_1,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x28++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_2,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x2C++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_3,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x40++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_0,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_1,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_2,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_3,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_0,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0x64++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_1,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0xA0++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_0,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xA4++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_1,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xE0++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_0,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_1,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_0,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x124++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_1,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x128++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_2,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x12C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_3,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x130++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_4,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x134++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_5,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x138++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_6,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x13C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_7,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x140++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_8,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x144++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_9,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x1A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_0,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_1,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_2,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_3,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_4,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_5,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_6,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_7,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_8,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_9,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x220++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_0,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x224++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_1,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_2,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x22C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_3,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_4,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x234++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_5,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_6,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_7,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_8,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_9,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x2A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_0,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_1,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_2,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_3,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_4,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_5,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_6,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_7,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_8,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_9,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x4A8++0x3 line.long 0x0 "CACHE_MMU_MAINT,Maintenance configuration register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " HOST_INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " bitfld.long 0x0 6. " CPU_INTERRUPT ,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "0,1" bitfld.long 0x0 7. " L1_CACHE1 ,Do maintenance operation in L1 cache" "0,1" textline " " bitfld.long 0x0 8.--9. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 10. " G_FLUSH ,Global flush bit" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "CACHE_MMU_MTSTART,Maintenance start configuration register" hexmask.long 0x0 0.--31. 1. " BEGIN_ADDRESS ,Start address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B0++0x3 line.long 0x0 "CACHE_MMU_MTEND,Maintenance end configuration register" hexmask.long 0x0 0.--31. 1. " END_ADDRESS ,End address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B4++0x3 line.long 0x0 "CACHE_MMU_MAINTST,Maintenance status register" bitfld.long 0x0 0. " STATUS ,Status bit" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved." group.byte 0x4B8++0x3 line.long 0x0 "CACHE_MMU_MMUCONFIG,MMU configuration register" bitfld.long 0x0 0. " MMU_LOCK ,MMU lock. Once this bit is set only a global flush, debugger, or hardware reset can clear." "0,1" bitfld.long 0x0 1. " PRIVILEGE ,Privilege bit. Once this bit is set, only global flush, debugger, or hardware reset can clear." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved." width 0x0B tree.end tree "IPU2_WUGEN_L3_MAIN" base ad:0x55081000 width 24. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_CTRL_REG,The register is used by one CPU to interrupt the other, thus used as a handshake between the two CPUs 0x0: Interrupt is cleared; 0x1: Interrupt is set." bitfld.long 0x0 0. " INT_CORTEX_1 ,Interrupt to IPUx_C0" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " INT_CORTEX_2 ,Interrupt to IPUx_C1" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "STANDBY_CORE_SYSCONFIG,Standby protocol" bitfld.long 0x0 0.--1. " STANDBYMODE ,0x0: Force-standby mode" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "IDLE_CORE_SYSCONFIG,Idle protocol" bitfld.long 0x0 0.--1. " IDLEMODE ,0x0: Force-idle mode" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "WUGEN_MEVT0,This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request: 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x0 0. " MIRQ0 ,Interrupt Mask bit 0" "0,1" bitfld.long 0x0 1. " MIRQ1 ,Interrupt Mask bit 1" "0,1" textline " " bitfld.long 0x0 2. " MIRQ2 ,Interrupt Mask bit 2" "0,1" bitfld.long 0x0 3. " MIRQ3 ,Interrupt Mask bit 3" "0,1" textline " " bitfld.long 0x0 4. " MIRQ4 ,Interrupt Mask bit 4" "0,1" bitfld.long 0x0 5. " MIRQ5 ,Interrupt Mask bit 5" "0,1" textline " " bitfld.long 0x0 6. " MIRQ6 ,Interrupt Mask bit 6" "0,1" bitfld.long 0x0 7. " MIRQ7 ,Interrupt Mask bit 7" "0,1" textline " " bitfld.long 0x0 8. " MIRQ8 ,Interrupt Mask bit 8" "0,1" bitfld.long 0x0 9. " MIRQ9 ,Interrupt Mask bit 9" "0,1" textline " " bitfld.long 0x0 10. " MIRQ10 ,Interrupt Mask bit 10" "0,1" bitfld.long 0x0 11. " MIRQ11 ,Interrupt Mask bit 11" "0,1" textline " " bitfld.long 0x0 12. " MIRQ12 ,Interrupt Mask bit 12" "0,1" bitfld.long 0x0 13. " MIRQ13 ,Interrupt Mask bit 13" "0,1" textline " " bitfld.long 0x0 14. " MIRQ14 ,Interrupt Mask bit 14" "0,1" bitfld.long 0x0 15. " MIRQ15 ,Interrupt Mask bit 15" "0,1" textline " " bitfld.long 0x0 16. " MIRQ16 ,Interrupt Mask bit 16" "0,1" bitfld.long 0x0 17. " MIRQ17 ,Interrupt Mask bit 17" "0,1" textline " " bitfld.long 0x0 18. " MIRQ18 ,Interrupt Mask bit 18" "0,1" bitfld.long 0x0 19. " MIRQ19 ,Interrupt Mask bit 19" "0,1" textline " " bitfld.long 0x0 20. " MIRQ20 ,Interrupt Mask bit 20" "0,1" bitfld.long 0x0 21. " MIRQ21 ,Interrupt Mask bit 21" "0,1" textline " " bitfld.long 0x0 22. " MIRQ22 ,Interrupt Mask bit 22" "0,1" bitfld.long 0x0 23. " MIRQ23 ,Interrupt Mask bit 23" "0,1" textline " " bitfld.long 0x0 24. " MIRQ24 ,Interrupt Mask bit 24" "0,1" bitfld.long 0x0 25. " MIRQ25 ,Interrupt Mask bit 25" "0,1" textline " " bitfld.long 0x0 26. " MIRQ26 ,Interrupt Mask bit 26" "0,1" bitfld.long 0x0 27. " MIRQ27 ,Interrupt Mask bit 27" "0,1" textline " " bitfld.long 0x0 28. " MIRQ28 ,Interrupt Mask bit 28" "0,1" bitfld.long 0x0 29. " MIRQ29 ,Interrupt Mask bit 29" "0,1" textline " " bitfld.long 0x0 30. " MIRQ30 ,Interrupt Mask bit 30" "0,1" bitfld.long 0x0 31. " MIRQ31 ,Interrupt Mask bit 31" "0,1" group.byte 0x10++0x3 line.long 0x0 "WUGEN_MEVT1,This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request: 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x0 0. " MIRQ32 ,Interrupt Mask bit 32" "0,1" bitfld.long 0x0 1. " MIRQ33 ,Interrupt Mask bit 33" "0,1" textline " " bitfld.long 0x0 2. " MIRQ34 ,Interrupt Mask bit 34" "0,1" bitfld.long 0x0 3. " MIRQ35 ,Interrupt Mask bit 35" "0,1" textline " " bitfld.long 0x0 4. " MIRQ36 ,Interrupt Mask bit 36" "0,1" bitfld.long 0x0 5. " MIRQ37 ,Interrupt Mask bit 37" "0,1" textline " " bitfld.long 0x0 6. " MIRQ38 ,Interrupt Mask bit 38" "0,1" bitfld.long 0x0 7. " MIRQ39 ,Interrupt Mask bit 39" "0,1" textline " " bitfld.long 0x0 8. " MIRQ40 ,Interrupt Mask bit 40" "0,1" bitfld.long 0x0 9. " MIRQ41 ,Interrupt Mask bit 41" "0,1" textline " " bitfld.long 0x0 10. " MIRQ42 ,Interrupt Mask bit 42" "0,1" bitfld.long 0x0 11. " MIRQ43 ,Interrupt Mask bit 43" "0,1" textline " " bitfld.long 0x0 12. " MIRQ44 ,Interrupt Mask bit 44" "0,1" bitfld.long 0x0 13. " MIRQ45 ,Interrupt Mask bit 45" "0,1" textline " " bitfld.long 0x0 14. " MIRQ46 ,Interrupt Mask bit 46" "0,1" bitfld.long 0x0 15. " MIRQ47 ,Interrupt Mask bit 47" "0,1" textline " " bitfld.long 0x0 16. " MIRQ48 ,Interrupt Mask bit 48" "0,1" bitfld.long 0x0 17. " MIRQ49 ,Interrupt Mask bit 49" "0,1" textline " " bitfld.long 0x0 18. " MIRQ50 ,Interrupt Mask bit 50" "0,1" bitfld.long 0x0 19. " MIRQ51 ,Interrupt Mask bit 51" "0,1" textline " " bitfld.long 0x0 20. " MIRQ52 ,Interrupt Mask bit 52" "0,1" bitfld.long 0x0 21. " MIRQ53 ,Interrupt Mask bit 53" "0,1" textline " " bitfld.long 0x0 22. " MIRQ54 ,Interrupt Mask bit 54" "0,1" bitfld.long 0x0 23. " MIRQ55 ,Interrupt Mask bit 55" "0,1" textline " " bitfld.long 0x0 24. " MIRQ56 ,Interrupt Mask bit 56" "0,1" bitfld.long 0x0 25. " MIRQ57 ,Interrupt Mask bit 57" "0,1" textline " " bitfld.long 0x0 26. " MIRQ58 ,Interrupt Mask bit 58" "0,1" bitfld.long 0x0 27. " MIRQ59 ,Interrupt Mask bit 59" "0,1" textline " " bitfld.long 0x0 28. " MIRQ60 ,Interrupt Mask bit 60" "0,1" bitfld.long 0x0 29. " MIRQ61 ,Interrupt Mask bit 61" "0,1" textline " " bitfld.long 0x0 30. " MIRQ62 ,Interrupt Mask bit 62" "0,1" bitfld.long 0x0 31. " MIRQ63 ,Interrupt Mask bit 63" "0,1" width 0x0B tree.end tree "IPU2_Cx_RW_TABLE" base ad:0xE00FE000 width 18. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_RW_PID1,Peripheral Identification register allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD1 ,IPUx_ROM memory address" group.byte 0x4++0x3 line.long 0x0 "CORTEXM4_RW_PID2,Peripheral Identification register  allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD2 ,IPUx_ROM memory address" width 0x0B tree.end tree "DSP_SYSTEM" base ad:0x01D00000 width 33. group.byte 0x0++0x3 line.long 0x0 "DSP_SYS_REVISION,DSP_SYS_REVISION" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "DSP_SYS_HWINFO,DSP_SYS_HWINFO" bitfld.long 0x0 0.--3. " NUM ,Instance Number Set by subsystem input. In a multi-DSP system, provides a unique/incrementing values for each DSP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " INFO ,0x0: No configurable options in subsystem." group.byte 0x8++0x3 line.long 0x0 "DSP_SYS_SYSCONFIG,DSP_SYS_SYSCONFIG" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,0x0: FORCE_IDLE This mode is a backup mode intended to be used only if the smart-idle mode is bugged. When in this mode, the IAF acknowledges a request to go idle from the power manager with minimal hardware condition. It is the responsibility of the software to ensure that the IAF are in a correct quiet state before requesting a force-idle transition. Additionally when in this mode, the IAF is not allowed to generate any wakeup request." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,0x0: FORCE_STANDBY This mode is a backup mode intended to be used only if the smart-idle mode is bugged. When in this mode, the SAF asserts with minimal hardware condition the 'STANDBY' status. It is the responsibility of the software to ensure that the SAF is in a correct quiet state before programming this mode. Additionally when in this mode, the SAF is not allowed to generate wakeup request." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reserved. Read returns 0." "0,1,2,3" textline " " bitfld.long 0x0 8. " RESERVED ,Reserved. User must write 0." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved. Read returns 0." group.byte 0xC++0x3 line.long 0x0 "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode." bitfld.long 0x0 0. " C66X_STAT ,C66x Status" "0,1" bitfld.long 0x0 1. " TC0_STAT ,EDMA TC0 Status" "0,1" textline " " bitfld.long 0x0 2. " TC1_STAT ,EDMA TC1 Status" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--5. " OCPI_DISC_STAT ,L3_MAIN (OCP) Initiator(s) Disconnect Status" "0,1,2,3" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses." bitfld.long 0x0 0. " OCPI_DISC ,OCP Initiator (on L3_MAIN) Disconnect request" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators." bitfld.long 0x0 0.--1. " TC0_DBS ,TC0 Default Burst size" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " TC1_DBS ,TC1 Default Burst size." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " TC0_L2PRES ,TC0 L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect." "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " TC1_L2PRES ,TC1 L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " CFG_L2PRES ,DSP CFG L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect" "0,1,2,3" bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " SDMA_L2PRES ,OCP Target port L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect." "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24. " NOPOSTOVERRIDE ,OCP Posted Write vs Non-Posted Write override" "0,1" bitfld.long 0x0 25.--27. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 28.--30. " SDMA_PRI ,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port. Can typically be left at default value. 0x0 is highest, ..., 0x7 is lowest priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x18++0x3 line.long 0x0 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs." bitfld.long 0x0 0. " MMU0_EN ,MMU0 Enable" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " MMU1_EN ,MMU1 Enable" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " MMU0_ABORT ,MMU0 Abort" "0,1" bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12. " MMU1_ABORT ,MMU1 Abort" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol). IRQWAKEEN0 is for interrupt inputs 63 thru 32, and IRQWAKEEN1 is for interrupt inputs 95 thru 64. Internal interrupts cannot cause a wake condition since in this state there is no guaranteed clock and all sub-modules should be in idle state. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding interrupt for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable bit vector for interrupt #n+32" group.byte 0x24++0x3 line.long 0x0 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol). IRQWAKEEN0 is for interrupt inputs 63 thru 32, and IRQWAKEEN1 is for interrupt inputs 95 thru 64. Internal interrupts cannot cause a wake condition since in this state there is no guaranteed clock and all sub-modules should be in idle state. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding interrupt for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable bit vector for interrupt #n+64" group.byte 0x30++0x3 line.long 0x0 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol). DMAWAKEEN0 is for dma event inputs 31 thru 0, and DMAWAKEEN1 is for dma event inputs 63 thru 32. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding dma event for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable for event #n" group.byte 0x34++0x3 line.long 0x0 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol). DMAWAKEEN0 is for dma event inputs 31 thru 0, and DMAWAKEEN1 is for dma event inputs 63 thru 32. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding dma event for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable for event #n+32" group.byte 0x40++0x3 line.long 0x0 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state." hexmask.long 0x0 0.--31. 1. " EVENT ,Output Event for event #n" group.byte 0x44++0x3 line.long 0x0 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state." hexmask.long 0x0 0.--31. 1. " EVENT ,Output Event for event #n" group.byte 0x50++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x0 0.--18. 1. " EVENT ,Settable raw status for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long.tbyte 0x0 0.--18. 1. " EVENT ,Clearable ,Clearable ,Clearable, enabled status for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long.tbyte 0x0 0.--18. 1. " ENABLE ,Enable for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long.tbyte 0x0 0.--18. 1. " ENABLE ,Enable for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long 0x0 0.--31. 1. " EVENT ,Settable raw status for event #n" group.byte 0x64++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long 0x0 0.--31. 1. " EVENT,Clearable ,Clearable ,Clearable, enabled status for event #n" group.byte 0x68++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n" group.byte 0x6C++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n" group.byte 0x70++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long 0x0 0.--31. 1. " EVENT ,Settable raw status for event #n+32" group.byte 0x74++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long 0x0 0.--31. 1. " EVENT,Clearable ,Clearable ,Clearable, enabled status for event #n+32" group.byte 0x78++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n+32" group.byte 0x7C++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n+32" group.byte 0xF8++0x3 line.long 0x0 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus." bitfld.long 0x0 0.--3. " GROUP ,Debug Group output control mux selectN: GN = select output group N ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0xFC++0x3 line.long 0x0 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group." hexmask.long 0x0 0.--31. 1. " VALUE ,Read returns state of hw_dbgout bus" width 0x0B tree.end tree "DSP_MMU0CFG" base ad:0x01D01000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP_MMU1CFG" base ad:0x01D02000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP_FW_L2_NOC_CFG" base ad:0x01D03000 width 77. group.byte 0x0++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" hexmask.long.word 0x0 0.--15. 1. " REQINFO_ERRLOG ,Error in reqinfo vector" bitfld.long 0x0 16.--20. " REGION_END_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGION_START_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26. " RESERVED ," "0,1" textline " " bitfld.long 0x0 27. " BLK_BURST_VIOLATION ,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x0 0.--27. 1. " SLVOFS_LOGICAL ,Address generated by the ARM before being translated" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " FW_UPDATE_REQ ,HW set/SW clear" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,HW set/SW clear" "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x88++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,MRM_PERMISSION_REGION_0_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x90++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" bitfld.long 0x0 0.--3. " START_REGION_1 ,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0 0.--3. " END_REGION_1 ,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " END_REGION_1_ENABLE ,End Region 1 enable" "0,1" group.byte 0x98++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x1000++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" hexmask.long.word 0x0 0.--15. 1. " REQINFO_ERRLOG ,Error in reqinfo vector" bitfld.long 0x0 16.--20. " REGION_END_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGION_START_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26. " RESERVED ," "0,1" textline " " bitfld.long 0x0 27. " BLK_BURST_VIOLATION ,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1004++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x0 0.--27. 1. " SLVOFS_LOGICAL ,Address generated by the ARM before being translated" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1040++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " FW_UPDATE_REQ ,HW set/SW clear" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,HW set/SW clear" "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x1088++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x108C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x4000++0x3 line.long 0x0 "DSPNOC_FLAGMUX_ID_COREID,DSPNOC_FLAGMUX_ID_COREID" hexmask.long.byte 0x0 0.--7. 1. " CORETYPEID ,Field identifying the type of IP." hexmask.long.tbyte 0x0 8.--31. 1. " CORECHECKSUM ,Field containing a checksum of the parameters of the IP." group.byte 0x4004++0x3 line.long 0x0 "DSPNOC_FLAGMUX_ID_REVISIONID,DSPNOC_FLAGMUX_ID_REVISIONID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4008++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FAULTEN,DSPNOC_FLAGMUX_FAULTEN" bitfld.long 0x0 0. " FAULTEN ,Global Fault Enable register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x400C++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FAULTSTATUS,DSPNOC_FLAGMUX_FAULTSTATUS" bitfld.long 0x0 0. " FAULTSTATUS ,Global Fault Status register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4010++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FLAGINEN0,DSPNOC_FLAGMUX_FLAGINEN0" bitfld.long 0x0 0. " FLAGINEN0 ,FlagIn Enable register #0" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4014++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FLAGINSTATUS0,DSPNOC_FLAGMUX_FLAGINSTATUS0" bitfld.long 0x0 0. " FLAGINSTATUS0 ,FlagIn Status register #0" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4200++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ID_COREID,DSPNOC_ERRORLOG_ID_COREID" hexmask.long.byte 0x0 0.--7. 1. " CORETYPEID ,Field identifying the type of IP." hexmask.long.tbyte 0x0 8.--31. 1. " CORECHECKSUM ,Field containing a checksum of the parameters of the IP." group.byte 0x4204++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ID_REVISIONID,DSPNOC_ERRORLOG_ID_REVISIONID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4208++0x3 line.long 0x0 "DSPNOC_ERRORLOG_FAULTEN,DSPNOC_ERRORLOG_FAULTEN" bitfld.long 0x0 0. " FAULTEN ,Enable Fault output" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x420C++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRVLD,DSPNOC_ERRORLOG_ERRVLD" bitfld.long 0x0 0. " ERRVLD ,Error logged Valid" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4210++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRCLR,DSPNOC_ERRORLOG_ERRCLR" bitfld.long 0x0 0. " ERRCLR ,Clr ErrVld status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4214++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock, Opcode, Len1, ErrCode values" bitfld.long 0x0 0. " LOCK ,Header: Lock bit value" "0,1" bitfld.long 0x0 1.--4. " OPC ,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. " ERRCODE ,Header: Error Code value" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--27. 1. " LEN1 ,Header: Len1 value" textline " " bitfld.long 0x0 28.--30. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " FORMAT ,Format of ErrLog0 register" "0,1" group.byte 0x4218++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG1,DSPNOC_ERRORLOG_ERRLOG1" hexmask.long.word 0x0 0.--14. 1. " ERRLOG1 ,Header: RouteId lsb value" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x4220++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG3,DSPNOC_ERRORLOG_ERRLOG3" hexmask.long 0x0 0.--30. 1. " ERRLOG3 ,Header: Addr lsb value" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x4228++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG5,DSPNOC_ERRORLOG_ERRLOG5" hexmask.long.tbyte 0x0 0.--21. 1. " ERRLOG5 ,Header: User lsb value" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "DSP_EDMA_TC0" base ad:0x01D05000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP_EDMA_TC1" base ad:0x01D06000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP_EDMA_CC" base ad:0x01D10000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPCC_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x0 0.--2. " NUMDMACH ,Number of DMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--6. " NUMQDMACH ,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 8.--10. " NUMINTCH ,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 12.--14. " NUMPAENTRY ,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 16.--18. " NUMTC ,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 20.--21. " NUMREGN ,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 24. " CHMAPEXIST ,Channel Mapping Existence" "0,1" bitfld.long 0x0 25. " MPEXIST ,Memory Protection Existence" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reads return 0's" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xFC++0x3 line.long 0x0 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x0 0. " CLKGDIS ,Auto Clock Gate Disable" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x114++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x118++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x11C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x138++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x13C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x144++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x148++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x14C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x150++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x154++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x158++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x15C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x160++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x164++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x168++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x16C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x170++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x174++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x178++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x17C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x180++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x194++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x198++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x19C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1AC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1BC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1CC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1DC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1EC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x248++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x254++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x260++0x3 line.long 0x0 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." bitfld.long 0x0 0.--2. " E0 ,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x280++0x3 line.long 0x0 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x0 0.--2. " TCNUMQ0 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " TCNUMQ1 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x0 0.--2. " PRIQ0 ,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " PRIQ1 ,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x300++0x3 line.long 0x0 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed #31" "0,1" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E32 ,Event Missed #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed #63" "0,1" group.byte 0x308++0x3 line.long 0x0 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed Clear #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed Clear #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed Clear #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed Clear #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed Clear #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed Clear #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed Clear #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed Clear #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed Clear #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed Clear #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed Clear #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed Clear #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed Clear #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed Clear #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed Clear #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed Clear #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed Clear #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed Clear #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed Clear #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed Clear #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed Clear #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed Clear #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed Clear #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed Clear #31" "0,1" group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E32 ,Event Missed Clear #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed Clear #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed Clear #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed Clear #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed Clear #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed Clear #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed Clear #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed Clear #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed Clear #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed Clear #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed Clear #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed Clear #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed Clear #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed Clear #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed Clear #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed Clear #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed Clear #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed Clear #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed Clear #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed Clear #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed Clear #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed Clear #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed Clear #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed Clear #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed Clear #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed Clear #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed Clear #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed Clear #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed Clear #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed Clear #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed Clear #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed Clear #63" "0,1" group.byte 0x310++0x3 line.long 0x0 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced. If any bit in the register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x314++0x3 line.long 0x0 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x318++0x3 line.long 0x0 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x0 0. " QTHRXCD0 ,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors were previously clear), then an error will be signaled with TPCC error interrupt. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x31C++0x3 line.long 0x0 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x0 0. " QTHRXCD0 ,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT0.WM, QSTAT0.THRXCD,[0] QTHRXCD0 ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM, QSTAT1.THRXCD,[1] QTHRXCD1 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT2.WM, QSTAT2.THRXCD,[2] QTHRXCD2 ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM, QSTAT3.THRXCD,[3] QTHRXCD3 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT4.WM, QSTAT4.THRXCD,[4] QTHRXCD4 ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT5.WM, QSTAT5.THRXCD,[5]QTHRXCD5 ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT6.WM, QSTAT6.THRXCD,[6]QTHRXCD6 ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT7.WM, QSTAT7.THRXCD,[7] QTHRXCD7 ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR. . Write 0x0 have no affect. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x320++0x3 line.long 0x0 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x0 0. " EVAL ,Error Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the/, , or registers. The CPU must also write 0x1 after any error interrupts are serviced in order for subsequent interrupts to be asserted. ." "0,1" bitfld.long 0x0 1. " SET ,Error Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of/, , or . ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x348++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x350++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x358++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x360++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x368++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x370++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x378++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x344++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x35C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x364++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x36C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x374++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x37C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x380++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x388++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x38C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x39C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x400++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x404++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x408++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x40C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x410++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x414++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x418++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x41C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x420++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x424++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x428++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x42C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x430++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x434++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x438++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x43C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x440++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x444++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x448++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x44C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x450++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x454++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x458++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x45C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x460++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x464++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x468++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x46C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x470++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x474++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x478++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x47C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRA,Queue Threshold A, for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q0 ,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q1 ,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q2 ,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q3 ,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x624++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRB,Queue Threshold B, for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q4 ,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q5 ,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q6 ,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q7 ,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x0 0. " EVTACTV ,DMA Event Active" "0,1" bitfld.long 0x0 1. " QEVTACTV ,QDMA Event Active" "0,1" textline " " bitfld.long 0x0 2. " TRACTV ,Transfer Request Active TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0,1" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4. " ACTV ,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals. The ACTV bit must remain high through the life of a:" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,reads return 0's" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " COMPACTV ,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " QUEACTV0 ,Queue 0 Active" "0,1" bitfld.long 0x0 17. " QUEACTV1 ,Queue 1 Active" "0,1" textline " " bitfld.long 0x0 18. " QUEACTV2 ,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0,1" bitfld.long 0x0 19. " QUEACTV3 ,Queue 3 Active" "0,1" textline " " bitfld.long 0x0 20. " QUEACTV4 ,Queue 4 Active" "0,1" bitfld.long 0x0 21. " QUEACTV5 ,Queue 5 Active" "0,1" textline " " bitfld.long 0x0 22. " QUEACTV6 ,Queue 6 Active" "0,1" bitfld.long 0x0 23. " QUEACTV7 ,Queue 7 Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,reads return 0's" group.byte 0x700++0x3 line.long 0x0 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 0.--5. " STRTEVT ,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " TYPE ,AET Event Type" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--13. " ENDINT ,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.tbyte 0x0 14.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " EN ,AET Enable" "0,1" group.byte 0x704++0x3 line.long 0x0 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x0 0. " STAT ,AET Status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x708++0x3 line.long 0x0 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x0 0. " CLR ,AET Clear commandCPU writes 0x0 has no effect. . CPU writes 0x1 to the CLR bit causes the tpcc_aet output signal and[0]STAT register to be cleared. ." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" hexmask.long 0x0 0.--31. 1. " FADDR ,Fault Address: 32-bit read-only status register containing the faulting address when a mMemory protection violation is detected. This register can only be cleared via theEDMA_TPCC_MPFCR." group.byte 0x804++0x3 line.long 0x0 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x0 0. " UXE ,User Execute Error" "0,1" bitfld.long 0x0 1. " UWE ,User Write Error" "0,1" textline " " bitfld.long 0x0 2. " URE ,User Read Error" "0,1" bitfld.long 0x0 3. " SXE ,Supervisor Execute Error" "0,1" textline " " bitfld.long 0x0 4. " SWE ,Supervisor Write Error" "0,1" bitfld.long 0x0 5. " SRE ,Supervisor Read Error" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--12. " FID ,Faulted ID: FID register contains valid info if any of the MP error bits (UXE, UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x808++0x3 line.long 0x0 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x0 0. " MPFCLR ,Fault Clear register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x80C++0x3 line.long 0x0 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0" "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x810++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x814++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x818++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x81C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x820++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x824++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x828++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x82C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x1000++0x3 line.long 0x0 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1004++0x3 line.long 0x0 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1008++0x3 line.long 0x0 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x100C++0x3 line.long 0x0 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1010++0x3 line.long 0x0 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1014++0x3 line.long 0x0 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1018++0x3 line.long 0x0 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x101C++0x3 line.long 0x0 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1020++0x3 line.long 0x0 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1024++0x3 line.long 0x0 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1028++0x3 line.long 0x0 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x102C++0x3 line.long 0x0 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1030++0x3 line.long 0x0 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1034++0x3 line.long 0x0 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1038++0x3 line.long 0x0 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x103C++0x3 line.long 0x0 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1040++0x3 line.long 0x0 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1044++0x3 line.long 0x0 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1050++0x3 line.long 0x0 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1054++0x3 line.long 0x0 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1058++0x3 line.long 0x0 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x105C++0x3 line.long 0x0 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1060++0x3 line.long 0x0 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1064++0x3 line.long 0x0 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1068++0x3 line.long 0x0 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x106C++0x3 line.long 0x0 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. . In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1070++0x3 line.long 0x0 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1074++0x3 line.long 0x0 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" bitfld.long 0x0 1. " SET ,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1080++0x3 line.long 0x0 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1084++0x3 line.long 0x0 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1088++0x3 line.long 0x0 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x108C++0x3 line.long 0x0 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1090++0x3 line.long 0x0 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1094++0x3 line.long 0x0 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2000++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2200++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2400++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2600++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2800++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2004++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2204++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2404++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2604++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2804++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2008++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2208++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2408++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2608++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2808++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x200C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x220C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x240C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x260C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x280C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2010++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2210++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2410++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2610++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2810++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2014++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2214++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2414++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2614++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2814++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2018++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2218++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2418++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2618++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2818++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x201C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x221C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x241C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x261C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x281C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2020++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2220++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2420++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2620++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2820++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2024++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2224++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2424++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2624++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2824++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2028++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2228++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2428++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2628++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2828++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x202C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x222C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x242C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x262C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x282C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2030++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2230++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2430++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2630++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2830++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2034++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2234++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2434++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2634++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2834++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2038++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2238++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2438++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2638++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2838++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x203C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x223C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x243C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x263C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x283C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2040++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2240++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2440++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2640++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2840++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2044++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2244++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2444++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2644++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2844++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2050++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2250++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2450++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2650++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2850++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2054++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2254++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2454++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2654++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2854++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2058++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2258++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2458++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2658++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2858++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x205C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x225C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x245C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x265C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x285C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2060++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2260++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2460++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2660++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2860++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2064++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2264++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2464++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2664++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2864++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2068++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2268++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2468++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2668++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2868++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x206C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x226C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x246C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x266C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x286C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2070++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2270++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2470++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2670++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2870++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2074++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2274++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2474++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2674++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2874++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2278++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2478++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2678++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2878++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2A78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2C78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2E78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2080++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2280++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2480++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2680++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2880++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2084++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2284++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2484++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2684++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2884++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2088++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2288++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2488++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2688++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2888++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x208C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x228C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x248C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x268C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x288C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2090++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2290++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2490++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2690++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2890++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2094++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2294++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2494++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2694++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2894++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2A94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2C94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2E94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x4000++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_0,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4020++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_1,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4040++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_2,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4060++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_3,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4080++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_4,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_5,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_6,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_7,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4100++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_8,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4120++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_9,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4140++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_10,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4160++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_11,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4180++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_12,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_13,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_14,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_15,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4200++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_16,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4220++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_17,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4240++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_18,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4260++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_19,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4280++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_20,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_21,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_22,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_23,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4300++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_24,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4320++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_25,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4340++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_26,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4360++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_27,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4380++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_28,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_29,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_30,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_31,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4400++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_32,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4420++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_33,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4440++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_34,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4460++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_35,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4480++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_36,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_37,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_38,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_39,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4500++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_40,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4520++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_41,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4540++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_42,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4560++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_43,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4580++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_44,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_45,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_46,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_47,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4600++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_48,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4620++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_49,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4640++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_50,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4660++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_51,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4680++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_52,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_53,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_54,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_55,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4700++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_56,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4720++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_57,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4740++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_58,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4760++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_59,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4780++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_60,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_61,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_62,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_63,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4800++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_64,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4820++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_65,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4840++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_66,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4860++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_67,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4880++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_68,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_69,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_70,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_71,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4900++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_72,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4920++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_73,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4940++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_74,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4960++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_75,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4980++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_76,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_77,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_78,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_79,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_80,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_81,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_82,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_83,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_84,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_85,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_86,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_87,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_88,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_89,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_90,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_91,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_92,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_93,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_94,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_95,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_96,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_97,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_98,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_99,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_100,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_101,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_102,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_103,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_104,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_105,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_106,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_107,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_108,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_109,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_110,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_111,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_112,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_113,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_114,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_115,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_116,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_117,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_118,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_119,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_120,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_121,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_122,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_123,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_124,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_125,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_126,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_127,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4004++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_0,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4024++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_1,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4044++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_2,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4064++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_3,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4084++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_4,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_5,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_6,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_7,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4104++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_8,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4124++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_9,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4144++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_10,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4164++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_11,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4184++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_12,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_13,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_14,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_15,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4204++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_16,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4224++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_17,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4244++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_18,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4264++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_19,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4284++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_20,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_21,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_22,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_23,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4304++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_24,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4324++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_25,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4344++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_26,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4364++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_27,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4384++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_28,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_29,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_30,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_31,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4404++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_32,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4424++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_33,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4444++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_34,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4464++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_35,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4484++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_36,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_37,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_38,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_39,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4504++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_40,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4524++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_41,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4544++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_42,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4564++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_43,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4584++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_44,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_45,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_46,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_47,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4604++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_48,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4624++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_49,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4644++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_50,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4664++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_51,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4684++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_52,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_53,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_54,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_55,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4704++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_56,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4724++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_57,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4744++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_58,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4764++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_59,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4784++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_60,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_61,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_62,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_63,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4804++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_64,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4824++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_65,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4844++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_66,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4864++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_67,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4884++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_68,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_69,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_70,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_71,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4904++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_72,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4924++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_73,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4944++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_74,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4964++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_75,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4984++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_76,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_77,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_78,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_79,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_80,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_81,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_82,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_83,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_84,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_85,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_86,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_87,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_88,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_89,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_90,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_91,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_92,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_93,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_94,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_95,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_96,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_97,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_98,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_99,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_100,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_101,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_102,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_103,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_104,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_105,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_106,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_107,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_108,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_109,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_110,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_111,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_112,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_113,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_114,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_115,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_116,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_117,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_118,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_119,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_120,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_121,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_122,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_123,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_124,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_125,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_126,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_127,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4008++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4028++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4048++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4068++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4088++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4108++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4128++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4148++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4168++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4188++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4208++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4228++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4248++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4268++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4288++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4308++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4328++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4348++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4368++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4388++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4408++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4428++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4448++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4468++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4488++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4508++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4528++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4548++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4568++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4588++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4608++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4628++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4648++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4668++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4688++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4708++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4728++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4748++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4768++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4788++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4808++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4828++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4848++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4868++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4888++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4908++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4928++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4948++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4968++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4988++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x400C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_0,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x402C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_1,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x404C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_2,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x406C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_3,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x408C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_4,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_5,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_6,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_7,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x410C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_8,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x412C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_9,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x414C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_10,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x416C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_11,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x418C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_12,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_13,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_14,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_15,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x420C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_16,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x422C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_17,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x424C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_18,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x426C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_19,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x428C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_20,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_21,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_22,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_23,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x430C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_24,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x432C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_25,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x434C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_26,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x436C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_27,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x438C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_28,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_29,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_30,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_31,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x440C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_32,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x442C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_33,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x444C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_34,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x446C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_35,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x448C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_36,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_37,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_38,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_39,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x450C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_40,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x452C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_41,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x454C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_42,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x456C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_43,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x458C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_44,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_45,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_46,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_47,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x460C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_48,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x462C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_49,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x464C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_50,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x466C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_51,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x468C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_52,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_53,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_54,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_55,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x470C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_56,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x472C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_57,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x474C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_58,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x476C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_59,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x478C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_60,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_61,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_62,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_63,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x480C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_64,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x482C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_65,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x484C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_66,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x486C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_67,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x488C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_68,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_69,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_70,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_71,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x490C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_72,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x492C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_73,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x494C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_74,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x496C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_75,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x498C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_76,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_77,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_78,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_79,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_80,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_81,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_82,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_83,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_84,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_85,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ACC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_86,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_87,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_88,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_89,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_90,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_91,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_92,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_93,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_94,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_95,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_96,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_97,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_98,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_99,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_100,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_101,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_102,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_103,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_104,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_105,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_106,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_107,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_108,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_109,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_110,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_111,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_112,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_113,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_114,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_115,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_116,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_117,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ECC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_118,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_119,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_120,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_121,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_122,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_123,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_124,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_125,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_126,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_127,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4010++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_0,EDMA_TPCC_BIDX_n_0" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4030++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_1,EDMA_TPCC_BIDX_n_1" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4050++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_2,EDMA_TPCC_BIDX_n_2" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4070++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_3,EDMA_TPCC_BIDX_n_3" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4090++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_4,EDMA_TPCC_BIDX_n_4" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_5,EDMA_TPCC_BIDX_n_5" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_6,EDMA_TPCC_BIDX_n_6" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_7,EDMA_TPCC_BIDX_n_7" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4110++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_8,EDMA_TPCC_BIDX_n_8" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4130++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_9,EDMA_TPCC_BIDX_n_9" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4150++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_10,EDMA_TPCC_BIDX_n_10" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4170++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_11,EDMA_TPCC_BIDX_n_11" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4190++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_12,EDMA_TPCC_BIDX_n_12" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_13,EDMA_TPCC_BIDX_n_13" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_14,EDMA_TPCC_BIDX_n_14" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_15,EDMA_TPCC_BIDX_n_15" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4210++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_16,EDMA_TPCC_BIDX_n_16" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4230++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_17,EDMA_TPCC_BIDX_n_17" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4250++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_18,EDMA_TPCC_BIDX_n_18" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4270++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_19,EDMA_TPCC_BIDX_n_19" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4290++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_20,EDMA_TPCC_BIDX_n_20" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_21,EDMA_TPCC_BIDX_n_21" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_22,EDMA_TPCC_BIDX_n_22" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_23,EDMA_TPCC_BIDX_n_23" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4310++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_24,EDMA_TPCC_BIDX_n_24" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4330++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_25,EDMA_TPCC_BIDX_n_25" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4350++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_26,EDMA_TPCC_BIDX_n_26" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4370++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_27,EDMA_TPCC_BIDX_n_27" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4390++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_28,EDMA_TPCC_BIDX_n_28" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_29,EDMA_TPCC_BIDX_n_29" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_30,EDMA_TPCC_BIDX_n_30" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_31,EDMA_TPCC_BIDX_n_31" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4410++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_32,EDMA_TPCC_BIDX_n_32" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4430++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_33,EDMA_TPCC_BIDX_n_33" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4450++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_34,EDMA_TPCC_BIDX_n_34" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4470++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_35,EDMA_TPCC_BIDX_n_35" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4490++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_36,EDMA_TPCC_BIDX_n_36" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_37,EDMA_TPCC_BIDX_n_37" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_38,EDMA_TPCC_BIDX_n_38" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_39,EDMA_TPCC_BIDX_n_39" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4510++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_40,EDMA_TPCC_BIDX_n_40" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4530++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_41,EDMA_TPCC_BIDX_n_41" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4550++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_42,EDMA_TPCC_BIDX_n_42" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4570++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_43,EDMA_TPCC_BIDX_n_43" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4590++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_44,EDMA_TPCC_BIDX_n_44" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_45,EDMA_TPCC_BIDX_n_45" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_46,EDMA_TPCC_BIDX_n_46" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_47,EDMA_TPCC_BIDX_n_47" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4610++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_48,EDMA_TPCC_BIDX_n_48" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4630++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_49,EDMA_TPCC_BIDX_n_49" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4650++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_50,EDMA_TPCC_BIDX_n_50" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4670++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_51,EDMA_TPCC_BIDX_n_51" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4690++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_52,EDMA_TPCC_BIDX_n_52" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_53,EDMA_TPCC_BIDX_n_53" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_54,EDMA_TPCC_BIDX_n_54" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_55,EDMA_TPCC_BIDX_n_55" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4710++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_56,EDMA_TPCC_BIDX_n_56" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4730++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_57,EDMA_TPCC_BIDX_n_57" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4750++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_58,EDMA_TPCC_BIDX_n_58" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4770++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_59,EDMA_TPCC_BIDX_n_59" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4790++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_60,EDMA_TPCC_BIDX_n_60" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_61,EDMA_TPCC_BIDX_n_61" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_62,EDMA_TPCC_BIDX_n_62" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_63,EDMA_TPCC_BIDX_n_63" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4810++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_64,EDMA_TPCC_BIDX_n_64" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4830++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_65,EDMA_TPCC_BIDX_n_65" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4850++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_66,EDMA_TPCC_BIDX_n_66" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4870++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_67,EDMA_TPCC_BIDX_n_67" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4890++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_68,EDMA_TPCC_BIDX_n_68" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_69,EDMA_TPCC_BIDX_n_69" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_70,EDMA_TPCC_BIDX_n_70" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_71,EDMA_TPCC_BIDX_n_71" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4910++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_72,EDMA_TPCC_BIDX_n_72" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4930++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_73,EDMA_TPCC_BIDX_n_73" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4950++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_74,EDMA_TPCC_BIDX_n_74" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4970++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_75,EDMA_TPCC_BIDX_n_75" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4990++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_76,EDMA_TPCC_BIDX_n_76" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_77,EDMA_TPCC_BIDX_n_77" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_78,EDMA_TPCC_BIDX_n_78" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_79,EDMA_TPCC_BIDX_n_79" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_80,EDMA_TPCC_BIDX_n_80" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_81,EDMA_TPCC_BIDX_n_81" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_82,EDMA_TPCC_BIDX_n_82" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_83,EDMA_TPCC_BIDX_n_83" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_84,EDMA_TPCC_BIDX_n_84" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_85,EDMA_TPCC_BIDX_n_85" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_86,EDMA_TPCC_BIDX_n_86" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_87,EDMA_TPCC_BIDX_n_87" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_88,EDMA_TPCC_BIDX_n_88" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_89,EDMA_TPCC_BIDX_n_89" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_90,EDMA_TPCC_BIDX_n_90" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_91,EDMA_TPCC_BIDX_n_91" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_92,EDMA_TPCC_BIDX_n_92" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_93,EDMA_TPCC_BIDX_n_93" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_94,EDMA_TPCC_BIDX_n_94" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_95,EDMA_TPCC_BIDX_n_95" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_96,EDMA_TPCC_BIDX_n_96" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_97,EDMA_TPCC_BIDX_n_97" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_98,EDMA_TPCC_BIDX_n_98" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_99,EDMA_TPCC_BIDX_n_99" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_100,EDMA_TPCC_BIDX_n_100" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_101,EDMA_TPCC_BIDX_n_101" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_102,EDMA_TPCC_BIDX_n_102" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_103,EDMA_TPCC_BIDX_n_103" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_104,EDMA_TPCC_BIDX_n_104" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_105,EDMA_TPCC_BIDX_n_105" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_106,EDMA_TPCC_BIDX_n_106" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_107,EDMA_TPCC_BIDX_n_107" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_108,EDMA_TPCC_BIDX_n_108" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_109,EDMA_TPCC_BIDX_n_109" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_110,EDMA_TPCC_BIDX_n_110" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_111,EDMA_TPCC_BIDX_n_111" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_112,EDMA_TPCC_BIDX_n_112" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_113,EDMA_TPCC_BIDX_n_113" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_114,EDMA_TPCC_BIDX_n_114" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_115,EDMA_TPCC_BIDX_n_115" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_116,EDMA_TPCC_BIDX_n_116" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_117,EDMA_TPCC_BIDX_n_117" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4ED0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_118,EDMA_TPCC_BIDX_n_118" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_119,EDMA_TPCC_BIDX_n_119" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_120,EDMA_TPCC_BIDX_n_120" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_121,EDMA_TPCC_BIDX_n_121" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_122,EDMA_TPCC_BIDX_n_122" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_123,EDMA_TPCC_BIDX_n_123" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_124,EDMA_TPCC_BIDX_n_124" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_125,EDMA_TPCC_BIDX_n_125" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_126,EDMA_TPCC_BIDX_n_126" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_127,EDMA_TPCC_BIDX_n_127" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4014++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4034++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4054++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4074++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4094++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4114++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4134++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4154++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4174++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4194++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4214++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4234++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4254++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4274++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4294++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4314++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4334++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4354++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4374++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4394++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4414++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4434++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4454++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4474++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4494++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4514++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4534++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4554++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4574++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4594++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4614++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4634++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4654++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4674++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4694++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4714++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4734++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4754++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4774++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4794++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4814++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4834++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4854++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4874++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4894++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4914++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4934++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4954++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4974++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4994++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4ED4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4018++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4038++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4058++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4078++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4098++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4118++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4138++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4158++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4178++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4198++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4218++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4238++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4258++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4278++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4298++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4318++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4338++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4358++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4378++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4398++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4418++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4438++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4458++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4478++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4498++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4518++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4538++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4558++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4578++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4598++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4618++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4638++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4658++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4678++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4698++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4718++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4738++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4758++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4778++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4798++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4818++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4838++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4858++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4878++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4898++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4918++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4938++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4958++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4978++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4998++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4ED8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x401C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x403C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x405C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x407C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x409C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x411C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x413C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x415C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x417C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x419C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x421C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x423C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x425C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x427C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x429C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x431C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x433C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x435C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x437C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x439C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x441C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x443C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x445C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x447C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x449C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x451C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x453C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x455C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x457C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x459C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x461C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x463C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x465C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x467C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x469C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x471C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x473C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x475C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x477C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x479C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x481C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x483C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x485C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x487C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x489C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x491C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x493C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x495C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x497C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x499C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ABC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ADC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4AFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_SYSTEM" base ad:0x40D00000 width 33. group.byte 0x0++0x3 line.long 0x0 "DSP_SYS_REVISION,DSP_SYS_REVISION" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "DSP_SYS_HWINFO,DSP_SYS_HWINFO" bitfld.long 0x0 0.--3. " NUM ,Instance Number Set by subsystem input. In a multi-DSP system, provides a unique/incrementing values for each DSP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " INFO ,0x0: No configurable options in subsystem." group.byte 0x8++0x3 line.long 0x0 "DSP_SYS_SYSCONFIG,DSP_SYS_SYSCONFIG" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,0x0: FORCE_IDLE This mode is a backup mode intended to be used only if the smart-idle mode is bugged. When in this mode, the IAF acknowledges a request to go idle from the power manager with minimal hardware condition. It is the responsibility of the software to ensure that the IAF are in a correct quiet state before requesting a force-idle transition. Additionally when in this mode, the IAF is not allowed to generate any wakeup request." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,0x0: FORCE_STANDBY This mode is a backup mode intended to be used only if the smart-idle mode is bugged. When in this mode, the SAF asserts with minimal hardware condition the 'STANDBY' status. It is the responsibility of the software to ensure that the SAF is in a correct quiet state before programming this mode. Additionally when in this mode, the SAF is not allowed to generate wakeup request." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reserved. Read returns 0." "0,1,2,3" textline " " bitfld.long 0x0 8. " RESERVED ,Reserved. User must write 0." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved. Read returns 0." group.byte 0xC++0x3 line.long 0x0 "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode." bitfld.long 0x0 0. " C66X_STAT ,C66x Status" "0,1" bitfld.long 0x0 1. " TC0_STAT ,EDMA TC0 Status" "0,1" textline " " bitfld.long 0x0 2. " TC1_STAT ,EDMA TC1 Status" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--5. " OCPI_DISC_STAT ,L3_MAIN (OCP) Initiator(s) Disconnect Status" "0,1,2,3" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses." bitfld.long 0x0 0. " OCPI_DISC ,OCP Initiator (on L3_MAIN) Disconnect request" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators." bitfld.long 0x0 0.--1. " TC0_DBS ,TC0 Default Burst size" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " TC1_DBS ,TC1 Default Burst size." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " TC0_L2PRES ,TC0 L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect." "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " TC1_L2PRES ,TC1 L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " CFG_L2PRES ,DSP CFG L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect" "0,1,2,3" bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " SDMA_L2PRES ,OCP Target port L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect." "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24. " NOPOSTOVERRIDE ,OCP Posted Write vs Non-Posted Write override" "0,1" bitfld.long 0x0 25.--27. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 28.--30. " SDMA_PRI ,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port. Can typically be left at default value. 0x0 is highest, ..., 0x7 is lowest priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x18++0x3 line.long 0x0 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs." bitfld.long 0x0 0. " MMU0_EN ,MMU0 Enable" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " MMU1_EN ,MMU1 Enable" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " MMU0_ABORT ,MMU0 Abort" "0,1" bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12. " MMU1_ABORT ,MMU1 Abort" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol). IRQWAKEEN0 is for interrupt inputs 63 thru 32, and IRQWAKEEN1 is for interrupt inputs 95 thru 64. Internal interrupts cannot cause a wake condition since in this state there is no guaranteed clock and all sub-modules should be in idle state. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding interrupt for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable bit vector for interrupt #n+32" group.byte 0x24++0x3 line.long 0x0 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol). IRQWAKEEN0 is for interrupt inputs 63 thru 32, and IRQWAKEEN1 is for interrupt inputs 95 thru 64. Internal interrupts cannot cause a wake condition since in this state there is no guaranteed clock and all sub-modules should be in idle state. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding interrupt for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable bit vector for interrupt #n+64" group.byte 0x30++0x3 line.long 0x0 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol). DMAWAKEEN0 is for dma event inputs 31 thru 0, and DMAWAKEEN1 is for dma event inputs 63 thru 32. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding dma event for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable for event #n" group.byte 0x34++0x3 line.long 0x0 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol). DMAWAKEEN0 is for dma event inputs 31 thru 0, and DMAWAKEEN1 is for dma event inputs 63 thru 32. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding dma event for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable for event #n+32" group.byte 0x40++0x3 line.long 0x0 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state." hexmask.long 0x0 0.--31. 1. " EVENT ,Output Event for event #n" group.byte 0x44++0x3 line.long 0x0 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state." hexmask.long 0x0 0.--31. 1. " EVENT ,Output Event for event #n" group.byte 0x50++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x0 0.--18. 1. " EVENT ,Settable raw status for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long.tbyte 0x0 0.--18. 1. " EVENT ,Clearable ,Clearable ,Clearable, enabled status for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long.tbyte 0x0 0.--18. 1. " ENABLE ,Enable for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long.tbyte 0x0 0.--18. 1. " ENABLE ,Enable for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long 0x0 0.--31. 1. " EVENT ,Settable raw status for event #n" group.byte 0x64++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long 0x0 0.--31. 1. " EVENT,Clearable ,Clearable ,Clearable, enabled status for event #n" group.byte 0x68++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n" group.byte 0x6C++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n" group.byte 0x70++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long 0x0 0.--31. 1. " EVENT ,Settable raw status for event #n+32" group.byte 0x74++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long 0x0 0.--31. 1. " EVENT,Clearable ,Clearable ,Clearable, enabled status for event #n+32" group.byte 0x78++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n+32" group.byte 0x7C++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n+32" group.byte 0xF8++0x3 line.long 0x0 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus." bitfld.long 0x0 0.--3. " GROUP ,Debug Group output control mux selectN: GN = select output group N ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0xFC++0x3 line.long 0x0 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group." hexmask.long 0x0 0.--31. 1. " VALUE ,Read returns state of hw_dbgout bus" width 0x0B tree.end tree "DSP1_MMU0CFG" base ad:0x40D01000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_MMU1CFG" base ad:0x40D02000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_FW_L2_NOC_CFG" base ad:0x40D03000 width 77. group.byte 0x0++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" hexmask.long.word 0x0 0.--15. 1. " REQINFO_ERRLOG ,Error in reqinfo vector" bitfld.long 0x0 16.--20. " REGION_END_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGION_START_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26. " RESERVED ," "0,1" textline " " bitfld.long 0x0 27. " BLK_BURST_VIOLATION ,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x0 0.--27. 1. " SLVOFS_LOGICAL ,Address generated by the ARM before being translated" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " FW_UPDATE_REQ ,HW set/SW clear" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,HW set/SW clear" "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x88++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,MRM_PERMISSION_REGION_0_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x90++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" bitfld.long 0x0 0.--3. " START_REGION_1 ,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0 0.--3. " END_REGION_1 ,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " END_REGION_1_ENABLE ,End Region 1 enable" "0,1" group.byte 0x98++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x1000++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" hexmask.long.word 0x0 0.--15. 1. " REQINFO_ERRLOG ,Error in reqinfo vector" bitfld.long 0x0 16.--20. " REGION_END_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGION_START_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26. " RESERVED ," "0,1" textline " " bitfld.long 0x0 27. " BLK_BURST_VIOLATION ,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1004++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x0 0.--27. 1. " SLVOFS_LOGICAL ,Address generated by the ARM before being translated" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1040++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " FW_UPDATE_REQ ,HW set/SW clear" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,HW set/SW clear" "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x1088++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x108C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x4000++0x3 line.long 0x0 "DSPNOC_FLAGMUX_ID_COREID,DSPNOC_FLAGMUX_ID_COREID" hexmask.long.byte 0x0 0.--7. 1. " CORETYPEID ,Field identifying the type of IP." hexmask.long.tbyte 0x0 8.--31. 1. " CORECHECKSUM ,Field containing a checksum of the parameters of the IP." group.byte 0x4004++0x3 line.long 0x0 "DSPNOC_FLAGMUX_ID_REVISIONID,DSPNOC_FLAGMUX_ID_REVISIONID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4008++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FAULTEN,DSPNOC_FLAGMUX_FAULTEN" bitfld.long 0x0 0. " FAULTEN ,Global Fault Enable register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x400C++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FAULTSTATUS,DSPNOC_FLAGMUX_FAULTSTATUS" bitfld.long 0x0 0. " FAULTSTATUS ,Global Fault Status register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4010++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FLAGINEN0,DSPNOC_FLAGMUX_FLAGINEN0" bitfld.long 0x0 0. " FLAGINEN0 ,FlagIn Enable register #0" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4014++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FLAGINSTATUS0,DSPNOC_FLAGMUX_FLAGINSTATUS0" bitfld.long 0x0 0. " FLAGINSTATUS0 ,FlagIn Status register #0" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4200++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ID_COREID,DSPNOC_ERRORLOG_ID_COREID" hexmask.long.byte 0x0 0.--7. 1. " CORETYPEID ,Field identifying the type of IP." hexmask.long.tbyte 0x0 8.--31. 1. " CORECHECKSUM ,Field containing a checksum of the parameters of the IP." group.byte 0x4204++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ID_REVISIONID,DSPNOC_ERRORLOG_ID_REVISIONID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4208++0x3 line.long 0x0 "DSPNOC_ERRORLOG_FAULTEN,DSPNOC_ERRORLOG_FAULTEN" bitfld.long 0x0 0. " FAULTEN ,Enable Fault output" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x420C++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRVLD,DSPNOC_ERRORLOG_ERRVLD" bitfld.long 0x0 0. " ERRVLD ,Error logged Valid" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4210++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRCLR,DSPNOC_ERRORLOG_ERRCLR" bitfld.long 0x0 0. " ERRCLR ,Clr ErrVld status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4214++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock, Opcode, Len1, ErrCode values" bitfld.long 0x0 0. " LOCK ,Header: Lock bit value" "0,1" bitfld.long 0x0 1.--4. " OPC ,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. " ERRCODE ,Header: Error Code value" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--27. 1. " LEN1 ,Header: Len1 value" textline " " bitfld.long 0x0 28.--30. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " FORMAT ,Format of ErrLog0 register" "0,1" group.byte 0x4218++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG1,DSPNOC_ERRORLOG_ERRLOG1" hexmask.long.word 0x0 0.--14. 1. " ERRLOG1 ,Header: RouteId lsb value" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x4220++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG3,DSPNOC_ERRORLOG_ERRLOG3" hexmask.long 0x0 0.--30. 1. " ERRLOG3 ,Header: Addr lsb value" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x4228++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG5,DSPNOC_ERRORLOG_ERRLOG5" hexmask.long.tbyte 0x0 0.--21. 1. " ERRLOG5 ,Header: User lsb value" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "DSP1_EDMA_TC0" base ad:0x40D05000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_EDMA_TC1" base ad:0x40D06000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_EDMA_CC" base ad:0x40D10000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPCC_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x0 0.--2. " NUMDMACH ,Number of DMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--6. " NUMQDMACH ,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 8.--10. " NUMINTCH ,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 12.--14. " NUMPAENTRY ,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 16.--18. " NUMTC ,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 20.--21. " NUMREGN ,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 24. " CHMAPEXIST ,Channel Mapping Existence" "0,1" bitfld.long 0x0 25. " MPEXIST ,Memory Protection Existence" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reads return 0's" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xFC++0x3 line.long 0x0 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x0 0. " CLKGDIS ,Auto Clock Gate Disable" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x114++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x118++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x11C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x138++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x13C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x144++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x148++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x14C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x150++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x154++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x158++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x15C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x160++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x164++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x168++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x16C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x170++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x174++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x178++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x17C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x180++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x194++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x198++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x19C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1AC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1BC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1CC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1DC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1EC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x248++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x254++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x260++0x3 line.long 0x0 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." bitfld.long 0x0 0.--2. " E0 ,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x280++0x3 line.long 0x0 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x0 0.--2. " TCNUMQ0 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " TCNUMQ1 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x0 0.--2. " PRIQ0 ,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " PRIQ1 ,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x300++0x3 line.long 0x0 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed #31" "0,1" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E32 ,Event Missed #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed #63" "0,1" group.byte 0x308++0x3 line.long 0x0 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed Clear #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed Clear #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed Clear #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed Clear #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed Clear #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed Clear #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed Clear #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed Clear #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed Clear #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed Clear #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed Clear #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed Clear #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed Clear #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed Clear #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed Clear #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed Clear #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed Clear #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed Clear #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed Clear #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed Clear #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed Clear #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed Clear #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed Clear #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed Clear #31" "0,1" group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E32 ,Event Missed Clear #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed Clear #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed Clear #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed Clear #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed Clear #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed Clear #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed Clear #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed Clear #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed Clear #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed Clear #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed Clear #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed Clear #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed Clear #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed Clear #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed Clear #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed Clear #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed Clear #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed Clear #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed Clear #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed Clear #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed Clear #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed Clear #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed Clear #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed Clear #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed Clear #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed Clear #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed Clear #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed Clear #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed Clear #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed Clear #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed Clear #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed Clear #63" "0,1" group.byte 0x310++0x3 line.long 0x0 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced. If any bit in the register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x314++0x3 line.long 0x0 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x318++0x3 line.long 0x0 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x0 0. " QTHRXCD0 ,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors were previously clear), then an error will be signaled with TPCC error interrupt. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x31C++0x3 line.long 0x0 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x0 0. " QTHRXCD0 ,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT0.WM, QSTAT0.THRXCD,[0] QTHRXCD0 ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM, QSTAT1.THRXCD,[1] QTHRXCD1 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT2.WM, QSTAT2.THRXCD,[2] QTHRXCD2 ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM, QSTAT3.THRXCD,[3] QTHRXCD3 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT4.WM, QSTAT4.THRXCD,[4] QTHRXCD4 ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT5.WM, QSTAT5.THRXCD,[5]QTHRXCD5 ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT6.WM, QSTAT6.THRXCD,[6]QTHRXCD6 ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT7.WM, QSTAT7.THRXCD,[7] QTHRXCD7 ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR. . Write 0x0 have no affect. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x320++0x3 line.long 0x0 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x0 0. " EVAL ,Error Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the/, , or registers. The CPU must also write 0x1 after any error interrupts are serviced in order for subsequent interrupts to be asserted. ." "0,1" bitfld.long 0x0 1. " SET ,Error Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of/, , or . ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x348++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x350++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x358++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x360++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x368++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x370++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x378++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x344++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x35C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x364++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x36C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x374++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x37C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x380++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x388++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x38C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x39C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x400++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x404++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x408++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x40C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x410++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x414++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x418++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x41C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x420++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x424++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x428++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x42C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x430++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x434++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x438++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x43C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x440++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x444++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x448++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x44C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x450++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x454++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x458++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x45C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x460++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x464++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x468++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x46C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x470++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x474++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x478++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x47C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRA,Queue Threshold A, for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q0 ,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q1 ,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q2 ,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q3 ,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x624++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRB,Queue Threshold B, for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q4 ,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q5 ,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q6 ,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q7 ,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x0 0. " EVTACTV ,DMA Event Active" "0,1" bitfld.long 0x0 1. " QEVTACTV ,QDMA Event Active" "0,1" textline " " bitfld.long 0x0 2. " TRACTV ,Transfer Request Active TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0,1" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4. " ACTV ,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals. The ACTV bit must remain high through the life of a:" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,reads return 0's" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " COMPACTV ,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " QUEACTV0 ,Queue 0 Active" "0,1" bitfld.long 0x0 17. " QUEACTV1 ,Queue 1 Active" "0,1" textline " " bitfld.long 0x0 18. " QUEACTV2 ,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0,1" bitfld.long 0x0 19. " QUEACTV3 ,Queue 3 Active" "0,1" textline " " bitfld.long 0x0 20. " QUEACTV4 ,Queue 4 Active" "0,1" bitfld.long 0x0 21. " QUEACTV5 ,Queue 5 Active" "0,1" textline " " bitfld.long 0x0 22. " QUEACTV6 ,Queue 6 Active" "0,1" bitfld.long 0x0 23. " QUEACTV7 ,Queue 7 Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,reads return 0's" group.byte 0x700++0x3 line.long 0x0 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 0.--5. " STRTEVT ,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " TYPE ,AET Event Type" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--13. " ENDINT ,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.tbyte 0x0 14.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " EN ,AET Enable" "0,1" group.byte 0x704++0x3 line.long 0x0 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x0 0. " STAT ,AET Status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x708++0x3 line.long 0x0 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x0 0. " CLR ,AET Clear commandCPU writes 0x0 has no effect. . CPU writes 0x1 to the CLR bit causes the tpcc_aet output signal and[0]STAT register to be cleared. ." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" hexmask.long 0x0 0.--31. 1. " FADDR ,Fault Address: 32-bit read-only status register containing the faulting address when a mMemory protection violation is detected. This register can only be cleared via theEDMA_TPCC_MPFCR." group.byte 0x804++0x3 line.long 0x0 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x0 0. " UXE ,User Execute Error" "0,1" bitfld.long 0x0 1. " UWE ,User Write Error" "0,1" textline " " bitfld.long 0x0 2. " URE ,User Read Error" "0,1" bitfld.long 0x0 3. " SXE ,Supervisor Execute Error" "0,1" textline " " bitfld.long 0x0 4. " SWE ,Supervisor Write Error" "0,1" bitfld.long 0x0 5. " SRE ,Supervisor Read Error" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--12. " FID ,Faulted ID: FID register contains valid info if any of the MP error bits (UXE, UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x808++0x3 line.long 0x0 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x0 0. " MPFCLR ,Fault Clear register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x80C++0x3 line.long 0x0 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0" "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x810++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x814++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x818++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x81C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x820++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x824++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x828++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x82C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x1000++0x3 line.long 0x0 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1004++0x3 line.long 0x0 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1008++0x3 line.long 0x0 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x100C++0x3 line.long 0x0 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1010++0x3 line.long 0x0 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1014++0x3 line.long 0x0 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1018++0x3 line.long 0x0 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x101C++0x3 line.long 0x0 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1020++0x3 line.long 0x0 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1024++0x3 line.long 0x0 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1028++0x3 line.long 0x0 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x102C++0x3 line.long 0x0 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1030++0x3 line.long 0x0 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1034++0x3 line.long 0x0 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1038++0x3 line.long 0x0 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x103C++0x3 line.long 0x0 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1040++0x3 line.long 0x0 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1044++0x3 line.long 0x0 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1050++0x3 line.long 0x0 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1054++0x3 line.long 0x0 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1058++0x3 line.long 0x0 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x105C++0x3 line.long 0x0 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1060++0x3 line.long 0x0 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1064++0x3 line.long 0x0 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1068++0x3 line.long 0x0 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x106C++0x3 line.long 0x0 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. . In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1070++0x3 line.long 0x0 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1074++0x3 line.long 0x0 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" bitfld.long 0x0 1. " SET ,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1080++0x3 line.long 0x0 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1084++0x3 line.long 0x0 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1088++0x3 line.long 0x0 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x108C++0x3 line.long 0x0 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1090++0x3 line.long 0x0 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1094++0x3 line.long 0x0 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2000++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2200++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2400++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2600++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2800++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2004++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2204++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2404++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2604++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2804++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2008++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2208++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2408++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2608++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2808++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x200C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x220C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x240C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x260C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x280C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2010++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2210++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2410++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2610++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2810++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2014++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2214++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2414++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2614++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2814++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2018++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2218++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2418++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2618++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2818++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x201C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x221C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x241C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x261C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x281C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2020++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2220++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2420++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2620++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2820++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2024++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2224++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2424++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2624++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2824++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2028++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2228++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2428++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2628++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2828++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x202C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x222C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x242C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x262C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x282C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2030++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2230++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2430++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2630++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2830++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2034++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2234++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2434++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2634++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2834++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2038++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2238++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2438++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2638++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2838++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x203C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x223C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x243C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x263C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x283C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2040++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2240++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2440++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2640++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2840++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2044++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2244++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2444++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2644++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2844++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2050++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2250++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2450++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2650++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2850++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2054++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2254++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2454++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2654++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2854++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2058++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2258++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2458++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2658++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2858++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x205C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x225C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x245C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x265C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x285C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2060++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2260++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2460++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2660++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2860++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2064++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2264++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2464++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2664++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2864++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2068++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2268++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2468++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2668++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2868++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x206C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x226C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x246C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x266C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x286C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2070++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2270++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2470++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2670++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2870++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2074++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2274++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2474++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2674++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2874++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2278++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2478++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2678++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2878++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2A78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2C78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2E78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2080++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2280++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2480++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2680++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2880++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2084++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2284++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2484++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2684++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2884++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2088++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2288++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2488++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2688++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2888++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x208C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x228C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x248C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x268C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x288C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2090++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2290++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2490++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2690++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2890++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2094++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2294++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2494++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2694++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2894++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2A94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2C94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2E94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x4000++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_0,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4020++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_1,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4040++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_2,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4060++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_3,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4080++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_4,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_5,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_6,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_7,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4100++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_8,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4120++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_9,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4140++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_10,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4160++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_11,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4180++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_12,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_13,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_14,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_15,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4200++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_16,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4220++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_17,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4240++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_18,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4260++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_19,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4280++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_20,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_21,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_22,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_23,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4300++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_24,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4320++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_25,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4340++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_26,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4360++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_27,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4380++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_28,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_29,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_30,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_31,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4400++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_32,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4420++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_33,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4440++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_34,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4460++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_35,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4480++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_36,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_37,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_38,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_39,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4500++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_40,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4520++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_41,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4540++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_42,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4560++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_43,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4580++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_44,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_45,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_46,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_47,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4600++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_48,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4620++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_49,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4640++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_50,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4660++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_51,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4680++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_52,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_53,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_54,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_55,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4700++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_56,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4720++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_57,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4740++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_58,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4760++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_59,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4780++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_60,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_61,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_62,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_63,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4800++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_64,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4820++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_65,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4840++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_66,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4860++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_67,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4880++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_68,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_69,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_70,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_71,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4900++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_72,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4920++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_73,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4940++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_74,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4960++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_75,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4980++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_76,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_77,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_78,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_79,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_80,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_81,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_82,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_83,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_84,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_85,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_86,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_87,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_88,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_89,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_90,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_91,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_92,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_93,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_94,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_95,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_96,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_97,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_98,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_99,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_100,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_101,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_102,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_103,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_104,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_105,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_106,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_107,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_108,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_109,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_110,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_111,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_112,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_113,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_114,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_115,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_116,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_117,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_118,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_119,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_120,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_121,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_122,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_123,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_124,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_125,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_126,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_127,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4004++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_0,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4024++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_1,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4044++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_2,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4064++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_3,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4084++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_4,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_5,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_6,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_7,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4104++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_8,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4124++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_9,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4144++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_10,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4164++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_11,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4184++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_12,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_13,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_14,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_15,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4204++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_16,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4224++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_17,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4244++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_18,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4264++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_19,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4284++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_20,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_21,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_22,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_23,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4304++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_24,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4324++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_25,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4344++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_26,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4364++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_27,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4384++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_28,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_29,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_30,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_31,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4404++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_32,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4424++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_33,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4444++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_34,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4464++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_35,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4484++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_36,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_37,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_38,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_39,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4504++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_40,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4524++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_41,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4544++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_42,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4564++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_43,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4584++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_44,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_45,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_46,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_47,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4604++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_48,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4624++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_49,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4644++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_50,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4664++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_51,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4684++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_52,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_53,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_54,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_55,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4704++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_56,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4724++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_57,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4744++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_58,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4764++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_59,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4784++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_60,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_61,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_62,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_63,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4804++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_64,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4824++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_65,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4844++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_66,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4864++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_67,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4884++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_68,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_69,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_70,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_71,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4904++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_72,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4924++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_73,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4944++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_74,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4964++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_75,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4984++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_76,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_77,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_78,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_79,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_80,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_81,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_82,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_83,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_84,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_85,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_86,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_87,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_88,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_89,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_90,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_91,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_92,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_93,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_94,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_95,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_96,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_97,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_98,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_99,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_100,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_101,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_102,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_103,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_104,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_105,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_106,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_107,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_108,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_109,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_110,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_111,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_112,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_113,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_114,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_115,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_116,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_117,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_118,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_119,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_120,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_121,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_122,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_123,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_124,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_125,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_126,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_127,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4008++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4028++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4048++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4068++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4088++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4108++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4128++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4148++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4168++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4188++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4208++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4228++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4248++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4268++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4288++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4308++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4328++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4348++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4368++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4388++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4408++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4428++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4448++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4468++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4488++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4508++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4528++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4548++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4568++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4588++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4608++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4628++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4648++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4668++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4688++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4708++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4728++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4748++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4768++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4788++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4808++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4828++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4848++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4868++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4888++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4908++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4928++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4948++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4968++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4988++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x400C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_0,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x402C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_1,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x404C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_2,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x406C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_3,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x408C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_4,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_5,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_6,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_7,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x410C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_8,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x412C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_9,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x414C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_10,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x416C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_11,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x418C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_12,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_13,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_14,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_15,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x420C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_16,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x422C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_17,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x424C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_18,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x426C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_19,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x428C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_20,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_21,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_22,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_23,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x430C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_24,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x432C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_25,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x434C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_26,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x436C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_27,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x438C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_28,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_29,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_30,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_31,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x440C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_32,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x442C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_33,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x444C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_34,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x446C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_35,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x448C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_36,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_37,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_38,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_39,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x450C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_40,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x452C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_41,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x454C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_42,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x456C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_43,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x458C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_44,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_45,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_46,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_47,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x460C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_48,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x462C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_49,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x464C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_50,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x466C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_51,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x468C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_52,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_53,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_54,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_55,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x470C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_56,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x472C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_57,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x474C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_58,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x476C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_59,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x478C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_60,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_61,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_62,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_63,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x480C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_64,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x482C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_65,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x484C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_66,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x486C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_67,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x488C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_68,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_69,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_70,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_71,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x490C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_72,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x492C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_73,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x494C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_74,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x496C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_75,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x498C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_76,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_77,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_78,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_79,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_80,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_81,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_82,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_83,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_84,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_85,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ACC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_86,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_87,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_88,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_89,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_90,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_91,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_92,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_93,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_94,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_95,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_96,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_97,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_98,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_99,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_100,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_101,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_102,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_103,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_104,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_105,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_106,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_107,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_108,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_109,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_110,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_111,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_112,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_113,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_114,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_115,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_116,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_117,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ECC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_118,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_119,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_120,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_121,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_122,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_123,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_124,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_125,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_126,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_127,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4010++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_0,EDMA_TPCC_BIDX_n_0" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4030++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_1,EDMA_TPCC_BIDX_n_1" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4050++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_2,EDMA_TPCC_BIDX_n_2" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4070++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_3,EDMA_TPCC_BIDX_n_3" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4090++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_4,EDMA_TPCC_BIDX_n_4" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_5,EDMA_TPCC_BIDX_n_5" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_6,EDMA_TPCC_BIDX_n_6" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_7,EDMA_TPCC_BIDX_n_7" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4110++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_8,EDMA_TPCC_BIDX_n_8" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4130++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_9,EDMA_TPCC_BIDX_n_9" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4150++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_10,EDMA_TPCC_BIDX_n_10" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4170++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_11,EDMA_TPCC_BIDX_n_11" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4190++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_12,EDMA_TPCC_BIDX_n_12" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_13,EDMA_TPCC_BIDX_n_13" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_14,EDMA_TPCC_BIDX_n_14" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_15,EDMA_TPCC_BIDX_n_15" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4210++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_16,EDMA_TPCC_BIDX_n_16" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4230++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_17,EDMA_TPCC_BIDX_n_17" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4250++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_18,EDMA_TPCC_BIDX_n_18" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4270++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_19,EDMA_TPCC_BIDX_n_19" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4290++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_20,EDMA_TPCC_BIDX_n_20" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_21,EDMA_TPCC_BIDX_n_21" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_22,EDMA_TPCC_BIDX_n_22" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_23,EDMA_TPCC_BIDX_n_23" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4310++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_24,EDMA_TPCC_BIDX_n_24" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4330++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_25,EDMA_TPCC_BIDX_n_25" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4350++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_26,EDMA_TPCC_BIDX_n_26" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4370++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_27,EDMA_TPCC_BIDX_n_27" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4390++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_28,EDMA_TPCC_BIDX_n_28" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_29,EDMA_TPCC_BIDX_n_29" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_30,EDMA_TPCC_BIDX_n_30" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_31,EDMA_TPCC_BIDX_n_31" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4410++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_32,EDMA_TPCC_BIDX_n_32" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4430++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_33,EDMA_TPCC_BIDX_n_33" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4450++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_34,EDMA_TPCC_BIDX_n_34" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4470++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_35,EDMA_TPCC_BIDX_n_35" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4490++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_36,EDMA_TPCC_BIDX_n_36" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_37,EDMA_TPCC_BIDX_n_37" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_38,EDMA_TPCC_BIDX_n_38" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_39,EDMA_TPCC_BIDX_n_39" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4510++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_40,EDMA_TPCC_BIDX_n_40" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4530++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_41,EDMA_TPCC_BIDX_n_41" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4550++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_42,EDMA_TPCC_BIDX_n_42" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4570++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_43,EDMA_TPCC_BIDX_n_43" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4590++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_44,EDMA_TPCC_BIDX_n_44" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_45,EDMA_TPCC_BIDX_n_45" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_46,EDMA_TPCC_BIDX_n_46" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_47,EDMA_TPCC_BIDX_n_47" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4610++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_48,EDMA_TPCC_BIDX_n_48" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4630++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_49,EDMA_TPCC_BIDX_n_49" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4650++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_50,EDMA_TPCC_BIDX_n_50" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4670++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_51,EDMA_TPCC_BIDX_n_51" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4690++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_52,EDMA_TPCC_BIDX_n_52" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_53,EDMA_TPCC_BIDX_n_53" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_54,EDMA_TPCC_BIDX_n_54" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_55,EDMA_TPCC_BIDX_n_55" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4710++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_56,EDMA_TPCC_BIDX_n_56" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4730++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_57,EDMA_TPCC_BIDX_n_57" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4750++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_58,EDMA_TPCC_BIDX_n_58" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4770++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_59,EDMA_TPCC_BIDX_n_59" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4790++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_60,EDMA_TPCC_BIDX_n_60" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_61,EDMA_TPCC_BIDX_n_61" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_62,EDMA_TPCC_BIDX_n_62" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_63,EDMA_TPCC_BIDX_n_63" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4810++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_64,EDMA_TPCC_BIDX_n_64" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4830++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_65,EDMA_TPCC_BIDX_n_65" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4850++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_66,EDMA_TPCC_BIDX_n_66" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4870++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_67,EDMA_TPCC_BIDX_n_67" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4890++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_68,EDMA_TPCC_BIDX_n_68" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_69,EDMA_TPCC_BIDX_n_69" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_70,EDMA_TPCC_BIDX_n_70" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_71,EDMA_TPCC_BIDX_n_71" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4910++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_72,EDMA_TPCC_BIDX_n_72" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4930++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_73,EDMA_TPCC_BIDX_n_73" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4950++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_74,EDMA_TPCC_BIDX_n_74" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4970++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_75,EDMA_TPCC_BIDX_n_75" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4990++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_76,EDMA_TPCC_BIDX_n_76" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_77,EDMA_TPCC_BIDX_n_77" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_78,EDMA_TPCC_BIDX_n_78" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_79,EDMA_TPCC_BIDX_n_79" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_80,EDMA_TPCC_BIDX_n_80" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_81,EDMA_TPCC_BIDX_n_81" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_82,EDMA_TPCC_BIDX_n_82" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_83,EDMA_TPCC_BIDX_n_83" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_84,EDMA_TPCC_BIDX_n_84" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_85,EDMA_TPCC_BIDX_n_85" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_86,EDMA_TPCC_BIDX_n_86" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_87,EDMA_TPCC_BIDX_n_87" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_88,EDMA_TPCC_BIDX_n_88" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_89,EDMA_TPCC_BIDX_n_89" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_90,EDMA_TPCC_BIDX_n_90" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_91,EDMA_TPCC_BIDX_n_91" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_92,EDMA_TPCC_BIDX_n_92" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_93,EDMA_TPCC_BIDX_n_93" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_94,EDMA_TPCC_BIDX_n_94" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_95,EDMA_TPCC_BIDX_n_95" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_96,EDMA_TPCC_BIDX_n_96" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_97,EDMA_TPCC_BIDX_n_97" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_98,EDMA_TPCC_BIDX_n_98" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_99,EDMA_TPCC_BIDX_n_99" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_100,EDMA_TPCC_BIDX_n_100" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_101,EDMA_TPCC_BIDX_n_101" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_102,EDMA_TPCC_BIDX_n_102" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_103,EDMA_TPCC_BIDX_n_103" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_104,EDMA_TPCC_BIDX_n_104" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_105,EDMA_TPCC_BIDX_n_105" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_106,EDMA_TPCC_BIDX_n_106" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_107,EDMA_TPCC_BIDX_n_107" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_108,EDMA_TPCC_BIDX_n_108" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_109,EDMA_TPCC_BIDX_n_109" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_110,EDMA_TPCC_BIDX_n_110" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_111,EDMA_TPCC_BIDX_n_111" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_112,EDMA_TPCC_BIDX_n_112" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_113,EDMA_TPCC_BIDX_n_113" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_114,EDMA_TPCC_BIDX_n_114" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_115,EDMA_TPCC_BIDX_n_115" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_116,EDMA_TPCC_BIDX_n_116" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_117,EDMA_TPCC_BIDX_n_117" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4ED0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_118,EDMA_TPCC_BIDX_n_118" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_119,EDMA_TPCC_BIDX_n_119" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_120,EDMA_TPCC_BIDX_n_120" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_121,EDMA_TPCC_BIDX_n_121" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_122,EDMA_TPCC_BIDX_n_122" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_123,EDMA_TPCC_BIDX_n_123" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_124,EDMA_TPCC_BIDX_n_124" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_125,EDMA_TPCC_BIDX_n_125" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_126,EDMA_TPCC_BIDX_n_126" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_127,EDMA_TPCC_BIDX_n_127" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4014++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4034++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4054++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4074++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4094++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4114++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4134++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4154++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4174++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4194++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4214++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4234++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4254++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4274++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4294++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4314++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4334++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4354++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4374++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4394++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4414++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4434++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4454++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4474++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4494++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4514++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4534++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4554++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4574++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4594++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4614++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4634++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4654++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4674++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4694++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4714++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4734++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4754++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4774++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4794++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4814++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4834++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4854++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4874++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4894++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4914++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4934++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4954++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4974++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4994++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4ED4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4018++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4038++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4058++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4078++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4098++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4118++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4138++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4158++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4178++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4198++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4218++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4238++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4258++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4278++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4298++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4318++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4338++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4358++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4378++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4398++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4418++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4438++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4458++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4478++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4498++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4518++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4538++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4558++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4578++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4598++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4618++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4638++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4658++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4678++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4698++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4718++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4738++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4758++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4778++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4798++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4818++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4838++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4858++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4878++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4898++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4918++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4938++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4958++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4978++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4998++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4ED8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x401C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x403C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x405C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x407C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x409C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x411C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x413C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x415C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x417C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x419C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x421C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x423C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x425C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x427C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x429C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x431C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x433C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x435C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x437C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x439C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x441C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x443C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x445C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x447C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x449C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x451C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x453C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x455C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x457C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x459C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x461C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x463C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x465C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x467C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x469C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x471C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x473C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x475C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x477C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x479C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x481C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x483C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x485C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x487C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x489C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x491C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x493C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x495C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x497C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x499C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ABC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ADC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4AFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_SYSTEM" base ad:0x41500000 width 33. group.byte 0x0++0x3 line.long 0x0 "DSP_SYS_REVISION,DSP_SYS_REVISION" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "DSP_SYS_HWINFO,DSP_SYS_HWINFO" bitfld.long 0x0 0.--3. " NUM ,Instance Number Set by subsystem input. In a multi-DSP system, provides a unique/incrementing values for each DSP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " INFO ,0x0: No configurable options in subsystem." group.byte 0x8++0x3 line.long 0x0 "DSP_SYS_SYSCONFIG,DSP_SYS_SYSCONFIG" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,0x0: FORCE_IDLE This mode is a backup mode intended to be used only if the smart-idle mode is bugged. When in this mode, the IAF acknowledges a request to go idle from the power manager with minimal hardware condition. It is the responsibility of the software to ensure that the IAF are in a correct quiet state before requesting a force-idle transition. Additionally when in this mode, the IAF is not allowed to generate any wakeup request." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,0x0: FORCE_STANDBY This mode is a backup mode intended to be used only if the smart-idle mode is bugged. When in this mode, the SAF asserts with minimal hardware condition the 'STANDBY' status. It is the responsibility of the software to ensure that the SAF is in a correct quiet state before programming this mode. Additionally when in this mode, the SAF is not allowed to generate wakeup request." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reserved. Read returns 0." "0,1,2,3" textline " " bitfld.long 0x0 8. " RESERVED ,Reserved. User must write 0." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved. Read returns 0." group.byte 0xC++0x3 line.long 0x0 "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode." bitfld.long 0x0 0. " C66X_STAT ,C66x Status" "0,1" bitfld.long 0x0 1. " TC0_STAT ,EDMA TC0 Status" "0,1" textline " " bitfld.long 0x0 2. " TC1_STAT ,EDMA TC1 Status" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--5. " OCPI_DISC_STAT ,L3_MAIN (OCP) Initiator(s) Disconnect Status" "0,1,2,3" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses." bitfld.long 0x0 0. " OCPI_DISC ,OCP Initiator (on L3_MAIN) Disconnect request" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators." bitfld.long 0x0 0.--1. " TC0_DBS ,TC0 Default Burst size" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " TC1_DBS ,TC1 Default Burst size." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " TC0_L2PRES ,TC0 L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect." "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " TC1_L2PRES ,TC1 L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " CFG_L2PRES ,DSP CFG L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect" "0,1,2,3" bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " SDMA_L2PRES ,OCP Target port L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect." "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24. " NOPOSTOVERRIDE ,OCP Posted Write vs Non-Posted Write override" "0,1" bitfld.long 0x0 25.--27. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 28.--30. " SDMA_PRI ,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port. Can typically be left at default value. 0x0 is highest, ..., 0x7 is lowest priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x18++0x3 line.long 0x0 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs." bitfld.long 0x0 0. " MMU0_EN ,MMU0 Enable" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " MMU1_EN ,MMU1 Enable" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " MMU0_ABORT ,MMU0 Abort" "0,1" bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12. " MMU1_ABORT ,MMU1 Abort" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol). IRQWAKEEN0 is for interrupt inputs 63 thru 32, and IRQWAKEEN1 is for interrupt inputs 95 thru 64. Internal interrupts cannot cause a wake condition since in this state there is no guaranteed clock and all sub-modules should be in idle state. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding interrupt for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable bit vector for interrupt #n+32" group.byte 0x24++0x3 line.long 0x0 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol). IRQWAKEEN0 is for interrupt inputs 63 thru 32, and IRQWAKEEN1 is for interrupt inputs 95 thru 64. Internal interrupts cannot cause a wake condition since in this state there is no guaranteed clock and all sub-modules should be in idle state. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding interrupt for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable bit vector for interrupt #n+64" group.byte 0x30++0x3 line.long 0x0 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol). DMAWAKEEN0 is for dma event inputs 31 thru 0, and DMAWAKEEN1 is for dma event inputs 63 thru 32. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding dma event for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable for event #n" group.byte 0x34++0x3 line.long 0x0 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol). DMAWAKEEN0 is for dma event inputs 31 thru 0, and DMAWAKEEN1 is for dma event inputs 63 thru 32. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding dma event for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable for event #n+32" group.byte 0x40++0x3 line.long 0x0 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state." hexmask.long 0x0 0.--31. 1. " EVENT ,Output Event for event #n" group.byte 0x44++0x3 line.long 0x0 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state." hexmask.long 0x0 0.--31. 1. " EVENT ,Output Event for event #n" group.byte 0x50++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x0 0.--18. 1. " EVENT ,Settable raw status for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long.tbyte 0x0 0.--18. 1. " EVENT ,Clearable ,Clearable ,Clearable, enabled status for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long.tbyte 0x0 0.--18. 1. " ENABLE ,Enable for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long.tbyte 0x0 0.--18. 1. " ENABLE ,Enable for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long 0x0 0.--31. 1. " EVENT ,Settable raw status for event #n" group.byte 0x64++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long 0x0 0.--31. 1. " EVENT,Clearable ,Clearable ,Clearable, enabled status for event #n" group.byte 0x68++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n" group.byte 0x6C++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n" group.byte 0x70++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long 0x0 0.--31. 1. " EVENT ,Settable raw status for event #n+32" group.byte 0x74++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long 0x0 0.--31. 1. " EVENT,Clearable ,Clearable ,Clearable, enabled status for event #n+32" group.byte 0x78++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n+32" group.byte 0x7C++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n+32" group.byte 0xF8++0x3 line.long 0x0 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus." bitfld.long 0x0 0.--3. " GROUP ,Debug Group output control mux selectN: GN = select output group N ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0xFC++0x3 line.long 0x0 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group." hexmask.long 0x0 0.--31. 1. " VALUE ,Read returns state of hw_dbgout bus" width 0x0B tree.end tree "DSP2_MMU0CFG" base ad:0x41501000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_MMU1CFG" base ad:0x41502000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_FW_L2_NOC_CFG" base ad:0x41503000 width 77. group.byte 0x0++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" hexmask.long.word 0x0 0.--15. 1. " REQINFO_ERRLOG ,Error in reqinfo vector" bitfld.long 0x0 16.--20. " REGION_END_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGION_START_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26. " RESERVED ," "0,1" textline " " bitfld.long 0x0 27. " BLK_BURST_VIOLATION ,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x0 0.--27. 1. " SLVOFS_LOGICAL ,Address generated by the ARM before being translated" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " FW_UPDATE_REQ ,HW set/SW clear" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,HW set/SW clear" "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x88++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,MRM_PERMISSION_REGION_0_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x90++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" bitfld.long 0x0 0.--3. " START_REGION_1 ,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0 0.--3. " END_REGION_1 ,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " END_REGION_1_ENABLE ,End Region 1 enable" "0,1" group.byte 0x98++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x1000++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" hexmask.long.word 0x0 0.--15. 1. " REQINFO_ERRLOG ,Error in reqinfo vector" bitfld.long 0x0 16.--20. " REGION_END_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGION_START_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26. " RESERVED ," "0,1" textline " " bitfld.long 0x0 27. " BLK_BURST_VIOLATION ,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1004++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x0 0.--27. 1. " SLVOFS_LOGICAL ,Address generated by the ARM before being translated" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1040++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " FW_UPDATE_REQ ,HW set/SW clear" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,HW set/SW clear" "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x1088++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x108C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x4000++0x3 line.long 0x0 "DSPNOC_FLAGMUX_ID_COREID,DSPNOC_FLAGMUX_ID_COREID" hexmask.long.byte 0x0 0.--7. 1. " CORETYPEID ,Field identifying the type of IP." hexmask.long.tbyte 0x0 8.--31. 1. " CORECHECKSUM ,Field containing a checksum of the parameters of the IP." group.byte 0x4004++0x3 line.long 0x0 "DSPNOC_FLAGMUX_ID_REVISIONID,DSPNOC_FLAGMUX_ID_REVISIONID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4008++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FAULTEN,DSPNOC_FLAGMUX_FAULTEN" bitfld.long 0x0 0. " FAULTEN ,Global Fault Enable register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x400C++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FAULTSTATUS,DSPNOC_FLAGMUX_FAULTSTATUS" bitfld.long 0x0 0. " FAULTSTATUS ,Global Fault Status register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4010++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FLAGINEN0,DSPNOC_FLAGMUX_FLAGINEN0" bitfld.long 0x0 0. " FLAGINEN0 ,FlagIn Enable register #0" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4014++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FLAGINSTATUS0,DSPNOC_FLAGMUX_FLAGINSTATUS0" bitfld.long 0x0 0. " FLAGINSTATUS0 ,FlagIn Status register #0" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4200++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ID_COREID,DSPNOC_ERRORLOG_ID_COREID" hexmask.long.byte 0x0 0.--7. 1. " CORETYPEID ,Field identifying the type of IP." hexmask.long.tbyte 0x0 8.--31. 1. " CORECHECKSUM ,Field containing a checksum of the parameters of the IP." group.byte 0x4204++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ID_REVISIONID,DSPNOC_ERRORLOG_ID_REVISIONID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4208++0x3 line.long 0x0 "DSPNOC_ERRORLOG_FAULTEN,DSPNOC_ERRORLOG_FAULTEN" bitfld.long 0x0 0. " FAULTEN ,Enable Fault output" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x420C++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRVLD,DSPNOC_ERRORLOG_ERRVLD" bitfld.long 0x0 0. " ERRVLD ,Error logged Valid" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4210++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRCLR,DSPNOC_ERRORLOG_ERRCLR" bitfld.long 0x0 0. " ERRCLR ,Clr ErrVld status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4214++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock, Opcode, Len1, ErrCode values" bitfld.long 0x0 0. " LOCK ,Header: Lock bit value" "0,1" bitfld.long 0x0 1.--4. " OPC ,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. " ERRCODE ,Header: Error Code value" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--27. 1. " LEN1 ,Header: Len1 value" textline " " bitfld.long 0x0 28.--30. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " FORMAT ,Format of ErrLog0 register" "0,1" group.byte 0x4218++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG1,DSPNOC_ERRORLOG_ERRLOG1" hexmask.long.word 0x0 0.--14. 1. " ERRLOG1 ,Header: RouteId lsb value" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x4220++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG3,DSPNOC_ERRORLOG_ERRLOG3" hexmask.long 0x0 0.--30. 1. " ERRLOG3 ,Header: Addr lsb value" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x4228++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG5,DSPNOC_ERRORLOG_ERRLOG5" hexmask.long.tbyte 0x0 0.--21. 1. " ERRLOG5 ,Header: User lsb value" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "DSP2_EDMA_TC0" base ad:0x41505000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_EDMA_TC1" base ad:0x41506000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_EDMA_CC" base ad:0x41510000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPCC_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x0 0.--2. " NUMDMACH ,Number of DMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--6. " NUMQDMACH ,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 8.--10. " NUMINTCH ,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 12.--14. " NUMPAENTRY ,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 16.--18. " NUMTC ,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 20.--21. " NUMREGN ,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 24. " CHMAPEXIST ,Channel Mapping Existence" "0,1" bitfld.long 0x0 25. " MPEXIST ,Memory Protection Existence" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reads return 0's" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xFC++0x3 line.long 0x0 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x0 0. " CLKGDIS ,Auto Clock Gate Disable" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x114++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x118++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x11C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x138++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x13C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x144++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x148++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x14C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x150++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x154++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x158++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x15C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x160++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x164++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x168++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x16C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x170++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x174++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x178++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x17C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x180++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x194++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x198++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x19C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1AC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1BC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1CC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1DC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1EC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x248++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x254++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x260++0x3 line.long 0x0 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." bitfld.long 0x0 0.--2. " E0 ,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x280++0x3 line.long 0x0 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x0 0.--2. " TCNUMQ0 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " TCNUMQ1 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x0 0.--2. " PRIQ0 ,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " PRIQ1 ,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x300++0x3 line.long 0x0 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed #31" "0,1" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E32 ,Event Missed #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed #63" "0,1" group.byte 0x308++0x3 line.long 0x0 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed Clear #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed Clear #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed Clear #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed Clear #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed Clear #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed Clear #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed Clear #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed Clear #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed Clear #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed Clear #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed Clear #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed Clear #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed Clear #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed Clear #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed Clear #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed Clear #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed Clear #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed Clear #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed Clear #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed Clear #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed Clear #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed Clear #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed Clear #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed Clear #31" "0,1" group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E32 ,Event Missed Clear #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed Clear #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed Clear #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed Clear #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed Clear #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed Clear #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed Clear #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed Clear #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed Clear #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed Clear #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed Clear #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed Clear #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed Clear #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed Clear #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed Clear #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed Clear #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed Clear #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed Clear #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed Clear #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed Clear #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed Clear #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed Clear #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed Clear #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed Clear #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed Clear #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed Clear #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed Clear #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed Clear #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed Clear #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed Clear #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed Clear #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed Clear #63" "0,1" group.byte 0x310++0x3 line.long 0x0 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced. If any bit in the register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x314++0x3 line.long 0x0 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x318++0x3 line.long 0x0 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x0 0. " QTHRXCD0 ,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors were previously clear), then an error will be signaled with TPCC error interrupt. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x31C++0x3 line.long 0x0 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x0 0. " QTHRXCD0 ,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT0.WM, QSTAT0.THRXCD,[0] QTHRXCD0 ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM, QSTAT1.THRXCD,[1] QTHRXCD1 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT2.WM, QSTAT2.THRXCD,[2] QTHRXCD2 ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM, QSTAT3.THRXCD,[3] QTHRXCD3 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT4.WM, QSTAT4.THRXCD,[4] QTHRXCD4 ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT5.WM, QSTAT5.THRXCD,[5]QTHRXCD5 ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT6.WM, QSTAT6.THRXCD,[6]QTHRXCD6 ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT7.WM, QSTAT7.THRXCD,[7] QTHRXCD7 ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR. . Write 0x0 have no affect. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x320++0x3 line.long 0x0 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x0 0. " EVAL ,Error Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the/, , or registers. The CPU must also write 0x1 after any error interrupts are serviced in order for subsequent interrupts to be asserted. ." "0,1" bitfld.long 0x0 1. " SET ,Error Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of/, , or . ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x348++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x350++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x358++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x360++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x368++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x370++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x378++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x344++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x35C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x364++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x36C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x374++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x37C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x380++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x388++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x38C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x39C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x400++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x404++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x408++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x40C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x410++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x414++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x418++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x41C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x420++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x424++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x428++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x42C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x430++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x434++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x438++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x43C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x440++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x444++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x448++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x44C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x450++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x454++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x458++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x45C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x460++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x464++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x468++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x46C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x470++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x474++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x478++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x47C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRA,Queue Threshold A, for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q0 ,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q1 ,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q2 ,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q3 ,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x624++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRB,Queue Threshold B, for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q4 ,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q5 ,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q6 ,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q7 ,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x0 0. " EVTACTV ,DMA Event Active" "0,1" bitfld.long 0x0 1. " QEVTACTV ,QDMA Event Active" "0,1" textline " " bitfld.long 0x0 2. " TRACTV ,Transfer Request Active TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0,1" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4. " ACTV ,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals. The ACTV bit must remain high through the life of a:" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,reads return 0's" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " COMPACTV ,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " QUEACTV0 ,Queue 0 Active" "0,1" bitfld.long 0x0 17. " QUEACTV1 ,Queue 1 Active" "0,1" textline " " bitfld.long 0x0 18. " QUEACTV2 ,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0,1" bitfld.long 0x0 19. " QUEACTV3 ,Queue 3 Active" "0,1" textline " " bitfld.long 0x0 20. " QUEACTV4 ,Queue 4 Active" "0,1" bitfld.long 0x0 21. " QUEACTV5 ,Queue 5 Active" "0,1" textline " " bitfld.long 0x0 22. " QUEACTV6 ,Queue 6 Active" "0,1" bitfld.long 0x0 23. " QUEACTV7 ,Queue 7 Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,reads return 0's" group.byte 0x700++0x3 line.long 0x0 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 0.--5. " STRTEVT ,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " TYPE ,AET Event Type" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--13. " ENDINT ,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.tbyte 0x0 14.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " EN ,AET Enable" "0,1" group.byte 0x704++0x3 line.long 0x0 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x0 0. " STAT ,AET Status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x708++0x3 line.long 0x0 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x0 0. " CLR ,AET Clear commandCPU writes 0x0 has no effect. . CPU writes 0x1 to the CLR bit causes the tpcc_aet output signal and[0]STAT register to be cleared. ." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" hexmask.long 0x0 0.--31. 1. " FADDR ,Fault Address: 32-bit read-only status register containing the faulting address when a mMemory protection violation is detected. This register can only be cleared via theEDMA_TPCC_MPFCR." group.byte 0x804++0x3 line.long 0x0 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x0 0. " UXE ,User Execute Error" "0,1" bitfld.long 0x0 1. " UWE ,User Write Error" "0,1" textline " " bitfld.long 0x0 2. " URE ,User Read Error" "0,1" bitfld.long 0x0 3. " SXE ,Supervisor Execute Error" "0,1" textline " " bitfld.long 0x0 4. " SWE ,Supervisor Write Error" "0,1" bitfld.long 0x0 5. " SRE ,Supervisor Read Error" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--12. " FID ,Faulted ID: FID register contains valid info if any of the MP error bits (UXE, UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x808++0x3 line.long 0x0 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x0 0. " MPFCLR ,Fault Clear register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x80C++0x3 line.long 0x0 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0" "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x810++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x814++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x818++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x81C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x820++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x824++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x828++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x82C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x1000++0x3 line.long 0x0 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1004++0x3 line.long 0x0 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1008++0x3 line.long 0x0 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x100C++0x3 line.long 0x0 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1010++0x3 line.long 0x0 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1014++0x3 line.long 0x0 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1018++0x3 line.long 0x0 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x101C++0x3 line.long 0x0 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1020++0x3 line.long 0x0 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1024++0x3 line.long 0x0 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1028++0x3 line.long 0x0 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x102C++0x3 line.long 0x0 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1030++0x3 line.long 0x0 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1034++0x3 line.long 0x0 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1038++0x3 line.long 0x0 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x103C++0x3 line.long 0x0 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1040++0x3 line.long 0x0 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1044++0x3 line.long 0x0 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1050++0x3 line.long 0x0 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1054++0x3 line.long 0x0 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1058++0x3 line.long 0x0 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x105C++0x3 line.long 0x0 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1060++0x3 line.long 0x0 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1064++0x3 line.long 0x0 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1068++0x3 line.long 0x0 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x106C++0x3 line.long 0x0 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. . In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1070++0x3 line.long 0x0 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1074++0x3 line.long 0x0 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" bitfld.long 0x0 1. " SET ,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1080++0x3 line.long 0x0 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1084++0x3 line.long 0x0 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1088++0x3 line.long 0x0 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x108C++0x3 line.long 0x0 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1090++0x3 line.long 0x0 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1094++0x3 line.long 0x0 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2000++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2200++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2400++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2600++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2800++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2004++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2204++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2404++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2604++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2804++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2008++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2208++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2408++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2608++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2808++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x200C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x220C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x240C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x260C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x280C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2010++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2210++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2410++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2610++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2810++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2014++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2214++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2414++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2614++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2814++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2018++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2218++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2418++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2618++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2818++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x201C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x221C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x241C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x261C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x281C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2020++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2220++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2420++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2620++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2820++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2024++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2224++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2424++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2624++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2824++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2028++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2228++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2428++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2628++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2828++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x202C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x222C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x242C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x262C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x282C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2030++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2230++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2430++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2630++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2830++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2034++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2234++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2434++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2634++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2834++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2038++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2238++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2438++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2638++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2838++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x203C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x223C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x243C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x263C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x283C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2040++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2240++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2440++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2640++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2840++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2044++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2244++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2444++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2644++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2844++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2050++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2250++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2450++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2650++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2850++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2054++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2254++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2454++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2654++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2854++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2058++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2258++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2458++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2658++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2858++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x205C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x225C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x245C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x265C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x285C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2060++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2260++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2460++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2660++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2860++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2064++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2264++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2464++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2664++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2864++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2068++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2268++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2468++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2668++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2868++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x206C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x226C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x246C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x266C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x286C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2070++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2270++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2470++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2670++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2870++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2074++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2274++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2474++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2674++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2874++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2278++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2478++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2678++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2878++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2A78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2C78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2E78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2080++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2280++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2480++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2680++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2880++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2084++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2284++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2484++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2684++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2884++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2088++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2288++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2488++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2688++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2888++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x208C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x228C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x248C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x268C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x288C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2090++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2290++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2490++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2690++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2890++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2094++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2294++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2494++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2694++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2894++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2A94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2C94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2E94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x4000++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_0,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4020++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_1,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4040++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_2,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4060++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_3,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4080++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_4,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_5,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_6,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_7,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4100++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_8,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4120++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_9,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4140++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_10,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4160++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_11,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4180++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_12,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_13,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_14,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_15,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4200++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_16,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4220++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_17,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4240++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_18,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4260++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_19,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4280++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_20,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_21,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_22,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_23,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4300++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_24,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4320++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_25,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4340++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_26,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4360++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_27,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4380++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_28,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_29,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_30,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_31,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4400++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_32,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4420++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_33,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4440++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_34,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4460++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_35,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4480++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_36,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_37,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_38,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_39,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4500++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_40,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4520++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_41,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4540++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_42,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4560++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_43,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4580++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_44,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_45,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_46,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_47,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4600++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_48,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4620++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_49,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4640++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_50,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4660++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_51,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4680++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_52,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_53,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_54,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_55,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4700++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_56,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4720++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_57,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4740++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_58,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4760++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_59,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4780++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_60,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_61,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_62,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_63,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4800++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_64,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4820++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_65,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4840++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_66,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4860++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_67,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4880++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_68,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_69,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_70,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_71,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4900++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_72,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4920++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_73,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4940++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_74,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4960++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_75,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4980++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_76,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_77,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_78,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_79,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_80,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_81,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_82,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_83,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_84,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_85,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_86,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_87,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_88,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_89,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_90,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_91,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_92,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_93,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_94,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_95,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_96,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_97,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_98,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_99,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_100,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_101,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_102,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_103,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_104,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_105,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_106,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_107,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_108,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_109,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_110,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_111,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_112,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_113,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_114,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_115,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_116,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_117,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_118,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_119,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_120,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_121,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_122,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_123,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_124,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_125,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_126,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_127,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4004++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_0,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4024++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_1,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4044++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_2,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4064++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_3,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4084++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_4,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_5,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_6,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_7,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4104++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_8,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4124++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_9,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4144++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_10,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4164++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_11,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4184++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_12,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_13,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_14,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_15,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4204++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_16,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4224++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_17,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4244++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_18,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4264++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_19,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4284++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_20,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_21,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_22,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_23,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4304++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_24,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4324++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_25,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4344++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_26,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4364++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_27,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4384++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_28,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_29,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_30,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_31,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4404++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_32,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4424++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_33,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4444++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_34,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4464++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_35,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4484++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_36,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_37,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_38,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_39,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4504++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_40,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4524++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_41,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4544++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_42,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4564++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_43,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4584++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_44,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_45,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_46,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_47,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4604++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_48,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4624++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_49,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4644++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_50,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4664++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_51,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4684++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_52,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_53,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_54,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_55,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4704++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_56,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4724++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_57,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4744++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_58,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4764++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_59,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4784++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_60,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_61,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_62,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_63,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4804++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_64,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4824++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_65,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4844++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_66,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4864++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_67,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4884++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_68,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_69,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_70,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_71,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4904++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_72,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4924++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_73,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4944++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_74,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4964++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_75,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4984++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_76,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_77,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_78,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_79,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_80,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_81,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_82,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_83,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_84,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_85,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_86,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_87,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_88,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_89,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_90,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_91,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_92,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_93,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_94,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_95,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_96,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_97,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_98,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_99,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_100,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_101,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_102,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_103,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_104,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_105,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_106,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_107,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_108,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_109,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_110,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_111,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_112,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_113,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_114,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_115,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_116,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_117,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_118,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_119,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_120,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_121,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_122,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_123,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_124,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_125,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_126,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_127,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4008++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4028++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4048++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4068++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4088++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4108++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4128++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4148++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4168++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4188++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4208++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4228++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4248++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4268++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4288++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4308++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4328++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4348++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4368++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4388++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4408++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4428++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4448++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4468++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4488++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4508++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4528++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4548++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4568++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4588++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4608++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4628++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4648++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4668++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4688++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4708++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4728++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4748++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4768++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4788++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4808++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4828++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4848++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4868++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4888++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4908++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4928++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4948++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4968++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4988++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x400C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_0,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x402C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_1,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x404C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_2,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x406C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_3,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x408C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_4,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_5,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_6,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_7,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x410C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_8,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x412C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_9,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x414C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_10,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x416C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_11,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x418C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_12,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_13,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_14,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_15,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x420C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_16,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x422C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_17,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x424C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_18,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x426C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_19,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x428C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_20,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_21,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_22,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_23,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x430C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_24,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x432C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_25,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x434C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_26,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x436C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_27,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x438C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_28,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_29,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_30,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_31,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x440C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_32,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x442C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_33,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x444C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_34,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x446C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_35,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x448C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_36,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_37,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_38,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_39,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x450C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_40,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x452C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_41,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x454C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_42,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x456C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_43,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x458C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_44,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_45,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_46,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_47,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x460C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_48,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x462C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_49,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x464C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_50,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x466C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_51,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x468C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_52,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_53,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_54,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_55,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x470C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_56,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x472C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_57,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x474C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_58,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x476C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_59,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x478C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_60,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_61,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_62,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_63,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x480C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_64,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x482C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_65,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x484C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_66,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x486C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_67,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x488C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_68,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_69,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_70,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_71,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x490C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_72,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x492C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_73,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x494C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_74,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x496C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_75,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x498C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_76,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_77,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_78,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_79,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_80,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_81,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_82,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_83,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_84,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_85,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ACC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_86,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_87,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_88,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_89,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_90,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_91,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_92,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_93,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_94,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_95,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_96,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_97,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_98,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_99,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_100,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_101,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_102,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_103,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_104,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_105,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_106,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_107,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_108,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_109,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_110,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_111,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_112,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_113,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_114,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_115,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_116,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_117,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ECC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_118,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_119,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_120,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_121,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_122,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_123,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_124,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_125,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_126,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_127,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4010++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_0,EDMA_TPCC_BIDX_n_0" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4030++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_1,EDMA_TPCC_BIDX_n_1" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4050++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_2,EDMA_TPCC_BIDX_n_2" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4070++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_3,EDMA_TPCC_BIDX_n_3" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4090++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_4,EDMA_TPCC_BIDX_n_4" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_5,EDMA_TPCC_BIDX_n_5" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_6,EDMA_TPCC_BIDX_n_6" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_7,EDMA_TPCC_BIDX_n_7" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4110++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_8,EDMA_TPCC_BIDX_n_8" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4130++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_9,EDMA_TPCC_BIDX_n_9" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4150++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_10,EDMA_TPCC_BIDX_n_10" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4170++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_11,EDMA_TPCC_BIDX_n_11" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4190++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_12,EDMA_TPCC_BIDX_n_12" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_13,EDMA_TPCC_BIDX_n_13" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_14,EDMA_TPCC_BIDX_n_14" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_15,EDMA_TPCC_BIDX_n_15" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4210++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_16,EDMA_TPCC_BIDX_n_16" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4230++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_17,EDMA_TPCC_BIDX_n_17" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4250++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_18,EDMA_TPCC_BIDX_n_18" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4270++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_19,EDMA_TPCC_BIDX_n_19" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4290++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_20,EDMA_TPCC_BIDX_n_20" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_21,EDMA_TPCC_BIDX_n_21" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_22,EDMA_TPCC_BIDX_n_22" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_23,EDMA_TPCC_BIDX_n_23" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4310++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_24,EDMA_TPCC_BIDX_n_24" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4330++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_25,EDMA_TPCC_BIDX_n_25" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4350++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_26,EDMA_TPCC_BIDX_n_26" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4370++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_27,EDMA_TPCC_BIDX_n_27" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4390++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_28,EDMA_TPCC_BIDX_n_28" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_29,EDMA_TPCC_BIDX_n_29" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_30,EDMA_TPCC_BIDX_n_30" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_31,EDMA_TPCC_BIDX_n_31" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4410++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_32,EDMA_TPCC_BIDX_n_32" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4430++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_33,EDMA_TPCC_BIDX_n_33" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4450++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_34,EDMA_TPCC_BIDX_n_34" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4470++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_35,EDMA_TPCC_BIDX_n_35" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4490++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_36,EDMA_TPCC_BIDX_n_36" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_37,EDMA_TPCC_BIDX_n_37" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_38,EDMA_TPCC_BIDX_n_38" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_39,EDMA_TPCC_BIDX_n_39" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4510++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_40,EDMA_TPCC_BIDX_n_40" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4530++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_41,EDMA_TPCC_BIDX_n_41" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4550++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_42,EDMA_TPCC_BIDX_n_42" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4570++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_43,EDMA_TPCC_BIDX_n_43" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4590++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_44,EDMA_TPCC_BIDX_n_44" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_45,EDMA_TPCC_BIDX_n_45" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_46,EDMA_TPCC_BIDX_n_46" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_47,EDMA_TPCC_BIDX_n_47" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4610++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_48,EDMA_TPCC_BIDX_n_48" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4630++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_49,EDMA_TPCC_BIDX_n_49" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4650++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_50,EDMA_TPCC_BIDX_n_50" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4670++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_51,EDMA_TPCC_BIDX_n_51" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4690++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_52,EDMA_TPCC_BIDX_n_52" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_53,EDMA_TPCC_BIDX_n_53" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_54,EDMA_TPCC_BIDX_n_54" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_55,EDMA_TPCC_BIDX_n_55" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4710++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_56,EDMA_TPCC_BIDX_n_56" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4730++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_57,EDMA_TPCC_BIDX_n_57" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4750++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_58,EDMA_TPCC_BIDX_n_58" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4770++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_59,EDMA_TPCC_BIDX_n_59" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4790++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_60,EDMA_TPCC_BIDX_n_60" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_61,EDMA_TPCC_BIDX_n_61" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_62,EDMA_TPCC_BIDX_n_62" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_63,EDMA_TPCC_BIDX_n_63" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4810++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_64,EDMA_TPCC_BIDX_n_64" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4830++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_65,EDMA_TPCC_BIDX_n_65" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4850++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_66,EDMA_TPCC_BIDX_n_66" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4870++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_67,EDMA_TPCC_BIDX_n_67" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4890++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_68,EDMA_TPCC_BIDX_n_68" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_69,EDMA_TPCC_BIDX_n_69" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_70,EDMA_TPCC_BIDX_n_70" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_71,EDMA_TPCC_BIDX_n_71" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4910++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_72,EDMA_TPCC_BIDX_n_72" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4930++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_73,EDMA_TPCC_BIDX_n_73" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4950++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_74,EDMA_TPCC_BIDX_n_74" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4970++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_75,EDMA_TPCC_BIDX_n_75" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4990++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_76,EDMA_TPCC_BIDX_n_76" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_77,EDMA_TPCC_BIDX_n_77" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_78,EDMA_TPCC_BIDX_n_78" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_79,EDMA_TPCC_BIDX_n_79" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_80,EDMA_TPCC_BIDX_n_80" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_81,EDMA_TPCC_BIDX_n_81" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_82,EDMA_TPCC_BIDX_n_82" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_83,EDMA_TPCC_BIDX_n_83" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_84,EDMA_TPCC_BIDX_n_84" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_85,EDMA_TPCC_BIDX_n_85" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_86,EDMA_TPCC_BIDX_n_86" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_87,EDMA_TPCC_BIDX_n_87" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_88,EDMA_TPCC_BIDX_n_88" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_89,EDMA_TPCC_BIDX_n_89" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_90,EDMA_TPCC_BIDX_n_90" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_91,EDMA_TPCC_BIDX_n_91" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_92,EDMA_TPCC_BIDX_n_92" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_93,EDMA_TPCC_BIDX_n_93" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_94,EDMA_TPCC_BIDX_n_94" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_95,EDMA_TPCC_BIDX_n_95" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_96,EDMA_TPCC_BIDX_n_96" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_97,EDMA_TPCC_BIDX_n_97" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_98,EDMA_TPCC_BIDX_n_98" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_99,EDMA_TPCC_BIDX_n_99" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_100,EDMA_TPCC_BIDX_n_100" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_101,EDMA_TPCC_BIDX_n_101" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_102,EDMA_TPCC_BIDX_n_102" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_103,EDMA_TPCC_BIDX_n_103" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_104,EDMA_TPCC_BIDX_n_104" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_105,EDMA_TPCC_BIDX_n_105" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_106,EDMA_TPCC_BIDX_n_106" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_107,EDMA_TPCC_BIDX_n_107" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_108,EDMA_TPCC_BIDX_n_108" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_109,EDMA_TPCC_BIDX_n_109" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_110,EDMA_TPCC_BIDX_n_110" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_111,EDMA_TPCC_BIDX_n_111" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_112,EDMA_TPCC_BIDX_n_112" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_113,EDMA_TPCC_BIDX_n_113" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_114,EDMA_TPCC_BIDX_n_114" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_115,EDMA_TPCC_BIDX_n_115" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_116,EDMA_TPCC_BIDX_n_116" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_117,EDMA_TPCC_BIDX_n_117" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4ED0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_118,EDMA_TPCC_BIDX_n_118" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_119,EDMA_TPCC_BIDX_n_119" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_120,EDMA_TPCC_BIDX_n_120" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_121,EDMA_TPCC_BIDX_n_121" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_122,EDMA_TPCC_BIDX_n_122" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_123,EDMA_TPCC_BIDX_n_123" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_124,EDMA_TPCC_BIDX_n_124" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_125,EDMA_TPCC_BIDX_n_125" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_126,EDMA_TPCC_BIDX_n_126" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_127,EDMA_TPCC_BIDX_n_127" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4014++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4034++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4054++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4074++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4094++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4114++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4134++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4154++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4174++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4194++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4214++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4234++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4254++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4274++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4294++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4314++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4334++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4354++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4374++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4394++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4414++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4434++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4454++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4474++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4494++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4514++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4534++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4554++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4574++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4594++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4614++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4634++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4654++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4674++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4694++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4714++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4734++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4754++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4774++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4794++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4814++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4834++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4854++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4874++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4894++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4914++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4934++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4954++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4974++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4994++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4ED4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4018++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4038++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4058++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4078++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4098++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4118++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4138++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4158++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4178++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4198++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4218++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4238++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4258++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4278++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4298++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4318++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4338++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4358++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4378++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4398++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4418++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4438++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4458++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4478++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4498++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4518++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4538++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4558++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4578++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4598++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4618++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4638++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4658++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4678++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4698++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4718++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4738++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4758++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4778++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4798++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4818++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4838++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4858++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4878++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4898++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4918++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4938++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4958++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4978++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4998++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4ED8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x401C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x403C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x405C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x407C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x409C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x411C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x413C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x415C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x417C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x419C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x421C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x423C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x425C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x427C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x429C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x431C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x433C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x435C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x437C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x439C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x441C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x443C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x445C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x447C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x449C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x451C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x453C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x455C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x457C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x459C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x461C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x463C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x465C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x467C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x469C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x471C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x473C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x475C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x477C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x479C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x481C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x483C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x485C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x487C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x489C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x491C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x493C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x495C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x497C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x499C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ABC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ADC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4AFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CM_CORE_AON__MPU" base ad:0x4A005300 width 28. group.byte 0x0++0x3 line.long 0x0 "CM_MPU_CLKSTCTRL,This register enables the MPU domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the MPU clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_MPU_GCLK ,This field indicates the state of the MPU_DPLL_CLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_MPU_STATICDEP,This register controls the static domain depedencies from MPU domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0. " IPU2_STATDEP ,Static dependency towards IPU2 clock domain" "0,1" bitfld.long 0x0 1. " DSP1_STATDEP ,Static dependency towards DSP1 clock domain" "0,1" textline " " bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN clock domain" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain" "0,1" textline " " bitfld.long 0x0 8. " DSS_STATDEP ,Static dependency towards DSS clock domain" "0,1" bitfld.long 0x0 9. " CAM_STATDEP ,Static dependency towards CAM clock domain" "0,1" textline " " bitfld.long 0x0 10. " GPU_STATDEP ,Static dependency towards GPU clock domain" "0,1" bitfld.long 0x0 11. " SDMA_STATDEP ,Static dependency towards SDMA clock domain" "0,1" textline " " bitfld.long 0x0 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain" "0,1" bitfld.long 0x0 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain" "0,1" textline " " bitfld.long 0x0 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain" "0,1" bitfld.long 0x0 15. " WKUPAON_STATDEP ,Static dependency towards WKUPAON clock domain" "0,1" textline " " bitfld.long 0x0 16. " COREAON_STATDEP ,Static dependency towards COREAON clock domain" "0,1" bitfld.long 0x0 17. " CUSTEFUSE_STATDEP ,Static dependency towards CUSTEFUSE clock domain" "0,1" textline " " bitfld.long 0x0 18. " DSP2_STATDEP ,Static dependency towards DSP2 clock domain" "0,1" bitfld.long 0x0 19. " EVE1_STATDEP ,Static dependency towards EVE1 clock domain" "0,1" textline " " bitfld.long 0x0 20. " EVE2_STATDEP ,Static dependency towards EVE2 clock domain" "0,1" bitfld.long 0x0 21. " EVE3_STATDEP ,Static dependency towards EVE3 clock domain" "0,1" textline " " bitfld.long 0x0 22. " EVE4_STATDEP ,Static dependency towards EVE4 clock domain" "0,1" bitfld.long 0x0 23. " IPU1_STATDEP ,Static dependency towards IPU1 clock domain" "0,1" textline " " bitfld.long 0x0 24. " IPU_STATDEP ,Static dependency towards IPU clock domain" "0,1" bitfld.long 0x0 25. " GMAC_STATDEP ,Static dependency towards GMAC clock domain" "0,1" textline " " bitfld.long 0x0 26. " L4PER2_STATDEP ,Static dependency towards L4PER2 clock domain" "0,1" bitfld.long 0x0 27. " L4PER3_STATDEP ,Static dependency towards L4PER3 clock domain" "0,1" textline " " bitfld.long 0x0 28. " VPE_STATDEP ,Static dependency towards VPE clock domain" "0,1" bitfld.long 0x0 29. " PCIE_STATDEP ,Static dependency towards PCIE clock domain" "0,1" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x8++0x3 line.long 0x0 "CM_MPU_DYNAMICDEP,This register controls the dynamic domain depedencies from MPU domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " EMIF_DYNDEP ,Dynamic dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" hexmask.long.tbyte 0x0 6.--23. 1. " RESERVED ," textline " " bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x20++0x3 line.long 0x0 "CM_MPU_MPU_CLKCTRL,This register manages the MPU clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24.--25. " CLKSEL_EMIF_DIV_MODE ,Selects the ratio for MPU - L3 async bridge versus MPU DPLL clock" "0,1,2,3" textline " " bitfld.long 0x0 26. " CLKSEL_ABE_DIV_MODE ,Selects the ratio for MPU - ABE async bridge versus MPU DPLL clock" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x28++0x3 line.long 0x0 "CM_MPU_MPU_MPU_DBG_CLKCTRL,This register manages the MPU_MPU_DBG clocks. [warm reset insensitive]" bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," width 0x0B tree.end tree "DSP2_PRM" base ad:0x4AE07B00 width 22. group.byte 0x0++0x3 line.long 0x0 "PM_DSP2_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " DSP2_L1_ONSTATE ,DSP_L1 state when domain is ON." "0,1,2,3" bitfld.long 0x0 18.--19. " DSP2_L2_ONSTATE ,DSP_L2 state when domain is ON." "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " DSP2_EDMA_ONSTATE ,DSP_EDMA state when domain is ON." "0,1,2,3" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_DSP2_PWRSTST,This register provides a status on the DSP domain current power state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " DSP2_L1_STATEST ,DSP_L1 memory state status" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " DSP2_L2_STATEST ,DSP_L2 memory state status" "0,1,2,3" bitfld.long 0x0 8.--9. " DSP2_EDMA_STATEST ,RSERVED" "0,1,2,3" textline " " hexmask.long.word 0x0 10.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_DSP2_RSTCTRL,This register controls the release of the DSP sub-system resets." bitfld.long 0x0 0. " RST_DSP2_LRST ,DSP Local reset control" "0,1" bitfld.long 0x0 1. " RST_DSP2 ,DSP SW reset control" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "RM_DSP2_RSTST,This register logs the different reset sources of the DSP domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RST_DSP2_LRST ,DSP Local SW reset" "0,1" bitfld.long 0x0 1. " RST_DSP2 ,DSP SW reset status" "0,1" textline " " bitfld.long 0x0 2. " RST_DSP2_EMU ,DSP domain has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module" "0,1" bitfld.long 0x0 3. " RST_DSP2_EMU_REQ ,DSP processor has been reset due to DSP emulation reset request driven from DSP-SS" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_DSP2_DSP2_CONTEXT,This register contains dedicated DSP context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSP_SYS_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_DSP_L1 ,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source." "0,1" bitfld.long 0x0 9. " LOSTMEM_DSP_L2 ,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " bitfld.long 0x0 10. " LOSTMEM_DSP_EDMA ,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," width 0x0B tree.end tree "WKUPAON_PRM" base ad:0x4AE07700 width 32. group.byte 0x24++0x3 line.long 0x0 "RM_WKUPAON_L4_WKUP_CONTEXT,This register contains dedicated L4_WKUP context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUPAON_RST signal)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PM_WKUPAON_WD_TIMER2_WKDEP,This register controls wakeup dependency based on WD_TIMER2 service requests." bitfld.long 0x0 0. " WKUPDEP_WD_TIMER2_MPU ,Wakeup dependency from WD_TIMER2 module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_WD_TIMER2_IPU2 ,Wakeup dependency from WD_TIMER2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_WD_TIMER2_DSP1 ,Wakeup dependency from WD_TIMER2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_WD_TIMER2_IPU1 ,Wakeup dependency from WD_TIMER2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_WD_TIMER2_DSP2 ,Wakeup dependency from WD_TIMER2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_WD_TIMER2_EVE1 ,Wakeup dependency from WD_TIMER2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_WD_TIMER2_EVE2 ,Wakeup dependency from WD_TIMER2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_WD_TIMER2_EVE3 ,Wakeup dependency from WD_TIMER2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_WD_TIMER2_EVE4 ,Wakeup dependency from WD_TIMER2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "RM_WKUPAON_WD_TIMER2_CONTEXT,This register contains dedicated WD_TIMER2 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUPAON_RST signal)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PM_WKUPAON_GPIO1_WKDEP,This register controls wakeup dependency based on GPIO1 service requests." bitfld.long 0x0 0. " WKUPDEP_GPIO1_IRQ1_MPU ,Wakeup dependency from GPIO1 module (SWakeup signal for POROCPSINTERRUPT1 ) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_GPIO1_IRQ1_IPU2 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_GPIO1_IRQ1_DSP1 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_GPIO1_IRQ1_IPU1 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_GPIO1_IRQ1_DSP2 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_GPIO1_IRQ1_EVE1 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_GPIO1_IRQ1_EVE2 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_GPIO1_IRQ1_EVE3 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_GPIO1_IRQ1_EVE4 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_GPIO1_IRQ2_MPU ,Wakeup dependency from GPIO1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_GPIO1_IRQ2_IPU2 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_GPIO1_IRQ2_DSP1 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " RESERVED ," "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_GPIO1_IRQ2_IPU1 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_GPIO1_IRQ2_DSP2 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_GPIO1_IRQ2_EVE1 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_GPIO1_IRQ2_EVE2 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_GPIO1_IRQ2_EVE3 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_GPIO1_IRQ2_EVE4 ,Wakeup dependency from GPIO1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "RM_WKUPAON_GPIO1_CONTEXT,This register contains dedicated GPIO1 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUPAON_RST signal)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PM_WKUPAON_TIMER1_WKDEP,This register controls wakeup dependency based on TIMER1 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER1_MPU ,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER1_IPU2 ,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER1_DSP1 ,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER1_IPU1 ,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER1_DSP2 ,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER1_EVE1 ,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER1_EVE2 ,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER1_EVE3 ,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER1_EVE4 ,Wakeup dependency from TIMER1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "RM_WKUPAON_TIMER1_CONTEXT,This register contains dedicated TIMER1 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUPAON_RST signal)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "PM_WKUPAON_TIMER12_WKDEP,This register controls wakeup dependency based on TIMER12 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER12_MPU ,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER12_IPU2 ,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER12_DSP1 ,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER12_IPU1 ,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER12_DSP2 ,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER12_EVE1 ,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER12_EVE2 ,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER12_EVE3 ,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER12_EVE4 ,Wakeup dependency from TIMER12 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "RM_WKUPAON_TIMER12_CONTEXT,This register contains dedicated TIMER12 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUPAON_RST signal)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "RM_WKUPAON_COUNTER_32K_CONTEXT,This register contains dedicated COUNTER_32K context statuses. This bit-field is only sensitive to the external power-on reset (SYS_PWRON_RST reset line)" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUPAON_SYS_PWRON_RST signal)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "PM_WKUPAON_KBD_WKDEP,This register controls wakeup dependency based on KBD service requests." bitfld.long 0x0 0. " WKUPDEP_KBD_MPU ,Wakeup dependency from KBD module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_KBD_IPU2 ,Wakeup dependency from KBD module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_KBD_DSP1 ,Wakeup dependency from KBD module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_KBD_IPU1 ,Wakeup dependency from KBD module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_KBD_DSP2 ,Wakeup dependency from KBD module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_KBD_EVE1 ,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_KBD_EVE2 ,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPAON_KBD_EVE3 ,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPAON_KBD_EVE4 ,Wakeup dependency from KBD module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "RM_WKUPAON_KBD_CONTEXT,This register contains dedicated KBD context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUPAON_RST signal)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PM_WKUPAON_UART10_WKDEP,This register controls wakeup dependency based on UART10 service requests." bitfld.long 0x0 0. " WKUPDEP_UART10_MPU ,Wakeup dependency from UART10 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_UART10_IPU2 ,Wakeup dependency from UART10 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_UART10_DSP1 ,Wakeup dependency from UART10 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_UART10_SDMA ,Wakeup dependency from UART10 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_UART10_IPU1 ,Wakeup dependency from UART10 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_UART10_DSP2 ,Wakeup dependency from UART10 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_UART10_EVE1 ,Wakeup dependency from UART10 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_UART10_EVE2 ,Wakeup dependency from UART10 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_UART10_EVE3 ,Wakeup dependency from UART10 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_UART10_EVE4 ,Wakeup dependency from UART10 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "RM_WKUPAON_UART10_CONTEXT,This register contains dedicated UART10 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUPAON_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_RETAINED_BANK ,Specify if memory-based context in UART memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "PM_WKUPAON_DCAN1_WKDEP,This register controls wakeup dependency based on DCAN1 service requests." bitfld.long 0x0 0. " WKUPDEP_DCAN1_MPU ,Wakeup dependency from DCAN1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_DCAN1_IPU2 ,Wakeup dependency from DCAN1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_DCAN1_DSP1 ,Wakeup dependency from DCAN1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_DCAN1_SDMA ,Wakeup dependency from DCAN1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_DCAN1_IPU1 ,Wakeup dependency from DCAN1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_DCAN1_DSP2 ,Wakeup dependency from DCAN1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_DCAN1_EVE1 ,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_DCAN1_EVE2 ,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_DCAN1_EVE3 ,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_DCAN1_EVE4 ,Wakeup dependency from DCAN1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "RM_WKUPAON_DCAN1_CONTEXT,This register contains dedicated DCAN1 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of WKUPAON_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_DCAN_MEM ,Specify if memory-based context in DCAN memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "OCP_SOCKET_PRM" base ad:0x4AE06000 width 26. group.byte 0x0++0x3 line.long 0x0 "REVISION_PRM,This register contains the IP revision code for the PRM part of the PRCM" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "PRM_IRQSTATUS_MPU,This register provides status on MPU interrupt events. Any event is logged independently of the corresponding IRQENABLE value. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared." bitfld.long 0x0 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_ST ,MPU DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_ST ,GMAC DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_ST ,GPU DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_ST ,DDR DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 8. " TRANSITION_ST ,Software supervised transition completed event interrupt status (any domain). Asserted upon completion of any clock domain force wakeup transition or upon completion of any power domain sleep transition with at least one enclosed clock domain configured in forced-sleep." "0,1" bitfld.long 0x0 9. " IO_ST ,IO pad event interrupt status." "0,1" textline " " bitfld.long 0x0 10. " RESERVED ," "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_ST ,DSP DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_ST ,EVE DPLL recalibration interrupt status." "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_ST ,GPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_ST ,DSPEVE ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_ST ,IVA ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "PRM_IRQSTATUS_MPU_2,This register provides status on MPU interrupt events. Any event is logged independently of the corresponding IRQENABLE value. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared." hexmask.long.byte 0x0 0.--6. 1. " RESERVED ," bitfld.long 0x0 7. " ABB_MPU_DONE_ST ,MPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware inPRM_ABBLDO_MPU_CTRL register). It is cleared by SW." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRM_IRQENABLE_MPU,This register is used to enable or disable MPU interrupt activation." bitfld.long 0x0 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_EN ,MPU DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_EN ,GMAC DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_EN ,GPU DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_EN ,DDR DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 8. " TRANSITION_EN ,Software supervised transition completed event interrupt enable (any domain)" "0,1" bitfld.long 0x0 9. " IO_EN ,IO pad event interrupt enable" "0,1" textline " " bitfld.long 0x0 10. " DPLL_DSP_RECAL_EN ,DSP DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 11. " DPLL_EVE_RECAL_EN ,EVE DPLL recalibration interrupt enable" "0,1" textline " " hexmask.long.tbyte 0x0 12.--28. 1. " RESERVED ," bitfld.long 0x0 29. " ABB_GPU_DONE_EN ,GPU ABB mode change done enable" "0,1" textline " " bitfld.long 0x0 30. " ABB_DSPEVE_DONE_EN ,DSPEVE ABB mode change done enable" "0,1" bitfld.long 0x0 31. " ABB_IVA_DONE_EN ,IVA ABB mode change done enable" "0,1" group.byte 0x1C++0x3 line.long 0x0 "PRM_IRQENABLE_MPU_2,This register is used to enable or disable MPU interrupt activation." hexmask.long.byte 0x0 0.--6. 1. " RESERVED ," bitfld.long 0x0 7. " ABB_MPU_DONE_EN ,MPU ABB mode change done enable" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRM_IRQSTATUS_IPU2,This register provides status on IPU2 interrupt events. Any event is logged independently of the corresponding IRQENABLE value. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared." bitfld.long 0x0 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_ST ,MPU DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_ST ,GMAC DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_ST ,GPU DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_ST ,DDR DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 8. " TRANSITION_ST ,Software supervised transition completed event interrupt status (any domain). Asserted upon completion of any clock domain force wakeup transition or upon completion of any power domain sleep transition with at least one enclosed clock domain configured in forced-sleep." "0,1" bitfld.long 0x0 9. " IO_ST ,IO pad event interrupt status." "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_ST ,IPU domain software supervised wakeup transition completed event interrupt status." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_ST ,DSP DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_ST ,EVE DPLL recalibration interrupt status." "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_ST ,GPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_ST ,DSPEVE ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_ST ,IVA ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_ST ,MPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" group.byte 0x28++0x3 line.long 0x0 "PRM_IRQENABLE_IPU2,This register is used to enable or disable IPU2 interrupt activation." bitfld.long 0x0 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_EN ,MPU DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_EN ,GMAC DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_EN ,GPU DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_EN ,DDR DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 8. " TRANSITION_EN ,Software supervised transition completed event interrupt enable (any domain)" "0,1" bitfld.long 0x0 9. " IO_EN ,IO pad event interrupt enable" "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_EN ,IPU domain software supervised wakeup transition completed event interrupt enable." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_EN ,DSP DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_EN ,EVE DPLL recalibration interrupt enable" "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_EN ,GPU ABB mode change done enable" "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_EN ,DSPEVE ABB mode change done enable" "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_EN ,IVA ABB mode change done enable" "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_EN ,MPU ABB mode change done enable" "0,1" group.byte 0x30++0x3 line.long 0x0 "PRM_IRQSTATUS_DSP1,This register provides status on DSP1 interrupt events. Any event is logged independently of the corresponding IRQENABLE value. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared." bitfld.long 0x0 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_ST ,MPU DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_ST ,GMAC DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_ST ,GPU DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_ST ,DDR DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_ST ,IO pad event interrupt status." "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_ST ,IPU domain software supervised wakeup transition completed event interrupt status." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_ST ,DSP DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_ST ,EVE DPLL recalibration interrupt status." "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_ST ,GPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_ST ,DSPEVE ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_ST ,IVA ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_ST ,MPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" group.byte 0x38++0x3 line.long 0x0 "PRM_IRQENABLE_DSP1,This register is used to enable or disable DSP1 interrupt activation." bitfld.long 0x0 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_EN ,MPU DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_EN ,GMAC DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_EN ,GPU DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_EN ,DDR DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_EN ,IO pad event interrupt enable" "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_EN ,IPU domain software supervised wakeup transition completed event interrupt enable." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_EN ,DSP DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_EN ,EVE DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 13. " DPLL_USB_RECAL_EN ,USB DPLL recalibration interrupt enable" "0,1" textline " " hexmask.long.word 0x0 14.--27. 1. " RESERVED ," bitfld.long 0x0 28. " ABB_GPU_DONE_EN ,GPU ABB mode change done enable" "0,1" textline " " bitfld.long 0x0 29. " ABB_DSPEVE_DONE_EN ,DSPEVE ABB mode change done enable" "0,1" bitfld.long 0x0 30. " ABB_IVA_DONE_EN ,IVA ABB mode change done enable" "0,1" textline " " bitfld.long 0x0 31. " ABB_MPU_DONE_EN ,MPU ABB mode change done enable" "0,1" group.byte 0x40++0x3 line.long 0x0 "CM_PRM_PROFILING_CLKCTRL,This register manages the PRM_PROFILING clock. [warm reset insensitive]" bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "PRM_IRQENABLE_DSP2,This register is used to enable or disable DSP2 interrupt activation." bitfld.long 0x0 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_EN ,MPU DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_EN ,GMAC DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_EN ,GPU DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_EN ,DDR DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_EN ,IO pad event interrupt enable" "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_EN ,IPU domain software supervised wakeup transition completed event interrupt enable." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_EN ,DSP DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_EN ,EVE DPLL recalibration interrupt enable" "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_EN ,GPU ABB mode change done enable" "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_EN ,DSPEVE ABB mode change done enable" "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_EN ,IVA ABB mode change done enable" "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_EN ,MPU ABB mode change done enable" "0,1" group.byte 0x48++0x3 line.long 0x0 "PRM_IRQENABLE_EVE1,This register is used to enable or disable EVE1 interrupt activation." bitfld.long 0x0 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_EN ,MPU DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_EN ,GMAC DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_EN ,GPU DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_EN ,DDR DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_EN ,IO pad event interrupt enable" "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_EN ,IPU domain software supervised wakeup transition completed event interrupt enable." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_EN ,DSP DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_EN ,EVE DPLL recalibration interrupt enable" "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_EN ,GPU ABB mode change done enable" "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_EN ,DSPEVE ABB mode change done enable" "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_EN ,IVA ABB mode change done enable" "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_EN ,MPU ABB mode change done enable" "0,1" group.byte 0x4C++0x3 line.long 0x0 "PRM_IRQENABLE_EVE2,This register is used to enable or disable EVE2 interrupt activation." bitfld.long 0x0 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_EN ,MPU DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_EN ,GMAC DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_EN ,GPU DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_EN ,DDR DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_EN ,IO pad event interrupt enable" "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_EN ,IPU domain software supervised wakeup transition completed event interrupt enable." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_EN ,DSP DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_EN ,EVE DPLL recalibration interrupt enable" "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_EN ,GPU ABB mode change done enable" "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_EN ,DSPEVE ABB mode change done enable" "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_EN ,IVA ABB mode change done enable" "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_EN ,MPU ABB mode change done enable" "0,1" group.byte 0x50++0x3 line.long 0x0 "PRM_IRQENABLE_EVE3,This register is used to enable or disable EVE3 interrupt activation." bitfld.long 0x0 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_EN ,MPU DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_EN ,GMAC DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_EN ,GPU DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_EN ,DDR DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_EN ,IO pad event interrupt enable" "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_EN ,IPU domain software supervised wakeup transition completed event interrupt enable." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_EN ,DSP DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_EN ,EVE DPLL recalibration interrupt enable" "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_EN ,GPU ABB mode change done enable" "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_EN ,DSPEVE ABB mode change done enable" "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_EN ,IVA ABB mode change done enable" "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_EN ,MPU ABB mode change done enable" "0,1" group.byte 0x54++0x3 line.long 0x0 "PRM_IRQENABLE_EVE4,This register is used to enable or disable EVE4 interrupt activation upon." bitfld.long 0x0 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_EN ,MPU DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_EN ,GMAC DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_EN ,GPU DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_EN ,DDR DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_EN ,IO pad event interrupt enable" "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_EN ,IPU domain software supervised wakeup transition completed event interrupt enable." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_EN ,DSP DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_EN ,EVE DPLL recalibration interrupt enable" "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_EN ,GPU ABB mode change done enable" "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_EN ,DSPEVE ABB mode change done enable" "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_EN ,IVA ABB mode change done enable" "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_EN ,MPU ABB mode change done enable" "0,1" group.byte 0x58++0x3 line.long 0x0 "PRM_IRQENABLE_IPU1,This register is used to enable or disable IPU1 interrupt activation." bitfld.long 0x0 0. " DPLL_CORE_RECAL_EN ,CORE DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_EN ,MPU DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_EN ,IVA DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_EN ,PER DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_EN ,ABEDPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_EN ,GMAC DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_EN ,GPU DPLL recalibration interrupt enable" "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_EN ,DDR DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 8. " TRANSITION_EN ,Software supervised transition completed event interrupt enable (any domain)" "0,1" bitfld.long 0x0 9. " IO_EN ,IO pad event interrupt enable" "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_EN ,IPU domain software supervised wakeup transition completed event interrupt enable." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_EN ,DSP DPLL recalibration interrupt enable" "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_EN ,EVE DPLL recalibration interrupt enable" "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_EN ,GPU ABB mode change done enable" "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_EN ,DSPEVE ABB mode change done enable" "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_EN ,IVA ABB mode change done enable" "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_EN ,MPU ABB mode change done enable" "0,1" group.byte 0x5C++0x3 line.long 0x0 "PRM_IRQSTATUS_DSP2,This register provides status on DSP interrupt events. Any event is logged independently of the corresponding IRQENABLE value. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared." bitfld.long 0x0 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_ST ,MPU DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_ST ,GMAC DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_ST ,GPU DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_ST ,DDR DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_ST ,IO pad event interrupt status." "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_ST ,IPU domain software supervised wakeup transition completed event interrupt status." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_ST ,DSP DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_ST ,EVE DPLL recalibration interrupt status." "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_ST ,GPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_ST ,DSPEVE ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_ST ,IVA ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_ST ,MPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" group.byte 0x60++0x3 line.long 0x0 "PRM_IRQSTATUS_EVE1,This register provides status on EVE interrupt events. Any event is logged independently of the corresponding IRQENABLE value. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared." bitfld.long 0x0 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_ST ,MPU DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_ST ,GMAC DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_ST ,GPU DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_ST ,DDR DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_ST ,IO pad event interrupt status." "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_ST ,IPU domain software supervised wakeup transition completed event interrupt status." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_ST ,DSP DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_ST ,EVE DPLL recalibration interrupt status." "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_ST ,GPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_ST ,DSPEVE ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_ST ,IVA ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_ST ,MPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" group.byte 0x64++0x3 line.long 0x0 "PRM_IRQSTATUS_EVE2,This register provides status on EVE interrupt events. Any event is logged independently of the corresponding IRQENABLE value. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared." bitfld.long 0x0 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_ST ,MPU DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_ST ,GMAC DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_ST ,GPU DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_ST ,DDR DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_ST ,IO pad event interrupt status." "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_ST ,IPU domain software supervised wakeup transition completed event interrupt status." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_ST ,DSP DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_ST ,EVE DPLL recalibration interrupt status." "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_ST ,GPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_ST ,DSPEVE ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_ST ,IVA ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_ST ,MPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" group.byte 0x68++0x3 line.long 0x0 "PRM_IRQSTATUS_EVE3,This register provides status on EVE interrupt events. Any event is logged independently of the corresponding IRQENABLE value. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared." bitfld.long 0x0 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_ST ,MPU DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_ST ,GMAC DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_ST ,GPU DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_ST ,DDR DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_ST ,IO pad event interrupt status." "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_ST ,IPU domain software supervised wakeup transition completed event interrupt status." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_ST ,DSP DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_ST ,EVE DPLL recalibration interrupt status." "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_ST ,GPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_ST ,DSPEVE ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_ST ,IVA ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_ST ,MPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" group.byte 0x6C++0x3 line.long 0x0 "PRM_IRQSTATUS_EVE4,This register provides status on EVE interrupt events. Any event is logged independently of the corresponding IRQENABLE value. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared." bitfld.long 0x0 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_ST ,MPU DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_ST ,GMAC DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_ST ,GPU DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_ST ,DDR DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " IO_ST ,IO pad event interrupt status." "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_ST ,IPU domain software supervised wakeup transition completed event interrupt status." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_ST ,DSP DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_ST ,EVE DPLL recalibration interrupt status." "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_ST ,GPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_ST ,DSPEVE ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_ST ,IVA ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_ST ,MPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" group.byte 0x70++0x3 line.long 0x0 "PRM_IRQSTATUS_IPU1,This register provides status on IPU1 interrupt events. Any event is logged independently of the corresponding IRQENABLE value. SW is required to clear a set bit by writing a '1' into the bit-position to be cleared." bitfld.long 0x0 0. " DPLL_CORE_RECAL_ST ,CORE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 1. " DPLL_MPU_RECAL_ST ,MPU DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 2. " DPLL_IVA_RECAL_ST ,IVA DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 3. " DPLL_PER_RECAL_ST ,PER DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 4. " DPLL_ABE_RECAL_ST ,ABE DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 5. " DPLL_GMAC_RECAL_ST ,GMAC DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 6. " DPLL_GPU_RECAL_ST ,GPU DPLL recalibration interrupt status." "0,1" bitfld.long 0x0 7. " DPLL_DDR_RECAL_ST ,DDR DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 8. " TRANSITION_ST ,Software supervised transition completed event interrupt status (any domain). Asserted upon completion of any clock domain force wakeup transition or upon completion of any power domain sleep transition with at least one enclosed clock domain configured in forced-sleep." "0,1" bitfld.long 0x0 9. " IO_ST ,IO pad event interrupt status." "0,1" textline " " bitfld.long 0x0 10. " FORCEWKUP_ST ,IPU domain software supervised wakeup transition completed event interrupt status." "0,1" bitfld.long 0x0 11. " DPLL_DSP_RECAL_ST ,DSP DPLL recalibration interrupt status." "0,1" textline " " bitfld.long 0x0 12. " DPLL_EVE_RECAL_ST ,EVE DPLL recalibration interrupt status." "0,1" hexmask.long.word 0x0 13.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ABB_GPU_DONE_ST ,GPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 29. " ABB_DSPEVE_DONE_ST ,DSPEVE ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" textline " " bitfld.long 0x0 30. " ABB_IVA_DONE_ST ,IVA ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" bitfld.long 0x0 31. " ABB_MPU_DONE_ST ,MPU ABB mode change completion status. This status is set for both automatic transition upon a voltage transition, and OPP change (when OPP_CHANGE bit is cleared by hardware in PRM_ABBLDO_MM_CTRL register). It is cleared by SW." "0,1" group.byte 0xE4++0x3 line.long 0x0 "PRM_DEBUG_CFG1,This register is used to configure the PRM's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. The signals included in each block are specified in the PRCM integration specification. [warm reset insensitive]" hexmask.long.word 0x0 0.--8. 1. " SEL1 ,Internal signal block select for debug word byte-1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xE8++0x3 line.long 0x0 "PRM_DEBUG_CFG2,This register is used to configure the PRM's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. The signals included in each block are specified in the PRCM integration specification. [warm reset insensitive]" hexmask.long.word 0x0 0.--8. 1. " SEL2 ,Internal signal block select for debug word byte-2" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xEC++0x3 line.long 0x0 "PRM_DEBUG_CFG3,This register is used to configure the PRM's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. The signals included in each block are specified in the PRCM integration specification. [warm reset insensitive]" hexmask.long.word 0x0 0.--8. 1. " SEL3 ,Internal signal block select for debug word byte-3" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "PRM_DEBUG_CFG,This register is used to configure the PRM's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. The signals included in each block are specified in the PRCM integration specification. [warm reset insensitive]" hexmask.long.word 0x0 0.--8. 1. " SEL0 ,Internal signal block select for debug word byte-0" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xF4++0x3 line.long 0x0 "PRM_DEBUG_OUT,This register is used to monitor the PRM's 32 bit HEDEBUG BUS [warm reset insensitive]" hexmask.long 0x0 0.--31. 1. " OUTPUT ,HW DEBUG OUTPUT" width 0x0B tree.end tree "IPU_PRM" base ad:0x4AE06500 width 22. group.byte 0x0++0x3 line.long 0x0 "PM_IPU_PWRSTCTRL,This register controls the IPU domain power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. " AESSMEM_RETSTATE ,AESSMEM memory state when domain is RETENTION." "0,1" textline " " bitfld.long 0x0 9. " RESERVED ," "0,1" bitfld.long 0x0 10. " PERIPHMEM_RETSTATE ,PERIPHMEM memory state when domain is RETENTION." "0,1" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 16.--17. " AESSMEM_ONSTATE ,AESSMEM memory state when domain is ON." "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" bitfld.long 0x0 20.--21. " PERIPHMEM_ONSTATE ,PERIPHMEM memory state when domain is ON." "0,1,2,3" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_IPU_PWRSTST,This register provides a status on the IPU domain current power domain state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " AESSMEM_STATEST ,AESSMEM memory state status" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8.--9. " PERIPHMEM_STATEST ,PERIPHMEM memory state status" "0,1,2,3" textline " " hexmask.long.word 0x0 10.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_IPU1_RSTCTRL,This register controls the release of the IPU1 sub-system resets." bitfld.long 0x0 0. " RST_CPU0 ,IPU Cortex M4 CPU0 reset control." "0,1" bitfld.long 0x0 1. " RST_CPU1 ,IPU Cortex M4 CPU1 reset control" "0,1" textline " " bitfld.long 0x0 2. " RST_IPU ,IPU1 system reset control." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "RM_IPU1_RSTST,This register logs the different reset sources of the IPU1 SS. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RST_CPU0 ,IPU Cortex-M4 CPU0 software reset status" "0,1" bitfld.long 0x0 1. " RST_CPU1 ,IPU Cortex-M4 CPU1 software reset status" "0,1" textline " " bitfld.long 0x0 2. " RST_IPU ,IPU system software reset status" "0,1" bitfld.long 0x0 3. " RST_EMULATION_CPU0 ,Cortex M4 CPU0 has been reset due to emulation reset source, for example, assert reset command initiated by the icepick module" "0,1" textline " " bitfld.long 0x0 4. " RST_EMULATION_CPU1 ,Cortex M4 CPU1 has been reset due to emulation reset source, for example, assert reset command initiated by the icepick module" "0,1" bitfld.long 0x0 5. " RST_ICECRUSHER_CPU0 ,Cortex M4 CPU0 has been reset due to IPU ICECRUSHER0 reset source" "0,1" textline " " bitfld.long 0x0 6. " RST_ICECRUSHER_CPU1 ,Cortex M4 CPU1 has been reset due to IPU ICECRUSHER1 reset source" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_IPU1_IPU1_CONTEXT,This register contains dedicated IPU1 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of IPU_RST signal)" "0,1" bitfld.long 0x0 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of IPU_RET_RST signal)" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " LOSTMEM_IPU_UNICACHE ,Specify if memory-based context in IPU_UNICACHE memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " bitfld.long 0x0 9. " LOSTMEM_IPU_L2RAM ,Specify if memory-based context in IPU_L2RAM memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "PM_IPU_MCASP1_WKDEP,This register controls wakeup dependency based on MCASP1 service requests." bitfld.long 0x0 0. " WKUPDEP_MCASP1_IRQ_MPU ,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCASP1_IRQ_IPU2 ,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCASP1_IRQ_DSP1 ,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCASP1_IRQ_IPU1 ,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCASP1_IRQ_DSP2 ,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCASP1_IRQ_EVE1 ,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCASP1_IRQ_EVE2 ,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCASP1_IRQ_EVE3 ,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCASP1_IRQ_EVE4 ,Wakeup dependency from MCASP1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_MCASP1_DMA_DSP1 ,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_MCASP1_DMA_SDMA ,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_MCASP1_DMA_DSP2 ,Wakeup dependency from MCASP1 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "PM_IPU_TIMER5_WKDEP,This register controls wakeup dependency based on TIMER5 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER5_MPU ,Wakeup dependency from TIMER5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER5_IPU2 ,Wakeup dependency from TIMER5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER5_DSP1 ,Wakeup dependency from TIMER5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER5_IPU1 ,Wakeup dependency from TIMER5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER5_DSP2 ,Wakeup dependency from TIMER5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER5_EVE1 ,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER5_EVE2 ,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER5_EVE3 ,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER5_EVE4 ,Wakeup dependency from TIMER5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "PM_IPU_TIMER6_WKDEP,This register controls wakeup dependency based on TIMER6 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER6_MPU ,Wakeup dependency from TIMER6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER6_IPU2 ,Wakeup dependency from TIMER6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER6_DSP1 ,Wakeup dependency from TIMER6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER6_IPU1 ,Wakeup dependency from TIMER6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER6_DSP2 ,Wakeup dependency from TIMER6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER6_EVE1 ,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER6_EVE2 ,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER6_EVE3 ,Wakeup dependency from TIMER6 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER6_EVE4 ,Wakeup dependency from TIMER6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "PM_IPU_TIMER7_WKDEP,This register controls wakeup dependency based on TIMER7 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER7_MPU ,Wakeup dependency from TIMER7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER7_IPU2 ,Wakeup dependency from TIMER7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER7_DSP1 ,Wakeup dependency from TIMER7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER7_IPU1 ,Wakeup dependency from TIMER7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER7_DSP2 ,Wakeup dependency from TIMER7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER7_EVE1 ,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER7_EVE2 ,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER7_EVE3 ,Wakeup dependency from TIMER7 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER7_EVE4 ,Wakeup dependency from TIMER7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "PM_IPU_TIMER8_WKDEP,This register controls wakeup dependency based on TIMER8 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER8_MPU ,Wakeup dependency from TIMER8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER8_IPU2 ,Wakeup dependency from TIMER8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER8_DSP1 ,Wakeup dependency from TIMER8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER8_IPU1 ,Wakeup dependency from TIMER8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER8_DSP2 ,Wakeup dependency from TIMER8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER8_EVE1 ,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER8_EVE2 ,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER8_EVE3 ,Wakeup dependency from TIMER8 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER8_EVE4 ,Wakeup dependency from TIMER8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "PM_IPU_I2C5_WKDEP,This register controls wakeup dependency based on I2C5 service requests." bitfld.long 0x0 0. " WKUPDEP_I2C5_IRQ_MPU ,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_I2C5_IRQ_IPU2 ,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_I2C5_IRQ_DSP1 ,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_I2C5_IRQ_IPU1 ,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_I2C5_IRQ_DSP2 ,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_I2C5_IRQ_EVE1 ,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_I2C5_IRQ_EVE2 ,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_I2C5_IRQ_EVE3 ,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_I2C5_IRQ_EVE4 ,Wakeup dependency from I2C5 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_I2C5_DMA_DSP1 ,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_I2C5_DMA_SDMA ,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_I2C5_DMA_DSP2 ,Wakeup dependency from I2C5 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PM_IPU_UART6_WKDEP,This register controls wakeup dependency based on UART6 service requests." bitfld.long 0x0 0. " WKUPDEP_UART6_MPU ,Wakeup dependency from UART6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_UART6_IPU2 ,Wakeup dependency from UART6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_UART6_DSP1 ,Wakeup dependency from UART6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_UART6_SDMA ,Wakeup dependency from UART6 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_UART6_IPU1 ,Wakeup dependency from UART6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_UART6_DSP2 ,Wakeup dependency from UART6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_UART6_EVE1 ,Wakeup dependency from UART6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_UART6_EVE2 ,Wakeup dependency from UART6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_UART6_EVE3 ,Wakeup dependency from UART6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_UART6_EVE4 ,Wakeup dependency from UART6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE__DSS" base ad:0x4A009100 width 23. group.byte 0x0++0x3 line.long 0x0 "CM_DSS_CLKSTCTRL,This register enables the DSS domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSS clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_DSS_L3_GICLK ,This field indicates the state of the DSS_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_DSS_GFCLK ,This field indicates the state of the DSS_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_VIDEO1_DPLL_CLK ,This field indicates the state of the VIDEO1_DPLL_CLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 11. " CLKACTIVITY_HDMI_DPLL_CLK ,This field indicates the state of the HDMI_DPLL_CLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 12. " CLKACTIVITY_VIDEO2_DPLL_CLK ,This field indicates the state of the VIDEO2_DPLL_CLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 13. " CLKACTIVITY_BB2D_GFCLK ,This field indicates the state of the BB2D_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 14. " CLKACTIVITY_SDVENC_GFCLK ,This field indicates the state of the SDVENC_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 15. " CLKACTIVITY_DSS_L4_GICLK ,This field indicates the state of the DSS_L4_GICLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 16. " CLKACTIVITY_DSS_SYS_GFCLK ,This field indicates the state of the DSS_SYS_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 17. " CLKACTIVITY_HDMI_CEC_GFCLK ,This field indicates the state of the HDMI_CEC_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 18. " CLKACTIVITY_HDMI_PHY_GFCLK ,This field indicates the state of the HDMI_PHY_GFCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_DSS_STATICDEP,This register controls the static domain depedencies from DSS domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "CM_DSS_DYNAMICDEP,This register controls the dynamic domain depedencies from DSS domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 domain" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_DSS_DSS_CLKCTRL,This register manages the DSS clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_DSSCLK ,Optional functional clock control." "0,1" bitfld.long 0x0 9. " OPTFCLKEN_48MHZ_CLK ,Optional functional clock control." "0,1" textline " " bitfld.long 0x0 10. " OPTFCLKEN_HDMI_CLK ,Optional functional clock control." "0,1" bitfld.long 0x0 11. " OPTFCLKEN_32KHZ_CLK ,Optional functional clock control." "0,1" textline " " bitfld.long 0x0 12. " OPTFCLKEN_VIDEO1_CLK ,Optional functional clock control." "0,1" bitfld.long 0x0 13. " OPTFCLKEN_VIDEO2_CLK ,Optional functional clock control." "0,1" textline " " bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" textline " " bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "CM_DSS_BB2D_CLKCTRL,This register manages the BB2D clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "CM_DSS_SDVENC_CLKCTRL,This register manages the SDVENC clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__CKGEN" base ad:0x4A005100 width 29. group.byte 0x0++0x3 line.long 0x0 "CM_CLKSEL_CORE,CORE module clock selection." bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CLKSEL_L3 ,Selects L3 interconnect clock (L3_clk)" "0,1" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. " CLKSEL_L4 ,Selects L4 interconnect clock (L4_clk)" "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "CM_CLKSEL_ABE,ABE module clock selection." bitfld.long 0x0 0.--1. " CLKSEL_OPP ,Selects the OPP divider ABE domain" "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " PAD_CLKS_GATE ,Gating control for PAD_CLKS clock tree in ABE" "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " SLIMBUS1_CLK_GATE ,Gating control for SLIMBUS_CLK clock tree in ABE. SLIMBUS module always gets the ungated version." "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "CM_DLL_CTRL,Special register for DLL control" bitfld.long 0x0 0. " DLL_OVERRIDE ,Control if DLL lock and code outputs are overriden or not" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_CLKMODE_DPLL_CORE,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set." "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled." "0,1" bitfld.long 0x0 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled." "0,1" textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "CM_IDLEST_DPLL_CORE,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_CORE,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "CM_CLKSEL_DPLL_CORE,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M). [warm reset insensitive]" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20. " DPLL_CLKOUTHIF_CLKSEL ,Selects the source of the DPLL CLKOUTHIF clock. Same as CLKINPHIFSEL pin on the DPLL" "0,1" bitfld.long 0x0 21. " RESERVED ," "0,1" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "CM_DIV_M2_DPLL_CORE,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M2 post-divider factor (1 to 31) of DPLL_CORE.... enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "CM_DIV_M3_DPLL_CORE,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,DPLL M3 post-divider factor (1 to 31)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUTHIF status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "CM_DIV_H11_DPLL_CORE,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,DPLL (H11+1) post-divider factor (1 to 63)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT1 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "CM_DIV_H12_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H12 post-divider factor (1 to 63) of DPLL_CORE.... enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT2 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "CM_DIV_H13_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H13 post-divider factor (1 to 63) of DPLL_CORE.... enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT3 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "CM_DIV_H14_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H14 post-divider factor (1 to 63) of DPLL_CORE. When a value of 63 is programmed in this register, HS divider will perform division by 2.5 that is divided by 2 at top level.... enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT4 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_CORE,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_CORE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "CM_DIV_H21_DPLL_CORE,This register provides controls over the CLKOUT1 o/p of the 2nd HSDIVIDER." bitfld.long 0x0 0.--5. " DIVHS ,DPLL (H21+1) post-divider factor (1 to 63)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER2 CLKOUT2 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "CM_DIV_H22_DPLL_CORE,This register provides controls over the CLKOUT2 o/p of the 2nd HSDIVIDER." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H22 post-divider factor (1 to 63) of DPLL_CORE.... enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER2 CLKOUT2 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "CM_DIV_H23_DPLL_CORE,This register provides controls over the CLKOUT3 o/p of the 2nd HSDIVIDER." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H23 post-divider factor (1 to 63) of DPLL_CORE.... enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER2 CLKOUT3 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "CM_DIV_H24_DPLL_CORE,This register provides controls over the CLKOUT4 o/p of the 2nd HSDIVIDER." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H24 post-divider factor (1 to 63) of DPLL_CORE.... enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER2 CLKOUT4 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "CM_CLKMODE_DPLL_MPU,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set." "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled." "0,1" bitfld.long 0x0 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled." "0,1" textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "CM_IDLEST_DPLL_MPU,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_MPU,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control;" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "CM_CLKSEL_DPLL_MPU,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M). [warm reset insensitive]" bitfld.long 0x0 19.--21. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Only CLKINPULOW bypass clock supported for this PLL" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "CM_DIV_M2_DPLL_MPU,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M2 post-divider factor (1 to 31) of DPLL_MPU.... enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_MPU,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_MPU,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "CM_BYPCLK_DPLL_MPU,Control MPU PLL BYPASS clock. [warm reset insensitive]" bitfld.long 0x0 0.--1. " CLKSEL ,Select the DPLL MPU bypass clock" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "CM_CLKMODE_DPLL_IVA,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set." "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled." "0,1" bitfld.long 0x0 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled." "0,1" textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "CM_IDLEST_DPLL_IVA,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_IVA,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control;" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xAC++0x3 line.long 0x0 "CM_CLKSEL_DPLL_IVA,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M). [warm reset insensitive]" bitfld.long 0x0 19.--21. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB0++0x3 line.long 0x0 "CM_DIV_M2_DPLL_IVA,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M2 post-divider factor (1 to 31) of DPLL_IVA.... enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "CM_DIV_M3_DPLL_IVA,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,DPLL M3 post-divider factor (1 to 31)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUTHIF status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xC8++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_IVA,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0xCC++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_IVA,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0xDC++0x3 line.long 0x0 "CM_BYPCLK_DPLL_IVA,Control IVA PLL BYPASS clock. [warm reset insensitive]" bitfld.long 0x0 0.--1. " CLKSEL ,Select the DPLL IVA bypass clock" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "CM_CLKMODE_DPLL_ABE,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set." "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled." "0,1" bitfld.long 0x0 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled." "0,1" textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xE4++0x3 line.long 0x0 "CM_IDLEST_DPLL_ABE,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xE8++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_ABE,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control;" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xEC++0x3 line.long 0x0 "CM_CLKSEL_DPLL_ABE,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M). [warm reset insensitive]" bitfld.long 0x0 19.--21. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Only CLKINPULOW bypass clock supported for this PLL" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "CM_DIV_M2_DPLL_ABE,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M2 post-divider factor (1 to 31) of DPLL_ABE.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " CLKX2ST ,DPLL CLKOUTX2 status" "0,1" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0xF4++0x3 line.long 0x0 "CM_DIV_M3_DPLL_ABE,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M3 post-divider factor (1 to 31) of DPLL_ABE.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUTHIF status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_ABE,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_ABE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "CM_CLKMODE_DPLL_DDR,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set." "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled." "0,1" bitfld.long 0x0 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled." "0,1" textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x114++0x3 line.long 0x0 "CM_IDLEST_DPLL_DDR,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x118++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_DDR,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control;" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x11C++0x3 line.long 0x0 "CM_CLKSEL_DPLL_DDR,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M). [warm reset insensitive]" bitfld.long 0x0 19.--21. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x120++0x3 line.long 0x0 "CM_DIV_M2_DPLL_DDR,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M2 post-divider factor (1 to 31) of DPLL_DDR.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "CM_DIV_M3_DPLL_DDR,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M3 post-divider factor (1 to 31) of DPLL_DDR.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUTHIF status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x128++0x3 line.long 0x0 "CM_DIV_H11_DPLL_DDR,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H11 post-divider factor (1 to 63) of DPLL_DDR.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT1 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x12C++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_DDR,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_DDR,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x134++0x3 line.long 0x0 "CM_CLKMODE_DPLL_DSP,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set." "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled." "0,1" bitfld.long 0x0 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled." "0,1" textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x138++0x3 line.long 0x0 "CM_IDLEST_DPLL_DSP,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x13C++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_DSP,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control;" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x140++0x3 line.long 0x0 "CM_CLKSEL_DPLL_DSP,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M). [warm reset insensitive]" bitfld.long 0x0 19.--21. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x144++0x3 line.long 0x0 "CM_DIV_M2_DPLL_DSP,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M2 post-divider factor (1 to 31) of DPLL_DSP.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x148++0x3 line.long 0x0 "CM_DIV_M3_DPLL_DSP,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M3 post-divider factor (1 to 31) of DPLL_DSP.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUTHIF status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x14C++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_DSP,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x150++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_DSP,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x154++0x3 line.long 0x0 "CM_BYPCLK_DPLL_DSP,Control IVA PLL BYPASS clock. [warm reset insensitive]" bitfld.long 0x0 0.--1. " CLKSEL ,Select the DPLL IVA bypass clock" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x160++0x3 line.long 0x0 "CM_SHADOW_FREQ_CONFIG1,Shadow register to program new DPLL configuration affecting EMIF and GPMC (L3 clock) functional frequency during DVFS. The PRCM h/w automatically applies the new configuration after EMIF/GPMC have been put in idle state." bitfld.long 0x0 0. " FREQ_UPDATE ,Writing '1' indicates that a new configuration is available. It is automatically cleared by h/w after the configuration has been applied." "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " DLL_OVERRIDE ,Shadow register forCM_DLL_CTRL.DLL_OVERRIDE.The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to '1'." "0,1" bitfld.long 0x0 3. " DLL_RESET ,Specify if DLL should be reset or not during the frequency change hardware sequence." "0,1" textline " " hexmask.long.byte 0x0 4.--10. 1. " RESERVED ," bitfld.long 0x0 11.--15. " DPLL_DDR_M2_DIV ,Shadow register forCM_DIV_M2_DPLL_DDR.DIVHS. The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to '1'. Divide value from 1 to 31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--18. " DPLL_DDR_DPLL_EN ,Shadow register forCM_CLKMODE_DPLL_DDR.DPLL_EN. The main register is automatically loaded with the shadow register value after EMIF IDLE if the FREQ_UPDATE field is set to '1'." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x164++0x3 line.long 0x0 "CM_SHADOW_FREQ_CONFIG2,Shadow register to program new DPLL configuration affecting GPMC (L3 clock) functional frequency during DVFS. The PRCM h/w automatically applies the new configuration after EMIF/GPMC have been put in idle state." bitfld.long 0x0 0. " GPMC_FREQ_UPDATE ,Controls whether or not GPMC has to be put automatically into idle during the frequency change operation." "0,1" bitfld.long 0x0 1. " CLKSEL_L3 ,Shadow register forCM_CLKSEL_CORE.CLKSEL_L3. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to '1' and GPMC_FREQ_UPDATE is set to '1'." "0,1" textline " " bitfld.long 0x0 2.--7. " DPLL_CORE_H12_DIV ,Shadow register forCM_DIV_H12_DPLL_CORE.DIVHS. The main register is automatically loaded with the shadow register value after GPMC IDLE if the CM_SHADOW_FREQ_CONFIG1.FREQ_UPDATE field is set to '1' and GPMC_FREQ_UPDATE is set to '1'. Divide value from 1 to 31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x170++0x3 line.long 0x0 "CM_DYN_DEP_PRESCAL,Control the time unit of the sliding window for dynamic dependencies (auto-sleep feature)." bitfld.long 0x0 0.--5. " PRESCAL ,Time unit is equal to (PRESCAL + 1) L4 clock cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x180++0x3 line.long 0x0 "CM_RESTORE_ST,Automatic restore status. This register is used by the system DMA to write a predefined value at the end of each automatic restore phase. [warm reset insensitive]" bitfld.long 0x0 0. " PHASE1_COMPLETED ,Indicates if restore phase 1 is completed." "0,1" bitfld.long 0x0 1. " PHASE2A_COMPLETED ,Indicates if restore phase 2a is completed." "0,1" textline " " bitfld.long 0x0 2. " PHASE2B_COMPLETED ,Indicates if restore phase 2b is completed." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x184++0x3 line.long 0x0 "CM_CLKMODE_DPLL_EVE,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set." "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled." "0,1" bitfld.long 0x0 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled." "0,1" textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x188++0x3 line.long 0x0 "CM_IDLEST_DPLL_EVE,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x18C++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_EVE,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control;" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x190++0x3 line.long 0x0 "CM_CLKSEL_DPLL_EVE,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M). [warm reset insensitive]" bitfld.long 0x0 19.--21. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x194++0x3 line.long 0x0 "CM_DIV_M2_DPLL_EVE,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M2 post-divider factor (1 to 31) of DPLL_EVE.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x198++0x3 line.long 0x0 "CM_DIV_M3_DPLL_EVE,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,DPLL M3 post-divider factor (1 to 31)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUTHIF status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x19C++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_EVE,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x1A0++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_EVE,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x1A4++0x3 line.long 0x0 "CM_BYPCLK_DPLL_EVE,Control IVA PLL BYPASS clock. [warm reset insensitive]" bitfld.long 0x0 0.--1. " CLKSEL ,Select the DPLL IVA bypass clock" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x1A8++0x3 line.long 0x0 "CM_CLKMODE_DPLL_GMAC,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set." "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled." "0,1" bitfld.long 0x0 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled." "0,1" textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x1AC++0x3 line.long 0x0 "CM_IDLEST_DPLL_GMAC,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x1B0++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_GMAC,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control;" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1B4++0x3 line.long 0x0 "CM_CLKSEL_DPLL_GMAC,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M). [warm reset insensitive]" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20. " DPLL_CLKOUTHIF_CLKSEL ,Selects the source of the DPLL CLKOUTHIF clock. Same as CLKINPHIFSEL pin on the DPLL" "0,1" bitfld.long 0x0 21. " RESERVED ," "0,1" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x1B8++0x3 line.long 0x0 "CM_DIV_M2_DPLL_GMAC,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M2 post-divider factor (1 to 31) of DPLL_GMAC.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x1BC++0x3 line.long 0x0 "CM_DIV_M3_DPLL_GMAC,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M3 post-divider factor (1 to 31) of DPLL_GMAC.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUTHIF status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x1C0++0x3 line.long 0x0 "CM_DIV_H11_DPLL_GMAC,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H11 post-divider factor (1 to 63) of DPLL_GMAC.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT1 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x1C4++0x3 line.long 0x0 "CM_DIV_H12_DPLL_GMAC,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H12 post-divider factor (1 to 63) of DPLL_GMAC.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT2 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x1C8++0x3 line.long 0x0 "CM_DIV_H13_DPLL_GMAC,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H13 post-divider factor (1 to 63) of DPLL_GMAC.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT3 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x1CC++0x3 line.long 0x0 "CM_DIV_H14_DPLL_GMAC,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,DPLL (H14+1) post-divider factor (1 to 63)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT4 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x1D0++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_GMAC,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x1D4++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_GMAC,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x1D8++0x3 line.long 0x0 "CM_CLKMODE_DPLL_GPU,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set." "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled." "0,1" bitfld.long 0x0 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled." "0,1" textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x1DC++0x3 line.long 0x0 "CM_IDLEST_DPLL_GPU,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x1E0++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_GPU,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1E4++0x3 line.long 0x0 "CM_CLKSEL_DPLL_GPU,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M). [warm reset insensitive]" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20. " DPLL_CLKOUTHIF_CLKSEL ,Selects the source of the DPLL CLKOUTHIF clock. Same as CLKINPHIFSEL pin on the DPLL" "0,1" bitfld.long 0x0 21. " RESERVED ," "0,1" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x1E8++0x3 line.long 0x0 "CM_DIV_M2_DPLL_GPU,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M2 post-divider factor (1 to 31) of DPLL_GPU.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x1EC++0x3 line.long 0x0 "CM_DIV_M3_DPLL_GPU,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,DPLL M3 post-divider factor (1 to 31)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUTHIF status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_GPU,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x1F4++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_GPU,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__RTC" base ad:0x4A005740 width 22. group.byte 0x0++0x3 line.long 0x0 "CM_RTC_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the WKUPAON clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_RTC_L4_GICLK ,This field indicates the state of the RTC_L4_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_RTC_AUX_CLK ,This field indicates the state of the RTC_AUX_CLK in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_RTC_RTCSS_CLKCTRL,This register manages the RTC clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," width 0x0B tree.end tree "INSTR_PRM" base ad:0x4AE07F00 width 21. group.byte 0x0++0x3 line.long 0x0 "PMI_IDENTICATION,PM profiling identification register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "PMI_SYS_CONFIG,PM profiling system configuartion register" bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local tartget state management mode" "0,1,2,3" bitfld.long 0x0 4.--5. " RESERVED ," "0,1,2,3" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PMI_STATUS,PM profiling status register" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " FIFOEMPTY ,PM Profiling buffer empty" "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PMI_CONFIGURATION,PM profiling configuration register" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ," bitfld.long 0x0 7. " EVT_CAPT_EN ,When HIGH the PM events capture is enabled" "0,1" textline " " hexmask.long.byte 0x0 8.--14. 1. " RESERVED ," bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.byte 0x0 16.--22. 1. " RESERVED ," bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--27. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28. " CLAIM_1 ,Current owner" "0,1" textline " " bitfld.long 0x0 29. " CLAIM_2 ,Debugger override qualifier" "0,1" bitfld.long 0x0 30.--31. " CLAIM_3 ,Ownership" "0,1,2,3" group.byte 0x28++0x3 line.long 0x0 "PMI_CLASS_FILTERING,PM profiling class filtering register" bitfld.long 0x0 0. " SNAP_CAPT_EN_00 ,Snapshot capture enable - Class-ID = 0x00" "0,1" bitfld.long 0x0 1. " SNAP_CAPT_EN_01 ,Snapshot capture enable - Class-ID = 0x01" "0,1" textline " " bitfld.long 0x0 2. " SNAP_CAPT_EN_02 ,Snapshot capture enable - Class-ID = 0x02" "0,1" bitfld.long 0x0 3. " SNAP_CAPT_EN_03 ,Snapshot capture enable - Class-ID = 0x03" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PMI_TRIGGERING,PM profiling triggering control register" bitfld.long 0x0 0. " TRIG_START_EN ,Enable start capturing PM events from external trigger detection" "0,1" bitfld.long 0x0 1. " TRIG_STOP_EN ,Enable stop capturing PM events from external trigger detection" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PMI_SAMPLING,PM profiling sampling window register" hexmask.long.byte 0x0 0.--7. 1. " SAMP_WIND_SIZE ,PM events sampling window size" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--19. " FCLK_DIV_FACOR ,FunClk divide factor ranging from 1 to 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE__CORE" base ad:0x4A008700 width 42. group.byte 0x0++0x3 line.long 0x0 "CM_L3MAIN1_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3MAIN1 clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_L3MAIN1_L3_GICLK ,This field indicates the state of the L3MAIN1_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_L3MAIN1_L4_GICLK ,This field indicates the state of the L3MAIN1_L4_GICLK clock in the domain. [warm reset insensitive]" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "CM_L3MAIN1_DYNAMICDEP,This register controls the dynamic domain depedencies from L3MAIN1 domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0. " IPU2_DYNDEP ,Dynamic dependency towards IPU2 clock domain" "0,1" bitfld.long 0x0 1. " DSP1_DYNDEP ,Dynamic dependency towards DSP1 clock domain" "0,1" textline " " bitfld.long 0x0 2. " IVA_DYNDEP ,Dynamic dependency towards IVA clock domain" "0,1" bitfld.long 0x0 3. " IPU_DYNDEP ,Dynamic dependency towards IPU clock domain" "0,1" textline " " bitfld.long 0x0 4. " EMIF_DYNDEP ,Dynamic dependency towards EMIF clock domain" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " DSS_DYNDEP ,Dynamic dependency towards DSS clock domain" "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " GPU_DYNDEP ,Dynamic dependency towards GPU clock domain" "0,1" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12. " L4CFG_DYNDEP ,Dynamic dependency towards L4CFG clock domain" "0,1" bitfld.long 0x0 13. " L4PER_DYNDEP ,Dynamic dependency towards L4PER1 clock domain" "0,1" textline " " bitfld.long 0x0 14. " L4SEC_DYNDEP ,Dynamic dependency towards L4SEC clock domain" "0,1" bitfld.long 0x0 15. " WKUPAON_DYNDEP ,Dynamic dependency towards WKUPAON clock domain" "0,1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" bitfld.long 0x0 18. " IPU1_DYNDEP ,Dynamic dependency towards IPU1 clock domain" "0,1" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20. " DSP2_DYNDEP ,Dynamic dependency towards DSP2 clock domain" "0,1" textline " " bitfld.long 0x0 21. " PCIE_DYNDEP ,Dynamic dependency towards PCIE clock domain" "0,1" bitfld.long 0x0 22. " L4PER2_DYNDEP ,Dynamic dependency towards L4PER2 clock domain" "0,1" textline " " bitfld.long 0x0 23. " L4PER3_DYNDEP ,Dynamic dependency towards L4PER3 clock domain" "0,1" bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28. " EVE1_DYNDEP ,Dynamic dependency towards EVE1 clock domain" "0,1" bitfld.long 0x0 29. " EVE2_DYNDEP ,Dynamic dependency towards EVE2 clock domain" "0,1" textline " " bitfld.long 0x0 30. " EVE3_DYNDEP ,Dynamic dependency towards EVE3 clock domain" "0,1" bitfld.long 0x0 31. " EVE4_DYNDEP ,Dynamic dependency towards EVE4 clock domain" "0,1" group.byte 0x20++0x3 line.long 0x0 "CM_L3MAIN1_L3_MAIN_1_CLKCTRL,This register manages the L3_MAIN_1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "CM_L3MAIN1_GPMC_CLKCTRL,This register manages the GPMC clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "CM_L3MAIN1_MMU_EDMA_CLKCTRL,This register manages the MMU_L4_EDMA clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "CM_L3MAIN1_MMU_PCIESS_CLKCTRL,This register manages the MMU_L4_PCIESS clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "CM_L3MAIN1_OCMC_RAM1_CLKCTRL,This register manages the OCMC_RAM1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "CM_L3MAIN1_OCMC_RAM2_CLKCTRL,This register manages the OCMC_RAM2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "CM_L3MAIN1_OCMC_RAM3_CLKCTRL,This register manages the OCMC_RAM3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "CM_L3MAIN1_OCMC_ROM_CLKCTRL,This register manages the OCMC_RAM clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "CM_L3MAIN1_TPCC_CLKCTRL,This register manages the TPCC clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "CM_L3MAIN1_TPTC1_CLKCTRL,This register manages the TPTC1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "CM_L3MAIN1_TPTC2_CLKCTRL,This register manages the TPTC2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CM_L3MAIN1_VCP1_CLKCTRL,This register manages the VCP1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "CM_L3MAIN1_VCP2_CLKCTRL,This register manages the VCP2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_CME_CLKCTRL,This register manages the SPARE_CME clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_HDMI_CLKCTRL,This register manages the SPARE_HDMI clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_ICM_CLKCTRL,This register manages the SPARE_ICM clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB0++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_IVA2_CLKCTRL,This register manages the SPARE_IVA2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_SATA2_CLKCTRL,This register manages the SPARE_SATA2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC0++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL,This register manages the SPARE_UNKNOWN4 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC8++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL,This register manages the SPARE_UNKNOWN5 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL,This register manages the SPARE_UNKNOWN6 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD8++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL,This register manages the SPARE_VIDEOPLL1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL,This register manages the SPARE_VIDEOPLL2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xF8++0x3 line.long 0x0 "CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL,This register manages the SPARE_VIDEOPLL3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x200++0x3 line.long 0x0 "CM_IPU2_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the IPU2 clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_IPU2_GFCLK ,This field indicates the state of the IPU2_GFCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x204++0x3 line.long 0x0 "CM_IPU2_STATICDEP,This register controls the static domain depedencies from IPU domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " DSP1_STATDEP ,Static dependency towards DSP clock domain" "0,1" textline " " bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain" "0,1" textline " " bitfld.long 0x0 8. " DSS_STATDEP ,Static dependency towards DSS clock domain" "0,1" bitfld.long 0x0 9. " CAM_STATDEP ,Static dependency towards CAM clock domain" "0,1" textline " " bitfld.long 0x0 10. " GPU_STATDEP ,Static dependency towards GPU clock domain" "0,1" bitfld.long 0x0 11. " SDMA_STATDEP ,Static dependency towards DMA clock domain" "0,1" textline " " bitfld.long 0x0 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain" "0,1" bitfld.long 0x0 13. " L4PER_STATDEP ,Static dependency towards L4PER1 clock domain" "0,1" textline " " bitfld.long 0x0 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain" "0,1" bitfld.long 0x0 15. " WKUPAON_STATDEP ,Static dependency towards WKUPAON clock domain" "0,1" textline " " bitfld.long 0x0 16. " COREAON_STATDEP ,Static dependency towards COREAON clock domain" "0,1" bitfld.long 0x0 17. " CUSTEFUSE_STATDEP ,Static dependency towards CUSTEFUSE clock domain" "0,1" textline " " bitfld.long 0x0 18. " DSP2_STATDEP ,Static dependency towards DSP2 clock domain" "0,1" bitfld.long 0x0 19. " EVE1_STATDEP ,Static dependency towards EVE1 clock domain" "0,1" textline " " bitfld.long 0x0 20. " EVE2_STATDEP ,Static dependency towards EVE2 clock domain" "0,1" bitfld.long 0x0 21. " EVE3_STATDEP ,Static dependency towards EVE3 clock domain" "0,1" textline " " bitfld.long 0x0 22. " EVE4_STATDEP ,Static dependency towards EVE4 clock domain" "0,1" bitfld.long 0x0 23. " IPU1_STATDEP ,Static dependency towards IPU1 clock domain" "0,1" textline " " bitfld.long 0x0 24. " IPU_STATDEP ,Static dependency towards IPU clock domain" "0,1" bitfld.long 0x0 25. " GMAC_STATDEP ,Static dependency towards GMAC clock domain" "0,1" textline " " bitfld.long 0x0 26. " L4PER2_STATDEP ,Static dependency towards L4PER2 clock domain" "0,1" bitfld.long 0x0 27. " L4PER3_STATDEP ,Static dependency towards L4PER3 clock domain" "0,1" textline " " bitfld.long 0x0 28. " VPE_STATDEP ,Static dependency towards VPE clock domain" "0,1" bitfld.long 0x0 29. " PCIE_STATDEP ,Static dependency towards PCIE clock domain" "0,1" textline " " bitfld.long 0x0 30. " ATL_STATDEP ,Static dependency towards ATL clock domain" "0,1" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x208++0x3 line.long 0x0 "CM_IPU2_DYNAMICDEP,This register controls the dynamic domain depedencies from IPU domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " CAM_DYNDEP ,Dynamic dependency towards CAM clock domain" "0,1" textline " " hexmask.long.word 0x0 10.--23. 1. " RESERVED ," bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x220++0x3 line.long 0x0 "CM_IPU2_IPU2_CLKCTRL,This register manages the IPU2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x300++0x3 line.long 0x0 "CM_DMA_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DMA clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_DMA_L3_GICLK ,This field indicates the state of the DMA_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x304++0x3 line.long 0x0 "CM_DMA_STATICDEP,This register controls the static domain depedencies from DMA domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0. " IPU2_STATDEP ,Static dependency towards IPU2 clock domain" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain" "0,1" textline " " bitfld.long 0x0 8. " DSS_STATDEP ,Static dependency towards DSS clock domain" "0,1" bitfld.long 0x0 9. " CAM_STATDEP ,Static dependency towards CAM clock domain" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain" "0,1" textline " " bitfld.long 0x0 13. " L4PER_STATDEP ,Static dependency towards L4PER1 clock domain" "0,1" bitfld.long 0x0 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain" "0,1" textline " " bitfld.long 0x0 15. " WKUPAON_STATDEP ,Static dependency towards WKUPAON clock domain" "0,1" hexmask.long.byte 0x0 16.--22. 1. " RESERVED ," textline " " bitfld.long 0x0 23. " IPU1_STATDEP ,Static dependency towards IPU1 clock domain" "0,1" bitfld.long 0x0 24. " IPU_STATDEP ,Static dependency towards IPU clock domain" "0,1" textline " " bitfld.long 0x0 25. " RESERVED ," "0,1" bitfld.long 0x0 26. " L4PER2_STATDEP ,Static dependency towards L4PER2 clock domain" "0,1" textline " " bitfld.long 0x0 27. " L4PER3_STATDEP ,Static dependency towards L4PER3 clock domain" "0,1" bitfld.long 0x0 28. " RESERVED ," "0,1" textline " " bitfld.long 0x0 29. " PCIE_STATDEP ,Static dependency towards PCIE clock domain" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x308++0x3 line.long 0x0 "CM_DMA_DYNAMICDEP,This register controls the dynamic domain depedencies from SDMA domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x320++0x3 line.long 0x0 "CM_DMA_DMA_SYSTEM_CLKCTRL,This register manages the DMA_SYSTEM clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x400++0x3 line.long 0x0 "CM_EMIF_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the EMIF clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_EMIF_L3_GICLK ,This field indicates the state of the EMIF_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_EMIF_DLL_GCLK ,This field indicates the state of the DLL_GCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_EMIF_PHY_GCLK ,This field indicates the state of the EMIF_PHY_GCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x420++0x3 line.long 0x0 "CM_EMIF_DMM_CLKCTRL,This register manages the DMM clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x428++0x3 line.long 0x0 "CM_EMIF_EMIF_OCP_FW_CLKCTRL,This register manages the EMIF_OCP_FW clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x430++0x3 line.long 0x0 "CM_EMIF_EMIF1_CLKCTRL,This register manages the EMIF1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL_LL ,Source of EMIF1 External Low Latency interface clock EMIF_LL_GCLK Value is provided by LLI_C2C_SELECT input pin" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x438++0x3 line.long 0x0 "CM_EMIF_EMIF2_CLKCTRL,This register manages the EMIF2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x440++0x3 line.long 0x0 "CM_EMIF_EMIF_DLL_CLKCTRL,This register manages the DLL clock." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " OPTFCLKEN_DLL_CLK ,Optional functional clock control." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "CM_ATL_ATL_CLKCTRL,This register manages the ATL clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--25. " CLKSEL_SOURCE1 ,Selects source for ATL clock" "0,1,2,3" bitfld.long 0x0 26.--27. " CLKSEL_SOURCE2 ,Selects source for ATL clock" "0,1,2,3" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x520++0x3 line.long 0x0 "CM_ATL_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the ATL clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_ATL_L3_GICLK ,This field indicates the state of the ATL_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_ATL_GFCLK ,This field indicates the state of the ATL_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x600++0x3 line.long 0x0 "CM_L4CFG_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4CFG clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_L4CFG_L4_GICLK ,This field indicates the state of the L4CFG_L4_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_L4CFG_L3_GICLK ,This field indicates the state of the L4CFG_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x608++0x3 line.long 0x0 "CM_L4CFG_DYNAMICDEP,This register controls the dynamic domain depedencies from L4CFG domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " EMIF_DYNDEP ,Dynamic dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" bitfld.long 0x0 6. " RESERVED ," "0,1" textline " " bitfld.long 0x0 7. " L3INIT_DYNDEP ,Dynamic dependency towards L3INIT clock domain" "0,1" bitfld.long 0x0 8.--10. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " SDMA_DYNDEP ,Dynamic dependency towards DMA clock domain" "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " COREAON_DYNDEP ,Dynamic dependency towards COREAON clock domain" "0,1" bitfld.long 0x0 17. " CUSTEFUSE_DYNDEP ,Dynamic dependency towards CUSTEFUSE clock domain" "0,1" textline " " bitfld.long 0x0 18. " RESERVED ," "0,1" bitfld.long 0x0 19. " MPU_DYNDEP ,Dynamic dependency towards MPU clock domain" "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x620++0x3 line.long 0x0 "CM_L4CFG_L4_CFG_CLKCTRL,This register manages the L4_CFG clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x628++0x3 line.long 0x0 "CM_L4CFG_SPINLOCK_CLKCTRL,This register manages the SPINLOCK clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x630++0x3 line.long 0x0 "CM_L4CFG_MAILBOX1_CLKCTRL,This register manages the MAILBOX1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x638++0x3 line.long 0x0 "CM_L4CFG_SAR_ROM_CLKCTRL,This register manages the SAR_ROM clocks. NOTE: This register is NOT supported on this device." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x640++0x3 line.long 0x0 "CM_L4CFG_OCP2SCP2_CLKCTRL,This register manages the OCP2SCP2 clocks and the optional clock of USB PHY." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x648++0x3 line.long 0x0 "CM_L4CFG_MAILBOX2_CLKCTRL,This register manages the MAILBOX2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x650++0x3 line.long 0x0 "CM_L4CFG_MAILBOX3_CLKCTRL,This register manages the MAILBOX3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x658++0x3 line.long 0x0 "CM_L4CFG_MAILBOX4_CLKCTRL,This register manages the MAILBOX4 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x660++0x3 line.long 0x0 "CM_L4CFG_MAILBOX5_CLKCTRL,This register manages the MAILBOX5 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x668++0x3 line.long 0x0 "CM_L4CFG_MAILBOX6_CLKCTRL,This register manages the MAILBOX6 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x670++0x3 line.long 0x0 "CM_L4CFG_MAILBOX7_CLKCTRL,This register manages the MAILBOX7 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x678++0x3 line.long 0x0 "CM_L4CFG_MAILBOX8_CLKCTRL,This register manages the MAILBOX8 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x680++0x3 line.long 0x0 "CM_L4CFG_MAILBOX9_CLKCTRL,This register manages the MAILBOX9 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x688++0x3 line.long 0x0 "CM_L4CFG_MAILBOX10_CLKCTRL,This register manages the MAILBOX10 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x690++0x3 line.long 0x0 "CM_L4CFG_MAILBOX11_CLKCTRL,This register manages the MAILBOX11 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x698++0x3 line.long 0x0 "CM_L4CFG_MAILBOX12_CLKCTRL,This register manages the MAILBOX12 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6A0++0x3 line.long 0x0 "CM_L4CFG_MAILBOX13_CLKCTRL,This register manages the MAILBOX13 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6A8++0x3 line.long 0x0 "CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL,This register manages the SPARE_SMARTREFLEX_RTC clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6B0++0x3 line.long 0x0 "CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL,This register manages the SPARE_SMARTREFLEX_SDRAM clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6B8++0x3 line.long 0x0 "CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL,This register manages the SPARE_SMARTREFLEX_WKUP clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C0++0x3 line.long 0x0 "CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL,This register manages the IO_DELAY_BLOCK clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x700++0x3 line.long 0x0 "CM_L3INSTR_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3INSTR clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_L3INSTR_L3_GICLK ,This field indicates the state of the L3INSTR_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_L3INSTR_DLL_AGING_GCLK ,This field indicates the state of the L3INSTR_DLL_AGING_GCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_L3INSTR_TS_GCLK ,This field indicates the state of the L3INSTR_TS_GCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x720++0x3 line.long 0x0 "CM_L3INSTR_L3_MAIN_2_CLKCTRL,This register manages the L3_MAIN_2 clocks. [warm reset insensitive]" bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status." "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x728++0x3 line.long 0x0 "CM_L3INSTR_L3_INSTR_CLKCTRL,This register manages the L3 INSTRUMENTATION clocks. [warm reset insensitive]" bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status." "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x740++0x3 line.long 0x0 "CM_L3INSTR_OCP_WP_NOC_CLKCTRL,This register manages the OCP_WP_NOC clocks. [warm reset insensitive]" bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status." "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x748++0x3 line.long 0x0 "CM_L3INSTR_DLL_AGING_CLKCTRL,This register manages the DLL_AGING clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x750++0x3 line.long 0x0 "CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,This register manages the CTRL_MODULE_BANDGAP clock." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--25. " CLKSEL ,Selects the divider value for generating the Thermal Sensor clock from WKUPAON_ICLK source. The divider has to be selected so as to guarantee a frequency between 1MHz and 2MHz." "0,1,2,3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree "CM_CORE__L3INIT" base ad:0x4A009300 width 34. group.byte 0x0++0x3 line.long 0x0 "CM_L3INIT_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3INIT clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_L3INIT_L3_GICLK ,This field indicates the state of the L3INIT_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_L3INIT_L4_GICLK ,This field indicates the state of the L3INIT_L4_GICLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK ,This field indicates the state of the L3INIT_USB_LFPS_TX_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 11. " CLKACTIVITY_L3INIT_48M_GFCLK ,This field indicates the state of the INIT_48M_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 12. " CLKACTIVITY_USB_DPLL_CLK ,This field indicates the state of the USB_DPLL_CLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 13. " CLKACTIVITY_USB_DPLL_HS_CLK ,This field indicates the state of the USB_DPLL_HS_CLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 14. " CLKACTIVITY_HSI_GFCLK ,This field indicates the state of the HSI_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 15. " CLKACTIVITY_MMC1_GFCLK ,This field indicates the state of the MMC1_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 16. " CLKACTIVITY_MMC2_GFCLK ,This field indicates the state of the MMC2 clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 17. " CLKACTIVITY_MLB_SHB_L3_GICLK ,This field indicates the state of the MLB_SHB_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 18. " CLKACTIVITY_MLB_SPB_L4_GICLK ,This field indicates the state of the MLB_SPB_L4_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 19. " CLKACTIVITY_MLB_SYS_L3_GFCLK ,This field indicates the state of the MLB_SYS_L3_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 20. " CLKACTIVITY_USB_OTG_SS_REF_CLK ,This field indicates the state of the USB_OTG_SS_REF_CLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 21. " CLKACTIVITY_L3INIT_480M_GFCLK ,This field indicates the state of the L3INIT_480M_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 22. " CLKACTIVITY_L3INIT_960M_GFCLK ,This field indicates the state of the L3INIT_960M_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 23. " CLKACTIVITY_L3INIT_32K_GFCLK ,This field indicates the state of the L3INIT_32K_FCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 24. " CLKACTIVITY_SATA_REF_GFCLK ,This field indicates the state of the SATA_REF_GFCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_L3INIT_STATICDEP,This register controls the static domain depedencies from L3INIT domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" bitfld.long 0x0 6.--11. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain" "0,1" bitfld.long 0x0 13. " L4PER_STATDEP ,Static dependency towards L4PER1 clock domain" "0,1" textline " " bitfld.long 0x0 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain" "0,1" bitfld.long 0x0 15. " WKUPAON_STATDEP ,Static dependency towards WKUPAON clock domain" "0,1" textline " " hexmask.long.word 0x0 16.--26. 1. " RESERVED ," bitfld.long 0x0 27. " L4PER3_STATDEP ,Static dependency towards L4PER3 clock domain" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x8++0x3 line.long 0x0 "CM_L3INIT_DYNAMICDEP,This register controls the dynamic domain depedencies from L3INIT domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "CM_L3INIT_MMC1_CLKCTRL,This register manages the MMC1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_CLK32K ,MMC optional clock control: 32K CLK" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24. " CLKSEL_SOURCE ,Selects the source of the functional clock." "0,1" textline " " bitfld.long 0x0 25.--26. " CLKSEL_DIV ,MMC1 clock divide ratio." "0,1,2,3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x30++0x3 line.long 0x0 "CM_L3INIT_MMC2_CLKCTRL,This register manages the MMC2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_CLK32K ,MMC optional clock control: 32K CLK" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24. " CLKSEL_SOURCE ,Selects the source of the functional clock." "0,1" textline " " bitfld.long 0x0 25.--26. " CLKSEL_DIV ,MMC2 clock divide ratio" "0,1,2,3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x40++0x3 line.long 0x0 "CM_L3INIT_USB_OTG_SS2_CLKCTRL,This register manages the USB_OTG_SS2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_REFCLK960M ,USB_OTG_SS optional clock control: REFCLK960M (960MHz clock)" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "CM_L3INIT_USB_OTG_SS3_CLKCTRL,This register manages the USB_OTG_SS3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "CM_L3INIT_USB_OTG_SS4_CLKCTRL,This register manages the USB_OTG_SS4 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "CM_L3INIT_MLB_SS_CLKCTRL,This register manages the MLBSS clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,This register manages the IEE1500_2_OCP clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "CM_L3INIT_SATA_CLKCTRL,This register manages the SATA clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_REF_CLK ,SATA optional clock control: REF_CLK (from SYS_CLK clock)" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "CM_PCIE_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L3INIT clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_PCIE_L3_GICLK ,This field indicates the state of the PCIE_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_PCIE_PHY_GCLK ,This field indicates the state of the PCIE_PHY_GCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_PCIE_PHY_DIV_GCLK ,This field indicates the state of the PCIE_PHY_DIV_GCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 11. " CLKACTIVITY_PCIE_REF_GFCLK ,This field indicates the state of the PCIE_REF_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 12. " CLKACTIVITY_PCIE_SYS_GFCLK ,This field indicates the state of the PCIE_SYS_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 13. " CLKACTIVITY_PCIE_32K_GFCLK ,This field indicates the state of the PCIE_32K_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "CM_PCIE_STATICDEP,This register controls the static domain depedencies from PCIE domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " DSP1_STATDEP ,Static dependency towards DSP1 clock domain" "0,1" textline " " bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain" "0,1" bitfld.long 0x0 8. " DSS_STATDEP ,Static dependency towards DSS clock domain" "0,1" textline " " bitfld.long 0x0 9. " CAM_STATDEP ,Static dependency towards CAM clock domain" "0,1" bitfld.long 0x0 10. " GPU_STATDEP ,Static dependency towards GPU clock domain" "0,1" textline " " bitfld.long 0x0 11. " SDMA_STATDEP ,Static dependency towards SDMA clock domain" "0,1" bitfld.long 0x0 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain" "0,1" textline " " bitfld.long 0x0 13. " L4PER_STATDEP ,Static dependency towards L4PER clock domain" "0,1" bitfld.long 0x0 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain" "0,1" textline " " bitfld.long 0x0 15. " RESERVED ," "0,1" bitfld.long 0x0 16. " COREAON_STATDEP ,Static dependency towards COREAON clock domain" "0,1" textline " " bitfld.long 0x0 17. " CUSTEFUSE_STATDEP ,Static dependency towards CUSTEFUSE clock domain" "0,1" bitfld.long 0x0 18. " DSP2_STATDEP ,Static dependency towards DSP2 clock domain" "0,1" textline " " bitfld.long 0x0 19. " EVE1_STATDEP ,Static dependency towards EVE1 clock domain" "0,1" bitfld.long 0x0 20. " EVE2_STATDEP ,Static dependency towards EVE2 clock domain" "0,1" textline " " bitfld.long 0x0 21. " EVE3_STATDEP ,Static dependency towards EVE3 clock domain" "0,1" bitfld.long 0x0 22. " EVE4_STATDEP ,Static dependency towards EVE4 clock domain" "0,1" textline " " bitfld.long 0x0 23. " IPU1_STATDEP ,Static dependency towards IPU1 clock domain" "0,1" bitfld.long 0x0 24. " IPU_STATDEP ,Static dependency towards IPU clock domain" "0,1" textline " " bitfld.long 0x0 25. " GMAC_STATDEP ,Static dependency towards GMAC clock domain" "0,1" bitfld.long 0x0 26. " L4PER2_STATDEP ,Static dependency towards L4PER2 clock domain" "0,1" textline " " bitfld.long 0x0 27. " L4PER3_STATDEP ,Static dependency towards L4PER3 clock domain" "0,1" bitfld.long 0x0 28. " VPE_STATDEP ,Static dependency towards VPE clock domain" "0,1" textline " " bitfld.long 0x0 29. " RESERVED ," "0,1" bitfld.long 0x0 30. " ATL_STATDEP ,Static dependency towards ATL clock domain" "0,1" textline " " bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xB0++0x3 line.long 0x0 "CM_PCIE_PCIESS1_CLKCTRL,This register manages the PCESS1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed.Note: In order to disable the APLL_PCIE, the user needs to disable PCIe_SSx (where x = 1 or 2) using the CM_PCIE_ PCIESSx_CLKCTRL[1:0] MODULEMODE registers. When PCIe_SS is disabled, the PRCM module automatically disables the APLL_PCIE. Please note that setting [1:0] MODE_SELECT bitfield to 0x0 does not disable the APLL_PCIE. ." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_32KHZ ,PCIE PHY optional clock control" "0,1" bitfld.long 0x0 9. " OPTFCLKEN_PCIEPHY_CLK ,PCIE PHY optional clock control" "0,1" textline " " bitfld.long 0x0 10. " OPTFCLKEN_PCIEPHY_CLK_DIV ,PCIE PHY optional clock control" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "CM_PCIE_PCIESS2_CLKCTRL,This register manages the PCESS2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed.Note: In order to disable the APLL_PCIE, the user needs to disable PCIe_SSx (where x = 1 or 2) using the CM_PCIE_ PCIESSx_CLKCTRL[1:0] MODULEMODE registers. When PCIe_SS is disabled, the PRCM module automatically disables the APLL_PCIE. Please note that setting [1:0] MODE_SELECT bitfield to 0x0 does not disable the APLL_PCIE. ." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_32KHZ ,PCIE PHY optional clock control" "0,1" bitfld.long 0x0 9. " OPTFCLKEN_PCIEPHY_CLK ,PCIE PHY optional clock control" "0,1" textline " " bitfld.long 0x0 10. " OPTFCLKEN_PCIEPHY_CLK_DIV ,PCIE PHY optional clock control" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0xC0++0x3 line.long 0x0 "CM_GMAC_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,WARNING: This bit field must not be programmed for SW_SLEEP or HW_AUTO for EEE mode. Controls the clock state transition of the GMAC clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_GMII_250MHZ_CLK ,This field indicates the state of the GMII_250MHZ_CLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_RGMII_5MHZ_CLK ,This field indicates the state of the RGMII_5MHZ_CLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_RMII_50MHZ_CLK ,This field indicates the state of the RMII_50MHZ_CLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 11. " CLKACTIVITY_GMAC_RFT_CLK ,This field indicates the state of the GMAC_RFT_CLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 12. " CLKACTIVITY_GMAC_MAIN_CLK ,This field indicates the state of the GMAC_MAIN_CLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xC4++0x3 line.long 0x0 "CM_GMAC_STATICDEP,This register controls the static domain depedencies from GMAC domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" hexmask.long.tbyte 0x0 6.--25. 1. " RESERVED ," textline " " bitfld.long 0x0 26. " L4PER2_STATDEP ,Static dependency towards L4PER2 clock domain" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xC8++0x3 line.long 0x0 "CM_GMAC_DYNAMICDEP,This register controls the dynamic domain depedencies from GMAC domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "CM_GMAC_GMAC_CLKCTRL,This register manages the GMAC clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24. " CLKSEL_REF ,Selects the source of the RMII_50MHZ_CLK functional clock. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 25.--27. " CLKSEL_RFT ,Selects the source of the GMAC_RFT_CLK. [warm reset insensitive]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xE0++0x3 line.long 0x0 "CM_L3INIT_OCP2SCP1_CLKCTRL,This register manages the OCP2SCP1 clocks and the optional clock of USB PHY." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xE8++0x3 line.long 0x0 "CM_L3INIT_OCP2SCP3_CLKCTRL,This register manages the OCP2SCP3 clocks and the optional clock of USB PHY." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "CM_L3INIT_USB_OTG_SS1_CLKCTRL,This register manages the USB_OTG_SS1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_REFCLK960M ,USB_OTG_SS optional clock control: REFCLK960M (960MHz clock)" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," width 0x0B tree.end tree "EMU_CM" base ad:0x4AE07A00 width 28. group.byte 0x0++0x3 line.long 0x0 "CM_EMU_CLKSTCTRL,This register enables the EMU domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain. [warm reset insensitive]" bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the EMU clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_EMU_SYS_CLK ,This field indicates the state of the EMU_SYS_CLK clock in the domain." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_EMU_DEBUGSS_CLKCTRL,This register manages the DEBUGSS clocks. [warm reset insensitive]" bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "CM_EMU_DYNAMICDEP,This register controls the dynamic domain depedencies from EMU domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " hexmask.long.tbyte 0x0 6.--23. 1. " RESERVED ," bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC++0x3 line.long 0x0 "CM_EMU_MPU_EMU_DBG_CLKCTRL,This register manages the MPU_EMU_DBG clocks. [warm reset insensitive]" bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE__OCP_SOCKET" base ad:0x4A008000 width 30. group.byte 0x0++0x3 line.long 0x0 "REVISION_CM_CORE,This register contains the IP revision code for the CM_CORE part of the PRCM" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x40++0x3 line.long 0x0 "CM_CM_CORE_PROFILING_CLKCTRL,This register manages the CM_CORE_PROFILING clocks. [warm reset insensitive]" bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "CM_CORE_DEBUG_CFG,This register is used to configure the CM_CORE's 32-bit debug output. There is one 8-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. The signals included in each block are specified in the PRCM integration specification. [warm reset insensitive]" hexmask.long.byte 0x0 0.--7. 1. " SEL0 ,Internal signal block select for debug word byte-0" hexmask.long.byte 0x0 8.--15. 1. " SEL1 ,Internal signal block select for debug word byte-1" textline " " hexmask.long.byte 0x0 16.--23. 1. " SEL2 ,Internal signal block select for debug word byte-2" hexmask.long.byte 0x0 24.--31. 1. " SEL3 ,Internal signal block select for debug word byte-3" width 0x0B tree.end tree "EVE1_PRM" base ad:0x4AE07B40 width 22. group.byte 0x0++0x3 line.long 0x0 "PM_EVE1_PWRSTCTRL,This register controls the EVE1 power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " EVE1_BANK_ONSTATE ,EVE1 state when domain is ON." "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_EVE1_PWRSTST,This register provides a status on the EVE1 domain current power state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " EVE1_BANK_STATEST ,EVE1 memory state status" "0,1,2,3" textline " " bitfld.long 0x0 6.--9. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 10.--19. 1. " RESERVED ," textline " " bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_EVE1_RSTCTRL,This register controls the release of the EVE1 sub-system resets." bitfld.long 0x0 0. " RST_EVE1_LRST ,EVE1 Local reset control" "0,1" bitfld.long 0x0 1. " RST_EVE1 ,EVE1 reset control" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "RM_EVE1_RSTST,This register logs the different reset sources of the EVE1 domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RST_EVE1_LRST ,EVE1 Local SW reset" "0,1" bitfld.long 0x0 1. " RST_EVE1 ,EVE1 SW reset status" "0,1" textline " " bitfld.long 0x0 2. " RST_EVE1_EMU ,EVE1 domain has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module" "0,1" bitfld.long 0x0 3. " RST_EVE1_EMU_REQ ,EVE1 processor has been reset due to EVE emulation reset request driven from EVE1-SS" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PM_EVE1_EVE1_WKDEP,This register controls wakeup dependency based on EVE1 service requests." bitfld.long 0x0 0. " WKUPDEP_EVE1_MPU ,Wakeup dependency from EVE1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_EVE1_IPU2 ,Wakeup dependency from EVE1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_EVE1_DSP1 ,Wakeup dependency from EVE1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_EVE1_SDMA ,Wakeup dependency from EVE1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_EVE1_IPU1 ,Wakeup dependency from EVE1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_EVE1_DSP2 ,Wakeup dependency from EVE1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " WKUPDEP_EVE1_EVE2 ,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_EVE1_EVE3 ,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_EVE1_EVE4 ,Wakeup dependency from EVE1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_EVE1_EVE1_CONTEXT,This register contains dedicated EVE1 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of EVE0_SYS_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_EVE_BANK ,Specify if memory-based context in EVE1 memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__VPE" base ad:0x4A005760 width 20. group.byte 0x0++0x3 line.long 0x0 "CM_VPE_CLKSTCTRL,This register enables the VPE domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSP clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_VPE_GCLK ,This field indicates the state of the VPE_GCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_VPE_VPE_CLKCTRL,This register manages the VPE clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "CM_VPE_STATICDEP,This register controls the static domain depedencies from VPE domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" hexmask.long.tbyte 0x0 6.--26. 1. " RESERVED ," textline " " bitfld.long 0x0 27. " L4PER3_STATDEP ,Static dependency towards L4PER3 clock domain" "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "CM_CORE__CUSTEFUSE" base ad:0x4A009600 width 38. group.byte 0x0++0x3 line.long 0x0 "CM_CUSTEFUSE_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the CUSTEFUSE clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_CUSTEFUSE_L4_GICLK ,This field indicates the state of the L4_CUSTEFUSE_GICLK clock input of the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_CUSTEFUSE_SYS_GFCLK ,This field indicates the state of the Cust_Efuse_SYS_CLK clock input of the domain. [warm reset insensitive]" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL,This register manages the CUSTEFUSE clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__EVE1" base ad:0x4A005640 width 22. group.byte 0x0++0x3 line.long 0x0 "CM_EVE1_CLKSTCTRL,This register enables the EVE domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSP clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_EVE1_GFCLK ,This field indicates the state of the EVE1_GFCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_EVE1_STATICDEP,This register controls the static domain depedencies from EVE1 domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" hexmask.long.word 0x0 6.--19. 1. " RESERVED ," textline " " bitfld.long 0x0 20. " EVE2_STATDEP ,Static dependency towards EVE2 clock domain" "0,1" bitfld.long 0x0 21. " EVE3_STATDEP ,Static dependency towards EVE3 clock domain" "0,1" textline " " bitfld.long 0x0 22. " EVE4_STATDEP ,Static dependency towards EVE4 clock domain" "0,1" hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_EVE1_EVE1_CLKCTRL,This register manages the EVE clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__EVE2" base ad:0x4A005680 width 22. group.byte 0x0++0x3 line.long 0x0 "CM_EVE2_CLKSTCTRL,This register enables the EVE domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSP clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_EVE2_GFCLK ,This field indicates the state of the EVE2_GFCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_EVE2_STATICDEP,This register controls the static domain depedencies from EVE2 domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" hexmask.long.word 0x0 6.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " EVE1_STATDEP ,Static dependency towards EVE1 clock domain" "0,1" bitfld.long 0x0 20. " RESERVED ," "0,1" textline " " bitfld.long 0x0 21. " EVE3_STATDEP ,Static dependency towards EVE3 clock domain" "0,1" bitfld.long 0x0 22. " EVE4_STATDEP ,Static dependency towards EVE4 clock domain" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_EVE2_EVE2_CLKCTRL,This register manages the EVE clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__EVE3" base ad:0x4A0056C0 width 22. group.byte 0x0++0x3 line.long 0x0 "CM_EVE3_CLKSTCTRL,This register enables the EVE domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSP clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_EVE3_GFCLK ,This field indicates the state of the EVE3_GFCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_EVE3_STATICDEP,This register controls the static domain depedencies from EVE3 domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" hexmask.long.word 0x0 6.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " EVE1_STATDEP ,Static dependency towards EVE1 clock domain" "0,1" bitfld.long 0x0 20. " EVE2_STATDEP ,Static dependency towards EVE2 clock domain" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ," "0,1" bitfld.long 0x0 22. " EVE4_STATDEP ,Static dependency towards EVE4 clock domain" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_EVE3_EVE3_CLKCTRL,This register manages the clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__EVE4" base ad:0x4A005700 width 22. group.byte 0x0++0x3 line.long 0x0 "CM_EVE4_CLKSTCTRL,This register enables the EVE domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSP clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_EVE4_GFCLK ,This field indicates the state of the EVE3_GFCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_EVE4_STATICDEP,This register controls the static domain depedencies from EVE4 domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" hexmask.long.word 0x0 6.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " EVE1_STATDEP ,Static dependency towards EVE1 clock domain" "0,1" bitfld.long 0x0 20. " EVE2_STATDEP ,Static dependency towards EVE2 clock domain" "0,1" textline " " bitfld.long 0x0 21. " EVE3_STATDEP ,Static dependency towards EVE3 clock domain" "0,1" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_EVE4_EVE4_CLKCTRL,This register manages the EVE clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," width 0x0B tree.end tree "L3INIT_PRM" base ad:0x4AE07300 width 31. group.byte 0x0++0x3 line.long 0x0 "PM_L3INIT_PWRSTCTRL,This register controls the L3INIT power state to reach upon a domain sleep transition.Note: In the L3INIT power domain OFF state is only allowed in systems where Ethernet RGMII is NOT used in the system - this is very application specific and may not be available in all TI standard software offerings." bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. " L3INIT_BANK1_RETSTATE ,L3INIT BANK1 state when domain is RETENTION." "0,1" textline " " bitfld.long 0x0 9. " L3INIT_BANK2_RETSTATE ,L3INIT BANK2 state when domain is RETENTION." "0,1" bitfld.long 0x0 10.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14.--15. " L3INIT_BANK1_ONSTATE ,L3INIT BANK1 state when domain is ON." "0,1,2,3" bitfld.long 0x0 16.--17. " L3INIT_BANK2_ONSTATE ,L3INIT BANK2 state when domain is ON." "0,1,2,3" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_L3INIT_PWRSTST,This register provides a status on the current L3INIT power domain state. [warm reset insensitive]." bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " L3INIT_BANK1_STATEST ,L3INIT BANK1 state status" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " L3INIT_BANK2_STATEST ,L3INIT BANK2 state status" "0,1,2,3" hexmask.long.word 0x0 8.--19. 1. " RESERVED ," textline " " bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_PCIESS_RSTCTRL,This register controls the release of the PCIESS local reset." bitfld.long 0x0 0. " RST_LOCAL_PCIE1 ,PCIESS1 local reset control" "0,1" bitfld.long 0x0 1. " RST_LOCAL_PCIE2 ,PCIESS2 local reset control" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "RM_PCIESS_RSTST,This register logs the different reset sources of the PCIESS domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RST_LOCAL_PCIE1 ,PCIESS1 local SW reset" "0,1" bitfld.long 0x0 1. " RST_LOCAL_PCIE2 ,PCIESS2 local SW reset" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PM_L3INIT_MMC1_WKDEP,This register controls wakeup dependency based on MMC1 service requests." bitfld.long 0x0 0. " WKUPDEP_MMC1_MPU ,Wakeup dependency from MMC1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MMC1_IPU2 ,Wakeup dependency from MMC1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MMC1_DSP1 ,Wakeup dependency from MMC1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_MMC1_SDMA ,Wakeup dependency from MMC1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MMC1_IPU1 ,Wakeup dependency from MMC1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MMC1_DSP2 ,Wakeup dependency from MMC1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MMC1_EVE1 ,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MMC1_EVE2 ,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MMC1_EVE3 ,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MMC1_EVE4 ,Wakeup dependency from MMC1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PM_L3INIT_MMC2_WKDEP,This register controls wakeup dependency based on MMC2 service requests." bitfld.long 0x0 0. " WKUPDEP_MMC2_MPU ,Wakeup dependency from MMC2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MMC2_IPU2 ,Wakeup dependency from MMC2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MMC2_DSP1 ,Wakeup dependency from MMC2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_MMC2_SDMA ,Wakeup dependency from MMC2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MMC2_IPU1 ,Wakeup dependency from MMC2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MMC2_DSP2 ,Wakeup dependency from MMC2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MMC2_EVE1 ,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MMC2_EVE2 ,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MMC2_EVE3 ,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MMC2_EVE4 ,Wakeup dependency from MMC2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PM_L3INIT_USB_OTG_SS2_WKDEP,This register controls wakeup dependency based on USB_OTG_SS2 service requests." bitfld.long 0x0 0. " WKUPDEP_USB_OTG_SS2_MPU ,Wakeup dependency from USB2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_USB_OTG_SS2_IPU2 ,Wakeup dependency from USB2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_USB_OTG_SS2_DSP1 ,Wakeup dependency from USB2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_USB_OTG_SS2_IPU1 ,Wakeup dependency from USB2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_USB_OTG_SS2_DSP2 ,Wakeup dependency from USB2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_USB_OTG_SS2_EVE1 ,Wakeup dependency from USB2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_USB_OTG_SS2_EVE2 ,Wakeup dependency from USB2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_USB_OTG_SS2_EVE3 ,Wakeup dependency from USB2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_USB_OTG_SS2_EVE4 ,Wakeup dependency from USB2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "RM_L3INIT_USB_OTG_SS2_CONTEXT,This register contains dedicated USB_OTG_SS2 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3INIT_RET_RST signal)" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "PM_L3INIT_USB_OTG_SS3_WKDEP,This register controls wakeup dependency based on USB_OTG_SS3 service requests." bitfld.long 0x0 0. " WKUPDEP_USB_OTG_SS3_MPU ,Wakeup dependency from USB3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_USB_OTG_SS3_IPU2 ,Wakeup dependency from USB3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_USB_OTG_SS3_DSP1 ,Wakeup dependency from USB3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_USB_OTG_SS3_IPU1 ,Wakeup dependency from USB3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_USB_OTG_SS3_DSP2 ,Wakeup dependency from USB3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_USB_OTG_SS3_EVE1 ,Wakeup dependency from USB3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_USB_OTG_SS3_EVE2 ,Wakeup dependency from USB3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_USB_OTG_SS3_EVE3 ,Wakeup dependency from USB3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_USB_OTG_SS3_EVE4 ,Wakeup dependency from USB3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "RM_L3INIT_USB_OTG_SS3_CONTEXT,This register contains dedicated USB_OTG_SS3 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3INIT_RET_RST signal)" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "PM_L3INIT_USB_OTG_SS4_WKDEP,This register controls wakeup dependency based on USB_OTG_SS4 service requests." bitfld.long 0x0 0. " WKUPDEP_USB_OTG_SS4_MPU ,Wakeup dependency from USB4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_USB_OTG_SS4_IPU2 ,Wakeup dependency from USB4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_USB_OTG_SS4_DSP1 ,Wakeup dependency from USB4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_USB_OTG_SS4_IPU1 ,Wakeup dependency from USB4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_USB_OTG_SS4_DSP2 ,Wakeup dependency from USB4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_USB_OTG_SS4_EVE1 ,Wakeup dependency from USB4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_USB_OTG_SS4_EVE2 ,Wakeup dependency from USB4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_USB_OTG_SS4_EVE3 ,Wakeup dependency from USB4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_USB_OTG_SS4_EVE4 ,Wakeup dependency from USB4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "RM_L3INIT_USB_OTG_SS4_CONTEXT,This register contains dedicated USB_OTG_SS4 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3INIT_RET_RST signal)" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "PM_L3INIT_SATA_WKDEP,This register controls wakeup dependency based on SATA service requests." bitfld.long 0x0 0. " WKUPDEP_SATA_MPU ,Wakeup dependency from SATA module (SWakeup signal) towards MPU + L3MAIN1 + L4CFG domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_SATA_IPU2 ,Wakeup dependency from SATA module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_SATA_DSP1 ,Wakeup dependency from SATA module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_SATA_IPU1 ,Wakeup dependency from SATA module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_SATA_DSP2 ,Wakeup dependency from SATA module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_SATA_EVE1 ,Wakeup dependency from SATA module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_SATA_EVE2 ,Wakeup dependency from SATA module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_SATA_EVE3 ,Wakeup dependency from SATA module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_SATA_EVE4 ,Wakeup dependency from SATA module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "RM_L3INIT_SATA_CONTEXT,This register contains dedicated SATA context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3INIT_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xB0++0x3 line.long 0x0 "PM_PCIE_PCIESS1_WKDEP,This register controls wakeup dependency based on PCIESS1 service requests." bitfld.long 0x0 0. " WKUPDEP_PCIESS1_MPU ,Wakeup dependency from PCIESS1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_PCIESS1_IPU2 ,Wakeup dependency from PCIESS1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_PCIESS1_DSP1 ,Wakeup dependency from PCIESS1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_PCIESS1_IPU1 ,Wakeup dependency from PCIESS1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_PCIESS1_DSP2 ,Wakeup dependency from PCIESS1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_PCIESS1_EVE1 ,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_PCIESS1_EVE2 ,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_PCIESS1_EVE3 ,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_PCIESS1_EVE4 ,Wakeup dependency from PCIESS1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "RM_PCIE_PCIESS1_CONTEXT,This register contains dedicated PCIESS1 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3INIT_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in PCIESS1_BANK memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "PM_PCIE_PCIESS2_WKDEP,This register controls wakeup dependency based on PCIESS2 service requests." bitfld.long 0x0 0. " WKUPDEP_PCIESS2_MPU ,Wakeup dependency from PCIESS2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_PCIESS2_IPU2 ,Wakeup dependency from PCIESS2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_PCIESS2_DSP1 ,Wakeup dependency from PCIESS2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_PCIESS2_IPU1 ,Wakeup dependency from PCIESS2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_PCIESS2_DSP2 ,Wakeup dependency from PCIESS2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_PCIESS2_EVE1 ,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_PCIESS2_EVE2 ,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_PCIESS2_EVE3 ,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_PCIESS2_EVE4 ,Wakeup dependency from PCIESS2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "RM_PCIE_PCIESS2_CONTEXT,This register contains dedicated PCIESS2 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3INIT_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in PCIESS1_BANK memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "PM_L3INIT_USB_OTG_SS1_WKDEP,This register controls wakeup dependency based on USB_OTG_SS1 service requests." bitfld.long 0x0 0. " WKUPDEP_USB_OTG_SS1_MPU ,Wakeup dependency from USB1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_USB_OTG_SS1_IPU2 ,Wakeup dependency from USB1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_USB_OTG_SS1_DSP1 ,Wakeup dependency from USB1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_USB_OTG_SS1_IPU1 ,Wakeup dependency from USB1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_USB_OTG_SS1_DSP2 ,Wakeup dependency from USB1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_USB_OTG_SS1_EVE1 ,Wakeup dependency from USB1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_USB_OTG_SS1_EVE2 ,Wakeup dependency from USB1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_USB_OTG_SS1_EVE3 ,Wakeup dependency from USB1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_USB_OTG_SS1_EVE4 ,Wakeup dependency from USB1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xF4++0x3 line.long 0x0 "RM_L3INIT_USB_OTG_SS1_CONTEXT,This register contains dedicated USB_OTG_SS1 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L3INIT_RET_RST signal)" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " LOSTMEM_L3INIT_BANK1 ,Specify if memory-based context in L3INIT_BANK1 memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE__CAM" base ad:0x4A009000 width 23. group.byte 0x0++0x3 line.long 0x0 "CM_CAM_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the CAM clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_VIP1_GCLK ,This field indicates the state of the VIP1_GCLK clock input of the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_VIP2_GCLK ,This field indicates the state of the VIP2_GCLK clock input of the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_VIP3_GCLK ,This field indicates the state of the VIP3_GCLK clock input of the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12. " RESERVED ," "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_CAM_STATICDEP,This register controls the static domain depedencies from CAM domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" bitfld.long 0x0 6.--11. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain" "0,1" bitfld.long 0x0 13.--18. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 19. " EVE1_STATDEP ,Static dependency towards EVE1 clock domain" "0,1" bitfld.long 0x0 20. " EVE2_STATDEP ,Static dependency towards EVE2 clock domain" "0,1" textline " " bitfld.long 0x0 21. " EVE3_STATDEP ,Static dependency towards EVE3 clock domain" "0,1" bitfld.long 0x0 22. " EVE4_STATDEP ,Static dependency towards EVE4 clock domain" "0,1" textline " " bitfld.long 0x0 23.--24. " RESERVED ," "0,1,2,3" bitfld.long 0x0 25. " GMAC_STATDEP ,Static dependency towards GMAC clock domain" "0,1" textline " " bitfld.long 0x0 26. " RESERVED ," "0,1" bitfld.long 0x0 27. " L4PER3_STATDEP ,Static dependency towards L4PER3 clock domain" "0,1" textline " " bitfld.long 0x0 28. " VPE_STATDEP ,Static dependency towards VPE clock domain" "0,1" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x20++0x3 line.long 0x0 "CM_CAM_VIP1_CLKCTRL,This register manages the VIP1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK" "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "CM_CAM_VIP2_CLKCTRL,This register manages the VIP2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for VIP between L3_ICLK and CORE_ISS_MAIN_CLK" "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "CM_CAM_VIP3_CLKCTRL,This register manages the clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24. " CLKSEL ,Selects functional clock forVIP between L3_ICLK and CORE_ISS_MAIN_CLK" "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "CM_CAM_LVDSRX_CLKCTRL,This register manages the LVDSRX clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "CM_CAM_CSI1_CLKCTRL,This register manages the CSI1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitve]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "CM_CAM_CSI2_CLKCTRL,This register manages the CSI2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," width 0x0B tree.end tree "DSS_PRM" base ad:0x4AE07100 width 21. group.byte 0x0++0x3 line.long 0x0 "PM_DSS_PWRSTCTRL,This register controls the DSS power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. " DSS_MEM_RETSTATE ,DSS_MEM state when domain is RETENTION." "0,1" textline " " hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " DSS_MEM_ONSTATE ,DSS_MEM state when domain is ON." "0,1,2,3" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_DSS_PWRSTST,This register provides a status on the current DSS power domain state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " DSS_MEM_STATEST ,DSS_MEM state status" "0,1,2,3" textline " " hexmask.long.word 0x0 6.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x20++0x3 line.long 0x0 "PM_DSS_DSS_WKDEP,This register controls wakeup dependency based on DSS service requests." bitfld.long 0x0 0. " WKUPDEP_DISPC_MPU ,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_DISPC_IPU2 ,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_DISPC_DSP1 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_DISPC_SDMA ,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_DISPC_IPU1 ,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_DISPC_DSP2 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_DISPC_EVE1 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_DISPC_EVE2 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_DISPC_EVE3 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_DISPC_EVE4 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_DSI1_A_MPU ,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_DSI1_A_IPU2 ,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_DSI1_A_DSP1 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " WKUPDEP_DSI1_A_SDMA ,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_DSI1_A_IPU1 ,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_DSI1_A_DSP2 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_DSI1_A_EVE1 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_DSI1_A_EVE2 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_DSI1_A_EVE3 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_DSI1_A_EVE4 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 20. " WKUPDEP_DSI1_B_MPU ,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 21. " WKUPDEP_DSI1_B_IPU2 ,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 22. " WKUPDEP_DSI1_B_DSP1 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 23. " WKUPDEP_DSI1_B_SDMA ,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 24. " WKUPDEP_DSI1_B_IPU1 ,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 25. " WKUPDEP_DSI1_B_DSP2 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 26. " WKUPDEP_DSI1_B_EVE1 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 27. " WKUPDEP_DSI1_B_EVE2 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 28. " WKUPDEP_DSI1_B_EVE3 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 29. " WKUPDEP_DSI1_B_EVE4 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x24++0x3 line.long 0x0 "RM_DSS_DSS_CONTEXT,This register contains dedicated DSS context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSS_RST signal)" "0,1" bitfld.long 0x0 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSS_RET_RST signal)" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " LOSTMEM_DSS_MEM ,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PM_DSS_DSS2_WKDEP,This register controls wakeup dependency based on DSS service requests." bitfld.long 0x0 0. " WKUPDEP_HDMIIRQ_MPU ,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_HDMIIRQ_IPU2 ,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_HDMIIRQ_DSP1 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_HDMIIRQ_IPU1 ,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_HDMIIRQ_DSP2 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_HDMIIRQ_EVE1 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_HDMIIRQ_EVE2 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_HDMIIRQ_EVE3 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_HDMIIRQ_EVE4 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_DSI1_C_MPU ,Wakeup dependency from DSS module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_DSI1_C_IPU2 ,Wakeup dependency from DSS module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_DSI1_C_DSP1 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " WKUPDEP_DSI1_C_SDMA ,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_DSI1_C_IPU1 ,Wakeup dependency from DSS module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_DSI1_C_DSP2 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_DSI1_C_EVE1 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_DSI1_C_EVE2 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_DSI1_C_EVE3 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_DSI1_C_EVE4 ,Wakeup dependency from DSS module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 20.--21. " RESERVED ," "0,1,2,3" bitfld.long 0x0 22. " WKUPDEP_HDMIDMA_DSP1 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 23. " WKUPDEP_HDMIDMA_SDMA ,Wakeup dependency from DSS module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 24. " RESERVED ," "0,1" textline " " bitfld.long 0x0 25. " WKUPDEP_HDMIDMA_DSP2 ,Wakeup dependency from DSS module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x34++0x3 line.long 0x0 "RM_DSS_BB2D_CONTEXT,This register contains dedicated BB2B context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSS_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_DSS_MEM ,Specify if memory-based context in DSS_MEM memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "EVE3_PRM" base ad:0x4AE07BC0 width 22. group.byte 0x0++0x3 line.long 0x0 "PM_EVE3_PWRSTCTRL,This register controls the EVE3 power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " EVE3_BANK_ONSTATE ,EVE3 state when domain is ON." "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_EVE3_PWRSTST,This register provides a status on the EVE3 domain current power state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " EVE3_BANK_STATEST ,EVE3 memory state status" "0,1,2,3" textline " " hexmask.long.word 0x0 6.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_EVE3_RSTCTRL,This register controls the release of the EVE3 sub-system resets." bitfld.long 0x0 0. " RST_EVE3_LRST ,EVE3 Local reset control" "0,1" bitfld.long 0x0 1. " RST_EVE3 ,EVE3 SW reset control" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "RM_EVE3_RSTST,This register logs the different reset sources of the EVE3 domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RST_EVE3_LRST ,EVE3 Local SW reset" "0,1" bitfld.long 0x0 1. " RST_EVE3 ,EVE3 SW reset status" "0,1" textline " " bitfld.long 0x0 2. " RST_EVE3_EMU ,EVE3 domain has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module" "0,1" bitfld.long 0x0 3. " RST_EVE3_EMU_REQ ,EVE3 processor has been reset due to EVE emulation reset request driven from EVE3-SS" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PM_EVE3_EVE3_WKDEP,This register controls wakeup dependency based on EVE3 service requests." bitfld.long 0x0 0. " WKUPDEP_EVE3_MPU ,Wakeup dependency from EVE3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_EVE3_IPU2 ,Wakeup dependency from EVE3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_EVE3_DSP1 ,Wakeup dependency from EVE3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_EVE3_SDMA ,Wakeup dependency from EVE3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_EVE3_IPU1 ,Wakeup dependency from EVE3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_EVE3_DSP2 ,Wakeup dependency from EVE3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_EVE3_EVE1 ,Wakeup dependency from EVE3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_EVE3_EVE2 ,Wakeup dependency from EVE3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " WKUPDEP_EVE3_EVE4 ,Wakeup dependency from EVE3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_EVE3_EVE3_CONTEXT,This register contains dedicated EVE3 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of EVE1_SYS_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_EVE_BANK ,Specify if memory-based context in EVE3 memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "GPU_PRM" base ad:0x4AE07200 width 20. group.byte 0x0++0x3 line.long 0x0 "PM_GPU_PWRSTCTRL,This register controls the GPU power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " GPU_MEM_ONSTATE ,GPU_MEM memory bank state when domain is ON." "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_GPU_PWRSTST,This register provides a status on the current GPU power domain state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " GPU_MEM_STATEST ,GPU_MEM memory bank state status" "0,1,2,3" textline " " hexmask.long.word 0x0 6.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x24++0x3 line.long 0x0 "RM_GPU_GPU_CONTEXT,This register contains dedicated GPU context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of GPU_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_GPU_MEM ,Specify if memory-based context in GPU_MEM memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "RTC_PRM" base ad:0x4AE07C40 width 22. group.byte 0x20++0x3 line.long 0x0 "PM_RTC_RTCSS_WKDEP,This register controls wakeup dependency based on RTCSS service requests." bitfld.long 0x0 0. " WKUPDEP_RTC_IRQ1_MPU ,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_RTC_IRQ1_IPU2 ,Wakeup dependency from RTCSS module ( alarm_swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_RTC_IRQ1_DSP1 ,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_RTC_IRQ1_IPU1 ,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_RTC_IRQ1_DSP2 ,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_RTC_IRQ1_EVE1 ,Wakeup dependency from RTCSS module ( alarm_swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_RTC_IRQ1_EVE2 ,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_RTC_IRQ1_EVE3 ,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_RTC_IRQ1_EVE4 ,Wakeup dependency from RTCSS module (alarm_swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_RTC_IRQ2_MPU ,Wakeup dependency from RTCSS module (timer_swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_RTC_IRQ2_IPU2 ,Wakeup dependency from RTCSS module (timer_swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_RTC_IRQ2_DSP1 ,Wakeup dependency from RTCSS module (timer_swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " RESERVED ," "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_RTC_IRQ2_IPU1 ,Wakeup dependency from RTCSS module (timer_swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_RTC_IRQ2_DSP2 ,Wakeup dependency from RTCSS module (timer_swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_RTC_IRQ2_EVE1 ,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_RTC_IRQ2_EVE2 ,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_RTC_IRQ2_EVE3 ,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_RTC_IRQ2_EVE4 ,Wakeup dependency from RTCSS module (timer_swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_RTC_RTCSS_CONTEXT,This register contains dedicated RTCSS context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of L4PER_RST signal)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE__RESTORE" base ad:0x4A009E00 width 39. group.byte 0x18++0x3 line.long 0x0 "CM_L3MAIN1_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_L3MAIN1_CLKSTCTRL register." group.byte 0x20++0x3 line.long 0x0 "CM_L4CFG_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,See CM_L4CFG_CLKSTCTRLregister." group.byte 0x28++0x3 line.long 0x0 "CM_L4PER_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_L4PER_CLKSTCTRL register." group.byte 0x2C++0x3 line.long 0x0 "CM_L3INIT_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_L3INIT_CLKSTCTRL register." group.byte 0x30++0x3 line.long 0x0 "CM_L3INSTR_L3_MAIN_2_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" hexmask.long 0x0 0.--31. 1. " RESTORE ,See CM_L3INSTR_L3_MAIN_3_CLKCTRL register." group.byte 0x34++0x3 line.long 0x0 "CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_L3INSTR_L3_INSTR_CLKCTRL register." group.byte 0x38++0x3 line.long 0x0 "CM_L3INSTR_OCP_WP_NOC_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_L3INSTR_OCP_WP_NOC_CLKCTRL register." group.byte 0x3C++0x3 line.long 0x0 "CM_CM_CORE_PROFILING_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_CM_CORE_PROFILING_CLKCTRL register." group.byte 0x48++0x3 line.long 0x0 "CM_L3MAIN1_DYNAMICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_L3MAIN1_DYNAMICDEP register." group.byte 0x58++0x3 line.long 0x0 "CM_L4CFG_DYNAMICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_L4CFG_DYNAMICDEP register." group.byte 0x5C++0x3 line.long 0x0 "CM_L4PER_DYNAMICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_L4PER_DYNAMICDEP register." group.byte 0x60++0x3 line.long 0x0 "CM_COREAON_IO_SRCOMP_CLKCTRL_RESTORE,Second address map for register CM_COREAON_IO_SRCOMP_CLKCTRL. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,See CCM_DYN_DEP_PRESCAL register." group.byte 0x6C++0x3 line.long 0x0 "CM_DMA_STATICDEP_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_DMA_STATICDEP register." width 0x0B tree.end tree "EVE2_PRM" base ad:0x4AE07B80 width 22. group.byte 0x0++0x3 line.long 0x0 "PM_EVE2_PWRSTCTRL,This register controls the EVE2 power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " EVE2_BANK_ONSTATE ,EVE2 state when domain is ON." "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_EVE2_PWRSTST,This register provides a status on the EVE2 domain current power state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " EVE2_BANK_STATEST ,EVE2 memory state status" "0,1,2,3" textline " " hexmask.long.word 0x0 6.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_EVE2_RSTCTRL,This register controls the release of the EVE2 sub-system resets." bitfld.long 0x0 0. " RST_EVE2_LRST ,EVE2 Local reset control" "0,1" bitfld.long 0x0 1. " RST_EVE2 ,EVE2 SW reset control" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "RM_EVE2_RSTST,This register logs the different reset sources of the EVE2 domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RST_EVE2_LRST ,EVE2 Local SW reset" "0,1" bitfld.long 0x0 1. " RST_EVE2 ,EVE2 SW reset status" "0,1" textline " " bitfld.long 0x0 2. " RST_EVE2_EMU ,EVE2 domain has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module" "0,1" bitfld.long 0x0 3. " RST_EVE2_EMU_REQ ,EVE2 processor has been reset due to EVE emulation reset request driven from EVE2-SS" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PM_EVE2_EVE2_WKDEP,This register controls wakeup dependency based on EVE2 service requests." bitfld.long 0x0 0. " WKUPDEP_EVE2_MPU ,Wakeup dependency from EVE2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_EVE2_IPU2 ,Wakeup dependency from EVE2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_EVE2_DSP1 ,Wakeup dependency from EVE2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_EVE2_SDMA ,Wakeup dependency from EVE2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_EVE2_IPU1 ,Wakeup dependency from EVE2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_EVE2_DSP2 ,Wakeup dependency from EVE2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_EVE2_EVE1 ,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_EVE2_EVE3 ,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_EVE2_EVE4 ,Wakeup dependency from EVE2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_EVE2_EVE2_CONTEXT,This register contains dedicated EVE2 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of EVE1_SYS_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_EVE_BANK ,Specify if memory-based context in EVE2 memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "CKGEN_PRM" base ad:0x4AE06100 width 39. group.byte 0x0++0x3 line.long 0x0 "CM_CLKSEL_SYSCLK1,Select the SYS CLK for SYSCLK1_32K_CLK. [warm reset insensitive]" bitfld.long 0x0 0. " CLKSEL ,Selects the divider value" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "CM_CLKSEL_WKUPAON,Control the functional clock source of WKUPAON, PRM and Smart Reflex functional clock." bitfld.long 0x0 0. " CLKSEL ,Select the clock source for WKUPAON_ICLK clock" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "CM_CLKSEL_ABE_PLL_REF,Control the source of the reference clock for DPLL_ABE" bitfld.long 0x0 0. " CLKSEL ,Select the source for the DPLL_ABE reference clock." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "CM_CLKSEL_SYS,ROM code sets the SYS_CLK configuration corresponding to the frequency of SYS_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " SYS_CLKSEL ,System clock input selection." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "CM_CLKSEL_ABE_PLL_BYPAS,Control the source of the bypass clock for DPLL_ABE" bitfld.long 0x0 0. " CLKSEL ,Control the source of the bypass clock for DPLL_ABE" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "CM_CLKSEL_ABE_PLL_SYS,Control the source of the SYS clock for DPLL_ABE" bitfld.long 0x0 0. " CLKSEL ,Select the SYS clock for the DPLL_ABE reference and bypass clock." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "CM_CLKSEL_ABE_24M,Select the ABE_24M_FCLK for TIMERS subsystems. [warm reset insensitive]" bitfld.long 0x0 0. " CLKSEL ,Selects the divider value" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_CLKSEL_ABE_SYS,Select the SYS CLK for IPU subsystems. [warm reset insensitive]" bitfld.long 0x0 0. " CLKSEL ,Selects the divider value" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "CM_CLKSEL_HDMI_MCASP_AUX,Select the HDMI_CLK for MCASP subsystems. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "CM_CLKSEL_HDMI_TIMER,Select the HDMI_CLK for TIMER subsystems. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "CM_CLKSEL_MCASP_SYS,Select the SYS CLK for ABE_24M_FCLK. [warm reset insensitive]" bitfld.long 0x0 0. " CLKSEL ,Selects the divider value" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "CM_CLKSEL_MLBP_MCASP,Select the MLBP_CLK for MCASP subsystems. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "CM_CLKSEL_MLB_MCASP,Select the MLB_CLK for MCASP subsystems. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX,Select the PER_ABE_X1_GFCLK_CLK for MCASP subsystems. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "CM_CLKSEL_TIMER_SYS,Select the SYS CLK for TIMERS subsystems. [warm reset insensitive]" bitfld.long 0x0 0. " CLKSEL ,Selects the divider value" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "CM_CLKSEL_VIDEO1_MCASP_AUX,Select the VIDEO1_CLK for MCASP subsystems. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "CM_CLKSEL_VIDEO1_TIMER,Select the VIDEO1_CLK for TIMER subsystems. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "CM_CLKSEL_VIDEO2_MCASP_AUX,Select the VIDEO2_CLK for MCASP subsystems. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "CM_CLKSEL_VIDEO2_TIMER,Select the VIDEO2_CLK for TIMER subsystems. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "CM_CLKSEL_CLKOUTMUX0,Control the source of the CLKOUTMUX0_CLK." bitfld.long 0x0 0.--4. " CLKSEL ,Select the source clock for CLKOUTMUX0_CLK.0x15-0x1F: RESERVED enum=SEL_DPLL_EVE_CLKOUT ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "CM_CLKSEL_CLKOUTMUX1,Control the source of the CLKOUTMUX1_CLK." bitfld.long 0x0 0.--4. " CLKSEL ,Select the source clock for CLKOUTMUX1_CLK.0x16-0x1F: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "CM_CLKSEL_CLKOUTMUX2,Control the source of the CLKOUTMUX2_CLK." bitfld.long 0x0 0.--4. " CLKSEL ,Select the source clock for CLKOUTMUX2_CLK.0x16-0x1F: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "CM_CLKSEL_HDMI_PLL_SYS,Control the source of the SYS clock for DPLL_HDMI" bitfld.long 0x0 0. " CLKSEL ,Select the SYS clock for the DPLL_HDMI" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "CM_CLKSEL_VIDEO1_PLL_SYS,Control the source of the SYS clock for DPLL_VIDEO1" bitfld.long 0x0 0. " CLKSEL ,Select the SYS clock for the DPLL_VIDEO1." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "CM_CLKSEL_VIDEO2_PLL_SYS,Control the source of the SYS clock for DPLL_VIDEO1" bitfld.long 0x0 0. " CLKSEL ,Select the SYS clock for the DPLL_VIDEO2." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "CM_CLKSEL_ABE_CLK_DIV,Select the ABE_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "CM_CLKSEL_ABE_GICLK_DIV,Select the ABE_GICLK. [warm reset insensitive]" bitfld.long 0x0 0. " CLKSEL ,Selects the divider value" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "CM_CLKSEL_AESS_FCLK_DIV,Select the AESS_FCLK. [warm reset insensitive]" bitfld.long 0x0 0. " CLKSEL ,Selects the divider value" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "CM_CLKSEL_EVE_CLK,Control the source of the EVE_CLK for EVE1, EVE2, EVE3, EVE4" bitfld.long 0x0 0. " CLKSEL ,Select the EVE_CLK for EVE1, EVE2, EVE3, EVE4" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX,Select the USB_OTG_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX,Select the CORE_DPLL_OUT_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "CM_CLKSEL_DSP_GFCLK_CLKOUTMUX,Select the DSP_GFCLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX,Select the EMIF_PHY_GCLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "CM_CLKSEL_EMU_CLK_CLKOUTMUX,Select the EMU_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX,Select the FUNC_96M_AON_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX,Select the GMAC_250M_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "CM_CLKSEL_GPU_GCLK_CLKOUTMUX,Select the GPU_GCLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "CM_CLKSEL_HDMI_CLK_CLKOUTMUX,Select the HDMI_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "CM_CLKSEL_IVA_GCLK_CLKOUTMUX,Select the IVA_GCLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xAC++0x3 line.long 0x0 "CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX,Select the L3INIT_480M_GFCLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xB0++0x3 line.long 0x0 "CM_CLKSEL_MPU_GCLK_CLKOUTMUX,Select the MPU_GCLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "CM_CLKSEL_PCIE1_CLK_CLKOUTMUX,Select the PCIE1_DCLK, where APLL_PCIE_M2_CLK is the source clock of PCIE1_DCLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "CM_CLKSEL_PCIE2_CLK_CLKOUTMUX,Select the PCIE2_DCLK, where PCIE_M2_CLK is the source clock of PCIE2_DCLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX,Select the PER_ABE_X1_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xC0++0x3 line.long 0x0 "CM_CLKSEL_SATA_CLK_CLKOUTMUX,Select the SATA_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xC4++0x3 line.long 0x0 "CM_CLKSEL_OSC_32K_CLK_CLKOUTMUX,Select the OSC_32K_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xC8++0x3 line.long 0x0 "CM_CLKSEL_SYS_CLK1_CLKOUTMUX,Select the SYS_CLK1. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xCC++0x3 line.long 0x0 "CM_CLKSEL_SYS_CLK2_CLKOUTMUX,Select the SYS_CLK2. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX,Select the VIDEO1_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xD4++0x3 line.long 0x0 "CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX,Select the VIDEO2_CLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xD8++0x3 line.long 0x0 "CM_CLKSEL_ABE_LP_CLK,Select the ABE_LP_CLK. [warm reset insensitive]" bitfld.long 0x0 0. " CLKSEL ,Selects the divider value" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "CM_CLKSEL_EVE_GFCLK_CLKOUTMUX,Select the EVE_GFCLK. [warm reset insensitive]" bitfld.long 0x0 0.--2. " CLKSEL ,Selects the divider value" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," width 0x0B tree.end tree "CAM_PRM" base ad:0x4AE07000 width 21. group.byte 0x0++0x3 line.long 0x0 "PM_CAM_PWRSTCTRL,This register controls the CAM power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " VIP_BANK_ONSTATE ,VIP_BANK memory state when domain is ON." "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_CAM_PWRSTST,This register provides a status on the current CAM power domain state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " VIP_BANK_STATEST ,VIP_BANK memory state status" "0,1,2,3" textline " " hexmask.long.word 0x0 6.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x20++0x3 line.long 0x0 "PM_CAM_VIP1_WKDEP,This register controls wakeup dependency based on VIP1 service requests." bitfld.long 0x0 0. " WKUPDEP_VIP1_MPU ,Wakeup dependency from VIP1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_VIP1_IPU2 ,Wakeup dependency from vip1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_VIP1_DSP1 ,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_VIP1_IPU1 ,Wakeup dependency from VIP1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_VIP1_DSP2 ,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_VIP1_EVE1 ,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_VIP1_EVE2 ,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_VIP1_EVE3 ,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_VIP1_EVE4 ,Wakeup dependency from VIP1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_CAM_VIP1_CONTEXT,This register contains dedicated VIP1 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CAM_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_VIP_BANK ,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PM_CAM_VIP2_WKDEP,This register controls wakeup dependency based on VIP2 service requests." bitfld.long 0x0 0. " WKUPDEP_VIP2_MPU ,Wakeup dependency from VIP2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_VIP2_IPU2 ,Wakeup dependency from VIP2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_VIP2_DSP1 ,Wakeup dependency from VIP2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_VIP2_IPU1 ,Wakeup dependency from VIP2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_VIP2_DSP2 ,Wakeup dependency from VIP1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_VIP2_EVE1 ,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_VIP2_EVE2 ,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_VIP2_EVE3 ,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_VIP2_EVE4 ,Wakeup dependency from VIP2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "RM_CAM_VIP2_CONTEXT,This register contains dedicated VIP2 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CAM_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_VIP_BANK ,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PM_CAM_VIP3_WKDEP,This register controls wakeup dependency based on VIP3 service requests." bitfld.long 0x0 0. " WKUPDEP_VIP3_MPU ,Wakeup dependency from VIP3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_VIP3_IPU2 ,Wakeup dependency from vip3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_VIP3_DSP1 ,Wakeup dependency from VIP3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_VIP3_IPU1 ,Wakeup dependency from VIP3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_VIP3_DSP2 ,Wakeup dependency from VIP3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_VIP3_EVE1 ,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_VIP3_EVE2 ,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_VIP3_EVE3 ,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_VIP3_EVE4 ,Wakeup dependency from VIP3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "RM_CAM_VIP3_CONTEXT,This register contains dedicated VIP3 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CAM_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_VIP_BANK ,Specify if memory-based context in VIP_MEM memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE__L4PER" base ad:0x4A009700 width 29. group.byte 0x0++0x3 line.long 0x0 "CM_L4PER_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4PER clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_L4PER_L3_GICLK ,This field indicates the state of the L4PER_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_TIMER10_GFCLK ,This field indicates the state of the DMT10_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_TIMER11_GFCLK ,This field indicates the state of the DMT11_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 11. " CLKACTIVITY_TIMER2_GFCLK ,This field indicates the state of the DMT2_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 12. " CLKACTIVITY_TIMER3_GFCLK ,This field indicates the state of the DMT3_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 13. " CLKACTIVITY_TIMER4_GFCLK ,This field indicates the state of the DMT4_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 14. " CLKACTIVITY_TIMER9_GFCLK ,This field indicates the state of the DMT9_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 15. " CLKACTIVITY_UART1_GFCLK ,This field indicates the state of the UART1_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 16. " CLKACTIVITY_UART2_GFCLK ,This field indicates the state of the UART2_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 17. " CLKACTIVITY_UART3_GFCLK ,This field indicates the state of the UART3_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 18. " CLKACTIVITY_UART4_GFCLK ,This field indicates the state of the UART4_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 19. " CLKACTIVITY_PER_12M_GFCLK ,This field indicates the state of the PER_12M_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 20. " CLKACTIVITY_PER_48M_GFCLK ,This field indicates the state of the PER_48M_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 21. " CLKACTIVITY_PER_96M_GFCLK ,This field indicates the state of the PER_96M_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 22. " CLKACTIVITY_MMC3_GFCLK ,This field indicates the state of the MMC3_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 23. " CLKACTIVITY_MMC4_GFCLK ,This field indicates the state of the MMC4_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 24. " CLKACTIVITY_GPIO_GFCLK ,This field indicates the state of the GPIO_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 25. " CLKACTIVITY_PER_192M_GFCLK ,This field indicates the state of the PER_192M_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 26. " CLKACTIVITY_UART5_GFCLK ,This field indicates the state of the UART5_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 27. " CLKACTIVITY_L4PER_32K_GFCLK ,This field indicates the state of the L4PER_32K_FCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x8++0x3 line.long 0x0 "CM_L4PER_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--2. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " IPU_DYNDEP ,Dynamic dependency towards IPU clock domain" "0,1" textline " " bitfld.long 0x0 4.--6. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " L3INIT_DYNDEP ,Dynamic dependency towards L3INIT clock domain" "0,1" textline " " bitfld.long 0x0 8. " DSS_DYNDEP ,Dynamic dependency towards DSS clock domain" "0,1" bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 14. " L4SEC_DYNDEP ,Dynamic dependency towards L4SEC clock domain" "0,1" hexmask.long.word 0x0 15.--23. 1. " RESERVED ," textline " " bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC++0x3 line.long 0x0 "CM_L4PER2_L4_PER2_CLKCTRL,This register manages the L4_PER2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "CM_L4PER3_L4_PER3_CLKCTRL,This register manages the L4_PER3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "CM_L4PER2_PRUSS1_CLKCTRL,This register manages the PRU-ICSS clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_L4PER2_PRUSS2_CLKCTRL,This register manages the PRU-ICSS clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "CM_L4PER_TIMER10_CLKCTRL,This register manages the TIMER10 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x30++0x3 line.long 0x0 "CM_L4PER_TIMER11_CLKCTRL,This register manages the TIMER11 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x38++0x3 line.long 0x0 "CM_L4PER_TIMER2_CLKCTRL,This register manages the TIMER2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40++0x3 line.long 0x0 "CM_L4PER_TIMER3_CLKCTRL,This register manages the TIMER3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x48++0x3 line.long 0x0 "CM_L4PER_TIMER4_CLKCTRL,This register manages the TIMER4 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "CM_L4PER_TIMER9_CLKCTRL,This register manages the TIMER9 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x58++0x3 line.long 0x0 "CM_L4PER_ELM_CLKCTRL,This register manages the ELM clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "CM_L4PER_GPIO2_CLKCTRL,This register manages the GPIO2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_DBCLK ,Optional functional clock control." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "CM_L4PER_GPIO3_CLKCTRL,This register manages the GPIO3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_DBCLK ,Optional functional clock control." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "CM_L4PER_GPIO4_CLKCTRL,This register manages the GPIO4 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_DBCLK ,Optional functional clock control." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "CM_L4PER_GPIO5_CLKCTRL,This register manages the GPIO5 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_DBCLK ,Optional functional clock control." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "CM_L4PER_GPIO6_CLKCTRL,This register manages the GPIO6 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_DBCLK ,Optional functional clock control." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CM_L4PER_HDQ1W_CLKCTRL,This register manages the HDQ1W clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "CM_L4PER2_PWMSS2_CLKCTRL,This register manages the PWMSS1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "CM_L4PER2_PWMSS3_CLKCTRL,This register manages the PWMSS2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "CM_L4PER_I2C1_CLKCTRL,This register manages the I2C1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "CM_L4PER_I2C2_CLKCTRL,This register manages the I2C2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB0++0x3 line.long 0x0 "CM_L4PER_I2C3_CLKCTRL,This register manages the I2C3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "CM_L4PER_I2C4_CLKCTRL,This register manages the I2C4 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC0++0x3 line.long 0x0 "CM_L4PER_L4_PER1_CLKCTRL,This register manages the L4_PER1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC4++0x3 line.long 0x0 "CM_L4PER2_PWMSS1_CLKCTRL,This register manages the PWMSS0 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC8++0x3 line.long 0x0 "CM_L4PER3_TIMER13_CLKCTRL,This register manages the TIMER13 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x3 line.long 0x0 "CM_L4PER3_TIMER14_CLKCTRL,This register manages the TIMER14 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "CM_L4PER3_TIMER15_CLKCTRL,This register manages the TIMER15 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xF0++0x3 line.long 0x0 "CM_L4PER_MCSPI1_CLKCTRL,This register manages the McSPI1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xF8++0x3 line.long 0x0 "CM_L4PER_MCSPI2_CLKCTRL,This register manages the McSPI2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "CM_L4PER_MCSPI3_CLKCTRL,This register manages the McSPI3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "CM_L4PER_MCSPI4_CLKCTRL,This register manages the McSPI4 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "CM_L4PER_GPIO7_CLKCTRL,This register manages the GPIO7 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_DBCLK ,Optional functional clock control." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x118++0x3 line.long 0x0 "CM_L4PER_GPIO8_CLKCTRL,This register manages the GPIO8 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_DBCLK ,Optional functional clock control." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x120++0x3 line.long 0x0 "CM_L4PER_MMC3_CLKCTRL,This register manages the MMC3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_CLK32K ,MMC optional clock control: 32K CLK" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL_MUX ,Select the clock for the MMC from DPLL_PER." "0,1" bitfld.long 0x0 25.--26. " CLKSEL_DIV ,Selects the divider value" "0,1,2,3" textline " " bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x128++0x3 line.long 0x0 "CM_L4PER_MMC4_CLKCTRL,This register manages the MMC4 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_CLK32K ,MMC optional clock control: 32K CLK" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL_MUX ,Select the clock for the MMC from DPLL_PER." "0,1" bitfld.long 0x0 25.--26. " CLKSEL_DIV ,Selects the divider value" "0,1,2,3" textline " " bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x130++0x3 line.long 0x0 "CM_L4PER3_TIMER16_CLKCTRL,This register manages the TIMER16 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x138++0x3 line.long 0x0 "CM_L4PER2_QSPI_CLKCTRL,This register manages the QSPI clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL_SOURCE ,Selects the source of the functional clock." "0,1" bitfld.long 0x0 25.--26. " CLKSEL_DIV ,QSPI clock divide ratio." "0,1,2,3" textline " " bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x140++0x3 line.long 0x0 "CM_L4PER_UART1_CLKCTRL,This register manages the UART1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x148++0x3 line.long 0x0 "CM_L4PER_UART2_CLKCTRL,This register manages the UART2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x150++0x3 line.long 0x0 "CM_L4PER_UART3_CLKCTRL,This register manages the UART3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x158++0x3 line.long 0x0 "CM_L4PER_UART4_CLKCTRL,This register manages the UART4 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x160++0x3 line.long 0x0 "CM_L4PER2_MCASP2_CLKCTRL,This register manages the McASP2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 22.--23. " CLKSEL_AUX_CLK ,Selects the source of the AUX clock" "0,1,2,3" bitfld.long 0x0 24.--27. " CLKSEL_AHCLKX ,Selects reference clock for AHCLKX enum=SEL_FUNC_24M_GFCLK . enum=SEL_XREF_CLK3 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " CLKSEL_AHCLKR ,Selects reference clock for AHCLKR enum=SEL_FUNC_24M_GFCLK . enum=SEL_XREF_CLK3 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x168++0x3 line.long 0x0 "CM_L4PER2_MCASP3_CLKCTRL,This register manages the McASP3 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 22.--23. " CLKSEL_AUX_CLK ,Selects the source of the AUX clock" "0,1,2,3" bitfld.long 0x0 24.--27. " CLKSEL_AHCLKX ,Selects reference clock for AHCLKX enum=SEL_FUNC_24M_GFCLK . enum=SEL_XREF_CLK3 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x170++0x3 line.long 0x0 "CM_L4PER_UART5_CLKCTRL,This register manages the UART5 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x178++0x3 line.long 0x0 "CM_L4PER2_MCASP5_CLKCTRL,This register manages the McASP5 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 22.--23. " CLKSEL_AUX_CLK ,Selects the source of the AUX clock" "0,1,2,3" bitfld.long 0x0 24.--27. " CLKSEL_AHCLKX ,Selects reference clock for AHCLKX enum=SEL_ATL_CLK3 . enum=SEL_XREF_CLK3 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x180++0x3 line.long 0x0 "CM_L4SEC_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4PER clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_L4SEC_L3_GICLK ,This field indicates the state of the L3_SECURE_GICLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x184++0x3 line.long 0x0 "CM_L4SEC_STATICDEP,This register controls the static domain depedencies from L4SEC domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" hexmask.long.byte 0x0 6.--12. 1. " RESERVED ," textline " " bitfld.long 0x0 13. " L4PER_STATDEP ,Static dependency towards L4PER1 clock domain" "0,1" hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x188++0x3 line.long 0x0 "CM_L4SEC_DYNAMICDEP,This register controls the dynamic domain depedencies from L4SEC domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x190++0x3 line.long 0x0 "CM_L4PER2_MCASP8_CLKCTRL,This register manages the McASP8 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 22.--23. " CLKSEL_AUX_CLK ,Selects the source of the AUX clock" "0,1,2,3" bitfld.long 0x0 24.--27. " CLKSEL_AHCLKX ,Selects reference clock for AHCLKX enum=SEL_FUNC_24M_GFCLK . enum=SEL_XREF_CLK3 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x198++0x3 line.long 0x0 "CM_L4PER2_MCASP4_CLKCTRL,This register manages the McASP4 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 22.--23. " CLKSEL_AUX_CLK ,Selects the source of the AUX clock" "0,1,2,3" bitfld.long 0x0 24.--27. " CLKSEL_AHCLKX ,Selects reference clock for AHCLKX enum=SEL_FUNC_24M_GFCLK . enum=SEL_XREF_CLK3 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1A0++0x3 line.long 0x0 "CM_L4SEC_AES1_CLKCTRL,This register manages the AES1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1A8++0x3 line.long 0x0 "CM_L4SEC_AES2_CLKCTRL,This register manages the AES2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1B0++0x3 line.long 0x0 "CM_L4SEC_DES3DES_CLKCTRL,This register manages the DES3DES clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1B8++0x3 line.long 0x0 "CM_L4SEC_FPKA_CLKCTRL,This register manages the FPKA clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1C0++0x3 line.long 0x0 "CM_L4SEC_RNG_CLKCTRL,This register manages the RNG clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1C8++0x3 line.long 0x0 "CM_L4SEC_SHA2MD51_CLKCTRL,This register manages the SHA2MD51 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1D0++0x3 line.long 0x0 "CM_L4PER2_UART7_CLKCTRL,This register manages the UART7 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x1D8++0x3 line.long 0x0 "CM_L4SEC_DMA_CRYPTO_CLKCTRL,This register manages the DMA_CRYPTO clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x1E0++0x3 line.long 0x0 "CM_L4PER2_UART8_CLKCTRL,This register manages the UART8 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x1E8++0x3 line.long 0x0 "CM_L4PER2_UART9_CLKCTRL,This register manages the UART9 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "CM_L4PER2_DCAN2_CLKCTRL,This register manages the DCAN2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1F8++0x3 line.long 0x0 "CM_L4SEC_SHA2MD52_CLKCTRL,This register manages the SHA2MD52 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1FC++0x3 line.long 0x0 "CM_L4PER2_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4PER clock domain." "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3.--6. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " CLKACTIVITY_ICSS_CLK ,This field indicates the state of the ICSS_CLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_UART7_GFCLK ,This field indicates the state of the UART7_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_UART8_GFCLK ,This field indicates the state of the UART8_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 11. " CLKACTIVITY_UART9_GFCLK ,This field indicates the state of the UART9_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 12. " CLKACTIVITY_QSPI_GFCLK ,This field indicates the state of the QSPI_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 13. " CLKACTIVITY_PER_192M_GFCLK ,This field indicates the state of the PER_192M_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 14. " CLKACTIVITY_ICSS_IEP_CLK ,This field indicates the state of the ICSS_IEP_CLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 15. " CLKACTIVITY_DCAN2_SYS_CLK ,This field indicates the state of the DCAN2_SYS_CLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 16. " CLKACTIVITY_L4PER2_L3_GICLK ,This field indicates the state of the L4PER2_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 17. " CLKACTIVITY_MCASP2_AHCLKX ,This field indicates the state of the MCASP2_AHCLKX clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 18. " CLKACTIVITY_MCASP2_AHCLKR ,This field indicates the state of the MCASP2_AHCLKR clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 19. " CLKACTIVITY_MCASP2_AUX_GFCLK ,This field indicates the state of the MCASP2_AUX_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 20. " CLKACTIVITY_MCASP3_AHCLKX ,This field indicates the state of the MCASP3_AHCLKX clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 21. " CLKACTIVITY_MCASP3_AUX_GFCLK ,This field indicates the state of the MCASP3_AUX_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 22. " CLKACTIVITY_MCASP4_AHCLKX ,This field indicates the state of the MCASP4_AHCLKX clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 23. " CLKACTIVITY_MCASP4_AUX_GFCLK ,This field indicates the state of the MCASP4_AUX_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 24. " CLKACTIVITY_MCASP5_AUX_GFCLK ,This field indicates the state of the MCASP5_AUX_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 25. " CLKACTIVITY_MCASP5_AHCLKX ,This field indicates the state of the MCASP5_AHCLKX clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 26. " CLKACTIVITY_MCASP6_AHCLKX ,This field indicates the state of the MCASP6_AUX_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 27. " CLKACTIVITY_MCASP6_AUX_GFCLK ,This field indicates the state of the MCASP6_AUX_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 28. " CLKACTIVITY_MCASP7_AHCLKX ,This field indicates the state of the MCASP7_AHCLKX clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 29. " CLKACTIVITY_MCASP7_AUX_GFCLK ,This field indicates the state of the MCASP7_AUX_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 30. " CLKACTIVITY_MCASP8_AHCLKX ,This field indicates the state of the MCASP8_AHCLKX clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 31. " CLKACTIVITY_MCASP8_AUX_GFCLK ,This field indicates the state of the MCASP8_AUX_GFCLK clock in the domain. [warm reset insensitive]" "0,1" group.byte 0x200++0x3 line.long 0x0 "CM_L4PER2_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER2 domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--2. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " IPU_DYNDEP ,Dynamic dependency towards IPU clock domain" "0,1" textline " " bitfld.long 0x0 4.--5. " RESERVED ," "0,1,2,3" bitfld.long 0x0 6. " ATL_DYNDEP ,Dynamic Dependency towards ATL clock domain" "0,1" textline " " bitfld.long 0x0 7. " L3INIT_DYNDEP ,Dynamic dependency towards L3INIT clock domain" "0,1" bitfld.long 0x0 8.--11. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12. " L4CFG_DYNDEP ,Dynamic dependency towards L4CFG clock domain" "0,1" hexmask.long.word 0x0 13.--21. 1. " RESERVED ," textline " " bitfld.long 0x0 22. " GMAC_DYNDEP ,Dynamic dependency towards GMAC clock domain" "0,1" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x204++0x3 line.long 0x0 "CM_L4PER2_MCASP6_CLKCTRL,This register manages the McASP6 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 22.--23. " CLKSEL_AUX_CLK ,Selects the source of the AUX clock" "0,1,2,3" bitfld.long 0x0 24.--27. " CLKSEL_AHCLKX ,Selects reference clock for AHCLKX enum=SEL_ATL_CLK3 . enum=SEL_XREF_CLK3 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x208++0x3 line.long 0x0 "CM_L4PER2_MCASP7_CLKCTRL,This register manages the McASP7 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 22.--23. " CLKSEL_AUX_CLK ,Selects the source of the AUX clock" "0,1,2,3" bitfld.long 0x0 24.--27. " CLKSEL_AHCLKX ,Selects reference clock for AHCLKX enum=SEL_ATL_CLK3 . enum=SEL_XREF_CLK3 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x20C++0x3 line.long 0x0 "CM_L4PER2_STATICDEP,This register controls the static domain depedencies from L4PER2 domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0. " IPU2_STATDEP ,Static dependency towards IPU2 clock domain" "0,1" bitfld.long 0x0 1. " DSP1_STATDEP ,Static dependency towards DSP1 clock domain" "0,1" textline " " bitfld.long 0x0 2.--4. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" textline " " hexmask.long.word 0x0 6.--17. 1. " RESERVED ," bitfld.long 0x0 18. " DSP2_STATDEP ,Static dependency towards DSP2 clock domain" "0,1" textline " " bitfld.long 0x0 19.--22. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 23. " IPU1_STATDEP ,Static dependency towards IPU1 clock domain" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "CM_L4PER3_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the L4PER clock domain." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8. " CLKACTIVITY_L4PER3_L3_GICLK ,This field indicates the state of the L4PER2_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 9. " CLKACTIVITY_TIMER13_GFCLK ,This field indicates the state of the DMT13_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 10. " CLKACTIVITY_TIMER14_GFCLK ,This field indicates the state of the DMT14_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 11. " CLKACTIVITY_TIMER15_GFCLK ,This field indicates the state of the DMT15_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 12. " CLKACTIVITY_TIMER16_GFCLK ,This field indicates the state of the DMT16_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "CM_L4PER3_DYNAMICDEP,This register controls the dynamic domain depedencies from L4PER3 domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--2. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " IPU_DYNDEP ,Dynamic dependency towards IPU clock domain" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " L3INIT_DYNDEP ,Dynamic dependency towards L3INIT clock domain" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " CAM_DYNDEP ,Dynamic dependency towards CAM clock domain" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " L4CFG_DYNDEP ,Dynamic dependency towards L4CFG clock domain" "0,1" textline " " hexmask.long.word 0x0 13.--22. 1. " RESERVED ," bitfld.long 0x0 23. " RTC_DYNDEP ,Dynamic dependency towards RTC clock domain" "0,1" textline " " bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " VPE_DYNDEP ,Dynamic dependency towards VPE clock domain" "0,1" width 0x0B tree.end tree "CM_CORE_AON__INSTR" base ad:0x4A005F00 width 21. group.byte 0x0++0x3 line.long 0x0 "CMI_IDENTICATION,CM profiling identification register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "CMI_SYS_CONFIG,CM profiling system configuartion register" bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local tartget state management mode" "0,1,2,3" bitfld.long 0x0 4.--5. " RESERVED ," "0,1,2,3" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "CMI_STATUS,CM profiling status register" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " FIFOEMPTY ,PM Profiling buffer empty" "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "CMI_CONFIGURATION,CM profiling configuration register" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ," bitfld.long 0x0 7. " EVT_CAPT_EN ,When HIGH the CM events capture is enabled" "0,1" textline " " hexmask.long.byte 0x0 8.--14. 1. " RESERVED ," bitfld.long 0x0 15. " MOD_ACT_EN ,When HIGH the CM Module Activity collection is enabled" "0,1" textline " " hexmask.long.byte 0x0 16.--22. 1. " RESERVED ," bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--27. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28. " CLAIM_1 ,Current owner" "0,1" textline " " bitfld.long 0x0 29. " CLAIM_2 ,Debugger override qualifier" "0,1" bitfld.long 0x0 30.--31. " CLAIM_3 ,Ownership" "0,1,2,3" group.byte 0x28++0x3 line.long 0x0 "CMI_CLASS_FILTERING,CM profiling class filtering register" bitfld.long 0x0 0. " SNAP_CAPT_EN_00 ,Snapshot capture enable - Class-ID = 0x00 [0x20]" "0,1" bitfld.long 0x0 1. " SNAP_CAPT_EN_01 ,Snapshot capture enable - Class-ID = 0x01 [0x21]" "0,1" textline " " bitfld.long 0x0 2. " SNAP_CAPT_EN_02 ,Snapshot capture enable - Class-ID = 0x02 [0x22]" "0,1" bitfld.long 0x0 3. " SNAP_CAPT_EN_03 ,Snapshot capture enable - Class-ID = 0x03 [0x23]" "0,1" textline " " hexmask.long.word 0x0 4.--15. 1. " RESERVED ," bitfld.long 0x0 16. " SNAP_CAPT_EN_10 ,Snapshot capture enable - Class-ID = 0x10" "0,1" textline " " bitfld.long 0x0 17. " SNAP_CAPT_EN_11 ," "0,1" bitfld.long 0x0 18. " SNAP_CAPT_EN_12 ," "0,1" textline " " bitfld.long 0x0 19. " SNAP_CAPT_EN_13 ," "0,1" bitfld.long 0x0 20. " SNAP_CAPT_EN_14 ," "0,1" textline " " bitfld.long 0x0 21. " SNAP_CAPT_EN_15 ," "0,1" bitfld.long 0x0 22. " SNAP_CAPT_EN_16 ," "0,1" textline " " bitfld.long 0x0 23. " SNAP_CAPT_EN_17 ," "0,1" bitfld.long 0x0 24. " SNAP_CAPT_EN_18 ," "0,1" textline " " bitfld.long 0x0 25. " SNAP_CAPT_EN_19 ," "0,1" bitfld.long 0x0 26. " SNAP_CAPT_EN_1A ," "0,1" textline " " bitfld.long 0x0 27. " SNAP_CAPT_EN_1B ," "0,1" bitfld.long 0x0 28. " SNAP_CAPT_EN_1C ," "0,1" textline " " bitfld.long 0x0 29. " SNAP_CAPT_EN_1D ," "0,1" bitfld.long 0x0 30. " SNAP_CAPT_EN_1E ," "0,1" textline " " bitfld.long 0x0 31. " SNAP_CAPT_EN_1F ,Snapshot capture enable - Class-ID = 0x1F" "0,1" group.byte 0x2C++0x3 line.long 0x0 "CMI_TRIGGERING,CM profiling triggering control register" bitfld.long 0x0 0. " TRIG_START_EN ,Enable start capturing CM events from external trigger detection" "0,1" bitfld.long 0x0 1. " TRIG_STOP_EN ,Enable stop capturing CM events from external trigger detection" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "CMI_SAMPLING,CM profiling sampling window register" hexmask.long.byte 0x0 0.--7. 1. " SAMP_WIND_SIZE ,CM events sampling window size" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--19. " FCLK_DIV_FACOR ,FunClk divide factor ranging from 1 to 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," width 0x0B tree.end tree "IVA_PRM" base ad:0x4AE06F00 width 20. group.byte 0x0++0x3 line.long 0x0 "PM_IVA_PWRSTCTRL,This register controls the IVA power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. " HWA_MEM_RETSTATE ,HWA memory state when domain is RETENTION." "0,1" textline " " bitfld.long 0x0 9. " SL2_MEM_RETSTATE ,SL2 memory state when domain is RETENTION." "0,1" bitfld.long 0x0 10. " TCM1_MEM_RETSTATE ,TCM1 memory state when domain is RETENTION." "0,1" textline " " bitfld.long 0x0 11. " TCM2_MEM_RETSTATE ,TCM2 memory state when domain is RETENTION." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " HWA_MEM_ONSTATE ,HWA memory state when domain is ON." "0,1,2,3" bitfld.long 0x0 18.--19. " SL2_MEM_ONSTATE ,SL2 memory state when domain is ON." "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " TCM1_MEM_ONSTATE ,TCM1 memory state when domain is ON." "0,1,2,3" bitfld.long 0x0 22.--23. " TCM2_MEM_ONSTATE ,TCM_CORE memory state when domain is ON." "0,1,2,3" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_IVA_PWRSTST,This register provides a status on the current IVA power domain state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " HWA_MEM_STATEST ,HWA memory state status" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " SL2_MEM_STATEST ,SL2 memory state status" "0,1,2,3" bitfld.long 0x0 8.--9. " TCM1_MEM_STATEST ,TCM1 memory state status" "0,1,2,3" textline " " bitfld.long 0x0 10.--11. " TCM2_MEM_STATEST ,TCM2 memory state status" "0,1,2,3" hexmask.long.byte 0x0 12.--19. 1. " RESERVED ," textline " " bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_IVA_RSTCTRL,This register controls the release of the IVA sub-system resets." bitfld.long 0x0 0. " RST_SEQ1 ,IVA sequencer1 reset control" "0,1" bitfld.long 0x0 1. " RST_SEQ2 ,IVA Sequencer2 reset control" "0,1" textline " " bitfld.long 0x0 2. " RST_LOGIC ,IVA logic and SL2 reset control" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "RM_IVA_RSTST,This register logs the different reset sources of the IVA domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RST_SEQ1 ,IVA Sequencer1 CPU SW reset" "0,1" bitfld.long 0x0 1. " RST_SEQ2 ,IVA Sequencer2 CPU SW reset" "0,1" textline " " bitfld.long 0x0 2. " RST_LOGIC ,IVA logic and SL2 SW reset" "0,1" bitfld.long 0x0 3. " RST_EMULATION_SEQ1 ,Sequencer1 CPU has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module" "0,1" textline " " bitfld.long 0x0 4. " RST_EMULATION_SEQ2 ,Sequencer2 CPU has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module" "0,1" bitfld.long 0x0 5. " RST_ICECRUSHER_SEQ1 ,Sequencer1 CPU has been reset due to IVA ICECRUSHER1 reset event" "0,1" textline " " bitfld.long 0x0 6. " RST_ICECRUSHER_SEQ2 ,Sequencer2 CPU has been reset due to IVA ICECRUSHER2 reset event" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_IVA_IVA_CONTEXT,This register contains dedicated IVA context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of IVA_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_TCM1_MEM ,Specify if memory-based context in TCM1_MEM memory bank has been lost due to a previous power transition or other reset source." "0,1" bitfld.long 0x0 9. " LOSTMEM_TCM2_MEM ,Specify if memory-based context in TCM2_MEM memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " bitfld.long 0x0 10. " LOSTMEM_HWA_MEM ,Specify if memory-based context in HWA_MEM memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "RM_IVA_SL2_CONTEXT,This register contains dedicated SL2 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of IVA_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_SL2_MEM ,Specify if memory-based context in SL2_MEM memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "DSP1_PRM" base ad:0x4AE06400 width 22. group.byte 0x0++0x3 line.long 0x0 "PM_DSP1_PWRSTCTRL,This register controls the DSP power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " DSP1_L1_ONSTATE ,DSP_L1 state when domain is ON." "0,1,2,3" bitfld.long 0x0 18.--19. " DSP1_L2_ONSTATE ,DSP_L2 state when domain is ON." "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " DSP1_EDMA_ONSTATE ,DSP_EDMA state when domain is ON." "0,1,2,3" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_DSP1_PWRSTST,This register provides a status on the DSP domain current power state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " DSP1_L1_STATEST ,DSP_L1 memory state status" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " DSP1_L2_STATEST ,DSP_L2 memory state status" "0,1,2,3" bitfld.long 0x0 8.--9. " DSP1_EDMA_STATEST ,DSP_EDMA memory state status" "0,1,2,3" textline " " hexmask.long.word 0x0 10.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_DSP1_RSTCTRL,This register controls the release of the DSP sub-system resets." bitfld.long 0x0 0. " RST_DSP1_LRST ,DSP Local reset control" "0,1" bitfld.long 0x0 1. " RST_DSP1 ,DSP reset control" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "RM_DSP1_RSTST,This register logs the different reset sources of the DSP domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RST_DSP1_LRST ,DSP Local SW reset" "0,1" bitfld.long 0x0 1. " RST_DSP1 ,DSP SW reset status" "0,1" textline " " bitfld.long 0x0 2. " RST_DSP1_EMU ,DSP domain has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module" "0,1" bitfld.long 0x0 3. " RST_DSP1_EMU_REQ ,DSP processor has been reset due to DSP emulation reset request driven from DSP-SS" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_DSP1_DSP1_CONTEXT,This register contains dedicated DSP context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of DSP_SYS_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_DSP_L1 ,Specify if memory-based context in DSP_L1 memory bank has been lost due to a previous power transition or other reset source." "0,1" bitfld.long 0x0 9. " LOSTMEM_DSP_L2 ,Specify if memory-based context in DSP_L2 memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " bitfld.long 0x0 10. " LOSTMEM_DSP_EDMA ,Specify if memory-based context in DSP_EDMA memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," width 0x0B tree.end tree "CORE_PRM" base ad:0x4AE06700 width 28. group.byte 0x0++0x3 line.long 0x0 "PM_CORE_PWRSTCTRL,This register controls the CORE power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" textline " " bitfld.long 0x0 5.--9. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 10. " IPU_L2RAM_RETSTATE ,IPU L2 bank state when domain is RETENTION." "0,1" textline " " bitfld.long 0x0 11. " IPU_UNICACHE_RETSTATE ,IPU UNICACHE bank state when domain is RETENTION." "0,1" hexmask.long.byte 0x0 12.--19. 1. " RESERVED ," textline " " bitfld.long 0x0 20.--21. " IPU_L2RAM_ONSTATE ,IPU L2 bank state when domain is ON." "0,1,2,3" bitfld.long 0x0 22.--23. " IPU_UNICACHE_ONSTATE ,IPU UNICACHE bank state when domain is ON." "0,1,2,3" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_CORE_PWRSTST,This register provides a status on the current CORE power domain state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--9. " IPU_L2RAM_STATEST ,IPU L2 bank state status" "0,1,2,3" textline " " bitfld.long 0x0 10.--11. " IPU_UNICACHE_STATEST ,IPU UNICACHE bank state status" "0,1,2,3" hexmask.long.byte 0x0 12.--19. 1. " RESERVED ," textline " " bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x50++0x3 line.long 0x0 "PM_L3MAIN1_OCMC_RAM1_WKDEP,This register controls wakeup dependency based on OCMC_RAM1 service requests." bitfld.long 0x0 0. " WKUPDEP_OCMC_RAM1_MPU ,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_OCMC_RAM1_IPU2 ,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_OCMC_RAM1_DSP1 ,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_OCMC_RAM1_IPU1 ,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_OCMC_RAM1_DSP2 ,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_OCMC_RAM1_EVE1 ,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_OCMC_RAM1_EVE2 ,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_OCMC_RAM1_EVE3 ,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_OCMC_RAM1_EVE4 ,Wakeup dependency from OCMC_RAM1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "PM_L3MAIN1_OCMC_RAM2_WKDEP,This register controls wakeup dependency based on OCMC_RAM2 service requests." bitfld.long 0x0 0. " WKUPDEP_OCMC_RAM2_MPU ,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_OCMC_RAM2_IPU2 ,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_OCMC_RAM2_DSP1 ,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_OCMC_RAM2_IPU1 ,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_OCMC_RAM2_DSP2 ,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_OCMC_RAM2_EVE1 ,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_OCMC_RAM2_EVE2 ,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_OCMC_RAM2_EVE3 ,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_OCMC_RAM2_EVE4 ,Wakeup dependency from OCMC_RAM2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "PM_L3MAIN1_OCMC_RAM3_WKDEP,This register controls wakeup dependency based on OCMC_RAM3 service requests." bitfld.long 0x0 0. " WKUPDEP_OCMC_RAM3_MPU ,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_OCMC_RAM3_IPU2 ,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_OCMC_RAM3_DSP1 ,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_OCMC_RAM3_IPU1 ,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_OCMC_RAM3_DSP2 ,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_OCMC_RAM3_EVE1 ,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_OCMC_RAM3_EVE2 ,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_OCMC_RAM3_EVE3 ,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_OCMC_RAM3_EVE4 ,Wakeup dependency from OCMC_RAM3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "PM_L3MAIN1_TPCC_WKDEP,This register controls wakeup dependency based on TPCC service requests." bitfld.long 0x0 0. " WKUPDEP_TPCC_MPU ,Wakeup dependency from TPCC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TPCC_IPU2 ,Wakeup dependency from TPCC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TPCC_DSP1 ,Wakeup dependency from TPCC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TPCC_IPU1 ,Wakeup dependency from TPCC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TPCC_DSP2 ,Wakeup dependency from TPCC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TPCC_EVE1 ,Wakeup dependency from TPCC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TPCC_EVE2 ,Wakeup dependency from TPCC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TPCC_EVE3 ,Wakeup dependency from TPCC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TPCC_EVE4 ,Wakeup dependency from TPCC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "PM_L3MAIN1_TPTC1_WKDEP,This register controls wakeup dependency based on TPTC service requests." bitfld.long 0x0 0. " WKUPDEP_TPTC1_MPU ,Wakeup dependency from TPTC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TPTC1_IPU2 ,Wakeup dependency from TPTC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TPTC1_DSP1 ,Wakeup dependency from TPTC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TPTC1_IPU1 ,Wakeup dependency from TPTC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TPTC1_DSP2 ,Wakeup dependency from TPTC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TPTC1_EVE1 ,Wakeup dependency from TPTC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TPTC1_EVE2 ,Wakeup dependency from TPTC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TPTC1_EVE3 ,Wakeup dependency from TPTC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TPTC1_EVE4 ,Wakeup dependency from TPTC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PM_L3MAIN1_TPTC2_WKDEP,This register controls wakeup dependency based on TPTC service requests." bitfld.long 0x0 0. " WKUPDEP_TPTC2_MPU ,Wakeup dependency from TPTC module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TPTC2_IPU2 ,Wakeup dependency from TPTC module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TPTC2_DSP1 ,Wakeup dependency from TPTC module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TPTC2_IPU1 ,Wakeup dependency from TPTC module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TPTC2_DSP2 ,Wakeup dependency from TPTC module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TPTC2_EVE1 ,Wakeup dependency from TPTC module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TPTC2_EVE2 ,Wakeup dependency from TPTC module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TPTC2_EVE3 ,Wakeup dependency from TPTC module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TPTC2_EVE4 ,Wakeup dependency from TPTC module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "RM_IPU2_RSTCTRL,This register controls the release of the IPU2 sub-system resets." bitfld.long 0x0 0. " RST_CPU0 ,IPU Cortex M4 CPU0 reset control." "0,1" bitfld.long 0x0 1. " RST_CPU1 ,IPU Cortex M4 CPU1 reset control" "0,1" textline " " bitfld.long 0x0 2. " RST_IPU ,IPU system reset control." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "RM_IPU2_RSTST,This register logs the different reset sources of the IPU2 SS. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RST_CPU0 ,IPU Cortex-M4 CPU0 software reset status" "0,1" bitfld.long 0x0 1. " RST_CPU1 ,IPU Cortex-M4 CPU1 software reset status" "0,1" textline " " bitfld.long 0x0 2. " RST_IPU ,IPU system software reset status" "0,1" bitfld.long 0x0 3. " RST_EMULATION_CPU0 ,Cortex M4 CPU0 has been reset due to emulation reset source, for example, assert reset command initiated by the icepick module" "0,1" textline " " bitfld.long 0x0 4. " RST_EMULATION_CPU1 ,Cortex M4 CPU1 has been reset due to emulation reset source, for example, assert reset command initiated by the icepick module" "0,1" bitfld.long 0x0 5. " RST_ICECRUSHER_CPU0 ,Cortex M4 CPU0 has been reset due to IPU ICECRUSHER0 reset source" "0,1" textline " " bitfld.long 0x0 6. " RST_ICECRUSHER_CPU1 ,Cortex M4 CPU1 has been reset due to IPU ICECRUSHER1 reset source" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "RM_IPU2_IPU2_CONTEXT,This register contains dedicated IPU2 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of IPU_RST signal)" "0,1" bitfld.long 0x0 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of IPU_RET_RST signal)" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " LOSTMEM_IPU_UNICACHE ,Specify if memory-based context in IPU_UNICACHE memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " bitfld.long 0x0 9. " LOSTMEM_IPU_L2RAM ,Specify if memory-based context in IPU_L2RAM memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE__CKGEN" base ad:0x4A008100 width 33. group.byte 0x4++0x3 line.long 0x0 "CM_CLKSEL_USB_60MHZ,Selects the configuration of the divider generating 60MHz clock for USB from the DPLL_USB o/p." bitfld.long 0x0 0. " CLKSEL ,Select the configuration of the divider" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "CM_CLKMODE_DPLL_PER,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " DPLL_DRIFTGUARD_EN ,This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set." "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " bitfld.long 0x0 10. " DPLL_LPMODE_EN ,Set the DPLL in Low Power mode. Check the DPLL documentation to see when this can be enabled." "0,1" bitfld.long 0x0 11. " DPLL_REGM4XEN ,Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled." "0,1" textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "CM_IDLEST_DPLL_PER,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_PER,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control;" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "CM_CLKSEL_DPLL_PER,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DPLL_DIV ,DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 8.--18. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 2047). (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M). [warm reset insensitive]" bitfld.long 0x0 19.--21. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "CM_DIV_M2_DPLL_PER,This register provides controls over the M2 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M2 post-divider factor (1 to 31) of DPLL_PER.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " CLKX2ST ,DPLL CLKOUTX2 status" "0,1" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "CM_DIV_M3_DPLL_PER,This register provides controls over the M3 divider of the DPLL." bitfld.long 0x0 0.--4. " DIVHS ,This field programs the M3 post-divider factor (1 to 31) of DPLL_PER.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUTHIF status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "CM_DIV_H11_DPLL_PER,This register provides controls over the CLKOUT1 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H11 post-divider factor (1 to 63) of DPLL_PER.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT1 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "CM_DIV_H12_DPLL_PER,This register provides controls over the CLKOUT2 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H12 post-divider factor (1 to 63) of DPLL_PER.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT2 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "CM_DIV_H13_DPLL_PER,This register provides controls over the CLKOUT3 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H13 post-divider factor (1 to 63) of DPLL_PER.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT3 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "CM_DIV_H14_DPLL_PER,This register provides controls over the CLKOUT4 o/p of the HSDIVIDER1." bitfld.long 0x0 0.--5. " DIVHS ,This field programs the H14 post-divider factor (1 to 63) of DPLL_PER. When a value of 63 is programmed in this register, HS divider will perform division by 2.5 that is divided by 2 at top level." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9. " CLKST ,HSDIVIDER1 CLKOUT4 status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_PER,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_PER,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "CM_CLKMODE_DPLL_USB,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 3.--11. 1. " RESERVED ," textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "CM_IDLEST_DPLL_USB,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_USB,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control;" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "CM_CLKSEL_DPLL_USB,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--7. 1. " DPLL_DIV ,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" hexmask.long.word 0x0 8.--19. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 4095). (equal to input M of DPLL; M=2 to 4095 = DPLL multiplies by M). [warm reset insensitive]" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21. " DPLL_SELFREQDCO ,select DCO output according to required frequency." "0,1" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " DPLL_SD_DIV ,Sigma-Delta divider select (2-255). This factor must be set by s/w to ensure optimum jitter performance. DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP / 250), where CLKINP is the input clock of the DPLL in MHz). Must be set with M and N factors, and must not be changed once DPLL is locked." group.byte 0x90++0x3 line.long 0x0 "CM_DIV_M2_DPLL_USB,This register provides controls over the M2 divider of the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DIVHS ,This field programs the M2 post-divider factor (1 to 127) of DPLL_USB.... ." bitfld.long 0x0 7.--8. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_USB,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--20. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [20:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0xAC++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_USB,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "CM_CLKDCOLDO_DPLL_USB,This register provides status over CLKDCOLDO output of the DPLL." hexmask.long.word 0x0 0.--8. 1. " RESERVED ," bitfld.long 0x0 9. " ST_DPLL_CLKDCOLDO ,DPLL CLKDCOLDO status" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "CM_CLKMODE_DPLL_PCIE_REF,This register allows controlling the DPLL modes." bitfld.long 0x0 0.--2. " DPLL_EN ,DPLL control." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 3.--11. 1. " RESERVED ," textline " " bitfld.long 0x0 12. " DPLL_SSC_EN ,Enable or disable Spread Spectrum Clocking" "0,1" bitfld.long 0x0 13. " DPLL_SSC_ACK ,Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature" "0,1" textline " " bitfld.long 0x0 14. " DPLL_SSC_DOWNSPREAD ,Control if only low frequency spread is required" "0,1" bitfld.long 0x0 15. " DPLL_SSC_TYPE ,Select between Triangular and SquareWave Spread Spectrum Clocking" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "CM_IDLEST_DPLL_PCIE_REF,This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_DPLL_CLK ,DPLL lock status" "0,1" bitfld.long 0x0 1.--3. " ST_DPLL_MODE ,DPLL mode status (for debug purpose)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " ST_DPLL_INIT ,DPLL init status (for debug purpose)." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_PCIE_REF,This register provides automatic control over the DPLL activity." bitfld.long 0x0 0.--2. " AUTO_DPLL_MODE ,DPLL automatic control;" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "CM_CLKSEL_DPLL_PCIE_REF,This register provides controls over the DPLL." hexmask.long.byte 0x0 0.--7. 1. " DPLL_DIV ,DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1). [warm reset insensitive]" hexmask.long.word 0x0 8.--19. 1. " DPLL_MULT ,DPLL multiplier factor (2 to 4095). (equal to input M of DPLL; M=2 to 4095 = DPLL multiplies by M). [warm reset insensitive]" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21. " DPLL_SELFREQDCO ,select DCO output according to required frequency." "0,1" textline " " bitfld.long 0x0 22. " DCC_EN ,Duty-cycle corrector for high frequency clock" "0,1" bitfld.long 0x0 23. " DPLL_BYP_CLKSEL ,Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " DPLL_SD_DIV ,Sigma-Delta divider select (2-255). This factor must be set by s/w to ensure optimum jitter performance. DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP / 250), where CLKINP is the input clock of the DPLL in MHz). Must be set with M and N factors, and must not be changed once DPLL is locked." group.byte 0x110++0x3 line.long 0x0 "CM_DIV_M2_DPLL_PCIE_REF,This register provides controls over the M2 divider of the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DIVHS ,This field programs the M2 post-divider factor (1 to 127) of DPLL_PCIE_REF.... ." bitfld.long 0x0 7.--8. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" bitfld.long 0x0 10. " CLKLDOST ,DPLL CLKOUTLDO status" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x114++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_PCIE_REF,Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.tbyte 0x0 0.--20. 1. " DELTAMSTEP ,DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [20:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x118++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_PCIE_REF,Control the Modulation Frequency (Fm) for Spread Spectrum Clocking. [warm reset insensitive]" hexmask.long.byte 0x0 0.--6. 1. " MODFREQDIV_MANTISSA ,Set the Mantissa component of MODFREQDIV factor" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " MODFREQDIV_EXPONENT ,Set the Exponent component of MODFREQDIV factor" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x11C++0x3 line.long 0x0 "CM_CLKMODE_APLL_PCIE,This register allows controlling the APLL modes." bitfld.long 0x0 0.--1. " MODE_SELECT ,Control APLL mode.Note:Please note that setting [1:0] MODE_SELECT bitfield to 0x0 does not disable the APLL_PCIE. In order to disable the APLL_PCIE, the user needs to disable PCIe_SSx (where x = 1 or 2) using the CM_PCIE_ PCIESSx_CLKCTRL[1:0] MODULEMODE registers. When PCIe_SS is disabled, the PRCM module automatically disables the APLL_PCIE. ." "0,1,2,3" bitfld.long 0x0 2. " MODE ,APLLPCIE Mode Status" "0,1" textline " " bitfld.long 0x0 3.--5. " INPSEL ,Reference clock is 100MHz." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. " RESERVED ," "0,1" textline " " bitfld.long 0x0 7. " REFSEL ,Select source of reference input clock" "0,1" bitfld.long 0x0 8. " CLKDIV_BYPASS ," "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x120++0x3 line.long 0x0 "CM_IDLEST_APLL_PCIE,This register allows monitoring APLL activity. This register is read only and automatically updated. [warm reset insensitive]" bitfld.long 0x0 0. " ST_APLL_CLK ,APLL lock status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "CM_DIV_M2_APLL_PCIE,This register provides controls over the M2 divider of the DPLL." hexmask.long.byte 0x0 0.--6. 1. " DIVHS ,DPLL M2 post-divider factor (1 to 127). (RESERVED)" bitfld.long 0x0 7.--8. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 9. " CLKST ,DPLL CLKOUT status" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x128++0x3 line.long 0x0 "CM_CLKVCOLDO_APLL_PCIE,This register provides status over CLKVCOLDO and CLKVCOLDO_DIV outputs of the APLL." hexmask.long.word 0x0 0.--8. 1. " RESERVED ," bitfld.long 0x0 9. " CLKST ,APLL CLKVCOLDO status" "0,1" textline " " bitfld.long 0x0 10. " CLK_DIVST ,APLL CLKVCOLDO_DIV status" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," width 0x0B tree.end tree "WKUPAON_CM" base ad:0x4AE07800 width 32. group.byte 0x0++0x3 line.long 0x0 "CM_WKUPAON_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the WKUPAON clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_SYS_CLK ,This field indicates the state of the SYS_CLK clock in the domain(it includes profiling, EMU_SYS_GCLK and all functional SYS_CLK. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_ABE_LP_CLK ,This field indicates the state of the ABE_LP_CLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " RESERVED ," "0,1" bitfld.long 0x0 11. " CLKACTIVITY_WKUPAON_SYS_GFCLK ,This field indicates the state of the WKUPAON_SYS_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 12. " CLKACTIVITY_WKUPAON_GICLK ,This field indicates the state of the WKUPAON_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 13. " RESERVED ," "0,1" textline " " bitfld.long 0x0 14. " CLKACTIVITY_SYS_CLK_FUNC ,This field indicates the state of the functional SYS_CLK clocks in the domain (this exclude activity of EMU_GCLK clock). [warm reset insensitive]" "0,1" bitfld.long 0x0 15. " CLKACTIVITY_SYS_CLK_ALL ,This field indicates the state of the SYS_CLK runing at SCRM level because of any SCRM clock request. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 16. " CLKACTIVITY_DCAN1_SYS_CLK ,This field indicates the state of the DCAN1_SYS_CLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 17. " CLKACTIVITY_TIMER1_GFCLK ,This field indicates the state of the TIMER1_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 18. " CLKACTIVITY_UART10_GFCLK ,This field indicates the state of the UART10_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_WKUPAON_L4_WKUP_CLKCTRL,This register manages the WKUPAON clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "CM_WKUPAON_WD_TIMER2_CLKCTRL,This register manages the WD_TIMER2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "CM_WKUPAON_GPIO1_CLKCTRL,This register manages the GPIO1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " OPTFCLKEN_DBCLK ,Optional functional clock control." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "CM_WKUPAON_TIMER1_CLKCTRL,This register manages the TIMER1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Select the source of the functional clock0xB-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x48++0x3 line.long 0x0 "CM_WKUPAON_TIMER12_CLKCTRL,This register manages the TIMER12 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "CM_WKUPAON_COUNTER_32K_CLKCTRL,This register manages the COUNTER_32K clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "CM_WKUPAON_KBD_CLKCTRL,This register manages the KBD clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "CM_WKUPAON_UART10_CLKCTRL,This register manages the UART10 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CM_WKUPAON_DCAN1_CLKCTRL,This register manages the DCAN1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects SYS clock for DCAN1 between SYS_CLK1 and SYS_CLK2" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__OCP_SOCKET" base ad:0x4A005000 width 34. group.byte 0x0++0x3 line.long 0x0 "REVISION_CM_CORE_AON,This register contains the IP revision code for the CM_CORE_AON part of the PRCM" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x40++0x3 line.long 0x0 "CM_CM_CORE_AON_PROFILING_CLKCTRL,This register manages the CM_CORE_AON_PROFILING clock. [warm reset insensitive]" bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xEC++0x3 line.long 0x0 "CM_CORE_AON_DEBUG_OUT,This register is used to monitor the CM_COREAON's 32 bit HEDEBUG BUS [warm reset insensitive]" hexmask.long 0x0 0.--31. 1. " OUTPUT ,HW DEBUG OUTPUT" group.byte 0xF0++0x3 line.long 0x0 "CM_CORE_AON_DEBUG_CFG0,This register is used to configure the CM_CORE_AON's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. The signals included in each block are specified in the PRCM integration specification. [warm reset insensitive]" hexmask.long.word 0x0 0.--9. 1. " SEL0 ,Internal signal block select for debug word byte-0" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xF4++0x3 line.long 0x0 "CM_CORE_AON_DEBUG_CFG1,This register is used to configure the CM_CORE_AON's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. The signals included in each block are specified in the PRCM integration specification. [warm reset insensitive]" hexmask.long.word 0x0 0.--9. 1. " SEL1 ,Internal signal block select for debug word byte-1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xF8++0x3 line.long 0x0 "CM_CORE_AON_DEBUG_CFG2,This register is used to configure the CM_CORE_AON's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. The signals included in each block are specified in the PRCM integration specification. [warm reset insensitive]" hexmask.long.word 0x0 0.--9. 1. " SEL2 ,Internal signal block select for debug word byte-2" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xFC++0x3 line.long 0x0 "CM_CORE_AON_DEBUG_CFG3,This register is used to configure the CM_CORE_AON's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. The signals included in each block are specified in the PRCM integration specification. [warm reset insensitive]" hexmask.long.word 0x0 0.--9. 1. " SEL3 ,Internal signal block select for debug word byte-3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "MPU_PRM" base ad:0x4AE06300 width 20. group.byte 0x0++0x3 line.long 0x0 "PM_MPU_PWRSTCTRL,This register controls the MPU domain power state to reach upon a domain sleep transition. If the value programmed in this register correspond to a lower power state than the one programmed in MPU-SS for CPU0 and/or CPU1, then value of this register is overwritten in PRCM logic to limit the power state to enter.Notes:Even if value of this register is overwritten in PRCM logic, value of this register remains unchanged. If user programs MPU power domain to go to CSWRET, then he can not program L2 cache to OFF mode.Note:Only the MPU Subsystem supports memory retention. MPU subsystem does not support OFF state. Only CPU1 supports FORCED_OFF state with no subsequent recovery to ON/active state - this is very application specific and may not be available in all TI standard software offerings." bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" textline " " bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 9. " MPU_L2_RETSTATE ,MPU_L2 memory state when domain is RETENTION. Should always be same as or higher than LogicRETState bit-field." "0,1" textline " " bitfld.long 0x0 10. " MPU_RAM_RETSTATE ,MPU_RAM memory state when domain is RETENTION." "0,1" hexmask.long.byte 0x0 11.--17. 1. " RESERVED ," textline " " bitfld.long 0x0 18.--19. " MPU_L2_ONSTATE ,MPU_L2 memory state when domain is ON." "0,1,2,3" bitfld.long 0x0 20.--21. " MPU_RAM_ONSTATE ,MPU_RAM memory state when domain is ON." "0,1,2,3" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_MPU_PWRSTST,This register provides a status on the MPU domain current power state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3.--5. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--7. " MPU_L2_STATEST ,MPU_L2 memory state status" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " MPU_RAM_STATEST ,MPU_RAM memory state status" "0,1,2,3" hexmask.long.word 0x0 10.--19. 1. " RESERVED ," textline " " bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x24++0x3 line.long 0x0 "RM_MPU_MPU_CONTEXT,This register contains dedicated MPU context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of MPU_RST signal)" "0,1" bitfld.long 0x0 1. " LOSTCONTEXT_RFF ,Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of MPU_MA_PWRON_RET_RST signal)" "0,1" textline " " hexmask.long.byte 0x0 2.--8. 1. " RESERVED ," bitfld.long 0x0 9. " LOSTMEM_MPU_L2 ,Specify if memory-based context in MPU_L2 memory bank has been lost due to a previous power transition or other reset source." "0,1" textline " " bitfld.long 0x0 10. " LOSTMEM_MPU_RAM ,Specify if memory-based context in MPU_RAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)." "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE__IVA" base ad:0x4A008F00 width 20. group.byte 0x0++0x3 line.long 0x0 "CM_IVA_CLKSTCTRL,This register enables the IVA domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the IVA clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_IVA_GCLK ,This field indicates the state of the IVA_ROOT_CLK clock input of the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_IVA_STATICDEP,This register controls the static domain depedencies from IVA domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "CM_IVA_DYNAMICDEP,This register controls the dynamic domain depedencies from IVA domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_IVA_IVA_CLKCTRL,This register manages the IVA clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "CM_IVA_SL2_CLKCTRL,This register manages the SL2 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__IPU" base ad:0x4A005500 width 23. group.byte 0x0++0x3 line.long 0x0 "CM_IPU1_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the IPU1 clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_IPU1_GFCLK ,This field indicates the state of the IPU1_GFCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_IPU1_STATICDEP,This register controls the static domain depedencies from IPU domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0. " IPU2_STATDEP ,Static dependency towards IPU2 clock domain" "0,1" bitfld.long 0x0 1. " DSP1_STATDEP ,Static dependency towards DSP clock domain" "0,1" textline " " bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " L3INIT_STATDEP ,Static dependency towards L3INIT clock domain" "0,1" textline " " bitfld.long 0x0 8. " DSS_STATDEP ,Static dependency towards DSS clock domain" "0,1" bitfld.long 0x0 9. " CAM_STATDEP ,Static dependency towards CAM clock domain" "0,1" textline " " bitfld.long 0x0 10. " GPU_STATDEP ,Static dependency towards GPU clock domain" "0,1" bitfld.long 0x0 11. " SDMA_STATDEP ,Static dependency towards DMA clock domain" "0,1" textline " " bitfld.long 0x0 12. " L4CFG_STATDEP ,Static dependency towards L4CFG clock domain" "0,1" bitfld.long 0x0 13. " L4PER_STATDEP ,Static dependency towards L4PER1 clock domain" "0,1" textline " " bitfld.long 0x0 14. " L4SEC_STATDEP ,Static dependency towards L4SEC clock domain" "0,1" bitfld.long 0x0 15. " WKUPAON_STATDEP ,Static dependency towards WKUPAON clock domain" "0,1" textline " " bitfld.long 0x0 16. " COREAON_STATDEP ,Static dependency towards COREAON clock domain" "0,1" bitfld.long 0x0 17. " CUSTEFUSE_STATDEP ,Static dependency towards CUSTEFUSE clock domain" "0,1" textline " " bitfld.long 0x0 18. " DSP2_STATDEP ,Static dependency towards DSP2 clock domain" "0,1" bitfld.long 0x0 19. " EVE1_STATDEP ,Static dependency towards EVE1 clock domain" "0,1" textline " " bitfld.long 0x0 20. " EVE2_STATDEP ,Static dependency towards EVE2 clock domain" "0,1" bitfld.long 0x0 21. " EVE3_STATDEP ,Static dependency towards EVE3 clock domain" "0,1" textline " " bitfld.long 0x0 22. " EVE4_STATDEP ,Static dependency towards EVE4 clock domain" "0,1" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24. " IPU_STATDEP ,Static dependency towards IPU clock domain" "0,1" bitfld.long 0x0 25. " GMAC_STATDEP ,Static dependency towards GMAC clock domain" "0,1" textline " " bitfld.long 0x0 26. " L4PER2_STATDEP ,Static dependency towards L4PER2 clock domain" "0,1" bitfld.long 0x0 27. " L4PER3_STATDEP ,Static dependency towards L4PER3 clock domain" "0,1" textline " " bitfld.long 0x0 28. " VPE_STATDEP ,Static dependency towards VPE clock domain" "0,1" bitfld.long 0x0 29. " PCIE_STATDEP ,Static dependency towards PCIE clock domain" "0,1" textline " " bitfld.long 0x0 30. " ATL_STATDEP ,Static dependency towards ATL clock domain" "0,1" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x8++0x3 line.long 0x0 "CM_IPU1_DYNAMICDEP,This register controls the dynamic domain depedencies from IPU domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " hexmask.long.tbyte 0x0 6.--23. 1. " RESERVED ," bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x20++0x3 line.long 0x0 "CM_IPU1_IPU1_CLKCTRL,This register manages the IPU1 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24. " CLKSEL ,Selects the timer functional clock" "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "CM_IPU_CLKSTCTRL,This register enables the ABE domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the ABE clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_IPU_L3_GICLK ,This field indicates the state of the IPU_L3_GICLK interface clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_TIMER5_GFCLK ,This field indicates the state of the TIMER5_GFCLK functional clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_TIMER6_GFCLK ,This field indicates the state of the TIMER6_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 11. " CLKACTIVITY_TIMER7_GFCLK ,This field indicates the state of the TIMER7_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 12. " CLKACTIVITY_TIMER8_GFCLK ,This field indicates the state of the TIMER8_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 13. " CLKACTIVITY_IPU_96M_GFCLK ,This field indicates the state of the IPU_96M_GFCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 14. " CLKACTIVITY_UART6_GFCLK ,This field indicates the state of the UART6_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16. " CLKACTIVITY_MCASP1_AUX_GFCLK ,This field indicates the state of the MCASP1_AUX_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 17. " CLKACTIVITY_MCASP1_AHCLKX ,This field indicates the state of the MCASP1_AHCLKX clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 18. " CLKACTIVITY_MCASP1_AHCLKR ,This field indicates the state of the MCASP1_AHCLKR clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "CM_IPU_MCASP1_CLKCTRL,This register manages the McASP clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 22.--23. " CLKSEL_AUX_CLK ,Selects the source of the AUX clock" "0,1,2,3" bitfld.long 0x0 24.--27. " CLKSEL_AHCLKX ,Selects reference clock for AHCLKX enum=SEL_FUNC_24M_GFCLK . enum=SEL_XREF_CLK3 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " CLKSEL_AHCLKR ,Selects reference clock for AHCLKR enum=SEL_FUNC_24M_GFCLK . enum=SEL_XREF_CLK3 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x58++0x3 line.long 0x0 "CM_IPU_TIMER5_CLKCTRL,This register manages the TIMER5 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xC-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x60++0x3 line.long 0x0 "CM_IPU_TIMER6_CLKCTRL,This register manages the TIMER6 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xC-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x68++0x3 line.long 0x0 "CM_IPU_TIMER7_CLKCTRL,This register manages the TIMER7 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xC-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x70++0x3 line.long 0x0 "CM_IPU_TIMER8_CLKCTRL,This register manages the TIMER8 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--27. " CLKSEL ,Selects the timer functional clock0xC-0xF: RESERVED enum=RESERVED ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x78++0x3 line.long 0x0 "CM_IPU_I2C5_CLKCTRL,This register manages the I2C5 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "CM_IPU_UART6_CLKCTRL,This register manages the UART6 clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " CLKSEL ,Selects functional clock for UART between FUNC_48M_FCLK and FUNC_192M_CLK" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," width 0x0B tree.end tree "EVE4_PRM" base ad:0x4AE07C00 width 22. group.byte 0x0++0x3 line.long 0x0 "PM_EVE4_PWRSTCTRL,This register controls the EVE4 power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " EVE4_BANK_ONSTATE ,EVE4 state when domain is ON." "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_EVE4_PWRSTST,This register provides a status on the EVE4 domain current power state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " EVE4_BANK_STATEST ,EVE4 memory state status" "0,1,2,3" textline " " hexmask.long.word 0x0 6.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_EVE4_RSTCTRL,This register controls the release of the EVE4 sub-system resets." bitfld.long 0x0 0. " RST_EVE4_LRST ,EVE4 Local reset control" "0,1" bitfld.long 0x0 1. " RST_EVE4 ,EVE4 SW reset control" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "RM_EVE4_RSTST,This register logs the different reset sources of the EVE4 domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RST_EVE4_LRST ,EVE4 Local SW reset" "0,1" bitfld.long 0x0 1. " RST_EVE4 ,EVE4 SW reset status" "0,1" textline " " bitfld.long 0x0 2. " RST_EVE4_EMU ,EVE4 domain has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module" "0,1" bitfld.long 0x0 3. " RST_EVE4_EMU_REQ ,EVE4 processor has been reset due to EVE emulation reset request driven from EVE4-SS" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PM_EVE4_EVE4_WKDEP,This register controls wakeup dependency based on EVE4 service requests." bitfld.long 0x0 0. " WKUPDEP_EVE4_MPU ,Wakeup dependency from EVE4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_EVE4_IPU2 ,Wakeup dependency from EVE4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_EVE4_DSP1 ,Wakeup dependency from EVE4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_EVE4_SDMA ,Wakeup dependency from EVE4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_EVE4_IPU1 ,Wakeup dependency from EVE4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_EVE4_DSP2 ,Wakeup dependency from EVE4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_EVE4_EVE1 ,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_EVE4_EVE2 ,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_EVE4_EVE3 ,Wakeup dependency from EVE4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_EVE4_EVE4_CONTEXT,This register contains dedicated EVE4 context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of EVE1_SYS_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_EVE_BANK ,Specify if memory-based context in EVE4 memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__DSP1" base ad:0x4A005400 width 22. group.byte 0x0++0x3 line.long 0x0 "CM_DSP1_CLKSTCTRL,This register enables the DSP domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSP clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_DSP1_GFCLK ,This field indicates the state of the DSP_ROOT_CLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_DSP1_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0. " IPU2_STATDEP ,Static dependency towards IPU2 Clock Domain" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA Clock Domain" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF Clock Domain" "0,1" bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 Clock Domain" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " L3INIT_STATDEP ,Static dependency towards L3INIT Clock Domain" "0,1" textline " " bitfld.long 0x0 8. " DSS_STATDEP ,Static dependency towards DSS Clock Domain" "0,1" bitfld.long 0x0 9. " CAM_STATDEP ,Static dependency towards CAM Clock Domain" "0,1" textline " " bitfld.long 0x0 10. " GPU_STATDEP ,Static dependency towards GPU Clock Domain" "0,1" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12. " L4CFG_STATDEP ,Static dependency towards L4CFG Clock Domain" "0,1" bitfld.long 0x0 13. " L4PER_STATDEP ,Static dependency towards L4PER1Clock Domain" "0,1" textline " " bitfld.long 0x0 14. " L4SEC_STATDEP ,Static dependency towards L4SEC Clock Domain" "0,1" bitfld.long 0x0 15. " WKUPAON_STATDEP ,Static dependency towards WKUPAON Clock Domain" "0,1" textline " " bitfld.long 0x0 16. " COREAON_STATDEP ,Static dependency towards COREAON Clock Domain" "0,1" bitfld.long 0x0 17. " CUSTEFUSE_STATDEP ,Static dependency towards CUSTEFUSE Clock Domain" "0,1" textline " " bitfld.long 0x0 18. " DSP2_STATDEP ,Static dependency towards DSP2 Clock Domain" "0,1" bitfld.long 0x0 19. " EVE1_STATDEP ,Static dependency towards EVE1 Clock Domain" "0,1" textline " " bitfld.long 0x0 20. " EVE2_STATDEP ,Static dependency towards EVE2 Clock Domain" "0,1" bitfld.long 0x0 21. " EVE3_STATDEP ,Static dependency towards EVE3 Clock Domain" "0,1" textline " " bitfld.long 0x0 22. " EVE4_STATDEP ,Static dependency towards EVE4 Clock Domain" "0,1" bitfld.long 0x0 23. " IPU1_STATDEP ,Static dependency towards IPU1 Clock Domain" "0,1" textline " " bitfld.long 0x0 24. " IPU_STATDEP ,Static dependency towards IPU Clock Domain" "0,1" bitfld.long 0x0 25. " GMAC_STATDEP ,Static dependency towards GMAC Clock Domain" "0,1" textline " " bitfld.long 0x0 26. " L4PER2_STATDEP ,Static dependency towards L4PER2 Clock Domain" "0,1" bitfld.long 0x0 27. " L4PER3_STATDEP ,Static dependency towards L4PER3 Clock Domain" "0,1" textline " " bitfld.long 0x0 28. " VPE_STATDEP ,Static dependency towards VPE Clock Domain" "0,1" bitfld.long 0x0 29. " PCIE_STATDEP ,Static dependency towards PCIE Clock Domain" "0,1" textline " " bitfld.long 0x0 30. " ATL_STATDEP ,Static dependency towards ATL Clock Domain" "0,1" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x8++0x3 line.long 0x0 "CM_DSP1_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " hexmask.long.tbyte 0x0 6.--23. 1. " RESERVED ," bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x20++0x3 line.long 0x0 "CM_DSP1_DSP1_CLKCTRL,This register manages the DSP clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," width 0x0B tree.end tree "CUSTEFUSE_PRM" base ad:0x4AE07600 width 38. group.byte 0x0++0x3 line.long 0x0 "PM_CUSTEFUSE_PWRSTCTRL,This register controls the CUSTEFUSE power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_CUSTEFUSE_PWRSTST,This register provides a status on the current CUSTEFUSE power domain state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " hexmask.long.tbyte 0x0 3.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x24++0x3 line.long 0x0 "RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,This register contains dedicated CUSTEFUSE module context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of CUSTEFUSE_RST signal)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "VPE_PRM" base ad:0x4AE07C80 width 20. group.byte 0x0++0x3 line.long 0x0 "PM_VPE_PWRSTCTRL,This register controls the VPE power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " LOWPOWERSTATECHANGE ,Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain." "0,1" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. " VPE_BANK_RETSTATE ,VPE_BANK state when domain is RETENTION." "0,1" textline " " hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " VPE_BANK_ONSTATE ,DSP_L1 state when domain is ON." "0,1,2,3" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PM_VPE_PWRSTST,This register provides a status on the VPE domain current power state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4.--5. " VPE_BANK_STATEST ,VPE_BANK memory state status" "0,1,2,3" textline " " hexmask.long.word 0x0 6.--19. 1. " RESERVED ," bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only." "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x20++0x3 line.long 0x0 "PM_VPE_VPE_WKDEP,This register controls wakeup dependency based on VPE service requests." bitfld.long 0x0 0. " WKUPDEP_VPE_MPU ,Wakeup dependency from VPE module (Swakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_VPE_IPU2 ,Wakeup dependency from VPE module ( Swakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_VPE_DSP1 ,Wakeup dependency from VPE module (Swakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_VPE_IPU1 ,Wakeup dependency from VPE module (Swakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_VPE_DSP2 ,Wakeup dependency from VPE module (Swakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_VPE_EVE1 ,Wakeup dependency from VPE module ( Swakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_VPE_EVE2 ,Wakeup dependency from VPE module (Swakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_VPE_EVE3 ,Wakeup dependency from VPE module (Swakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_VPE_EVE4 ,Wakeup dependency from VPE module (Swakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "RM_VPE_VPE_CONTEXT,This register contains dedicated VPE context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of VPE_RST signal)" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " LOSTMEM_VPE_BANK ,Specify if memory-based context in VPE memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__DSP2" base ad:0x4A005600 width 22. group.byte 0x0++0x3 line.long 0x0 "CM_DSP2_CLKSTCTRL,This register enables the DSP domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the DSP clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_DSP2_GFCLK ,This field indicates the state of the DSP_ROOT_CLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_DSP2_STATICDEP,This register controls the static domain depedencies from DSP domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0. " IPU2_STATDEP ,Static dependency towards IPU2 Clock Domain" "0,1" bitfld.long 0x0 1. " DSP1_STATDEP ,Static dependency towards DSP1Clock Domain" "0,1" textline " " bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA Clock Domain" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF Clock Domain" "0,1" bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 Clock Domain" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " L3INIT_STATDEP ,Static dependency towards L3INIT Clock Domain" "0,1" textline " " bitfld.long 0x0 8. " DSS_STATDEP ,Static dependency towards DSS Clock Domain" "0,1" bitfld.long 0x0 9. " CAM_STATDEP ,Static dependency towards CAM Clock Domain" "0,1" textline " " bitfld.long 0x0 10. " GPU_STATDEP ,Static dependency towards GPU Clock Domain" "0,1" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12. " L4CFG_STATDEP ,Static dependency towards L4CFG Clock Domain" "0,1" bitfld.long 0x0 13. " L4PER_STATDEP ,Static dependency towards L4PER1 Clock Domain" "0,1" textline " " bitfld.long 0x0 14. " L4SEC_STATDEP ,Static dependency towards L4SEC Clock Domain" "0,1" bitfld.long 0x0 15. " WKUPAON_STATDEP ,Static dependency towards WKUPAON Clock Domain" "0,1" textline " " bitfld.long 0x0 16. " COREAON_STATDEP ,Static dependency towards COREAON Clock Domain" "0,1" bitfld.long 0x0 17. " CUSTEFUSE_STATDEP ,Static dependency towards CUSTEFUSE Clock Domain" "0,1" textline " " bitfld.long 0x0 18. " RESERVED ," "0,1" bitfld.long 0x0 19. " EVE1_STATDEP ,Static dependency towards EVE1 Clock Domain" "0,1" textline " " bitfld.long 0x0 20. " EVE2_STATDEP ,Static dependency towards EVE2 Clock Domain" "0,1" bitfld.long 0x0 21. " EVE3_STATDEP ,Static dependency towards EVE3 Clock Domain" "0,1" textline " " bitfld.long 0x0 22. " EVE4_STATDEP ,Static dependency towards EVE4 Clock Domain" "0,1" bitfld.long 0x0 23. " IPU1_STATDEP ,Static dependency towards IPU1Clock Domain" "0,1" textline " " bitfld.long 0x0 24. " IPU_STATDEP ,Static dependency towards IPU Clock Domain" "0,1" bitfld.long 0x0 25. " GMAC_STATDEP ,Static dependency towards GMAC Clock Domain" "0,1" textline " " bitfld.long 0x0 26. " L4PER2_STATDEP ,Static dependency towards L4PER2 Clock Domain" "0,1" bitfld.long 0x0 27. " L4PER3_STATDEP ,Static dependency towards L4PER3 Clock Domain" "0,1" textline " " bitfld.long 0x0 28. " VPE_STATDEP ,Static dependency towards VPE Clock Domain" "0,1" bitfld.long 0x0 29. " PCIE_STATDEP ,Static dependency towards PCIE Clock Domain" "0,1" textline " " bitfld.long 0x0 30. " ATL_STATDEP ,Static dependency towards ATL Clock Domain" "0,1" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x8++0x3 line.long 0x0 "CM_DSP2_DYNAMICDEP,This register controls the dynamic domain depedencies from DSP domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " hexmask.long.tbyte 0x0 6.--23. 1. " RESERVED ," bitfld.long 0x0 24.--27. " WINDOWSIZE ,Size of sliding window used to monitor OCP interface activity for determination of auto-sleep feature. Time unit defined byCM_DYN_DEP_PRESCAL register." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x20++0x3 line.long 0x0 "CM_DSP2_DSP2_CLKCTRL,This register manages the DSP clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE__COREAON" base ad:0x4A008600 width 39. group.byte 0x0++0x3 line.long 0x0 "CM_COREAON_CLKSTCTRL,This register enables the domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the COREAON clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_COREAON_L4_GICLK ,This field indicates the state of the COREAON_L4_GICLK clock of the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_SR_MPU_SYS_GFCLK ,This field indicates the state of the SR_MPU_SYS_GFCLK clock input of the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_SR_GPU_SYS_GFCLK ,This field indicates the state of the SR_GPU_SYS_GFCLK clock input of the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 11. " CLKACTIVITY_SR_CORE_SYS_GFCLK ,This field indicates the state of the SR_CORE_SYS_GFCLK clock input of the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 12. " CLKACTIVITY_COREAON_32K_GFCLK ,This field indicates the state of the COREAON_32K_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 13. " CLKACTIVITY_SR_DSPEVE_SYS_GFCLK ,This field indicates the state of the SR_DSPEVE_SYS_GFCLK clock input of the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 14. " CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK ,This field indicates the state of the COREAON_IO_SRCOMP_GFCLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 15. " CLKACTIVITY_SR_IVAHD_SYS_GFCLK ,This field indicates the state of the SR_IVAHD_SYS_GFCLK clock input of the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 16. " CLKACTIVITY_ABE_GICLK ,This field indicates the state of the ABE_GICLK clock input of the domain. [warm reset insensitive]" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,This register manages the SR_MPU clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,This register manages the SR_CORE clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "CM_COREAON_USB_PHY1_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " OPTFCLKEN_CLK32K ,Optional functional clock control." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "CM_COREAON_IO_SRCOMP_CLKCTRL,This register manages the clock delivered to the IO Slew rate compensation cells. [warm reset insensitive]" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " CLKEN_SRCOMP_FCLK ,Functional clock control." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "CM_COREAON_SMARTREFLEX_GPU_CLKCTRL,This register manages the SR_GPU clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL,This register manages the SR_DSPEVE clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL,This register manages the SR_IVAHD clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CM_COREAON_USB_PHY2_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " OPTFCLKEN_CLK32K ,Optional functional clock control." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "CM_COREAON_USB_PHY3_CORE_CLKCTRL,This register manages the USB PHY 32KHz clock." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " OPTFCLKEN_CLK32K ,Optional functional clock control." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "CM_COREAON_CLKOUTMUX1_CLKCTRL,Used for controlling the CLKOUTMUX 1 gate." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " OPTFCLKEN_CLKOUTMUX1_CLK ,Optional functional clock control." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xB0++0x3 line.long 0x0 "CM_COREAON_CLKOUTMUX2_CLKCTRL,Used for controlling the CLKOUTMUX 2 gate." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " OPTFCLKEN_CLKOUTMUX2_CLK ,Optional functional clock control." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xC0++0x3 line.long 0x0 "CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL,Used for controlling the L3INIT_60M_GFCLK gate." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " OPTFCLKEN_L3INIT_60M_GFCLK ,Optional functional clock control; used to control the clock of USB2PHY2." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "CM_COREAON_ABE_GICLK_CLKCTRL,Used for controlling ABE_GICLK gate." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " OPTFCLKEN_ABE_GICLK ,Optional functional clock control." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "L4PER_PRM" base ad:0x4AE07400 width 24. group.byte 0x28++0x3 line.long 0x0 "PM_L4PER_TIMER10_WKDEP,This register controls wakeup dependency based on TIMER10 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER10_MPU ,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER10_IPU2 ,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER10_DSP1 ,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER10_IPU1 ,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER10_DSP2 ,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER10_EVE1 ,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER10_EVE2 ,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER10_EVE3 ,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER10_EVE4 ,Wakeup dependency from TIMER10 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PM_L4PER_TIMER11_WKDEP,This register controls wakeup dependency based on TIMER11 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER11_MPU ,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER11_IPU2 ,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER11_DSP1 ,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER11_IPU1 ,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER11_DSP2 ,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER11_EVE1 ,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER11_EVE2 ,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER11_EVE3 ,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER11_EVE4 ,Wakeup dependency from TIMER11 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PM_L4PER_TIMER2_WKDEP,This register controls wakeup dependency based on TIMER2 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER2_MPU ,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER2_IPU2 ,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER2_DSP1 ,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER2_IPU1 ,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER2_DSP2 ,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER2_EVE1 ,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER2_EVE2 ,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER2_EVE3 ,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER2_EVE4 ,Wakeup dependency from TIMER2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PM_L4PER_TIMER3_WKDEP,This register controls wakeup dependency based on TIMER3 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER3_MPU ,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER3_IPU2 ,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER3_DSP1 ,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER3_IPU1 ,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER3_DSP2 ,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER3_EVE1 ,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER3_EVE2 ,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER3_EVE3 ,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER3_EVE4 ,Wakeup dependency from TIMER3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "PM_L4PER_TIMER4_WKDEP,This register controls wakeup dependency based on TIMER4 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER4_MPU ,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER4_IPU2 ,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER4_DSP1 ,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER4_IPU1 ,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER4_DSP2 ,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER4_EVE1 ,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER4_EVE2 ,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER4_EVE3 ,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER4_EVE4 ,Wakeup dependency from TIMER4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "PM_L4PER_TIMER9_WKDEP,This register controls wakeup dependency based on TIMER9 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER9_MPU ,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER9_IPU2 ,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER9_DSP1 ,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER9_IPU1 ,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER9_DSP2 ,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER9_EVE1 ,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER9_EVE2 ,W(SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER9_EVE3 ,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER9_EVE4 ,Wakeup dependency from TIMER9 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "PM_L4PER_GPIO2_WKDEP,This register controls wakeup dependency based on GPIO2 service requests." bitfld.long 0x0 0. " WKUPDEP_GPIO2_IRQ1_MPU ,Wakeup dependency from GPIO2 module (SWakeup signal for POROCPSINTERRUPT1 ) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_GPIO2_IRQ1_IPU2 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_GPIO2_IRQ1_DSP1 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_GPIO2_IRQ1_IPU1 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_GPIO2_IRQ1_DSP2 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_GPIO2_IRQ1_EVE1 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_GPIO2_IRQ1_EVE2 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_GPIO2_IRQ1_EVE3 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_GPIO2_IRQ1_EVE4 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_GPIO2_IRQ2_MPU ,Wakeup dependency from GPIO2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_GPIO2_IRQ2_IPU2 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_GPIO2_IRQ2_DSP1 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " RESERVED ," "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_GPIO2_IRQ2_IPU1 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_GPIO2_IRQ2_DSP2 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_GPIO2_IRQ2_EVE1 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_GPIO2_IRQ2_EVE2 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_GPIO2_IRQ2_EVE3 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_GPIO2_IRQ2_EVE4 ,Wakeup dependency from GPIO2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "PM_L4PER_GPIO3_WKDEP,This register controls wakeup dependency based on GPIO3 service requests." bitfld.long 0x0 0. " WKUPDEP_GPIO3_IRQ1_MPU ,Wakeup dependency from GPIO3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_GPIO3_IRQ1_IPU2 ,3Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_GPIO3_IRQ1_DSP1 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_GPIO3_IRQ1_IPU1 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_GPIO3_IRQ1_DSP2 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_GPIO3_IRQ1_EVE1 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_GPIO3_IRQ1_EVE2 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_GPIO3_IRQ1_EVE3 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_GPIO3_IRQ1_EVE4 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_GPIO3_IRQ2_MPU ,Wakeup dependency from GPIO3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_GPIO3_IRQ2_IPU2 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_GPIO3_IRQ2_DSP1 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " RESERVED ," "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_GPIO3_IRQ2_IPU1 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_GPIO3_IRQ2_DSP2 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_GPIO3_IRQ2_EVE1 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_GPIO3_IRQ2_EVE2 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_GPIO3_IRQ2_EVE3 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_GPIO3_IRQ2_EVE4 ,Wakeup dependency from GPIO3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "PM_L4PER_GPIO4_WKDEP,This register controls wakeup dependency based on GPIO4 service requests." bitfld.long 0x0 0. " WKUPDEP_GPIO4_IRQ1_MPU ,Wakeup dependency from GPIO4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_GPIO4_IRQ1_IPU2 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_GPIO4_IRQ1_DSP1 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_GPIO4_IRQ1_IPU1 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_GPIO4_IRQ1_DSP2 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_GPIO4_IRQ1_EVE1 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_GPIO4_IRQ1_EVE2 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_GPIO4_IRQ1_EVE3 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_GPIO4_IRQ1_EVE4 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_GPIO4_IRQ2_MPU ,Wakeup dependency from GPIO4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_GPIO4_IRQ2_IPU2 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_GPIO4_IRQ2_DSP1 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " RESERVED ," "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_GPIO4_IRQ2_IPU1 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_GPIO4_IRQ2_DSP2 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_GPIO4_IRQ2_EVE1 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_GPIO4_IRQ2_EVE2 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_GPIO4_IRQ2_EVE3 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_GPIO4_IRQ2_EVE4 ,Wakeup dependency from GPIO4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "PM_L4PER_GPIO5_WKDEP,This register controls wakeup dependency based on GPIO5 service requests." bitfld.long 0x0 0. " WKUPDEP_GPIO5_IRQ1_MPU ,Wakeup dependency from GPIO5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_GPIO5_IRQ1_IPU2 ,5Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_GPIO5_IRQ1_DSP1 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_GPIO5_IRQ1_IPU1 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_GPIO5_IRQ1_DSP2 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_GPIO5_IRQ1_EVE1 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_GPIO5_IRQ1_EVE2 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_GPIO5_IRQ1_EVE3 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_GPIO5_IRQ1_EVE4 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_GPIO5_IRQ2_MPU ,Wakeup dependency from GPIO5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_GPIO5_IRQ2_IPU2 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_GPIO5_IRQ2_DSP1 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " RESERVED ," "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_GPIO5_IRQ2_IPU1 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_GPIO5_IRQ2_DSP2 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_GPIO5_IRQ2_EVE1 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_GPIO5_IRQ2_EVE2 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_GPIO5_IRQ2_EVE3 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_GPIO5_IRQ2_EVE4 ,Wakeup dependency from GPIO5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PM_L4PER_GPIO6_WKDEP,This register controls wakeup dependency based on GPIO6 service requests." bitfld.long 0x0 0. " WKUPDEP_GPIO6_IRQ1_MPU ,Wakeup dependency from GPIO6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_GPIO6_IRQ1_IPU2 ,5Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_GPIO6_IRQ1_DSP1 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_GPIO6_IRQ1_IPU1 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_GPIO6_IRQ1_DSP2 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_GPIO6_IRQ1_EVE1 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_GPIO6_IRQ1_EVE2 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_GPIO6_IRQ1_EVE3 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_GPIO6_IRQ1_EVE4 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_GPIO6_IRQ2_MPU ,Wakeup dependency from GPIO6 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_GPIO6_IRQ2_IPU2 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_GPIO6_IRQ2_DSP1 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " RESERVED ," "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_GPIO6_IRQ2_IPU1 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_GPIO6_IRQ2_DSP2 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_GPIO6_IRQ2_EVE1 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_GPIO6_IRQ2_EVE2 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_GPIO6_IRQ2_EVE3 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_GPIO6_IRQ2_EVE4 ,Wakeup dependency from GPIO6 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PM_L4PER_I2C1_WKDEP,This register controls wakeup dependency based on I2C1 service requests." bitfld.long 0x0 0. " WKUPDEP_I2C1_IRQ_MPU ,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_I2C1_IRQ_IPU2 ,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_I2C1_IRQ_DSP1 ,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_I2C1_IRQ_IPU1 ,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_I2C1_IRQ_DSP2 ,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_I2C1_IRQ_EVE1 ,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_I2C1_IRQ_EVE2 ,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_I2C1_IRQ_EVE3 ,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_I2C1_IRQ_EVE4 ,Wakeup dependency from I2C1 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_I2C1_DMA_DSP1 ,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_I2C1_DMA_SDMA ,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_I2C1_DMA_DSP2 ,Wakeup dependency from I2C1 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "PM_L4PER_I2C2_WKDEP,This register controls wakeup dependency based on I2C2 service requests." bitfld.long 0x0 0. " WKUPDEP_I2C2_IRQ_MPU ,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_I2C2_IRQ_IPU2 ,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_I2C2_IRQ_DSP1 ,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_I2C2_IRQ_IPU1 ,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_I2C2_IRQ_DSP2 ,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_I2C2_IRQ_EVE1 ,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_I2C2_IRQ_EVE2 ,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_I2C2_IRQ_EVE3 ,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_I2C2_IRQ_EVE4 ,Wakeup dependency from I2C2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_I2C2_DMA_DSP1 ,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_I2C2_DMA_SDMA ,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_I2C2_DMA_DSP2 ,Wakeup dependency from I2C2 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xB0++0x3 line.long 0x0 "PM_L4PER_I2C3_WKDEP,This register controls wakeup dependency based on I2C3 service requests." bitfld.long 0x0 0. " WKUPDEP_I2C3_IRQ_MPU ,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_I2C3_IRQ_IPU2 ,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_I2C3_IRQ_DSP1 ,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_I2C3_IRQ_IPU1 ,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_I2C3_IRQ_DSP2 ,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_I2C3_IRQ_EVE1 ,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_I2C3_IRQ_EVE2 ,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_I2C3_IRQ_EVE3 ,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_I2C3_IRQ_EVE4 ,Wakeup dependency from I2C3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_I2C3_DMA_DSP1 ,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_I2C3_DMA_SDMA ,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_I2C3_DMA_DSP2 ,Wakeup dependency from I2C3 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "PM_L4PER_I2C4_WKDEP,This register controls wakeup dependency based on I2C4 service requests." bitfld.long 0x0 0. " WKUPDEP_I2C4_IRQ_MPU ,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_I2C4_IRQ_IPU2 ,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_I2C4_IRQ_DSP1 ,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_I2C4_IRQ_IPU1 ,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_I2C4_IRQ_DSP2 ,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_I2C4_IRQ_EVE1 ,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_I2C4_IRQ_EVE2 ,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_I2C4_IRQ_EVE3 ,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_I2C4_IRQ_EVE4 ,Wakeup dependency from I2C4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_I2C4_DMA_DSP1 ,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_I2C4_DMA_SDMA ,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_I2C4_DMA_DSP2 ,Wakeup dependency from I2C4 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xC8++0x3 line.long 0x0 "PM_L4PER_TIMER13_WKDEP,This register controls wakeup dependency based on TIMER13 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER13_MPU ,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER13_IPU2 ,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER13_DSP1 ,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER13_IPU1 ,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER13_DSP2 ,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER13_EVE1 ,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER13_EVE2 ,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER13_EVE3 ,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER13_EVE4 ,Wakeup dependency from TIMER13 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "PM_L4PER_TIMER14_WKDEP,This register controls wakeup dependency based on TIMER14 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER14_MPU ,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER14_IPU2 ,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER14_DSP1 ,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER14_IPU1 ,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER14_DSP2 ,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER14_EVE1 ,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER14_EVE2 ,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER14_EVE3 ,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER14_EVE4 ,Wakeup dependency from TIMER14 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xD8++0x3 line.long 0x0 "PM_L4PER_TIMER15_WKDEP,This register controls wakeup dependency based on TIMER15 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER15_MPU ,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER15_IPU2 ,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER15_DSP1 ,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER15_IPU1 ,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER15_DSP2 ,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER15_EVE1 ,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER15_EVE2 ,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER15_EVE3 ,Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER15_EVE4 ,5Wakeup dependency from TIMER15 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "PM_L4PER_MCSPI1_WKDEP,This register controls wakeup dependency based on MCSPI1 service requests." bitfld.long 0x0 0. " WKUPDEP_MCSPI1_MPU ,Wakeup dependency from MCSPI1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCSPI1_IPU2 ,Wakeup dependency from MCSPI1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCSPI1_DSP1 ,Wakeup dependency from MCSPI1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_MCSPI1_SDMA ,Wakeup dependency from MCSPI1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCSPI1_IPU1 ,Wakeup dependency from MCSPI1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCSPI1_DSP2 ,Wakeup dependency from MCSPI1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCSPI1_EVE1 ,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCSPI1_EVE2 ,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCSPI1_EVE3 ,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCSPI1_EVE4 ,Wakeup dependency from MCSPI1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xF8++0x3 line.long 0x0 "PM_L4PER_MCSPI2_WKDEP,This register controls wakeup dependency based on MCSPI2 service requests." bitfld.long 0x0 0. " WKUPDEP_MCSPI2_MPU ,Wakeup dependency from MCSPI2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCSPI2_IPU2 ,Wakeup dependency from MCSPI2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCSPI2_DSP1 ,Wakeup dependency from MCSPI2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_MCSPI2_SDMA ,Wakeup dependency from MCSPI2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCSPI2_IPU1 ,Wakeup dependency from MCSPI2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCSPI2_DSP2 ,Wakeup dependency from MCSPI2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCSPI2_EVE1 ,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCSPI2_EVE2 ,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCSPI2_EVE3 ,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCSPI2_EVE4 ,Wakeup dependency from MCSPI2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "PM_L4PER_MCSPI3_WKDEP,This register controls wakeup dependency based on MCSPI3 service requests." bitfld.long 0x0 0. " WKUPDEP_MCSPI3_MPU ,Wakeup dependency from MCSPI3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCSPI3_IPU2 ,Wakeup dependency from MCSPI3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCSPI3_DSP1 ,Wakeup dependency from MCSPI3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_MCSPI3_SDMA ,Wakeup dependency from MCSPI3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCSPI3_IPU1 ,Wakeup dependency from MCSPI3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCSPI3_DSP2 ,Wakeup dependency from MCSPI3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCSPI3_EVE1 ,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCSPI3_EVE2 ,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCSPI3_EVE3 ,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCSPI3_EVE4 ,Wakeup dependency from MCSPI3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "PM_L4PER_MCSPI4_WKDEP,This register controls wakeup dependency based on MCSPI4 service requests." bitfld.long 0x0 0. " WKUPDEP_MCSPI4_MPU ,Wakeup dependency from MCSPI4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCSPI4_IPU2 ,Wakeup dependency from MCSPI4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCSPI4_DSP1 ,Wakeup dependency from MCSPI4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_MCSPI4_SDMA ,Wakeup dependency from MCSPI4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCSPI4_IPU1 ,Wakeup dependency from MCSPI4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCSPI4_DSP2 ,Wakeup dependency from MCSPI4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCSPI4_EVE1 ,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCSPI4_EVE2 ,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCSPI4_EVE3 ,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCSPI4_EVE4 ,Wakeup dependency from MCSPI4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "PM_L4PER_GPIO7_WKDEP,This register controls wakeup dependency based on GPIO7 service requests." bitfld.long 0x0 0. " WKUPDEP_GPIO7_IRQ1_MPU ,Wakeup dependency from GPIO7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_GPIO7_IRQ1_IPU2 ,5Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_GPIO7_IRQ1_DSP1 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_GPIO7_IRQ1_IPU1 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_GPIO7_IRQ1_DSP2 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_GPIO7_IRQ1_EVE1 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_GPIO7_IRQ1_EVE2 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_GPIO7_IRQ1_EVE3 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_GPIO7_IRQ1_EVE4 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_GPIO7_IRQ2_MPU ,Wakeup dependency from GPIO7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_GPIO7_IRQ2_IPU2 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_GPIO7_IRQ2_DSP1 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " RESERVED ," "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_GPIO7_IRQ2_IPU1 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_GPIO7_IRQ2_DSP2 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_GPIO7_IRQ2_EVE1 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_GPIO7_IRQ2_EVE2 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_GPIO7_IRQ2_EVE3 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_GPIO7_IRQ2_EVE4 ,Wakeup dependency from GPIO7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x118++0x3 line.long 0x0 "PM_L4PER_GPIO8_WKDEP,This register controls wakeup dependency based on GPIO8 service requests." bitfld.long 0x0 0. " WKUPDEP_GPIO8_IRQ1_MPU ,Wakeup dependency from GPIO8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_GPIO8_IRQ1_IPU2 ,5Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_GPIO8_IRQ1_DSP1 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_GPIO8_IRQ1_IPU1 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_GPIO8_IRQ1_DSP2 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_GPIO8_IRQ1_EVE1 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_GPIO8_IRQ1_EVE2 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_GPIO8_IRQ1_EVE3 ,Wakeup dependency from GPIO8 (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_GPIO8_IRQ1_EVE4 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10. " WKUPDEP_GPIO8_IRQ2_MPU ,Wakeup dependency from GPIO8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 11. " WKUPDEP_GPIO8_IRQ2_IPU2 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 12. " WKUPDEP_GPIO8_IRQ2_DSP1 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 13. " RESERVED ," "0,1" textline " " bitfld.long 0x0 14. " WKUPDEP_GPIO8_IRQ2_IPU1 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 15. " WKUPDEP_GPIO8_IRQ2_DSP2 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 16. " WKUPDEP_GPIO8_IRQ2_EVE1 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 17. " WKUPDEP_GPIO8_IRQ2_EVE2 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 18. " WKUPDEP_GPIO8_IRQ2_EVE3 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 19. " WKUPDEP_GPIO8_IRQ2_EVE4 ,Wakeup dependency from GPIO8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x120++0x3 line.long 0x0 "PM_L4PER_MMC3_WKDEP,This register controls wakeup dependency based on MMC3 service requests." bitfld.long 0x0 0. " WKUPDEP_MMC3_MPU ,Wakeup dependency from MMC3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MMC3_IPU2 ,Wakeup dependency from MMC3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MMC3_DSP1 ,Wakeup dependency from MMC3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_MMC3_SDMA ,Wakeup dependency from MMC3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MMC3_IPU1 ,Wakeup dependency from MMC3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MMC3_DSP2 ,Wakeup dependency from MMC3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MMC3_EVE1 ,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MMC3_EVE2 ,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MMC3_EVE3 ,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MMC3_EVE4 ,Wakeup dependency from MMC3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x128++0x3 line.long 0x0 "PM_L4PER_MMC4_WKDEP,This register controls wakeup dependency based on MMC4 service requests." bitfld.long 0x0 0. " WKUPDEP_MMC4_MPU ,Wakeup dependency from MMC4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MMC4_IPU2 ,Wakeup dependency from MMC4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MMC4_DSP1 ,Wakeup dependency from MMC4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_MMC4_SDMA ,Wakeup dependency from MMC4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MMC4_IPU1 ,Wakeup dependency from MMC4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MMC4_DSP2 ,Wakeup dependency from MMC4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MMC4_EVE1 ,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MMC4_EVE2 ,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MMC4_EVE3 ,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MMC4_EVE4 ,Wakeup dependency from MMC4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "PM_L4PER_TIMER16_WKDEP,This register controls wakeup dependency based on TIMER16 service requests." bitfld.long 0x0 0. " WKUPDEP_TIMER16_MPU ,6Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_TIMER16_IPU2 ,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_TIMER16_DSP1 ,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_TIMER16_IPU1 ,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_TIMER16_DSP2 ,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_TIMER16_EVE1 ,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_TIMER16_EVE2 ,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_TIMER16_EVE3 ,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_TIMER16_EVE4 ,Wakeup dependency from TIMER16 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x138++0x3 line.long 0x0 "PM_L4PER2_QSPI_WKDEP,This register controls wakeup dependency based on QSPI service requests." bitfld.long 0x0 0. " WKUPDEP_QSPI_MPU ,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_QSPI_IPU2 ,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_QSPI_DSP1 ,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_QSPI_IPU1 ,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_QSPI_DSP2 ,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_QSPI_EVE1 ,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_QSPI_EVE2 ,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_QSPI_EVE3 ,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_QSPI_EVE4 ,Wakeup dependency from QSPI module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x140++0x3 line.long 0x0 "PM_L4PER_UART1_WKDEP,This register controls wakeup dependency based on UART1 service requests." bitfld.long 0x0 0. " WKUPDEP_UART1_MPU ,Wakeup dependency from UART1 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_UART1_IPU2 ,Wakeup dependency from UART1 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_UART1_DSP1 ,Wakeup dependency from UART1 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_UART1_SDMA ,Wakeup dependency from UART1 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_UART1_IPU1 ,Wakeup dependency from UART1 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_UART1_DSP2 ,Wakeup dependency from UART1 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_UART1_EVE1 ,Wakeup dependency from UART1 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_UART1_EVE2 ,Wakeup dependency from UART1 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_UART1_EVE3 ,Wakeup dependency from UART1 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_UART1_EVE4 ,Wakeup dependency from UART1 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x148++0x3 line.long 0x0 "PM_L4PER_UART2_WKDEP,This register controls wakeup dependency based on UART2 service requests." bitfld.long 0x0 0. " WKUPDEP_UART2_MPU ,Wakeup dependency from UART2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_UART2_IPU2 ,Wakeup dependency from UART2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_UART2_DSP1 ,Wakeup dependency from UART2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_UART2_SDMA ,2Wakeup dependency from UART2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_UART2_IPU1 ,Wakeup dependency from UART2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_UART2_DSP2 ,Wakeup dependency from UART2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_UART2_EVE1 ,Wakeup dependency from UART2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_UART2_EVE2 ,Wakeup dependency from UART2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_UART2_EVE3 ,Wakeup dependency from UART2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_UART2_EVE4 ,Wakeup dependency from UART2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x150++0x3 line.long 0x0 "PM_L4PER_UART3_WKDEP,This register controls wakeup dependency based on UART3 service requests." bitfld.long 0x0 0. " WKUPDEP_UART3_MPU ,Wakeup dependency from UART3 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_UART3_IPU2 ,Wakeup dependency from UART3 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_UART3_DSP1 ,Wakeup dependency from UART3 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_UART3_SDMA ,Wakeup dependency from UART3 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_UART3_IPU1 ,Wakeup dependency from UART3 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_UART3_DSP2 ,Wakeup dependency from UART3 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_UART3_EVE1 ,Wakeup dependency from UART3 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_UART3_EVE2 ,Wakeup dependency from UART3 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_UART3_EVE3 ,Wakeup dependency from UART3 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_UART3_EVE4 ,Wakeup dependency from UART3 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x158++0x3 line.long 0x0 "PM_L4PER_UART4_WKDEP,This register controls wakeup dependency based on UART4 service requests." bitfld.long 0x0 0. " WKUPDEP_UART4_MPU ,Wakeup dependency from UART4 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_UART4_IPU2 ,Wakeup dependency from UART4 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_UART4_DSP1 ,Wakeup dependency from UART4 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_UART4_SDMA ,Wakeup dependency from UART4 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_UART4_IPU1 ,Wakeup dependency from UART4 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_UART4_DSP2 ,Wakeup dependency from UART4 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_UART4_EVE1 ,Wakeup dependency from UART4 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_UART4_EVE2 ,Wakeup dependency from UART4 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_UART4_EVE3 ,Wakeup dependency from UART4 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_UART4_EVE4 ,Wakeup dependency from UART4 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x160++0x3 line.long 0x0 "PM_L4PER2_MCASP2_WKDEP,This register controls wakeup dependency based on MCASP2 service requests." bitfld.long 0x0 0. " WKUPDEP_MCASP2_IRQ_MPU ,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCASP2_IRQ_IPU2 ,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCASP2_IRQ_DSP1 ,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCASP2_IRQ_IPU1 ,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCASP2_IRQ_DSP2 ,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCASP2_IRQ_EVE1 ,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCASP2_IRQ_EVE2 ,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCASP2_IRQ_EVE3 ,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCASP2_IRQ_EVE4 ,Wakeup dependency from MCASP2 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_MCASP2_DMA_DSP1 ,Wakeup dependency from MCASP2 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_MCASP2_DMA_SDMA ,Wakeup dependency from MCASP2 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_MCASP2_DMA_DSP2 ,Wakeup dependency from MCASP2 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x168++0x3 line.long 0x0 "PM_L4PER2_MCASP3_WKDEP,This register controls wakeup dependency based on MCASP3 service requests." bitfld.long 0x0 0. " WKUPDEP_MCASP3_IRQ_MPU ,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCASP3_IRQ_IPU2 ,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCASP3_IRQ_DSP1 ,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCASP3_IRQ_IPU1 ,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCASP3_IRQ_DSP2 ,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCASP3_IRQ_EVE1 ,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCASP3_IRQ_EVE2 ,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCASP3_IRQ_EVE3 ,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCASP3_IRQ_EVE4 ,Wakeup dependency from MCASP3 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_MCASP3_DMA_DSP1 ,3Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_MCASP3_DMA_SDMA ,Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_MCASP3_DMA_DSP2 ,Wakeup dependency from MCASP3 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x170++0x3 line.long 0x0 "PM_L4PER_UART5_WKDEP,This register controls wakeup dependency based on UART5 service requests." bitfld.long 0x0 0. " WKUPDEP_UART5_MPU ,Wakeup dependency from UART5 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_UART5_IPU2 ,Wakeup dependency from UART5 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_UART5_DSP1 ,Wakeup dependency from UART5 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_UART5_SDMA ,Wakeup dependency from UART5 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_UART5_IPU1 ,Wakeup dependency from UART5 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_UART5_DSP2 ,Wakeup dependency from UART5 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_UART5_EVE1 ,Wakeup dependency from UART5 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_UART5_EVE2 ,Wakeup dependency from UART5 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_UART5_EVE3 ,Wakeup dependency from UART5 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_UART5_EVE4 ,Wakeup dependency from UART5 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x178++0x3 line.long 0x0 "PM_L4PER2_MCASP5_WKDEP,This register controls wakeup dependency based on MCASP5 service requests." bitfld.long 0x0 0. " WKUPDEP_MCASP5_IRQ_MPU ,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCASP5_IRQ_IPU2 ,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCASP5_IRQ_DSP1 ,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCASP5_IRQ_IPU1 ,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCASP5_IRQ_DSP2 ,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCASP5_IRQ_EVE1 ,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCASP5_IRQ_EVE2 ,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCASP5_IRQ_EVE3 ,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCASP5_IRQ_EVE4 ,Wakeup dependency from MCASP5 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_MCASP5_DMA_DSP1 ,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_MCASP5_DMA_SDMA ,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_MCASP5_DMA_DSP2 ,Wakeup dependency from MCASP5 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x180++0x3 line.long 0x0 "PM_L4PER2_MCASP6_WKDEP,This register controls wakeup dependency based on MCASP6 service requests." bitfld.long 0x0 0. " WKUPDEP_MCASP6_IRQ_MPU ,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCASP6_IRQ_IPU2 ,Wakeup dependency from MCASP6 (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCASP6_IRQ_DSP1 ,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCASP6_IRQ_IPU1 ,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCASP6_IRQ_DSP2 ,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCASP6_IRQ_EVE1 ,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCASP6_IRQ_EVE2 ,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCASP6_IRQ_EVE3 ,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCASP6_IRQ_EVE4 ,Wakeup dependency from MCASP6 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_MCASP6_DMA_DSP1 ,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_MCASP6_DMA_SDMA ,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_MCASP6_DMA_DSP2 ,Wakeup dependency from MCASP6 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x188++0x3 line.long 0x0 "PM_L4PER2_MCASP7_WKDEP,This register controls wakeup dependency based on MCASP7 service requests." bitfld.long 0x0 0. " WKUPDEP_MCASP7_IRQ_MPU ,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCASP7_IRQ_IPU2 ,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCASP7_IRQ_DSP1 ,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCASP7_IRQ_IPU1 ,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCASP7_IRQ_DSP2 ,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCASP7_IRQ_EVE1 ,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCASP7_IRQ_EVE2 ,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCASP7_IRQ_EVE3 ,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCASP7_IRQ_EVE4 ,Wakeup dependency from MCASP7 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_MCASP7_DMA_DSP1 ,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_MCASP7_DMA_SDMA ,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_MCASP7_DMA_DSP2 ,Wakeup dependency from MCASP7 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x190++0x3 line.long 0x0 "PM_L4PER2_MCASP8_WKDEP,This register controls wakeup dependency based on MCASP8 service requests." bitfld.long 0x0 0. " WKUPDEP_MCASP8_IRQ_MPU ,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCASP8_IRQ_IPU2 ,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCASP8_IRQ_DSP1 ,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCASP8_IRQ_IPU1 ,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCASP8_IRQ_DSP2 ,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCASP8_IRQ_EVE1 ,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCASP8_IRQ_EVE2 ,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCASP8_IRQ_EVE3 ,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCASP8_IRQ_EVE4 ,Wakeup dependency from MCASP8 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_MCASP8_DMA_DSP1 ,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_MCASP8_DMA_SDMA ,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_MCASP8_DMA_DSP2 ,Wakeup dependency from MCASP8 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x198++0x3 line.long 0x0 "PM_L4PER2_MCASP4_WKDEP,This register controls wakeup dependency based on MCASP4 service requests." bitfld.long 0x0 0. " WKUPDEP_MCASP4_IRQ_MPU ,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_MCASP4_IRQ_IPU2 ,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_MCASP4_IRQ_DSP1 ,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_MCASP4_IRQ_IPU1 ,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_MCASP4_IRQ_DSP2 ,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_MCASP4_IRQ_EVE1 ,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_MCASP4_IRQ_EVE2 ,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_MCASP4_IRQ_EVE3 ,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_MCASP4_IRQ_EVE4 ,Wakeup dependency from MCASP4 module (SWakeup IRQ signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12. " WKUPDEP_MCASP4_DMA_DSP1 ,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 13. " WKUPDEP_MCASP4_DMA_SDMA ,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " WKUPDEP_MCASP4_DMA_DSP2 ,Wakeup dependency from MCASP4 module (SWakeup_dma signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x1D0++0x3 line.long 0x0 "PM_L4PER2_UART7_WKDEP,This register controls wakeup dependency based on UART7 service requests." bitfld.long 0x0 0. " WKUPDEP_UART7_MPU ,Wakeup dependency from UART7 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_UART7_IPU2 ,Wakeup dependency from UART7 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_UART7_DSP1 ,Wakeup dependency from UART7 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_UART7_SDMA ,Wakeup dependency from UART7 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_UART7_IPU1 ,Wakeup dependency from UART7 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_UART7_DSP2 ,Wakeup dependency from UART7 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_UART7_EVE1 ,Wakeup dependency from UART7 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_UART7_EVE2 ,Wakeup dependency from UART7 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_UART7_EVE3 ,Wakeup dependency from UART7 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_UART7_EVE4 ,Wakeup dependency from UART7 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x1E0++0x3 line.long 0x0 "PM_L4PER2_UART8_WKDEP,This register controls wakeup dependency based on UART8 service requests." bitfld.long 0x0 0. " WKUPDEP_UART8_MPU ,Wakeup dependency from UART8 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_UART8_IPU2 ,Wakeup dependency from UART8 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_UART8_DSP1 ,Wakeup dependency from UART8 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_UART8_SDMA ,Wakeup dependency from UART8 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_UART8_IPU1 ,Wakeup dependency from UART8 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_UART8_DSP2 ,Wakeup dependency from UART8 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_UART8_EVE1 ,Wakeup dependency from UART8 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_UART8_EVE2 ,Wakeup dependency from UART8 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_UART8_EVE3 ,Wakeup dependency from UART8 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_UART8_EVE4 ,Wakeup dependency from UART8 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x1E8++0x3 line.long 0x0 "PM_L4PER2_UART9_WKDEP,This register controls wakeup dependency based on UART9 service requests." bitfld.long 0x0 0. " WKUPDEP_UART9_MPU ,Wakeup dependency from UART9 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_UART9_IPU2 ,Wakeup dependency from UART9 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_UART9_DSP1 ,Wakeup dependency from UART9 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_UART9_SDMA ,Wakeup dependency from UART9 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_UART9_IPU1 ,Wakeup dependency from UART9 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_UART9_DSP2 ,Wakeup dependency from UART9 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_UART9_EVE1 ,Wakeup dependency from UART9 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_UART9_EVE2 ,Wakeup dependency from UART9 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_UART9_EVE3 ,Wakeup dependency from UART9 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_UART9_EVE4 ,Wakeup dependency from UART9 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "PM_L4PER2_DCAN2_WKDEP,This register controls wakeup dependency based on DCAN2 service requests." bitfld.long 0x0 0. " WKUPDEP_DCAN2_MPU ,Wakeup dependency from DCAN2 module (SWakeup signal) towards MPU + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 1. " WKUPDEP_DCAN2_IPU2 ,Wakeup dependency from DCAN2 module (SWakeup signal) towards IPU2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 2. " WKUPDEP_DCAN2_DSP1 ,Wakeup dependency from DCAN2 module (SWakeup signal) towards DSP + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 3. " WKUPDEP_DCAN2_SDMA ,Wakeup dependency from DCAN2 module (SWakeup signal) towards SDMA + L3MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 4. " WKUPDEP_DCAN2_IPU1 ,Wakeup dependency from DCAN2 module (SWakeup signal) towards IPU1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 5. " WKUPDEP_DCAN2_DSP2 ,Wakeup dependency from DCAN2 module (SWakeup signal) towards DSP2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 6. " WKUPDEP_DCAN2_EVE1 ,Wakeup dependency from DCAN2 module (SWakeup signal) towards EVE1 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 7. " WKUPDEP_DCAN2_EVE2 ,Wakeup dependency from DCAN2 module (SWakeup signal) towards EVE2 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " bitfld.long 0x0 8. " WKUPDEP_DCAN2_EVE3 ,Wakeup dependency from DCAN2 module (SWakeup signal) towards EVE3 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" bitfld.long 0x0 9. " WKUPDEP_DCAN2_EVE4 ,Wakeup dependency from DCAN2 module (SWakeup signal) towards EVE4 + L3_MAIN1 + L4PER1 + L4PER2 + L4PER3 domains" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE_AON__RESTORE" base ad:0x4A005E00 width 42. group.byte 0x0++0x3 line.long 0x0 "CM_CLKSEL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_CLKSEL_CORE register." group.byte 0x4++0x3 line.long 0x0 "CM_DIV_M2_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_DIV_M2_DPLL_CORE register." group.byte 0x8++0x3 line.long 0x0 "CM_DIV_M3_DPLL_CORE_RESTORE,Second address map for register CM_DIV_M3_DPLL_CORE. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,See CM_DIV_M3_DPLL_CORE register." group.byte 0xC++0x3 line.long 0x0 "CM_DIV_H11_DPLL_CORE_RESTORE,Second address map for register CM_DIV_H11_DPLL_CORE. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,See CM_DIV_H11_DPLL_CORE register." group.byte 0x10++0x3 line.long 0x0 "CM_DIV_H12_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_DIV_H12_DPLL_CORE register." group.byte 0x14++0x3 line.long 0x0 "CM_DIV_H13_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_DIV_H12_DPLL_CORE register." group.byte 0x18++0x3 line.long 0x0 "CM_DIV_H14_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_DIV_H14_DPLL_CORE register." group.byte 0x1C++0x3 line.long 0x0 "CM_DIV_H21_DPLL_CORE_RESTORE,Second address map for register CM_DIV_H21_DPLL_CORE. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,See CM_DIV_H21_DPLL_CORE register." group.byte 0x20++0x3 line.long 0x0 "CM_DIV_H22_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_DIV_H22_DPLL_CORE register." group.byte 0x24++0x3 line.long 0x0 "CM_DIV_H23_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_DIV_H23_DPLL_CORE register." group.byte 0x28++0x3 line.long 0x0 "CM_DIV_H24_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_DIV_H24_DPLL_CORE register." group.byte 0x2C++0x3 line.long 0x0 "CM_CLKSEL_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_CLKSEL_DPLL_CORE register." group.byte 0x30++0x3 line.long 0x0 "CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE,Second address map for register CM_SSC_DELTAMSTEP_DPLL_CORE. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" hexmask.long 0x0 0.--31. 1. " RESTORE ,See CM_SSC_DELTAMSTEP_DPLL_CORE register." group.byte 0x34++0x3 line.long 0x0 "CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE,Second address map for register CM_SSC_MODFREQDIV_DPLL_CORE. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" hexmask.long 0x0 0.--31. 1. " RESTORE ,See CM_SSC_MODFREQDIV_DPLL_CORE register." group.byte 0x38++0x3 line.long 0x0 "CM_CLKMODE_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_CLKMODE_DPLL_CORE register." group.byte 0x3C++0x3 line.long 0x0 "CM_SHADOW_FREQ_CONFIG2_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_SHADOW_FREQ_CONFIG2 register." group.byte 0x40++0x3 line.long 0x0 "CM_SHADOW_FREQ_CONFIG1_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_SHADOW_FREQ_CONFIG1 register." group.byte 0x44++0x3 line.long 0x0 "CM_AUTOIDLE_DPLL_CORE_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,See CM_AUTOIDLE_DPLL_COREregister." group.byte 0x48++0x3 line.long 0x0 "CM_MPU_CLKSTCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_MPU_CLKSTCTRL register." group.byte 0x4C++0x3 line.long 0x0 "CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode. [warm reset insensitive]" hexmask.long 0x0 0.--31. 1. " RESTORE ,SeeCM_CM_CORE_AON_PROFILING_CLKCTRL register." group.byte 0x50++0x3 line.long 0x0 "CM_DYN_DEP_PRESCAL_RESTORE,Second address map for register. Used only by automatic restore upon wakeup from device OFF mode." hexmask.long 0x0 0.--31. 1. " RESTORE ,See CCM_DYN_DEP_PRESCAL register." width 0x0B tree.end tree "DEVICE_PRM" base ad:0x4AE07D00 width 25. group.byte 0x0++0x3 line.long 0x0 "PRM_RSTCTRL,Global software cold and warm reset control. This register is auto-cleared. Only write 1 is possible. A read returns 0 only." bitfld.long 0x0 0. " RST_GLOBAL_WARM_SW ,Global WARM software reset control. This bit is reset upon any global source of reset (warm and cold)." "0,1" bitfld.long 0x0 1. " RST_GLOBAL_COLD_SW ,Global COLD software reset control. This bit is reset only upon a global cold source of reset." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRM_RSTST,This register logs the global reset sources. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " GLOBAL_COLD_RST ,Power-on (cold) reset event" "0,1" bitfld.long 0x0 1. " GLOBAL_WARM_SW_RST ,Global warm software reset event" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ," "0,1" bitfld.long 0x0 3. " MPU_WDT_RST ,WD_TIMER2 and MPU subsystem watchdog reset event. This is a source of global WARM reset." "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5. " EXTERNAL_WARM_RST ,External warm reset event" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " ICEPICK_RST ,IcePick reset event. This is a source of global warm reset initiated by the emulation." "0,1" textline " " bitfld.long 0x0 10. " RESERVED ," "0,1" bitfld.long 0x0 11. " TSHUT_MPU_RST ,TSHUT_MPU warm reset event. This is a source of global WARM reset." "0,1" textline " " bitfld.long 0x0 12. " TSHUT_MM_RST ,TSHUT_GPU warm reset event. This is a source of global WARM reset." "0,1" bitfld.long 0x0 13. " TSHUT_CORE_RST ,TSHUT_CORE warm reset event. This is a source of global WARM reset." "0,1" textline " " bitfld.long 0x0 14. " RESERVED ," "0,1" bitfld.long 0x0 15. " TSHUT_DSPEVE_RST ,TSHUT_DSPEVE warm reset event. This is a source of global WARM reset." "0,1" textline " " bitfld.long 0x0 16. " TSHUT_IVA_RST ,TSHUT_IVA warm reset event. This is a source of global WARM reset." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRM_RSTTIME,Reset duration control. [warm reset insensitive]" hexmask.long.word 0x0 0.--9. 1. " RSTTIME1 ,Global reset duration 1 in number of Func_32k_clk clock cycles. This bit-field is only sensitive to the external power-on reset (WKUPAON_SYS_PWRON_RST reset line)" bitfld.long 0x0 10.--14. " RSTTIME2 ,Power domain reset duration 2 in number of RM.SYSCLK clock cycles." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRM_PSCON_COUNT,This register allows controlling 2 parameters for power state controller. [warm reset insensitive]" hexmask.long.byte 0x0 0.--7. 1. " PCHARGE_TIME ,Number of system clock cycles for the SRAM pre-charge duration. Target is 600ns." hexmask.long.byte 0x0 8.--15. 1. " PONOUT_2_PGOODIN_TIME ,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS. The duration is computed as 8 x NbCycles of system clock cycles. Target is 10us." textline " " hexmask.long.byte 0x0 16.--23. 1. " HG_PONOUT_2_PGOODIN_TIME ,The value 'NbCycles' set in this field determines the duration of the PONOUT to PGOODIN transition for power domain without DPS. The duration is computed as 8 x NbCycles of system clock cycles. Target is 10us." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRM_IO_COUNT,This register allows controlling DDR IO isolation removal setup. [warm reset insensitive]" hexmask.long.byte 0x0 0.--7. 1. " ISO_2_ON_TIME ,Determines the setup time of the DDR IOs going out of isolation. Counting on the system clock. Target is 1.5us." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRM_IO_PMCTRL,This register allows controlling power management features of the IOs." bitfld.long 0x0 0. " ISOCLK_OVERRIDE ,Override control on ISOCLKIN signal to IO pad ring. Used at boot time when it is needed to change the mode of an IO from 1.8V default mode to 1.2V mode. When not overriden, this signal is controlled by hardware only." "0,1" bitfld.long 0x0 1. " ISOCLK_STATUS ,Gives value of ISOCLKOUT signal coming back from IO pad ring." "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " ISOOVR_EXTEND ,Control non-EMIF IO isolation extension upon a device wakeup from OFF mode." "0,1" textline " " bitfld.long 0x0 5. " IO_ON_STATUS ,Gives the functional status of the IO ring." "0,1" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8. " WUCLK_CTRL ,Direct control on WUCLKIN signal to IO pad ring." "0,1" bitfld.long 0x0 9. " WUCLK_STATUS ,Gives value of WUCLKOUT signal coming back from IO pad ring." "0,1" textline " " bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 16. " GLOBAL_WUEN ,Global IO wakeup enable. This is a gating condition to all individual IO WUEN coming from control module. Gating is done in the Spinner logic." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "PRM_SRAM_COUNT,Common setup for SRAM LDO transition counters. Applies to all voltage domains. [warm reset insensitive]" bitfld.long 0x0 0.--5. " PCHARGECNT_VALUE ,Delay between de-assertion of standby_rta_ret_on and standby_rta_ret_good. Counting on system clock. Target is 600ns." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 8.--15. 1. " VSETUPCNT_VALUE ,SRAM LDO rampup time from retention to active mode. The duration is computed as 8 x NbCycles of system clock cycles. Target is 30us." hexmask.long.byte 0x0 16.--23. 1. " SLPCNT_VALUE ,Delay between retention/off assertion of last SRAM bank and SRAMALLRET signal to LDO is driven high. Counting on system clock. Target is 2us." textline " " hexmask.long.byte 0x0 24.--31. 1. " STARTUP_COUNT ,Determines the start-up duration of SRAM and ABB LDO. The duration is computed as 16 x NbCycles of system clock cycles. Target is 50us." group.byte 0xC4++0x3 line.long 0x0 "PRM_SLDO_CORE_SETUP,Setup of the SRAM LDO for CORE voltage domain. [warm reset insensitive]" bitfld.long 0x0 0. " ENABLE_RTA ,Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 1. " ABBOFF_ACT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 2. " ABBOFF_SLEEP ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 3. " ENFUNC1 ,ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 4. " ENFUNC2 ,ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 5. " ENFUNC3 ,ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO." "0,1" bitfld.long 0x0 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO." "0,1" textline " " bitfld.long 0x0 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xC8++0x3 line.long 0x0 "PRM_SLDO_CORE_CTRL,Control and status of the SRAM LDO for CORE voltage domain. [warm reset insensitive]" bitfld.long 0x0 0. " RETMODE_ENABLE ,Control if the SRAM LDO retention mode is used or not." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " SRAMLDO_STATUS ,SRAMLDO status" "0,1" bitfld.long 0x0 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state." "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xCC++0x3 line.long 0x0 "PRM_SLDO_MPU_SETUP,Setup of the SRAM LDO for MPU voltage domain. [warm reset insensitive]" bitfld.long 0x0 0. " ENABLE_RTA ,Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 1. " ABBOFF_ACT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 2. " ABBOFF_SLEEP ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 3. " ENFUNC1 ,ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 4. " ENFUNC2 ,ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 5. " ENFUNC3 ,ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO." "0,1" bitfld.long 0x0 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO." "0,1" textline " " bitfld.long 0x0 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "PRM_SLDO_MPU_CTRL,Control and status of the SRAM LDO for MPU voltage domain. [warm reset insensitive]" bitfld.long 0x0 0. " RETMODE_ENABLE ,Control if the SRAM LDO retention mode is used or not." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " SRAMLDO_STATUS ,SRAMLDO status" "0,1" bitfld.long 0x0 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state." "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xD4++0x3 line.long 0x0 "PRM_SLDO_GPU_SETUP,Setup of the SRAM LDO for GPU voltage domain. [warm reset insensitive]" bitfld.long 0x0 0. " ENABLE_RTA ,Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 1. " ABBOFF_ACT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 2. " ABBOFF_SLEEP ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 3. " ENFUNC1 ,ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 4. " ENFUNC2 ,ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 5. " ENFUNC3 ,ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO." "0,1" bitfld.long 0x0 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO." "0,1" textline " " bitfld.long 0x0 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xD8++0x3 line.long 0x0 "PRM_SLDO_GPU_CTRL,Control and status of the SRAM LDO for GPU voltage domain. [warm reset insensitive]" bitfld.long 0x0 0. " RETMODE_ENABLE ,Control if the SRAM LDO retention mode is used or not." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " SRAMLDO_STATUS ,SRAMLDO status" "0,1" bitfld.long 0x0 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state." "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xDC++0x3 line.long 0x0 "PRM_ABBLDO_MPU_SETUP,Selects the MPU_ABB LDO mode." bitfld.long 0x0 0. " SR2EN ,Enable ABB power management" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " ACTIVE_FBB_SEL ,Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive]" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x0 8.--15. 1. " SR2_WTCNT_VALUE ,LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive]" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "PRM_ABBLDO_MPU_CTRL,Control and Status of ABB on MPU voltage domain. [warm reset insensitive]" bitfld.long 0x0 0.--1. " OPP_SEL ,To control the ABB LDO (FBB/RBB) at a given OPP, set to 0x1. Refer to section ABB LDO Programming sequence." "0,1,2,3" bitfld.long 0x0 2. " OPP_CHANGE ,When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_TRANSITION from VBBLDO_CON is de-asserted." "0,1" textline " " bitfld.long 0x0 3.--4. " SR2_STATUS ,Indicate ABB LDO current operation status" "0,1,2,3" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " SR2_IN_TRANSITION ,Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion." "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xE4++0x3 line.long 0x0 "PRM_ABBLDO_GPU_SETUP,Selects the GPU_ABB LDO mode." bitfld.long 0x0 0. " SR2EN ,Enable ABB power management" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " ACTIVE_FBB_SEL ,Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive]" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x0 8.--15. 1. " SR2_WTCNT_VALUE ,LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive]" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xE8++0x3 line.long 0x0 "PRM_ABBLDO_GPU_CTRL,Control and Status of ABB on GPU voltage domain. [warm reset insensitive]" bitfld.long 0x0 0.--1. " OPP_SEL ,To control the ABB LDO (FBB/RBB) at a given OPP, set to 0x1. Refer to section ABB LDO Programming sequence." "0,1,2,3" bitfld.long 0x0 2. " OPP_CHANGE ,When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_TRANSITION from VBBLDO_CON is de-asserted." "0,1" textline " " bitfld.long 0x0 3.--4. " SR2_STATUS ,Indicate ABB LDO current operation status" "0,1,2,3" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " SR2_IN_TRANSITION ,Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion." "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xEC++0x3 line.long 0x0 "PRM_BANDGAP_SETUP,Setup of the bandgap. [warm reset insensitive]" hexmask.long.byte 0x0 0.--7. 1. " STARTUP_COUNT ,Determines the start-up duration of BANDGAP. The duration is computed as 32 x NbCycles of system clock cycles. Target is 100us." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "PRM_DEVICE_OFF_CTRL,This register is used to control device OFF transition." bitfld.long 0x0 0. " DEVICE_OFF_ENABLE ,Controls transition to device OFF mode." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " EMIF1_OFFWKUP_DISABLE ,Controls the EMIF1_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF2 upon a device wakeup from OFF mode. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " EMIF2_OFFWKUP_DISABLE ,Controls the EMIF2_DEVICE_OFFWKUP_CORESRTACTST notifier sent to EMIF1 upon a device wakeup from OFF mode. [warm reset insensitive]" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xF4++0x3 line.long 0x0 "PRM_PHASE1_CNDP,This register stores the start descriptor address of automatic restore phase1. [warm reset insensitive] NOTE: This register is NOT supported on this device." hexmask.long 0x0 0.--31. 1. " PHASE1_CNDP ,Start descriptor address of automatic restore phase1. Hard-coded to SAR_ROM base address." group.byte 0xF8++0x3 line.long 0x0 "PRM_PHASE2A_CNDP,This register stores the start descriptor address of automatic restore phase2A. [warm reset insensitive] NOTE: This register is NOT supported on this device." hexmask.long 0x0 0.--31. 1. " PHASE2A_CNDP ,Start descriptor address of automatic restore phase2A. Hard-coded to SAR_ROM base address + 0x30." group.byte 0xFC++0x3 line.long 0x0 "PRM_PHASE2B_CNDP,This register stores the start descriptor address of automatic restore phase2B. [warm reset insensitive] NOTE: This register is NOT supported on this device." hexmask.long 0x0 0.--31. 1. " PHASE2B_CNDP ,Start descriptor address of automatic restore phase2B. Hard-coded to SAR_ROM base address + 0x60." group.byte 0x118++0x3 line.long 0x0 "PRM_SLDO_DSPEVE_SETUP,Setup of the SRAM LDO for DSPEVE voltage domain. [warm reset insensitive]" bitfld.long 0x0 0. " ENABLE_RTA ,Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 1. " ABBOFF_ACT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 2. " ABBOFF_SLEEP ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 3. " ENFUNC1 ,ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 4. " ENFUNC2 ,ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 5. " ENFUNC3 ,ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO." "0,1" bitfld.long 0x0 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO." "0,1" textline " " bitfld.long 0x0 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x11C++0x3 line.long 0x0 "PRM_SLDO_IVA_SETUP,Setup of the SRAM LDO for IVA voltage domain. [warm reset insensitive]" bitfld.long 0x0 0. " ENABLE_RTA ,Control for HD memory RTA feature. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 1. " ABBOFF_ACT ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during active mode. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 2. " ABBOFF_SLEEP ,Determines whether SRAMNWA is supplied by VDDS or VDDAR during deep-sleep. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 3. " ENFUNC1 ,ENFUNC1 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 4. " ENFUNC2 ,ENFUNC2 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" bitfld.long 0x0 5. " ENFUNC3 ,ENFUNC3 input of SRAM LDO. After PowerOn reset and Efuse sensing, this bitfield is automatically loaded with an Efuse value from control module. Bitfield remains writable after this." "0,1" textline " " bitfld.long 0x0 6. " ENFUNC4 ,ENFUNC4 input of SRAM LDO." "0,1" bitfld.long 0x0 7. " ENFUNC5 ,ENFUNC5 input of SRAM LDO." "0,1" textline " " bitfld.long 0x0 8. " AIPOFF ,Override on AIPOFF input of SRAM LDO." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x120++0x3 line.long 0x0 "PRM_ABBLDO_DSPEVE_CTRL,Control and Status of ABB on DSPEVE voltage domain. [warm reset insensitive]" bitfld.long 0x0 0.--1. " OPP_SEL ,To control the ABB LDO (FBB/RBB) at a given OPP, set to 0x1. Refer to section ABB LDO Programming sequence." "0,1,2,3" bitfld.long 0x0 2. " OPP_CHANGE ,When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_TRANSITION from VBBLDO_CON is de-asserted." "0,1" textline " " bitfld.long 0x0 3.--4. " SR2_STATUS ,Indicate ABB LDO current operation status" "0,1,2,3" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " SR2_IN_TRANSITION ,Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion." "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "PRM_ABBLDO_IVA_CTRL,Control and Status of ABB on IVA voltage domain. [warm reset insensitive]" bitfld.long 0x0 0.--1. " OPP_SEL ,To control the ABB LDO (FBB/RBB) at a given OPP, set to 0x1. Refer to section ABB LDO Programming sequence." "0,1,2,3" bitfld.long 0x0 2. " OPP_CHANGE ,When OPP_CHANGE is set to 1, VBBLDO_CON samples OPP_SEL ACTIVE_FBB_SEL upon detecting rising edge. VBBLDO_CON asserts signal SR2_IN_TRANSITION in response to OPP_CHANGE. OPP_CHANGE should be cleared to 0 when SR2_IN_TRANSITION from VBBLDO_CON is de-asserted." "0,1" textline " " bitfld.long 0x0 3.--4. " SR2_STATUS ,Indicate ABB LDO current operation status" "0,1,2,3" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " SR2_IN_TRANSITION ,Indicates VBBLDO_CON is or is not in transition state. This output should be used by programming interface to clear OPP_CHANGE bit as an indication of OPP change completion." "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x128++0x3 line.long 0x0 "PRM_SLDO_DSPEVE_CTRL,Control and status of the SRAM LDO for CORE voltage domain. [warm reset insensitive]" bitfld.long 0x0 0. " RETMODE_ENABLE ,Control if the SRAM LDO retention mode is used or not." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " SRAMLDO_STATUS ,SRAMLDO status" "0,1" bitfld.long 0x0 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state." "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x12C++0x3 line.long 0x0 "PRM_SLDO_IVA_CTRL,Control and status of the SRAM LDO for CORE voltage domain. [warm reset insensitive]" bitfld.long 0x0 0. " RETMODE_ENABLE ,Control if the SRAM LDO retention mode is used or not." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " SRAMLDO_STATUS ,SRAMLDO status" "0,1" bitfld.long 0x0 9. " SRAM_IN_TRANSITION ,Status indicating SRAM LDO state machine state." "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "PRM_ABBLDO_DSPEVE_SETUP,Selects the GPU_ABB LDO mode." bitfld.long 0x0 0. " SR2EN ,Enable ABB power management" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " ACTIVE_FBB_SEL ,Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive]" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x0 8.--15. 1. " SR2_WTCNT_VALUE ,LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive]" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x134++0x3 line.long 0x0 "PRM_ABBLDO_IVA_SETUP,Selects the GPU_ABB LDO mode." bitfld.long 0x0 0. " SR2EN ,Enable ABB power management" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " ACTIVE_FBB_SEL ,Defines ABB LDO mode when voltage is in slow fast OPP. [warm reset insensitive]" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x0 8.--15. 1. " SR2_WTCNT_VALUE ,LDO settling time for active-mode OPP change. Counting at a 16 system clock cycles rate. Target is 50us. [warm reset insensitive]" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," width 0x0B tree.end tree "CM_CORE__GPU" base ad:0x4A009200 width 20. group.byte 0x0++0x3 line.long 0x0 "CM_GPU_CLKSTCTRL,This register enables the GPU domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also hold one status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the clock state transition of the GPU clock domain." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 8. " CLKACTIVITY_GPU_L3_GICLK ,This field indicates the state of the GPU_L3_GICLK clock in the domain. [warm reset insensitive]" "0,1" bitfld.long 0x0 9. " CLKACTIVITY_GPU_CORE_GCLK ,This field indicates the state of the GPU_CORE_GCLK clock in the domain. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 10. " CLKACTIVITY_GPU_HYD_GCLK ,This field indicates the state of the GPU_HYD_GCLK clock in the domain. [warm reset insensitive]" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "CM_GPU_STATICDEP,This register controls the static domain depedencies from GPU domain towards 'target' domains. It is relevant only for domain having system initiator(s)." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " IVA_STATDEP ,Static dependency towards IVA clock domain" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " EMIF_STATDEP ,Static dependency towards EMIF clock domain" "0,1" textline " " bitfld.long 0x0 5. " L3MAIN1_STATDEP ,Static dependency towards L3MAIN1 clock domain" "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "CM_GPU_DYNAMICDEP,This register controls the dynamic domain depedencies from GPU domain towards 'target' domains. It is relevant only for domain having OCP master port(s)." bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " L3MAIN1_DYNDEP ,Dynamic dependency towards L3MAIN1 clock domain" "0,1" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CM_GPU_GPU_CLKCTRL,This register manages the GPU clocks." bitfld.long 0x0 0.--1. " MODULEMODE ,Control the way mandatory clocks are managed." "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " IDLEST ,Module idle status. [warm reset insensitive]" "0,1,2,3" bitfld.long 0x0 18. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24.--25. " CLKSEL_CORE_CLK ,Select the source of the functional clock" "0,1,2,3" textline " " bitfld.long 0x0 26.--27. " CLKSEL_HYD_CLK ,Select the source of the functional clock" "0,1,2,3" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "MPU_PRCM_OCP_SOCKET" base ad:0x48243000 width 19. group.byte 0x0++0x3 line.long 0x0 "REVISION_PRCM_MPU,IP Revision register" hexmask.long 0x0 0.--31. 1. "REVISION,IP revision" width 0x0B tree.end tree "MPU_PRCM_CM_C0" base ad:0x48243600 width 22. group.byte 0x0++0x3 line.long 0x0 "CM_CPU0_CLKSTCTRL,This register enables the CPU domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the full domain transition of the CPU domain." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "CM_CPU0_CPU0_CLKCTRL,This register manages the CPU clocks." bitfld.long 0x0 0. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MPU_PRCM_CM_C1" base ad:0x48243A00 width 22. group.byte 0x0++0x3 line.long 0x0 "CM_CPU1_CLKSTCTRL,This register enables the MPU domain power state transition. It controls the HW supervised domain power state transition between ON-ACTIVE and ON-INACTIVE states. It also holds 1 status bit per clock input of the domain." bitfld.long 0x0 0.--1. " CLKTRCTRL ,Controls the full domain transition of the CPU domain." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "CM_CPU1_CPU1_CLKCTRL,This register manages the MPU clocks." bitfld.long 0x0 0. " STBYST ,Module standby status. [warm reset insensitive]" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MPU_AXI2OCP_MISC" base ad:0x482A2000 width 13. group.byte 0x0++0x3 line.long 0x0 "MA_PRIORITY,Memory adapter priority register. This register indicates the priority of memory access from MPU_MA to EMIF. This priority is used by EMIF in scheduling MPU_MA access to EMIF. 0x0 is highest priority and 0x7 is lowest priority." bitfld.long 0x0 0.--2. " PRIORITY ,MPU_MA priority value" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " HIMEM_INTERLEAVE_UN ,HIMEM_INTERLEAVE_UN" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MPU_PRCM_PRM_C0" base ad:0x48243400 width 22. group.byte 0x0++0x3 line.long 0x0 "PM_CPU0_PWRSTCTRL,This register controls the CPU domain power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "0,1" textline " " bitfld.long 0x0 3.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8. " L1_BANK_RETSTATE ,CPU_L1 memory state when domain is RETENTION." "0,1" textline " " hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--17. " L1_BANK_ONSTATE ,CPU_L1 memory state when domain is ON." "0,1,2,3" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "PM_CPU0_PWRSTST,This register provides a status on the CPU domain current power state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 4.--5. " L1_BANK_STATEST ,CPU_L1 memory state status" "0,1,2,3" textline " " hexmask.long.word 0x0 6.--19. 1. " RESERVED ,Reserved" bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low power state entered" "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_CPU0_CPU0_RSTCTRL,This register controls the assertion/release of the CPU CORE reset." bitfld.long 0x0 0. " RST ,CPU warm local reset control" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "RM_CPU0_CPU0_RSTST,This register logs the different reset sources of the MPU domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RSTST ,MPU_C0 software reset" "0,1" bitfld.long 0x0 1. " DBGRST_REQ_RSTST ,MPU_C0 processor has been reset due to MPU_C0 emulation reset request driven from MPUSS." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "RM_CPU0_CPU0_CONTEXT,This register contains dedicated CPU context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 8. " LOSTMEM_CPU_L1 ,Specify if memory-based context in CPU_L1 memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MPU_PRCM_PRM_C1" base ad:0x48243800 width 22. group.byte 0x0++0x3 line.long 0x0 "PM_CPU1_PWRSTCTRL,This register controls the CPU domain power state to reach upon a domain sleep transition" bitfld.long 0x0 0.--1. " POWERSTATE ,Power state control" "0,1,2,3" bitfld.long 0x0 2. " LOGICRETSTATE ,Logic state when power domain is RETENTION" "0,1" textline " " bitfld.long 0x0 3.--6. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 7. " FORCED_OFF ,Selects if logic must be forced in OFF state." "0,1" textline " " bitfld.long 0x0 8. " L1_BANK_RETSTATE ,CPU L1 memory state when domain is RETENTION." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--17. " L1_BANK_ONSTATE ,CPU_L1 memory state when domain is ON." "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "PM_CPU1_PWRSTST,This register provides a status on the CPU domain current power state. [warm reset insensitive]" bitfld.long 0x0 0.--1. " POWERSTATEST ,Current power state status" "0,1,2,3" bitfld.long 0x0 2. " LOGICSTATEST ,Logic state status" "0,1" textline " " bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 4.--5. " L1_BANK_STATEST ,CPU_L1 memory state status" "0,1,2,3" textline " " hexmask.long.word 0x0 6.--19. 1. " RESERVED ,Reserved" bitfld.long 0x0 20. " INTRANSITION ,Domain transition status" "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " LASTPOWERSTATEENTERED ,Last low-power state entered" "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "RM_CPU1_CPU1_RSTCTRL,This register controls the assertion/release of the CPU CORE reset." bitfld.long 0x0 0. " RST ,CPU warm local reset control" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "RM_CPU1_CPU1_RSTST,This register logs the different reset sources of the MPU domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" bitfld.long 0x0 0. " RSTST ,MPU_C1 software reset" "0,1" bitfld.long 0x0 1. " DBGRST_REQ_RSTST ,MPU_C1 processor has been reset due to MPU_C0 emulation reset request driven from MPUSS" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "RM_CPU1_CPU1_CONTEXT,This register contains dedicated CPU context statuses. [warm reset insensitive]" bitfld.long 0x0 0. " LOSTCONTEXT_DFF ,Specify if DFF-based context has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 8. " LOSTMEM_CPU_L1 ,Specify if memory-based context in CPU_L1 memory bank has been lost due to a previous power transition or other reset source." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MPU_WUGEN" base ad:0x48281000 width 18. group.byte 0x0++0x3 line.long 0x0 "WKG_CONTROL_0,Wake-up generator control and status register for MPU_C0" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Reserved" bitfld.long 0x0 8. " STANDBYWFI ,This bit gives software the visibility to track whether WFI mode have been entered. 0x0: WFI mode has not been entered 0x1: WFI mode has been entered" "0,1" textline " " bitfld.long 0x0 9. " STANDBYWFE ,This bit gives software the visibility to track whether WFE mode have been entered. 0x0: WFE mode has not been entered 0x1: WFE mode has been entered" "0,1" bitfld.long 0x0 10. " EVENTO ,EVENTO status bit. The event output signal is active, when one SEV instruction is executed. This bit is set when a rising edge of EVENTO from CPU is detected. 0x0: Rising edge of EVENTO is not detected 0x1: Rising edge of EVENTO is detected" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 13. " MPU_COLD_RESET ,This bit is set when the MPU_COLD_RESET signal is asserted. 0x0: MPU_COLD_RESET reset signal has not been asserted 0x1: MPU_COLD_RESET reset request has been asserted" "0,1" textline " " bitfld.long 0x0 14. " MPU_WARM_RESET ,This bit is set when the MPU_WARM_RESET signal is asserted. 0x0: MPU_WARM_RESET reset signal has not been asserted 0x1: MPU_WARM_RESET reset request has been asserted" "0,1" bitfld.long 0x0 15. " DOMAINRESET ,MPU always-on power domain (PD_MPUAON) reset status bit. It shows if the reset occurred previously. 0x0: no reset occur 0x1: reset occur" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "WKG_ENB_A_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_0 to MPU_IRQ_31). Write 0x0: Disable interrupt. Write 0x1: Enable interrupt." bitfld.long 0x0 0. " WKG_ENB_FOR_INTR0 ,Wakeup enable for interrupt line MPU_IRQ_0" "0,1" bitfld.long 0x0 1. " WKG_ENB_FOR_INTR1 ,Wakeup enable for interrupt line MPU_IRQ_1" "0,1" textline " " bitfld.long 0x0 2. " WKG_ENB_FOR_INTR2 ,Wakeup enable for interrupt line MPU_IRQ_2" "0,1" bitfld.long 0x0 3. " WKG_ENB_FOR_INTR3 ,Wakeup enable for interrupt line MPU_IRQ_3" "0,1" textline " " bitfld.long 0x0 4. " WKG_ENB_FOR_INTR4 ,Wakeup enable for interrupt line MPU_IRQ_4" "0,1" bitfld.long 0x0 5. " WKG_ENB_FOR_INTR5 ,Wakeup enable for interrupt line MPU_IRQ_5" "0,1" textline " " bitfld.long 0x0 6. " WKG_ENB_FOR_INTR6 ,Wakeup enable for interrupt line MPU_IRQ_6" "0,1" bitfld.long 0x0 7. " WKG_ENB_FOR_INTR7 ,Wakeup enable for interrupt line MPU_IRQ_7" "0,1" textline " " bitfld.long 0x0 8. " WKG_ENB_FOR_INTR8 ,Wakeup enable for interrupt line MPU_IRQ_8" "0,1" bitfld.long 0x0 9. " WKG_ENB_FOR_INTR9 ,Wakeup enable for interrupt line MPU_IRQ_9" "0,1" textline " " bitfld.long 0x0 10. " WKG_ENB_FOR_INTR10 ,Wakeup enable for interrupt line MPU_IRQ_10" "0,1" bitfld.long 0x0 11. " WKG_ENB_FOR_INTR11 ,Wakeup enable for interrupt line MPU_IRQ_11" "0,1" textline " " bitfld.long 0x0 12. " WKG_ENB_FOR_INTR12 ,Wakeup enable for interrupt line MPU_IRQ_12" "0,1" bitfld.long 0x0 13. " WKG_ENB_FOR_INTR13 ,Wakeup enable for interrupt line MPU_IRQ_13" "0,1" textline " " bitfld.long 0x0 14. " WKG_ENB_FOR_INTR14 ,Wakeup enable for interrupt line MPU_IRQ_14" "0,1" bitfld.long 0x0 15. " WKG_ENB_FOR_INTR15 ,Wakeup enable for interrupt line MPU_IRQ_15" "0,1" textline " " bitfld.long 0x0 16. " WKG_ENB_FOR_INTR16 ,Wakeup enable for interrupt line MPU_IRQ_16" "0,1" bitfld.long 0x0 17. " WKG_ENB_FOR_INTR17 ,Wakeup enable for interrupt line MPU_IRQ_17" "0,1" textline " " bitfld.long 0x0 18. " WKG_ENB_FOR_INTR18 ,Wakeup enable for interrupt line MPU_IRQ_18" "0,1" bitfld.long 0x0 19. " WKG_ENB_FOR_INTR19 ,Wakeup enable for interrupt line MPU_IRQ_19" "0,1" textline " " bitfld.long 0x0 20. " WKG_ENB_FOR_INTR20 ,Wakeup enable for interrupt line MPU_IRQ_20" "0,1" bitfld.long 0x0 21. " WKG_ENB_FOR_INTR21 ,Wakeup enable for interrupt line MPU_IRQ_21" "0,1" textline " " bitfld.long 0x0 22. " WKG_ENB_FOR_INTR22 ,Wakeup enable for interrupt line MPU_IRQ_22" "0,1" bitfld.long 0x0 23. " WKG_ENB_FOR_INTR23 ,Wakeup enable for interrupt line MPU_IRQ_23" "0,1" textline " " bitfld.long 0x0 24. " WKG_ENB_FOR_INTR24 ,Wakeup enable for interrupt line MPU_IRQ_24" "0,1" bitfld.long 0x0 25. " WKG_ENB_FOR_INTR25 ,Wakeup enable for interrupt line MPU_IRQ_25" "0,1" textline " " bitfld.long 0x0 26. " WKG_ENB_FOR_INTR26 ,Wakeup enable for interrupt line MPU_IRQ_26" "0,1" bitfld.long 0x0 27. " WKG_ENB_FOR_INTR27 ,Wakeup enable for interrupt line MPU_IRQ_27" "0,1" textline " " bitfld.long 0x0 28. " WKG_ENB_FOR_INTR28 ,Wakeup enable for interrupt line MPU_IRQ_28" "0,1" bitfld.long 0x0 29. " WKG_ENB_FOR_INTR29 ,Wakeup enable for interrupt line MPU_IRQ_29" "0,1" textline " " bitfld.long 0x0 30. " WKG_ENB_FOR_INTR30 ,Wakeup enable for interrupt line MPU_IRQ_30" "0,1" bitfld.long 0x0 31. " WKG_ENB_FOR_INTR31 ,Wakeup enable for interrupt line MPU_IRQ_31" "0,1" group.byte 0x14++0x3 line.long 0x0 "WKG_ENB_B_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_32 to MPU_IRQ_63). Write 0x0: Disable interrupt. Write 0x1: Enable interrupt." bitfld.long 0x0 0. " WKG_ENB_FOR_INTR32 ,Wakeup enable for interrupt line MPU_IRQ_32" "0,1" bitfld.long 0x0 1. " WKG_ENB_FOR_INTR33 ,Wakeup enable for interrupt line MPU_IRQ_33" "0,1" textline " " bitfld.long 0x0 2. " WKG_ENB_FOR_INTR34 ,Wakeup enable for interrupt line MPU_IRQ_34" "0,1" bitfld.long 0x0 3. " WKG_ENB_FOR_INTR35 ,Wakeup enable for interrupt line MPU_IRQ_35" "0,1" textline " " bitfld.long 0x0 4. " WKG_ENB_FOR_INTR36 ,Wakeup enable for interrupt line MPU_IRQ_36" "0,1" bitfld.long 0x0 5. " WKG_ENB_FOR_INTR37 ,Wakeup enable for interrupt line MPU_IRQ_37" "0,1" textline " " bitfld.long 0x0 6. " WKG_ENB_FOR_INTR38 ,Wakeup enable for interrupt line MPU_IRQ_38" "0,1" bitfld.long 0x0 7. " WKG_ENB_FOR_INTR39 ,Wakeup enable for interrupt line MPU_IRQ_39" "0,1" textline " " bitfld.long 0x0 8. " WKG_ENB_FOR_INTR40 ,Wakeup enable for interrupt line MPU_IRQ_40" "0,1" bitfld.long 0x0 9. " WKG_ENB_FOR_INTR41 ,Wakeup enable for interrupt line MPU_IRQ_41" "0,1" textline " " bitfld.long 0x0 10. " WKG_ENB_FOR_INTR42 ,Wakeup enable for interrupt line MPU_IRQ_42" "0,1" bitfld.long 0x0 11. " WKG_ENB_FOR_INTR43 ,Wakeup enable for interrupt line MPU_IRQ_43" "0,1" textline " " bitfld.long 0x0 12. " WKG_ENB_FOR_INTR44 ,Wakeup enable for interrupt line MPU_IRQ_44" "0,1" bitfld.long 0x0 13. " WKG_ENB_FOR_INTR45 ,Wakeup enable for interrupt line MPU_IRQ_45" "0,1" textline " " bitfld.long 0x0 14. " WKG_ENB_FOR_INTR46 ,Wakeup enable for interrupt line MPU_IRQ_46" "0,1" bitfld.long 0x0 15. " WKG_ENB_FOR_INTR47 ,Wakeup enable for interrupt line MPU_IRQ_47" "0,1" textline " " bitfld.long 0x0 16. " WKG_ENB_FOR_INTR48 ,Wakeup enable for interrupt line MPU_IRQ_48" "0,1" bitfld.long 0x0 17. " WKG_ENB_FOR_INTR49 ,Wakeup enable for interrupt line MPU_IRQ_49" "0,1" textline " " bitfld.long 0x0 18. " WKG_ENB_FOR_INTR50 ,Wakeup enable for interrupt line MPU_IRQ_50" "0,1" bitfld.long 0x0 19. " WKG_ENB_FOR_INTR51 ,Wakeup enable for interrupt line MPU_IRQ_51" "0,1" textline " " bitfld.long 0x0 20. " WKG_ENB_FOR_INTR52 ,Wakeup enable for interrupt line MPU_IRQ_52" "0,1" bitfld.long 0x0 21. " WKG_ENB_FOR_INTR53 ,Wakeup enable for interrupt line MPU_IRQ_53" "0,1" textline " " bitfld.long 0x0 22. " WKG_ENB_FOR_INTR54 ,Wakeup enable for interrupt line MPU_IRQ_54" "0,1" bitfld.long 0x0 23. " WKG_ENB_FOR_INTR55 ,Wakeup enable for interrupt line MPU_IRQ_55" "0,1" textline " " bitfld.long 0x0 24. " WKG_ENB_FOR_INTR56 ,Wakeup enable for interrupt line MPU_IRQ_56" "0,1" bitfld.long 0x0 25. " WKG_ENB_FOR_INTR57 ,Wakeup enable for interrupt line MPU_IRQ_57" "0,1" textline " " bitfld.long 0x0 26. " WKG_ENB_FOR_INTR58 ,Wakeup enable for interrupt line MPU_IRQ_58" "0,1" bitfld.long 0x0 27. " WKG_ENB_FOR_INTR59 ,Wakeup enable for interrupt line MPU_IRQ_59" "0,1" textline " " bitfld.long 0x0 28. " WKG_ENB_FOR_INTR60 ,Wakeup enable for interrupt line MPU_IRQ_60" "0,1" bitfld.long 0x0 29. " WKG_ENB_FOR_INTR61 ,Wakeup enable for interrupt line MPU_IRQ_61" "0,1" textline " " bitfld.long 0x0 30. " WKG_ENB_FOR_INTR62 ,Wakeup enable for interrupt line MPU_IRQ_62" "0,1" bitfld.long 0x0 31. " WKG_ENB_FOR_INTR63 ,Wakeup enable for interrupt line MPU_IRQ_63" "0,1" group.byte 0x18++0x3 line.long 0x0 "WKG_ENB_C_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_64 to MPU_IRQ_95). Write 0x0: Disable interrupt. Write 0x1: Enable interrupt." bitfld.long 0x0 0. " WKG_ENB_FOR_INTR64 ,Wakeup enable for interrupt line MPU_IRQ_64" "0,1" bitfld.long 0x0 1. " WKG_ENB_FOR_INTR65 ,Wakeup enable for interrupt line MPU_IRQ_65" "0,1" textline " " bitfld.long 0x0 2. " WKG_ENB_FOR_INTR66 ,Wakeup enable for interrupt line MPU_IRQ_66" "0,1" bitfld.long 0x0 3. " WKG_ENB_FOR_INTR67 ,Wakeup enable for interrupt line MPU_IRQ_67" "0,1" textline " " bitfld.long 0x0 4. " WKG_ENB_FOR_INTR68 ,Wakeup enable for interrupt line MPU_IRQ_68" "0,1" bitfld.long 0x0 5. " WKG_ENB_FOR_INTR69 ,Wakeup enable for interrupt line MPU_IRQ_69" "0,1" textline " " bitfld.long 0x0 6. " WKG_ENB_FOR_INTR70 ,Wakeup enable for interrupt line MPU_IRQ_70" "0,1" bitfld.long 0x0 7. " WKG_ENB_FOR_INTR71 ,Wakeup enable for interrupt line MPU_IRQ_71" "0,1" textline " " bitfld.long 0x0 8. " WKG_ENB_FOR_INTR72 ,Wakeup enable for interrupt line MPU_IRQ_72" "0,1" bitfld.long 0x0 9. " WKG_ENB_FOR_INTR73 ,Wakeup enable for interrupt line MPU_IRQ_73" "0,1" textline " " bitfld.long 0x0 10. " WKG_ENB_FOR_INTR74 ,Wakeup enable for interrupt line MPU_IRQ_74" "0,1" bitfld.long 0x0 11. " WKG_ENB_FOR_INTR75 ,Wakeup enable for interrupt line MPU_IRQ_75" "0,1" textline " " bitfld.long 0x0 12. " WKG_ENB_FOR_INTR76 ,Wakeup enable for interrupt line MPU_IRQ_76" "0,1" bitfld.long 0x0 13. " WKG_ENB_FOR_INTR77 ,Wakeup enable for interrupt line MPU_IRQ_77" "0,1" textline " " bitfld.long 0x0 14. " WKG_ENB_FOR_INTR78 ,Wakeup enable for interrupt line MPU_IRQ_78" "0,1" bitfld.long 0x0 15. " WKG_ENB_FOR_INTR79 ,Wakeup enable for interrupt line MPU_IRQ_79" "0,1" textline " " bitfld.long 0x0 16. " WKG_ENB_FOR_INTR80 ,Wakeup enable for interrupt line MPU_IRQ_80" "0,1" bitfld.long 0x0 17. " WKG_ENB_FOR_INTR81 ,Wakeup enable for interrupt line MPU_IRQ_81" "0,1" textline " " bitfld.long 0x0 18. " WKG_ENB_FOR_INTR82 ,Wakeup enable for interrupt line MPU_IRQ_82" "0,1" bitfld.long 0x0 19. " WKG_ENB_FOR_INTR83 ,Wakeup enable for interrupt line MPU_IRQ_83" "0,1" textline " " bitfld.long 0x0 20. " WKG_ENB_FOR_INTR84 ,Wakeup enable for interrupt line MPU_IRQ_84" "0,1" bitfld.long 0x0 21. " WKG_ENB_FOR_INTR85 ,Wakeup enable for interrupt line MPU_IRQ_85" "0,1" textline " " bitfld.long 0x0 22. " WKG_ENB_FOR_INTR86 ,Wakeup enable for interrupt line MPU_IRQ_86" "0,1" bitfld.long 0x0 23. " WKG_ENB_FOR_INTR87 ,Wakeup enable for interrupt line MPU_IRQ_87" "0,1" textline " " bitfld.long 0x0 24. " WKG_ENB_FOR_INTR88 ,Wakeup enable for interrupt line MPU_IRQ_88" "0,1" bitfld.long 0x0 25. " WKG_ENB_FOR_INTR89 ,Wakeup enable for interrupt line MPU_IRQ_89" "0,1" textline " " bitfld.long 0x0 26. " WKG_ENB_FOR_INTR90 ,Wakeup enable for interrupt line MPU_IRQ_90" "0,1" bitfld.long 0x0 27. " WKG_ENB_FOR_INTR91 ,Wakeup enable for interrupt line MPU_IRQ_91" "0,1" textline " " bitfld.long 0x0 28. " WKG_ENB_FOR_INTR92 ,Wakeup enable for interrupt line MPU_IRQ_92" "0,1" bitfld.long 0x0 29. " WKG_ENB_FOR_INTR93 ,Wakeup enable for interrupt line MPU_IRQ_93" "0,1" textline " " bitfld.long 0x0 30. " WKG_ENB_FOR_INTR94 ,Wakeup enable for interrupt line MPU_IRQ_94" "0,1" bitfld.long 0x0 31. " WKG_ENB_FOR_INTR95 ,Wakeup enable for interrupt line MPU_IRQ_95" "0,1" group.byte 0x1C++0x3 line.long 0x0 "WKG_ENB_D_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_96 to MPU_IRQ_127). Write 0x0: Disable interrupt. Write 0x1: Enable interrupt." bitfld.long 0x0 0. " WKG_ENB_FOR_INTR96 ,Wakeup enable for interrupt line MPU_IRQ_96" "0,1" bitfld.long 0x0 1. " WKG_ENB_FOR_INTR97 ,Wakeup enable for interrupt line MPU_IRQ_97" "0,1" textline " " bitfld.long 0x0 2. " WKG_ENB_FOR_INTR98 ,Wakeup enable for interrupt line MPU_IRQ_98" "0,1" bitfld.long 0x0 3. " WKG_ENB_FOR_INTR99 ,Wakeup enable for interrupt line MPU_IRQ_99" "0,1" textline " " bitfld.long 0x0 4. " WKG_ENB_FOR_INTR100 ,Wakeup enable for interrupt line MPU_IRQ_100" "0,1" bitfld.long 0x0 5. " WKG_ENB_FOR_INTR101 ,Wakeup enable for interrupt line MPU_IRQ_101" "0,1" textline " " bitfld.long 0x0 6. " WKG_ENB_FOR_INTR102 ,Wakeup enable for interrupt line MPU_IRQ_102" "0,1" bitfld.long 0x0 7. " WKG_ENB_FOR_INTR103 ,Wakeup enable for interrupt line MPU_IRQ_103" "0,1" textline " " bitfld.long 0x0 8. " WKG_ENB_FOR_INTR104 ,Wakeup enable for interrupt line MPU_IRQ_104" "0,1" bitfld.long 0x0 9. " WKG_ENB_FOR_INTR105 ,Wakeup enable for interrupt line MPU_IRQ_105" "0,1" textline " " bitfld.long 0x0 10. " WKG_ENB_FOR_INTR106 ,Wakeup enable for interrupt line MPU_IRQ_106" "0,1" bitfld.long 0x0 11. " WKG_ENB_FOR_INTR107 ,Wakeup enable for interrupt line MPU_IRQ_107" "0,1" textline " " bitfld.long 0x0 12. " WKG_ENB_FOR_INTR108 ,Wakeup enable for interrupt line MPU_IRQ_108" "0,1" bitfld.long 0x0 13. " WKG_ENB_FOR_INTR109 ,Wakeup enable for interrupt line MPU_IRQ_109" "0,1" textline " " bitfld.long 0x0 14. " WKG_ENB_FOR_INTR110 ,Wakeup enable for interrupt line MPU_IRQ_110" "0,1" bitfld.long 0x0 15. " WKG_ENB_FOR_INTR111 ,Wakeup enable for interrupt line MPU_IRQ_111" "0,1" textline " " bitfld.long 0x0 16. " WKG_ENB_FOR_INTR112 ,Wakeup enable for interrupt line MPU_IRQ_112" "0,1" bitfld.long 0x0 17. " WKG_ENB_FOR_INTR113 ,Wakeup enable for interrupt line MPU_IRQ_113" "0,1" textline " " bitfld.long 0x0 18. " WKG_ENB_FOR_INTR114 ,Wakeup enable for interrupt line MPU_IRQ_114" "0,1" bitfld.long 0x0 19. " WKG_ENB_FOR_INTR115 ,Wakeup enable for interrupt line MPU_IRQ_115" "0,1" textline " " bitfld.long 0x0 20. " WKG_ENB_FOR_INTR116 ,Wakeup enable for interrupt line MPU_IRQ_116" "0,1" bitfld.long 0x0 21. " WKG_ENB_FOR_INTR117 ,Wakeup enable for interrupt line MPU_IRQ_117" "0,1" textline " " bitfld.long 0x0 22. " WKG_ENB_FOR_INTR118 ,Wakeup enable for interrupt line MPU_IRQ_118" "0,1" bitfld.long 0x0 23. " WKG_ENB_FOR_INTR119 ,Wakeup enable for interrupt line MPU_IRQ_119" "0,1" textline " " bitfld.long 0x0 24. " WKG_ENB_FOR_INTR120 ,Wakeup enable for interrupt line MPU_IRQ_120" "0,1" bitfld.long 0x0 25. " WKG_ENB_FOR_INTR121 ,Wakeup enable for interrupt line MPU_IRQ_121" "0,1" textline " " bitfld.long 0x0 26. " WKG_ENB_FOR_INTR122 ,Wakeup enable for interrupt line MPU_IRQ_122" "0,1" bitfld.long 0x0 27. " WKG_ENB_FOR_INTR123 ,Wakeup enable for interrupt line MPU_IRQ_123" "0,1" textline " " bitfld.long 0x0 28. " WKG_ENB_FOR_INTR124 ,Wakeup enable for interrupt line MPU_IRQ_124" "0,1" bitfld.long 0x0 29. " WKG_ENB_FOR_INTR125 ,Wakeup enable for interrupt line MPU_IRQ_125" "0,1" textline " " bitfld.long 0x0 30. " WKG_ENB_FOR_INTR126 ,Wakeup enable for interrupt line MPU_IRQ_126" "0,1" bitfld.long 0x0 31. " WKG_ENB_FOR_INTR127 ,Wakeup enable for interrupt line MPU_IRQ_127" "0,1" group.byte 0x20++0x3 line.long 0x0 "WKG_ENB_E_0,Wake-up interrupt enable register for MPU_C0 (interrupts MPU_IRQ_128 to MPU_IRQ_159). Write 0x0: Disable interrupt. Write 0x1: Enable interrupt." bitfld.long 0x0 0. " WKG_ENB_FOR_INTR128 ,Wakeup enable for interrupt line MPU_IRQ_128" "0,1" bitfld.long 0x0 1. " WKG_ENB_FOR_INTR129 ,Wakeup enable for interrupt line MPU_IRQ_129" "0,1" textline " " bitfld.long 0x0 2. " WKG_ENB_FOR_INTR130 ,Wakeup enable for interrupt line MPU_IRQ_130" "0,1" bitfld.long 0x0 3. " WKG_ENB_FOR_INTR131 ,Wakeup enable for interrupt line MPU_IRQ_131" "0,1" textline " " bitfld.long 0x0 4. " WKG_ENB_FOR_INTR132 ,Wakeup enable for interrupt line MPU_IRQ_132" "0,1" bitfld.long 0x0 5. " WKG_ENB_FOR_INTR133 ,Wakeup enable for interrupt line MPU_IRQ_133" "0,1" textline " " bitfld.long 0x0 6. " WKG_ENB_FOR_INTR134 ,Wakeup enable for interrupt line MPU_IRQ_134" "0,1" bitfld.long 0x0 7. " WKG_ENB_FOR_INTR135 ,Wakeup enable for interrupt line MPU_IRQ_135" "0,1" textline " " bitfld.long 0x0 8. " WKG_ENB_FOR_INTR136 ,Wakeup enable for interrupt line MPU_IRQ_136" "0,1" bitfld.long 0x0 9. " WKG_ENB_FOR_INTR137 ,Wakeup enable for interrupt line MPU_IRQ_137" "0,1" textline " " bitfld.long 0x0 10. " WKG_ENB_FOR_INTR138 ,Wakeup enable for interrupt line MPU_IRQ_138" "0,1" bitfld.long 0x0 11. " WKG_ENB_FOR_INTR139 ,Wakeup enable for interrupt line MPU_IRQ_139" "0,1" textline " " bitfld.long 0x0 12. " WKG_ENB_FOR_INTR140 ,Wakeup enable for interrupt line MPU_IRQ_140" "0,1" bitfld.long 0x0 13. " WKG_ENB_FOR_INTR141 ,Wakeup enable for interrupt line MPU_IRQ_141" "0,1" textline " " bitfld.long 0x0 14. " WKG_ENB_FOR_INTR142 ,Wakeup enable for interrupt line MPU_IRQ_142" "0,1" bitfld.long 0x0 15. " WKG_ENB_FOR_INTR143 ,Wakeup enable for interrupt line MPU_IRQ_143" "0,1" textline " " bitfld.long 0x0 16. " WKG_ENB_FOR_INTR144 ,Wakeup enable for interrupt line MPU_IRQ_144" "0,1" bitfld.long 0x0 17. " WKG_ENB_FOR_INTR145 ,Wakeup enable for interrupt line MPU_IRQ_145" "0,1" textline " " bitfld.long 0x0 18. " WKG_ENB_FOR_INTR146 ,Wakeup enable for interrupt line MPU_IRQ_146" "0,1" bitfld.long 0x0 19. " WKG_ENB_FOR_INTR147 ,Wakeup enable for interrupt line MPU_IRQ_147" "0,1" textline " " bitfld.long 0x0 20. " WKG_ENB_FOR_INTR148 ,Wakeup enable for interrupt line MPU_IRQ_148" "0,1" bitfld.long 0x0 21. " WKG_ENB_FOR_INTR149 ,Wakeup enable for interrupt line MPU_IRQ_149" "0,1" textline " " bitfld.long 0x0 22. " WKG_ENB_FOR_INTR150 ,Wakeup enable for interrupt line MPU_IRQ_150" "0,1" bitfld.long 0x0 23. " WKG_ENB_FOR_INTR151 ,Wakeup enable for interrupt line MPU_IRQ_151" "0,1" textline " " bitfld.long 0x0 24. " WKG_ENB_FOR_INTR152 ,Wakeup enable for interrupt line MPU_IRQ_152" "0,1" bitfld.long 0x0 25. " WKG_ENB_FOR_INTR153 ,Wakeup enable for interrupt line MPU_IRQ_153" "0,1" textline " " bitfld.long 0x0 26. " WKG_ENB_FOR_INTR154 ,Wakeup enable for interrupt line MPU_IRQ_154" "0,1" bitfld.long 0x0 27. " WKG_ENB_FOR_INTR155 ,Wakeup enable for interrupt line MPU_IRQ_155" "0,1" textline " " bitfld.long 0x0 28. " WKG_ENB_FOR_INTR156 ,Wakeup enable for interrupt line MPU_IRQ_156" "0,1" bitfld.long 0x0 29. " WKG_ENB_FOR_INTR157 ,Wakeup enable for interrupt line MPU_IRQ_157" "0,1" textline " " bitfld.long 0x0 30. " WKG_ENB_FOR_INTR158 ,Wakeup enable for interrupt line MPU_IRQ_158" "0,1" bitfld.long 0x0 31. " WKG_ENB_FOR_INTR159 ,Wakeup enable for interrupt line MPU_IRQ_159" "0,1" group.byte 0x400++0x3 line.long 0x0 "WKG_CONTROL_1,Wake-up generator control and status register for MPU_C1" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Reserved" bitfld.long 0x0 8. " STANDBYWFI ,This bit gives software the visibility to track whether WFI mode have been entered. 0x0: WFI mode has not been entered. 0x1: WFI mode has been entered." "0,1" textline " " bitfld.long 0x0 9. " STANDBYWFE ,This bit gives software the visibility to track whether WFE mode have been entered. 0x0: WFE mode has not been entered. 0x1: WFE mode has been entered." "0,1" bitfld.long 0x0 10. " EVENTO ,EVENTO status bit. The event output signal is active, when one SEV instruction is executed. This bit is set when a rising edge of EVENTO from CPU is detected. 0x0: Rising edge of EVENTO is not detected. 0x1: Rising edge of EVENTO is detected." "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 13. " MPU_COLD_RESET ,This bit is set when the MPU_COLD_RESET signal is asserted. 0x0: MPU_COLD_RESET reset signal has not been asserted. 0x1: MPU_COLD_RESET reset request has been asserted." "0,1" textline " " bitfld.long 0x0 14. " MPU_WARM_RESET ,This bit is set when the MPU_WARM_RESET signal is asserted. 0x0: MPU_WARM_RESET reset signal has not been asserted. 0x1: MPU_WARM_RESET reset request has been asserted." "0,1" bitfld.long 0x0 15. " DOMAINRESET ,MPU always-on power domain (PD_MPUAON) reset status bit. It shows if the reset occurred previously. 0x0: No reset occurred. 0x1: Reset occurred." "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x410++0x3 line.long 0x0 "WKG_ENB_A_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_0 to MPU_IRQ_31). Write 0x0: Disable interrupt. Write 0x1: Enable interrupt." bitfld.long 0x0 0. " WKG_ENB_FOR_INTR0 ,Wakeup enable for interrupt line MPU_IRQ_0" "0,1" bitfld.long 0x0 1. " WKG_ENB_FOR_INTR1 ,Wakeup enable for interrupt line MPU_IRQ_1" "0,1" textline " " bitfld.long 0x0 2. " WKG_ENB_FOR_INTR2 ,Wakeup enable for interrupt line MPU_IRQ_2" "0,1" bitfld.long 0x0 3. " WKG_ENB_FOR_INTR3 ,Wakeup enable for interrupt line MPU_IRQ_3" "0,1" textline " " bitfld.long 0x0 4. " WKG_ENB_FOR_INTR4 ,Wakeup enable for interrupt line MPU_IRQ_4" "0,1" bitfld.long 0x0 5. " WKG_ENB_FOR_INTR5 ,Wakeup enable for interrupt line MPU_IRQ_5" "0,1" textline " " bitfld.long 0x0 6. " WKG_ENB_FOR_INTR6 ,Wakeup enable for interrupt line MPU_IRQ_6" "0,1" bitfld.long 0x0 7. " WKG_ENB_FOR_INTR7 ,Wakeup enable for interrupt line MPU_IRQ_7" "0,1" textline " " bitfld.long 0x0 8. " WKG_ENB_FOR_INTR8 ,Wakeup enable for interrupt line MPU_IRQ_8" "0,1" bitfld.long 0x0 9. " WKG_ENB_FOR_INTR9 ,Wakeup enable for interrupt line MPU_IRQ_9" "0,1" textline " " bitfld.long 0x0 10. " WKG_ENB_FOR_INTR10 ,Wakeup enable for interrupt line MPU_IRQ_10" "0,1" bitfld.long 0x0 11. " WKG_ENB_FOR_INTR11 ,Wakeup enable for interrupt line MPU_IRQ_11" "0,1" textline " " bitfld.long 0x0 12. " WKG_ENB_FOR_INTR12 ,Wakeup enable for interrupt line MPU_IRQ_12" "0,1" bitfld.long 0x0 13. " WKG_ENB_FOR_INTR13 ,Wakeup enable for interrupt line MPU_IRQ_13" "0,1" textline " " bitfld.long 0x0 14. " WKG_ENB_FOR_INTR14 ,Wakeup enable for interrupt line MPU_IRQ_14" "0,1" bitfld.long 0x0 15. " WKG_ENB_FOR_INTR15 ,Wakeup enable for interrupt line MPU_IRQ_15" "0,1" textline " " bitfld.long 0x0 16. " WKG_ENB_FOR_INTR16 ,Wakeup enable for interrupt line MPU_IRQ_16" "0,1" bitfld.long 0x0 17. " WKG_ENB_FOR_INTR17 ,Wakeup enable for interrupt line MPU_IRQ_17" "0,1" textline " " bitfld.long 0x0 18. " WKG_ENB_FOR_INTR18 ,Wakeup enable for interrupt line MPU_IRQ_18" "0,1" bitfld.long 0x0 19. " WKG_ENB_FOR_INTR19 ,Wakeup enable for interrupt line MPU_IRQ_19" "0,1" textline " " bitfld.long 0x0 20. " WKG_ENB_FOR_INTR20 ,Wakeup enable for interrupt line MPU_IRQ_20" "0,1" bitfld.long 0x0 21. " WKG_ENB_FOR_INTR21 ,Wakeup enable for interrupt line MPU_IRQ_21" "0,1" textline " " bitfld.long 0x0 22. " WKG_ENB_FOR_INTR22 ,Wakeup enable for interrupt line MPU_IRQ_22" "0,1" bitfld.long 0x0 23. " WKG_ENB_FOR_INTR23 ,Wakeup enable for interrupt line MPU_IRQ_23" "0,1" textline " " bitfld.long 0x0 24. " WKG_ENB_FOR_INTR24 ,Wakeup enable for interrupt line MPU_IRQ_24" "0,1" bitfld.long 0x0 25. " WKG_ENB_FOR_INTR25 ,Wakeup enable for interrupt line MPU_IRQ_25" "0,1" textline " " bitfld.long 0x0 26. " WKG_ENB_FOR_INTR26 ,Wakeup enable for interrupt line MPU_IRQ_26" "0,1" bitfld.long 0x0 27. " WKG_ENB_FOR_INTR27 ,Wakeup enable for interrupt line MPU_IRQ_27" "0,1" textline " " bitfld.long 0x0 28. " WKG_ENB_FOR_INTR28 ,Wakeup enable for interrupt line MPU_IRQ_28" "0,1" bitfld.long 0x0 29. " WKG_ENB_FOR_INTR29 ,Wakeup enable for interrupt line MPU_IRQ_29" "0,1" textline " " bitfld.long 0x0 30. " WKG_ENB_FOR_INTR30 ,Wakeup enable for interrupt line MPU_IRQ_30" "0,1" bitfld.long 0x0 31. " WKG_ENB_FOR_INTR31 ,Wakeup enable for interrupt line MPU_IRQ_31" "0,1" group.byte 0x414++0x3 line.long 0x0 "WKG_ENB_B_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_32 to MPU_IRQ_63). Write 0x0: Disable interrupt. Write 0x1: Enable interrupt." bitfld.long 0x0 0. " WKG_ENB_FOR_INTR32 ,Wakeup enable for interrupt line MPU_IRQ_32" "0,1" bitfld.long 0x0 1. " WKG_ENB_FOR_INTR33 ,Wakeup enable for interrupt line MPU_IRQ_33" "0,1" textline " " bitfld.long 0x0 2. " WKG_ENB_FOR_INTR34 ,Wakeup enable for interrupt line MPU_IRQ_34" "0,1" bitfld.long 0x0 3. " WKG_ENB_FOR_INTR35 ,Wakeup enable for interrupt line MPU_IRQ_35" "0,1" textline " " bitfld.long 0x0 4. " WKG_ENB_FOR_INTR36 ,Wakeup enable for interrupt line MPU_IRQ_36" "0,1" bitfld.long 0x0 5. " WKG_ENB_FOR_INTR37 ,Wakeup enable for interrupt line MPU_IRQ_37" "0,1" textline " " bitfld.long 0x0 6. " WKG_ENB_FOR_INTR38 ,Wakeup enable for interrupt line MPU_IRQ_38" "0,1" bitfld.long 0x0 7. " WKG_ENB_FOR_INTR39 ,Wakeup enable for interrupt line MPU_IRQ_39" "0,1" textline " " bitfld.long 0x0 8. " WKG_ENB_FOR_INTR40 ,Wakeup enable for interrupt line MPU_IRQ_40" "0,1" bitfld.long 0x0 9. " WKG_ENB_FOR_INTR41 ,Wakeup enable for interrupt line MPU_IRQ_41" "0,1" textline " " bitfld.long 0x0 10. " WKG_ENB_FOR_INTR42 ,Wakeup enable for interrupt line MPU_IRQ_42" "0,1" bitfld.long 0x0 11. " WKG_ENB_FOR_INTR43 ,Wakeup enable for interrupt line MPU_IRQ_43" "0,1" textline " " bitfld.long 0x0 12. " WKG_ENB_FOR_INTR44 ,Wakeup enable for interrupt line MPU_IRQ_44" "0,1" bitfld.long 0x0 13. " WKG_ENB_FOR_INTR45 ,Wakeup enable for interrupt line MPU_IRQ_45" "0,1" textline " " bitfld.long 0x0 14. " WKG_ENB_FOR_INTR46 ,Wakeup enable for interrupt line MPU_IRQ_46" "0,1" bitfld.long 0x0 15. " WKG_ENB_FOR_INTR47 ,Wakeup enable for interrupt line MPU_IRQ_47" "0,1" textline " " bitfld.long 0x0 16. " WKG_ENB_FOR_INTR48 ,Wakeup enable for interrupt line MPU_IRQ_48" "0,1" bitfld.long 0x0 17. " WKG_ENB_FOR_INTR49 ,Wakeup enable for interrupt line MPU_IRQ_49" "0,1" textline " " bitfld.long 0x0 18. " WKG_ENB_FOR_INTR50 ,Wakeup enable for interrupt line MPU_IRQ_50" "0,1" bitfld.long 0x0 19. " WKG_ENB_FOR_INTR51 ,Wakeup enable for interrupt line MPU_IRQ_51" "0,1" textline " " bitfld.long 0x0 20. " WKG_ENB_FOR_INTR52 ,Wakeup enable for interrupt line MPU_IRQ_52" "0,1" bitfld.long 0x0 21. " WKG_ENB_FOR_INTR53 ,Wakeup enable for interrupt line MPU_IRQ_53" "0,1" textline " " bitfld.long 0x0 22. " WKG_ENB_FOR_INTR54 ,Wakeup enable for interrupt line MPU_IRQ_54" "0,1" bitfld.long 0x0 23. " WKG_ENB_FOR_INTR55 ,Wakeup enable for interrupt line MPU_IRQ_55" "0,1" textline " " bitfld.long 0x0 24. " WKG_ENB_FOR_INTR56 ,Wakeup enable for interrupt line MPU_IRQ_56" "0,1" bitfld.long 0x0 25. " WKG_ENB_FOR_INTR57 ,Wakeup enable for interrupt line MPU_IRQ_57" "0,1" textline " " bitfld.long 0x0 26. " WKG_ENB_FOR_INTR58 ,Wakeup enable for interrupt line MPU_IRQ_58" "0,1" bitfld.long 0x0 27. " WKG_ENB_FOR_INTR59 ,Wakeup enable for interrupt line MPU_IRQ_59" "0,1" textline " " bitfld.long 0x0 28. " WKG_ENB_FOR_INTR60 ,Wakeup enable for interrupt line MPU_IRQ_60" "0,1" bitfld.long 0x0 29. " WKG_ENB_FOR_INTR61 ,Wakeup enable for interrupt line MPU_IRQ_61" "0,1" textline " " bitfld.long 0x0 30. " WKG_ENB_FOR_INTR62 ,Wakeup enable for interrupt line MPU_IRQ_62" "0,1" bitfld.long 0x0 31. " WKG_ENB_FOR_INTR63 ,Wakeup enable for interrupt line MPU_IRQ_63" "0,1" group.byte 0x418++0x3 line.long 0x0 "WKG_ENB_C_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_64 to MPU_IRQ_95). Write 0x0: Disable interrupt. Write 0x1: Enable interrupt." bitfld.long 0x0 0. " WKG_ENB_FOR_INTR64 ,Wakeup enable for interrupt line MPU_IRQ_64" "0,1" bitfld.long 0x0 1. " WKG_ENB_FOR_INTR65 ,Wakeup enable for interrupt line MPU_IRQ_65" "0,1" textline " " bitfld.long 0x0 2. " WKG_ENB_FOR_INTR66 ,Wakeup enable for interrupt line MPU_IRQ_66" "0,1" bitfld.long 0x0 3. " WKG_ENB_FOR_INTR67 ,Wakeup enable for interrupt line MPU_IRQ_67" "0,1" textline " " bitfld.long 0x0 4. " WKG_ENB_FOR_INTR68 ,Wakeup enable for interrupt line MPU_IRQ_68" "0,1" bitfld.long 0x0 5. " WKG_ENB_FOR_INTR69 ,Wakeup enable for interrupt line MPU_IRQ_69" "0,1" textline " " bitfld.long 0x0 6. " WKG_ENB_FOR_INTR70 ,Wakeup enable for interrupt line MPU_IRQ_70" "0,1" bitfld.long 0x0 7. " WKG_ENB_FOR_INTR71 ,Wakeup enable for interrupt line MPU_IRQ_71" "0,1" textline " " bitfld.long 0x0 8. " WKG_ENB_FOR_INTR72 ,Wakeup enable for interrupt line MPU_IRQ_72" "0,1" bitfld.long 0x0 9. " WKG_ENB_FOR_INTR73 ,Wakeup enable for interrupt line MPU_IRQ_73" "0,1" textline " " bitfld.long 0x0 10. " WKG_ENB_FOR_INTR74 ,Wakeup enable for interrupt line MPU_IRQ_74" "0,1" bitfld.long 0x0 11. " WKG_ENB_FOR_INTR75 ,Wakeup enable for interrupt line MPU_IRQ_75" "0,1" textline " " bitfld.long 0x0 12. " WKG_ENB_FOR_INTR76 ,Wakeup enable for interrupt line MPU_IRQ_76" "0,1" bitfld.long 0x0 13. " WKG_ENB_FOR_INTR77 ,Wakeup enable for interrupt line MPU_IRQ_77" "0,1" textline " " bitfld.long 0x0 14. " WKG_ENB_FOR_INTR78 ,Wakeup enable for interrupt line MPU_IRQ_78" "0,1" bitfld.long 0x0 15. " WKG_ENB_FOR_INTR79 ,Wakeup enable for interrupt line MPU_IRQ_79" "0,1" textline " " bitfld.long 0x0 16. " WKG_ENB_FOR_INTR80 ,Wakeup enable for interrupt line MPU_IRQ_80" "0,1" bitfld.long 0x0 17. " WKG_ENB_FOR_INTR81 ,Wakeup enable for interrupt line MPU_IRQ_81" "0,1" textline " " bitfld.long 0x0 18. " WKG_ENB_FOR_INTR82 ,Wakeup enable for interrupt line MPU_IRQ_82" "0,1" bitfld.long 0x0 19. " WKG_ENB_FOR_INTR83 ,Wakeup enable for interrupt line MPU_IRQ_83" "0,1" textline " " bitfld.long 0x0 20. " WKG_ENB_FOR_INTR84 ,Wakeup enable for interrupt line MPU_IRQ_84" "0,1" bitfld.long 0x0 21. " WKG_ENB_FOR_INTR85 ,Wakeup enable for interrupt line MPU_IRQ_85" "0,1" textline " " bitfld.long 0x0 22. " WKG_ENB_FOR_INTR86 ,Wakeup enable for interrupt line MPU_IRQ_86" "0,1" bitfld.long 0x0 23. " WKG_ENB_FOR_INTR87 ,Wakeup enable for interrupt line MPU_IRQ_87" "0,1" textline " " bitfld.long 0x0 24. " WKG_ENB_FOR_INTR88 ,Wakeup enable for interrupt line MPU_IRQ_88" "0,1" bitfld.long 0x0 25. " WKG_ENB_FOR_INTR89 ,Wakeup enable for interrupt line MPU_IRQ_89" "0,1" textline " " bitfld.long 0x0 26. " WKG_ENB_FOR_INTR90 ,Wakeup enable for interrupt line MPU_IRQ_90" "0,1" bitfld.long 0x0 27. " WKG_ENB_FOR_INTR91 ,Wakeup enable for interrupt line MPU_IRQ_91" "0,1" textline " " bitfld.long 0x0 28. " WKG_ENB_FOR_INTR92 ,Wakeup enable for interrupt line MPU_IRQ_92" "0,1" bitfld.long 0x0 29. " WKG_ENB_FOR_INTR93 ,Wakeup enable for interrupt line MPU_IRQ_93" "0,1" textline " " bitfld.long 0x0 30. " WKG_ENB_FOR_INTR94 ,Wakeup enable for interrupt line MPU_IRQ_94" "0,1" bitfld.long 0x0 31. " WKG_ENB_FOR_INTR95 ,Wakeup enable for interrupt line MPU_IRQ_95" "0,1" group.byte 0x41C++0x3 line.long 0x0 "WKG_ENB_D_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_96 to MPU_IRQ_127). Write 0x0: Disable interrupt. Write 0x1: Enable interrupt." bitfld.long 0x0 0. " WKG_ENB_FOR_INTR96 ,Wakeup enable for interrupt line MPU_IRQ_96" "0,1" bitfld.long 0x0 1. " WKG_ENB_FOR_INTR97 ,Wakeup enable for interrupt line MPU_IRQ_97" "0,1" textline " " bitfld.long 0x0 2. " WKG_ENB_FOR_INTR98 ,Wakeup enable for interrupt line MPU_IRQ_98" "0,1" bitfld.long 0x0 3. " WKG_ENB_FOR_INTR99 ,Wakeup enable for interrupt line MPU_IRQ_99" "0,1" textline " " bitfld.long 0x0 4. " WKG_ENB_FOR_INTR100 ,Wakeup enable for interrupt line MPU_IRQ_100" "0,1" bitfld.long 0x0 5. " WKG_ENB_FOR_INTR101 ,Wakeup enable for interrupt line MPU_IRQ_101" "0,1" textline " " bitfld.long 0x0 6. " WKG_ENB_FOR_INTR102 ,Wakeup enable for interrupt line MPU_IRQ_102" "0,1" bitfld.long 0x0 7. " WKG_ENB_FOR_INTR103 ,Wakeup enable for interrupt line MPU_IRQ_103" "0,1" textline " " bitfld.long 0x0 8. " WKG_ENB_FOR_INTR104 ,Wakeup enable for interrupt line MPU_IRQ_104" "0,1" bitfld.long 0x0 9. " WKG_ENB_FOR_INTR105 ,Wakeup enable for interrupt line MPU_IRQ_105" "0,1" textline " " bitfld.long 0x0 10. " WKG_ENB_FOR_INTR106 ,Wakeup enable for interrupt line MPU_IRQ_106" "0,1" bitfld.long 0x0 11. " WKG_ENB_FOR_INTR107 ,Wakeup enable for interrupt line MPU_IRQ_107" "0,1" textline " " bitfld.long 0x0 12. " WKG_ENB_FOR_INTR108 ,Wakeup enable for interrupt line MPU_IRQ_108" "0,1" bitfld.long 0x0 13. " WKG_ENB_FOR_INTR109 ,Wakeup enable for interrupt line MPU_IRQ_109" "0,1" textline " " bitfld.long 0x0 14. " WKG_ENB_FOR_INTR110 ,Wakeup enable for interrupt line MPU_IRQ_110" "0,1" bitfld.long 0x0 15. " WKG_ENB_FOR_INTR111 ,Wakeup enable for interrupt line MPU_IRQ_111" "0,1" textline " " bitfld.long 0x0 16. " WKG_ENB_FOR_INTR112 ,Wakeup enable for interrupt line MPU_IRQ_112" "0,1" bitfld.long 0x0 17. " WKG_ENB_FOR_INTR113 ,Wakeup enable for interrupt line MPU_IRQ_113" "0,1" textline " " bitfld.long 0x0 18. " WKG_ENB_FOR_INTR114 ,Wakeup enable for interrupt line MPU_IRQ_114" "0,1" bitfld.long 0x0 19. " WKG_ENB_FOR_INTR115 ,Wakeup enable for interrupt line MPU_IRQ_115" "0,1" textline " " bitfld.long 0x0 20. " WKG_ENB_FOR_INTR116 ,Wakeup enable for interrupt line MPU_IRQ_116" "0,1" bitfld.long 0x0 21. " WKG_ENB_FOR_INTR117 ,Wakeup enable for interrupt line MPU_IRQ_117" "0,1" textline " " bitfld.long 0x0 22. " WKG_ENB_FOR_INTR118 ,Wakeup enable for interrupt line MPU_IRQ_118" "0,1" bitfld.long 0x0 23. " WKG_ENB_FOR_INTR119 ,Wakeup enable for interrupt line MPU_IRQ_119" "0,1" textline " " bitfld.long 0x0 24. " WKG_ENB_FOR_INTR120 ,Wakeup enable for interrupt line MPU_IRQ_120" "0,1" bitfld.long 0x0 25. " WKG_ENB_FOR_INTR121 ,Wakeup enable for interrupt line MPU_IRQ_121" "0,1" textline " " bitfld.long 0x0 26. " WKG_ENB_FOR_INTR122 ,Wakeup enable for interrupt line MPU_IRQ_122" "0,1" bitfld.long 0x0 27. " WKG_ENB_FOR_INTR123 ,Wakeup enable for interrupt line MPU_IRQ_123" "0,1" textline " " bitfld.long 0x0 28. " WKG_ENB_FOR_INTR124 ,Wakeup enable for interrupt line MPU_IRQ_124" "0,1" bitfld.long 0x0 29. " WKG_ENB_FOR_INTR125 ,Wakeup enable for interrupt line MPU_IRQ_125" "0,1" textline " " bitfld.long 0x0 30. " WKG_ENB_FOR_INTR126 ,Wakeup enable for interrupt line MPU_IRQ_126" "0,1" bitfld.long 0x0 31. " WKG_ENB_FOR_INTR127 ,Wakeup enable for interrupt line MPU_IRQ_127" "0,1" group.byte 0x420++0x3 line.long 0x0 "WKG_ENB_E_1,Wake-up interrupt enable register for MPU_C1 (interrupts MPU_IRQ_128 to MPU_IRQ_159). Write 0x0: Disable interrupt. Write 0x1: Enable interrupt." bitfld.long 0x0 0. " WKG_ENB_FOR_INTR128 ,Wakeup enable for interrupt line MPU_IRQ_128" "0,1" bitfld.long 0x0 1. " WKG_ENB_FOR_INTR129 ,Wakeup enable for interrupt line MPU_IRQ_129" "0,1" textline " " bitfld.long 0x0 2. " WKG_ENB_FOR_INTR130 ,Wakeup enable for interrupt line MPU_IRQ_130" "0,1" bitfld.long 0x0 3. " WKG_ENB_FOR_INTR131 ,Wakeup enable for interrupt line MPU_IRQ_131" "0,1" textline " " bitfld.long 0x0 4. " WKG_ENB_FOR_INTR132 ,Wakeup enable for interrupt line MPU_IRQ_132" "0,1" bitfld.long 0x0 5. " WKG_ENB_FOR_INTR133 ,Wakeup enable for interrupt line MPU_IRQ_133" "0,1" textline " " bitfld.long 0x0 6. " WKG_ENB_FOR_INTR134 ,Wakeup enable for interrupt line MPU_IRQ_134" "0,1" bitfld.long 0x0 7. " WKG_ENB_FOR_INTR135 ,Wakeup enable for interrupt line MPU_IRQ_135" "0,1" textline " " bitfld.long 0x0 8. " WKG_ENB_FOR_INTR136 ,Wakeup enable for interrupt line MPU_IRQ_136" "0,1" bitfld.long 0x0 9. " WKG_ENB_FOR_INTR137 ,Wakeup enable for interrupt line MPU_IRQ_137" "0,1" textline " " bitfld.long 0x0 10. " WKG_ENB_FOR_INTR138 ,Wakeup enable for interrupt line MPU_IRQ_138" "0,1" bitfld.long 0x0 11. " WKG_ENB_FOR_INTR139 ,Wakeup enable for interrupt line MPU_IRQ_139" "0,1" textline " " bitfld.long 0x0 12. " WKG_ENB_FOR_INTR140 ,Wakeup enable for interrupt line MPU_IRQ_140" "0,1" bitfld.long 0x0 13. " WKG_ENB_FOR_INTR141 ,Wakeup enable for interrupt line MPU_IRQ_141" "0,1" textline " " bitfld.long 0x0 14. " WKG_ENB_FOR_INTR142 ,Wakeup enable for interrupt line MPU_IRQ_142" "0,1" bitfld.long 0x0 15. " WKG_ENB_FOR_INTR143 ,Wakeup enable for interrupt line MPU_IRQ_143" "0,1" textline " " bitfld.long 0x0 16. " WKG_ENB_FOR_INTR144 ,Wakeup enable for interrupt line MPU_IRQ_144" "0,1" bitfld.long 0x0 17. " WKG_ENB_FOR_INTR145 ,Wakeup enable for interrupt line MPU_IRQ_145" "0,1" textline " " bitfld.long 0x0 18. " WKG_ENB_FOR_INTR146 ,Wakeup enable for interrupt line MPU_IRQ_146" "0,1" bitfld.long 0x0 19. " WKG_ENB_FOR_INTR147 ,Wakeup enable for interrupt line MPU_IRQ_147" "0,1" textline " " bitfld.long 0x0 20. " WKG_ENB_FOR_INTR148 ,Wakeup enable for interrupt line MPU_IRQ_148" "0,1" bitfld.long 0x0 21. " WKG_ENB_FOR_INTR149 ,Wakeup enable for interrupt line MPU_IRQ_149" "0,1" textline " " bitfld.long 0x0 22. " WKG_ENB_FOR_INTR150 ,Wakeup enable for interrupt line MPU_IRQ_150" "0,1" bitfld.long 0x0 23. " WKG_ENB_FOR_INTR151 ,Wakeup enable for interrupt line MPU_IRQ_151" "0,1" textline " " bitfld.long 0x0 24. " WKG_ENB_FOR_INTR152 ,Wakeup enable for interrupt line MPU_IRQ_152" "0,1" bitfld.long 0x0 25. " WKG_ENB_FOR_INTR153 ,Wakeup enable for interrupt line MPU_IRQ_153" "0,1" textline " " bitfld.long 0x0 26. " WKG_ENB_FOR_INTR154 ,Wakeup enable for interrupt line MPU_IRQ_154" "0,1" bitfld.long 0x0 27. " WKG_ENB_FOR_INTR155 ,Wakeup enable for interrupt line MPU_IRQ_155" "0,1" textline " " bitfld.long 0x0 28. " WKG_ENB_FOR_INTR156 ,Wakeup enable for interrupt line MPU_IRQ_156" "0,1" bitfld.long 0x0 29. " WKG_ENB_FOR_INTR157 ,Wakeup enable for interrupt line MPU_IRQ_157" "0,1" textline " " bitfld.long 0x0 30. " WKG_ENB_FOR_INTR158 ,Wakeup enable for interrupt line MPU_IRQ_158" "0,1" bitfld.long 0x0 31. " WKG_ENB_FOR_INTR159 ,Wakeup enable for interrupt line MPU_IRQ_159" "0,1" group.byte 0x800++0x3 line.long 0x0 "AUX_CORE_BOOT_0,This register is used by the ROM code and OS during SMP boot. It is used to indicate the boot status to MPU_C1." bitfld.long 0x0 0.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MPU_C1_STATUS ,MPU_C1 boot status. If ` 0x0, branch at the address specified inAUX_CORE_BOOT_1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x804++0x3 line.long 0x0 "AUX_CORE_BOOT_1,This register is used by the ROM code and OS during SMP boot. It is intended to store the execution start address of MPU_C1. When needed, the SMP OS (executing on MPU_C0) stores the execution start address of MPU_C1 in, and then wakes up MPU_C1 by executing a SEV command. When MPU_C1 receives an event (caused by the SEV command), it executes the event handler in the ROM Code, which eventually branches to the address stored in ." hexmask.long 0x0 0.--31. 1. " AUX_CORE_BOOT_1 ,SMP boot register" group.byte 0x808++0x3 line.long 0x0 "STM_HWEVENTS_INV,Gives programmable control of inverting or not inverting MPUHWDBGOUT[31:0] going to HWEVENTS[31:0] input of CS_STM" bitfld.long 0x0 0. " STM_HWEVENT_INV_0 ,Polarity inversion control for MPUHWDBGOUT0 signal." "0,1" bitfld.long 0x0 1. " STM_HWEVENT_INV_1 ,Polarity inversion control for MPUHWDBGOUT1 signal." "0,1" textline " " bitfld.long 0x0 2. " STM_HWEVENT_INV_2 ,Polarity inversion control for MPUHWDBGOUT2 signal." "0,1" bitfld.long 0x0 3. " STM_HWEVENT_INV_3 ,Polarity inversion control for MPUHWDBGOUT3 signal." "0,1" textline " " bitfld.long 0x0 4. " STM_HWEVENT_INV_4 ,Polarity inversion control for MPUHWDBGOUT4 signal." "0,1" bitfld.long 0x0 5. " STM_HWEVENT_INV_5 ,Polarity inversion control for MPUHWDBGOUT5 signal." "0,1" textline " " bitfld.long 0x0 6. " STM_HWEVENT_INV_6 ,Polarity inversion control for MPUHWDBGOUT6 signal." "0,1" bitfld.long 0x0 7. " STM_HWEVENT_INV_7 ,Polarity inversion control for MPUHWDBGOUT7 signal." "0,1" textline " " bitfld.long 0x0 8. " STM_HWEVENT_INV_8 ,Polarity inversion control for MPUHWDBGOUT8 signal." "0,1" bitfld.long 0x0 9. " STM_HWEVENT_INV_9 ,Polarity inversion control for MPUHWDBGOUT9 signal." "0,1" textline " " bitfld.long 0x0 10. " STM_HWEVENT_INV_10 ,Polarity inversion control for MPUHWDBGOUT10 signal." "0,1" bitfld.long 0x0 11. " STM_HWEVENT_INV_11 ,Polarity inversion control for MPUHWDBGOUT11 signal." "0,1" textline " " bitfld.long 0x0 12. " STM_HWEVENT_INV_12 ,Polarity inversion control for MPUHWDBGOUT12 signal." "0,1" bitfld.long 0x0 13. " STM_HWEVENT_INV_13 ,Polarity inversion control for MPUHWDBGOUT13 signal." "0,1" textline " " bitfld.long 0x0 14. " STM_HWEVENT_INV_14 ,Polarity inversion control for MPUHWDBGOUT14 signal." "0,1" bitfld.long 0x0 15. " STM_HWEVENT_INV_15 ,Polarity inversion control for MPUHWDBGOUT15 signal." "0,1" textline " " bitfld.long 0x0 16. " STM_HWEVENT_INV_16 ,Polarity inversion control for MPUHWDBGOUT16 signal." "0,1" bitfld.long 0x0 17. " STM_HWEVENT_INV_17 ,Polarity inversion control for MPUHWDBGOUT17 signal." "0,1" textline " " bitfld.long 0x0 18. " STM_HWEVENT_INV_18 ,Polarity inversion control for MPUHWDBGOUT18 signal." "0,1" bitfld.long 0x0 19. " STM_HWEVENT_INV_19 ,Polarity inversion control for MPUHWDBGOUT19 signal." "0,1" textline " " bitfld.long 0x0 20. " STM_HWEVENT_INV_20 ,Polarity inversion control for MPUHWDBGOUT20 signal." "0,1" bitfld.long 0x0 21. " STM_HWEVENT_INV_21 ,Polarity inversion control for MPUHWDBGOUT21 signal." "0,1" textline " " bitfld.long 0x0 22. " STM_HWEVENT_INV_22 ,Polarity inversion control for MPUHWDBGOUT22 signal." "0,1" bitfld.long 0x0 23. " STM_HWEVENT_INV_23 ,Polarity inversion control for MPUHWDBGOUT23 signal." "0,1" textline " " bitfld.long 0x0 24. " STM_HWEVENT_INV_24 ,Polarity inversion control for MPUHWDBGOUT24 signal." "0,1" bitfld.long 0x0 25. " STM_HWEVENT_INV_25 ,Polarity inversion control for MPUHWDBGOUT25 signal." "0,1" textline " " bitfld.long 0x0 26. " STM_HWEVENT_INV_26 ,Polarity inversion control for MPUHWDBGOUT26 signal." "0,1" bitfld.long 0x0 27. " STM_HWEVENT_INV_27 ,Polarity inversion control for MPUHWDBGOUT27 signal." "0,1" textline " " bitfld.long 0x0 28. " STM_HWEVENT_INV_28 ,Polarity inversion control for MPUHWDBGOUT28 signal." "0,1" bitfld.long 0x0 29. " STM_HWEVENT_INV_29 ,Polarity inversion control for MPUHWDBGOUT29 signal." "0,1" textline " " bitfld.long 0x0 30. " STM_HWEVENT_INV_30 ,Polarity inversion control for MPUHWDBGOUT30 signal." "0,1" bitfld.long 0x0 31. " STM_HWEVENT_INV_31 ,Polarity inversion control for MPUHWDBGOUT31 signal." "0,1" group.byte 0x80C++0x3 line.long 0x0 "AMBA_IF_MODE,This register controls the MPU core interface tie-off values for BI, BO, BCM and SBD. This register is located in MPU always-on domain and is reset by MPUAON_RST." bitfld.long 0x0 0. " SBD ,SYSBARDISABLE input of MPU core." "0,1" bitfld.long 0x0 1. " BCM ,BROADCASTMAINTENANCE input of MPU core." "0,1" textline " " bitfld.long 0x0 2. " BO ,BROADCASTOUTER input of MPU core." "0,1" bitfld.long 0x0 3. " BI ,BROADCASTINNER input of MPU core." "0,1" textline " " bitfld.long 0x0 4. " APB_FENCE_EN ,Enables APB fencing logic." "0,1" bitfld.long 0x0 5. " ES2_PM_MODE ,Enables OFF mode behavior. 0x0 : OFF Mode 1, CPUs would enter and exit OFF mode together. 0x1 : OFF Mode 2, CPUs are allowed to enter/exit OFF mode independently. NOTE: This bit is NOT supported in this device." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved. Ignored on write and zero on read." group.byte 0xC08++0x3 line.long 0x0 "TIMESTAMPCYCLELO,Lower 32 bits of the 48-bit timestamp counter value" hexmask.long 0x0 0.--31. 1. " COUNTER_31_0 ,Lower 32 bits of the 48-bit timestamp counter value." group.byte 0xC0C++0x3 line.long 0x0 "TIMESTAMPCYCLEHI,Higher 16 bits of the 48-bit timestamp counter value" hexmask.long.word 0x0 0.--15. 1. " COUNTER_47_32 ,Higher 16 bits of the timestamp counter value." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved. Ignored on write and zero on read." width 0x0B tree.end tree "MPU_WD_TIMER" base ad:0x482A0000 width 31. group.byte 0x0++0x3 line.long 0x0 "WDT_LOAD_REGISTER_i_0,When a new value is stored in this register, the is immediately loaded with this value and the prescaler state is cleared. This register is reset by warm reset of the corresponding CPU." hexmask.long 0x0 0.--31. 1. " NEWCOUNT ,New value to load intoWDT_COUNT_REGISTER_i." group.byte 0x20++0x3 line.long 0x0 "WDT_LOAD_REGISTER_i_1,When a new value is stored in this register, the is immediately loaded with this value and the prescaler state is cleared. This register is reset by warm reset of the corresponding CPU." hexmask.long 0x0 0.--31. 1. " NEWCOUNT ,New value to load intoWDT_COUNT_REGISTER_i." group.byte 0x4++0x3 line.long 0x0 "WDT_COUNT_REGISTER_i_0,This register is a 32-bit decrementing counter. The decrement rate is programmed in the. The can be read to get the current count. It decrements if the MPU_WD_TIMER_Cx is enabled ([0] ENABLE = 0x1). If the processor related to the corresponding watchdog channel is in debug state, the counter does not decrement until the processor returns to non-debug state. The decrements down to zero and stops. The only way to update the is to write to the . If a software failure prevents the from being refreshed, the reaches zero, the watchdog timeout status flag is set and all interrupt requests or reset requests enabled in the are signalled. If a reset request is enabled, the global PRCM is then responsible for resetting the MPUSS. Debug state is inferred by monitoring the DBGACK signal corresponding to this core. This register is reset by warm reset of the corresponding MPU core." hexmask.long 0x0 0.--31. 1. " CURRENTCOUNT ,Current count of the MPU_WD_TIMER." group.byte 0x24++0x3 line.long 0x0 "WDT_COUNT_REGISTER_i_1,This register is a 32-bit decrementing counter. The decrement rate is programmed in the. The can be read to get the current count. It decrements if the MPU_WD_TIMER_Cx is enabled ([0] ENABLE = 0x1). If the processor related to the corresponding watchdog channel is in debug state, the counter does not decrement until the processor returns to non-debug state. The decrements down to zero and stops. The only way to update the is to write to the . If a software failure prevents the from being refreshed, the reaches zero, the watchdog timeout status flag is set and all interrupt requests or reset requests enabled in the are signalled. If a reset request is enabled, the global PRCM is then responsible for resetting the MPUSS. Debug state is inferred by monitoring the DBGACK signal corresponding to this core. This register is reset by warm reset of the corresponding MPU core." hexmask.long 0x0 0.--31. 1. " CURRENTCOUNT ,Current count of the MPU_WD_TIMER." group.byte 0x8++0x3 line.long 0x0 "WDT_WARNING_REGISTER_i_0,The is compared to the . If is less than or equal to the and [8] WARNEN = 0b1, a warning interrupt is signalled to the MPU_INTC. The warning condition can be used to signal an interrupt that gives software a notice that the MPU_WD_TIMER_Cx is getting close to a timeout, when a more serious action should be taken." hexmask.long 0x0 0.--31. 1. " WARNING_WATERMARK ,A warning condition occurs when theWDT_COUNT_REGISTER_i value is less than or equal to the WDT_WARNING_REGISTER_i." group.byte 0x28++0x3 line.long 0x0 "WDT_WARNING_REGISTER_i_1,The is compared to the . If is less than or equal to the and [8] WARNEN = 0b1, a warning interrupt is signalled to the MPU_INTC. The warning condition can be used to signal an interrupt that gives software a notice that the MPU_WD_TIMER_Cx is getting close to a timeout, when a more serious action should be taken." hexmask.long 0x0 0.--31. 1. " WARNING_WATERMARK ,A warning condition occurs when theWDT_COUNT_REGISTER_i value is less than or equal to the WDT_WARNING_REGISTER_i." group.byte 0xC++0x3 line.long 0x0 "WDT_PRESCALER_REGISTER_i_0,This register is used to set the count rate of the MPU_WD_TIMER_Cx counter." hexmask.long.word 0x0 0.--9. 1. " PRESCALER ,Sets the prescaler ratio.WDT_COUNT_REGISTER_i decrements every (PRESCALER + 1) MPU_DPLL_CLK clocks. Note: If the prescaler is set to (MPU_DPLL_CLK [in MHz] - 1), the MPU_WD_TIMER_Cx counter counts at a 1 microsecond rate." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved. Ignored on writes. Reads return 0s." group.byte 0x2C++0x3 line.long 0x0 "WDT_PRESCALER_REGISTER_i_1,This register is used to set the count rate of the MPU_WD_TIMER_Cx counter." hexmask.long.word 0x0 0.--9. 1. " PRESCALER ,Sets the prescaler ratio.WDT_COUNT_REGISTER_i decrements every (PRESCALER + 1) MPU_DPLL_CLK clocks. Note: If the prescaler is set to (MPU_DPLL_CLK [in MHz] - 1), the MPU_WD_TIMER_Cx counter counts at a 1 microsecond rate." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved. Ignored on writes. Reads return 0s." group.byte 0x10++0x3 line.long 0x0 "WDT_CONTROL_REGISTER_i_0,This register controls the behavior of the MPU_WD_TIMER_Cx. This register is reset by warm reset of the corresponding MPU core." bitfld.long 0x0 0. " ENABLE ,Enable for MPU_WD_TIMER_Cx. 0: MPU_WD_TIMER_Cx is disabled. It will not count down and it will not generate a reset request. All MPU_WD_TIMER_Cx registers may be accessed. 1: MPU_WD_TIMER_Cx is enabled. It will count down and generate a reset request if it reaches 0. This bit is reset by warm or power-on reset." "0,1" bitfld.long 0x0 1. " INTREN ,Interrupt Enable. If this field is 0b1 when the timer reaches zero, an interrupt request is sent to the MPU_INTC." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved. Ignored on writes. Reads return 0s." "0,1" bitfld.long 0x0 3. " MPUSSRSTEN ,MPUSS Reset Enable. If this field is 0b1 when the timer reaches zero, a request is sent to the global PRCM to begin a global warm reset." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved. Ignored on writes. Reads return 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " WARNEN ,Warning Interrupt Enable. If this bit is set and the warning watermark test is true, a warning interrupt is generated to the MPU_INTC." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved. Ignored on writes. Reads return 0s." group.byte 0x30++0x3 line.long 0x0 "WDT_CONTROL_REGISTER_i_1,This register controls the behavior of the MPU_WD_TIMER_Cx. This register is reset by warm reset of the corresponding MPU core." bitfld.long 0x0 0. " ENABLE ,Enable for MPU_WD_TIMER_Cx. 0: MPU_WD_TIMER_Cx is disabled. It will not count down and it will not generate a reset request. All MPU_WD_TIMER_Cx registers may be accessed. 1: MPU_WD_TIMER_Cx is enabled. It will count down and generate a reset request if it reaches 0. This bit is reset by warm or power-on reset." "0,1" bitfld.long 0x0 1. " INTREN ,Interrupt Enable. If this field is 0b1 when the timer reaches zero, an interrupt request is sent to the MPU_INTC." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved. Ignored on writes. Reads return 0s." "0,1" bitfld.long 0x0 3. " MPUSSRSTEN ,MPUSS Reset Enable. If this field is 0b1 when the timer reaches zero, a request is sent to the global PRCM to begin a global warm reset." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved. Ignored on writes. Reads return 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " WARNEN ,Warning Interrupt Enable. If this bit is set and the warning watermark test is true, a warning interrupt is generated to the MPU_INTC." "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved. Ignored on writes. Reads return 0s." group.byte 0x14++0x3 line.long 0x0 "WDT_RESET_STATUS_REGISTER_i_0,The TO bit indicated that this MPU_WD_TIMER_Cx has timed out. This might be used to figure out which MPU_WD_TIMER_Cx signalled a reset. This register is not reset by warm reset, but only by cold reset." bitfld.long 0x0 0. " TO ,Timeout. Indicates theWDT_COUNT_REGISTER_i has reached zero (timed out) and the signalling enabled in the WDT_CONTROL_REGISTER_i has occurred. Can be used to determine which MPU_WD_TIMER_Cx instance caused a reset. Write a '1' to this bit to reset it." "0,1" bitfld.long 0x0 1. " WARN ,Warning. Indicates that the count has passed the warning watermark level while theWDT_CONTROL_REGISTER_i[8] WARNEN bit was set. Write a '1' to this bit to reset it." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved. Ignored on writes. Reads return 0s." group.byte 0x34++0x3 line.long 0x0 "WDT_RESET_STATUS_REGISTER_i_1,The TO bit indicated that this MPU_WD_TIMER_Cx has timed out. This might be used to figure out which MPU_WD_TIMER_Cx signalled a reset. This register is not reset by warm reset, but only by cold reset." bitfld.long 0x0 0. " TO ,Timeout. Indicates theWDT_COUNT_REGISTER_i has reached zero (timed out) and the signalling enabled in the WDT_CONTROL_REGISTER_i has occurred. Can be used to determine which MPU_WD_TIMER_Cx instance caused a reset. Write a '1' to this bit to reset it." "0,1" bitfld.long 0x0 1. " WARN ,Warning. Indicates that the count has passed the warning watermark level while theWDT_CONTROL_REGISTER_i[8] WARNEN bit was set. Write a '1' to this bit to reset it." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved. Ignored on writes. Reads return 0s." width 0x0B tree.end tree "MPU_PRCM_DEVICE" base ad:0x48243200 width 41. group.byte 0x0++0x3 line.long 0x0 "PRM_RSTST,This register logs the global reset sources, thus contains information regarding the cold/warm reset events generated by global PRCM. Each bit is set upon release of the domain reset signal. Must be cleared by software. This register is insensitive to global warm reset." bitfld.long 0x0 0. " GLOBAL_COLD_RST ,Power-on (cold) reset event generated by global PRCM" "0,1" bitfld.long 0x0 1. " GLOBAL_WARM_RST ,Global warm reset event generated by global PRCM" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "PRM_PSCON_COUNT,Programmable precharge count for L1cache" hexmask.long.byte 0x0 0.--7. 1. " PCHARGE_TIME ,Programmable precharge count during retention" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 16.--23. 1. " HG_PONOUT_2_PGDOODIN_TIME ,The value set in this field determines the slow ramp-up time and the duration (number of cycles) of the PONOUTHG to PGOODINHG (transition for power domain without DPS). The duration is computed as 8 x HG_PONOUT_2_PGDOODIN_TIME of system clock cycles. Target is 10us." bitfld.long 0x0 24. " HG_EN ,HG power chain switch enable" "0,1" textline " " bitfld.long 0x0 25. " HG_RAMPUP ,Ramp-up mode selection of HG power chain switch" "0,1" bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x3 line.long 0x0 "PRM_FRAC_INCREMENTER_NUMERATOR,Fractional incrementor" hexmask.long.word 0x0 0.--11. 1. " SYS_MODE_NUMERATOR ,Numerator to be used in fractional incrementor when SYS_CLK1 is used as PRCM clock.NOTE: The reset value corresponds to SYS_CLK1 = 38.4 MHz. Because the device does not support such SYS_CLK1 frequency, it is SW responsibility to set a value corresponding to one of the SYS_CLK1 frequencies listed in . ." bitfld.long 0x0 12.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ABE_LP_MODE_NUMERATOR ,Numerator to be used in fractional incrementor when ABE_LP_CLK clock is used as PRCM clock. Reset value corresponds to ABE_LP_CLK clock = 12.288 MHz." bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD,Reload command and denominator to be used in fractional incrementor" hexmask.long.word 0x0 0.--11. 1. " DENOMINATOR ,Denominator to be used in fractional incrementor when when SYS_CLK1 is used as PRCM clock.NOTE: The reset value corresponds to SYS_CLK1 = 38.4 MHz. Because the device does not support such SYS_CLK1 frequency, it is SW responsibility to set a value corresponding to one of the SYS_CLK1 frequencies listed in . ." bitfld.long 0x0 12.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " RELOAD ,Reload counter value from coarse counter. 0->1 transition in this field is used to load the coarse counter into counter." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP_SYSTEM" base ad:0x1D00000 width 33. group.byte 0x0++0x3 line.long 0x0 "DSP_SYS_REVISION,DSP_SYS_REVISION" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "DSP_SYS_HWINFO,DSP_SYS_HWINFO" bitfld.long 0x0 0.--3. " NUM ,Instance Number Set by subsystem input. In a multi-DSP system, provides a unique/incrementing values for each DSP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " INFO ,0x0: No configurable options in subsystem." group.byte 0x8++0x3 line.long 0x0 "DSP_SYS_SYSCONFIG,DSP_SYS_SYSCONFIG" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,0x0: FORCE_IDLE This mode is a backup mode intended to be used only if the smart-idle mode is bugged. When in this mode, the IAF acknowledges a request to go idle from the power manager with minimal hardware condition. It is the responsibility of the software to ensure that the IAF are in a correct quiet state before requesting a force-idle transition. Additionally when in this mode, the IAF is not allowed to generate any wakeup request." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,0x0: FORCE_STANDBY This mode is a backup mode intended to be used only if the smart-idle mode is bugged. When in this mode, the SAF asserts with minimal hardware condition the 'STANDBY' status. It is the responsibility of the software to ensure that the SAF is in a correct quiet state before programming this mode. Additionally when in this mode, the SAF is not allowed to generate wakeup request." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reserved. Read returns 0." "0,1,2,3" textline " " bitfld.long 0x0 8. " RESERVED ,Reserved. User must write 0." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved. Read returns 0." group.byte 0xC++0x3 line.long 0x0 "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode." bitfld.long 0x0 0. " C66X_STAT ,C66x Status" "0,1" bitfld.long 0x0 1. " TC0_STAT ,EDMA TC0 Status" "0,1" textline " " bitfld.long 0x0 2. " TC1_STAT ,EDMA TC1 Status" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--5. " OCPI_DISC_STAT ,L3_MAIN (OCP) Initiator(s) Disconnect Status" "0,1,2,3" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses." bitfld.long 0x0 0. " OCPI_DISC ,OCP Initiator (on L3_MAIN) Disconnect request" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators." bitfld.long 0x0 0.--1. " TC0_DBS ,TC0 Default Burst size" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " TC1_DBS ,TC1 Default Burst size." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " TC0_L2PRES ,TC0 L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect." "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " TC1_L2PRES ,TC1 L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " CFG_L2PRES ,DSP CFG L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect" "0,1,2,3" bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " SDMA_L2PRES ,OCP Target port L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect." "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24. " NOPOSTOVERRIDE ,OCP Posted Write vs Non-Posted Write override" "0,1" bitfld.long 0x0 25.--27. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 28.--30. " SDMA_PRI ,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port. Can typically be left at default value. 0x0 is highest, ..., 0x7 is lowest priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x18++0x3 line.long 0x0 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs." bitfld.long 0x0 0. " MMU0_EN ,MMU0 Enable" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " MMU1_EN ,MMU1 Enable" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " MMU0_ABORT ,MMU0 Abort" "0,1" bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12. " MMU1_ABORT ,MMU1 Abort" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol). IRQWAKEEN0 is for interrupt inputs 63 thru 32, and IRQWAKEEN1 is for interrupt inputs 95 thru 64. Internal interrupts cannot cause a wake condition since in this state there is no guaranteed clock and all sub-modules should be in idle state. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding interrupt for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable bit vector for interrupt #n+32" group.byte 0x24++0x3 line.long 0x0 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol). IRQWAKEEN0 is for interrupt inputs 63 thru 32, and IRQWAKEEN1 is for interrupt inputs 95 thru 64. Internal interrupts cannot cause a wake condition since in this state there is no guaranteed clock and all sub-modules should be in idle state. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding interrupt for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable bit vector for interrupt #n+64" group.byte 0x30++0x3 line.long 0x0 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol). DMAWAKEEN0 is for dma event inputs 31 thru 0, and DMAWAKEEN1 is for dma event inputs 63 thru 32. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding dma event for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable for event #n" group.byte 0x34++0x3 line.long 0x0 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol). DMAWAKEEN0 is for dma event inputs 31 thru 0, and DMAWAKEEN1 is for dma event inputs 63 thru 32. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding dma event for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable for event #n+32" group.byte 0x40++0x3 line.long 0x0 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state." hexmask.long 0x0 0.--31. 1. " EVENT ,Output Event for event #n" group.byte 0x44++0x3 line.long 0x0 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state." hexmask.long 0x0 0.--31. 1. " EVENT ,Output Event for event #n" group.byte 0x50++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x0 0.--18. 1. " EVENT ,Settable raw status for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long.tbyte 0x0 0.--18. 1. " EVENT ,Clearable ,Clearable ,Clearable, enabled status for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long.tbyte 0x0 0.--18. 1. " ENABLE ,Enable for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long.tbyte 0x0 0.--18. 1. " ENABLE ,Enable for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long 0x0 0.--31. 1. " EVENT ,Settable raw status for event #n" group.byte 0x64++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long 0x0 0.--31. 1. " EVENT,Clearable ,Clearable ,Clearable, enabled status for event #n" group.byte 0x68++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n" group.byte 0x6C++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n" group.byte 0x70++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long 0x0 0.--31. 1. " EVENT ,Settable raw status for event #n+32" group.byte 0x74++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long 0x0 0.--31. 1. " EVENT,Clearable ,Clearable ,Clearable, enabled status for event #n+32" group.byte 0x78++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n+32" group.byte 0x7C++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n+32" group.byte 0xF8++0x3 line.long 0x0 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus." bitfld.long 0x0 0.--3. " GROUP ,Debug Group output control mux selectN: GN = select output group N ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0xFC++0x3 line.long 0x0 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group." hexmask.long 0x0 0.--31. 1. " VALUE ,Read returns state of hw_dbgout bus" width 0x0B tree.end tree "DSP1_SYSTEM" base ad:0x40D00000 width 33. group.byte 0x0++0x3 line.long 0x0 "DSP_SYS_REVISION,DSP_SYS_REVISION" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "DSP_SYS_HWINFO,DSP_SYS_HWINFO" bitfld.long 0x0 0.--3. " NUM ,Instance Number Set by subsystem input. In a multi-DSP system, provides a unique/incrementing values for each DSP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " INFO ,0x0: No configurable options in subsystem." group.byte 0x8++0x3 line.long 0x0 "DSP_SYS_SYSCONFIG,DSP_SYS_SYSCONFIG" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,0x0: FORCE_IDLE This mode is a backup mode intended to be used only if the smart-idle mode is bugged. When in this mode, the IAF acknowledges a request to go idle from the power manager with minimal hardware condition. It is the responsibility of the software to ensure that the IAF are in a correct quiet state before requesting a force-idle transition. Additionally when in this mode, the IAF is not allowed to generate any wakeup request." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,0x0: FORCE_STANDBY This mode is a backup mode intended to be used only if the smart-idle mode is bugged. When in this mode, the SAF asserts with minimal hardware condition the 'STANDBY' status. It is the responsibility of the software to ensure that the SAF is in a correct quiet state before programming this mode. Additionally when in this mode, the SAF is not allowed to generate wakeup request." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reserved. Read returns 0." "0,1,2,3" textline " " bitfld.long 0x0 8. " RESERVED ,Reserved. User must write 0." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved. Read returns 0." group.byte 0xC++0x3 line.long 0x0 "DSP_SYS_STAT,This register is intended to provide indication to software (including a remote host) as to whether the DSP is able to enter a low power mode." bitfld.long 0x0 0. " C66X_STAT ,C66x Status" "0,1" bitfld.long 0x0 1. " TC0_STAT ,EDMA TC0 Status" "0,1" textline " " bitfld.long 0x0 2. " TC1_STAT ,EDMA TC1 Status" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--5. " OCPI_DISC_STAT ,L3_MAIN (OCP) Initiator(s) Disconnect Status" "0,1,2,3" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "DSP_SYS_DISC_CONFIG,This register is used to manually disconnect the OCP busses." bitfld.long 0x0 0. " OCPI_DISC ,OCP Initiator (on L3_MAIN) Disconnect request" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "DSP_SYS_BUS_CONFIG,This register controls the burst and priority settings for the internal initiators." bitfld.long 0x0 0.--1. " TC0_DBS ,TC0 Default Burst size" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " TC1_DBS ,TC1 Default Burst size." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " TC0_L2PRES ,TC0 L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect." "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " TC1_L2PRES ,TC1 L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " CFG_L2PRES ,DSP CFG L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect" "0,1,2,3" bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " SDMA_L2PRES ,OCP Target port L2 Interconnect Pressure. Driven on ocp mflag to control arbitration within the L2 interconnect." "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24. " NOPOSTOVERRIDE ,OCP Posted Write vs Non-Posted Write override" "0,1" bitfld.long 0x0 25.--27. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 28.--30. " SDMA_PRI ,Sets the CBA/VBusM Priority for the DSP C66x CorePac SDMA port. Can typically be left at default value. 0x0 is highest, ..., 0x7 is lowest priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x18++0x3 line.long 0x0 "DSP_SYS_MMU_CONFIG,This register is used to enable the subsystem MMUs." bitfld.long 0x0 0. " MMU0_EN ,MMU0 Enable" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " MMU1_EN ,MMU1 Enable" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " MMU0_ABORT ,MMU0 Abort" "0,1" bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12. " MMU1_ABORT ,MMU1 Abort" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "DSP_SYS_IRQWAKEEN0,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol). IRQWAKEEN0 is for interrupt inputs 63 thru 32, and IRQWAKEEN1 is for interrupt inputs 95 thru 64. Internal interrupts cannot cause a wake condition since in this state there is no guaranteed clock and all sub-modules should be in idle state. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding interrupt for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable bit vector for interrupt #n+32" group.byte 0x24++0x3 line.long 0x0 "DSP_SYS_IRQWAKEEN1,The register provides a global interrupt wakeup enable bit vector that defines which input interrupts are used to cause a wake from powerdown state (via the slave idle protocol). IRQWAKEEN0 is for interrupt inputs 63 thru 32, and IRQWAKEEN1 is for interrupt inputs 95 thru 64. Internal interrupts cannot cause a wake condition since in this state there is no guaranteed clock and all sub-modules should be in idle state. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding interrupt for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable bit vector for interrupt #n+64" group.byte 0x30++0x3 line.long 0x0 "DSP_SYS_DMAWAKEEN0,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol). DMAWAKEEN0 is for dma event inputs 31 thru 0, and DMAWAKEEN1 is for dma event inputs 63 thru 32. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding dma event for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable for event #n" group.byte 0x34++0x3 line.long 0x0 "DSP_SYS_DMAWAKEEN1,The register provides a global dma event wakeup enable bit vector that defines which input dma events are used to cause a wake from powerdown state (via the slave idle protocol). DMAWAKEEN0 is for dma event inputs 31 thru 0, and DMAWAKEEN1 is for dma event inputs 63 thru 32. Software can write 1 to set and 0 to clear the corresponding bit (i.e., enable the corresponding dma event for wakeup). Reads of this register return the actual state of the enable register." hexmask.long 0x0 0.--31. 1. " ENABLE ,Wakeup Enable for event #n+32" group.byte 0x40++0x3 line.long 0x0 "DSP_SYS_EVTOUT_SET,These registers can be used to drive event outputs from the DSP subsystem to a desired state." hexmask.long 0x0 0.--31. 1. " EVENT ,Output Event for event #n" group.byte 0x44++0x3 line.long 0x0 "DSP_SYS_EVTOUT_CLR,These registers can be used to drive event outputs from the DSP subsystem to a desired state." hexmask.long 0x0 0.--31. 1. " EVENT ,Output Event for event #n" group.byte 0x50++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long.tbyte 0x0 0.--18. 1. " EVENT ,Settable raw status for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long.tbyte 0x0 0.--18. 1. " EVENT ,Clearable ,Clearable ,Clearable, enabled status for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long.tbyte 0x0 0.--18. 1. " ENABLE ,Enable for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "DSP_SYS_ERRINT_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long.tbyte 0x0 0.--18. 1. " ENABLE ,Enable for event #n" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long 0x0 0.--31. 1. " EVENT ,Settable raw status for event #n" group.byte 0x64++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long 0x0 0.--31. 1. " EVENT,Clearable ,Clearable ,Clearable, enabled status for event #n" group.byte 0x68++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n" group.byte 0x6C++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE0_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n" group.byte 0x70++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQSTATUS_RAW,This register provides a per-event raw interrupt status vector" hexmask.long 0x0 0.--31. 1. " EVENT ,Settable raw status for event #n+32" group.byte 0x74++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQSTATUS,This register provides a per-event enabled interrupt status vector." hexmask.long 0x0 0.--31. 1. " EVENT,Clearable ,Clearable ,Clearable, enabled status for event #n+32" group.byte 0x78++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQENABLE_SET,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n+32" group.byte 0x7C++0x3 line.long 0x0 "DSP_SYS_EDMAWAKE1_IRQENABLE_CLR,This register provides a per-event interrupt enable bit vector." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enable for event #n+32" group.byte 0xF8++0x3 line.long 0x0 "DSP_SYS_HW_DBGOUT_SEL,THis register is used to select which group of internal signals are mapped to the hw_dbgout output bus." bitfld.long 0x0 0.--3. " GROUP ,Debug Group output control mux selectN: GN = select output group N ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0xFC++0x3 line.long 0x0 "DSP_SYS_HW_DBGOUT_VAL,This register is used to read the value of the currently selected debug output group." hexmask.long 0x0 0.--31. 1. " VALUE ,Read returns state of hw_dbgout bus" width 0x0B tree.end tree "DSP_FW_L2_NOC_CFG" base ad:0x1D03000 width 77. group.byte 0x0++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_ERROR_LOG_0,Core 0 Error log register" hexmask.long.word 0x0 0.--15. 1. " REQINFO_ERRLOG ,Error in reqinfo vector" bitfld.long 0x0 16.--20. " REGION_END_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGION_START_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26. " RESERVED ," "0,1" textline " " bitfld.long 0x0 27. " BLK_BURST_VIOLATION ,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x0 0.--27. 1. " SLVOFS_LOGICAL ,Address generated by the ARM before being translated" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " FW_UPDATE_REQ ,HW set/SW clear" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,HW set/SW clear" "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x88++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_0,MRM_PERMISSION_REGION_0_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x90++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_START_REGION_1,Start physical address of region 1" bitfld.long 0x0 0.--3. " START_REGION_1 ,Physical target start address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_END_REGION_1,End physical address of region 1" bitfld.long 0x0 0.--3. " END_REGION_1 ,Physical target end address of firewall region 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " END_REGION_1_ENABLE ,End Region 1 enable" "0,1" group.byte 0x98++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_LOW_1,RM_PERMISSION_REGION_1_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU0_CTRL_TARG_OCP_FW_503000_MRM_PERMISSION_REGION_HIGH_1,RM_PERMISSION_REGION_1_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x1000++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_ERROR_LOG_0,Core 0 Error log register" hexmask.long.word 0x0 0.--15. 1. " REQINFO_ERRLOG ,Error in reqinfo vector" bitfld.long 0x0 16.--20. " REGION_END_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGION_START_ERRLOG ,Wrong access hit this region number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26. " RESERVED ," "0,1" textline " " bitfld.long 0x0 27. " BLK_BURST_VIOLATION ,2D burst not allowed or exceeding allowed size" "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1004++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_LOGICAL_ADDR_ERRLOG_0,Core 0 Logical Physical Address Error log register" hexmask.long 0x0 0.--27. 1. " SLVOFS_LOGICAL ,Address generated by the ARM before being translated" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1040++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " FW_UPDATE_REQ ,HW set/SW clear" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,HW set/SW clear" "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x1088++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_LOW_0,RM_PERMISSION_REGION_0_LOW register" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Domain Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Domain Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x108C++0x3 line.long 0x0 "L3_DSPSS_INIT_OCP_MMU1_CTRL_TARG_OCP_FW_504000_MRM_PERMISSION_REGION_HIGH_0,RM_PERMISSION_REGION_0_HIGH register" bitfld.long 0x0 0. " R0 ,Initiator ID0 permission" "0,1" bitfld.long 0x0 1. " W0 ,Initiator ID0 permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Initiator ID1 permission" "0,1" bitfld.long 0x0 3. " W1 ,Initiator ID1 permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Initiator ID2 permission" "0,1" bitfld.long 0x0 5. " W2 ,Initiator ID2 permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Initiator ID3 permission" "0,1" bitfld.long 0x0 7. " W3 ,Initiator ID3 permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Initiator ID4 permission" "0,1" bitfld.long 0x0 9. " W4 ,Initiator ID4 permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Initiator ID5 permission" "0,1" bitfld.long 0x0 11. " W5 ,Initiator ID5 permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Initiator ID6 permission" "0,1" bitfld.long 0x0 13. " W6 ,Initiator ID6 permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Initiator ID7 permission" "0,1" bitfld.long 0x0 15. " W7 ,Initiator ID7 permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Initiator ID8 permission" "0,1" bitfld.long 0x0 17. " W8 ,Initiator ID8 permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Initiator ID9 permission" "0,1" bitfld.long 0x0 19. " W9 ,Initiator ID9 permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Initiator ID10 permission" "0,1" bitfld.long 0x0 21. " W10 ,Initiator ID10 permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Initiator ID11 permission" "0,1" bitfld.long 0x0 23. " W11 ,Initiator ID11 permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Initiator ID12 permission" "0,1" bitfld.long 0x0 25. " W12 ,Initiator ID12 permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Initiator ID13 permission" "0,1" bitfld.long 0x0 27. " W13 ,Initiator ID13 permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Initiator ID14 permission" "0,1" bitfld.long 0x0 29. " W14 ,Initiator ID14 permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Initiator ID15 permission" "0,1" bitfld.long 0x0 31. " W15 ,Initiator ID15 permission" "0,1" group.byte 0x4000++0x3 line.long 0x0 "DSPNOC_FLAGMUX_ID_COREID,DSPNOC_FLAGMUX_ID_COREID" hexmask.long.byte 0x0 0.--7. 1. " CORETYPEID ,Field identifying the type of IP." hexmask.long.tbyte 0x0 8.--31. 1. " CORECHECKSUM ,Field containing a checksum of the parameters of the IP." group.byte 0x4004++0x3 line.long 0x0 "DSPNOC_FLAGMUX_ID_REVISIONID,DSPNOC_FLAGMUX_ID_REVISIONID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4008++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FAULTEN,DSPNOC_FLAGMUX_FAULTEN" bitfld.long 0x0 0. " FAULTEN ,Global Fault Enable register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x400C++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FAULTSTATUS,DSPNOC_FLAGMUX_FAULTSTATUS" bitfld.long 0x0 0. " FAULTSTATUS ,Global Fault Status register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4010++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FLAGINEN0,DSPNOC_FLAGMUX_FLAGINEN0" bitfld.long 0x0 0. " FLAGINEN0 ,FlagIn Enable register #0" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4014++0x3 line.long 0x0 "DSPNOC_FLAGMUX_FLAGINSTATUS0,DSPNOC_FLAGMUX_FLAGINSTATUS0" bitfld.long 0x0 0. " FLAGINSTATUS0 ,FlagIn Status register #0" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4200++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ID_COREID,DSPNOC_ERRORLOG_ID_COREID" hexmask.long.byte 0x0 0.--7. 1. " CORETYPEID ,Field identifying the type of IP." hexmask.long.tbyte 0x0 8.--31. 1. " CORECHECKSUM ,Field containing a checksum of the parameters of the IP." group.byte 0x4204++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ID_REVISIONID,DSPNOC_ERRORLOG_ID_REVISIONID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4208++0x3 line.long 0x0 "DSPNOC_ERRORLOG_FAULTEN,DSPNOC_ERRORLOG_FAULTEN" bitfld.long 0x0 0. " FAULTEN ,Enable Fault output" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x420C++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRVLD,DSPNOC_ERRORLOG_ERRVLD" bitfld.long 0x0 0. " ERRVLD ,Error logged Valid" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4210++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRCLR,DSPNOC_ERRORLOG_ERRCLR" bitfld.long 0x0 0. " ERRCLR ,Clr ErrVld status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4214++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG0,Header: Lock, Opcode, Len1, ErrCode values" bitfld.long 0x0 0. " LOCK ,Header: Lock bit value" "0,1" bitfld.long 0x0 1.--4. " OPC ,Header: Opcode value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--10. " ERRCODE ,Header: Error Code value" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--27. 1. " LEN1 ,Header: Len1 value" textline " " bitfld.long 0x0 28.--30. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " FORMAT ,Format of ErrLog0 register" "0,1" group.byte 0x4218++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG1,DSPNOC_ERRORLOG_ERRLOG1" hexmask.long.word 0x0 0.--14. 1. " ERRLOG1 ,Header: RouteId lsb value" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x4220++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG3,DSPNOC_ERRORLOG_ERRLOG3" hexmask.long 0x0 0.--30. 1. " ERRLOG3 ,Header: Addr lsb value" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x4228++0x3 line.long 0x0 "DSPNOC_ERRORLOG_ERRLOG5,DSPNOC_ERRORLOG_ERRLOG5" hexmask.long.tbyte 0x0 0.--21. 1. " ERRLOG5 ,Header: User lsb value" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "IPU2_UNICACHE_MMU_AMMU" base ad:0x55080800 width 28. group.byte 0x0++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_0,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x4++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_1,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x8++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_2,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0xC++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_3,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x20++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_0,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x24++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_1,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x28++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_2,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x2C++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_3,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x40++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_0,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_1,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_2,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_3,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_0,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0x64++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_1,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0xA0++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_0,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xA4++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_1,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xE0++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_0,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_1,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_0,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x124++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_1,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x128++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_2,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x12C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_3,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x130++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_4,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x134++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_5,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x138++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_6,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x13C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_7,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x140++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_8,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x144++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_9,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x1A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_0,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_1,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_2,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_3,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_4,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_5,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_6,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_7,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_8,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_9,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x220++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_0,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x224++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_1,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_2,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x22C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_3,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_4,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x234++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_5,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_6,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_7,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_8,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_9,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x2A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_0,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_1,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_2,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_3,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_4,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_5,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_6,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_7,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_8,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_9,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x4A8++0x3 line.long 0x0 "CACHE_MMU_MAINT,Maintenance configuration register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " HOST_INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " bitfld.long 0x0 6. " CPU_INTERRUPT ,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "0,1" bitfld.long 0x0 7. " L1_CACHE1 ,Do maintenance operation in L1 cache" "0,1" textline " " bitfld.long 0x0 8.--9. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 10. " G_FLUSH ,Global flush bit" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "CACHE_MMU_MTSTART,Maintenance start configuration register" hexmask.long 0x0 0.--31. 1. " BEGIN_ADDRESS ,Start address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B0++0x3 line.long 0x0 "CACHE_MMU_MTEND,Maintenance end configuration register" hexmask.long 0x0 0.--31. 1. " END_ADDRESS ,End address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B4++0x3 line.long 0x0 "CACHE_MMU_MAINTST,Maintenance status register" bitfld.long 0x0 0. " STATUS ,Status bit" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved." group.byte 0x4B8++0x3 line.long 0x0 "CACHE_MMU_MMUCONFIG,MMU configuration register" bitfld.long 0x0 0. " MMU_LOCK ,MMU lock. Once this bit is set only a global flush, debugger, or hardware reset can clear." "0,1" bitfld.long 0x0 1. " PRIVILEGE ,Privilege bit. Once this bit is set, only global flush, debugger, or hardware reset can clear." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved." width 0x0B tree.end tree "IPU1_UNICACHE_MMU_AMMU" base ad:0x58880800 width 28. group.byte 0x0++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_0,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x4++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_1,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x8++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_2,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0xC++0x3 line.long 0x0 "CACHE_MMU_LARGE_ADDR_i_3,Large page address" hexmask.long 0x0 0.--24. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source address" group.byte 0x20++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_0,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x24++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_1,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x28++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_2,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x2C++0x3 line.long 0x0 "CACHE_MMU_LARGE_XLTE_i_3,Large page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.tbyte 0x0 1.--24. 1. " RESERVED ,Reserved" textline " " hexmask.long.byte 0x0 25.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x40++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_0,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_1,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_2,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "CACHE_MMU_LARGE_POLICY_i_3,Large page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_0,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0x64++0x3 line.long 0x0 "CACHE_MMU_MED_ADDR_j_1,Medium page address" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source address" group.byte 0xA0++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_0,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xA4++0x3 line.long 0x0 "CACHE_MMU_MED_XLTE_j_1,Medium page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--16. 1. " RESERVED ,Reserved." textline " " hexmask.long.word 0x0 17.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0xE0++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_0,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "CACHE_MMU_MED_POLICY_j_1,Medium page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" textline " " bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" textline " " bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_0,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x124++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_1,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x128++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_2,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x12C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_3,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x130++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_4,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x134++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_5,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x138++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_6,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x13C++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_7,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x140++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_8,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x144++0x3 line.long 0x0 "CACHE_MMU_SMALL_ADDR_k_9,Small page address" hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reserved." hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source address" group.byte 0x1A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_0,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_1,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_2,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_3,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_4,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_5,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_6,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_7,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_8,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x1C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_XLTE_k_9,Small page translated address" bitfld.long 0x0 0. " IGNORE ,Do not use translated address." "0,1" hexmask.long.word 0x0 1.--11. 1. " RESERVED ,Reserved" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " ADDRESS ,Logical source translated address" group.byte 0x220++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_0,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x224++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_1,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_2,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x22C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_3,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_4,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x234++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_5,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_6,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_7,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_8,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "CACHE_MMU_SMALL_POLICY_k_9,Small page policy" bitfld.long 0x0 0. " ENABLE ,Enable page" "0,1" bitfld.long 0x0 1. " SIZE ,Size of page" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3. " VOLATILE ,Volatile qualifier" "0,1" textline " " bitfld.long 0x0 4. " EXECUTE ,Execute only" "0,1" bitfld.long 0x0 5. " READ ,Read only" "0,1" textline " " bitfld.long 0x0 6. " PRELOAD ,Preload region" "0,1" bitfld.long 0x0 7. " EXCLUSION ,Cache exclusion" "0,1" textline " " bitfld.long 0x0 8. " COHERENCY ,Coherency" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ,Reserved." textline " " bitfld.long 0x0 16. " L1_CACHEABLE ,L1 cache policy" "0,1" bitfld.long 0x0 17. " L1_POSTED ,L1 posted policy" "0,1" textline " " bitfld.long 0x0 18. " L1_ALLOCATE ,L1 allocate policy" "0,1" bitfld.long 0x0 19. " L1_WR_POLICY ,L1 write policy" "0,1" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x2A0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_0,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_1,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2A8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_2,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2AC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_3,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_4,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_5,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2B8++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_6,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2BC++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_7,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C0++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_8,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x2C4++0x3 line.long 0x0 "CACHE_MMU_SMALL_MAINT_k_9,Small page maintenance configuration" bitfld.long 0x0 0. " PRELOAD ,Preload page" "0,1" bitfld.long 0x0 1. " LOCK ,Lock page" "0,1" textline " " bitfld.long 0x0 2. " CLEAN ,Evict page" "0,1" bitfld.long 0x0 3. " INVALIDATE ,Invalidate page" "0,1" textline " " bitfld.long 0x0 4. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved." group.byte 0x4A8++0x3 line.long 0x0 "CACHE_MMU_MAINT,Maintenance configuration register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " HOST_INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " bitfld.long 0x0 6. " CPU_INTERRUPT ,Generate interrupt to cpu when maintenance operation initiated by CPU is complete" "0,1" bitfld.long 0x0 7. " L1_CACHE1 ,Do maintenance operation in L1 cache" "0,1" textline " " bitfld.long 0x0 8.--9. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 10. " G_FLUSH ,Global flush bit" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "CACHE_MMU_MTSTART,Maintenance start configuration register" hexmask.long 0x0 0.--31. 1. " BEGIN_ADDRESS ,Start address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B0++0x3 line.long 0x0 "CACHE_MMU_MTEND,Maintenance end configuration register" hexmask.long 0x0 0.--31. 1. " END_ADDRESS ,End address of maintenance operations, resets to 0x0000 0000 when finished" group.byte 0x4B4++0x3 line.long 0x0 "CACHE_MMU_MAINTST,Maintenance status register" bitfld.long 0x0 0. " STATUS ,Status bit" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved." group.byte 0x4B8++0x3 line.long 0x0 "CACHE_MMU_MMUCONFIG,MMU configuration register" bitfld.long 0x0 0. " MMU_LOCK ,MMU lock. Once this bit is set only a global flush, debugger, or hardware reset can clear." "0,1" bitfld.long 0x0 1. " PRIVILEGE ,Privilege bit. Once this bit is set, only global flush, debugger, or hardware reset can clear." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved." width 0x0B tree.end tree "IPU2_UNICACHE_SCTM" base ad:0x55080400 width 25. group.byte 0x0++0x3 line.long 0x0 "CACHE_SCTM_CTCNTL,CACHE_SCTM_CTCNTL" bitfld.long 0x0 0. " ENBL ,SCTM global enable" "0,1" bitfld.long 0x0 1.--2. " IDLEMODE ,Idle mode control" "0,1,2,3" textline " " bitfld.long 0x0 3.--6. " REVISION ,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 7.--12. " NUMCNTR ,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 13.--17. " NUMTIMR ,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 18.--25. 1. " NUMINPT ,Number of event input signals" textline " " bitfld.long 0x0 26.--31. " NUMSTM ,Number of timers that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x40++0x3 line.long 0x0 "CACHE_SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" hexmask.long 0x0 0.--31. 1. " INTERVAL ,Interval match value for the timers in the SCTM" group.byte 0x44++0x3 line.long 0x0 "CACHE_SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" hexmask.long 0x0 0.--31. 1. " INTERVAL ,Interval match value for the timers in the SCTM" group.byte 0x7C++0x3 line.long 0x0 "CACHE_SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x0 0.--2. " NUMEVT ,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved." group.byte 0xF0++0x3 line.long 0x0 "CACHE_SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x0 0.--7. 1. " ENABLE ,The counter enable bit field" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0xF8++0x3 line.long 0x0 "CACHE_SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x0 0.--7. 1. " RESET ,The counter reset bit field" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0x100++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WT_i_0,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WT: with timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "0,1" bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "0,1" textline " " bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match" "0,1" bitfld.long 0x0 11.--15. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection1-31: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x104++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WT_i_1,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WT: with timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "0,1" bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "0,1" textline " " bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match" "0,1" bitfld.long 0x0 11.--15. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection1-31: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x108++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_0,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x10C++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_1,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x110++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_2,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x114++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_3,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x118++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_4,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x11C++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_5,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x180++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x184++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x188++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x18C++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x190++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x194++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x198++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x19C++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" width 0x0B tree.end tree "IPU1_UNICACHE_SCTM" base ad:0x58880400 width 25. group.byte 0x0++0x3 line.long 0x0 "CACHE_SCTM_CTCNTL,CACHE_SCTM_CTCNTL" bitfld.long 0x0 0. " ENBL ,SCTM global enable" "0,1" bitfld.long 0x0 1.--2. " IDLEMODE ,Idle mode control" "0,1,2,3" textline " " bitfld.long 0x0 3.--6. " REVISION ,Revision ID of SCTM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 7.--12. " NUMCNTR ,Number of counters in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 13.--17. " NUMTIMR ,Number of timers in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 18.--25. 1. " NUMINPT ,Number of event input signals" textline " " bitfld.long 0x0 26.--31. " NUMSTM ,Number of timers that can export via STM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x40++0x3 line.long 0x0 "CACHE_SCTM_TINTVLR_i_0,These registers contain the interval match value for the corresponding timers in the SCTM" hexmask.long 0x0 0.--31. 1. " INTERVAL ,Interval match value for the timers in the SCTM" group.byte 0x44++0x3 line.long 0x0 "CACHE_SCTM_TINTVLR_i_1,These registers contain the interval match value for the corresponding timers in the SCTM" hexmask.long 0x0 0.--31. 1. " INTERVAL ,Interval match value for the timers in the SCTM" group.byte 0x7C++0x3 line.long 0x0 "CACHE_SCTM_CTDBGNUM,Counter Timer Number Debug Event Register" bitfld.long 0x0 0.--2. " NUMEVT ,Number of input selectors for debug events" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved." group.byte 0xF0++0x3 line.long 0x0 "CACHE_SCTM_CTGNBL,These registers provide for simultaneous enable/disable of 32 counters" hexmask.long.byte 0x0 0.--7. 1. " ENABLE ,The counter enable bit field" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0xF8++0x3 line.long 0x0 "CACHE_SCTM_CTGRST,These registers provide for simultaneous reset of 32 counters" hexmask.long.byte 0x0 0.--7. 1. " RESET ,The counter reset bit field" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0x100++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WT_i_0,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WT: with timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "0,1" bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "0,1" textline " " bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match" "0,1" bitfld.long 0x0 11.--15. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection1-31: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x104++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WT_i_1,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WT: with timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " bitfld.long 0x0 8. " INT ,Generate interrupt on interval match" "0,1" bitfld.long 0x0 9. " DBG ,Signal debug logic on interval match" "0,1" textline " " bitfld.long 0x0 10. " RESTART ,Restart the timer after an interval match" "0,1" bitfld.long 0x0 11.--15. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " INPSEL ,Counter Timer input selection1-31: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x108++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_0,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x10C++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_1,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x110++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_2,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x114++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_3,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x118++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_4,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x11C++0x3 line.long 0x0 "CACHE_SCTM_CTCR_WOT_j_5,These registers contain the control and status settings for a single counter in the module. There will be a CTCR for every counter in the module (WOT: without timer)" bitfld.long 0x0 0. " ENBL ,Counter enable control" "0,1" bitfld.long 0x0 1. " RESET ,Counter reset control" "0,1" textline " " bitfld.long 0x0 2. " CHAIN ,Counter is chained to an adjacent counter" "0,1" bitfld.long 0x0 3. " DURMODE ,Counter is in duration or occurrence mode" "0,1" textline " " bitfld.long 0x0 4. " FREE ,Counter ignores processor debug halt state" "0,1" bitfld.long 0x0 5. " IDLE ,Counter ignores processor IDLE state" "0,1" textline " " bitfld.long 0x0 6. " OVRFLW ,Counter has wrapped since it was last read" "0,1" bitfld.long 0x0 7. " CHNSDW ,Counter has a shadow register for chain reads." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved." bitfld.long 0x0 16.--20. " INPSEL ,Counter input selection131: Index of event input signal selected ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x180++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_0,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x184++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_1,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x188++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_2,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x18C++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_3,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x190++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_4,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x194++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_5,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x198++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_6,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" group.byte 0x19C++0x3 line.long 0x0 "CACHE_SCTM_CTCNTR_k_7,These registers contain the value of an individual counter in the module. There will be a CTCNTR for every counter in the module" hexmask.long 0x0 0.--31. 1. " COUNT ,Counter value" width 0x0B tree.end tree "IPU2_WUGEN" base ad:0x55081000 width 24. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_CTRL_REG,The register is used by one CPU to interrupt the other, thus used as a handshake between the two CPUs 0x0: Interrupt is cleared; 0x1: Interrupt is set." bitfld.long 0x0 0. " INT_CORTEX_1 ,Interrupt to IPUx_C0" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " INT_CORTEX_2 ,Interrupt to IPUx_C1" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "STANDBY_CORE_SYSCONFIG,Standby protocol" bitfld.long 0x0 0.--1. " STANDBYMODE ,0x0: Force-standby mode" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "IDLE_CORE_SYSCONFIG,Idle protocol" bitfld.long 0x0 0.--1. " IDLEMODE ,0x0: Force-idle mode" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "WUGEN_MEVT0,This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request: 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x0 0. " MIRQ0 ,Interrupt Mask bit 0" "0,1" bitfld.long 0x0 1. " MIRQ1 ,Interrupt Mask bit 1" "0,1" textline " " bitfld.long 0x0 2. " MIRQ2 ,Interrupt Mask bit 2" "0,1" bitfld.long 0x0 3. " MIRQ3 ,Interrupt Mask bit 3" "0,1" textline " " bitfld.long 0x0 4. " MIRQ4 ,Interrupt Mask bit 4" "0,1" bitfld.long 0x0 5. " MIRQ5 ,Interrupt Mask bit 5" "0,1" textline " " bitfld.long 0x0 6. " MIRQ6 ,Interrupt Mask bit 6" "0,1" bitfld.long 0x0 7. " MIRQ7 ,Interrupt Mask bit 7" "0,1" textline " " bitfld.long 0x0 8. " MIRQ8 ,Interrupt Mask bit 8" "0,1" bitfld.long 0x0 9. " MIRQ9 ,Interrupt Mask bit 9" "0,1" textline " " bitfld.long 0x0 10. " MIRQ10 ,Interrupt Mask bit 10" "0,1" bitfld.long 0x0 11. " MIRQ11 ,Interrupt Mask bit 11" "0,1" textline " " bitfld.long 0x0 12. " MIRQ12 ,Interrupt Mask bit 12" "0,1" bitfld.long 0x0 13. " MIRQ13 ,Interrupt Mask bit 13" "0,1" textline " " bitfld.long 0x0 14. " MIRQ14 ,Interrupt Mask bit 14" "0,1" bitfld.long 0x0 15. " MIRQ15 ,Interrupt Mask bit 15" "0,1" textline " " bitfld.long 0x0 16. " MIRQ16 ,Interrupt Mask bit 16" "0,1" bitfld.long 0x0 17. " MIRQ17 ,Interrupt Mask bit 17" "0,1" textline " " bitfld.long 0x0 18. " MIRQ18 ,Interrupt Mask bit 18" "0,1" bitfld.long 0x0 19. " MIRQ19 ,Interrupt Mask bit 19" "0,1" textline " " bitfld.long 0x0 20. " MIRQ20 ,Interrupt Mask bit 20" "0,1" bitfld.long 0x0 21. " MIRQ21 ,Interrupt Mask bit 21" "0,1" textline " " bitfld.long 0x0 22. " MIRQ22 ,Interrupt Mask bit 22" "0,1" bitfld.long 0x0 23. " MIRQ23 ,Interrupt Mask bit 23" "0,1" textline " " bitfld.long 0x0 24. " MIRQ24 ,Interrupt Mask bit 24" "0,1" bitfld.long 0x0 25. " MIRQ25 ,Interrupt Mask bit 25" "0,1" textline " " bitfld.long 0x0 26. " MIRQ26 ,Interrupt Mask bit 26" "0,1" bitfld.long 0x0 27. " MIRQ27 ,Interrupt Mask bit 27" "0,1" textline " " bitfld.long 0x0 28. " MIRQ28 ,Interrupt Mask bit 28" "0,1" bitfld.long 0x0 29. " MIRQ29 ,Interrupt Mask bit 29" "0,1" textline " " bitfld.long 0x0 30. " MIRQ30 ,Interrupt Mask bit 30" "0,1" bitfld.long 0x0 31. " MIRQ31 ,Interrupt Mask bit 31" "0,1" group.byte 0x10++0x3 line.long 0x0 "WUGEN_MEVT1,This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request: 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x0 0. " MIRQ32 ,Interrupt Mask bit 32" "0,1" bitfld.long 0x0 1. " MIRQ33 ,Interrupt Mask bit 33" "0,1" textline " " bitfld.long 0x0 2. " MIRQ34 ,Interrupt Mask bit 34" "0,1" bitfld.long 0x0 3. " MIRQ35 ,Interrupt Mask bit 35" "0,1" textline " " bitfld.long 0x0 4. " MIRQ36 ,Interrupt Mask bit 36" "0,1" bitfld.long 0x0 5. " MIRQ37 ,Interrupt Mask bit 37" "0,1" textline " " bitfld.long 0x0 6. " MIRQ38 ,Interrupt Mask bit 38" "0,1" bitfld.long 0x0 7. " MIRQ39 ,Interrupt Mask bit 39" "0,1" textline " " bitfld.long 0x0 8. " MIRQ40 ,Interrupt Mask bit 40" "0,1" bitfld.long 0x0 9. " MIRQ41 ,Interrupt Mask bit 41" "0,1" textline " " bitfld.long 0x0 10. " MIRQ42 ,Interrupt Mask bit 42" "0,1" bitfld.long 0x0 11. " MIRQ43 ,Interrupt Mask bit 43" "0,1" textline " " bitfld.long 0x0 12. " MIRQ44 ,Interrupt Mask bit 44" "0,1" bitfld.long 0x0 13. " MIRQ45 ,Interrupt Mask bit 45" "0,1" textline " " bitfld.long 0x0 14. " MIRQ46 ,Interrupt Mask bit 46" "0,1" bitfld.long 0x0 15. " MIRQ47 ,Interrupt Mask bit 47" "0,1" textline " " bitfld.long 0x0 16. " MIRQ48 ,Interrupt Mask bit 48" "0,1" bitfld.long 0x0 17. " MIRQ49 ,Interrupt Mask bit 49" "0,1" textline " " bitfld.long 0x0 18. " MIRQ50 ,Interrupt Mask bit 50" "0,1" bitfld.long 0x0 19. " MIRQ51 ,Interrupt Mask bit 51" "0,1" textline " " bitfld.long 0x0 20. " MIRQ52 ,Interrupt Mask bit 52" "0,1" bitfld.long 0x0 21. " MIRQ53 ,Interrupt Mask bit 53" "0,1" textline " " bitfld.long 0x0 22. " MIRQ54 ,Interrupt Mask bit 54" "0,1" bitfld.long 0x0 23. " MIRQ55 ,Interrupt Mask bit 55" "0,1" textline " " bitfld.long 0x0 24. " MIRQ56 ,Interrupt Mask bit 56" "0,1" bitfld.long 0x0 25. " MIRQ57 ,Interrupt Mask bit 57" "0,1" textline " " bitfld.long 0x0 26. " MIRQ58 ,Interrupt Mask bit 58" "0,1" bitfld.long 0x0 27. " MIRQ59 ,Interrupt Mask bit 59" "0,1" textline " " bitfld.long 0x0 28. " MIRQ60 ,Interrupt Mask bit 60" "0,1" bitfld.long 0x0 29. " MIRQ61 ,Interrupt Mask bit 61" "0,1" textline " " bitfld.long 0x0 30. " MIRQ62 ,Interrupt Mask bit 62" "0,1" bitfld.long 0x0 31. " MIRQ63 ,Interrupt Mask bit 63" "0,1" width 0x0B tree.end tree "IPU1_WUGEN" base ad:0x58881000 width 24. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_CTRL_REG,The register is used by one CPU to interrupt the other, thus used as a handshake between the two CPUs 0x0: Interrupt is cleared; 0x1: Interrupt is set." bitfld.long 0x0 0. " INT_CORTEX_1 ,Interrupt to IPUx_C0" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " INT_CORTEX_2 ,Interrupt to IPUx_C1" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "STANDBY_CORE_SYSCONFIG,Standby protocol" bitfld.long 0x0 0.--1. " STANDBYMODE ,0x0: Force-standby mode" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "IDLE_CORE_SYSCONFIG,Idle protocol" bitfld.long 0x0 0.--1. " IDLEMODE ,0x0: Force-idle mode" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "WUGEN_MEVT0,This register contains the interrupt mask (LSB) wake-up enable bit per interrupt request: 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x0 0. " MIRQ0 ,Interrupt Mask bit 0" "0,1" bitfld.long 0x0 1. " MIRQ1 ,Interrupt Mask bit 1" "0,1" textline " " bitfld.long 0x0 2. " MIRQ2 ,Interrupt Mask bit 2" "0,1" bitfld.long 0x0 3. " MIRQ3 ,Interrupt Mask bit 3" "0,1" textline " " bitfld.long 0x0 4. " MIRQ4 ,Interrupt Mask bit 4" "0,1" bitfld.long 0x0 5. " MIRQ5 ,Interrupt Mask bit 5" "0,1" textline " " bitfld.long 0x0 6. " MIRQ6 ,Interrupt Mask bit 6" "0,1" bitfld.long 0x0 7. " MIRQ7 ,Interrupt Mask bit 7" "0,1" textline " " bitfld.long 0x0 8. " MIRQ8 ,Interrupt Mask bit 8" "0,1" bitfld.long 0x0 9. " MIRQ9 ,Interrupt Mask bit 9" "0,1" textline " " bitfld.long 0x0 10. " MIRQ10 ,Interrupt Mask bit 10" "0,1" bitfld.long 0x0 11. " MIRQ11 ,Interrupt Mask bit 11" "0,1" textline " " bitfld.long 0x0 12. " MIRQ12 ,Interrupt Mask bit 12" "0,1" bitfld.long 0x0 13. " MIRQ13 ,Interrupt Mask bit 13" "0,1" textline " " bitfld.long 0x0 14. " MIRQ14 ,Interrupt Mask bit 14" "0,1" bitfld.long 0x0 15. " MIRQ15 ,Interrupt Mask bit 15" "0,1" textline " " bitfld.long 0x0 16. " MIRQ16 ,Interrupt Mask bit 16" "0,1" bitfld.long 0x0 17. " MIRQ17 ,Interrupt Mask bit 17" "0,1" textline " " bitfld.long 0x0 18. " MIRQ18 ,Interrupt Mask bit 18" "0,1" bitfld.long 0x0 19. " MIRQ19 ,Interrupt Mask bit 19" "0,1" textline " " bitfld.long 0x0 20. " MIRQ20 ,Interrupt Mask bit 20" "0,1" bitfld.long 0x0 21. " MIRQ21 ,Interrupt Mask bit 21" "0,1" textline " " bitfld.long 0x0 22. " MIRQ22 ,Interrupt Mask bit 22" "0,1" bitfld.long 0x0 23. " MIRQ23 ,Interrupt Mask bit 23" "0,1" textline " " bitfld.long 0x0 24. " MIRQ24 ,Interrupt Mask bit 24" "0,1" bitfld.long 0x0 25. " MIRQ25 ,Interrupt Mask bit 25" "0,1" textline " " bitfld.long 0x0 26. " MIRQ26 ,Interrupt Mask bit 26" "0,1" bitfld.long 0x0 27. " MIRQ27 ,Interrupt Mask bit 27" "0,1" textline " " bitfld.long 0x0 28. " MIRQ28 ,Interrupt Mask bit 28" "0,1" bitfld.long 0x0 29. " MIRQ29 ,Interrupt Mask bit 29" "0,1" textline " " bitfld.long 0x0 30. " MIRQ30 ,Interrupt Mask bit 30" "0,1" bitfld.long 0x0 31. " MIRQ31 ,Interrupt Mask bit 31" "0,1" group.byte 0x10++0x3 line.long 0x0 "WUGEN_MEVT1,This register contains the interrupt mask (MSB) wake-up enable bit per interrupt request: 0x0: Interrupt is disabled; 0x1: Interrupt is enabled." bitfld.long 0x0 0. " MIRQ32 ,Interrupt Mask bit 32" "0,1" bitfld.long 0x0 1. " MIRQ33 ,Interrupt Mask bit 33" "0,1" textline " " bitfld.long 0x0 2. " MIRQ34 ,Interrupt Mask bit 34" "0,1" bitfld.long 0x0 3. " MIRQ35 ,Interrupt Mask bit 35" "0,1" textline " " bitfld.long 0x0 4. " MIRQ36 ,Interrupt Mask bit 36" "0,1" bitfld.long 0x0 5. " MIRQ37 ,Interrupt Mask bit 37" "0,1" textline " " bitfld.long 0x0 6. " MIRQ38 ,Interrupt Mask bit 38" "0,1" bitfld.long 0x0 7. " MIRQ39 ,Interrupt Mask bit 39" "0,1" textline " " bitfld.long 0x0 8. " MIRQ40 ,Interrupt Mask bit 40" "0,1" bitfld.long 0x0 9. " MIRQ41 ,Interrupt Mask bit 41" "0,1" textline " " bitfld.long 0x0 10. " MIRQ42 ,Interrupt Mask bit 42" "0,1" bitfld.long 0x0 11. " MIRQ43 ,Interrupt Mask bit 43" "0,1" textline " " bitfld.long 0x0 12. " MIRQ44 ,Interrupt Mask bit 44" "0,1" bitfld.long 0x0 13. " MIRQ45 ,Interrupt Mask bit 45" "0,1" textline " " bitfld.long 0x0 14. " MIRQ46 ,Interrupt Mask bit 46" "0,1" bitfld.long 0x0 15. " MIRQ47 ,Interrupt Mask bit 47" "0,1" textline " " bitfld.long 0x0 16. " MIRQ48 ,Interrupt Mask bit 48" "0,1" bitfld.long 0x0 17. " MIRQ49 ,Interrupt Mask bit 49" "0,1" textline " " bitfld.long 0x0 18. " MIRQ50 ,Interrupt Mask bit 50" "0,1" bitfld.long 0x0 19. " MIRQ51 ,Interrupt Mask bit 51" "0,1" textline " " bitfld.long 0x0 20. " MIRQ52 ,Interrupt Mask bit 52" "0,1" bitfld.long 0x0 21. " MIRQ53 ,Interrupt Mask bit 53" "0,1" textline " " bitfld.long 0x0 22. " MIRQ54 ,Interrupt Mask bit 54" "0,1" bitfld.long 0x0 23. " MIRQ55 ,Interrupt Mask bit 55" "0,1" textline " " bitfld.long 0x0 24. " MIRQ56 ,Interrupt Mask bit 56" "0,1" bitfld.long 0x0 25. " MIRQ57 ,Interrupt Mask bit 57" "0,1" textline " " bitfld.long 0x0 26. " MIRQ58 ,Interrupt Mask bit 58" "0,1" bitfld.long 0x0 27. " MIRQ59 ,Interrupt Mask bit 59" "0,1" textline " " bitfld.long 0x0 28. " MIRQ60 ,Interrupt Mask bit 60" "0,1" bitfld.long 0x0 29. " MIRQ61 ,Interrupt Mask bit 61" "0,1" textline " " bitfld.long 0x0 30. " MIRQ62 ,Interrupt Mask bit 62" "0,1" bitfld.long 0x0 31. " MIRQ63 ,Interrupt Mask bit 63" "0,1" width 0x0B tree.end tree "IPU2_UNICACHE_CFG" base ad:0x55080000 width 15. group.byte 0x4++0x3 line.long 0x0 "CACHE_CONFIG,Configuration Register" bitfld.long 0x0 0. " CACHE_LOCK ,Unicache lock. Once this bit is set only debugger or hardware reset can clear." "0,1" bitfld.long 0x0 1. " BYPASS ,Bypass cache" "0,1" textline " " bitfld.long 0x0 2. " LOCK_INT ,Lock access to interrupt registers" "0,1" bitfld.long 0x0 3. " LOCK_PORT ,Lock access to interface registers" "0,1" textline " " bitfld.long 0x0 4. " LOCK_MAIN ,Lock access to maintenance registers" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "CACHE_INT,Interrupt Register" bitfld.long 0x0 0. " CONFIG ,Configuration error" "0,1" bitfld.long 0x0 1. " PAGEFAULT ,Unicache MMU page fault" "0,1" textline " " bitfld.long 0x0 2. " MAINT ,Maintenance is completed" "0,1" bitfld.long 0x0 3. " WRITE ,Interface write response error" "0,1" textline " " bitfld.long 0x0 4. " READ ,Interface read response error" "0,1" bitfld.long 0x0 5.--8. " PORT ,Slave interface number that has recorded an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved." group.byte 0xC++0x3 line.long 0x0 "CACHE_OCP,Interface Configuration Register" bitfld.long 0x0 0. " WRAP ,OCP wrap mode (critical word first)" "0,1" bitfld.long 0x0 1. " WRBUFFER ,Write throughs and write back no allocate are buffered" "0,1" textline " " bitfld.long 0x0 2. " WRALLOCATE ,Follow write allocate sideband signals" "0,1" bitfld.long 0x0 3. " CACHED ,Follow cacheable sideband signals" "0,1" textline " " bitfld.long 0x0 4. " PREFETCH ,Always prefetch data" "0,1" bitfld.long 0x0 5. " CLEANBUF ,Clean write and prefetch buffers in cache" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved." group.byte 0x10++0x3 line.long 0x0 "CACHE_MAINT,Maintenance Configuration Register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved." group.byte 0x14++0x3 line.long 0x0 "CACHE_MTSTART,Maintenance Start Configuration Register" hexmask.long 0x0 0.--31. 1. " START_ADDR ,Start address of maintenance operations, reset to 0x0000 0000 when finished" group.byte 0x18++0x3 line.long 0x0 "CACHE_MTEND,Maintenance End Configuration Register" hexmask.long 0x0 0.--31. 1. " END_ADDR ,End address of maintenance operations, reset to 0x0000 0000 when finished" group.byte 0x1C++0x3 line.long 0x0 "CACHE_CTADDR,Cache Test Address Register" hexmask.long 0x0 0.--31. 1. " ADDRESS ,Address of cache visibility when readCACHE_CTDATA register, autoincrements" group.byte 0x20++0x3 line.long 0x0 "CACHE_CTDATA,Cache Test Data Register" hexmask.long 0x0 0.--31. 1. " DATA ,Cache data at address ofCACHE_CTADDR register, CACHE_CTADDR autoincrements each time CACHE_CTDATA is read" width 0x0B tree.end tree "IPU1_UNICACHE_CFG" base ad:0x58880000 width 15. group.byte 0x4++0x3 line.long 0x0 "CACHE_CONFIG,Configuration Register" bitfld.long 0x0 0. " CACHE_LOCK ,Unicache lock. Once this bit is set only debugger or hardware reset can clear." "0,1" bitfld.long 0x0 1. " BYPASS ,Bypass cache" "0,1" textline " " bitfld.long 0x0 2. " LOCK_INT ,Lock access to interrupt registers" "0,1" bitfld.long 0x0 3. " LOCK_PORT ,Lock access to interface registers" "0,1" textline " " bitfld.long 0x0 4. " LOCK_MAIN ,Lock access to maintenance registers" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "CACHE_INT,Interrupt Register" bitfld.long 0x0 0. " CONFIG ,Configuration error" "0,1" bitfld.long 0x0 1. " PAGEFAULT ,Unicache MMU page fault" "0,1" textline " " bitfld.long 0x0 2. " MAINT ,Maintenance is completed" "0,1" bitfld.long 0x0 3. " WRITE ,Interface write response error" "0,1" textline " " bitfld.long 0x0 4. " READ ,Interface read response error" "0,1" bitfld.long 0x0 5.--8. " PORT ,Slave interface number that has recorded an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved." group.byte 0xC++0x3 line.long 0x0 "CACHE_OCP,Interface Configuration Register" bitfld.long 0x0 0. " WRAP ,OCP wrap mode (critical word first)" "0,1" bitfld.long 0x0 1. " WRBUFFER ,Write throughs and write back no allocate are buffered" "0,1" textline " " bitfld.long 0x0 2. " WRALLOCATE ,Follow write allocate sideband signals" "0,1" bitfld.long 0x0 3. " CACHED ,Follow cacheable sideband signals" "0,1" textline " " bitfld.long 0x0 4. " PREFETCH ,Always prefetch data" "0,1" bitfld.long 0x0 5. " CLEANBUF ,Clean write and prefetch buffers in cache" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved." group.byte 0x10++0x3 line.long 0x0 "CACHE_MAINT,Maintenance Configuration Register" bitfld.long 0x0 0. " PRELOAD ,Preload region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 1. " LOCK ,Lock region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 2. " UNLOCK ,Unlock region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 3. " CLEAN ,Evict dirty lines in region defined by maintenance start/end addresses" "0,1" textline " " bitfld.long 0x0 4. " INVALIDATE ,Invalidate lines in region defined by maintenance start/end addresses" "0,1" bitfld.long 0x0 5. " INTERRUPT ,Generate interrupt when maintenance operation is complete" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved." group.byte 0x14++0x3 line.long 0x0 "CACHE_MTSTART,Maintenance Start Configuration Register" hexmask.long 0x0 0.--31. 1. " START_ADDR ,Start address of maintenance operations, reset to 0x0000 0000 when finished" group.byte 0x18++0x3 line.long 0x0 "CACHE_MTEND,Maintenance End Configuration Register" hexmask.long 0x0 0.--31. 1. " END_ADDR ,End address of maintenance operations, reset to 0x0000 0000 when finished" group.byte 0x1C++0x3 line.long 0x0 "CACHE_CTADDR,Cache Test Address Register" hexmask.long 0x0 0.--31. 1. " ADDRESS ,Address of cache visibility when readCACHE_CTDATA register, autoincrements" group.byte 0x20++0x3 line.long 0x0 "CACHE_CTDATA,Cache Test Data Register" hexmask.long 0x0 0.--31. 1. " DATA ,Cache data at address ofCACHE_CTADDR register, CACHE_CTADDR autoincrements each time CACHE_CTDATA is read" width 0x0B tree.end tree "IPU1_C0_RW_TABLE" base ad:0xE00FE000 width 18. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_RW_PID1,Peripheral Identification register allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD1 ,IPUx_ROM memory address" group.byte 0x4++0x3 line.long 0x0 "CORTEXM4_RW_PID2,Peripheral Identification register  allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD2 ,IPUx_ROM memory address" width 0x0B tree.end tree "IPU1_C1_RW_TABLE" base ad:0xE00FE000 width 18. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_RW_PID1,Peripheral Identification register allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD1 ,IPUx_ROM memory address" group.byte 0x4++0x3 line.long 0x0 "CORTEXM4_RW_PID2,Peripheral Identification register  allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD2 ,IPUx_ROM memory address" width 0x0B tree.end tree "IPU2_C0_RW_TABLE" base ad:0xE00FE000 width 18. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_RW_PID1,Peripheral Identification register allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD1 ,IPUx_ROM memory address" group.byte 0x4++0x3 line.long 0x0 "CORTEXM4_RW_PID2,Peripheral Identification register  allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD2 ,IPUx_ROM memory address" width 0x0B tree.end tree "IPU2_C1_RW_TABLE" base ad:0xE00FE000 width 18. group.byte 0x0++0x3 line.long 0x0 "CORTEXM4_RW_PID1,Peripheral Identification register allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD1 ,IPUx_ROM memory address" group.byte 0x4++0x3 line.long 0x0 "CORTEXM4_RW_PID2,Peripheral Identification register  allows the user software to differentiate between the two ARM Cortex-M4 processors (two CPUs). The same piece of code running on the two CPUs can result in different execution (for example, branch to different location) depending on the address stored in the register. The address is stored by the BIOS code. The register cannot be accessed when the BIOS code is running (used)." hexmask.long 0x0 0.--31. 1. " BASEADD2 ,IPUx_ROM memory address" width 0x0B tree.end tree "VIP1_VPDMA" base ad:0x4897D000 width 31. group.byte 0x0++0x3 line.long 0x0 "VIP_PID,PID VIP VPDMA register" hexmask.long 0x0 0.--31. 1. " PID ,PID of VPDMA module" group.byte 0x4++0x3 line.long 0x0 "VIP_LIST_ADDR,The location of a new list to begin processing." hexmask.long 0x0 0.--31. 1. " VIP_LIST_ADDR ,Location of a new list of descriptors. This register must be written with the VPDMA Configuration Location after reset." group.byte 0x8++0x3 line.long 0x0 "VIP_LIST_ATTR,The attributes of a new list. This register should always be written after." hexmask.long.word 0x0 0.--15. 1. " LIST_SIZE ,Number of 128 bit word in the new list of descriptors. Writes to this register will activate the list in the list stack of the list manager and begin transfer of the list into VPDMA. This size can not be 0." bitfld.long 0x0 16.--18. " LIST_TYPE ,The type of list that has been generated.\\n0: Normal List\\n1: Self-Modifying List\\n2: List Doorbell\\nOthers Reserved for future use" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RDY ,This bit is low when a new list cannot be written to theVIP_LIST_ADDR register. The reasons this bit would be low are at initial startup if the LIST_MANAGER State Machine image has not completed loading. It also would be low if the last write to the VIP_LIST_ATTR attempted to start a list that is currently active. When this bit is low any writes to the list address register will cause access to not be accepted until this bit has set by the previous list having completed." "0,1" bitfld.long 0x0 20. " STOP ,This bit is written with the LIST_NUMBER field to stop a self-modifying list. When this bit is written a one the list specified by the LIST_NUMBER is sent a stop signal and will finish the current frame of transfers and then free the list resources." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " LIST_NUM ,The list number that should be assigned to the list located atVIP_LIST_ADDR. If the list is still active this will block all future list writes until the list is available." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xC++0x3 line.long 0x0 "VIP_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list." bitfld.long 0x0 0. " SYNC_LISTS0 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it." "0,1" bitfld.long 0x0 1. " SYNC_LISTS1 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it." "0,1" textline " " bitfld.long 0x0 2. " SYNC_LISTS2 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it." "0,1" bitfld.long 0x0 3. " SYNC_LISTS3 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it." "0,1" textline " " bitfld.long 0x0 4. " SYNC_LISTS4 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it." "0,1" bitfld.long 0x0 5. " SYNC_LISTS5 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it." "0,1" textline " " bitfld.long 0x0 6. " SYNC_LISTS6 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it." "0,1" bitfld.long 0x0 7. " SYNC_LISTS7 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " LIST0_BUSY ,The list 0 is currently running. Any attempt to load a new list to list 0 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 17. " LIST1_BUSY ,The list 1 is currently running. Any attempt to load a new list to list 1 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 18. " LIST2_BUSY ,The list 2 is currently running. Any attempt to load a new list to list 2 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 19. " LIST3_BUSY ,The list 3 is currently running. Any attempt to load a new list to list 3 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 20. " LIST4_BUSY ,The list 4 is currently running. Any attempt to load a new list to list 4 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 21. " LIST5_BUSY ,The list 5 is currently running. Any attempt to load a new list to list 5 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 22. " LIST6_BUSY ,The list 6 is currently running. Any attempt to load a new list to list 6 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 23. " LIST7_BUSY ,The list 7 is currently running. Any attempt to load a new list to list 7 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "VIP_BG_RGB,The registers used to set the background color for RGB" hexmask.long.byte 0x0 0.--7. 1. " BLEND ,The blend value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 8.--15. 1. " BLUE ,The blue value to give on an RGB data port for a blank pixel when using virtual video buffering" textline " " hexmask.long.byte 0x0 16.--23. 1. " GREEN ,The green value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 24.--31. 1. " RED ,The red value to give on an RGB data port for a blank pixel when using virtual video buffering" group.byte 0x1C++0x3 line.long 0x0 "VIP_BG_YUV,The registers used to set the background color for YUV" hexmask.long.byte 0x0 0.--7. 1. " CB ,The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 8.--15. 1. " CR ,The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering" textline " " hexmask.long.byte 0x0 16.--23. 1. " Y ,The Y value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "VIP_VPDMA_SETUP,Configures global parameters that are shared by all clients." bitfld.long 0x0 0. " SEC_BASE_CH ,Use Secondary Channels for Mosaic mode" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 1 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 1 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x38++0x3 line.long 0x0 "VIP_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 2 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 2 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x3C++0x3 line.long 0x0 "VIP_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 3 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 3 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x40++0x3 line.long 0x0 "VIP_INT0_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_HQ_VID1_LUMA ,The last write DMA transaction has completed for channel hq_vid1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_HQ_VID1_CHROMA ,The last write DMA transaction has completed for channel hq_vid1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_HQ_VID2_LUMA ,The last write DMA transaction has completed for channel hq_vid2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_HQ_VID2_CHROMA ,The last write DMA transaction has completed for channel hq_vid2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_HQ_VID3_LUMA ,The last write DMA transaction has completed for channel hq_vid3_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_HQ_VID3_CHROMA ,The last write DMA transaction has completed for channel hq_vid3_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_HQ_MV ,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client dei_hq_mv_in will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_HQ_MV_OUT ,The last write DMA transaction has completed for channel hq_mv_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_hq_mv_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_HQ_SCALER ,The last write DMA transaction has completed for channel hq_scaler. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_SCALER_LUMA ,The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SCALER_CHROMA ,The last write DMA transaction has completed for channel scaler_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_STAT_SCALER_OUT ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value" "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_GRPX1 ,The last read DMA transaction has occurred for channel grpx1 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx1_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_GRPX2 ,The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx2_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX3 ,The last read DMA transaction has occurred for channel grpx3 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx3_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x44++0x3 line.long 0x0 "VIP_INT0_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_HQ_VID1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_HQ_VID1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_HQ_VID2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_HQ_VID2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_HQ_VID3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_HQ_VID3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_HQ_MV ,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_HQ_MV_OUT ,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_HQ_SCALER ,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_SCALER_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SCALER_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_MASK_SCALER_OUT ,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_GRPX1 ,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_GRPX2 ,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX3 ,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x48++0x3 line.long 0x0 "VIP_INT0_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x4C++0x3 line.long 0x0 "VIP_INT0_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_PORTA_SRC0 ,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_PORTA_SRC1 ,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_PORTA_SRC2 ,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_PORTA_SRC3 ,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_PORTA_SRC4 ,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_PORTA_SRC5 ,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_PORTA_SRC6 ,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_PORTA_SRC7 ,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_PORTA_SRC8 ,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_PORTA_SRC9 ,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_PORTA_SRC10 ,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_PORTA_SRC11 ,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_PORTA_SRC12 ,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_PORTA_SRC13 ,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_PORTA_SRC14 ,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_PORTA_SRC15 ,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_PORTB_SRC0 ,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_PORTB_SRC1 ,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_PORTB_SRC2 ,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_PORTB_SRC3 ,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_PORTB_SRC4 ,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_PORTB_SRC5 ,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_PORTB_SRC6 ,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_PORTB_SRC7 ,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_PORTB_SRC8 ,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_PORTB_SRC9 ,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x50++0x3 line.long 0x0 "VIP_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x54++0x3 line.long 0x0 "VIP_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_PORTB_SRC10 ,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_PORTB_SRC11 ,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_PORTB_SRC12 ,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_PORTB_SRC13 ,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_PORTB_SRC14 ,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_PORTB_SRC15 ,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_ANCA_SRC0 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_ANCA_SRC1 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_ANCA_SRC2 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_ANCA_SRC3 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_ANCA_SRC4 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_ANCA_SRC5 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_ANCA_SRC6 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_ANCA_SRC7 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_ANCA_SRC8 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_ANCA_SRC9 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_ANCA_SRC10 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_ANCA_SRC11 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_ANCA_SRC12 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_ANCA_SRC13 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_ANCA_SRC14 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_ANCA_SRC15 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_ANCB_SRC0 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_ANCB_SRC1 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_ANCB_SRC2 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_ANCB_SRC3 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_ANCB_SRC4 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_ANCB_SRC5 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_ANCB_SRC6 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_ANCB_SRC7 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_ANCB_SRC8 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_ANCB_SRC9 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x58++0x3 line.long 0x0 "VIP_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_PORTA_LUMA ,The last write DMA transaction has completed for channel vip1_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip1_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_PORTB_LUMA ,The last write DMA transaction has completed for channel vip1_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip1_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_PORTA_RGB ,The last write DMA transaction has completed for channel vip1_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_PORTB_RGB ,The last write DMA transaction has completed for channel vip1_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x5C++0x3 line.long 0x0 "VIP_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_ANCB_SRC10 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_ANCB_SRC11 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_ANCB_SRC12 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_ANCB_SRC13 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_ANCB_SRC14 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_ANCB_SRC15 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_PORTA_RGB ,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_PORTB_RGB ,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_PORTA_SRC0 ,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_PORTA_SRC1 ,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_PORTA_SRC2 ,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_PORTA_SRC3 ,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_PORTA_SRC4 ,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_PORTA_SRC5 ,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_PORTA_SRC6 ,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_PORTA_SRC7 ,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_PORTA_SRC8 ,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_PORTA_SRC9 ,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_PORTA_SRC10 ,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_PORTA_SRC11 ,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_PORTA_SRC12 ,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_PORTA_SRC13 ,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_PORTA_SRC14 ,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_PORTA_SRC15 ,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_PORTB_SRC0 ,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_PORTB_SRC1 ,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_PORTB_SRC2 ,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_PORTB_SRC3 ,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x60++0x3 line.long 0x0 "VIP_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x64++0x3 line.long 0x0 "VIP_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_PORTB_SRC4 ,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_PORTB_SRC5 ,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_PORTB_SRC6 ,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_PORTB_SRC7 ,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_PORTB_SRC8 ,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_PORTB_SRC9 ,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_PORTB_SRC10 ,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_PORTB_SRC11 ,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_PORTB_SRC12 ,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_PORTB_SRC13 ,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_PORTB_SRC14 ,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_PORTB_SRC15 ,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_ANCA_SRC0 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_ANCA_SRC1 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_ANCA_SRC2 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_ANCA_SRC3 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_ANCA_SRC4 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_ANCA_SRC5 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_ANCA_SRC6 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_ANCA_SRC7 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_ANCA_SRC8 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_ANCA_SRC9 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_ANCA_SRC10 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_ANCA_SRC11 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_ANCA_SRC12 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_ANCA_SRC13 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_ANCA_SRC14 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_ANCA_SRC15 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_ANCB_SRC0 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_ANCB_SRC1 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_ANCB_SRC2 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_ANCB_SRC3 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x68++0x3 line.long 0x0 "VIP_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_PORTA_LUMA ,The last write DMA transaction has completed for channel vip2_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip2_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_PORTB_LUMA ,The last write DMA transaction has completed for channel vip2_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip2_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_PORTA_RGB ,The last write DMA transaction has completed for channel vip2_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_PORTB_RGB ,The last write DMA transaction has completed for channel vip2_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_OTHER ,This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_NF_WRITE_LUMA ,The last write DMA transaction has completed for channel nf_write_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_NF_WRITE_CHROMA ,The last write DMA transaction has completed for channel nf_write_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_NF_LAST_LUMA ,The last write DMA transaction has completed for channel nf_last_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_NF_LAST_CHROMA ,The last write DMA transaction has completed for channel nf_last_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VBI_SD_VENC ,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client vbi_sdvenc will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_POST_COMP_WR ,The last write DMA transaction has completed for channel post_comp_wr. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client hdmi_wrbk_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_PIP_FRAME ,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client pip_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_AUX_IN ,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client comp_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_TRANSCODE1_LUMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_TRANSCODE1_CHROMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_TRANSCODE2_LUMA ,The last write DMA transaction has completed for channel transcode2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_TRANSCODE2_CHROMA ,The last write DMA transaction has completed for channel transcode2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x6C++0x3 line.long 0x0 "VIP_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_ANCB_SRC4 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_ANCB_SRC5 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_ANCB_SRC6 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_ANCB_SRC7 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_ANCB_SRC8 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_ANCB_SRC9 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_ANCB_SRC10 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_ANCB_SRC11 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_ANCB_SRC12 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_ANCB_SRC13 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_ANCB_SRC14 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_ANCB_SRC15 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_PORTA_RGB ,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_PORTB_RGB ,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_OTHER ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_NF_WRITE_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_NF_WRITE_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_NF_LAST_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_NF_LAST_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VBI_SD_VENC ,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_POST_COMP_WR ,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_PIP_FRAME ,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_AUX_IN ,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_TRANSCODE1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_TRANSCODE1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_TRANSCODE2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_TRANSCODE2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x78++0x3 line.long 0x0 "VIP_INT0_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_DEI_HQ_1_CHROMA ,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_DEI_HQ_1_LUMA ,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_DEI_HQ_2_LUMA ,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_DEI_HQ_2_CHROMA ,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_DEI_HQ_3_LUMA ,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_DEI_HQ_3_CHROMA ,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_DEI_HQ_MV_IN ,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_DEI_HQ_MV_OUT ,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_DEI_SC_OUT ,The client interface dei_sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_PIP_WRBK ,The client interface pip_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SC_IN_CHROMA ,The client interface sc_in_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_SC_IN_LUMA ,The client interface sc_in_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_STAT_SC_OUT ,The client interface sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_COMP_WRBK ,The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX1_DATA ,The client interface grpx1_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x7C++0x3 line.long 0x0 "VIP_INT0_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_DEI_HQ_1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_DEI_HQ_1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_DEI_HQ_2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_DEI_HQ_2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_DEI_HQ_3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_DEI_HQ_3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_DEI_HQ_MV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_DEI_HQ_MV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_DEI_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_PIP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SC_IN_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_SC_IN_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_MASK_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_COMP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX1_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x80++0x3 line.long 0x0 "VIP_INT0_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_GRPX2_DATA ,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_GRPX3_DATA ,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_LO_Y ,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_LO_UV ,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_UP_Y ,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_UP_UV ,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_LO_Y ,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_LO_UV ,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_UP_Y ,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_UP_UV ,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_GRPX1_ST ,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_GRPX2_ST ,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_GRPX3_ST ,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_NF_422_IN ,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_NF_420_Y_IN ,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_NF_420_UV_IN ,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_NF_420_Y_OUT ,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_NF_420_UV_OUT ,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_STAT_VBI_SDVENC ,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VPI_CTL ,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_HDMI_WRBK_OUT ,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_TRANS1_CHROMA ,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_TRANS1_LUMA ,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_TRANS2_CHROMA ,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_TRANS2_LUMA ,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_ANC_A ,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_ANC_B ,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_ANC_A ,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_ANC_B ,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x84++0x3 line.long 0x0 "VIP_INT0_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_GRPX2_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_GRPX3_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_GRPX1_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_GRPX2_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_GRPX3_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_NF_422_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_NF_420_Y_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_NF_420_UV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_NF_420_Y_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_NF_420_UV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_MASK_VBI_SDVENC ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VPI_CTL ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_HDMI_WRBK_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_TRANS1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_TRANS1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_TRANS2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_TRANS2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x88++0x3 line.long 0x0 "VIP_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_LIST0_COMPLETE ,List 0 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_LIST0_NOTIFY ,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_LIST1_COMPLETE ,List 1 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_LIST1_NOTIFY ,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_LIST2_COMPLETE ,List 2 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_LIST2_NOTIFY ,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_LIST3_COMPLETE ,List 3 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_LIST3_NOTIFY ,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_LIST4_COMPLETE ,List 4 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_LIST4_NOTIFY ,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_LIST5_COMPLETE ,List 5 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_LIST5_NOTIFY ,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_LIST6_COMPLETE ,List 6 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_LIST6_NOTIFY ,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_LIST7_COMPLETE ,List 7 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_LIST7_NOTIFY ,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_CONTROL_DESCRIPTOR_INT0 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_CONTROL_DESCRIPTOR_INT1 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_CONTROL_DESCRIPTOR_INT2 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_CONTROL_DESCRIPTOR_INT3 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_CONTROL_DESCRIPTOR_INT4 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_CONTROL_DESCRIPTOR_INT5 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_CONTROL_DESCRIPTOR_INT6 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_CONTROL_DESCRIPTOR_INT7 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_CONTROL_DESCRIPTOR_INT8 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_CONTROL_DESCRIPTOR_INT9 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_CONTROL_DESCRIPTOR_INT10 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_CONTROL_DESCRIPTOR_INT11 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_CONTROL_DESCRIPTOR_INT12 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_CONTROL_DESCRIPTOR_INT13 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_CONTROL_DESCRIPTOR_INT14 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_CONTROL_DESCRIPTOR_INT15 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x8C++0x3 line.long 0x0 "VIP_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_LIST0_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_LIST0_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_LIST1_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_LIST1_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_LIST2_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_LIST2_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_LIST3_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_LIST3_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_LIST4_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_LIST4_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_LIST5_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_LIST5_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_LIST6_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_LIST6_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_LIST7_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_LIST7_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_CONTROL_DESCRIPTOR_INT0 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_CONTROL_DESCRIPTOR_INT1 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_CONTROL_DESCRIPTOR_INT2 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_CONTROL_DESCRIPTOR_INT3 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_CONTROL_DESCRIPTOR_INT4 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_CONTROL_DESCRIPTOR_INT5 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_CONTROL_DESCRIPTOR_INT6 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_CONTROL_DESCRIPTOR_INT7 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_CONTROL_DESCRIPTOR_INT8 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_CONTROL_DESCRIPTOR_INT9 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_CONTROL_DESCRIPTOR_INT10 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_CONTROL_DESCRIPTOR_INT11 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_CONTROL_DESCRIPTOR_INT12 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_CONTROL_DESCRIPTOR_INT13 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_CONTROL_DESCRIPTOR_INT14 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_CONTROL_DESCRIPTOR_INT15 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x90++0x3 line.long 0x0 "VIP_INT1_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_HQ_VID1_LUMA ,The last write DMA transaction has completed for channel hq_vid1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_HQ_VID1_CHROMA ,The last write DMA transaction has completed for channel hq_vid1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_HQ_VID2_LUMA ,The last write DMA transaction has completed for channel hq_vid2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_HQ_VID2_CHROMA ,The last write DMA transaction has completed for channel hq_vid2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_HQ_VID3_LUMA ,The last write DMA transaction has completed for channel hq_vid3_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_HQ_VID3_CHROMA ,The last write DMA transaction has completed for channel hq_vid3_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_HQ_MV ,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client dei_hq_mv_in will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_HQ_MV_OUT ,The last write DMA transaction has completed for channel hq_mv_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_hq_mv_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_HQ_SCALER ,The last write DMA transaction has completed for channel hq_scaler. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_SCALER_LUMA ,The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SCALER_CHROMA ,The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_STAT_SCALER_OUT ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_GRPX1 ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_GRPX2 ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX3 ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x94++0x3 line.long 0x0 "VIP_INT1_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_HQ_VID1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_HQ_VID1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_HQ_VID2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_HQ_VID2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_HQ_VID3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_HQ_VID3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_HQ_MV ,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_HQ_MV_OUT ,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_HQ_SCALER ,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_SCALER_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SCALER_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_MASK_SCALER_OUT ,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_GRPX1 ,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_GRPX2 ,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX3 ,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x98++0x3 line.long 0x0 "VIP_INT1_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x9C++0x3 line.long 0x0 "VIP_INT1_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_PORTA_SRC0 ,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_PORTA_SRC1 ,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_PORTA_SRC2 ,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_PORTA_SRC3 ,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_PORTA_SRC4 ,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_PORTA_SRC5 ,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_PORTA_SRC6 ,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_PORTA_SRC7 ,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_PORTA_SRC8 ,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_PORTA_SRC9 ,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_PORTA_SRC10 ,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_PORTA_SRC11 ,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_PORTA_SRC12 ,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_PORTA_SRC13 ,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_PORTA_SRC14 ,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_PORTA_SRC15 ,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_PORTB_SRC0 ,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_PORTB_SRC1 ,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_PORTB_SRC2 ,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_PORTB_SRC3 ,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_PORTB_SRC4 ,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_PORTB_SRC5 ,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_PORTB_SRC6 ,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_PORTB_SRC7 ,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_PORTB_SRC8 ,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_PORTB_SRC9 ,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xA0++0x3 line.long 0x0 "VIP_INT1_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xA4++0x3 line.long 0x0 "VIP_INT1_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_PORTB_SRC10 ,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_PORTB_SRC11 ,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_PORTB_SRC12 ,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_PORTB_SRC13 ,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_PORTB_SRC14 ,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_PORTB_SRC15 ,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_ANCA_SRC0 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_ANCA_SRC1 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_ANCA_SRC2 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_ANCA_SRC3 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_ANCA_SRC4 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_ANCA_SRC5 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_ANCA_SRC6 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_ANCA_SRC7 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_ANCA_SRC8 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_ANCA_SRC9 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_ANCA_SRC10 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_ANCA_SRC11 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_ANCA_SRC12 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_ANCA_SRC13 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_ANCA_SRC14 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_ANCA_SRC15 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_ANCB_SRC0 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_ANCB_SRC1 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_ANCB_SRC2 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_ANCB_SRC3 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_ANCB_SRC4 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_ANCB_SRC5 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_ANCB_SRC6 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_ANCB_SRC7 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_ANCB_SRC8 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_ANCB_SRC9 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xA8++0x3 line.long 0x0 "VIP_INT1_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_PORTA_LUMA ,The last write DMA transaction has completed for channel vip1_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip1_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_PORTB_LUMA ,The last write DMA transaction has completed for channel vip1_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip1_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_PORTA_RGB ,The last write DMA transaction has completed for channel vip1_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_PORTB_RGB ,The last write DMA transaction has completed for channel vip1_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xAC++0x3 line.long 0x0 "VIP_INT1_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_ANCB_SRC10 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_ANCB_SRC11 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_ANCB_SRC12 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_ANCB_SRC13 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_ANCB_SRC14 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_ANCB_SRC15 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_PORTA_RGB ,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_PORTB_RGB ,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_PORTA_SRC0 ,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_PORTA_SRC1 ,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_PORTA_SRC2 ,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_PORTA_SRC3 ,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_PORTA_SRC4 ,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_PORTA_SRC5 ,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_PORTA_SRC6 ,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_PORTA_SRC7 ,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_PORTA_SRC8 ,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_PORTA_SRC9 ,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_PORTA_SRC10 ,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_PORTA_SRC11 ,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_PORTA_SRC12 ,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_PORTA_SRC13 ,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_PORTA_SRC14 ,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_PORTA_SRC15 ,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_PORTB_SRC0 ,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_PORTB_SRC1 ,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_PORTB_SRC2 ,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_PORTB_SRC3 ,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xB0++0x3 line.long 0x0 "VIP_INT1_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xB4++0x3 line.long 0x0 "VIP_INT1_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_PORTB_SRC4 ,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_PORTB_SRC5 ,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_PORTB_SRC6 ,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_PORTB_SRC7 ,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_PORTB_SRC8 ,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_PORTB_SRC9 ,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_PORTB_SRC10 ,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_PORTB_SRC11 ,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_PORTB_SRC12 ,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_PORTB_SRC13 ,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_PORTB_SRC14 ,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_PORTB_SRC15 ,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_ANCA_SRC0 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_ANCA_SRC1 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_ANCA_SRC2 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_ANCA_SRC3 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_ANCA_SRC4 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_ANCA_SRC5 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_ANCA_SRC6 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_ANCA_SRC7 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_ANCA_SRC8 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_ANCA_SRC9 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_ANCA_SRC10 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_ANCA_SRC11 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_ANCA_SRC12 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_ANCA_SRC13 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_ANCA_SRC14 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_ANCA_SRC15 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_ANCB_SRC0 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_ANCB_SRC1 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_ANCB_SRC2 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_ANCB_SRC3 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xB8++0x3 line.long 0x0 "VIP_INT1_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_PORTA_LUMA ,The last write DMA transaction has completed for channel vip2_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip2_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_PORTB_LUMA ,The last write DMA transaction has completed for channel vip2_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip2_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_PORTA_RGB ,The last write DMA transaction has completed for channel vip2_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_PORTB_RGB ,The last write DMA transaction has completed for channel vip2_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_OTHER ,This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_NF_WRITE_LUMA ,The last write DMA transaction has completed for channel nf_write_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_NF_WRITE_CHROMA ,The last write DMA transaction has completed for channel nf_write_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_NF_LAST_LUMA ,The last write DMA transaction has completed for channel nf_last_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_NF_LAST_CHROMA ,The last write DMA transaction has completed for channel nf_last_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VBI_SD_VENC ,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client vbi_sdvenc will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_POST_COMP_WR ,The last write DMA transaction has completed for channel post_comp_wr. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client hdmi_wrbk_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_PIP_FRAME ,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client pip_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_AUX_IN ,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client comp_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_TRANSCODE1_LUMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_TRANSCODE1_CHROMA ,The last write DMA transaction has completed for channel transcode1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_TRANSCODE2_LUMA ,The last write DMA transaction has completed for channel transcode2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_TRANSCODE2_CHROMA ,The last write DMA transaction has completed for channel transcode2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xBC++0x3 line.long 0x0 "VIP_INT1_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_ANCB_SRC4 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_ANCB_SRC5 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_ANCB_SRC6 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_ANCB_SRC7 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_ANCB_SRC8 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_ANCB_SRC9 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_ANCB_SRC10 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_ANCB_SRC11 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_ANCB_SRC12 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_ANCB_SRC13 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_ANCB_SRC14 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_ANCB_SRC15 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_PORTA_RGB ,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_PORTB_RGB ,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_OTHER ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_NF_WRITE_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_NF_WRITE_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_NF_LAST_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_NF_LAST_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VBI_SD_VENC ,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_POST_COMP_WR ,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_PIP_FRAME ,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_AUX_IN ,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_TRANSCODE1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_TRANSCODE1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_TRANSCODE2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_TRANSCODE2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xC8++0x3 line.long 0x0 "VIP_INT1_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_DEI_HQ_1_CHROMA ,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_DEI_HQ_1_LUMA ,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_DEI_HQ_2_LUMA ,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_DEI_HQ_2_CHROMA ,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_DEI_HQ_3_LUMA ,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_DEI_HQ_3_CHROMA ,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_DEI_HQ_MV_IN ,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_DEI_HQ_MV_OUT ,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_PORTA_RGB ,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_PORTB_RGB ,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_NF_READ ,The interrupt for Noise Filter Input Data 422 Interleaved should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_NF_WRITE_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_NF_WRITE_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_NF_LAST_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_NF_LAST_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VBI_SD_VENC ,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_POST_COMP_WR ,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_PIP_FRAME ,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_AUX_IN ,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_TRANSCODE1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_TRANSCODE1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_TRANSCODE2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_TRANSCODE2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xCC++0x3 line.long 0x0 "VIP_INT1_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_DEI_HQ_1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_DEI_HQ_1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_DEI_HQ_2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_DEI_HQ_2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_DEI_HQ_3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_DEI_HQ_3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_DEI_HQ_MV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_DEI_HQ_MV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_DEI_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_PIP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SC_IN_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_SC_IN_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_MASK_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_COMP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX1_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xD0++0x3 line.long 0x0 "VIP_INT1_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_GRPX2_DATA ,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_GRPX3_DATA ,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_LO_Y ,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_LO_UV ,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_UP_Y ,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_UP_UV ,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_LO_Y ,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_LO_UV ,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_UP_Y ,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_UP_UV ,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_GRPX1_ST ,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_GRPX2_ST ,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_GRPX3_ST ,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_NF_422_IN ,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_NF_420_Y_IN ,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_NF_420_UV_IN ,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_NF_420_Y_OUT ,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_NF_420_UV_OUT ,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_STAT_VBI_SDVENC ,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VPI_CTL ,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_HDMI_WRBK_OUT ,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_TRANS1_CHROMA ,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_TRANS1_LUMA ,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_TRANS2_CHROMA ,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_TRANS2_LUMA ,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_ANC_A ,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_ANC_B ,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_ANC_A ,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_ANC_B ,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0xD4++0x3 line.long 0x0 "VIP_INT1_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_GRPX2_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_GRPX3_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_GRPX1_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_GRPX2_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_GRPX3_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_NF_422_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_NF_420_Y_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_NF_420_UV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_NF_420_Y_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_NF_420_UV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_MASK_VBI_SDVENC ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VPI_CTL ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_HDMI_WRBK_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_TRANS1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_TRANS1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_TRANS2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_TRANS2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0xD8++0x3 line.long 0x0 "VIP_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_LIST0_COMPLETE ,List 0 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_LIST0_NOTIFY ,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_LIST1_COMPLETE ,List 1 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_LIST1_NOTIFY ,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_LIST2_COMPLETE ,List 2 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_LIST2_NOTIFY ,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_LIST3_COMPLETE ,List 3 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_LIST3_NOTIFY ,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_LIST4_COMPLETE ,List 4 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_LIST4_NOTIFY ,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_LIST5_COMPLETE ,List 5 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_LIST5_NOTIFY ,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_LIST6_COMPLETE ,List 6 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_LIST6_NOTIFY ,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_LIST7_COMPLETE ,List 7 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_LIST7_NOTIFY ,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_CONTROL_DESCRIPTOR_INT0 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_CONTROL_DESCRIPTOR_INT1 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_CONTROL_DESCRIPTOR_INT2 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_CONTROL_DESCRIPTOR_INT3 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_CONTROL_DESCRIPTOR_INT4 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_CONTROL_DESCRIPTOR_INT5 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_CONTROL_DESCRIPTOR_INT6 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_CONTROL_DESCRIPTOR_INT7 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_CONTROL_DESCRIPTOR_INT8 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_CONTROL_DESCRIPTOR_INT9 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_CONTROL_DESCRIPTOR_INT10 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_CONTROL_DESCRIPTOR_INT11 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_CONTROL_DESCRIPTOR_INT12 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_CONTROL_DESCRIPTOR_INT13 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_CONTROL_DESCRIPTOR_INT14 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_CONTROL_DESCRIPTOR_INT15 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xDC++0x3 line.long 0x0 "VIP_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_LIST0_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_LIST0_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_LIST1_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_LIST1_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_LIST2_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_LIST2_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_LIST3_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_LIST3_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_LIST4_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_LIST4_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_LIST5_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_LIST5_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_LIST6_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_LIST6_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_LIST7_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_LIST7_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_CONTROL_DESCRIPTOR_INT0 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_CONTROL_DESCRIPTOR_INT1 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_CONTROL_DESCRIPTOR_INT2 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_CONTROL_DESCRIPTOR_INT3 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_CONTROL_DESCRIPTOR_INT4 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_CONTROL_DESCRIPTOR_INT5 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_CONTROL_DESCRIPTOR_INT6 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_CONTROL_DESCRIPTOR_INT7 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_CONTROL_DESCRIPTOR_INT8 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_CONTROL_DESCRIPTOR_INT9 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_CONTROL_DESCRIPTOR_INT10 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_CONTROL_DESCRIPTOR_INT11 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_CONTROL_DESCRIPTOR_INT12 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_CONTROL_DESCRIPTOR_INT13 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_CONTROL_DESCRIPTOR_INT14 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_CONTROL_DESCRIPTOR_INT15 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x200++0x3 line.long 0x0 "VIP_PERF_MON0,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: vip2_anc_b 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: vip2_anc_b 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x204++0x3 line.long 0x0 "VIP_PERF_MON1,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x208++0x3 line.long 0x0 "VIP_PERF_MON2,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x20C++0x3 line.long 0x0 "VIP_PERF_MON3,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x210++0x3 line.long 0x0 "VIP_PERF_MON4,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x214++0x3 line.long 0x0 "VIP_PERF_MON5,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x218++0x3 line.long 0x0 "VIP_PERF_MON6,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x21C++0x3 line.long 0x0 "VIP_PERF_MON7,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x220++0x3 line.long 0x0 "VIP_PERF_MON8,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x224++0x3 line.long 0x0 "VIP_PERF_MON9,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x228++0x3 line.long 0x0 "VIP_PERF_MON10,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x22C++0x3 line.long 0x0 "VIP_PERF_MON11,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x230++0x3 line.long 0x0 "VIP_PERF_MON12,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x234++0x3 line.long 0x0 "VIP_PERF_MON13,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x238++0x3 line.long 0x0 "VIP_PERF_MON14,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x23C++0x3 line.long 0x0 "VIP_PERF_MON15,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x240++0x3 line.long 0x0 "VIP_PERF_MON16,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x244++0x3 line.long 0x0 "VIP_PERF_MON17,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x248++0x3 line.long 0x0 "VIP_PERF_MON18,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x24C++0x3 line.long 0x0 "VIP_PERF_MON19,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x250++0x3 line.long 0x0 "VIP_PERF_MON20,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x254++0x3 line.long 0x0 "VIP_PERF_MON21,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x258++0x3 line.long 0x0 "VIP_PERF_MON22,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x25C++0x3 line.long 0x0 "VIP_PERF_MON23,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x260++0x3 line.long 0x0 "VIP_PERF_MON24,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x264++0x3 line.long 0x0 "VIP_PERF_MON25,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x268++0x3 line.long 0x0 "VIP_PERF_MON26,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x26C++0x3 line.long 0x0 "VIP_PERF_MON27,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x270++0x3 line.long 0x0 "VIP_PERF_MON28,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x274++0x3 line.long 0x0 "VIP_PERF_MON29,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x278++0x3 line.long 0x0 "VIP_PERF_MON30,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x27C++0x3 line.long 0x0 "VIP_PERF_MON31,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x280++0x3 line.long 0x0 "VIP_PERF_MON32,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3: vip1_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3: vip1_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x284++0x3 line.long 0x0 "VIP_PERF_MON33,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: vip1_lo_y 3: vip1_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: vip1_lo_y 3: vip1_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x288++0x3 line.long 0x0 "VIP_PERF_MON34,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_lo_y 1: 2: vip1_lo_uv 3: vip1_up_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_lo_y 1: 2: vip1_lo_uv 3: vip1_up_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x28C++0x3 line.long 0x0 "VIP_PERF_MON35,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_lo_uv 1: vip1_lo_y 2: vip1_up_y 3: vip1_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_lo_uv 1: vip1_lo_y 2: vip1_up_y 3: vip1_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x290++0x3 line.long 0x0 "VIP_PERF_MON36,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_up_y 1: vip1_lo_uv 2: vip1_up_uv 3: vip2_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_up_y 1: vip1_lo_uv 2: vip1_up_uv 3: vip2_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x294++0x3 line.long 0x0 "VIP_PERF_MON37,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_up_uv 1: vip1_up_y 2: vip2_lo_y 3: vip2_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_up_uv 1: vip1_up_y 2: vip2_lo_y 3: vip2_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x298++0x3 line.long 0x0 "VIP_PERF_MON38,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_lo_y 1: vip1_up_uv 2: vip2_lo_uv 3: vip2_up_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_lo_y 1: vip1_up_uv 2: vip2_lo_uv 3: vip2_up_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x29C++0x3 line.long 0x0 "VIP_PERF_MON39,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_lo_uv 1: vip2_lo_y 2: vip2_up_y 3: vip2_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_lo_uv 1: vip2_lo_y 2: vip2_up_y 3: vip2_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A0++0x3 line.long 0x0 "VIP_PERF_MON40,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_up_y 1: vip2_lo_uv 2: vip2_up_uv 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_up_y 1: vip2_lo_uv 2: vip2_up_uv 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A4++0x3 line.long 0x0 "VIP_PERF_MON41,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_up_uv 1: vip2_up_y 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_up_uv 1: vip2_up_y 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A8++0x3 line.long 0x0 "VIP_PERF_MON42,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: vip2_up_uv 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: vip2_up_uv 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2AC++0x3 line.long 0x0 "VIP_PERF_MON43,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B0++0x3 line.long 0x0 "VIP_PERF_MON44,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B4++0x3 line.long 0x0 "VIP_PERF_MON45,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B8++0x3 line.long 0x0 "VIP_PERF_MON46,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2BC++0x3 line.long 0x0 "VIP_PERF_MON47,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C0++0x3 line.long 0x0 "VIP_PERF_MON48,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C4++0x3 line.long 0x0 "VIP_PERF_MON49,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C8++0x3 line.long 0x0 "VIP_PERF_MON50,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3: vpi_ctl" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3: vpi_ctl" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2CC++0x3 line.long 0x0 "VIP_PERF_MON51,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: vpi_ctl 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: vpi_ctl 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2D0++0x3 line.long 0x0 "VIP_PERF_MON52,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vpi_ctl 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vpi_ctl 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2D4++0x3 line.long 0x0 "VIP_PERF_MON53,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: vpi_ctl 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: vpi_ctl 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2D8++0x3 line.long 0x0 "VIP_PERF_MON54,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2DC++0x3 line.long 0x0 "VIP_PERF_MON55,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2E0++0x3 line.long 0x0 "VIP_PERF_MON56,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3: vip1_anc_a" "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ," "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3: vip1_anc_a" "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ," "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2E4++0x3 line.long 0x0 "VIP_PERF_MON57,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: vip1_anc_a 3: vip1_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: vip1_anc_a 3: vip1_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2E8++0x3 line.long 0x0 "VIP_PERF_MON58,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_anc_a 1: 2: vip1_anc_b 3: vip2_anc_a" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_anc_a 1: 2: vip1_anc_b 3: vip2_anc_a" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2EC++0x3 line.long 0x0 "VIP_PERF_MON59,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_anc_b 1: vip1_anc_a 2: vip2_anc_a 3: vip2_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_anc_b 1: vip1_anc_a 2: vip2_anc_a 3: vip2_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2F0++0x3 line.long 0x0 "VIP_PERF_MON60,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_anc_a 1: vip1_anc_b 2: vip2_anc_b 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_anc_a 1: vip1_anc_b 2: vip2_anc_b 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2F4++0x3 line.long 0x0 "VIP_PERF_MON61,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_anc_b 1: vip2_anc_a 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_anc_b 1: vip2_anc_a 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x388++0x3 line.long 0x0 "VIP0_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x38C++0x3 line.long 0x0 "VIP0_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x390++0x3 line.long 0x0 "VIP0_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x394++0x3 line.long 0x0 "VIP0_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x398++0x3 line.long 0x0 "VIP1_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x39C++0x3 line.long 0x0 "VIP1_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3A0++0x3 line.long 0x0 "VIP1_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3A4++0x3 line.long 0x0 "VIP1_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3D0++0x3 line.long 0x0 "VPI_CTL_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3E8++0x3 line.long 0x0 "VIP0_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3EC++0x3 line.long 0x0 "VIP0_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3F0++0x3 line.long 0x0 "VIP1_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3F4++0x3 line.long 0x0 "VIP1_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." width 0x0B tree.end tree "VIP2_VPDMA" base ad:0x4899D000 width 31. group.byte 0x0++0x3 line.long 0x0 "VIP_PID,PID VIP VPDMA register" hexmask.long 0x0 0.--31. 1. " PID ,PID of VPDMA module" group.byte 0x4++0x3 line.long 0x0 "VIP_LIST_ADDR,The location of a new list to begin processing." hexmask.long 0x0 0.--31. 1. " VIP_LIST_ADDR ,Location of a new list of descriptors. This register must be written with the VPDMA Configuration Location after reset." group.byte 0x8++0x3 line.long 0x0 "VIP_LIST_ATTR,The attributes of a new list. This register should always be written after." hexmask.long.word 0x0 0.--15. 1. " LIST_SIZE ,Number of 128 bit word in the new list of descriptors. Writes to this register will activate the list in the list stack of the list manager and begin transfer of the list into VPDMA. This size can not be 0." bitfld.long 0x0 16.--18. " LIST_TYPE ,The type of list that has been generated.\\n0: Normal List\\n1: Self-Modifying List\\n2: List Doorbell\\nOthers Reserved for future use" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RDY ,This bit is low when a new list cannot be written to theVIP_LIST_ADDR register. The reasons this bit would be low are at initial startup if the LIST_MANAGER State Machine image has not completed loading. It also would be low if the last write to the VIP_LIST_ATTR attempted to start a list that is currently active. When this bit is low any writes to the list address register will cause access to not be accepted until this bit has set by the previous list having completed." "0,1" bitfld.long 0x0 20. " STOP ,This bit is written with the LIST_NUMBER field to stop a self-modifying list. When this bit is written a one the list specified by the LIST_NUMBER is sent a stop signal and will finish the current frame of transfers and then free the list resources." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " LIST_NUM ,The list number that should be assigned to the list located atVIP_LIST_ADDR. If the list is still active this will block all future list writes until the list is available." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xC++0x3 line.long 0x0 "VIP_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list." bitfld.long 0x0 0. " SYNC_LISTS0 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it." "0,1" bitfld.long 0x0 1. " SYNC_LISTS1 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it." "0,1" textline " " bitfld.long 0x0 2. " SYNC_LISTS2 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it." "0,1" bitfld.long 0x0 3. " SYNC_LISTS3 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it." "0,1" textline " " bitfld.long 0x0 4. " SYNC_LISTS4 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it." "0,1" bitfld.long 0x0 5. " SYNC_LISTS5 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it." "0,1" textline " " bitfld.long 0x0 6. " SYNC_LISTS6 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it." "0,1" bitfld.long 0x0 7. " SYNC_LISTS7 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " LIST0_BUSY ,The list 0 is currently running. Any attempt to load a new list to list 0 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 17. " LIST1_BUSY ,The list 1 is currently running. Any attempt to load a new list to list 1 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 18. " LIST2_BUSY ,The list 2 is currently running. Any attempt to load a new list to list 2 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 19. " LIST3_BUSY ,The list 3 is currently running. Any attempt to load a new list to list 3 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 20. " LIST4_BUSY ,The list 4 is currently running. Any attempt to load a new list to list 4 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 21. " LIST5_BUSY ,The list 5 is currently running. Any attempt to load a new list to list 5 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 22. " LIST6_BUSY ,The list 6 is currently running. Any attempt to load a new list to list 6 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 23. " LIST7_BUSY ,The list 7 is currently running. Any attempt to load a new list to list 7 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "VIP_BG_RGB,The registers used to set the background color for RGB" hexmask.long.byte 0x0 0.--7. 1. " BLEND ,The blend value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 8.--15. 1. " BLUE ,The blue value to give on an RGB data port for a blank pixel when using virtual video buffering" textline " " hexmask.long.byte 0x0 16.--23. 1. " GREEN ,The green value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 24.--31. 1. " RED ,The red value to give on an RGB data port for a blank pixel when using virtual video buffering" group.byte 0x1C++0x3 line.long 0x0 "VIP_BG_YUV,The registers used to set the background color for YUV" hexmask.long.byte 0x0 0.--7. 1. " CB ,The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 8.--15. 1. " CR ,The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering" textline " " hexmask.long.byte 0x0 16.--23. 1. " Y ,The Y value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "VIP_VPDMA_SETUP,Configures global parameters that are shared by all clients." bitfld.long 0x0 0. " SEC_BASE_CH ,Use Secondary Channels for Mosaic mode" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 1 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 1 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x38++0x3 line.long 0x0 "VIP_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 2 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 2 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x3C++0x3 line.long 0x0 "VIP_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 3 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 3 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x40++0x3 line.long 0x0 "VIP_INT0_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_HQ_VID1_LUMA ,The last write DMA transaction has completed for channel hq_vid1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_HQ_VID1_CHROMA ,The last write DMA transaction has completed for channel hq_vid1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_HQ_VID2_LUMA ,The last write DMA transaction has completed for channel hq_vid2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_HQ_VID2_CHROMA ,The last write DMA transaction has completed for channel hq_vid2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_HQ_VID3_LUMA ,The last write DMA transaction has completed for channel hq_vid3_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_HQ_VID3_CHROMA ,The last write DMA transaction has completed for channel hq_vid3_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_HQ_MV ,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client dei_hq_mv_in will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_HQ_MV_OUT ,The last write DMA transaction has completed for channel hq_mv_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_hq_mv_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_HQ_SCALER ,The last write DMA transaction has completed for channel hq_scaler. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_SCALER_LUMA ,The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SCALER_CHROMA ,The last write DMA transaction has completed for channel scaler_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_STAT_SCALER_OUT ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value" "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_GRPX1 ,The last read DMA transaction has occurred for channel grpx1 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx1_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_GRPX2 ,The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx2_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX3 ,The last read DMA transaction has occurred for channel grpx3 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx3_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x44++0x3 line.long 0x0 "VIP_INT0_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_HQ_VID1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_HQ_VID1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_HQ_VID2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_HQ_VID2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_HQ_VID3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_HQ_VID3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_HQ_MV ,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_HQ_MV_OUT ,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_HQ_SCALER ,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_SCALER_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SCALER_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_MASK_SCALER_OUT ,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_GRPX1 ,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_GRPX2 ,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX3 ,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x48++0x3 line.long 0x0 "VIP_INT0_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x4C++0x3 line.long 0x0 "VIP_INT0_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_PORTA_SRC0 ,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_PORTA_SRC1 ,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_PORTA_SRC2 ,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_PORTA_SRC3 ,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_PORTA_SRC4 ,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_PORTA_SRC5 ,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_PORTA_SRC6 ,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_PORTA_SRC7 ,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_PORTA_SRC8 ,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_PORTA_SRC9 ,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_PORTA_SRC10 ,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_PORTA_SRC11 ,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_PORTA_SRC12 ,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_PORTA_SRC13 ,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_PORTA_SRC14 ,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_PORTA_SRC15 ,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_PORTB_SRC0 ,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_PORTB_SRC1 ,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_PORTB_SRC2 ,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_PORTB_SRC3 ,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_PORTB_SRC4 ,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_PORTB_SRC5 ,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_PORTB_SRC6 ,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_PORTB_SRC7 ,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_PORTB_SRC8 ,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_PORTB_SRC9 ,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x50++0x3 line.long 0x0 "VIP_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x54++0x3 line.long 0x0 "VIP_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_PORTB_SRC10 ,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_PORTB_SRC11 ,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_PORTB_SRC12 ,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_PORTB_SRC13 ,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_PORTB_SRC14 ,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_PORTB_SRC15 ,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_ANCA_SRC0 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_ANCA_SRC1 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_ANCA_SRC2 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_ANCA_SRC3 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_ANCA_SRC4 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_ANCA_SRC5 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_ANCA_SRC6 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_ANCA_SRC7 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_ANCA_SRC8 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_ANCA_SRC9 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_ANCA_SRC10 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_ANCA_SRC11 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_ANCA_SRC12 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_ANCA_SRC13 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_ANCA_SRC14 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_ANCA_SRC15 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_ANCB_SRC0 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_ANCB_SRC1 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_ANCB_SRC2 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_ANCB_SRC3 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_ANCB_SRC4 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_ANCB_SRC5 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_ANCB_SRC6 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_ANCB_SRC7 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_ANCB_SRC8 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_ANCB_SRC9 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x58++0x3 line.long 0x0 "VIP_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_PORTA_LUMA ,The last write DMA transaction has completed for channel vip1_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip1_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_PORTB_LUMA ,The last write DMA transaction has completed for channel vip1_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip1_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_PORTA_RGB ,The last write DMA transaction has completed for channel vip1_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_PORTB_RGB ,The last write DMA transaction has completed for channel vip1_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x5C++0x3 line.long 0x0 "VIP_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_ANCB_SRC10 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_ANCB_SRC11 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_ANCB_SRC12 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_ANCB_SRC13 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_ANCB_SRC14 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_ANCB_SRC15 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_PORTA_RGB ,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_PORTB_RGB ,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_PORTA_SRC0 ,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_PORTA_SRC1 ,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_PORTA_SRC2 ,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_PORTA_SRC3 ,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_PORTA_SRC4 ,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_PORTA_SRC5 ,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_PORTA_SRC6 ,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_PORTA_SRC7 ,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_PORTA_SRC8 ,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_PORTA_SRC9 ,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_PORTA_SRC10 ,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_PORTA_SRC11 ,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_PORTA_SRC12 ,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_PORTA_SRC13 ,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_PORTA_SRC14 ,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_PORTA_SRC15 ,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_PORTB_SRC0 ,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_PORTB_SRC1 ,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_PORTB_SRC2 ,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_PORTB_SRC3 ,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x60++0x3 line.long 0x0 "VIP_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x64++0x3 line.long 0x0 "VIP_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_PORTB_SRC4 ,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_PORTB_SRC5 ,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_PORTB_SRC6 ,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_PORTB_SRC7 ,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_PORTB_SRC8 ,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_PORTB_SRC9 ,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_PORTB_SRC10 ,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_PORTB_SRC11 ,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_PORTB_SRC12 ,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_PORTB_SRC13 ,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_PORTB_SRC14 ,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_PORTB_SRC15 ,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_ANCA_SRC0 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_ANCA_SRC1 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_ANCA_SRC2 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_ANCA_SRC3 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_ANCA_SRC4 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_ANCA_SRC5 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_ANCA_SRC6 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_ANCA_SRC7 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_ANCA_SRC8 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_ANCA_SRC9 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_ANCA_SRC10 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_ANCA_SRC11 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_ANCA_SRC12 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_ANCA_SRC13 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_ANCA_SRC14 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_ANCA_SRC15 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_ANCB_SRC0 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_ANCB_SRC1 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_ANCB_SRC2 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_ANCB_SRC3 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x68++0x3 line.long 0x0 "VIP_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_PORTA_LUMA ,The last write DMA transaction has completed for channel vip2_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip2_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_PORTB_LUMA ,The last write DMA transaction has completed for channel vip2_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip2_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_PORTA_RGB ,The last write DMA transaction has completed for channel vip2_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_PORTB_RGB ,The last write DMA transaction has completed for channel vip2_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_OTHER ,This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_NF_WRITE_LUMA ,The last write DMA transaction has completed for channel nf_write_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_NF_WRITE_CHROMA ,The last write DMA transaction has completed for channel nf_write_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_NF_LAST_LUMA ,The last write DMA transaction has completed for channel nf_last_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_NF_LAST_CHROMA ,The last write DMA transaction has completed for channel nf_last_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VBI_SD_VENC ,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client vbi_sdvenc will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_POST_COMP_WR ,The last write DMA transaction has completed for channel post_comp_wr. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client hdmi_wrbk_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_PIP_FRAME ,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client pip_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_AUX_IN ,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client comp_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_TRANSCODE1_LUMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_TRANSCODE1_CHROMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_TRANSCODE2_LUMA ,The last write DMA transaction has completed for channel transcode2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_TRANSCODE2_CHROMA ,The last write DMA transaction has completed for channel transcode2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x6C++0x3 line.long 0x0 "VIP_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_ANCB_SRC4 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_ANCB_SRC5 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_ANCB_SRC6 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_ANCB_SRC7 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_ANCB_SRC8 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_ANCB_SRC9 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_ANCB_SRC10 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_ANCB_SRC11 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_ANCB_SRC12 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_ANCB_SRC13 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_ANCB_SRC14 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_ANCB_SRC15 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_PORTA_RGB ,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_PORTB_RGB ,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_OTHER ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_NF_WRITE_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_NF_WRITE_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_NF_LAST_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_NF_LAST_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VBI_SD_VENC ,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_POST_COMP_WR ,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_PIP_FRAME ,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_AUX_IN ,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_TRANSCODE1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_TRANSCODE1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_TRANSCODE2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_TRANSCODE2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x78++0x3 line.long 0x0 "VIP_INT0_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_DEI_HQ_1_CHROMA ,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_DEI_HQ_1_LUMA ,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_DEI_HQ_2_LUMA ,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_DEI_HQ_2_CHROMA ,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_DEI_HQ_3_LUMA ,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_DEI_HQ_3_CHROMA ,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_DEI_HQ_MV_IN ,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_DEI_HQ_MV_OUT ,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_DEI_SC_OUT ,The client interface dei_sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_PIP_WRBK ,The client interface pip_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SC_IN_CHROMA ,The client interface sc_in_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_SC_IN_LUMA ,The client interface sc_in_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_STAT_SC_OUT ,The client interface sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_COMP_WRBK ,The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX1_DATA ,The client interface grpx1_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x7C++0x3 line.long 0x0 "VIP_INT0_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_DEI_HQ_1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_DEI_HQ_1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_DEI_HQ_2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_DEI_HQ_2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_DEI_HQ_3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_DEI_HQ_3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_DEI_HQ_MV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_DEI_HQ_MV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_DEI_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_PIP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SC_IN_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_SC_IN_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_MASK_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_COMP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX1_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x80++0x3 line.long 0x0 "VIP_INT0_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_GRPX2_DATA ,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_GRPX3_DATA ,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_LO_Y ,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_LO_UV ,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_UP_Y ,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_UP_UV ,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_LO_Y ,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_LO_UV ,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_UP_Y ,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_UP_UV ,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_GRPX1_ST ,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_GRPX2_ST ,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_GRPX3_ST ,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_NF_422_IN ,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_NF_420_Y_IN ,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_NF_420_UV_IN ,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_NF_420_Y_OUT ,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_NF_420_UV_OUT ,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_STAT_VBI_SDVENC ,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VPI_CTL ,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_HDMI_WRBK_OUT ,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_TRANS1_CHROMA ,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_TRANS1_LUMA ,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_TRANS2_CHROMA ,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_TRANS2_LUMA ,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_ANC_A ,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_ANC_B ,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_ANC_A ,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_ANC_B ,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x84++0x3 line.long 0x0 "VIP_INT0_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_GRPX2_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_GRPX3_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_GRPX1_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_GRPX2_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_GRPX3_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_NF_422_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_NF_420_Y_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_NF_420_UV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_NF_420_Y_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_NF_420_UV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_MASK_VBI_SDVENC ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VPI_CTL ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_HDMI_WRBK_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_TRANS1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_TRANS1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_TRANS2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_TRANS2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x88++0x3 line.long 0x0 "VIP_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_LIST0_COMPLETE ,List 0 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_LIST0_NOTIFY ,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_LIST1_COMPLETE ,List 1 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_LIST1_NOTIFY ,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_LIST2_COMPLETE ,List 2 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_LIST2_NOTIFY ,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_LIST3_COMPLETE ,List 3 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_LIST3_NOTIFY ,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_LIST4_COMPLETE ,List 4 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_LIST4_NOTIFY ,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_LIST5_COMPLETE ,List 5 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_LIST5_NOTIFY ,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_LIST6_COMPLETE ,List 6 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_LIST6_NOTIFY ,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_LIST7_COMPLETE ,List 7 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_LIST7_NOTIFY ,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_CONTROL_DESCRIPTOR_INT0 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_CONTROL_DESCRIPTOR_INT1 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_CONTROL_DESCRIPTOR_INT2 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_CONTROL_DESCRIPTOR_INT3 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_CONTROL_DESCRIPTOR_INT4 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_CONTROL_DESCRIPTOR_INT5 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_CONTROL_DESCRIPTOR_INT6 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_CONTROL_DESCRIPTOR_INT7 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_CONTROL_DESCRIPTOR_INT8 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_CONTROL_DESCRIPTOR_INT9 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_CONTROL_DESCRIPTOR_INT10 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_CONTROL_DESCRIPTOR_INT11 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_CONTROL_DESCRIPTOR_INT12 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_CONTROL_DESCRIPTOR_INT13 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_CONTROL_DESCRIPTOR_INT14 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_CONTROL_DESCRIPTOR_INT15 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x8C++0x3 line.long 0x0 "VIP_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_LIST0_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_LIST0_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_LIST1_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_LIST1_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_LIST2_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_LIST2_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_LIST3_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_LIST3_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_LIST4_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_LIST4_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_LIST5_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_LIST5_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_LIST6_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_LIST6_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_LIST7_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_LIST7_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_CONTROL_DESCRIPTOR_INT0 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_CONTROL_DESCRIPTOR_INT1 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_CONTROL_DESCRIPTOR_INT2 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_CONTROL_DESCRIPTOR_INT3 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_CONTROL_DESCRIPTOR_INT4 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_CONTROL_DESCRIPTOR_INT5 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_CONTROL_DESCRIPTOR_INT6 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_CONTROL_DESCRIPTOR_INT7 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_CONTROL_DESCRIPTOR_INT8 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_CONTROL_DESCRIPTOR_INT9 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_CONTROL_DESCRIPTOR_INT10 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_CONTROL_DESCRIPTOR_INT11 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_CONTROL_DESCRIPTOR_INT12 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_CONTROL_DESCRIPTOR_INT13 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_CONTROL_DESCRIPTOR_INT14 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_CONTROL_DESCRIPTOR_INT15 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x90++0x3 line.long 0x0 "VIP_INT1_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_HQ_VID1_LUMA ,The last write DMA transaction has completed for channel hq_vid1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_HQ_VID1_CHROMA ,The last write DMA transaction has completed for channel hq_vid1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_HQ_VID2_LUMA ,The last write DMA transaction has completed for channel hq_vid2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_HQ_VID2_CHROMA ,The last write DMA transaction has completed for channel hq_vid2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_HQ_VID3_LUMA ,The last write DMA transaction has completed for channel hq_vid3_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_HQ_VID3_CHROMA ,The last write DMA transaction has completed for channel hq_vid3_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_HQ_MV ,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client dei_hq_mv_in will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_HQ_MV_OUT ,The last write DMA transaction has completed for channel hq_mv_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_hq_mv_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_HQ_SCALER ,The last write DMA transaction has completed for channel hq_scaler. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_SCALER_LUMA ,The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SCALER_CHROMA ,The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_STAT_SCALER_OUT ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_GRPX1 ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_GRPX2 ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX3 ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x94++0x3 line.long 0x0 "VIP_INT1_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_HQ_VID1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_HQ_VID1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_HQ_VID2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_HQ_VID2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_HQ_VID3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_HQ_VID3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_HQ_MV ,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_HQ_MV_OUT ,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_HQ_SCALER ,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_SCALER_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SCALER_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_MASK_SCALER_OUT ,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_GRPX1 ,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_GRPX2 ,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX3 ,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x98++0x3 line.long 0x0 "VIP_INT1_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x9C++0x3 line.long 0x0 "VIP_INT1_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_PORTA_SRC0 ,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_PORTA_SRC1 ,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_PORTA_SRC2 ,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_PORTA_SRC3 ,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_PORTA_SRC4 ,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_PORTA_SRC5 ,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_PORTA_SRC6 ,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_PORTA_SRC7 ,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_PORTA_SRC8 ,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_PORTA_SRC9 ,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_PORTA_SRC10 ,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_PORTA_SRC11 ,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_PORTA_SRC12 ,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_PORTA_SRC13 ,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_PORTA_SRC14 ,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_PORTA_SRC15 ,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_PORTB_SRC0 ,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_PORTB_SRC1 ,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_PORTB_SRC2 ,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_PORTB_SRC3 ,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_PORTB_SRC4 ,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_PORTB_SRC5 ,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_PORTB_SRC6 ,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_PORTB_SRC7 ,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_PORTB_SRC8 ,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_PORTB_SRC9 ,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xA0++0x3 line.long 0x0 "VIP_INT1_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xA4++0x3 line.long 0x0 "VIP_INT1_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_PORTB_SRC10 ,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_PORTB_SRC11 ,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_PORTB_SRC12 ,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_PORTB_SRC13 ,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_PORTB_SRC14 ,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_PORTB_SRC15 ,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_ANCA_SRC0 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_ANCA_SRC1 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_ANCA_SRC2 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_ANCA_SRC3 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_ANCA_SRC4 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_ANCA_SRC5 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_ANCA_SRC6 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_ANCA_SRC7 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_ANCA_SRC8 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_ANCA_SRC9 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_ANCA_SRC10 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_ANCA_SRC11 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_ANCA_SRC12 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_ANCA_SRC13 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_ANCA_SRC14 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_ANCA_SRC15 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_ANCB_SRC0 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_ANCB_SRC1 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_ANCB_SRC2 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_ANCB_SRC3 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_ANCB_SRC4 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_ANCB_SRC5 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_ANCB_SRC6 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_ANCB_SRC7 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_ANCB_SRC8 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_ANCB_SRC9 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xA8++0x3 line.long 0x0 "VIP_INT1_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_PORTA_LUMA ,The last write DMA transaction has completed for channel vip1_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip1_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_PORTB_LUMA ,The last write DMA transaction has completed for channel vip1_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip1_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_PORTA_RGB ,The last write DMA transaction has completed for channel vip1_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_PORTB_RGB ,The last write DMA transaction has completed for channel vip1_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xAC++0x3 line.long 0x0 "VIP_INT1_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_ANCB_SRC10 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_ANCB_SRC11 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_ANCB_SRC12 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_ANCB_SRC13 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_ANCB_SRC14 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_ANCB_SRC15 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_PORTA_RGB ,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_PORTB_RGB ,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_PORTA_SRC0 ,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_PORTA_SRC1 ,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_PORTA_SRC2 ,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_PORTA_SRC3 ,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_PORTA_SRC4 ,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_PORTA_SRC5 ,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_PORTA_SRC6 ,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_PORTA_SRC7 ,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_PORTA_SRC8 ,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_PORTA_SRC9 ,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_PORTA_SRC10 ,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_PORTA_SRC11 ,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_PORTA_SRC12 ,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_PORTA_SRC13 ,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_PORTA_SRC14 ,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_PORTA_SRC15 ,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_PORTB_SRC0 ,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_PORTB_SRC1 ,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_PORTB_SRC2 ,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_PORTB_SRC3 ,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xB0++0x3 line.long 0x0 "VIP_INT1_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xB4++0x3 line.long 0x0 "VIP_INT1_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_PORTB_SRC4 ,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_PORTB_SRC5 ,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_PORTB_SRC6 ,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_PORTB_SRC7 ,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_PORTB_SRC8 ,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_PORTB_SRC9 ,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_PORTB_SRC10 ,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_PORTB_SRC11 ,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_PORTB_SRC12 ,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_PORTB_SRC13 ,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_PORTB_SRC14 ,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_PORTB_SRC15 ,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_ANCA_SRC0 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_ANCA_SRC1 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_ANCA_SRC2 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_ANCA_SRC3 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_ANCA_SRC4 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_ANCA_SRC5 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_ANCA_SRC6 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_ANCA_SRC7 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_ANCA_SRC8 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_ANCA_SRC9 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_ANCA_SRC10 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_ANCA_SRC11 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_ANCA_SRC12 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_ANCA_SRC13 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_ANCA_SRC14 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_ANCA_SRC15 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_ANCB_SRC0 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_ANCB_SRC1 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_ANCB_SRC2 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_ANCB_SRC3 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xB8++0x3 line.long 0x0 "VIP_INT1_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_PORTA_LUMA ,The last write DMA transaction has completed for channel vip2_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip2_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_PORTB_LUMA ,The last write DMA transaction has completed for channel vip2_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip2_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_PORTA_RGB ,The last write DMA transaction has completed for channel vip2_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_PORTB_RGB ,The last write DMA transaction has completed for channel vip2_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_OTHER ,This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_NF_WRITE_LUMA ,The last write DMA transaction has completed for channel nf_write_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_NF_WRITE_CHROMA ,The last write DMA transaction has completed for channel nf_write_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_NF_LAST_LUMA ,The last write DMA transaction has completed for channel nf_last_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_NF_LAST_CHROMA ,The last write DMA transaction has completed for channel nf_last_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VBI_SD_VENC ,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client vbi_sdvenc will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_POST_COMP_WR ,The last write DMA transaction has completed for channel post_comp_wr. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client hdmi_wrbk_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_PIP_FRAME ,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client pip_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_AUX_IN ,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client comp_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_TRANSCODE1_LUMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_TRANSCODE1_CHROMA ,The last write DMA transaction has completed for channel transcode1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_TRANSCODE2_LUMA ,The last write DMA transaction has completed for channel transcode2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_TRANSCODE2_CHROMA ,The last write DMA transaction has completed for channel transcode2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xBC++0x3 line.long 0x0 "VIP_INT1_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_ANCB_SRC4 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_ANCB_SRC5 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_ANCB_SRC6 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_ANCB_SRC7 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_ANCB_SRC8 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_ANCB_SRC9 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_ANCB_SRC10 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_ANCB_SRC11 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_ANCB_SRC12 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_ANCB_SRC13 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_ANCB_SRC14 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_ANCB_SRC15 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_PORTA_RGB ,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_PORTB_RGB ,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_OTHER ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_NF_WRITE_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_NF_WRITE_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_NF_LAST_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_NF_LAST_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VBI_SD_VENC ,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_POST_COMP_WR ,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_PIP_FRAME ,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_AUX_IN ,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_TRANSCODE1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_TRANSCODE1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_TRANSCODE2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_TRANSCODE2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xC8++0x3 line.long 0x0 "VIP_INT1_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_DEI_HQ_1_CHROMA ,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_DEI_HQ_1_LUMA ,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_DEI_HQ_2_LUMA ,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_DEI_HQ_2_CHROMA ,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_DEI_HQ_3_LUMA ,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_DEI_HQ_3_CHROMA ,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_DEI_HQ_MV_IN ,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_DEI_HQ_MV_OUT ,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_PORTA_RGB ,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_PORTB_RGB ,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_NF_READ ,The interrupt for Noise Filter Input Data 422 Interleaved should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_NF_WRITE_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_NF_WRITE_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_NF_LAST_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_NF_LAST_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VBI_SD_VENC ,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_POST_COMP_WR ,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_PIP_FRAME ,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_AUX_IN ,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_TRANSCODE1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_TRANSCODE1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_TRANSCODE2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_TRANSCODE2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xCC++0x3 line.long 0x0 "VIP_INT1_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_DEI_HQ_1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_DEI_HQ_1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_DEI_HQ_2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_DEI_HQ_2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_DEI_HQ_3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_DEI_HQ_3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_DEI_HQ_MV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_DEI_HQ_MV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_DEI_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_PIP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SC_IN_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_SC_IN_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_MASK_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_COMP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX1_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xD0++0x3 line.long 0x0 "VIP_INT1_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_GRPX2_DATA ,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_GRPX3_DATA ,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_LO_Y ,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_LO_UV ,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_UP_Y ,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_UP_UV ,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_LO_Y ,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_LO_UV ,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_UP_Y ,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_UP_UV ,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_GRPX1_ST ,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_GRPX2_ST ,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_GRPX3_ST ,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_NF_422_IN ,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_NF_420_Y_IN ,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_NF_420_UV_IN ,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_NF_420_Y_OUT ,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_NF_420_UV_OUT ,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_STAT_VBI_SDVENC ,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VPI_CTL ,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_HDMI_WRBK_OUT ,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_TRANS1_CHROMA ,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_TRANS1_LUMA ,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_TRANS2_CHROMA ,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_TRANS2_LUMA ,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_ANC_A ,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_ANC_B ,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_ANC_A ,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_ANC_B ,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0xD4++0x3 line.long 0x0 "VIP_INT1_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_GRPX2_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_GRPX3_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_GRPX1_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_GRPX2_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_GRPX3_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_NF_422_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_NF_420_Y_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_NF_420_UV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_NF_420_Y_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_NF_420_UV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_MASK_VBI_SDVENC ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VPI_CTL ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_HDMI_WRBK_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_TRANS1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_TRANS1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_TRANS2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_TRANS2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0xD8++0x3 line.long 0x0 "VIP_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_LIST0_COMPLETE ,List 0 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_LIST0_NOTIFY ,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_LIST1_COMPLETE ,List 1 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_LIST1_NOTIFY ,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_LIST2_COMPLETE ,List 2 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_LIST2_NOTIFY ,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_LIST3_COMPLETE ,List 3 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_LIST3_NOTIFY ,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_LIST4_COMPLETE ,List 4 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_LIST4_NOTIFY ,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_LIST5_COMPLETE ,List 5 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_LIST5_NOTIFY ,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_LIST6_COMPLETE ,List 6 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_LIST6_NOTIFY ,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_LIST7_COMPLETE ,List 7 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_LIST7_NOTIFY ,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_CONTROL_DESCRIPTOR_INT0 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_CONTROL_DESCRIPTOR_INT1 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_CONTROL_DESCRIPTOR_INT2 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_CONTROL_DESCRIPTOR_INT3 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_CONTROL_DESCRIPTOR_INT4 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_CONTROL_DESCRIPTOR_INT5 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_CONTROL_DESCRIPTOR_INT6 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_CONTROL_DESCRIPTOR_INT7 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_CONTROL_DESCRIPTOR_INT8 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_CONTROL_DESCRIPTOR_INT9 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_CONTROL_DESCRIPTOR_INT10 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_CONTROL_DESCRIPTOR_INT11 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_CONTROL_DESCRIPTOR_INT12 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_CONTROL_DESCRIPTOR_INT13 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_CONTROL_DESCRIPTOR_INT14 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_CONTROL_DESCRIPTOR_INT15 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xDC++0x3 line.long 0x0 "VIP_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_LIST0_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_LIST0_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_LIST1_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_LIST1_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_LIST2_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_LIST2_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_LIST3_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_LIST3_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_LIST4_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_LIST4_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_LIST5_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_LIST5_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_LIST6_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_LIST6_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_LIST7_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_LIST7_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_CONTROL_DESCRIPTOR_INT0 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_CONTROL_DESCRIPTOR_INT1 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_CONTROL_DESCRIPTOR_INT2 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_CONTROL_DESCRIPTOR_INT3 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_CONTROL_DESCRIPTOR_INT4 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_CONTROL_DESCRIPTOR_INT5 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_CONTROL_DESCRIPTOR_INT6 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_CONTROL_DESCRIPTOR_INT7 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_CONTROL_DESCRIPTOR_INT8 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_CONTROL_DESCRIPTOR_INT9 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_CONTROL_DESCRIPTOR_INT10 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_CONTROL_DESCRIPTOR_INT11 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_CONTROL_DESCRIPTOR_INT12 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_CONTROL_DESCRIPTOR_INT13 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_CONTROL_DESCRIPTOR_INT14 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_CONTROL_DESCRIPTOR_INT15 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x200++0x3 line.long 0x0 "VIP_PERF_MON0,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: vip2_anc_b 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: vip2_anc_b 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x204++0x3 line.long 0x0 "VIP_PERF_MON1,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x208++0x3 line.long 0x0 "VIP_PERF_MON2,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x20C++0x3 line.long 0x0 "VIP_PERF_MON3,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x210++0x3 line.long 0x0 "VIP_PERF_MON4,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x214++0x3 line.long 0x0 "VIP_PERF_MON5,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x218++0x3 line.long 0x0 "VIP_PERF_MON6,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x21C++0x3 line.long 0x0 "VIP_PERF_MON7,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x220++0x3 line.long 0x0 "VIP_PERF_MON8,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x224++0x3 line.long 0x0 "VIP_PERF_MON9,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x228++0x3 line.long 0x0 "VIP_PERF_MON10,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x22C++0x3 line.long 0x0 "VIP_PERF_MON11,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x230++0x3 line.long 0x0 "VIP_PERF_MON12,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x234++0x3 line.long 0x0 "VIP_PERF_MON13,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x238++0x3 line.long 0x0 "VIP_PERF_MON14,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x23C++0x3 line.long 0x0 "VIP_PERF_MON15,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x240++0x3 line.long 0x0 "VIP_PERF_MON16,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x244++0x3 line.long 0x0 "VIP_PERF_MON17,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x248++0x3 line.long 0x0 "VIP_PERF_MON18,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x24C++0x3 line.long 0x0 "VIP_PERF_MON19,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x250++0x3 line.long 0x0 "VIP_PERF_MON20,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x254++0x3 line.long 0x0 "VIP_PERF_MON21,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x258++0x3 line.long 0x0 "VIP_PERF_MON22,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x25C++0x3 line.long 0x0 "VIP_PERF_MON23,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x260++0x3 line.long 0x0 "VIP_PERF_MON24,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x264++0x3 line.long 0x0 "VIP_PERF_MON25,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x268++0x3 line.long 0x0 "VIP_PERF_MON26,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x26C++0x3 line.long 0x0 "VIP_PERF_MON27,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x270++0x3 line.long 0x0 "VIP_PERF_MON28,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x274++0x3 line.long 0x0 "VIP_PERF_MON29,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x278++0x3 line.long 0x0 "VIP_PERF_MON30,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x27C++0x3 line.long 0x0 "VIP_PERF_MON31,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x280++0x3 line.long 0x0 "VIP_PERF_MON32,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3: vip1_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3: vip1_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x284++0x3 line.long 0x0 "VIP_PERF_MON33,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: vip1_lo_y 3: vip1_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: vip1_lo_y 3: vip1_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x288++0x3 line.long 0x0 "VIP_PERF_MON34,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_lo_y 1: 2: vip1_lo_uv 3: vip1_up_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_lo_y 1: 2: vip1_lo_uv 3: vip1_up_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x28C++0x3 line.long 0x0 "VIP_PERF_MON35,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_lo_uv 1: vip1_lo_y 2: vip1_up_y 3: vip1_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_lo_uv 1: vip1_lo_y 2: vip1_up_y 3: vip1_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x290++0x3 line.long 0x0 "VIP_PERF_MON36,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_up_y 1: vip1_lo_uv 2: vip1_up_uv 3: vip2_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_up_y 1: vip1_lo_uv 2: vip1_up_uv 3: vip2_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x294++0x3 line.long 0x0 "VIP_PERF_MON37,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_up_uv 1: vip1_up_y 2: vip2_lo_y 3: vip2_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_up_uv 1: vip1_up_y 2: vip2_lo_y 3: vip2_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x298++0x3 line.long 0x0 "VIP_PERF_MON38,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_lo_y 1: vip1_up_uv 2: vip2_lo_uv 3: vip2_up_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_lo_y 1: vip1_up_uv 2: vip2_lo_uv 3: vip2_up_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x29C++0x3 line.long 0x0 "VIP_PERF_MON39,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_lo_uv 1: vip2_lo_y 2: vip2_up_y 3: vip2_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_lo_uv 1: vip2_lo_y 2: vip2_up_y 3: vip2_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A0++0x3 line.long 0x0 "VIP_PERF_MON40,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_up_y 1: vip2_lo_uv 2: vip2_up_uv 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_up_y 1: vip2_lo_uv 2: vip2_up_uv 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A4++0x3 line.long 0x0 "VIP_PERF_MON41,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_up_uv 1: vip2_up_y 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_up_uv 1: vip2_up_y 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A8++0x3 line.long 0x0 "VIP_PERF_MON42,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: vip2_up_uv 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: vip2_up_uv 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2AC++0x3 line.long 0x0 "VIP_PERF_MON43,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B0++0x3 line.long 0x0 "VIP_PERF_MON44,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B4++0x3 line.long 0x0 "VIP_PERF_MON45,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B8++0x3 line.long 0x0 "VIP_PERF_MON46,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2BC++0x3 line.long 0x0 "VIP_PERF_MON47,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C0++0x3 line.long 0x0 "VIP_PERF_MON48,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C4++0x3 line.long 0x0 "VIP_PERF_MON49,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C8++0x3 line.long 0x0 "VIP_PERF_MON50,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3: vpi_ctl" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3: vpi_ctl" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2CC++0x3 line.long 0x0 "VIP_PERF_MON51,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: vpi_ctl 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: vpi_ctl 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2D0++0x3 line.long 0x0 "VIP_PERF_MON52,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vpi_ctl 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vpi_ctl 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2D4++0x3 line.long 0x0 "VIP_PERF_MON53,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: vpi_ctl 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: vpi_ctl 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2D8++0x3 line.long 0x0 "VIP_PERF_MON54,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2DC++0x3 line.long 0x0 "VIP_PERF_MON55,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2E0++0x3 line.long 0x0 "VIP_PERF_MON56,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3: vip1_anc_a" "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ," "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3: vip1_anc_a" "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ," "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2E4++0x3 line.long 0x0 "VIP_PERF_MON57,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: vip1_anc_a 3: vip1_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: vip1_anc_a 3: vip1_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2E8++0x3 line.long 0x0 "VIP_PERF_MON58,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_anc_a 1: 2: vip1_anc_b 3: vip2_anc_a" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_anc_a 1: 2: vip1_anc_b 3: vip2_anc_a" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2EC++0x3 line.long 0x0 "VIP_PERF_MON59,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_anc_b 1: vip1_anc_a 2: vip2_anc_a 3: vip2_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_anc_b 1: vip1_anc_a 2: vip2_anc_a 3: vip2_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2F0++0x3 line.long 0x0 "VIP_PERF_MON60,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_anc_a 1: vip1_anc_b 2: vip2_anc_b 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_anc_a 1: vip1_anc_b 2: vip2_anc_b 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2F4++0x3 line.long 0x0 "VIP_PERF_MON61,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_anc_b 1: vip2_anc_a 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_anc_b 1: vip2_anc_a 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x388++0x3 line.long 0x0 "VIP0_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x38C++0x3 line.long 0x0 "VIP0_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x390++0x3 line.long 0x0 "VIP0_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x394++0x3 line.long 0x0 "VIP0_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x398++0x3 line.long 0x0 "VIP1_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x39C++0x3 line.long 0x0 "VIP1_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3A0++0x3 line.long 0x0 "VIP1_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3A4++0x3 line.long 0x0 "VIP1_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3D0++0x3 line.long 0x0 "VPI_CTL_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3E8++0x3 line.long 0x0 "VIP0_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3EC++0x3 line.long 0x0 "VIP0_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3F0++0x3 line.long 0x0 "VIP1_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3F4++0x3 line.long 0x0 "VIP1_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." width 0x0B tree.end tree "VIP3_VPDMA" base ad:0x489BD000 width 31. group.byte 0x0++0x3 line.long 0x0 "VIP_PID,PID VIP VPDMA register" hexmask.long 0x0 0.--31. 1. " PID ,PID of VPDMA module" group.byte 0x4++0x3 line.long 0x0 "VIP_LIST_ADDR,The location of a new list to begin processing." hexmask.long 0x0 0.--31. 1. " VIP_LIST_ADDR ,Location of a new list of descriptors. This register must be written with the VPDMA Configuration Location after reset." group.byte 0x8++0x3 line.long 0x0 "VIP_LIST_ATTR,The attributes of a new list. This register should always be written after." hexmask.long.word 0x0 0.--15. 1. " LIST_SIZE ,Number of 128 bit word in the new list of descriptors. Writes to this register will activate the list in the list stack of the list manager and begin transfer of the list into VPDMA. This size can not be 0." bitfld.long 0x0 16.--18. " LIST_TYPE ,The type of list that has been generated.\\n0: Normal List\\n1: Self-Modifying List\\n2: List Doorbell\\nOthers Reserved for future use" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RDY ,This bit is low when a new list cannot be written to theVIP_LIST_ADDR register. The reasons this bit would be low are at initial startup if the LIST_MANAGER State Machine image has not completed loading. It also would be low if the last write to the VIP_LIST_ATTR attempted to start a list that is currently active. When this bit is low any writes to the list address register will cause access to not be accepted until this bit has set by the previous list having completed." "0,1" bitfld.long 0x0 20. " STOP ,This bit is written with the LIST_NUMBER field to stop a self-modifying list. When this bit is written a one the list specified by the LIST_NUMBER is sent a stop signal and will finish the current frame of transfers and then free the list resources." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " LIST_NUM ,The list number that should be assigned to the list located atVIP_LIST_ADDR. If the list is still active this will block all future list writes until the list is available." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xC++0x3 line.long 0x0 "VIP_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list." bitfld.long 0x0 0. " SYNC_LISTS0 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it." "0,1" bitfld.long 0x0 1. " SYNC_LISTS1 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it." "0,1" textline " " bitfld.long 0x0 2. " SYNC_LISTS2 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it." "0,1" bitfld.long 0x0 3. " SYNC_LISTS3 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it." "0,1" textline " " bitfld.long 0x0 4. " SYNC_LISTS4 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it." "0,1" bitfld.long 0x0 5. " SYNC_LISTS5 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it." "0,1" textline " " bitfld.long 0x0 6. " SYNC_LISTS6 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it." "0,1" bitfld.long 0x0 7. " SYNC_LISTS7 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " LIST0_BUSY ,The list 0 is currently running. Any attempt to load a new list to list 0 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 17. " LIST1_BUSY ,The list 1 is currently running. Any attempt to load a new list to list 1 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 18. " LIST2_BUSY ,The list 2 is currently running. Any attempt to load a new list to list 2 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 19. " LIST3_BUSY ,The list 3 is currently running. Any attempt to load a new list to list 3 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 20. " LIST4_BUSY ,The list 4 is currently running. Any attempt to load a new list to list 4 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 21. " LIST5_BUSY ,The list 5 is currently running. Any attempt to load a new list to list 5 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 22. " LIST6_BUSY ,The list 6 is currently running. Any attempt to load a new list to list 6 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 23. " LIST7_BUSY ,The list 7 is currently running. Any attempt to load a new list to list 7 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "VIP_BG_RGB,The registers used to set the background color for RGB" hexmask.long.byte 0x0 0.--7. 1. " BLEND ,The blend value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 8.--15. 1. " BLUE ,The blue value to give on an RGB data port for a blank pixel when using virtual video buffering" textline " " hexmask.long.byte 0x0 16.--23. 1. " GREEN ,The green value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 24.--31. 1. " RED ,The red value to give on an RGB data port for a blank pixel when using virtual video buffering" group.byte 0x1C++0x3 line.long 0x0 "VIP_BG_YUV,The registers used to set the background color for YUV" hexmask.long.byte 0x0 0.--7. 1. " CB ,The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 8.--15. 1. " CR ,The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering" textline " " hexmask.long.byte 0x0 16.--23. 1. " Y ,The Y value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "VIP_VPDMA_SETUP,Configures global parameters that are shared by all clients." bitfld.long 0x0 0. " SEC_BASE_CH ,Use Secondary Channels for Mosaic mode" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 1 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 1 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x38++0x3 line.long 0x0 "VIP_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 2 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 2 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x3C++0x3 line.long 0x0 "VIP_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 3 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 3 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x40++0x3 line.long 0x0 "VIP_INT0_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_HQ_VID1_LUMA ,The last write DMA transaction has completed for channel hq_vid1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_HQ_VID1_CHROMA ,The last write DMA transaction has completed for channel hq_vid1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_HQ_VID2_LUMA ,The last write DMA transaction has completed for channel hq_vid2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_HQ_VID2_CHROMA ,The last write DMA transaction has completed for channel hq_vid2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_HQ_VID3_LUMA ,The last write DMA transaction has completed for channel hq_vid3_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_HQ_VID3_CHROMA ,The last write DMA transaction has completed for channel hq_vid3_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_HQ_MV ,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client dei_hq_mv_in will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_HQ_MV_OUT ,The last write DMA transaction has completed for channel hq_mv_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_hq_mv_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_HQ_SCALER ,The last write DMA transaction has completed for channel hq_scaler. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_SCALER_LUMA ,The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SCALER_CHROMA ,The last write DMA transaction has completed for channel scaler_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_STAT_SCALER_OUT ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value" "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_GRPX1 ,The last read DMA transaction has occurred for channel grpx1 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx1_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_GRPX2 ,The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx2_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX3 ,The last read DMA transaction has occurred for channel grpx3 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx3_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x44++0x3 line.long 0x0 "VIP_INT0_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_HQ_VID1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_HQ_VID1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_HQ_VID2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_HQ_VID2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_HQ_VID3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_HQ_VID3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_HQ_MV ,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_HQ_MV_OUT ,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_HQ_SCALER ,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_SCALER_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SCALER_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_MASK_SCALER_OUT ,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_GRPX1 ,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_GRPX2 ,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX3 ,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x48++0x3 line.long 0x0 "VIP_INT0_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x4C++0x3 line.long 0x0 "VIP_INT0_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_PORTA_SRC0 ,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_PORTA_SRC1 ,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_PORTA_SRC2 ,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_PORTA_SRC3 ,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_PORTA_SRC4 ,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_PORTA_SRC5 ,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_PORTA_SRC6 ,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_PORTA_SRC7 ,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_PORTA_SRC8 ,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_PORTA_SRC9 ,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_PORTA_SRC10 ,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_PORTA_SRC11 ,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_PORTA_SRC12 ,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_PORTA_SRC13 ,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_PORTA_SRC14 ,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_PORTA_SRC15 ,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_PORTB_SRC0 ,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_PORTB_SRC1 ,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_PORTB_SRC2 ,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_PORTB_SRC3 ,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_PORTB_SRC4 ,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_PORTB_SRC5 ,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_PORTB_SRC6 ,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_PORTB_SRC7 ,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_PORTB_SRC8 ,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_PORTB_SRC9 ,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x50++0x3 line.long 0x0 "VIP_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x54++0x3 line.long 0x0 "VIP_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_PORTB_SRC10 ,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_PORTB_SRC11 ,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_PORTB_SRC12 ,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_PORTB_SRC13 ,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_PORTB_SRC14 ,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_PORTB_SRC15 ,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_ANCA_SRC0 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_ANCA_SRC1 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_ANCA_SRC2 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_ANCA_SRC3 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_ANCA_SRC4 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_ANCA_SRC5 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_ANCA_SRC6 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_ANCA_SRC7 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_ANCA_SRC8 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_ANCA_SRC9 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_ANCA_SRC10 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_ANCA_SRC11 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_ANCA_SRC12 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_ANCA_SRC13 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_ANCA_SRC14 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_ANCA_SRC15 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_ANCB_SRC0 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_ANCB_SRC1 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_ANCB_SRC2 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_ANCB_SRC3 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_ANCB_SRC4 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_ANCB_SRC5 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_ANCB_SRC6 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_ANCB_SRC7 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_ANCB_SRC8 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_ANCB_SRC9 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x58++0x3 line.long 0x0 "VIP_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_PORTA_LUMA ,The last write DMA transaction has completed for channel vip1_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip1_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_PORTB_LUMA ,The last write DMA transaction has completed for channel vip1_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip1_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_PORTA_RGB ,The last write DMA transaction has completed for channel vip1_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_PORTB_RGB ,The last write DMA transaction has completed for channel vip1_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x5C++0x3 line.long 0x0 "VIP_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_ANCB_SRC10 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_ANCB_SRC11 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_ANCB_SRC12 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_ANCB_SRC13 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_ANCB_SRC14 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_ANCB_SRC15 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_PORTA_RGB ,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_PORTB_RGB ,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_PORTA_SRC0 ,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_PORTA_SRC1 ,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_PORTA_SRC2 ,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_PORTA_SRC3 ,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_PORTA_SRC4 ,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_PORTA_SRC5 ,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_PORTA_SRC6 ,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_PORTA_SRC7 ,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_PORTA_SRC8 ,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_PORTA_SRC9 ,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_PORTA_SRC10 ,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_PORTA_SRC11 ,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_PORTA_SRC12 ,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_PORTA_SRC13 ,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_PORTA_SRC14 ,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_PORTA_SRC15 ,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_PORTB_SRC0 ,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_PORTB_SRC1 ,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_PORTB_SRC2 ,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_PORTB_SRC3 ,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x60++0x3 line.long 0x0 "VIP_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x64++0x3 line.long 0x0 "VIP_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_PORTB_SRC4 ,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_PORTB_SRC5 ,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_PORTB_SRC6 ,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_PORTB_SRC7 ,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_PORTB_SRC8 ,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_PORTB_SRC9 ,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_PORTB_SRC10 ,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_PORTB_SRC11 ,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_PORTB_SRC12 ,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_PORTB_SRC13 ,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_PORTB_SRC14 ,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_PORTB_SRC15 ,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_ANCA_SRC0 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_ANCA_SRC1 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_ANCA_SRC2 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_ANCA_SRC3 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_ANCA_SRC4 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_ANCA_SRC5 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_ANCA_SRC6 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_ANCA_SRC7 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_ANCA_SRC8 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_ANCA_SRC9 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_ANCA_SRC10 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_ANCA_SRC11 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_ANCA_SRC12 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_ANCA_SRC13 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_ANCA_SRC14 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_ANCA_SRC15 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_ANCB_SRC0 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_ANCB_SRC1 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_ANCB_SRC2 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_ANCB_SRC3 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x68++0x3 line.long 0x0 "VIP_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_PORTA_LUMA ,The last write DMA transaction has completed for channel vip2_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip2_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_PORTB_LUMA ,The last write DMA transaction has completed for channel vip2_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip2_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_PORTA_RGB ,The last write DMA transaction has completed for channel vip2_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_PORTB_RGB ,The last write DMA transaction has completed for channel vip2_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_OTHER ,This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_NF_WRITE_LUMA ,The last write DMA transaction has completed for channel nf_write_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_NF_WRITE_CHROMA ,The last write DMA transaction has completed for channel nf_write_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_NF_LAST_LUMA ,The last write DMA transaction has completed for channel nf_last_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_NF_LAST_CHROMA ,The last write DMA transaction has completed for channel nf_last_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VBI_SD_VENC ,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client vbi_sdvenc will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_POST_COMP_WR ,The last write DMA transaction has completed for channel post_comp_wr. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client hdmi_wrbk_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_PIP_FRAME ,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client pip_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_AUX_IN ,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client comp_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_TRANSCODE1_LUMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_TRANSCODE1_CHROMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_TRANSCODE2_LUMA ,The last write DMA transaction has completed for channel transcode2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_TRANSCODE2_CHROMA ,The last write DMA transaction has completed for channel transcode2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x6C++0x3 line.long 0x0 "VIP_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_ANCB_SRC4 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_ANCB_SRC5 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_ANCB_SRC6 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_ANCB_SRC7 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_ANCB_SRC8 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_ANCB_SRC9 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_ANCB_SRC10 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_ANCB_SRC11 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_ANCB_SRC12 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_ANCB_SRC13 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_ANCB_SRC14 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_ANCB_SRC15 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_PORTA_RGB ,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_PORTB_RGB ,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_OTHER ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_NF_WRITE_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_NF_WRITE_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_NF_LAST_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_NF_LAST_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VBI_SD_VENC ,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_POST_COMP_WR ,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_PIP_FRAME ,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_AUX_IN ,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_TRANSCODE1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_TRANSCODE1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_TRANSCODE2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_TRANSCODE2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x78++0x3 line.long 0x0 "VIP_INT0_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_DEI_HQ_1_CHROMA ,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_DEI_HQ_1_LUMA ,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_DEI_HQ_2_LUMA ,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_DEI_HQ_2_CHROMA ,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_DEI_HQ_3_LUMA ,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_DEI_HQ_3_CHROMA ,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_DEI_HQ_MV_IN ,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_DEI_HQ_MV_OUT ,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_DEI_SC_OUT ,The client interface dei_sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_PIP_WRBK ,The client interface pip_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SC_IN_CHROMA ,The client interface sc_in_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_SC_IN_LUMA ,The client interface sc_in_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_STAT_SC_OUT ,The client interface sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_COMP_WRBK ,The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX1_DATA ,The client interface grpx1_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x7C++0x3 line.long 0x0 "VIP_INT0_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_DEI_HQ_1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_DEI_HQ_1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_DEI_HQ_2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_DEI_HQ_2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_DEI_HQ_3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_DEI_HQ_3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_DEI_HQ_MV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_DEI_HQ_MV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_DEI_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_PIP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SC_IN_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_SC_IN_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_MASK_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_COMP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX1_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x80++0x3 line.long 0x0 "VIP_INT0_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_GRPX2_DATA ,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_GRPX3_DATA ,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_LO_Y ,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_LO_UV ,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_UP_Y ,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_UP_UV ,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_LO_Y ,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_LO_UV ,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_UP_Y ,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_UP_UV ,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_GRPX1_ST ,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_GRPX2_ST ,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_GRPX3_ST ,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_NF_422_IN ,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_NF_420_Y_IN ,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_NF_420_UV_IN ,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_NF_420_Y_OUT ,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_NF_420_UV_OUT ,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_STAT_VBI_SDVENC ,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VPI_CTL ,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_HDMI_WRBK_OUT ,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_TRANS1_CHROMA ,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_TRANS1_LUMA ,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_TRANS2_CHROMA ,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_TRANS2_LUMA ,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_ANC_A ,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_ANC_B ,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_ANC_A ,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_ANC_B ,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x84++0x3 line.long 0x0 "VIP_INT0_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_GRPX2_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_GRPX3_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_GRPX1_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_GRPX2_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_GRPX3_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_NF_422_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_NF_420_Y_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_NF_420_UV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_NF_420_Y_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_NF_420_UV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_MASK_VBI_SDVENC ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VPI_CTL ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_HDMI_WRBK_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_TRANS1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_TRANS1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_TRANS2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_TRANS2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x88++0x3 line.long 0x0 "VIP_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_LIST0_COMPLETE ,List 0 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_LIST0_NOTIFY ,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_LIST1_COMPLETE ,List 1 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_LIST1_NOTIFY ,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_LIST2_COMPLETE ,List 2 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_LIST2_NOTIFY ,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_LIST3_COMPLETE ,List 3 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_LIST3_NOTIFY ,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_LIST4_COMPLETE ,List 4 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_LIST4_NOTIFY ,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_LIST5_COMPLETE ,List 5 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_LIST5_NOTIFY ,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_LIST6_COMPLETE ,List 6 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_LIST6_NOTIFY ,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_LIST7_COMPLETE ,List 7 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_LIST7_NOTIFY ,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_CONTROL_DESCRIPTOR_INT0 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_CONTROL_DESCRIPTOR_INT1 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_CONTROL_DESCRIPTOR_INT2 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_CONTROL_DESCRIPTOR_INT3 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_CONTROL_DESCRIPTOR_INT4 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_CONTROL_DESCRIPTOR_INT5 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_CONTROL_DESCRIPTOR_INT6 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_CONTROL_DESCRIPTOR_INT7 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_CONTROL_DESCRIPTOR_INT8 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_CONTROL_DESCRIPTOR_INT9 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_CONTROL_DESCRIPTOR_INT10 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_CONTROL_DESCRIPTOR_INT11 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_CONTROL_DESCRIPTOR_INT12 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_CONTROL_DESCRIPTOR_INT13 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_CONTROL_DESCRIPTOR_INT14 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_CONTROL_DESCRIPTOR_INT15 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x8C++0x3 line.long 0x0 "VIP_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_LIST0_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_LIST0_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_LIST1_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_LIST1_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_LIST2_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_LIST2_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_LIST3_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_LIST3_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_LIST4_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_LIST4_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_LIST5_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_LIST5_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_LIST6_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_LIST6_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_LIST7_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_LIST7_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_CONTROL_DESCRIPTOR_INT0 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_CONTROL_DESCRIPTOR_INT1 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_CONTROL_DESCRIPTOR_INT2 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_CONTROL_DESCRIPTOR_INT3 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_CONTROL_DESCRIPTOR_INT4 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_CONTROL_DESCRIPTOR_INT5 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_CONTROL_DESCRIPTOR_INT6 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_CONTROL_DESCRIPTOR_INT7 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_CONTROL_DESCRIPTOR_INT8 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_CONTROL_DESCRIPTOR_INT9 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_CONTROL_DESCRIPTOR_INT10 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_CONTROL_DESCRIPTOR_INT11 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_CONTROL_DESCRIPTOR_INT12 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_CONTROL_DESCRIPTOR_INT13 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_CONTROL_DESCRIPTOR_INT14 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_CONTROL_DESCRIPTOR_INT15 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x90++0x3 line.long 0x0 "VIP_INT1_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_HQ_VID1_LUMA ,The last write DMA transaction has completed for channel hq_vid1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_HQ_VID1_CHROMA ,The last write DMA transaction has completed for channel hq_vid1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_HQ_VID2_LUMA ,The last write DMA transaction has completed for channel hq_vid2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_HQ_VID2_CHROMA ,The last write DMA transaction has completed for channel hq_vid2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_HQ_VID3_LUMA ,The last write DMA transaction has completed for channel hq_vid3_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_HQ_VID3_CHROMA ,The last write DMA transaction has completed for channel hq_vid3_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_HQ_MV ,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client dei_hq_mv_in will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_HQ_MV_OUT ,The last write DMA transaction has completed for channel hq_mv_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_hq_mv_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_HQ_SCALER ,The last write DMA transaction has completed for channel hq_scaler. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_SCALER_LUMA ,The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SCALER_CHROMA ,The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_STAT_SCALER_OUT ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_GRPX1 ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_GRPX2 ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX3 ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x94++0x3 line.long 0x0 "VIP_INT1_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_HQ_VID1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_HQ_VID1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_HQ_VID2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_HQ_VID2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_HQ_VID3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_HQ_VID3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_HQ_MV ,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_HQ_MV_OUT ,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_HQ_SCALER ,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_SCALER_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SCALER_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_MASK_SCALER_OUT ,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_GRPX1 ,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_GRPX2 ,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX3 ,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x98++0x3 line.long 0x0 "VIP_INT1_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x9C++0x3 line.long 0x0 "VIP_INT1_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_PORTA_SRC0 ,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_PORTA_SRC1 ,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_PORTA_SRC2 ,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_PORTA_SRC3 ,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_PORTA_SRC4 ,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_PORTA_SRC5 ,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_PORTA_SRC6 ,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_PORTA_SRC7 ,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_PORTA_SRC8 ,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_PORTA_SRC9 ,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_PORTA_SRC10 ,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_PORTA_SRC11 ,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_PORTA_SRC12 ,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_PORTA_SRC13 ,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_PORTA_SRC14 ,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_PORTA_SRC15 ,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_PORTB_SRC0 ,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_PORTB_SRC1 ,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_PORTB_SRC2 ,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_PORTB_SRC3 ,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_PORTB_SRC4 ,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_PORTB_SRC5 ,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_PORTB_SRC6 ,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_PORTB_SRC7 ,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_PORTB_SRC8 ,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_PORTB_SRC9 ,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xA0++0x3 line.long 0x0 "VIP_INT1_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xA4++0x3 line.long 0x0 "VIP_INT1_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_PORTB_SRC10 ,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_PORTB_SRC11 ,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_PORTB_SRC12 ,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_PORTB_SRC13 ,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_PORTB_SRC14 ,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_PORTB_SRC15 ,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_ANCA_SRC0 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_ANCA_SRC1 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_ANCA_SRC2 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_ANCA_SRC3 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_ANCA_SRC4 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_ANCA_SRC5 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_ANCA_SRC6 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_ANCA_SRC7 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_ANCA_SRC8 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_ANCA_SRC9 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_ANCA_SRC10 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_ANCA_SRC11 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_ANCA_SRC12 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_ANCA_SRC13 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_ANCA_SRC14 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_ANCA_SRC15 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_ANCB_SRC0 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_ANCB_SRC1 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_ANCB_SRC2 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_ANCB_SRC3 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_ANCB_SRC4 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_ANCB_SRC5 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_ANCB_SRC6 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_ANCB_SRC7 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_ANCB_SRC8 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_ANCB_SRC9 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xA8++0x3 line.long 0x0 "VIP_INT1_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_PORTA_LUMA ,The last write DMA transaction has completed for channel vip1_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip1_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_PORTB_LUMA ,The last write DMA transaction has completed for channel vip1_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip1_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_PORTA_RGB ,The last write DMA transaction has completed for channel vip1_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_PORTB_RGB ,The last write DMA transaction has completed for channel vip1_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xAC++0x3 line.long 0x0 "VIP_INT1_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_ANCB_SRC10 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_ANCB_SRC11 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_ANCB_SRC12 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_ANCB_SRC13 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_ANCB_SRC14 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_ANCB_SRC15 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_PORTA_RGB ,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_PORTB_RGB ,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_PORTA_SRC0 ,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_PORTA_SRC1 ,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_PORTA_SRC2 ,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_PORTA_SRC3 ,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_PORTA_SRC4 ,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_PORTA_SRC5 ,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_PORTA_SRC6 ,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_PORTA_SRC7 ,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_PORTA_SRC8 ,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_PORTA_SRC9 ,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_PORTA_SRC10 ,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_PORTA_SRC11 ,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_PORTA_SRC12 ,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_PORTA_SRC13 ,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_PORTA_SRC14 ,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_PORTA_SRC15 ,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_PORTB_SRC0 ,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_PORTB_SRC1 ,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_PORTB_SRC2 ,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_PORTB_SRC3 ,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xB0++0x3 line.long 0x0 "VIP_INT1_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xB4++0x3 line.long 0x0 "VIP_INT1_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_PORTB_SRC4 ,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_PORTB_SRC5 ,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_PORTB_SRC6 ,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_PORTB_SRC7 ,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_PORTB_SRC8 ,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_PORTB_SRC9 ,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_PORTB_SRC10 ,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_PORTB_SRC11 ,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_PORTB_SRC12 ,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_PORTB_SRC13 ,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_PORTB_SRC14 ,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_PORTB_SRC15 ,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_ANCA_SRC0 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_ANCA_SRC1 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_ANCA_SRC2 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_ANCA_SRC3 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_ANCA_SRC4 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_ANCA_SRC5 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_ANCA_SRC6 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_ANCA_SRC7 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_ANCA_SRC8 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_ANCA_SRC9 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_ANCA_SRC10 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_ANCA_SRC11 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_ANCA_SRC12 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_ANCA_SRC13 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_ANCA_SRC14 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_ANCA_SRC15 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_ANCB_SRC0 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_ANCB_SRC1 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_ANCB_SRC2 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_ANCB_SRC3 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xB8++0x3 line.long 0x0 "VIP_INT1_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_PORTA_LUMA ,The last write DMA transaction has completed for channel vip2_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip2_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_PORTB_LUMA ,The last write DMA transaction has completed for channel vip2_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip2_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_PORTA_RGB ,The last write DMA transaction has completed for channel vip2_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_PORTB_RGB ,The last write DMA transaction has completed for channel vip2_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_OTHER ,This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_NF_WRITE_LUMA ,The last write DMA transaction has completed for channel nf_write_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_NF_WRITE_CHROMA ,The last write DMA transaction has completed for channel nf_write_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_NF_LAST_LUMA ,The last write DMA transaction has completed for channel nf_last_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_NF_LAST_CHROMA ,The last write DMA transaction has completed for channel nf_last_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VBI_SD_VENC ,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client vbi_sdvenc will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_POST_COMP_WR ,The last write DMA transaction has completed for channel post_comp_wr. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client hdmi_wrbk_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_PIP_FRAME ,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client pip_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_AUX_IN ,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client comp_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_TRANSCODE1_LUMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_TRANSCODE1_CHROMA ,The last write DMA transaction has completed for channel transcode1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_TRANSCODE2_LUMA ,The last write DMA transaction has completed for channel transcode2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_TRANSCODE2_CHROMA ,The last write DMA transaction has completed for channel transcode2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xBC++0x3 line.long 0x0 "VIP_INT1_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_ANCB_SRC4 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_ANCB_SRC5 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_ANCB_SRC6 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_ANCB_SRC7 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_ANCB_SRC8 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_ANCB_SRC9 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_ANCB_SRC10 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_ANCB_SRC11 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_ANCB_SRC12 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_ANCB_SRC13 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_ANCB_SRC14 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_ANCB_SRC15 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_PORTA_RGB ,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_PORTB_RGB ,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_OTHER ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_NF_WRITE_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_NF_WRITE_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_NF_LAST_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_NF_LAST_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VBI_SD_VENC ,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_POST_COMP_WR ,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_PIP_FRAME ,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_AUX_IN ,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_TRANSCODE1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_TRANSCODE1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_TRANSCODE2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_TRANSCODE2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xC8++0x3 line.long 0x0 "VIP_INT1_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_DEI_HQ_1_CHROMA ,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_DEI_HQ_1_LUMA ,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_DEI_HQ_2_LUMA ,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_DEI_HQ_2_CHROMA ,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_DEI_HQ_3_LUMA ,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_DEI_HQ_3_CHROMA ,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_DEI_HQ_MV_IN ,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_DEI_HQ_MV_OUT ,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_PORTA_RGB ,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_PORTB_RGB ,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_NF_READ ,The interrupt for Noise Filter Input Data 422 Interleaved should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_NF_WRITE_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_NF_WRITE_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_NF_LAST_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_NF_LAST_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VBI_SD_VENC ,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_POST_COMP_WR ,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_PIP_FRAME ,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_AUX_IN ,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_TRANSCODE1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_TRANSCODE1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_TRANSCODE2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_TRANSCODE2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xCC++0x3 line.long 0x0 "VIP_INT1_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_DEI_HQ_1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_DEI_HQ_1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_DEI_HQ_2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_DEI_HQ_2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_DEI_HQ_3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_DEI_HQ_3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_DEI_HQ_MV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_DEI_HQ_MV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_DEI_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_PIP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SC_IN_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_SC_IN_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_MASK_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_COMP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX1_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0xD0++0x3 line.long 0x0 "VIP_INT1_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_GRPX2_DATA ,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_GRPX3_DATA ,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_LO_Y ,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_LO_UV ,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_UP_Y ,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_UP_UV ,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_LO_Y ,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_LO_UV ,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_UP_Y ,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_UP_UV ,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_GRPX1_ST ,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_GRPX2_ST ,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_GRPX3_ST ,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_NF_422_IN ,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_NF_420_Y_IN ,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_NF_420_UV_IN ,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_NF_420_Y_OUT ,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_NF_420_UV_OUT ,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_STAT_VBI_SDVENC ,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VPI_CTL ,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_HDMI_WRBK_OUT ,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_TRANS1_CHROMA ,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_TRANS1_LUMA ,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_TRANS2_CHROMA ,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_TRANS2_LUMA ,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_ANC_A ,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_ANC_B ,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_ANC_A ,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_ANC_B ,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0xD4++0x3 line.long 0x0 "VIP_INT1_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_GRPX2_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_GRPX3_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_GRPX1_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_GRPX2_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_GRPX3_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_NF_422_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_NF_420_Y_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_NF_420_UV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_NF_420_Y_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_NF_420_UV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_MASK_VBI_SDVENC ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VPI_CTL ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_HDMI_WRBK_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_TRANS1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_TRANS1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_TRANS2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_TRANS2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0xD8++0x3 line.long 0x0 "VIP_INT1_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int1." bitfld.long 0x0 0. " INT_STAT_LIST0_COMPLETE ,List 0 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_LIST0_NOTIFY ,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_LIST1_COMPLETE ,List 1 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_LIST1_NOTIFY ,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_LIST2_COMPLETE ,List 2 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_LIST2_NOTIFY ,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_LIST3_COMPLETE ,List 3 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_LIST3_NOTIFY ,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_LIST4_COMPLETE ,List 4 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_LIST4_NOTIFY ,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_LIST5_COMPLETE ,List 5 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_LIST5_NOTIFY ,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_LIST6_COMPLETE ,List 6 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_LIST6_NOTIFY ,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_LIST7_COMPLETE ,List 7 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_LIST7_NOTIFY ,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_CONTROL_DESCRIPTOR_INT0 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_CONTROL_DESCRIPTOR_INT1 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_CONTROL_DESCRIPTOR_INT2 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_CONTROL_DESCRIPTOR_INT3 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_CONTROL_DESCRIPTOR_INT4 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_CONTROL_DESCRIPTOR_INT5 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_CONTROL_DESCRIPTOR_INT6 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_CONTROL_DESCRIPTOR_INT7 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_CONTROL_DESCRIPTOR_INT8 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_CONTROL_DESCRIPTOR_INT9 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_CONTROL_DESCRIPTOR_INT10 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_CONTROL_DESCRIPTOR_INT11 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_CONTROL_DESCRIPTOR_INT12 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_CONTROL_DESCRIPTOR_INT13 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_CONTROL_DESCRIPTOR_INT14 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_CONTROL_DESCRIPTOR_INT15 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0xDC++0x3 line.long 0x0 "VIP_INT1_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int1." bitfld.long 0x0 0. " INT_MASK_LIST0_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_LIST0_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_LIST1_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_LIST1_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_LIST2_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_LIST2_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_LIST3_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_LIST3_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_LIST4_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_LIST4_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_LIST5_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_LIST5_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_LIST6_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_LIST6_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_LIST7_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_LIST7_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_CONTROL_DESCRIPTOR_INT0 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_CONTROL_DESCRIPTOR_INT1 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_CONTROL_DESCRIPTOR_INT2 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_CONTROL_DESCRIPTOR_INT3 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_CONTROL_DESCRIPTOR_INT4 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_CONTROL_DESCRIPTOR_INT5 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_CONTROL_DESCRIPTOR_INT6 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_CONTROL_DESCRIPTOR_INT7 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_CONTROL_DESCRIPTOR_INT8 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_CONTROL_DESCRIPTOR_INT9 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_CONTROL_DESCRIPTOR_INT10 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_CONTROL_DESCRIPTOR_INT11 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_CONTROL_DESCRIPTOR_INT12 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_CONTROL_DESCRIPTOR_INT13 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_CONTROL_DESCRIPTOR_INT14 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_CONTROL_DESCRIPTOR_INT15 ,The interrupt for should generate an interrupt on interrupt vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x200++0x3 line.long 0x0 "VIP_PERF_MON0,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: vip2_anc_b 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: vip2_anc_b 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x204++0x3 line.long 0x0 "VIP_PERF_MON1,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x208++0x3 line.long 0x0 "VIP_PERF_MON2,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x20C++0x3 line.long 0x0 "VIP_PERF_MON3,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x210++0x3 line.long 0x0 "VIP_PERF_MON4,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x214++0x3 line.long 0x0 "VIP_PERF_MON5,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x218++0x3 line.long 0x0 "VIP_PERF_MON6,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x21C++0x3 line.long 0x0 "VIP_PERF_MON7,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x220++0x3 line.long 0x0 "VIP_PERF_MON8,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x224++0x3 line.long 0x0 "VIP_PERF_MON9,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x228++0x3 line.long 0x0 "VIP_PERF_MON10,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x22C++0x3 line.long 0x0 "VIP_PERF_MON11,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x230++0x3 line.long 0x0 "VIP_PERF_MON12,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x234++0x3 line.long 0x0 "VIP_PERF_MON13,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x238++0x3 line.long 0x0 "VIP_PERF_MON14,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x23C++0x3 line.long 0x0 "VIP_PERF_MON15,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x240++0x3 line.long 0x0 "VIP_PERF_MON16,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x244++0x3 line.long 0x0 "VIP_PERF_MON17,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x248++0x3 line.long 0x0 "VIP_PERF_MON18,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x24C++0x3 line.long 0x0 "VIP_PERF_MON19,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x250++0x3 line.long 0x0 "VIP_PERF_MON20,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x254++0x3 line.long 0x0 "VIP_PERF_MON21,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x258++0x3 line.long 0x0 "VIP_PERF_MON22,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x25C++0x3 line.long 0x0 "VIP_PERF_MON23,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x260++0x3 line.long 0x0 "VIP_PERF_MON24,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x264++0x3 line.long 0x0 "VIP_PERF_MON25,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x268++0x3 line.long 0x0 "VIP_PERF_MON26,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x26C++0x3 line.long 0x0 "VIP_PERF_MON27,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x270++0x3 line.long 0x0 "VIP_PERF_MON28,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x274++0x3 line.long 0x0 "VIP_PERF_MON29,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x278++0x3 line.long 0x0 "VIP_PERF_MON30,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x27C++0x3 line.long 0x0 "VIP_PERF_MON31,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x280++0x3 line.long 0x0 "VIP_PERF_MON32,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3: vip1_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3: vip1_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x284++0x3 line.long 0x0 "VIP_PERF_MON33,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: vip1_lo_y 3: vip1_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: vip1_lo_y 3: vip1_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x288++0x3 line.long 0x0 "VIP_PERF_MON34,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_lo_y 1: 2: vip1_lo_uv 3: vip1_up_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_lo_y 1: 2: vip1_lo_uv 3: vip1_up_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x28C++0x3 line.long 0x0 "VIP_PERF_MON35,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_lo_uv 1: vip1_lo_y 2: vip1_up_y 3: vip1_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_lo_uv 1: vip1_lo_y 2: vip1_up_y 3: vip1_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x290++0x3 line.long 0x0 "VIP_PERF_MON36,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_up_y 1: vip1_lo_uv 2: vip1_up_uv 3: vip2_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_up_y 1: vip1_lo_uv 2: vip1_up_uv 3: vip2_lo_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x294++0x3 line.long 0x0 "VIP_PERF_MON37,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_up_uv 1: vip1_up_y 2: vip2_lo_y 3: vip2_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_up_uv 1: vip1_up_y 2: vip2_lo_y 3: vip2_lo_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x298++0x3 line.long 0x0 "VIP_PERF_MON38,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_lo_y 1: vip1_up_uv 2: vip2_lo_uv 3: vip2_up_y" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_lo_y 1: vip1_up_uv 2: vip2_lo_uv 3: vip2_up_y" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x29C++0x3 line.long 0x0 "VIP_PERF_MON39,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_lo_uv 1: vip2_lo_y 2: vip2_up_y 3: vip2_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_lo_uv 1: vip2_lo_y 2: vip2_up_y 3: vip2_up_uv" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A0++0x3 line.long 0x0 "VIP_PERF_MON40,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_up_y 1: vip2_lo_uv 2: vip2_up_uv 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_up_y 1: vip2_lo_uv 2: vip2_up_uv 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A4++0x3 line.long 0x0 "VIP_PERF_MON41,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_up_uv 1: vip2_up_y 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_up_uv 1: vip2_up_y 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A8++0x3 line.long 0x0 "VIP_PERF_MON42,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: vip2_up_uv 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: vip2_up_uv 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2AC++0x3 line.long 0x0 "VIP_PERF_MON43,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B0++0x3 line.long 0x0 "VIP_PERF_MON44,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B4++0x3 line.long 0x0 "VIP_PERF_MON45,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B8++0x3 line.long 0x0 "VIP_PERF_MON46,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2BC++0x3 line.long 0x0 "VIP_PERF_MON47,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C0++0x3 line.long 0x0 "VIP_PERF_MON48,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C4++0x3 line.long 0x0 "VIP_PERF_MON49,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C8++0x3 line.long 0x0 "VIP_PERF_MON50,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3: vpi_ctl" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3: vpi_ctl" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2CC++0x3 line.long 0x0 "VIP_PERF_MON51,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: vpi_ctl 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: vpi_ctl 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2D0++0x3 line.long 0x0 "VIP_PERF_MON52,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vpi_ctl 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vpi_ctl 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2D4++0x3 line.long 0x0 "VIP_PERF_MON53,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: vpi_ctl 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: vpi_ctl 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2D8++0x3 line.long 0x0 "VIP_PERF_MON54,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2DC++0x3 line.long 0x0 "VIP_PERF_MON55,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2E0++0x3 line.long 0x0 "VIP_PERF_MON56,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: 3: vip1_anc_a" "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ," "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: 3: vip1_anc_a" "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ," "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2E4++0x3 line.long 0x0 "VIP_PERF_MON57,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: 1: 2: vip1_anc_a 3: vip1_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: 1: 2: vip1_anc_a 3: vip1_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2E8++0x3 line.long 0x0 "VIP_PERF_MON58,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_anc_a 1: 2: vip1_anc_b 3: vip2_anc_a" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_anc_a 1: 2: vip1_anc_b 3: vip2_anc_a" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2EC++0x3 line.long 0x0 "VIP_PERF_MON59,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip1_anc_b 1: vip1_anc_a 2: vip2_anc_a 3: vip2_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip1_anc_b 1: vip1_anc_a 2: vip2_anc_a 3: vip2_anc_b" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2F0++0x3 line.long 0x0 "VIP_PERF_MON60,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_anc_a 1: vip1_anc_b 2: vip2_anc_b 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_anc_a 1: vip1_anc_b 2: vip2_anc_b 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2F4++0x3 line.long 0x0 "VIP_PERF_MON61,The register can be used to capture timing differences between events in the VPDMA\\n" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter. 0: vip2_anc_b 1: vip2_anc_a 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter. 0: command request 1: command accept 2: data request 3: data rcvd 4: data empty 5: data full 6: frame start 7: frame end" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter. 0: vip2_anc_b 1: vip2_anc_a 2: 3:" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x388++0x3 line.long 0x0 "VIP0_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x38C++0x3 line.long 0x0 "VIP0_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x390++0x3 line.long 0x0 "VIP0_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x394++0x3 line.long 0x0 "VIP0_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x398++0x3 line.long 0x0 "VIP1_LO_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x39C++0x3 line.long 0x0 "VIP1_LO_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3A0++0x3 line.long 0x0 "VIP1_UP_Y_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3A4++0x3 line.long 0x0 "VIP1_UP_UV_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3D0++0x3 line.long 0x0 "VPI_CTL_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3E8++0x3 line.long 0x0 "VIP0_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3EC++0x3 line.long 0x0 "VIP0_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3F0++0x3 line.long 0x0 "VIP1_ANC_A_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3F4++0x3 line.long 0x0 "VIP1_ANC_B_CSTAT,The register holds status information and control for the client.\\n" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client.\\n0 : Change in value of hdmi_field_id\\n1 : Change in value of dvo2_field_id\\n2 : Change in value of hdcomp_field_id\\n3 : Change in value of sd_field_id\\n4 : Use List Manager Internal Field0\\n5 : Use List Manager Internal Field1\\n6 : Use List Manager Internal Field2\\n7 : Start on channel active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." width 0x0B tree.end tree "VIP1_top_level" base ad:0x48970000 width 28. group.byte 0x0++0x3 line.long 0x0 "VIP_CLKC_PID,This register follows the format described in PDR3.5" bitfld.long 0x0 0.--5. " MINOR ,inor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Custom IP" "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " MAJOR ,ajor Release Number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNC ,The function of the module being used" bitfld.long 0x0 28.--29. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,The scheme of the register used. This indicates the PDR3.5 Method" "0,1,2,3" group.byte 0x10++0x3 line.long 0x0 "VIP_SYSCONFIG,VIP_SYSCONFIG" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state 0x0 : Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup mode, for debug only 0x1 : No-idle mode: local target never enters idle state. Backup mode, for debug only 0x2 : Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events 0x3 : Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state. Mode is only relevant if the appropriate IP module 'swakeup' output(s) is (are) implemented" "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state 0x0: Force-standby mode: local initiator is unconditionally placed in standby state. Backup mode, for debug only 0x1: No-standby mode: local initiator is unconditionally placed out of standby state. Backup mode, for debug only 0x2: Same behavior as bit-field value of 0x1. 0x3: Reserved" "0,1,2,3" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_RAW ,VPDMA INT0 List0 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_RAW ,VPDMA INT0 List0 Notify Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_RAW ,VPDMA INT0 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_RAW ,VPDMA INT0 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_RAW ,VPDMA INT0 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_RAW ,VPDMA INT0 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_RAW ,VPDMA INT0 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_RAW ,VPDMA INT0 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_RAW ,VPDMA INT0 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_RAW ,VPDMA INT0 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_RAW ,VPDMA INT0 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_RAW ,VPDMA INT0 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_RAW ,VPDMA INT0 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_RAW ,VPDMA INT0 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_RAW ,VPDMA INT0 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_RAW ,VPDMA INT0 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_RAW ,VPDMA INT0 Descriptor Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_RAW ,VIP1 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_RAW ,VIP2 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_RAW ,VPDMA INT0 Channel Group0 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_RAW ,VPDMA INT0 Channel Group1 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_RAW ,VPDMA INT0 Channel Group2 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_RAW ,VPDMA INT0 Channel Group3 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_RAW ,VPDMA INT0 Channel Group4 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_RAW ,VPDMA INT0 Channel Group5 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_RAW ,VPDMA INT0 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x28++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_ENA0,INTC INTR0 Interrupt Status Enabled/Clear Register 0. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA ,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA ,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA ,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA ,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA ,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA ,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA ,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA ,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA ,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA ,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA ,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA ,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA ,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA ,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA ,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA ,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA ,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA ,VIP1 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA ,VIP2 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_ENA1,INTC INTR0 Interrupt Status Enabled/Clear Register 1. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA ,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA ,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA ,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA ,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA ,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA ,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA ,VPDMA INT0 Client Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x30++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_SET0,INTC INTR0 Interrupt Enable/Set Register 0. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_SET ,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_SET ,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_SET ,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_SET ,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_SET ,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_SET ,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_SET ,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_SET ,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_SET ,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_SET ,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_SET ,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_SET ,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_SET ,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_SET ,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_SET ,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_SET ,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA_SET ,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_SET ,VIP1 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_SET ,VIP2 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_SET1,INTC INTR0 Interrupt Enable/Set Register 1. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_SET ,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_SET ,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_SET ,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_SET ,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_SET ,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_SET ,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_CHANNEL_GROUP6_ENA_SET ,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA_SET ,VPDMA INT0 Client Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x38++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_CLR ,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_CLR ,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_CLR ,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_CLR ,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_CLR ,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_CLR ,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_CLR ,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_CLR ,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_CLR ,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_CLR ,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_CLR ,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_CLR ,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_CLR ,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_CLR ,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_CLR ,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_CLR ,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA_CLR ,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_CLR ,VIP1 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_CLR ,VIP2 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR ,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA_CLR ,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x40++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_RAW0,INTC intr1 Interrupt Status Raw/Set Register 0. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_RAW ,VPDMA INT1 List0 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_RAW ,VPDMA INT1 List0 Notify Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_RAW ,VPDMA INT1 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_RAW ,VPDMA INT1 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_RAW ,VPDMA INT1 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_RAW ,VPDMA INT1 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_RAW ,VPDMA INT1 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_RAW ,VPDMA INT1 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_RAW ,VPDMA INT1 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_RAW ,VPDMA INT1 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_RAW ,VPDMA INT1 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_RAW ,VPDMA INT1 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_RAW ,VPDMA INT1 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_RAW ,VPDMA INT1 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_RAW ,VPDMA INT1 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_RAW ,VPDMA INT1 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_RAW ,VPDMA INT1 Descriptor Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_RAW ,VIP1 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_RAW ,VIP2 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_RAW1,INTC intr1 Interrupt Status Raw/Set Register 1. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_RAW ,VPDMA INT1 Channel Group0 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_RAW ,VPDMA INT1 Channel Group1 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_RAW ,VPDMA INT1 Channel Group2 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_RAW ,VPDMA INT1 Channel Group3 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_RAW ,VPDMA INT1 Channel Group4 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_RAW ,VPDMA INT1 Channel Group5 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_RAW ,VPDMA INT1 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x48++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_ENA0,INTC intr1 Interrupt Status Enabled/Clear Register 0. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_ENA ,VPDMA INT1 List0 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_ENA ,VPDMA INT1 List0 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_ENA ,VPDMA INT1 List1 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_ENA ,VPDMA INT1 List1 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_ENA ,VPDMA INT1 List2 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_ENA ,VPDMA INT1 List2 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_ENA ,VPDMA INT1 List3 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_ENA ,VPDMA INT1 List3 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_ENA ,VPDMA INT1 List4 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_ENA ,VPDMA INT1 List4 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_ENA ,VPDMA INT1 List5 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_ENA ,VPDMA INT1 List5 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_ENA ,VPDMA INT1 List6 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_ENA ,VPDMA INT1 List6 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_ENA ,VPDMA INT1 List7 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_ENA ,VPDMA INT1 List7 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_ENA ,VPDMA INT1 Descriptor Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA ,VIP1 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA ,VIP2 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_ENA1,INTC intr1 Interrupt Status Enabled/Clear Register 1. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_ENA ,VPDMA INT1 Channel Group0 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_ENA ,VPDMA INT1 Channel Group1 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_ENA ,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_ENA ,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_ENA ,VPDMA INT1 Channel Group4 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_ENA ,VPDMA INT1 Channel Group5 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_ENA ,VPDMA INT1 Client Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x50++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_SET0,INTC intr1 Interrupt Enable/Set Register 0. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_ENA_SET ,VPDMA INT1 List0 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_ENA_SET ,VPDMA INT1 List0 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_ENA_SET ,VPDMA INT1 List1 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_ENA_SET ,VPDMA INT1 List1 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_ENA_SET ,VPDMA INT1 List2 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_ENA_SET ,VPDMA INT1 List2 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_ENA_SET ,VPDMA INT1 List3 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_ENA_SET ,VPDMA INT1 List3 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_ENA_SET ,VPDMA INT1 List4 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_ENA_SET ,VPDMA INT1 List4 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_ENA_SET ,VPDMA INT1 List5 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_ENA_SET ,VPDMA INT1 List5 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_ENA_SET ,VPDMA INT1 List6 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_ENA_SET ,VPDMA INT1 List6 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_ENA_SET ,VPDMA INT1 List7 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_ENA_SET ,VPDMA INT1 List7 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_ENA_SET ,VPDMA INT1 Descriptor Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_SET ,VIP1 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_SET ,VIP2 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_SET1,INTC intr1 Interrupt Enable/Set Register 1. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_ENA_SET ,VPDMA INT1 Channel Group0 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_ENA_SET ,VPDMA INT1 Channel Group1 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_ENA_SET ,VPDMA INT1 Channel Group2 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_ENA_SET ,VPDMA INT1 Channel Group3 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_ENA_SET ,VPDMA INT1 Channel Group4 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_ENA_SET ,VPDMA INT1 Channel Group5 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_CHANNEL_GROUP6_ENA_SET ,VPDMA INT1 Channel Group6 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_ENA_SET ,VPDMA INT1 Client Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x58++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_CLR0,INTC intr1 Interrupt Enable/Clear Register 0. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_ENA_CLR ,VPDMA INT1 List0 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_ENA_CLR ,VPDMA INT1 List0 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_ENA_CLR ,VPDMA INT1 List1 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_ENA_CLR ,VPDMA INT1 List1 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_ENA_CLR ,VPDMA INT1 List2 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_ENA_CLR ,VPDMA INT1 List2 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_ENA_CLR ,VPDMA INT1 List3 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_ENA_CLR ,VPDMA INT1 List3 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_ENA_CLR ,VPDMA INT1 List4 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_ENA_CLR ,VPDMA INT1 List4 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_ENA_CLR ,VPDMA INT1 List5 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_ENA_CLR ,VPDMA INT1 List5 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_ENA_CLR ,VPDMA INT1 List6 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_ENA_CLR ,VPDMA INT1 List6 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_ENA_CLR ,VPDMA INT1 List7 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_ENA_CLR ,VPDMA INT1 List7 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_ENA_CLR ,VPDMA INT1 Descriptor Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_CLR ,VIP1 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_CLR ,VIP2 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_CLR1,INTC intr1 Interrupt Enable/Clear Register 1. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT1 Channel Group0 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT1 Channel Group1 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT1 Channel Group2 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT1 Channel Group3 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT1 Channel Group4 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT1 Channel Group5 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_CHANNEL_GROUP6_ENA_CLR ,VPDMA INT1 Channel Group6 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_ENA_CLR ,VPDMA INT1 Client Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xA0++0x3 line.long 0x0 "VIP_INTC_EOI,INTC EOI Register. This register contains the EOI vector register contents as defined by HL0.8" hexmask.long 0x0 0.--31. 1. " EOI_VECTOR ,Number associated with the ipgenericirq for intr output. There are 4 interrupt outputs Write 0x0 : Write to intr0 IP Generic Write 0x1 : Write to intr1 IP Generic Write 0x2 : Write to intr2 IP Generic Write 0x3 : Write to intr3 IP Generic Any other write value is ignored." group.byte 0x100++0x3 line.long 0x0 "VIP_CLKC_CLKEN,CLKC Module Clock Enable Register. This register contains clock enables for the processing paths in the VIP module." bitfld.long 0x0 0. " VPDMA_EN ,VPDMA Clock Enable, 1 = Clock Enabled, 0 = Clock Disabled" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIP1_DP_EN ,VIP Slice0 Data Path Clock Enable, 1 = Clock Enabled, 0 = Clock Disabled" "0,1" bitfld.long 0x0 17. " VIP2_DP_EN ,VIP Slice1 Data Path Clock Enable, 1 = Clock Enabled, 0 = Clock Disabled" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "VIP_CLKC_RST,CLKC Module Reset Register. This register contains resets for the processing paths in the VIP module." bitfld.long 0x0 0. " VPDMA_RST ,VPDMA Reset" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " VIP1_DP_RST ,VIP Slice0 Data Path Reset" "0,1" bitfld.long 0x0 17. " VIP2_DP_RST ,VIP Slice1 Data Path Reset" "0,1" textline " " bitfld.long 0x0 18. " S0_PARSER_RST ,VIP Slice0 parser reset" "0,1" bitfld.long 0x0 19. " S1_PARSER_RST ,VIP Slice1 parser reset" "0,1" textline " " bitfld.long 0x0 20. " S0_CSC_RST ,VIP Slice0 CSC reset" "0,1" bitfld.long 0x0 21. " S1_CSC_RST ,VIP Slice1 CSC reset" "0,1" textline " " bitfld.long 0x0 22. " S0_SC_RST ,VIP Slice0 SC reset" "0,1" bitfld.long 0x0 23. " S1_SC_RST ,VIP Slice1 SC reset" "0,1" textline " " bitfld.long 0x0 24. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 25. " S0_CHR_DS_0_RST ,VIP Slice0 CHRDS0 reset" "0,1" textline " " bitfld.long 0x0 26. " S1_CHR_DS_0_RST ,VIP Slice1 CHRDS0 reset" "0,1" bitfld.long 0x0 27. " S0_CHR_DS_1_RST ,VIP Slice0 CHRDS1 reset" "0,1" textline " " bitfld.long 0x0 28. " S1_CHR_DS_1_RST ,VIP Slice1 CHRDS1 reset" "0,1" bitfld.long 0x0 29.--30. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 31. " MAIN_RST ,Reset for all modules in VIP Main Data Path" "0,1" group.byte 0x108++0x3 line.long 0x0 "VIP_CLKC_DPS,CLKC Main Data Path Select Register. This register selects the various data paths within main portion (non-VIP) of the subsystem" bitfld.long 0x0 0. " VPDMA_RST ,VPDMA Reset" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIP1_DP_RST ,Video Input Port 1 Data Path Reset" "0,1" bitfld.long 0x0 17. " VIP2_DP_RST ,Video Input Port 2 Data Path Reset" "0,1" textline " " hexmask.long.word 0x0 18.--30. 1. " RESERVED ," bitfld.long 0x0 31. " MAIN_RST ,Reset for all modules in DSS Main Data Path" "0,1" group.byte 0x10C++0x3 line.long 0x0 "VIP_CLKC_VIP0DPS,CLKC Video Input Port 1 Data Path Select Register. This register selects the various data paths within the Video Input Port portion of the subsystem" bitfld.long 0x0 0.--2. " VIP1_CSC_SRC_SELECT ,Video Input Port 1 CSC Source Select 000 : Path Disabled 001 : Source from VIP_PARSER A (422) port 010 : Source from VIP_PARSER B port 011 : Source from Transcode (422) 100 : Source from VIP_PARSER A (RGB) port 101 : Source from Compositor (RGB) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " VIP1_SC_SRC_SELECT ,Video Input Port 1 SC_M Source Select 000 : Path Disabled 001 : Source from Color Space Converter (CSC) 010 : Source from VIP_PARSER A port 011 : Source from VIP_PARSER B port 100 : Source from Transcode (422) 101 : Reserved 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6. " VIP1_RGB_SRC_SELECT ,Video Input Port 1 RGB Output Path Select 0 : Source from Compositor RGB input 1 : Source from CSC" "0,1" bitfld.long 0x0 7. " VIP1_RGB_OUT_LO_SELECT ,Video Input Port 1 LO RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" textline " " bitfld.long 0x0 8. " VIP1_RGB_OUT_HI_SELECT ,Video Input Port 1 HI RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" bitfld.long 0x0 9.--11. " VIP1_CHR_DS_1_SRC_SELECT ,Video Input Port 1 Chroma Downsampler 1 Source Select 000 : Path Disabled (no input to CHR_DS) 001 : Source from Scaler (SC_M) 010 : Source from Color Space Converter (CSC) 011 : Source from VIP_PARSER A port 100 : Source from VIP_PARSER B port 101 : Source from Transcode (422) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12.--14. " VIP1_CHR_DS_2_SRC_SELECT ,Video Input Port 1 Chroma Downsampler 2 Source Select 0 : Path Disabled (no input to CHR_DS) 1 : Source from Scaler (SC_M) 2 : Source from Color Space Converter (CSC) 3 : Source from VIP_PARSER A port 4 : Source from VIP_PARSER B port 5 : Source from Transcode (422) 6 : Reserved 7 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " VIP1_MULTI_CHANNEL_SELECT ,Video Input Port 1 Multi Channel Select 0 : VIP_PARSER A and B channels operate in single channel mode 1 : VIP_PARSER A and B channels directly drive VPDMA (multi-channel case) Multi-Channel means that the A and B sources are from multiple channels and used in a multiplexed stream mode. The VIP Parser extracts the channel ID from each source and outputs this information to VPDMA, and thus to memory. When operating in a multiplexed stream mode, this bit must be set to 1 to enable the channel information to be passed to memory. If this is not set, the channel number (or source number) will be 0 for all streams. If vip1_rgb_out_select = 1, then VIP_PARSER A port is connected to VPDMA" "0,1" textline " " bitfld.long 0x0 16. " VIP1_CHR_DS_1_BYPASS ,Video Input Port 1 Chroma Downsampler 1 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" bitfld.long 0x0 17. " VIP1_CHR_DS_2_BYPASS ,Video Input Port 1 Chroma Downsampler 2 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" textline " " hexmask.long.byte 0x0 18.--25. 1. " RESERVED ," bitfld.long 0x0 26. " VIP1_TESTPORT_B_SELECT ,0 : Normal mode 1: Test Mode" "0,1" textline " " bitfld.long 0x0 27. " VIP1_TESTPORT_A_SELECT ,0 : Normal mode 1: Test Mode" "0,1" bitfld.long 0x0 28.--31. " VIP1_DATAPATH_SELECT ,VIP1 Datapath Register Field Enable 0000 : All fields written 0001 : Only vip1_csc_src_select written 0010 : Only vip1_sc_src_select written 0011 : Only vip1_rgb_src_select written 0100 : Only vip1_rgb_out_lo_select written 0101 : Only vip1_rgb_out_hi_select written 0110 : Only vip1_chr_ds_1_src_select written 0111 : Only vip1_chr_ds_2_src_select written 1000 : Only vip1_multi_channel_select written 1001 : Only vip1_chr_ds_1_bypass written 1010 : Only vip1_chr_ds_2_bypass written 1011 : Reserved 1100 : Reserved 1101 : Reserved 1110 : Reserved 1111 : Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x110++0x3 line.long 0x0 "VIP_CLKC_VIP1DPS,CLKC Video Input Port 2 Data Path Select Register. This register selects the various data paths within the Video Input Port portion of the subsystem" bitfld.long 0x0 0.--2. " VIP2_CSC_SRC_SELECT ,Video Input Port 2 CSC Source Select 000 : Path Disabled 001 : Source from VIP_PARSER A (422) port 010 : Source from VIP_PARSER B port 011 : Source from Transcode (422) 100 : Source from VIP_PARSER A (RGB) port 101 : Source from Compositor (RGB) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " VIP2_SC_SRC_SELECT ,Video Input Port 2 SC_M Source Select 000 : Path Disabled 001 : Source from Color Space Converter (CSC) 010 : Source from VIP_PARSER A port 011 : Source from VIP_PARSER B port 100 : Source from Transcode (422) 101 : Reserved 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6. " VIP2_RGB_SRC_SELECT ,Video Input Port 2 RGB Output Path Select 0 : Source from Compositor RGB input 1 : Source from CSC" "0,1" bitfld.long 0x0 7. " VIP2_RGB_OUT_LO_SELECT ,Video Input Port 2 LO RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" textline " " bitfld.long 0x0 8. " VIP2_RGB_OUT_HI_SELECT ,Video Input Port 2 HI RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" bitfld.long 0x0 9.--11. " VIP2_CHR_DS_1_SRC_SELECT ,Video Input Port 2 Chroma Downsampler 1 Source Select 000 : Path Disabled (no input to CHR_DS) 001 : Source from Scaler (SC_M) 010 : Source from Color Space Converter (CSC) 011 : Source from VIP_PARSER A port 100 : Source from VIP_PARSER B port 101 : Source from Transcode (422) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12.--14. " VIP2_CHR_DS_2_SRC_SELECT ,Video Input Port 2 Chroma Downsampler 2 Source Select 0 : Path Disabled (no input to CHR_DS) 1 : Source from Scaler (SC_M) 2 : Source from Color Space Converter (CSC) 3 : Source from VIP_PARSER A port 4 : Source from VIP_PARSER B port 5 : Source from Transcode (422) 6 : Reserved 7 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " VIP2_MULTI_CHANNEL_SELECT ,Video Input Port 2 Multi Channel Select 0 : VIP_PARSER A and B channels operate in single channel mode 1 : VIP_PARSER A and B channels directly drive VPDMA (multi-channel case) Multi-Channel means that the A and B sources are from multiple channels and used in a multiplexed stream mode. The VIP Parser extracts the channel ID from each source and outputs this information to VPDMA, and thus to memory. When operating in a multiplexed stream mode, this bit must be set to 1 to enable the channel information to be passed to memory. If this is not set, the channel number (or source number) will be 0 for all streams. If vip2_rgb_out_select = 1, then VIP_PARSER A port is connected to VPDMA" "0,1" textline " " bitfld.long 0x0 16. " VIP2_CHR_DS_1_BYPASS ,Video Input Port 2 Chroma Downsampler 1 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" bitfld.long 0x0 17. " VIP2_CHR_DS_2_BYPASS ,Video Input Port 2 Chroma Downsampler 2 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" textline " " hexmask.long.byte 0x0 18.--25. 1. " RESERVED ," bitfld.long 0x0 26. " VIP2_TESTPORT_B_SELECT ,0 : Normal mode 1: Test Mode" "0,1" textline " " bitfld.long 0x0 27. " VIP2_TESTPORT_A_SELECT ,0 : Normal mode 1: Test Mode" "0,1" bitfld.long 0x0 28.--31. " VIP2_DATAPATH_SELECT ,VIP2 Datapath Register Field Enable 0000 : All fields written 0001 : Only vip2_csc_src_select written 0010 : Only vip2_sc_src_select written 0011 : Only vip2_rgb_src_select written 0100 : Only vip2_rgb_out_lo_select written 0101 : Only vip2_rgb_out_hi_select written 0110 : Only vip2_chr_ds_1_src_select written 0111 : Only vip2_chr_ds_2_src_select written 1000 : Only vip2_multi_channel_select written 1001 : Only vip2_chr_ds_1_bypass written 1010 : Only vip2_chr_ds_2_bypass written 1011 : Reserved 1100 : Reserved 1101 : Reserved 1110 : Reserved 1111 : Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "VIP2_top_level" base ad:0x48990000 width 28. group.byte 0x0++0x3 line.long 0x0 "VIP_CLKC_PID,This register follows the format described in PDR3.5" bitfld.long 0x0 0.--5. " MINOR ,inor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Custom IP" "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " MAJOR ,ajor Release Number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNC ,The function of the module being used" bitfld.long 0x0 28.--29. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,The scheme of the register used. This indicates the PDR3.5 Method" "0,1,2,3" group.byte 0x10++0x3 line.long 0x0 "VIP_SYSCONFIG,VIP_SYSCONFIG" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state 0x0 : Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup mode, for debug only 0x1 : No-idle mode: local target never enters idle state. Backup mode, for debug only 0x2 : Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events 0x3 : Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state. Mode is only relevant if the appropriate IP module 'swakeup' output(s) is (are) implemented" "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state 0x0: Force-standby mode: local initiator is unconditionally placed in standby state. Backup mode, for debug only 0x1: No-standby mode: local initiator is unconditionally placed out of standby state. Backup mode, for debug only 0x2: Same behavior as bit-field value of 0x1. 0x3: Reserved" "0,1,2,3" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_RAW ,VPDMA INT0 List0 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_RAW ,VPDMA INT0 List0 Notify Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_RAW ,VPDMA INT0 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_RAW ,VPDMA INT0 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_RAW ,VPDMA INT0 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_RAW ,VPDMA INT0 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_RAW ,VPDMA INT0 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_RAW ,VPDMA INT0 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_RAW ,VPDMA INT0 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_RAW ,VPDMA INT0 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_RAW ,VPDMA INT0 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_RAW ,VPDMA INT0 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_RAW ,VPDMA INT0 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_RAW ,VPDMA INT0 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_RAW ,VPDMA INT0 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_RAW ,VPDMA INT0 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_RAW ,VPDMA INT0 Descriptor Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_RAW ,VIP1 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_RAW ,VIP2 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_RAW ,VPDMA INT0 Channel Group0 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_RAW ,VPDMA INT0 Channel Group1 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_RAW ,VPDMA INT0 Channel Group2 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_RAW ,VPDMA INT0 Channel Group3 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_RAW ,VPDMA INT0 Channel Group4 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_RAW ,VPDMA INT0 Channel Group5 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_RAW ,VPDMA INT0 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x28++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_ENA0,INTC INTR0 Interrupt Status Enabled/Clear Register 0. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA ,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA ,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA ,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA ,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA ,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA ,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA ,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA ,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA ,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA ,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA ,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA ,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA ,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA ,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA ,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA ,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA ,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA ,VIP1 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA ,VIP2 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_ENA1,INTC INTR0 Interrupt Status Enabled/Clear Register 1. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA ,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA ,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA ,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA ,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA ,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA ,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA ,VPDMA INT0 Client Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x30++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_SET0,INTC INTR0 Interrupt Enable/Set Register 0. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_SET ,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_SET ,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_SET ,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_SET ,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_SET ,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_SET ,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_SET ,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_SET ,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_SET ,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_SET ,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_SET ,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_SET ,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_SET ,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_SET ,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_SET ,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_SET ,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA_SET ,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_SET ,VIP1 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_SET ,VIP2 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_SET1,INTC INTR0 Interrupt Enable/Set Register 1. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_SET ,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_SET ,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_SET ,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_SET ,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_SET ,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_SET ,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_CHANNEL_GROUP6_ENA_SET ,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA_SET ,VPDMA INT0 Client Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x38++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_CLR ,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_CLR ,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_CLR ,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_CLR ,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_CLR ,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_CLR ,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_CLR ,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_CLR ,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_CLR ,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_CLR ,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_CLR ,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_CLR ,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_CLR ,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_CLR ,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_CLR ,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_CLR ,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA_CLR ,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_CLR ,VIP1 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_CLR ,VIP2 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR ,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA_CLR ,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x40++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_RAW0,INTC intr1 Interrupt Status Raw/Set Register 0. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_RAW ,VPDMA INT1 List0 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_RAW ,VPDMA INT1 List0 Notify Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_RAW ,VPDMA INT1 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_RAW ,VPDMA INT1 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_RAW ,VPDMA INT1 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_RAW ,VPDMA INT1 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_RAW ,VPDMA INT1 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_RAW ,VPDMA INT1 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_RAW ,VPDMA INT1 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_RAW ,VPDMA INT1 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_RAW ,VPDMA INT1 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_RAW ,VPDMA INT1 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_RAW ,VPDMA INT1 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_RAW ,VPDMA INT1 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_RAW ,VPDMA INT1 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_RAW ,VPDMA INT1 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_RAW ,VPDMA INT1 Descriptor Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_RAW ,VIP1 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_RAW ,VIP2 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_RAW1,INTC intr1 Interrupt Status Raw/Set Register 1. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_RAW ,VPDMA INT1 Channel Group0 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_RAW ,VPDMA INT1 Channel Group1 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_RAW ,VPDMA INT1 Channel Group2 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_RAW ,VPDMA INT1 Channel Group3 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_RAW ,VPDMA INT1 Channel Group4 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_RAW ,VPDMA INT1 Channel Group5 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_RAW ,VPDMA INT1 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x48++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_ENA0,INTC intr1 Interrupt Status Enabled/Clear Register 0. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_ENA ,VPDMA INT1 List0 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_ENA ,VPDMA INT1 List0 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_ENA ,VPDMA INT1 List1 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_ENA ,VPDMA INT1 List1 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_ENA ,VPDMA INT1 List2 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_ENA ,VPDMA INT1 List2 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_ENA ,VPDMA INT1 List3 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_ENA ,VPDMA INT1 List3 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_ENA ,VPDMA INT1 List4 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_ENA ,VPDMA INT1 List4 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_ENA ,VPDMA INT1 List5 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_ENA ,VPDMA INT1 List5 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_ENA ,VPDMA INT1 List6 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_ENA ,VPDMA INT1 List6 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_ENA ,VPDMA INT1 List7 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_ENA ,VPDMA INT1 List7 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_ENA ,VPDMA INT1 Descriptor Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA ,VIP1 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA ,VIP2 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_ENA1,INTC intr1 Interrupt Status Enabled/Clear Register 1. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_ENA ,VPDMA INT1 Channel Group0 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_ENA ,VPDMA INT1 Channel Group1 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_ENA ,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_ENA ,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_ENA ,VPDMA INT1 Channel Group4 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_ENA ,VPDMA INT1 Channel Group5 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_ENA ,VPDMA INT1 Client Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x50++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_SET0,INTC intr1 Interrupt Enable/Set Register 0. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_ENA_SET ,VPDMA INT1 List0 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_ENA_SET ,VPDMA INT1 List0 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_ENA_SET ,VPDMA INT1 List1 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_ENA_SET ,VPDMA INT1 List1 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_ENA_SET ,VPDMA INT1 List2 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_ENA_SET ,VPDMA INT1 List2 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_ENA_SET ,VPDMA INT1 List3 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_ENA_SET ,VPDMA INT1 List3 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_ENA_SET ,VPDMA INT1 List4 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_ENA_SET ,VPDMA INT1 List4 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_ENA_SET ,VPDMA INT1 List5 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_ENA_SET ,VPDMA INT1 List5 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_ENA_SET ,VPDMA INT1 List6 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_ENA_SET ,VPDMA INT1 List6 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_ENA_SET ,VPDMA INT1 List7 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_ENA_SET ,VPDMA INT1 List7 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_ENA_SET ,VPDMA INT1 Descriptor Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_SET ,VIP1 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_SET ,VIP2 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_SET1,INTC intr1 Interrupt Enable/Set Register 1. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_ENA_SET ,VPDMA INT1 Channel Group0 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_ENA_SET ,VPDMA INT1 Channel Group1 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_ENA_SET ,VPDMA INT1 Channel Group2 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_ENA_SET ,VPDMA INT1 Channel Group3 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_ENA_SET ,VPDMA INT1 Channel Group4 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_ENA_SET ,VPDMA INT1 Channel Group5 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_CHANNEL_GROUP6_ENA_SET ,VPDMA INT1 Channel Group6 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_ENA_SET ,VPDMA INT1 Client Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x58++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_CLR0,INTC intr1 Interrupt Enable/Clear Register 0. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_ENA_CLR ,VPDMA INT1 List0 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_ENA_CLR ,VPDMA INT1 List0 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_ENA_CLR ,VPDMA INT1 List1 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_ENA_CLR ,VPDMA INT1 List1 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_ENA_CLR ,VPDMA INT1 List2 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_ENA_CLR ,VPDMA INT1 List2 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_ENA_CLR ,VPDMA INT1 List3 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_ENA_CLR ,VPDMA INT1 List3 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_ENA_CLR ,VPDMA INT1 List4 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_ENA_CLR ,VPDMA INT1 List4 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_ENA_CLR ,VPDMA INT1 List5 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_ENA_CLR ,VPDMA INT1 List5 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_ENA_CLR ,VPDMA INT1 List6 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_ENA_CLR ,VPDMA INT1 List6 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_ENA_CLR ,VPDMA INT1 List7 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_ENA_CLR ,VPDMA INT1 List7 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_ENA_CLR ,VPDMA INT1 Descriptor Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_CLR ,VIP1 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_CLR ,VIP2 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_CLR1,INTC intr1 Interrupt Enable/Clear Register 1. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT1 Channel Group0 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT1 Channel Group1 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT1 Channel Group2 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT1 Channel Group3 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT1 Channel Group4 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT1 Channel Group5 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_CHANNEL_GROUP6_ENA_CLR ,VPDMA INT1 Channel Group6 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_ENA_CLR ,VPDMA INT1 Client Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xA0++0x3 line.long 0x0 "VIP_INTC_EOI,INTC EOI Register. This register contains the EOI vector register contents as defined by HL0.8" hexmask.long 0x0 0.--31. 1. " EOI_VECTOR ,Number associated with the ipgenericirq for intr output. There are 4 interrupt outputs Write 0x0 : Write to intr0 IP Generic Write 0x1 : Write to intr1 IP Generic Write 0x2 : Write to intr2 IP Generic Write 0x3 : Write to intr3 IP Generic Any other write value is ignored." group.byte 0x100++0x3 line.long 0x0 "VIP_CLKC_CLKEN,CLKC Module Clock Enable Register. This register contains clock enables for the processing paths in the VIP module." bitfld.long 0x0 0. " VPDMA_EN ,VPDMA Clock Enable, 1 = Clock Enabled, 0 = Clock Disabled" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIP1_DP_EN ,VIP Slice0 Data Path Clock Enable, 1 = Clock Enabled, 0 = Clock Disabled" "0,1" bitfld.long 0x0 17. " VIP2_DP_EN ,VIP Slice1 Data Path Clock Enable, 1 = Clock Enabled, 0 = Clock Disabled" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "VIP_CLKC_RST,CLKC Module Reset Register. This register contains resets for the processing paths in the VIP module." bitfld.long 0x0 0. " VPDMA_RST ,VPDMA Reset" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " VIP1_DP_RST ,VIP Slice0 Data Path Reset" "0,1" bitfld.long 0x0 17. " VIP2_DP_RST ,VIP Slice1 Data Path Reset" "0,1" textline " " bitfld.long 0x0 18. " S0_PARSER_RST ,VIP Slice0 parser reset" "0,1" bitfld.long 0x0 19. " S1_PARSER_RST ,VIP Slice1 parser reset" "0,1" textline " " bitfld.long 0x0 20. " S0_CSC_RST ,VIP Slice0 CSC reset" "0,1" bitfld.long 0x0 21. " S1_CSC_RST ,VIP Slice1 CSC reset" "0,1" textline " " bitfld.long 0x0 22. " S0_SC_RST ,VIP Slice0 SC reset" "0,1" bitfld.long 0x0 23. " S1_SC_RST ,VIP Slice1 SC reset" "0,1" textline " " bitfld.long 0x0 24. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 25. " S0_CHR_DS_0_RST ,VIP Slice0 CHRDS0 reset" "0,1" textline " " bitfld.long 0x0 26. " S1_CHR_DS_0_RST ,VIP Slice1 CHRDS0 reset" "0,1" bitfld.long 0x0 27. " S0_CHR_DS_1_RST ,VIP Slice0 CHRDS1 reset" "0,1" textline " " bitfld.long 0x0 28. " S1_CHR_DS_1_RST ,VIP Slice1 CHRDS1 reset" "0,1" bitfld.long 0x0 29.--30. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 31. " MAIN_RST ,Reset for all modules in VIP Main Data Path" "0,1" group.byte 0x108++0x3 line.long 0x0 "VIP_CLKC_DPS,CLKC Main Data Path Select Register. This register selects the various data paths within main portion (non-VIP) of the subsystem" bitfld.long 0x0 0. " VPDMA_RST ,VPDMA Reset" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIP1_DP_RST ,Video Input Port 1 Data Path Reset" "0,1" bitfld.long 0x0 17. " VIP2_DP_RST ,Video Input Port 2 Data Path Reset" "0,1" textline " " hexmask.long.word 0x0 18.--30. 1. " RESERVED ," bitfld.long 0x0 31. " MAIN_RST ,Reset for all modules in DSS Main Data Path" "0,1" group.byte 0x10C++0x3 line.long 0x0 "VIP_CLKC_VIP0DPS,CLKC Video Input Port 1 Data Path Select Register. This register selects the various data paths within the Video Input Port portion of the subsystem" bitfld.long 0x0 0.--2. " VIP1_CSC_SRC_SELECT ,Video Input Port 1 CSC Source Select 000 : Path Disabled 001 : Source from VIP_PARSER A (422) port 010 : Source from VIP_PARSER B port 011 : Source from Transcode (422) 100 : Source from VIP_PARSER A (RGB) port 101 : Source from Compositor (RGB) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " VIP1_SC_SRC_SELECT ,Video Input Port 1 SC_M Source Select 000 : Path Disabled 001 : Source from Color Space Converter (CSC) 010 : Source from VIP_PARSER A port 011 : Source from VIP_PARSER B port 100 : Source from Transcode (422) 101 : Reserved 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6. " VIP1_RGB_SRC_SELECT ,Video Input Port 1 RGB Output Path Select 0 : Source from Compositor RGB input 1 : Source from CSC" "0,1" bitfld.long 0x0 7. " VIP1_RGB_OUT_LO_SELECT ,Video Input Port 1 LO RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" textline " " bitfld.long 0x0 8. " VIP1_RGB_OUT_HI_SELECT ,Video Input Port 1 HI RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" bitfld.long 0x0 9.--11. " VIP1_CHR_DS_1_SRC_SELECT ,Video Input Port 1 Chroma Downsampler 1 Source Select 000 : Path Disabled (no input to CHR_DS) 001 : Source from Scaler (SC_M) 010 : Source from Color Space Converter (CSC) 011 : Source from VIP_PARSER A port 100 : Source from VIP_PARSER B port 101 : Source from Transcode (422) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12.--14. " VIP1_CHR_DS_2_SRC_SELECT ,Video Input Port 1 Chroma Downsampler 2 Source Select 0 : Path Disabled (no input to CHR_DS) 1 : Source from Scaler (SC_M) 2 : Source from Color Space Converter (CSC) 3 : Source from VIP_PARSER A port 4 : Source from VIP_PARSER B port 5 : Source from Transcode (422) 6 : Reserved 7 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " VIP1_MULTI_CHANNEL_SELECT ,Video Input Port 1 Multi Channel Select 0 : VIP_PARSER A and B channels operate in single channel mode 1 : VIP_PARSER A and B channels directly drive VPDMA (multi-channel case) Multi-Channel means that the A and B sources are from multiple channels and used in a multiplexed stream mode. The VIP Parser extracts the channel ID from each source and outputs this information to VPDMA, and thus to memory. When operating in a multiplexed stream mode, this bit must be set to 1 to enable the channel information to be passed to memory. If this is not set, the channel number (or source number) will be 0 for all streams. If vip1_rgb_out_select = 1, then VIP_PARSER A port is connected to VPDMA" "0,1" textline " " bitfld.long 0x0 16. " VIP1_CHR_DS_1_BYPASS ,Video Input Port 1 Chroma Downsampler 1 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" bitfld.long 0x0 17. " VIP1_CHR_DS_2_BYPASS ,Video Input Port 1 Chroma Downsampler 2 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" textline " " hexmask.long.byte 0x0 18.--25. 1. " RESERVED ," bitfld.long 0x0 26. " VIP1_TESTPORT_B_SELECT ,0 : Normal mode 1: Test Mode" "0,1" textline " " bitfld.long 0x0 27. " VIP1_TESTPORT_A_SELECT ,0 : Normal mode 1: Test Mode" "0,1" bitfld.long 0x0 28.--31. " VIP1_DATAPATH_SELECT ,VIP1 Datapath Register Field Enable 0000 : All fields written 0001 : Only vip1_csc_src_select written 0010 : Only vip1_sc_src_select written 0011 : Only vip1_rgb_src_select written 0100 : Only vip1_rgb_out_lo_select written 0101 : Only vip1_rgb_out_hi_select written 0110 : Only vip1_chr_ds_1_src_select written 0111 : Only vip1_chr_ds_2_src_select written 1000 : Only vip1_multi_channel_select written 1001 : Only vip1_chr_ds_1_bypass written 1010 : Only vip1_chr_ds_2_bypass written 1011 : Reserved 1100 : Reserved 1101 : Reserved 1110 : Reserved 1111 : Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x110++0x3 line.long 0x0 "VIP_CLKC_VIP1DPS,CLKC Video Input Port 2 Data Path Select Register. This register selects the various data paths within the Video Input Port portion of the subsystem" bitfld.long 0x0 0.--2. " VIP2_CSC_SRC_SELECT ,Video Input Port 2 CSC Source Select 000 : Path Disabled 001 : Source from VIP_PARSER A (422) port 010 : Source from VIP_PARSER B port 011 : Source from Transcode (422) 100 : Source from VIP_PARSER A (RGB) port 101 : Source from Compositor (RGB) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " VIP2_SC_SRC_SELECT ,Video Input Port 2 SC_M Source Select 000 : Path Disabled 001 : Source from Color Space Converter (CSC) 010 : Source from VIP_PARSER A port 011 : Source from VIP_PARSER B port 100 : Source from Transcode (422) 101 : Reserved 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6. " VIP2_RGB_SRC_SELECT ,Video Input Port 2 RGB Output Path Select 0 : Source from Compositor RGB input 1 : Source from CSC" "0,1" bitfld.long 0x0 7. " VIP2_RGB_OUT_LO_SELECT ,Video Input Port 2 LO RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" textline " " bitfld.long 0x0 8. " VIP2_RGB_OUT_HI_SELECT ,Video Input Port 2 HI RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" bitfld.long 0x0 9.--11. " VIP2_CHR_DS_1_SRC_SELECT ,Video Input Port 2 Chroma Downsampler 1 Source Select 000 : Path Disabled (no input to CHR_DS) 001 : Source from Scaler (SC_M) 010 : Source from Color Space Converter (CSC) 011 : Source from VIP_PARSER A port 100 : Source from VIP_PARSER B port 101 : Source from Transcode (422) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12.--14. " VIP2_CHR_DS_2_SRC_SELECT ,Video Input Port 2 Chroma Downsampler 2 Source Select 0 : Path Disabled (no input to CHR_DS) 1 : Source from Scaler (SC_M) 2 : Source from Color Space Converter (CSC) 3 : Source from VIP_PARSER A port 4 : Source from VIP_PARSER B port 5 : Source from Transcode (422) 6 : Reserved 7 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " VIP2_MULTI_CHANNEL_SELECT ,Video Input Port 2 Multi Channel Select 0 : VIP_PARSER A and B channels operate in single channel mode 1 : VIP_PARSER A and B channels directly drive VPDMA (multi-channel case) Multi-Channel means that the A and B sources are from multiple channels and used in a multiplexed stream mode. The VIP Parser extracts the channel ID from each source and outputs this information to VPDMA, and thus to memory. When operating in a multiplexed stream mode, this bit must be set to 1 to enable the channel information to be passed to memory. If this is not set, the channel number (or source number) will be 0 for all streams. If vip2_rgb_out_select = 1, then VIP_PARSER A port is connected to VPDMA" "0,1" textline " " bitfld.long 0x0 16. " VIP2_CHR_DS_1_BYPASS ,Video Input Port 2 Chroma Downsampler 1 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" bitfld.long 0x0 17. " VIP2_CHR_DS_2_BYPASS ,Video Input Port 2 Chroma Downsampler 2 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" textline " " hexmask.long.byte 0x0 18.--25. 1. " RESERVED ," bitfld.long 0x0 26. " VIP2_TESTPORT_B_SELECT ,0 : Normal mode 1: Test Mode" "0,1" textline " " bitfld.long 0x0 27. " VIP2_TESTPORT_A_SELECT ,0 : Normal mode 1: Test Mode" "0,1" bitfld.long 0x0 28.--31. " VIP2_DATAPATH_SELECT ,VIP2 Datapath Register Field Enable 0000 : All fields written 0001 : Only vip2_csc_src_select written 0010 : Only vip2_sc_src_select written 0011 : Only vip2_rgb_src_select written 0100 : Only vip2_rgb_out_lo_select written 0101 : Only vip2_rgb_out_hi_select written 0110 : Only vip2_chr_ds_1_src_select written 0111 : Only vip2_chr_ds_2_src_select written 1000 : Only vip2_multi_channel_select written 1001 : Only vip2_chr_ds_1_bypass written 1010 : Only vip2_chr_ds_2_bypass written 1011 : Reserved 1100 : Reserved 1101 : Reserved 1110 : Reserved 1111 : Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "VIP3_top_level" base ad:0x489B0000 width 28. group.byte 0x0++0x3 line.long 0x0 "VIP_CLKC_PID,This register follows the format described in PDR3.5" bitfld.long 0x0 0.--5. " MINOR ,inor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Custom IP" "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " MAJOR ,ajor Release Number" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNC ,The function of the module being used" bitfld.long 0x0 28.--29. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,The scheme of the register used. This indicates the PDR3.5 Method" "0,1,2,3" group.byte 0x10++0x3 line.long 0x0 "VIP_SYSCONFIG,VIP_SYSCONFIG" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state 0x0 : Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup mode, for debug only 0x1 : No-idle mode: local target never enters idle state. Backup mode, for debug only 0x2 : Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events 0x3 : Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state. Mode is only relevant if the appropriate IP module 'swakeup' output(s) is (are) implemented" "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state 0x0: Force-standby mode: local initiator is unconditionally placed in standby state. Backup mode, for debug only 0x1: No-standby mode: local initiator is unconditionally placed out of standby state. Backup mode, for debug only 0x2: Same behavior as bit-field value of 0x1. 0x3: Reserved" "0,1,2,3" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_RAW0,INTC INTR0 Interrupt Status Raw/Set Register 0. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_RAW ,VPDMA INT0 List0 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_RAW ,VPDMA INT0 List0 Notify Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_RAW ,VPDMA INT0 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_RAW ,VPDMA INT0 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_RAW ,VPDMA INT0 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_RAW ,VPDMA INT0 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_RAW ,VPDMA INT0 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_RAW ,VPDMA INT0 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_RAW ,VPDMA INT0 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_RAW ,VPDMA INT0 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_RAW ,VPDMA INT0 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_RAW ,VPDMA INT0 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_RAW ,VPDMA INT0 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_RAW ,VPDMA INT0 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_RAW ,VPDMA INT0 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_RAW ,VPDMA INT0 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_RAW ,VPDMA INT0 Descriptor Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_RAW ,VIP1 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_RAW ,VIP2 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_RAW1,INTC INTR0 Interrupt Status Raw/Set Register 1. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_RAW ,VPDMA INT0 Channel Group0 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_RAW ,VPDMA INT0 Channel Group1 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_RAW ,VPDMA INT0 Channel Group2 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_RAW ,VPDMA INT0 Channel Group3 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_RAW ,VPDMA INT0 Channel Group4 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_RAW ,VPDMA INT0 Channel Group5 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_RAW ,VPDMA INT0 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x28++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_ENA0,INTC INTR0 Interrupt Status Enabled/Clear Register 0. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA ,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA ,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA ,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA ,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA ,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA ,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA ,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA ,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA ,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA ,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA ,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA ,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA ,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA ,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA ,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA ,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA ,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA ,VIP1 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA ,VIP2 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "VIP_INTC_INTR0_STATUS_ENA1,INTC INTR0 Interrupt Status Enabled/Clear Register 1. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA ,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA ,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA ,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA ,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA ,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA ,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA ,VPDMA INT0 Client Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x30++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_SET0,INTC INTR0 Interrupt Enable/Set Register 0. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_SET ,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_SET ,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_SET ,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_SET ,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_SET ,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_SET ,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_SET ,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_SET ,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_SET ,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_SET ,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_SET ,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_SET ,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_SET ,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_SET ,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_SET ,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_SET ,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA_SET ,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_SET ,VIP1 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_SET ,VIP2 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_SET1,INTC INTR0 Interrupt Enable/Set Register 1. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_SET ,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_SET ,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_SET ,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_SET ,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_SET ,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_SET ,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_CHANNEL_GROUP6_ENA_SET ,VPDMA INT0 Channel Group6 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA_SET ,VPDMA INT0 Client Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x38++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_CLR0,INTC INTR0 Interrupt Enable/Clear Register 0. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_CLR ,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_CLR ,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_CLR ,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_CLR ,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_CLR ,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_CLR ,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_CLR ,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_CLR ,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_CLR ,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_CLR ,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_CLR ,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_CLR ,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_CLR ,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_CLR ,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_CLR ,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_CLR ,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA_CLR ,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_CLR ,VIP1 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_CLR ,VIP2 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "VIP_INTC_INTR0_ENA_CLR1,INTC INTR0 Interrupt Enable/Clear Register 1. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_CHANNEL_GROUP6_ENA_CLR ,VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA_CLR ,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x40++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_RAW0,INTC intr1 Interrupt Status Raw/Set Register 0. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_RAW ,VPDMA INT1 List0 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_RAW ,VPDMA INT1 List0 Notify Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_RAW ,VPDMA INT1 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_RAW ,VPDMA INT1 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_RAW ,VPDMA INT1 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_RAW ,VPDMA INT1 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_RAW ,VPDMA INT1 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_RAW ,VPDMA INT1 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_RAW ,VPDMA INT1 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_RAW ,VPDMA INT1 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_RAW ,VPDMA INT1 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_RAW ,VPDMA INT1 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_RAW ,VPDMA INT1 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_RAW ,VPDMA INT1 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_RAW ,VPDMA INT1 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_RAW ,VPDMA INT1 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_RAW ,VPDMA INT1 Descriptor Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_RAW ,VIP1 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_RAW ,VIP2 Parser Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_RAW1,INTC intr1 Interrupt Status Raw/Set Register 1. This register contains the raw interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_RAW ,VPDMA INT1 Channel Group0 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_RAW ,VPDMA INT1 Channel Group1 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_RAW ,VPDMA INT1 Channel Group2 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_RAW ,VPDMA INT1 Channel Group3 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_RAW ,VPDMA INT1 Channel Group4 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_RAW ,VPDMA INT1 Channel Group5 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_RAW ,VPDMA INT1 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_RAW ,VIP2 Chroma Downsampler 2 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x48++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_ENA0,INTC intr1 Interrupt Status Enabled/Clear Register 0. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_ENA ,VPDMA INT1 List0 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_ENA ,VPDMA INT1 List0 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_ENA ,VPDMA INT1 List1 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_ENA ,VPDMA INT1 List1 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_ENA ,VPDMA INT1 List2 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_ENA ,VPDMA INT1 List2 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_ENA ,VPDMA INT1 List3 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_ENA ,VPDMA INT1 List3 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_ENA ,VPDMA INT1 List4 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_ENA ,VPDMA INT1 List4 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_ENA ,VPDMA INT1 List5 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_ENA ,VPDMA INT1 List5 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_ENA ,VPDMA INT1 List6 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_ENA ,VPDMA INT1 List6 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_ENA ,VPDMA INT1 List7 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_ENA ,VPDMA INT1 List7 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_ENA ,VPDMA INT1 Descriptor Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA ,VIP1 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA ,VIP2 Parser Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "VIP_INTC_INTR1_STATUS_ENA1,INTC intr1 Interrupt Status Enabled/Clear Register 1. This register contains the enabled interrupt status as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_ENA ,VPDMA INT1 Channel Group0 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_ENA ,VPDMA INT1 Channel Group1 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_ENA ,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_ENA ,VPDMA INT1 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_ENA ,VPDMA INT1 Channel Group4 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_ENA ,VPDMA INT1 Channel Group5 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_ENA ,VPDMA INT1 Client Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA ,VIP2 Chroma Downsampler 2 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x50++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_SET0,INTC intr1 Interrupt Enable/Set Register 0. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_ENA_SET ,VPDMA INT1 List0 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_ENA_SET ,VPDMA INT1 List0 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_ENA_SET ,VPDMA INT1 List1 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_ENA_SET ,VPDMA INT1 List1 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_ENA_SET ,VPDMA INT1 List2 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_ENA_SET ,VPDMA INT1 List2 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_ENA_SET ,VPDMA INT1 List3 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_ENA_SET ,VPDMA INT1 List3 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_ENA_SET ,VPDMA INT1 List4 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_ENA_SET ,VPDMA INT1 List4 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_ENA_SET ,VPDMA INT1 List5 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_ENA_SET ,VPDMA INT1 List5 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_ENA_SET ,VPDMA INT1 List6 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_ENA_SET ,VPDMA INT1 List6 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_ENA_SET ,VPDMA INT1 List7 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_ENA_SET ,VPDMA INT1 List7 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_ENA_SET ,VPDMA INT1 Descriptor Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_SET ,VIP1 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_SET ,VIP2 Parser Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_SET1,INTC intr1 Interrupt Enable/Set Register 1. This register contains the interrupt enable status/set as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_ENA_SET ,VPDMA INT1 Channel Group0 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_ENA_SET ,VPDMA INT1 Channel Group1 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_ENA_SET ,VPDMA INT1 Channel Group2 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_ENA_SET ,VPDMA INT1 Channel Group3 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_ENA_SET ,VPDMA INT1 Channel Group4 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_ENA_SET ,VPDMA INT1 Channel Group5 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_CHANNEL_GROUP6_ENA_SET ,VPDMA INT1 Channel Group6 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_ENA_SET ,VPDMA INT1 Client Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_SET ,VIP2 Chroma Downsampler 2 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x58++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_CLR0,INTC intr1 Interrupt Enable/Clear Register 0. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_LIST0_COMPLETE_ENA_CLR ,VPDMA INT1 List0 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_LIST0_NOTIFY_ENA_CLR ,VPDMA INT1 List0 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_LIST1_COMPLETE_ENA_CLR ,VPDMA INT1 List1 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_LIST1_NOTIFY_ENA_CLR ,VPDMA INT1 List1 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_LIST2_COMPLETE_ENA_CLR ,VPDMA INT1 List2 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_LIST2_NOTIFY_ENA_CLR ,VPDMA INT1 List2 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_LIST3_COMPLETE_ENA_CLR ,VPDMA INT1 List3 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_LIST3_NOTIFY_ENA_CLR ,VPDMA INT1 List3 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT1_LIST4_COMPLETE_ENA_CLR ,VPDMA INT1 List4 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT1_LIST4_NOTIFY_ENA_CLR ,VPDMA INT1 List4 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT1_LIST5_COMPLETE_ENA_CLR ,VPDMA INT1 List5 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT1_LIST5_NOTIFY_ENA_CLR ,VPDMA INT1 List5 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT1_LIST6_COMPLETE_ENA_CLR ,VPDMA INT1 List6 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT1_LIST6_NOTIFY_ENA_CLR ,VPDMA INT1 List6 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT1_LIST7_COMPLETE_ENA_CLR ,VPDMA INT1 List7 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT1_LIST7_NOTIFY_ENA_CLR ,VPDMA INT1 List7 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT1_DESCRIPTOR_ENA_CLR ,VPDMA INT1 Descriptor Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " VIP1_PARSER_INT_ENA_CLR ,VIP1 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 21. " VIP2_PARSER_INT_ENA_CLR ,VIP2 Parser Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "VIP_INTC_INTR1_ENA_CLR1,INTC intr1 Interrupt Enable/Clear Register 1. This register contains the interrupt enable status/clear as defined in HL0.8" bitfld.long 0x0 0. " VPDMA_INT1_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT1 Channel Group0 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT1_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT1 Channel Group1 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT1_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT1 Channel Group2 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT1_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT1 Channel Group3 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT1_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT1 Channel Group4 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT1_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT1 Channel Group5 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT1_CHANNEL_GROUP6_ENA_CLR ,VPDMA INT1 Channel Group6 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT1_CLIENT_ENA_CLR ,VPDMA INT1 Client Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 23. " VIP1_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 24. " VIP2_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 25. " VIP2_CHR_DS_2_UV_ERR_INT_ENA_CLR ,VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xA0++0x3 line.long 0x0 "VIP_INTC_EOI,INTC EOI Register. This register contains the EOI vector register contents as defined by HL0.8" hexmask.long 0x0 0.--31. 1. " EOI_VECTOR ,Number associated with the ipgenericirq for intr output. There are 4 interrupt outputs Write 0x0 : Write to intr0 IP Generic Write 0x1 : Write to intr1 IP Generic Write 0x2 : Write to intr2 IP Generic Write 0x3 : Write to intr3 IP Generic Any other write value is ignored." group.byte 0x100++0x3 line.long 0x0 "VIP_CLKC_CLKEN,CLKC Module Clock Enable Register. This register contains clock enables for the processing paths in the VIP module." bitfld.long 0x0 0. " VPDMA_EN ,VPDMA Clock Enable, 1 = Clock Enabled, 0 = Clock Disabled" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIP1_DP_EN ,VIP Slice0 Data Path Clock Enable, 1 = Clock Enabled, 0 = Clock Disabled" "0,1" bitfld.long 0x0 17. " VIP2_DP_EN ,VIP Slice1 Data Path Clock Enable, 1 = Clock Enabled, 0 = Clock Disabled" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "VIP_CLKC_RST,CLKC Module Reset Register. This register contains resets for the processing paths in the VIP module." bitfld.long 0x0 0. " VPDMA_RST ,VPDMA Reset" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " VIP1_DP_RST ,VIP Slice0 Data Path Reset" "0,1" bitfld.long 0x0 17. " VIP2_DP_RST ,VIP Slice1 Data Path Reset" "0,1" textline " " bitfld.long 0x0 18. " S0_PARSER_RST ,VIP Slice0 parser reset" "0,1" bitfld.long 0x0 19. " S1_PARSER_RST ,VIP Slice1 parser reset" "0,1" textline " " bitfld.long 0x0 20. " S0_CSC_RST ,VIP Slice0 CSC reset" "0,1" bitfld.long 0x0 21. " S1_CSC_RST ,VIP Slice1 CSC reset" "0,1" textline " " bitfld.long 0x0 22. " S0_SC_RST ,VIP Slice0 SC reset" "0,1" bitfld.long 0x0 23. " S1_SC_RST ,VIP Slice1 SC reset" "0,1" textline " " bitfld.long 0x0 24. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 25. " S0_CHR_DS_0_RST ,VIP Slice0 CHRDS0 reset" "0,1" textline " " bitfld.long 0x0 26. " S1_CHR_DS_0_RST ,VIP Slice1 CHRDS0 reset" "0,1" bitfld.long 0x0 27. " S0_CHR_DS_1_RST ,VIP Slice0 CHRDS1 reset" "0,1" textline " " bitfld.long 0x0 28. " S1_CHR_DS_1_RST ,VIP Slice1 CHRDS1 reset" "0,1" bitfld.long 0x0 29.--30. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 31. " MAIN_RST ,Reset for all modules in VIP Main Data Path" "0,1" group.byte 0x108++0x3 line.long 0x0 "VIP_CLKC_DPS,CLKC Main Data Path Select Register. This register selects the various data paths within main portion (non-VIP) of the subsystem" bitfld.long 0x0 0. " VPDMA_RST ,VPDMA Reset" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIP1_DP_RST ,Video Input Port 1 Data Path Reset" "0,1" bitfld.long 0x0 17. " VIP2_DP_RST ,Video Input Port 2 Data Path Reset" "0,1" textline " " hexmask.long.word 0x0 18.--30. 1. " RESERVED ," bitfld.long 0x0 31. " MAIN_RST ,Reset for all modules in DSS Main Data Path" "0,1" group.byte 0x10C++0x3 line.long 0x0 "VIP_CLKC_VIP0DPS,CLKC Video Input Port 1 Data Path Select Register. This register selects the various data paths within the Video Input Port portion of the subsystem" bitfld.long 0x0 0.--2. " VIP1_CSC_SRC_SELECT ,Video Input Port 1 CSC Source Select 000 : Path Disabled 001 : Source from VIP_PARSER A (422) port 010 : Source from VIP_PARSER B port 011 : Source from Transcode (422) 100 : Source from VIP_PARSER A (RGB) port 101 : Source from Compositor (RGB) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " VIP1_SC_SRC_SELECT ,Video Input Port 1 SC_M Source Select 000 : Path Disabled 001 : Source from Color Space Converter (CSC) 010 : Source from VIP_PARSER A port 011 : Source from VIP_PARSER B port 100 : Source from Transcode (422) 101 : Reserved 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6. " VIP1_RGB_SRC_SELECT ,Video Input Port 1 RGB Output Path Select 0 : Source from Compositor RGB input 1 : Source from CSC" "0,1" bitfld.long 0x0 7. " VIP1_RGB_OUT_LO_SELECT ,Video Input Port 1 LO RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" textline " " bitfld.long 0x0 8. " VIP1_RGB_OUT_HI_SELECT ,Video Input Port 1 HI RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" bitfld.long 0x0 9.--11. " VIP1_CHR_DS_1_SRC_SELECT ,Video Input Port 1 Chroma Downsampler 1 Source Select 000 : Path Disabled (no input to CHR_DS) 001 : Source from Scaler (SC_M) 010 : Source from Color Space Converter (CSC) 011 : Source from VIP_PARSER A port 100 : Source from VIP_PARSER B port 101 : Source from Transcode (422) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12.--14. " VIP1_CHR_DS_2_SRC_SELECT ,Video Input Port 1 Chroma Downsampler 2 Source Select 0 : Path Disabled (no input to CHR_DS) 1 : Source from Scaler (SC_M) 2 : Source from Color Space Converter (CSC) 3 : Source from VIP_PARSER A port 4 : Source from VIP_PARSER B port 5 : Source from Transcode (422) 6 : Reserved 7 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " VIP1_MULTI_CHANNEL_SELECT ,Video Input Port 1 Multi Channel Select 0 : VIP_PARSER A and B channels operate in single channel mode 1 : VIP_PARSER A and B channels directly drive VPDMA (multi-channel case) Multi-Channel means that the A and B sources are from multiple channels and used in a multiplexed stream mode. The VIP Parser extracts the channel ID from each source and outputs this information to VPDMA, and thus to memory. When operating in a multiplexed stream mode, this bit must be set to 1 to enable the channel information to be passed to memory. If this is not set, the channel number (or source number) will be 0 for all streams. If vip1_rgb_out_select = 1, then VIP_PARSER A port is connected to VPDMA" "0,1" textline " " bitfld.long 0x0 16. " VIP1_CHR_DS_1_BYPASS ,Video Input Port 1 Chroma Downsampler 1 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" bitfld.long 0x0 17. " VIP1_CHR_DS_2_BYPASS ,Video Input Port 1 Chroma Downsampler 2 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" textline " " hexmask.long.byte 0x0 18.--25. 1. " RESERVED ," bitfld.long 0x0 26. " VIP1_TESTPORT_B_SELECT ,0 : Normal mode 1: Test Mode" "0,1" textline " " bitfld.long 0x0 27. " VIP1_TESTPORT_A_SELECT ,0 : Normal mode 1: Test Mode" "0,1" bitfld.long 0x0 28.--31. " VIP1_DATAPATH_SELECT ,VIP1 Datapath Register Field Enable 0000 : All fields written 0001 : Only vip1_csc_src_select written 0010 : Only vip1_sc_src_select written 0011 : Only vip1_rgb_src_select written 0100 : Only vip1_rgb_out_lo_select written 0101 : Only vip1_rgb_out_hi_select written 0110 : Only vip1_chr_ds_1_src_select written 0111 : Only vip1_chr_ds_2_src_select written 1000 : Only vip1_multi_channel_select written 1001 : Only vip1_chr_ds_1_bypass written 1010 : Only vip1_chr_ds_2_bypass written 1011 : Reserved 1100 : Reserved 1101 : Reserved 1110 : Reserved 1111 : Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x110++0x3 line.long 0x0 "VIP_CLKC_VIP1DPS,CLKC Video Input Port 2 Data Path Select Register. This register selects the various data paths within the Video Input Port portion of the subsystem" bitfld.long 0x0 0.--2. " VIP2_CSC_SRC_SELECT ,Video Input Port 2 CSC Source Select 000 : Path Disabled 001 : Source from VIP_PARSER A (422) port 010 : Source from VIP_PARSER B port 011 : Source from Transcode (422) 100 : Source from VIP_PARSER A (RGB) port 101 : Source from Compositor (RGB) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " VIP2_SC_SRC_SELECT ,Video Input Port 2 SC_M Source Select 000 : Path Disabled 001 : Source from Color Space Converter (CSC) 010 : Source from VIP_PARSER A port 011 : Source from VIP_PARSER B port 100 : Source from Transcode (422) 101 : Reserved 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6. " VIP2_RGB_SRC_SELECT ,Video Input Port 2 RGB Output Path Select 0 : Source from Compositor RGB input 1 : Source from CSC" "0,1" bitfld.long 0x0 7. " VIP2_RGB_OUT_LO_SELECT ,Video Input Port 2 LO RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" textline " " bitfld.long 0x0 8. " VIP2_RGB_OUT_HI_SELECT ,Video Input Port 2 HI RGB Output Select 0 : Output Type is 420/422 1 : Output Type is RGB" "0,1" bitfld.long 0x0 9.--11. " VIP2_CHR_DS_1_SRC_SELECT ,Video Input Port 2 Chroma Downsampler 1 Source Select 000 : Path Disabled (no input to CHR_DS) 001 : Source from Scaler (SC_M) 010 : Source from Color Space Converter (CSC) 011 : Source from VIP_PARSER A port 100 : Source from VIP_PARSER B port 101 : Source from Transcode (422) 110 : Reserved 111 : Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12.--14. " VIP2_CHR_DS_2_SRC_SELECT ,Video Input Port 2 Chroma Downsampler 2 Source Select 0 : Path Disabled (no input to CHR_DS) 1 : Source from Scaler (SC_M) 2 : Source from Color Space Converter (CSC) 3 : Source from VIP_PARSER A port 4 : Source from VIP_PARSER B port 5 : Source from Transcode (422) 6 : Reserved 7 : Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " VIP2_MULTI_CHANNEL_SELECT ,Video Input Port 2 Multi Channel Select 0 : VIP_PARSER A and B channels operate in single channel mode 1 : VIP_PARSER A and B channels directly drive VPDMA (multi-channel case) Multi-Channel means that the A and B sources are from multiple channels and used in a multiplexed stream mode. The VIP Parser extracts the channel ID from each source and outputs this information to VPDMA, and thus to memory. When operating in a multiplexed stream mode, this bit must be set to 1 to enable the channel information to be passed to memory. If this is not set, the channel number (or source number) will be 0 for all streams. If vip2_rgb_out_select = 1, then VIP_PARSER A port is connected to VPDMA" "0,1" textline " " bitfld.long 0x0 16. " VIP2_CHR_DS_1_BYPASS ,Video Input Port 2 Chroma Downsampler 1 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" bitfld.long 0x0 17. " VIP2_CHR_DS_2_BYPASS ,Video Input Port 2 Chroma Downsampler 2 Bypass 0 : VIP Chroma Downsampler 1 selected 1 : VIP Chroma Downsampler 1 Bypassed Chroma Downsampler Bypassed means the output format from the VIP will be 422 data. Selected means the output format will be 420" "0,1" textline " " hexmask.long.byte 0x0 18.--25. 1. " RESERVED ," bitfld.long 0x0 26. " VIP2_TESTPORT_B_SELECT ,0 : Normal mode 1: Test Mode" "0,1" textline " " bitfld.long 0x0 27. " VIP2_TESTPORT_A_SELECT ,0 : Normal mode 1: Test Mode" "0,1" bitfld.long 0x0 28.--31. " VIP2_DATAPATH_SELECT ,VIP2 Datapath Register Field Enable 0000 : All fields written 0001 : Only vip2_csc_src_select written 0010 : Only vip2_sc_src_select written 0011 : Only vip2_rgb_src_select written 0100 : Only vip2_rgb_out_lo_select written 0101 : Only vip2_rgb_out_hi_select written 0110 : Only vip2_chr_ds_1_src_select written 0111 : Only vip2_chr_ds_2_src_select written 1000 : Only vip2_multi_channel_select written 1001 : Only vip2_chr_ds_1_bypass written 1010 : Only vip2_chr_ds_2_bypass written 1011 : Reserved 1100 : Reserved 1101 : Reserved 1110 : Reserved 1111 : Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "VIP1_Slice0_csc" base ad:0x48975700 width 11. group.byte 0x0++0x3 line.long 0x0 "VIP_CSC00,VIP_CSC00" hexmask.long.word 0x0 0.--12. 1. " A0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. Rules for converting a real number coefficient to a 12-bit hex number for this register: - If the real number is positive, then simply multiply it by 1024, and convert the integer part to hex format. For example, 0.673 X 1024 = 689.152, then 0x2B1 should fill in to this register - If the real number is negative, then multiply it by 1024, and convert it to 2's compliment format in 12-bit. For example, if a coefficient is -1.893, by *1024 to this number, it becomes -1938. The 2'S compliment format of -1938 is 0x186E (in 13-bit width). Then 0x186E should be the number assigned to this register." bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x4++0x3 line.long 0x0 "VIP_CSC01,VIP_CSC01" hexmask.long.word 0x0 0.--12. 1. " C0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " A1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x8++0x3 line.long 0x0 "VIP_CSC02,VIP_CSC02" hexmask.long.word 0x0 0.--12. 1. " B1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " C1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0xC++0x3 line.long 0x0 "VIP_CSC03,VIP_CSC03" hexmask.long.word 0x0 0.--12. 1. " A2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x10++0x3 line.long 0x0 "VIP_CSC04,VIP_CSC04" hexmask.long.word 0x0 0.--12. 1. " C2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--27. 1. " D0 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. For example, if this coefficient is 749, then 0x2ED (hex format) should be assigned to this register. Another example, if this coefficient is -1021, then 0xC03 should be assigned to this register." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_CSC05,VIP_CSC05" hexmask.long.word 0x0 0.--11. 1. " D1 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " D2 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 28. " BYPASS ,Full CSC bypass mode" "0,1" textline " " bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "VIP1_Slice1_csc" base ad:0x48975C00 width 11. group.byte 0x0++0x3 line.long 0x0 "VIP_CSC00,VIP_CSC00" hexmask.long.word 0x0 0.--12. 1. " A0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. Rules for converting a real number coefficient to a 12-bit hex number for this register: - If the real number is positive, then simply multiply it by 1024, and convert the integer part to hex format. For example, 0.673 X 1024 = 689.152, then 0x2B1 should fill in to this register - If the real number is negative, then multiply it by 1024, and convert it to 2's compliment format in 12-bit. For example, if a coefficient is -1.893, by *1024 to this number, it becomes -1938. The 2'S compliment format of -1938 is 0x186E (in 13-bit width). Then 0x186E should be the number assigned to this register." bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x4++0x3 line.long 0x0 "VIP_CSC01,VIP_CSC01" hexmask.long.word 0x0 0.--12. 1. " C0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " A1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x8++0x3 line.long 0x0 "VIP_CSC02,VIP_CSC02" hexmask.long.word 0x0 0.--12. 1. " B1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " C1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0xC++0x3 line.long 0x0 "VIP_CSC03,VIP_CSC03" hexmask.long.word 0x0 0.--12. 1. " A2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x10++0x3 line.long 0x0 "VIP_CSC04,VIP_CSC04" hexmask.long.word 0x0 0.--12. 1. " C2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--27. 1. " D0 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. For example, if this coefficient is 749, then 0x2ED (hex format) should be assigned to this register. Another example, if this coefficient is -1021, then 0xC03 should be assigned to this register." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_CSC05,VIP_CSC05" hexmask.long.word 0x0 0.--11. 1. " D1 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " D2 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 28. " BYPASS ,Full CSC bypass mode" "0,1" textline " " bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "VIP2_Slice0_csc" base ad:0x48995700 width 11. group.byte 0x0++0x3 line.long 0x0 "VIP_CSC00,VIP_CSC00" hexmask.long.word 0x0 0.--12. 1. " A0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. Rules for converting a real number coefficient to a 12-bit hex number for this register: - If the real number is positive, then simply multiply it by 1024, and convert the integer part to hex format. For example, 0.673 X 1024 = 689.152, then 0x2B1 should fill in to this register - If the real number is negative, then multiply it by 1024, and convert it to 2's compliment format in 12-bit. For example, if a coefficient is -1.893, by *1024 to this number, it becomes -1938. The 2'S compliment format of -1938 is 0x186E (in 13-bit width). Then 0x186E should be the number assigned to this register." bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x4++0x3 line.long 0x0 "VIP_CSC01,VIP_CSC01" hexmask.long.word 0x0 0.--12. 1. " C0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " A1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x8++0x3 line.long 0x0 "VIP_CSC02,VIP_CSC02" hexmask.long.word 0x0 0.--12. 1. " B1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " C1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0xC++0x3 line.long 0x0 "VIP_CSC03,VIP_CSC03" hexmask.long.word 0x0 0.--12. 1. " A2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x10++0x3 line.long 0x0 "VIP_CSC04,VIP_CSC04" hexmask.long.word 0x0 0.--12. 1. " C2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--27. 1. " D0 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. For example, if this coefficient is 749, then 0x2ED (hex format) should be assigned to this register. Another example, if this coefficient is -1021, then 0xC03 should be assigned to this register." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_CSC05,VIP_CSC05" hexmask.long.word 0x0 0.--11. 1. " D1 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " D2 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 28. " BYPASS ,Full CSC bypass mode" "0,1" textline " " bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "VIP2_Slice1_csc" base ad:0x48995C00 width 11. group.byte 0x0++0x3 line.long 0x0 "VIP_CSC00,VIP_CSC00" hexmask.long.word 0x0 0.--12. 1. " A0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. Rules for converting a real number coefficient to a 12-bit hex number for this register: - If the real number is positive, then simply multiply it by 1024, and convert the integer part to hex format. For example, 0.673 X 1024 = 689.152, then 0x2B1 should fill in to this register - If the real number is negative, then multiply it by 1024, and convert it to 2's compliment format in 12-bit. For example, if a coefficient is -1.893, by *1024 to this number, it becomes -1938. The 2'S compliment format of -1938 is 0x186E (in 13-bit width). Then 0x186E should be the number assigned to this register." bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x4++0x3 line.long 0x0 "VIP_CSC01,VIP_CSC01" hexmask.long.word 0x0 0.--12. 1. " C0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " A1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x8++0x3 line.long 0x0 "VIP_CSC02,VIP_CSC02" hexmask.long.word 0x0 0.--12. 1. " B1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " C1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0xC++0x3 line.long 0x0 "VIP_CSC03,VIP_CSC03" hexmask.long.word 0x0 0.--12. 1. " A2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x10++0x3 line.long 0x0 "VIP_CSC04,VIP_CSC04" hexmask.long.word 0x0 0.--12. 1. " C2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--27. 1. " D0 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. For example, if this coefficient is 749, then 0x2ED (hex format) should be assigned to this register. Another example, if this coefficient is -1021, then 0xC03 should be assigned to this register." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_CSC05,VIP_CSC05" hexmask.long.word 0x0 0.--11. 1. " D1 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " D2 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 28. " BYPASS ,Full CSC bypass mode" "0,1" textline " " bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "VIP3_Slice0_csc" base ad:0x489B5700 width 11. group.byte 0x0++0x3 line.long 0x0 "VIP_CSC00,VIP_CSC00" hexmask.long.word 0x0 0.--12. 1. " A0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. Rules for converting a real number coefficient to a 12-bit hex number for this register: - If the real number is positive, then simply multiply it by 1024, and convert the integer part to hex format. For example, 0.673 X 1024 = 689.152, then 0x2B1 should fill in to this register - If the real number is negative, then multiply it by 1024, and convert it to 2's compliment format in 12-bit. For example, if a coefficient is -1.893, by *1024 to this number, it becomes -1938. The 2'S compliment format of -1938 is 0x186E (in 13-bit width). Then 0x186E should be the number assigned to this register." bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x4++0x3 line.long 0x0 "VIP_CSC01,VIP_CSC01" hexmask.long.word 0x0 0.--12. 1. " C0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " A1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x8++0x3 line.long 0x0 "VIP_CSC02,VIP_CSC02" hexmask.long.word 0x0 0.--12. 1. " B1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " C1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0xC++0x3 line.long 0x0 "VIP_CSC03,VIP_CSC03" hexmask.long.word 0x0 0.--12. 1. " A2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x10++0x3 line.long 0x0 "VIP_CSC04,VIP_CSC04" hexmask.long.word 0x0 0.--12. 1. " C2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--27. 1. " D0 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. For example, if this coefficient is 749, then 0x2ED (hex format) should be assigned to this register. Another example, if this coefficient is -1021, then 0xC03 should be assigned to this register." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_CSC05,VIP_CSC05" hexmask.long.word 0x0 0.--11. 1. " D1 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " D2 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 28. " BYPASS ,Full CSC bypass mode" "0,1" textline " " bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "VIP3_Slice1_csc" base ad:0x489B5C00 width 11. group.byte 0x0++0x3 line.long 0x0 "VIP_CSC00,VIP_CSC00" hexmask.long.word 0x0 0.--12. 1. " A0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. Rules for converting a real number coefficient to a 12-bit hex number for this register: - If the real number is positive, then simply multiply it by 1024, and convert the integer part to hex format. For example, 0.673 X 1024 = 689.152, then 0x2B1 should fill in to this register - If the real number is negative, then multiply it by 1024, and convert it to 2's compliment format in 12-bit. For example, if a coefficient is -1.893, by *1024 to this number, it becomes -1938. The 2'S compliment format of -1938 is 0x186E (in 13-bit width). Then 0x186E should be the number assigned to this register." bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x4++0x3 line.long 0x0 "VIP_CSC01,VIP_CSC01" hexmask.long.word 0x0 0.--12. 1. " C0 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " A1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x8++0x3 line.long 0x0 "VIP_CSC02,VIP_CSC02" hexmask.long.word 0x0 0.--12. 1. " B1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " C1 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0xC++0x3 line.long 0x0 "VIP_CSC03,VIP_CSC03" hexmask.long.word 0x0 0.--12. 1. " A2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x10++0x3 line.long 0x0 "VIP_CSC04,VIP_CSC04" hexmask.long.word 0x0 0.--12. 1. " C2 ,Coefficients of color space converter. This coefficient is a real number in the range of 4. The MSB is sign bit. (Same format conversion as A0)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--27. 1. " D0 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. For example, if this coefficient is 749, then 0x2ED (hex format) should be assigned to this register. Another example, if this coefficient is -1021, then 0xC03 should be assigned to this register." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_CSC05,VIP_CSC05" hexmask.long.word 0x0 0.--11. 1. " D1 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " D2 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0)" bitfld.long 0x0 28. " BYPASS ,Full CSC bypass mode" "0,1" textline " " bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "VIP1_Slice0_parser" base ad:0x48975500 width 30. group.byte 0x0++0x3 line.long 0x0 "VIP_MAIN,Main Configuration for VIP Parser" bitfld.long 0x0 0.--1. " DATA_INTERFACE_MODE ,00 = 24b Port A data interface. 01 = 16b Port A data interface. 10 = 8b Port A data interfaces. 11 = Undefined. Port B is always an 8b data interface." "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " CLIP_BLNK ,Discrete Sync Only; 0 = Do not clip Blanking Data; 1 = Clip Blanking Data as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" bitfld.long 0x0 5. " CLIP_ACTIVE ,Discrete Sync Only; 0 = Do not clip active pixels; 1 = Clip Active Pixels as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single 4:2:2 YUV stream 0001 = embedded sync 2x multiplexed 4:2:2 YUV stream 0010 = embedded sync 4x multiplexed 4:2:2 YUV stream 0011 = embedded sync line multiplexed 4:2:2 YUV stream 0100 = discrete sync single 4:2:2 YUV stream 0101 = embedded sync single RGB stream or single 444 YUV stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,Embedded Sync Only In 8b mode.. there is only one channel on data[7:0]. In 16b mode.. there are two channels. The Luma Channel is on data[15:8]. The Chroma Channel is on data[7:0]. In 24b mode.. there are three channels. The R channel is on data[23:16].. the G channel is on [15:8]. and the B channel is on data[7:0]. 00 = Use data[7:0] to extract control codes. 01 = Use data[15:8] to extract control codes. 10 = Use data[23:16] to extract control codes. 11 = Undefined In 16b and 24b modes.. this register is also used to select the channel from which Ancillary Data is extracted. The Ancillary Data channel must be the same as the control code channel. For 8b mode.. the anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable Port 1 = Enable Port" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port A logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x8++0x3 line.long 0x0 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_a_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_a_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--30. " REPACK_SEL ,000 = Straight Through 001 = Cross Swap 010 = Left Center Swap 011 = Center Right Swap 100 = Right Rotate 101 = Left Rotate 110 = RAW16 to RGB565 Mapping 111 = RAW12 Swap" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xC++0x3 line.long 0x0 "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single YUV stream 0001 = embedded sync 2x multiplexed YUV stream 0010 = embedded sync 4x multiplexed YUV stream 0011 = embedded sync line multiplexed YUV stream 0100 = discrete sync single YUV stream 0101 = embedded sync single RGB stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,PORT B supports on 8b mode. Always write 0 to this field. The anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable 1 = Enable" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port B logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x10++0x3 line.long 0x0 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_b_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_b_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x0 0. " PRTA_VDET_MASK ,Port A Video Detect FIQ Mask" "0,1" bitfld.long 0x0 1. " PRTB_VDET_MASK ,Port B Video Detect FIQ Mask" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_OF ,Port A Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_OF ,Port B Async FIFO Overflow FIQ Mask" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_OF ,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_OF ,Output FIFO Port A Ancillary Overflow Mask" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_OF ,Output FIFO Port B Luma Overflow Mask" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_OF ,Output FIFO Port B Ancillary Overflow Mask" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN ,Port A Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN ,Port A Link Disconnect Scrnum 0 Mask" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN ,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN ,Port B Link Disconnect Srcnum 0 Mask" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE ,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE ,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION_MASK ,Port A YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION_MASK ,Port A ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION_MASK ,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION_MASK ,Port B ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE_MASK ,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_MASK ,Port B Cfg Disable Complete Mask" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x0 0. " PRTA_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_CLR ,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_CLR ,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_CLR ,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_CLR ,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_CLR ,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_CLR ,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_A_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x0 0. " PRTA_VDET_STATUS ,VDET Status for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_STATUS ,VDET Status for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_STATUS ,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_STATUS ,Async FIFO Port B Overflow Status" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_LUMA_STATUS ,Output FIFO Port A Luma Overflow Status" "0,1" bitfld.long 0x0 5. " OUTPUT_FIFO_PRTA_CHROMA_STATUS ,Output FIFO Port A Chroma Overflow Status" "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_STATUS ,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_LUMA_STATUS ,Output FIFO Port B Luma Overflow Status" "0,1" textline " " bitfld.long 0x0 8. " OUTPUT_FIFO_PRTB_CHROMA_STATUS ,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_STATUS ,Output FIFO Port B Ancillary Overflow Status" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_STATUS ,Port A Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_STATUS ,Port A Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_STATUS ,Port B Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_STATUS ,Port B Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_STATUS ,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_STATUS ,Port B Source 0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION ,Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION ,Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION ,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION ,Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE ,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Current Field" "0,1" group.byte 0x24++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Current Field" "0,1" group.byte 0x28++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_SOURCE_FID ,For Source ID 11. from Port B Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Current Field" "0,1" group.byte 0x2C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Current Field" "0,1" group.byte 0x30++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC0_HEIGHT ,On Port A. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC0_WIDTH ,On Port A. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x34++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC1_HEIGHT ,On Port A. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC1_WIDTH ,On Port A. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x38++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC2_HEIGHT ,On Port A. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC2_WIDTH ,On Port A. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x3C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC3_HEIGHT ,On Port A. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC3_WIDTH ,On Port A. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x40++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC4_HEIGHT ,On Port A. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC4_WIDTH ,On Port A. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC5_HEIGHT ,On Port A. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC5_WIDTH ,On Port A. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x48++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC6_HEIGHT ,On Port A. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC6_WIDTH ,On Port A. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x4C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC7_HEIGHT ,On Port A. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC7_WIDTH ,On Port A. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x50++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC8_HEIGHT ,On Port A. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC8_WIDTH ,On Port A. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x54++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC9_HEIGHT ,On Port A. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC9_WIDTH ,On Port A. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x58++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC10_HEIGHT ,On Port A. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC10_WIDTH ,On Port A. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x5C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC11_HEIGHT ,On Port A. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC11_WIDTH ,On Port A. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x60++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC12_HEIGHT ,On Port A. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC12_WIDTH ,On Port A. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC13_HEIGHT ,On Port A. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC13_WIDTH ,On Port A. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x68++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC14_HEIGHT ,On Port A. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC14_WIDTH ,On Port A. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x6C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC15_HEIGHT ,On Port A. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC15_WIDTH ,On Port A. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x70++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC0_HEIGHT ,On Port B. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC0_WIDTH ,On Port B. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x74++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC1_HEIGHT ,On Port B. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC1_WIDTH ,On Port B. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x78++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC2_HEIGHT ,On Port B. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC2_WIDTH ,On Port B. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x7C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC3_HEIGHT ,On Port B. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC3_WIDTH ,On Port B. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x80++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC4_HEIGHT ,On Port B. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC4_WIDTH ,On Port B. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x84++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC5_HEIGHT ,On Port B. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC5_WIDTH ,On Port B. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x88++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC6_HEIGHT ,On Port B. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC6_WIDTH ,On Port B. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC7_HEIGHT ,On Port B. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC7_WIDTH ,On Port B. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x90++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC8_HEIGHT ,On Port B. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC8_WIDTH ,On Port B. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x94++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC9_HEIGHT ,On Port B. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC9_WIDTH ,On Port B. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x98++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC10_HEIGHT ,On Port B. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC10_WIDTH ,On Port B. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x9C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC11_HEIGHT ,On Port B. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC11_WIDTH ,On Port B. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA0++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC12_HEIGHT ,On Port B. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC12_WIDTH ,On Port B. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA4++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC13_HEIGHT ,On Port B. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC13_WIDTH ,On Port B. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA8++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC14_HEIGHT ,On Port B. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC14_WIDTH ,On Port B. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xAC++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC15_HEIGHT ,On Port B. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC15_WIDTH ,On Port B. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xB0++0x3 line.long 0x0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTA_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port A for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB4++0x3 line.long 0x0 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTB_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port B for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB8++0x3 line.long 0x0 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBC++0x3 line.long 0x0 "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's ancillary data region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping.. the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC8++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xCC++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnums active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xDC++0x3 line.long 0x0 "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xE0++0x3 line.long 0x0 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." group.byte 0xE4++0x3 line.long 0x0 "VIP_XTRA9_PORT_B,Reserved Register for Port B" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." width 0x0B tree.end tree "VIP1_Slice1_parser" base ad:0x48975A00 width 30. group.byte 0x0++0x3 line.long 0x0 "VIP_MAIN,Main Configuration for VIP Parser" bitfld.long 0x0 0.--1. " DATA_INTERFACE_MODE ,00 = 24b Port A data interface. 01 = 16b Port A data interface. 10 = 8b Port A data interfaces. 11 = Undefined. Port B is always an 8b data interface." "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " CLIP_BLNK ,Discrete Sync Only; 0 = Do not clip Blanking Data; 1 = Clip Blanking Data as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" bitfld.long 0x0 5. " CLIP_ACTIVE ,Discrete Sync Only; 0 = Do not clip active pixels; 1 = Clip Active Pixels as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single 4:2:2 YUV stream 0001 = embedded sync 2x multiplexed 4:2:2 YUV stream 0010 = embedded sync 4x multiplexed 4:2:2 YUV stream 0011 = embedded sync line multiplexed 4:2:2 YUV stream 0100 = discrete sync single 4:2:2 YUV stream 0101 = embedded sync single RGB stream or single 444 YUV stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,Embedded Sync Only In 8b mode.. there is only one channel on data[7:0]. In 16b mode.. there are two channels. The Luma Channel is on data[15:8]. The Chroma Channel is on data[7:0]. In 24b mode.. there are three channels. The R channel is on data[23:16].. the G channel is on [15:8]. and the B channel is on data[7:0]. 00 = Use data[7:0] to extract control codes. 01 = Use data[15:8] to extract control codes. 10 = Use data[23:16] to extract control codes. 11 = Undefined In 16b and 24b modes.. this register is also used to select the channel from which Ancillary Data is extracted. The Ancillary Data channel must be the same as the control code channel. For 8b mode.. the anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable Port 1 = Enable Port" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port A logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x8++0x3 line.long 0x0 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_a_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_a_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--30. " REPACK_SEL ,000 = Straight Through 001 = Cross Swap 010 = Left Center Swap 011 = Center Right Swap 100 = Right Rotate 101 = Left Rotate 110 = RAW16 to RGB565 Mapping 111 = RAW12 Swap" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xC++0x3 line.long 0x0 "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single YUV stream 0001 = embedded sync 2x multiplexed YUV stream 0010 = embedded sync 4x multiplexed YUV stream 0011 = embedded sync line multiplexed YUV stream 0100 = discrete sync single YUV stream 0101 = embedded sync single RGB stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,PORT B supports on 8b mode. Always write 0 to this field. The anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable 1 = Enable" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port B logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x10++0x3 line.long 0x0 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_b_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_b_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x0 0. " PRTA_VDET_MASK ,Port A Video Detect FIQ Mask" "0,1" bitfld.long 0x0 1. " PRTB_VDET_MASK ,Port B Video Detect FIQ Mask" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_OF ,Port A Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_OF ,Port B Async FIFO Overflow FIQ Mask" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_OF ,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_OF ,Output FIFO Port A Ancillary Overflow Mask" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_OF ,Output FIFO Port B Luma Overflow Mask" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_OF ,Output FIFO Port B Ancillary Overflow Mask" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN ,Port A Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN ,Port A Link Disconnect Scrnum 0 Mask" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN ,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN ,Port B Link Disconnect Srcnum 0 Mask" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE ,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE ,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION_MASK ,Port A YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION_MASK ,Port A ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION_MASK ,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION_MASK ,Port B ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE_MASK ,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_MASK ,Port B Cfg Disable Complete Mask" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x0 0. " PRTA_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_CLR ,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_CLR ,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_CLR ,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_CLR ,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_CLR ,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_CLR ,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_A_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x0 0. " PRTA_VDET_STATUS ,VDET Status for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_STATUS ,VDET Status for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_STATUS ,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_STATUS ,Async FIFO Port B Overflow Status" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_LUMA_STATUS ,Output FIFO Port A Luma Overflow Status" "0,1" bitfld.long 0x0 5. " OUTPUT_FIFO_PRTA_CHROMA_STATUS ,Output FIFO Port A Chroma Overflow Status" "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_STATUS ,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_LUMA_STATUS ,Output FIFO Port B Luma Overflow Status" "0,1" textline " " bitfld.long 0x0 8. " OUTPUT_FIFO_PRTB_CHROMA_STATUS ,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_STATUS ,Output FIFO Port B Ancillary Overflow Status" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_STATUS ,Port A Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_STATUS ,Port A Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_STATUS ,Port B Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_STATUS ,Port B Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_STATUS ,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_STATUS ,Port B Source 0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION ,Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION ,Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION ,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION ,Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE ,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Current Field" "0,1" group.byte 0x24++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Current Field" "0,1" group.byte 0x28++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_SOURCE_FID ,For Source ID 11. from Port B Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Current Field" "0,1" group.byte 0x2C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Current Field" "0,1" group.byte 0x30++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC0_HEIGHT ,On Port A. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC0_WIDTH ,On Port A. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x34++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC1_HEIGHT ,On Port A. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC1_WIDTH ,On Port A. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x38++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC2_HEIGHT ,On Port A. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC2_WIDTH ,On Port A. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x3C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC3_HEIGHT ,On Port A. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC3_WIDTH ,On Port A. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x40++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC4_HEIGHT ,On Port A. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC4_WIDTH ,On Port A. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC5_HEIGHT ,On Port A. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC5_WIDTH ,On Port A. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x48++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC6_HEIGHT ,On Port A. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC6_WIDTH ,On Port A. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x4C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC7_HEIGHT ,On Port A. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC7_WIDTH ,On Port A. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x50++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC8_HEIGHT ,On Port A. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC8_WIDTH ,On Port A. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x54++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC9_HEIGHT ,On Port A. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC9_WIDTH ,On Port A. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x58++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC10_HEIGHT ,On Port A. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC10_WIDTH ,On Port A. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x5C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC11_HEIGHT ,On Port A. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC11_WIDTH ,On Port A. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x60++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC12_HEIGHT ,On Port A. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC12_WIDTH ,On Port A. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC13_HEIGHT ,On Port A. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC13_WIDTH ,On Port A. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x68++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC14_HEIGHT ,On Port A. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC14_WIDTH ,On Port A. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x6C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC15_HEIGHT ,On Port A. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC15_WIDTH ,On Port A. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x70++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC0_HEIGHT ,On Port B. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC0_WIDTH ,On Port B. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x74++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC1_HEIGHT ,On Port B. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC1_WIDTH ,On Port B. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x78++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC2_HEIGHT ,On Port B. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC2_WIDTH ,On Port B. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x7C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC3_HEIGHT ,On Port B. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC3_WIDTH ,On Port B. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x80++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC4_HEIGHT ,On Port B. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC4_WIDTH ,On Port B. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x84++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC5_HEIGHT ,On Port B. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC5_WIDTH ,On Port B. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x88++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC6_HEIGHT ,On Port B. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC6_WIDTH ,On Port B. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC7_HEIGHT ,On Port B. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC7_WIDTH ,On Port B. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x90++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC8_HEIGHT ,On Port B. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC8_WIDTH ,On Port B. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x94++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC9_HEIGHT ,On Port B. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC9_WIDTH ,On Port B. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x98++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC10_HEIGHT ,On Port B. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC10_WIDTH ,On Port B. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x9C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC11_HEIGHT ,On Port B. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC11_WIDTH ,On Port B. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA0++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC12_HEIGHT ,On Port B. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC12_WIDTH ,On Port B. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA4++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC13_HEIGHT ,On Port B. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC13_WIDTH ,On Port B. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA8++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC14_HEIGHT ,On Port B. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC14_WIDTH ,On Port B. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xAC++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC15_HEIGHT ,On Port B. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC15_WIDTH ,On Port B. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xB0++0x3 line.long 0x0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTA_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port A for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB4++0x3 line.long 0x0 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTB_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port B for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB8++0x3 line.long 0x0 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBC++0x3 line.long 0x0 "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's ancillary data region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping.. the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC8++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xCC++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnums active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xDC++0x3 line.long 0x0 "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xE0++0x3 line.long 0x0 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." group.byte 0xE4++0x3 line.long 0x0 "VIP_XTRA9_PORT_B,Reserved Register for Port B" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." width 0x0B tree.end tree "VIP2_Slice0_parser" base ad:0x48995500 width 30. group.byte 0x0++0x3 line.long 0x0 "VIP_MAIN,Main Configuration for VIP Parser" bitfld.long 0x0 0.--1. " DATA_INTERFACE_MODE ,00 = 24b Port A data interface. 01 = 16b Port A data interface. 10 = 8b Port A data interfaces. 11 = Undefined. Port B is always an 8b data interface." "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " CLIP_BLNK ,Discrete Sync Only; 0 = Do not clip Blanking Data; 1 = Clip Blanking Data as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" bitfld.long 0x0 5. " CLIP_ACTIVE ,Discrete Sync Only; 0 = Do not clip active pixels; 1 = Clip Active Pixels as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single 4:2:2 YUV stream 0001 = embedded sync 2x multiplexed 4:2:2 YUV stream 0010 = embedded sync 4x multiplexed 4:2:2 YUV stream 0011 = embedded sync line multiplexed 4:2:2 YUV stream 0100 = discrete sync single 4:2:2 YUV stream 0101 = embedded sync single RGB stream or single 444 YUV stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,Embedded Sync Only In 8b mode.. there is only one channel on data[7:0]. In 16b mode.. there are two channels. The Luma Channel is on data[15:8]. The Chroma Channel is on data[7:0]. In 24b mode.. there are three channels. The R channel is on data[23:16].. the G channel is on [15:8]. and the B channel is on data[7:0]. 00 = Use data[7:0] to extract control codes. 01 = Use data[15:8] to extract control codes. 10 = Use data[23:16] to extract control codes. 11 = Undefined In 16b and 24b modes.. this register is also used to select the channel from which Ancillary Data is extracted. The Ancillary Data channel must be the same as the control code channel. For 8b mode.. the anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable Port 1 = Enable Port" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port A logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x8++0x3 line.long 0x0 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_a_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_a_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--30. " REPACK_SEL ,000 = Straight Through 001 = Cross Swap 010 = Left Center Swap 011 = Center Right Swap 100 = Right Rotate 101 = Left Rotate 110 = RAW16 to RGB565 Mapping 111 = RAW12 Swap" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xC++0x3 line.long 0x0 "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single YUV stream 0001 = embedded sync 2x multiplexed YUV stream 0010 = embedded sync 4x multiplexed YUV stream 0011 = embedded sync line multiplexed YUV stream 0100 = discrete sync single YUV stream 0101 = embedded sync single RGB stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,PORT B supports on 8b mode. Always write 0 to this field. The anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable 1 = Enable" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port B logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x10++0x3 line.long 0x0 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_b_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_b_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x0 0. " PRTA_VDET_MASK ,Port A Video Detect FIQ Mask" "0,1" bitfld.long 0x0 1. " PRTB_VDET_MASK ,Port B Video Detect FIQ Mask" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_OF ,Port A Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_OF ,Port B Async FIFO Overflow FIQ Mask" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_OF ,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_OF ,Output FIFO Port A Ancillary Overflow Mask" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_OF ,Output FIFO Port B Luma Overflow Mask" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_OF ,Output FIFO Port B Ancillary Overflow Mask" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN ,Port A Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN ,Port A Link Disconnect Scrnum 0 Mask" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN ,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN ,Port B Link Disconnect Srcnum 0 Mask" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE ,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE ,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION_MASK ,Port A YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION_MASK ,Port A ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION_MASK ,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION_MASK ,Port B ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE_MASK ,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_MASK ,Port B Cfg Disable Complete Mask" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x0 0. " PRTA_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_CLR ,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_CLR ,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_CLR ,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_CLR ,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_CLR ,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_CLR ,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_A_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x0 0. " PRTA_VDET_STATUS ,VDET Status for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_STATUS ,VDET Status for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_STATUS ,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_STATUS ,Async FIFO Port B Overflow Status" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_LUMA_STATUS ,Output FIFO Port A Luma Overflow Status" "0,1" bitfld.long 0x0 5. " OUTPUT_FIFO_PRTA_CHROMA_STATUS ,Output FIFO Port A Chroma Overflow Status" "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_STATUS ,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_LUMA_STATUS ,Output FIFO Port B Luma Overflow Status" "0,1" textline " " bitfld.long 0x0 8. " OUTPUT_FIFO_PRTB_CHROMA_STATUS ,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_STATUS ,Output FIFO Port B Ancillary Overflow Status" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_STATUS ,Port A Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_STATUS ,Port A Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_STATUS ,Port B Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_STATUS ,Port B Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_STATUS ,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_STATUS ,Port B Source 0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION ,Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION ,Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION ,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION ,Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE ,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Current Field" "0,1" group.byte 0x24++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Current Field" "0,1" group.byte 0x28++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_SOURCE_FID ,For Source ID 11. from Port B Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Current Field" "0,1" group.byte 0x2C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Current Field" "0,1" group.byte 0x30++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC0_HEIGHT ,On Port A. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC0_WIDTH ,On Port A. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x34++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC1_HEIGHT ,On Port A. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC1_WIDTH ,On Port A. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x38++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC2_HEIGHT ,On Port A. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC2_WIDTH ,On Port A. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x3C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC3_HEIGHT ,On Port A. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC3_WIDTH ,On Port A. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x40++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC4_HEIGHT ,On Port A. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC4_WIDTH ,On Port A. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC5_HEIGHT ,On Port A. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC5_WIDTH ,On Port A. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x48++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC6_HEIGHT ,On Port A. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC6_WIDTH ,On Port A. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x4C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC7_HEIGHT ,On Port A. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC7_WIDTH ,On Port A. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x50++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC8_HEIGHT ,On Port A. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC8_WIDTH ,On Port A. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x54++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC9_HEIGHT ,On Port A. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC9_WIDTH ,On Port A. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x58++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC10_HEIGHT ,On Port A. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC10_WIDTH ,On Port A. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x5C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC11_HEIGHT ,On Port A. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC11_WIDTH ,On Port A. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x60++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC12_HEIGHT ,On Port A. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC12_WIDTH ,On Port A. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC13_HEIGHT ,On Port A. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC13_WIDTH ,On Port A. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x68++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC14_HEIGHT ,On Port A. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC14_WIDTH ,On Port A. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x6C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC15_HEIGHT ,On Port A. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC15_WIDTH ,On Port A. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x70++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC0_HEIGHT ,On Port B. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC0_WIDTH ,On Port B. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x74++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC1_HEIGHT ,On Port B. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC1_WIDTH ,On Port B. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x78++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC2_HEIGHT ,On Port B. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC2_WIDTH ,On Port B. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x7C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC3_HEIGHT ,On Port B. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC3_WIDTH ,On Port B. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x80++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC4_HEIGHT ,On Port B. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC4_WIDTH ,On Port B. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x84++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC5_HEIGHT ,On Port B. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC5_WIDTH ,On Port B. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x88++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC6_HEIGHT ,On Port B. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC6_WIDTH ,On Port B. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC7_HEIGHT ,On Port B. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC7_WIDTH ,On Port B. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x90++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC8_HEIGHT ,On Port B. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC8_WIDTH ,On Port B. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x94++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC9_HEIGHT ,On Port B. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC9_WIDTH ,On Port B. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x98++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC10_HEIGHT ,On Port B. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC10_WIDTH ,On Port B. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x9C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC11_HEIGHT ,On Port B. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC11_WIDTH ,On Port B. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA0++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC12_HEIGHT ,On Port B. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC12_WIDTH ,On Port B. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA4++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC13_HEIGHT ,On Port B. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC13_WIDTH ,On Port B. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA8++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC14_HEIGHT ,On Port B. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC14_WIDTH ,On Port B. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xAC++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC15_HEIGHT ,On Port B. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC15_WIDTH ,On Port B. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xB0++0x3 line.long 0x0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTA_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port A for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB4++0x3 line.long 0x0 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTB_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port B for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB8++0x3 line.long 0x0 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBC++0x3 line.long 0x0 "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's ancillary data region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping.. the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC8++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xCC++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnums active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xDC++0x3 line.long 0x0 "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xE0++0x3 line.long 0x0 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." group.byte 0xE4++0x3 line.long 0x0 "VIP_XTRA9_PORT_B,Reserved Register for Port B" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." width 0x0B tree.end tree "VIP2_Slice1_parser" base ad:0x48995A00 width 30. group.byte 0x0++0x3 line.long 0x0 "VIP_MAIN,Main Configuration for VIP Parser" bitfld.long 0x0 0.--1. " DATA_INTERFACE_MODE ,00 = 24b Port A data interface. 01 = 16b Port A data interface. 10 = 8b Port A data interfaces. 11 = Undefined. Port B is always an 8b data interface." "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " CLIP_BLNK ,Discrete Sync Only; 0 = Do not clip Blanking Data; 1 = Clip Blanking Data as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" bitfld.long 0x0 5. " CLIP_ACTIVE ,Discrete Sync Only; 0 = Do not clip active pixels; 1 = Clip Active Pixels as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single 4:2:2 YUV stream 0001 = embedded sync 2x multiplexed 4:2:2 YUV stream 0010 = embedded sync 4x multiplexed 4:2:2 YUV stream 0011 = embedded sync line multiplexed 4:2:2 YUV stream 0100 = discrete sync single 4:2:2 YUV stream 0101 = embedded sync single RGB stream or single 444 YUV stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,Embedded Sync Only In 8b mode.. there is only one channel on data[7:0]. In 16b mode.. there are two channels. The Luma Channel is on data[15:8]. The Chroma Channel is on data[7:0]. In 24b mode.. there are three channels. The R channel is on data[23:16].. the G channel is on [15:8]. and the B channel is on data[7:0]. 00 = Use data[7:0] to extract control codes. 01 = Use data[15:8] to extract control codes. 10 = Use data[23:16] to extract control codes. 11 = Undefined In 16b and 24b modes.. this register is also used to select the channel from which Ancillary Data is extracted. The Ancillary Data channel must be the same as the control code channel. For 8b mode.. the anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable Port 1 = Enable Port" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port A logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x8++0x3 line.long 0x0 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_a_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_a_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--30. " REPACK_SEL ,000 = Straight Through 001 = Cross Swap 010 = Left Center Swap 011 = Center Right Swap 100 = Right Rotate 101 = Left Rotate 110 = RAW16 to RGB565 Mapping 111 = RAW12 Swap" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xC++0x3 line.long 0x0 "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single YUV stream 0001 = embedded sync 2x multiplexed YUV stream 0010 = embedded sync 4x multiplexed YUV stream 0011 = embedded sync line multiplexed YUV stream 0100 = discrete sync single YUV stream 0101 = embedded sync single RGB stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,PORT B supports on 8b mode. Always write 0 to this field. The anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable 1 = Enable" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port B logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x10++0x3 line.long 0x0 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_b_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_b_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x0 0. " PRTA_VDET_MASK ,Port A Video Detect FIQ Mask" "0,1" bitfld.long 0x0 1. " PRTB_VDET_MASK ,Port B Video Detect FIQ Mask" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_OF ,Port A Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_OF ,Port B Async FIFO Overflow FIQ Mask" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_OF ,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_OF ,Output FIFO Port A Ancillary Overflow Mask" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_OF ,Output FIFO Port B Luma Overflow Mask" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_OF ,Output FIFO Port B Ancillary Overflow Mask" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN ,Port A Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN ,Port A Link Disconnect Scrnum 0 Mask" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN ,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN ,Port B Link Disconnect Srcnum 0 Mask" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE ,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE ,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION_MASK ,Port A YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION_MASK ,Port A ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION_MASK ,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION_MASK ,Port B ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE_MASK ,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_MASK ,Port B Cfg Disable Complete Mask" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x0 0. " PRTA_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_CLR ,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_CLR ,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_CLR ,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_CLR ,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_CLR ,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_CLR ,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_A_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x0 0. " PRTA_VDET_STATUS ,VDET Status for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_STATUS ,VDET Status for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_STATUS ,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_STATUS ,Async FIFO Port B Overflow Status" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_LUMA_STATUS ,Output FIFO Port A Luma Overflow Status" "0,1" bitfld.long 0x0 5. " OUTPUT_FIFO_PRTA_CHROMA_STATUS ,Output FIFO Port A Chroma Overflow Status" "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_STATUS ,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_LUMA_STATUS ,Output FIFO Port B Luma Overflow Status" "0,1" textline " " bitfld.long 0x0 8. " OUTPUT_FIFO_PRTB_CHROMA_STATUS ,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_STATUS ,Output FIFO Port B Ancillary Overflow Status" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_STATUS ,Port A Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_STATUS ,Port A Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_STATUS ,Port B Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_STATUS ,Port B Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_STATUS ,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_STATUS ,Port B Source 0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION ,Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION ,Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION ,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION ,Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE ,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Current Field" "0,1" group.byte 0x24++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Current Field" "0,1" group.byte 0x28++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_SOURCE_FID ,For Source ID 11. from Port B Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Current Field" "0,1" group.byte 0x2C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Current Field" "0,1" group.byte 0x30++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC0_HEIGHT ,On Port A. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC0_WIDTH ,On Port A. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x34++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC1_HEIGHT ,On Port A. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC1_WIDTH ,On Port A. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x38++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC2_HEIGHT ,On Port A. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC2_WIDTH ,On Port A. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x3C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC3_HEIGHT ,On Port A. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC3_WIDTH ,On Port A. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x40++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC4_HEIGHT ,On Port A. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC4_WIDTH ,On Port A. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC5_HEIGHT ,On Port A. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC5_WIDTH ,On Port A. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x48++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC6_HEIGHT ,On Port A. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC6_WIDTH ,On Port A. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x4C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC7_HEIGHT ,On Port A. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC7_WIDTH ,On Port A. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x50++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC8_HEIGHT ,On Port A. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC8_WIDTH ,On Port A. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x54++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC9_HEIGHT ,On Port A. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC9_WIDTH ,On Port A. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x58++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC10_HEIGHT ,On Port A. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC10_WIDTH ,On Port A. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x5C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC11_HEIGHT ,On Port A. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC11_WIDTH ,On Port A. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x60++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC12_HEIGHT ,On Port A. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC12_WIDTH ,On Port A. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC13_HEIGHT ,On Port A. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC13_WIDTH ,On Port A. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x68++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC14_HEIGHT ,On Port A. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC14_WIDTH ,On Port A. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x6C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC15_HEIGHT ,On Port A. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC15_WIDTH ,On Port A. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x70++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC0_HEIGHT ,On Port B. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC0_WIDTH ,On Port B. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x74++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC1_HEIGHT ,On Port B. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC1_WIDTH ,On Port B. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x78++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC2_HEIGHT ,On Port B. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC2_WIDTH ,On Port B. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x7C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC3_HEIGHT ,On Port B. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC3_WIDTH ,On Port B. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x80++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC4_HEIGHT ,On Port B. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC4_WIDTH ,On Port B. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x84++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC5_HEIGHT ,On Port B. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC5_WIDTH ,On Port B. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x88++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC6_HEIGHT ,On Port B. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC6_WIDTH ,On Port B. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC7_HEIGHT ,On Port B. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC7_WIDTH ,On Port B. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x90++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC8_HEIGHT ,On Port B. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC8_WIDTH ,On Port B. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x94++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC9_HEIGHT ,On Port B. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC9_WIDTH ,On Port B. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x98++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC10_HEIGHT ,On Port B. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC10_WIDTH ,On Port B. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x9C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC11_HEIGHT ,On Port B. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC11_WIDTH ,On Port B. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA0++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC12_HEIGHT ,On Port B. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC12_WIDTH ,On Port B. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA4++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC13_HEIGHT ,On Port B. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC13_WIDTH ,On Port B. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA8++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC14_HEIGHT ,On Port B. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC14_WIDTH ,On Port B. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xAC++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC15_HEIGHT ,On Port B. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC15_WIDTH ,On Port B. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xB0++0x3 line.long 0x0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTA_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port A for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB4++0x3 line.long 0x0 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTB_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port B for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB8++0x3 line.long 0x0 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBC++0x3 line.long 0x0 "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's ancillary data region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping.. the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC8++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xCC++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnums active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xDC++0x3 line.long 0x0 "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xE0++0x3 line.long 0x0 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." group.byte 0xE4++0x3 line.long 0x0 "VIP_XTRA9_PORT_B,Reserved Register for Port B" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." width 0x0B tree.end tree "VIP3_Slice0_parser" base ad:0x489B5500 width 30. group.byte 0x0++0x3 line.long 0x0 "VIP_MAIN,Main Configuration for VIP Parser" bitfld.long 0x0 0.--1. " DATA_INTERFACE_MODE ,00 = 24b Port A data interface. 01 = 16b Port A data interface. 10 = 8b Port A data interfaces. 11 = Undefined. Port B is always an 8b data interface." "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " CLIP_BLNK ,Discrete Sync Only; 0 = Do not clip Blanking Data; 1 = Clip Blanking Data as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" bitfld.long 0x0 5. " CLIP_ACTIVE ,Discrete Sync Only; 0 = Do not clip active pixels; 1 = Clip Active Pixels as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single 4:2:2 YUV stream 0001 = embedded sync 2x multiplexed 4:2:2 YUV stream 0010 = embedded sync 4x multiplexed 4:2:2 YUV stream 0011 = embedded sync line multiplexed 4:2:2 YUV stream 0100 = discrete sync single 4:2:2 YUV stream 0101 = embedded sync single RGB stream or single 444 YUV stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,Embedded Sync Only In 8b mode.. there is only one channel on data[7:0]. In 16b mode.. there are two channels. The Luma Channel is on data[15:8]. The Chroma Channel is on data[7:0]. In 24b mode.. there are three channels. The R channel is on data[23:16].. the G channel is on [15:8]. and the B channel is on data[7:0]. 00 = Use data[7:0] to extract control codes. 01 = Use data[15:8] to extract control codes. 10 = Use data[23:16] to extract control codes. 11 = Undefined In 16b and 24b modes.. this register is also used to select the channel from which Ancillary Data is extracted. The Ancillary Data channel must be the same as the control code channel. For 8b mode.. the anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable Port 1 = Enable Port" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port A logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x8++0x3 line.long 0x0 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_a_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_a_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--30. " REPACK_SEL ,000 = Straight Through 001 = Cross Swap 010 = Left Center Swap 011 = Center Right Swap 100 = Right Rotate 101 = Left Rotate 110 = RAW16 to RGB565 Mapping 111 = RAW12 Swap" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xC++0x3 line.long 0x0 "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single YUV stream 0001 = embedded sync 2x multiplexed YUV stream 0010 = embedded sync 4x multiplexed YUV stream 0011 = embedded sync line multiplexed YUV stream 0100 = discrete sync single YUV stream 0101 = embedded sync single RGB stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,PORT B supports on 8b mode. Always write 0 to this field. The anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable 1 = Enable" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port B logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x10++0x3 line.long 0x0 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_b_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_b_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x0 0. " PRTA_VDET_MASK ,Port A Video Detect FIQ Mask" "0,1" bitfld.long 0x0 1. " PRTB_VDET_MASK ,Port B Video Detect FIQ Mask" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_OF ,Port A Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_OF ,Port B Async FIFO Overflow FIQ Mask" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_OF ,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_OF ,Output FIFO Port A Ancillary Overflow Mask" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_OF ,Output FIFO Port B Luma Overflow Mask" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_OF ,Output FIFO Port B Ancillary Overflow Mask" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN ,Port A Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN ,Port A Link Disconnect Scrnum 0 Mask" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN ,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN ,Port B Link Disconnect Srcnum 0 Mask" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE ,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE ,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION_MASK ,Port A YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION_MASK ,Port A ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION_MASK ,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION_MASK ,Port B ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE_MASK ,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_MASK ,Port B Cfg Disable Complete Mask" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x0 0. " PRTA_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_CLR ,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_CLR ,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_CLR ,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_CLR ,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_CLR ,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_CLR ,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_A_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x0 0. " PRTA_VDET_STATUS ,VDET Status for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_STATUS ,VDET Status for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_STATUS ,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_STATUS ,Async FIFO Port B Overflow Status" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_LUMA_STATUS ,Output FIFO Port A Luma Overflow Status" "0,1" bitfld.long 0x0 5. " OUTPUT_FIFO_PRTA_CHROMA_STATUS ,Output FIFO Port A Chroma Overflow Status" "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_STATUS ,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_LUMA_STATUS ,Output FIFO Port B Luma Overflow Status" "0,1" textline " " bitfld.long 0x0 8. " OUTPUT_FIFO_PRTB_CHROMA_STATUS ,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_STATUS ,Output FIFO Port B Ancillary Overflow Status" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_STATUS ,Port A Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_STATUS ,Port A Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_STATUS ,Port B Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_STATUS ,Port B Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_STATUS ,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_STATUS ,Port B Source 0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION ,Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION ,Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION ,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION ,Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE ,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Current Field" "0,1" group.byte 0x24++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Current Field" "0,1" group.byte 0x28++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_SOURCE_FID ,For Source ID 11. from Port B Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Current Field" "0,1" group.byte 0x2C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Current Field" "0,1" group.byte 0x30++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC0_HEIGHT ,On Port A. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC0_WIDTH ,On Port A. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x34++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC1_HEIGHT ,On Port A. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC1_WIDTH ,On Port A. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x38++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC2_HEIGHT ,On Port A. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC2_WIDTH ,On Port A. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x3C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC3_HEIGHT ,On Port A. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC3_WIDTH ,On Port A. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x40++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC4_HEIGHT ,On Port A. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC4_WIDTH ,On Port A. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC5_HEIGHT ,On Port A. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC5_WIDTH ,On Port A. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x48++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC6_HEIGHT ,On Port A. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC6_WIDTH ,On Port A. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x4C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC7_HEIGHT ,On Port A. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC7_WIDTH ,On Port A. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x50++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC8_HEIGHT ,On Port A. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC8_WIDTH ,On Port A. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x54++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC9_HEIGHT ,On Port A. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC9_WIDTH ,On Port A. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x58++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC10_HEIGHT ,On Port A. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC10_WIDTH ,On Port A. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x5C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC11_HEIGHT ,On Port A. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC11_WIDTH ,On Port A. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x60++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC12_HEIGHT ,On Port A. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC12_WIDTH ,On Port A. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC13_HEIGHT ,On Port A. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC13_WIDTH ,On Port A. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x68++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC14_HEIGHT ,On Port A. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC14_WIDTH ,On Port A. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x6C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC15_HEIGHT ,On Port A. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC15_WIDTH ,On Port A. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x70++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC0_HEIGHT ,On Port B. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC0_WIDTH ,On Port B. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x74++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC1_HEIGHT ,On Port B. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC1_WIDTH ,On Port B. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x78++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC2_HEIGHT ,On Port B. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC2_WIDTH ,On Port B. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x7C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC3_HEIGHT ,On Port B. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC3_WIDTH ,On Port B. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x80++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC4_HEIGHT ,On Port B. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC4_WIDTH ,On Port B. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x84++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC5_HEIGHT ,On Port B. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC5_WIDTH ,On Port B. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x88++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC6_HEIGHT ,On Port B. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC6_WIDTH ,On Port B. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC7_HEIGHT ,On Port B. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC7_WIDTH ,On Port B. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x90++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC8_HEIGHT ,On Port B. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC8_WIDTH ,On Port B. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x94++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC9_HEIGHT ,On Port B. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC9_WIDTH ,On Port B. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x98++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC10_HEIGHT ,On Port B. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC10_WIDTH ,On Port B. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x9C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC11_HEIGHT ,On Port B. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC11_WIDTH ,On Port B. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA0++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC12_HEIGHT ,On Port B. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC12_WIDTH ,On Port B. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA4++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC13_HEIGHT ,On Port B. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC13_WIDTH ,On Port B. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA8++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC14_HEIGHT ,On Port B. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC14_WIDTH ,On Port B. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xAC++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC15_HEIGHT ,On Port B. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC15_WIDTH ,On Port B. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xB0++0x3 line.long 0x0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTA_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port A for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB4++0x3 line.long 0x0 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTB_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port B for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB8++0x3 line.long 0x0 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBC++0x3 line.long 0x0 "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's ancillary data region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping.. the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC8++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xCC++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnums active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xDC++0x3 line.long 0x0 "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xE0++0x3 line.long 0x0 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." group.byte 0xE4++0x3 line.long 0x0 "VIP_XTRA9_PORT_B,Reserved Register for Port B" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." width 0x0B tree.end tree "VIP3_Slice1_parser" base ad:0x489B5A00 width 30. group.byte 0x0++0x3 line.long 0x0 "VIP_MAIN,Main Configuration for VIP Parser" bitfld.long 0x0 0.--1. " DATA_INTERFACE_MODE ,00 = 24b Port A data interface. 01 = 16b Port A data interface. 10 = 8b Port A data interfaces. 11 = Undefined. Port B is always an 8b data interface." "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4. " CLIP_BLNK ,Discrete Sync Only; 0 = Do not clip Blanking Data; 1 = Clip Blanking Data as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" bitfld.long 0x0 5. " CLIP_ACTIVE ,Discrete Sync Only; 0 = Do not clip active pixels; 1 = Clip Active Pixels as follows: 0xFF -> 0xFE, 0x00 -> 0x01" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_PORT_A,Configuration for Input Port A" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single 4:2:2 YUV stream 0001 = embedded sync 2x multiplexed 4:2:2 YUV stream 0010 = embedded sync 4x multiplexed 4:2:2 YUV stream 0011 = embedded sync line multiplexed 4:2:2 YUV stream 0100 = discrete sync single 4:2:2 YUV stream 0101 = embedded sync single RGB stream or single 444 YUV stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,Embedded Sync Only In 8b mode.. there is only one channel on data[7:0]. In 16b mode.. there are two channels. The Luma Channel is on data[15:8]. The Chroma Channel is on data[7:0]. In 24b mode.. there are three channels. The R channel is on data[23:16].. the G channel is on [15:8]. and the B channel is on data[7:0]. 00 = Use data[7:0] to extract control codes. 01 = Use data[15:8] to extract control codes. 10 = Use data[23:16] to extract control codes. 11 = Undefined In 16b and 24b modes.. this register is also used to select the channel from which Ancillary Data is extracted. The Ancillary Data channel must be the same as the control code channel. For 8b mode.. the anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable Port 1 = Enable Port" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port A logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x8++0x3 line.long 0x0 "VIP_XTRA_PORT_A,ore Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_a_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_a_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--30. " REPACK_SEL ,000 = Straight Through 001 = Cross Swap 010 = Left Center Swap 011 = Center Right Swap 100 = Right Rotate 101 = Left Rotate 110 = RAW16 to RGB565 Mapping 111 = RAW12 Swap" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xC++0x3 line.long 0x0 "VIP_PORT_B,Configuration for Input Port B" bitfld.long 0x0 0.--3. " SYNC_TYPE ,0000 = embedded sync single YUV stream 0001 = embedded sync 2x multiplexed YUV stream 0010 = embedded sync 4x multiplexed YUV stream 0011 = embedded sync line multiplexed YUV stream 0100 = discrete sync single YUV stream 0101 = embedded sync single RGB stream 0110 = reserved 0111 = reserved 1000 = reserved 1001 = reserved 1010 = discrete sync single 24b RGB stream" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " CTRL_CHAN_SEL ,PORT B supports on 8b mode. Always write 0 to this field. The anc_chan_sel_8b register is used to select the Luma or Chroma channel from which Ancillary Data is taken." "0,1,2,3" textline " " bitfld.long 0x0 6. " CLR_ASYNC_FIFO_WR ,0 = Normal 1 = Clear Async FIFO Write Logic" "0,1" bitfld.long 0x0 7. " CLR_ASYNC_FIFO_RD ,0 = Normal 1 = Clear Async FIFO Read Logic" "0,1" textline " " bitfld.long 0x0 8. " ENABLE ,0 = Disable 1 = Enable" "0,1" bitfld.long 0x0 9. " FID_POLARITY ,0 = Keep FID as found 1 = Invert Determined Value of FID" "0,1" textline " " bitfld.long 0x0 10. " PIXCLK_EDGE_POLARITY ,0 = Rising Edge is active PIXCLK edge 1 = Falling Edge is active PIXCLK edge" "0,1" bitfld.long 0x0 11. " HSYNC_POLARITY ,Discrete Sync Only 0 = HSYNC is active low 1 = HSYNC is active high" "0,1" textline " " bitfld.long 0x0 12. " VSYNC_POLARITY ,Discrete Sync Only 0 = VSYNC is active low 1 = VSYNC is active high" "0,1" bitfld.long 0x0 13. " ACTVID_POLARITY ,Discrete Sync Only 0 = ACTVID is active low 1 = ACTVID is active high" "0,1" textline " " bitfld.long 0x0 14. " FID_DETECT_MODE ,Discrete Sync Only 0 = Take FID from pin 1 = FID is determined by VSYNC skew" "0,1" bitfld.long 0x0 15. " USE_ACTVID_HSYNC_N ,Discrete Sync Only 0 = Use HSYNC style line capture 1 = Use ACTVID style line capture" "0,1" textline " " bitfld.long 0x0 16.--21. " FID_SKEW_PRECOUNT ,Discrete Sync Only pre count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " DISCRETE_BASIC_MODE ,This register is valid for Discrete Sync mode only. 0 = Normal Discrete Mode. Hsync Style Capture operates as follows: - Captures line starting from HSYNC inactive to active condition. - VSYNC determined by sync window. - FID can be determined by VSYNC skew or captured from pin at first pixel in first line. ACTVID style capture works as follows: - Captures line during contiguous ACTVID envelope. - VSYNC is captured at the first pixel in each line. - FID is captured on first pixel of ACTVID window. 1 = Basic Discrete Mode. When using hsync with Hsync Style Capture operates as follows: - The last line of active video ends on the pixel clock cycle where VSYNC transitions from inactive to active. - FID pin value is captured on this cycle and is used for the next field. - FID detection by VSYNC skew is not allowed. ACTVID style capture works as follows: - VSYNC is expected to transition from inactive to active between ACTVID window. - This VSYNC transition allows the next line in an ACTVID envelope to be sent to a new VPDMA buffer. - FID value is determined by the FID pin value on the cycle where VSYNC transitions from inactive to active. In basic discrete mode, there is no Vertical Ancillary Data. Therefore, VPDMA descriptors should not use Ancillary Data channels." "0,1" textline " " bitfld.long 0x0 23. " SW_RESET ,0 = Normal 1 = Reset Port B logic. Must be set to ?0? again by the software for the module to function." "0,1" bitfld.long 0x0 24.--29. " FID_SKEW_POSTCOUNT ,Discrete Sync Only post count value when using vsync skew in FID determination" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " ANALYZER_2X4X_SRCNUM_POS ,Embedded Sync Only 0 = For 2x/4x mux mode, srcnum is in the least significant nibble of the XV/fvh codeword (srcnum replaces the protection bits) 1 = For 2x/4x mux mode, srcnum is in the least significant nibble of a horizontal blanking pixel value" "0,1" bitfld.long 0x0 31. " ANALYZER_FVH_ERR_CORRECTION_ENABLE ,Embedded Sync Only 0 = Ignore the protection bits in the XV (fvh) codeword header. This setting is typically desired. 1 = Use the protection bits in an attempt to do error correction for the fvh control bits." "0,1" group.byte 0x10++0x3 line.long 0x0 "VIP_XTRA_PORT_B,ore Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " SRC0_NUMLINES ,Number of expected lines on Source Number 0. The Port_b_src0_size interrupt will trigger if a field/frame is encountered that differs from this linecount." bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13.--14. " ANC_CHAN_SEL_8B ,In 8b mode, Vertically Ancillary Data typically resides in the Luma sites. This bit allows vertical ancillary data to be extracted from the chroma sites instead . 00 = Extract 8b Mode Vertical Ancillary Data from Luma Sites 01 = Extract 8b Mode Vertical Ancillary Data from Chroma Sites 10, 11 = Extract every single sample of vertical ancillary data. The output line is twice as wide as the other modes. For 16b and 24b inputs, ctrl_chan_sel is used to select which channel is used as a source for vertical ancillary data." "0,1,2,3" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--27. 1. " SRC0_NUMPIX ,Number of expected pixels on Source Number 0. The Port_b_src0_size interrupt will trigger if a line is encountered that differs from this pixelcount." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VIP_FIQ_MASK,ask Bits for ARM FIQs" bitfld.long 0x0 0. " PRTA_VDET_MASK ,Port A Video Detect FIQ Mask" "0,1" bitfld.long 0x0 1. " PRTB_VDET_MASK ,Port B Video Detect FIQ Mask" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_OF ,Port A Async FIFO Overflow FIQ Mask" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_OF ,Port B Async FIFO Overflow FIQ Mask" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_OF ,Output FIFO Port A Luma Overflow Mask" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_OF ,Output FIFO Port A Ancillary Overflow Mask" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_OF ,Output FIFO Port B Luma Overflow Mask" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_OF ,Output FIFO Port B Ancillary Overflow Mask" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN ,Port A Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN ,Port A Link Disconnect Scrnum 0 Mask" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN ,Port B Link Connect Srcnum 0 Mask" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN ,Port B Link Disconnect Srcnum 0 Mask" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE ,Video size detected on Port A does not match size programmed in xtra_port_a register" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE ,Video size detected on Port B does not match size programmed in xtra_port_b register" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION_MASK ,Port A YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION_MASK ,Port A ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION_MASK ,Port B YUV VPI Protocol Violation Mask" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION_MASK ,Port B ANC VPI Protocol Violation Mask" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE_MASK ,Port A Cfg Disable Complete Mask" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_MASK ,Port B Cfg Disable Complete Mask" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "VIP_FIQ_CLEAR,Clears bits in the FIQ Status" bitfld.long 0x0 0. " PRTA_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_CLR ,Write 1 followed by 0 to Clear Video Detect FIQ for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_CLR ,Write 1 followed by 0 to Clear Async FIFO Port A Overflow FIQ" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_CLR ,Write 1 followed by 0 to Clear Async FIFO Port B Overflow FIQ" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Luma Overflow FIQ" "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port A Ancillary Overflow FIQ" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_YUV_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Luma Overflow FIQ" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_CLR ,Write 1 followed by 0 to Clear Output FIFO Port B Ancillary Overflow FIQ" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_CLR ,Write 1 followed by 0 to Clear Port A Link Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_CLR ,Write 1 followed by 0 to Clear Port A Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_CLR ,Write 1 followed by 0 to Clear Port B Link Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_CLR ,Write 1 followed by 0 to Clear Port B Link Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port A Src0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_CLR ,Write 1 followed by 0 to Clear Port B Src0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_CFG_DISABLE_COMPLETE_CLR ,Write 1 followed by 0 to Clear Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_ANC_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_A_YUV_PROTOCOL_VIOLATION_CLR ,Write 1 followed by 0 to Clear Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "VIP_FIQ_STATUS,FIQ Status values" bitfld.long 0x0 0. " PRTA_VDET_STATUS ,VDET Status for Port A" "0,1" bitfld.long 0x0 1. " PRTB_VDET_STATUS ,VDET Status for Port B" "0,1" textline " " bitfld.long 0x0 2. " ASYNC_FIFO_PRTA_STATUS ,Async FIFO Port A Overflow Status" "0,1" bitfld.long 0x0 3. " ASYNC_FIFO_PRTB_STATUS ,Async FIFO Port B Overflow Status" "0,1" textline " " bitfld.long 0x0 4. " OUTPUT_FIFO_PRTA_LUMA_STATUS ,Output FIFO Port A Luma Overflow Status" "0,1" bitfld.long 0x0 5. " OUTPUT_FIFO_PRTA_CHROMA_STATUS ,Output FIFO Port A Chroma Overflow Status" "0,1" textline " " bitfld.long 0x0 6. " OUTPUT_FIFO_PRTA_ANC_STATUS ,Output FIFO Port A Ancillary Overflow Status" "0,1" bitfld.long 0x0 7. " OUTPUT_FIFO_PRTB_LUMA_STATUS ,Output FIFO Port B Luma Overflow Status" "0,1" textline " " bitfld.long 0x0 8. " OUTPUT_FIFO_PRTB_CHROMA_STATUS ,Output FIFO Port B Chroma Overflow Status" "0,1" bitfld.long 0x0 9. " OUTPUT_FIFO_PRTB_ANC_STATUS ,Output FIFO Port B Ancillary Overflow Status" "0,1" textline " " bitfld.long 0x0 10. " PORT_A_CONN_STATUS ,Port A Connect FIQ" "0,1" bitfld.long 0x0 11. " PORT_A_DISCONN_STATUS ,Port A Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 12. " PORT_B_CONN_STATUS ,Port B Connect FIQ" "0,1" bitfld.long 0x0 13. " PORT_B_DISCONN_STATUS ,Port B Disconnect FIQ" "0,1" textline " " bitfld.long 0x0 14. " PORT_A_SRC0_SIZE_STATUS ,Port A Source 0 Size FIQ" "0,1" bitfld.long 0x0 15. " PORT_B_SRC0_SIZE_STATUS ,Port B Source 0 Size FIQ" "0,1" textline " " bitfld.long 0x0 16. " PORT_A_YUV_PROTOCOL_VIOLATION ,Port A YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 17. " PORT_A_ANC_PROTOCOL_VIOLATION ,Port A ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 18. " PORT_B_YUV_PROTOCOL_VIOLATION ,Port B YUV VPI Protocol Violation FIQ" "0,1" bitfld.long 0x0 19. " PORT_B_ANC_PROTOCOL_VIOLATION ,Port B ANC VPI Protocol Violation FIQ" "0,1" textline " " bitfld.long 0x0 20. " PORT_A_CFG_DISABLE_COMPLETE ,Port A Cfg Disable Complete FIQ" "0,1" bitfld.long 0x0 21. " PORT_B_CFG_DISABLE_COMPLETE_CLR ,Port B Cfg Disable Complete FIQ" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC_FID,Current and Previous Output Port A Source FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port A. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port A. Source Field ID for Current Field" "0,1" group.byte 0x24++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_ENC_FID,Current and Previous Output Port A Encoder FID values" bitfld.long 0x0 0. " PRTA_SRC0_PREV_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTA_SRC0_CURR_ENC_FID ,For Source ID 0 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTA_SRC1_PREV_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTA_SRC1_CURR_ENC_FID ,For Source ID 1 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTA_SRC2_PREV_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTA_SRC2_CURR_ENC_FID ,For Source ID 2 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTA_SRC3_PREV_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTA_SRC3_CURR_ENC_FID ,For Source ID 3 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTA_SRC4_PREV_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTA_SRC4_CURR_ENC_FID ,For Source ID 4 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTA_SRC5_PREV_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTA_SRC5_CURR_ENC_FID ,For Source ID 5 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTA_SRC6_PREV_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTA_SRC6_CURR_ENC_FID ,For Source ID 6 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTA_SRC7_PREV_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTA_SRC7_CURR_ENC_FID ,For Source ID 7 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTA_SRC8_PREV_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTA_SRC8_CURR_ENC_FID ,For Source ID 8 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTA_SRC9_PREV_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTA_SRC9_CURR_ENC_FID ,For Source ID 9 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTA_SRC10_PREV_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTA_SRC10_CURR_ENC_FID ,For Source ID 10 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTA_SRC11_PREV_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTA_SRC11_CURR_ENC_FID ,For Source ID 11 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTA_SRC12_PREV_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTA_SRC12_CURR_ENC_FID ,For Source ID 12 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTA_SRC13_PREV_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTA_SRC13_CURR_ENC_FID ,For Source ID 13 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTA_SRC14_PREV_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTA_SRC14_CURR_ENC_FID ,For Source ID 14 from Port A. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTA_SRC15_PREV_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTA_SRC15_CURR_ENC_FID ,For Source ID 15 from Port A. Encoder Field ID for Current Field" "0,1" group.byte 0x28++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC_FID,Current and Previous Output Port B Source FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_SOURCE_FID ,For Source ID 0 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_SOURCE_FID ,For Source ID 1 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_SOURCE_FID ,For Source ID 2 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_SOURCE_FID ,For Source ID 3 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_SOURCE_FID ,For Source ID 4 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_SOURCE_FID ,For Source ID 5 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_SOURCE_FID ,For Source ID 6 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_SOURCE_FID ,For Source ID 7 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_SOURCE_FID ,For Source ID 8 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_SOURCE_FID ,For Source ID 9 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_SOURCE_FID ,For Source ID 10 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_SOURCE_FID ,For Source ID 11. from Port B Source Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_SOURCE_FID ,For Source ID 11 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_SOURCE_FID ,For Source ID 12 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_SOURCE_FID ,For Source ID 13 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_SOURCE_FID ,For Source ID 14 from Port B. Source Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_SOURCE_FID ,For Source ID 15 from Port B. Source Field ID for Current Field" "0,1" group.byte 0x2C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_ENC_FID,Current and Previous Output Port B Encoder FID values" bitfld.long 0x0 0. " PRTB_SRC0_PREV_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 1. " PRTB_SRC0_CURR_ENC_FID ,For Source ID 0 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 2. " PRTB_SRC1_PREV_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 3. " PRTB_SRC1_CURR_ENC_FID ,For Source ID 1 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 4. " PRTB_SRC2_PREV_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 5. " PRTB_SRC2_CURR_ENC_FID ,For Source ID 2 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 6. " PRTB_SRC3_PREV_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 7. " PRTB_SRC3_CURR_ENC_FID ,For Source ID 3 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 8. " PRTB_SRC4_PREV_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 9. " PRTB_SRC4_CURR_ENC_FID ,For Source ID 4 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 10. " PRTB_SRC5_PREV_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 11. " PRTB_SRC5_CURR_ENC_FID ,For Source ID 5 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 12. " PRTB_SRC6_PREV_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 13. " PRTB_SRC6_CURR_ENC_FID ,For Source ID 6 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 14. " PRTB_SRC7_PREV_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 15. " PRTB_SRC7_CURR_ENC_FID ,For Source ID 7 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 16. " PRTB_SRC8_PREV_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 17. " PRTB_SRC8_CURR_ENC_FID ,For Source ID 8 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 18. " PRTB_SRC9_PREV_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 19. " PRTB_SRC9_CURR_ENC_FID ,For Source ID 9 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 20. " PRTB_SRC10_PREV_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 21. " PRTB_SRC10_CURR_ENC_FID ,For Source ID 10 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 22. " PRTB_SRC11_PREV_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 23. " PRTB_SRC11_CURR_ENC_FID ,For Source ID 11 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 24. " PRTB_SRC12_PREV_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 25. " PRTB_SRC12_CURR_ENC_FID ,For Source ID 12 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 26. " PRTB_SRC13_PREV_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 27. " PRTB_SRC13_CURR_ENC_FID ,For Source ID 13 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 28. " PRTB_SRC14_PREV_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 29. " PRTB_SRC14_CURR_ENC_FID ,For Source ID 14 from Port B. Encoder Field ID for Current Field" "0,1" textline " " bitfld.long 0x0 30. " PRTB_SRC15_PREV_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Previous Field" "0,1" bitfld.long 0x0 31. " PRTB_SRC15_CURR_ENC_FID ,For Source ID 15 from Port B. Encoder Field ID for Current Field" "0,1" group.byte 0x30++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC0_HEIGHT ,On Port A. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC0_WIDTH ,On Port A. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x34++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC1_HEIGHT ,On Port A. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC1_WIDTH ,On Port A. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x38++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC2_HEIGHT ,On Port A. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC2_WIDTH ,On Port A. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x3C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC3_HEIGHT ,On Port A. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC3_WIDTH ,On Port A. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x40++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC4_HEIGHT ,On Port A. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC4_WIDTH ,On Port A. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC5_HEIGHT ,On Port A. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC5_WIDTH ,On Port A. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x48++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC6_HEIGHT ,On Port A. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC6_WIDTH ,On Port A. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x4C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC7_HEIGHT ,On Port A. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC7_WIDTH ,On Port A. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x50++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC8_HEIGHT ,On Port A. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC8_WIDTH ,On Port A. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x54++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC9_HEIGHT ,On Port A. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC9_WIDTH ,On Port A. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x58++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC10_HEIGHT ,On Port A. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC10_WIDTH ,On Port A. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x5C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC11_HEIGHT ,On Port A. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC11_WIDTH ,On Port A. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x60++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC12_HEIGHT ,On Port A. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC12_WIDTH ,On Port A. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC13_HEIGHT ,On Port A. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC13_WIDTH ,On Port A. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x68++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC14_HEIGHT ,On Port A. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC14_WIDTH ,On Port A. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x6C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_A_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTA_SRC15_HEIGHT ,On Port A. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTA_SRC15_WIDTH ,On Port A. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x70++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC0_SIZE,Width and Height for Source 0" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC0_HEIGHT ,On Port B. Height of Source ID 0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC0_WIDTH ,On Port B. Width of Source ID 0" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x74++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC1_SIZE,Width and Height for Source 1" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC1_HEIGHT ,On Port B. Height of Source ID 1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC1_WIDTH ,On Port B. Width of Source ID 1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x78++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC2_SIZE,Width and Height for Source 2" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC2_HEIGHT ,On Port B. Height of Source ID 2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC2_WIDTH ,On Port B. Width of Source ID 2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x7C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC3_SIZE,Width and Height for Source 3" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC3_HEIGHT ,On Port B. Height of Source ID 3" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC3_WIDTH ,On Port B. Width of Source ID 3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x80++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC4_SIZE,Width and Height for Source 4" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC4_HEIGHT ,On Port B. Height of Source ID 4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC4_WIDTH ,On Port B. Width of Source ID 4" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x84++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC5_SIZE,Width and Height for Source 5" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC5_HEIGHT ,On Port B. Height of Source ID 5" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC5_WIDTH ,On Port B. Width of Source ID 5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x88++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC6_SIZE,Width and Height for Source 6" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC6_HEIGHT ,On Port B. Height of Source ID 6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC6_WIDTH ,On Port B. Width of Source ID 6" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC7_SIZE,Width and Height for Source 7" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC7_HEIGHT ,On Port B. Height of Source ID 7" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC7_WIDTH ,On Port B. Width of Source ID 7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x90++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC8_SIZE,Width and Height for Source 8" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC8_HEIGHT ,On Port B. Height of Source ID 8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC8_WIDTH ,On Port B. Width of Source ID 8" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x94++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC9_SIZE,Width and Height for Source 9" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC9_HEIGHT ,On Port B. Height of Source ID 9" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC9_WIDTH ,On Port B. Width of Source ID 9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x98++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC10_SIZE,Width and Height for Source 10" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC10_HEIGHT ,On Port B. Height of Source ID 10" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC10_WIDTH ,On Port B. Width of Source ID 10" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x9C++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC11_SIZE,Width and Height for Source 11" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC11_HEIGHT ,On Port B. Height of Source ID 11" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC11_WIDTH ,On Port B. Width of Source ID 11" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA0++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC12_SIZE,Width and Height for Source 12" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC12_HEIGHT ,On Port B. Height of Source ID 12" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC12_WIDTH ,On Port B. Width of Source ID 12" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA4++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC13_SIZE,Width and Height for Source 13" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC13_HEIGHT ,On Port B. Height of Source ID 13" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC13_WIDTH ,On Port B. Width of Source ID 13" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xA8++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC14_SIZE,Width and Height for Source 14" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC14_HEIGHT ,On Port B. Height of Source ID 14" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC14_WIDTH ,On Port B. Width of Source ID 14" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xAC++0x3 line.long 0x0 "VIP_OUTPUT_PORT_B_SRC15_SIZE,Width and Height for Source 15" hexmask.long.word 0x0 0.--10. 1. " PRTB_SRC15_HEIGHT ,On Port B. Height of Source ID 15" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PRTB_SRC15_WIDTH ,On Port B. Width of Source ID 15" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xB0++0x3 line.long 0x0 "VIP_PORT_A_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTA_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port A for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB4++0x3 line.long 0x0 "VIP_PORT_B_VDET_VEC,Each bit represents the VDET bit setting for Line Mux Mode" hexmask.long 0x0 0.--31. 1. " PRTB_VDET_VEC ,For Embedded Sync Only In Line Mux Mode. each bit represents the vdet value on Port B for the corresponding source id. This vector is meaningless for 1x/2x/4x mux modes." group.byte 0xB8++0x3 line.long 0x0 "VIP_ANC_CROP_HORZ_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xBC++0x3 line.long 0x0 "VIP_ANC_CROP_VERT_PORT_A,Ancillary Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's ancillary data region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_A,Active Video Cropping Configuration for Input Port A" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping.. the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC8++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_HORZ_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ANC_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ANC_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Ancillary data)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xCC++0x3 line.long 0x0 "VIP_ANC_VIP_CROP_VERT_PORT_B,Ancillary Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ANC_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical ancillary data region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ANC_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnums active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x3 line.long 0x0 "VIP_CROP_HORZ_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMPIX ,The number of pixels to crop from the beginning of each line." bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ACT_BYPASS_N ,0 = Bypass cropping module 1 = Cropping module enabled" "0,1" hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMPIX ,When cropping, the number of pixels to keep after the skip_numpix value. skip_numpix + use_numpix must be smaller than the original line width." textline " " bitfld.long 0x0 28.--31. " ACT_TARGET_SRCNUM ,The cropping module can work on only one srcnum. specified in this field. for each dss_vip_parser output port (Active video)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD4++0x3 line.long 0x0 "VIP_CROP_VERT_PORT_B,Active Video Cropping Configuration for Input Port B" hexmask.long.word 0x0 0.--11. 1. " ACT_SKIP_NUMLINES ,The number of lines to crop from the top of the vertical active video region." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " ACT_USE_NUMLINES ,When cropping, the number of lines to keep after the skip_numlines value. Use_numlines + skip_numlines must be smaller than the total number of lines in the srcnum's active video region." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "VIP_XTRA6_PORT_A,Cfg Disable Active Srcnum Vector Input for Port A" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xDC++0x3 line.long 0x0 "VIP_XTRA7_PORT_B,Cfg Disable Active Srcnum Vector Input for Port B" hexmask.long.word 0x0 0.--15. 1. " ANC_SRCNUM_STOP_IMMEDIATELY ,For the Ancillary Data Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." hexmask.long.word 0x0 16.--31. 1. " YUV_SRCNUM_STOP_IMMEDIATELY ,For the Active Video Port to the VPDMA, logic exists to ensure that a complete frame is sent out to the VPDMA following cfg_enable transitioning inactive for that port. Each bit in this vector represents a srcnum (remapped srcnum for TI line mux mode) going to the VPDMA. For example, bit 0 is srcnum 0, bit 1 is srcnum 1, etc. A ?0? in a bit position means that the hardware will wait for that srcnum, if it is in the middle of a frame, to continue until the end of the frame before stopping. A ?1? in a bit position means that it is ok for a srcnum to stop in the middle of a frame. For example, suppose a source is removed and the input will never complete sending a frame. If the bit position representing that srcnum is set to ?0?, the port will never disable." group.byte 0xE0++0x3 line.long 0x0 "VIP_XTRA8_PORT_A,Reserved Register for Port A" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." group.byte 0xE4++0x3 line.long 0x0 "VIP_XTRA9_PORT_B,Reserved Register for Port B" hexmask.long 0x0 0.--31. 1. " RESERVED ,ust be 0x0 at all times." width 0x0B tree.end tree "VIP1_Slice0_sc" base ad:0x48975800 width 14. group.byte 0x0++0x3 line.long 0x0 "VIP_CFG_SC0,VIP_CFG_SC0" bitfld.long 0x0 0. " CFG_INTERLACE_O ,This parameter is used by vertical scaling. 0: The output format of SC is progressive 1: The output format of SC is interlace" "0,1" bitfld.long 0x0 1. " CFG_LINEAR ,This parameter is used by horizontal scaling. 0: Anamorphic scaling 1: Linear scaling" "0,1" textline " " bitfld.long 0x0 2. " CFG_SC_BYPASS ,This parameter is a general purpose. 0: Scaling module will engaged 1: Scaling module will be bypassed" "0,1" bitfld.long 0x0 3. " CFG_INVT_FID ,This parameter is used by vertical scaling. 0: Progressive input 1: Interlaced input Must be set to 1 when CFG_INTERFACE_I = 1." "0,1" textline " " bitfld.long 0x0 4. " CFG_USE_RAV ,This parameter is used by vertical scaling. 0: Poly-phase filter will be used for the vertical scaling 1: Running average filter will be used for the vertical scaling (down scaling only)" "0,1" bitfld.long 0x0 5. " CFG_ENABLE_EV ,This parameter is used by the edge-detection block. 0: The output of edge-detection block will be force to ?0? 1: The calculation results of edge-detection block will be output normally" "0,1" textline " " bitfld.long 0x0 6. " CFG_AUTO_HS ,This parameter is used by horizontal scaling. 0: the cfg_dcm_2x and cfg_dcm_4x bits will enable appropriate decimation filters 1: HW will decide whether up-scaling or down-scaling is required based on horizontal scaling ratio (SR). SR 0.5 : horizontal polyphase filter is enabled, all decimation filters are disabled SR = 0.5 : dcm_2x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.5 SR 0.25 : dcm_2x and horizontal polyphase filter both are enabled SR = 0.25 : dcm_4x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.25 SR 0.125 : dcm_4x and horizontal polyphase filter are both enabled SR = 0.125 : Functionally supported, but not recommended in auto mode for image quality concerns" "0,1" bitfld.long 0x0 7. " CFG_DCM_2X ,This parameter is used by horizontal scaling. 0: the 2X decimation filter is disabled 1: the 2X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (0.25 horizontal scale ratio 0.5). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" textline " " bitfld.long 0x0 8. " CFG_DCM_4X ,This parameter is used by horizontal scaling. 0: the 4X decimation filter is disabled 1: the 4X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (horizontal scale ratio 0.25). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" bitfld.long 0x0 9. " CFG_HP_BYPASS ,This parameter is used by horizontal scaling. If cfg_auto_hs is 0, horizontal polyphase filter is always enabled. In this case, this register is DON?T CARE. If cfg_auto_hs is 1, 0 : The polyphase scaler is always used regardless of the scaling ratio. 1 : The polyphase scaler is bypassed only when (tar_w == src_w) or (tar_w == src_w/2) or (tar_w == src_w/4)" "0,1" textline " " bitfld.long 0x0 10. " CFG_INTERLACE_I ,This parameter is used by both horizontal and vertical scaling 0: the input video format is progressive 1: the input video format is interlace" "0,1" bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 14. " CFG_Y_PK_EN ,This parameter is used by peaking block. 0: disable luma peaking 1: enable luma peaking" "0,1" bitfld.long 0x0 15. " CFG_TRIM ,Trimming enable. When 1, the input image whose size is specified by orgW and orgH registers is trimmed to the size with srcW and srcH from the offset specified by offW and offH. 0: disable trimming 1: enable trimming" "0,1" textline " " bitfld.long 0x0 16. " CFG_FID_SELFGEN ,FID self generate enable. When input is progressive and this bit is set, the SC generates self-toggling (top/bottom) output FID when performing interlacing." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_CFG_SC1,VIP_CFG_SC1" hexmask.long 0x0 0.--26. 1. " CFG_ROW_ACC_INC ,This parameter is used by vertical scaling. It defines the increment of the row accumulator in vertical poly-phase filter. It can be calculated by following formula: row_acc_inc = round(2^16 *(src_h)/(tar_h)) In case of interlaced input, srcH is input field height In case of interlaced output, tarH is output field height." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8++0x3 line.long 0x0 "VIP_CFG_SC2,VIP_CFG_SC2" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this offset will be applied to a frame. In interlace mode: this offset will be applied to the top field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC++0x3 line.long 0x0 "VIP_CFG_SC3,VIP_CFG_SC3" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this parameter will not be used. In interlace mode: this offset will be applied to the bottom field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10++0x3 line.long 0x0 "VIP_CFG_SC4,VIP_CFG_SC4" hexmask.long.word 0x0 0.--10. 1. " CFG_TAR_H ,This parameter is a general purpose. Scaled target picture height.. unit is line... This parameter defines the final output picture size. For the interlace output.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_TAR_W ,This parameter is a general purpose. Scaled target picture width. unit is pixel. This parameter defines the final output picture size" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_LIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'lin_acc_inc' that is defined in CFG_SC9" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " CFG_NLIN_ACC_INIT_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'nlin_acc_init' that is defined in CFG_SC10" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "VIP_CFG_SC5,VIP_CFG_SC5" hexmask.long.word 0x0 0.--10. 1. " CFG_SRC_H ,This parameter is a general purpose. This parameter defines the height of the source image. For the interlace input.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_SRC_W ,This parameter is a general purpose. This parameter defines the width of the source image" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_NLIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of ?nlin_acc_inc? that is defined in CFG_SC11" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x18++0x3 line.long 0x0 "VIP_CFG_SC6,VIP_CFG_SC6" hexmask.long.word 0x0 0.--9. 1. " CFG_ROW_ACC_INIT_RAV ,This parameter is used by vertical scaling. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for progressive format or top field of interlace format)" hexmask.long.word 0x0 10.--19. 1. " CFG_ROW_ACC_INIT_RAV_B ,This parameter is used by vertical scaling. it is used only when the input is interlace format. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for bottom field of interlace format)" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_CFG_SC8,VIP_CFG_SC8" hexmask.long.word 0x0 0.--10. 1. " CFG_NLIN_LEFT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on left-hand side. In other words. it defines the location of the last pixel in the left-sidenonlinear strip. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_NLIN_RIGHT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on right-hand side. In other words. it defines the location of the last pixel where the linear scaling is ended. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VIP_CFG_SC9,VIP_CFG_SC9" hexmask.long 0x0 0.--31. 1. " CFG_LIN_ACC_INC ,This parameter is used by horizontal scaling. It defines the increment of the linear accumulator. if SR 0.5 then lin_acc_inc = round(2^24*(srcWi -1) /(tarWi -1)) else if 0.25 SR ? 0.5 lin_acc_inc = round(2^24*(srcWi/2 -1) /(tarWi - 1)) else if SR ? 0.25 lin_acc_inc = round(2^24*(srcWi/4 -1) /(tarWi - 1)) where srcWi and tarWi are the inner source width and the inner target width respectively." group.byte 0x28++0x3 line.long 0x0 "VIP_CFG_SC10,VIP_CFG_SC10" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INIT ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the initialization value of the nonlinear accumulator. nlin_acc_init = K*(1-2*d) Here the definitions of K and d are the same as in CFG_SC11" group.byte 0x2C++0x3 line.long 0x0 "VIP_CFG_SC11,VIP_CFG_SC11" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INC ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the increment of the nonlinear accumulator. if upscaling then d = 0 if Ltar !=0 then K =round[2^24*Lsrc/(Ltar*Ltar) ] where Lsrc= (srcW-srcWi)/2 else K = 0 elseif downscaling d = (tarW-1)/2 if Ltar!=0 then K = round[ 2^24 * Lsrc / (Ltar*(Ltar-2d))] where Lsrc= (srcW-srcWi)/(2n) and n=1..2 or 4 else K = 0 nlin_acc_inc = 2*K (negative for downscaling)" group.byte 0x30++0x3 line.long 0x0 "VIP_CFG_SC12,VIP_CFG_SC12" hexmask.long 0x0 0.--24. 1. " CFG_COL_ACC_OFFSET ,This parameter is used in horizontal scaling. It defines the luma accumulator's offset. Normally this parameter can be set as 0 if no horizontal offset is involved. In some applications.. such as Pan and Scan.. a corresponding offset value should be set. The format is 1.24." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_CFG_SC13,VIP_CFG_SC13" hexmask.long.word 0x0 0.--9. 1. " CFG_SC_FACTOR_RAV ,This parameter is used by vertical scaling. Vertical scaling factor: It is defined as following: 1024*tarH/srcH. It is used for downscaling by the running average filter" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "VIP_CFG_SC18,VIP_CFG_SC18" hexmask.long.word 0x0 0.--9. 1. " CFG_HS_FACTOR ,This parameter is used by horizontal scaling. Horizontal-scaling-factor = tarWi/srcWi. Numerical format: 6.4 (6 bit integer and 4 bit fraction)" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "VIP_CFG_SC19,VIP_CFG_SC19" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF0 ,This parameter is used by the peaking block. Defines the coefficient 0 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF1 ,This parameter is used by the peaking block. Defines the coefficient 1 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_HPF_COEF2 ,This parameter is used by the peaking block. Defines the coefficient 2 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 24.--31. 1. " CFG_HPF_COEF3 ,This parameter is used by the peaking block. Defines the coefficient 3 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." group.byte 0x50++0x3 line.long 0x0 "VIP_CFG_SC20,VIP_CFG_SC20" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF4 ,This parameter is used by the peaking block. Defines the coefficient 4 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF5 ,This parameter is used by the peaking block. Defines the coefficient 5 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " bitfld.long 0x0 16.--18. " CFG_HPF_NORM_SHIFT ,This parameter is used by the peaking block. Defines the decimal point of the hpf coefficient." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 20.--28. 1. " CFG_NL_LIMIT ,This parameter is used by the peaking block. The maximum of clipping." bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x54++0x3 line.long 0x0 "VIP_CFG_SC21,VIP_CFG_SC21" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_LO_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be 0" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_NL_LO_SLOPE ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The format is fixed point 4.4." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "VIP_CFG_SC22,VIP_CFG_SC22" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_HI_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be nl_hi_thr." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The gain is 2^(nl_hi_slope_shift-3)." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "VIP_CFG_SC24,VIP_CFG_SC24" hexmask.long.word 0x0 0.--10. 1. " CFG_ORG_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_ORG_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_CFG_SC25,VIP_CFG_SC25" hexmask.long.word 0x0 0.--10. 1. " CFG_OFF_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_OFF_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "VIP1_Slice1_sc" base ad:0x48975D00 width 14. group.byte 0x0++0x3 line.long 0x0 "VIP_CFG_SC0,VIP_CFG_SC0" bitfld.long 0x0 0. " CFG_INTERLACE_O ,This parameter is used by vertical scaling. 0: The output format of SC is progressive 1: The output format of SC is interlace" "0,1" bitfld.long 0x0 1. " CFG_LINEAR ,This parameter is used by horizontal scaling. 0: Anamorphic scaling 1: Linear scaling" "0,1" textline " " bitfld.long 0x0 2. " CFG_SC_BYPASS ,This parameter is a general purpose. 0: Scaling module will engaged 1: Scaling module will be bypassed" "0,1" bitfld.long 0x0 3. " CFG_INVT_FID ,This parameter is used by vertical scaling. 0: Progressive input 1: Interlaced input Must be set to 1 when CFG_INTERFACE_I = 1." "0,1" textline " " bitfld.long 0x0 4. " CFG_USE_RAV ,This parameter is used by vertical scaling. 0: Poly-phase filter will be used for the vertical scaling 1: Running average filter will be used for the vertical scaling (down scaling only)" "0,1" bitfld.long 0x0 5. " CFG_ENABLE_EV ,This parameter is used by the edge-detection block. 0: The output of edge-detection block will be force to ?0? 1: The calculation results of edge-detection block will be output normally" "0,1" textline " " bitfld.long 0x0 6. " CFG_AUTO_HS ,This parameter is used by horizontal scaling. 0: the cfg_dcm_2x and cfg_dcm_4x bits will enable appropriate decimation filters 1: HW will decide whether up-scaling or down-scaling is required based on horizontal scaling ratio (SR). SR 0.5 : horizontal polyphase filter is enabled, all decimation filters are disabled SR = 0.5 : dcm_2x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.5 SR 0.25 : dcm_2x and horizontal polyphase filter both are enabled SR = 0.25 : dcm_4x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.25 SR 0.125 : dcm_4x and horizontal polyphase filter are both enabled SR = 0.125 : Functionally supported, but not recommended in auto mode for image quality concerns" "0,1" bitfld.long 0x0 7. " CFG_DCM_2X ,This parameter is used by horizontal scaling. 0: the 2X decimation filter is disabled 1: the 2X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (0.25 horizontal scale ratio 0.5). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" textline " " bitfld.long 0x0 8. " CFG_DCM_4X ,This parameter is used by horizontal scaling. 0: the 4X decimation filter is disabled 1: the 4X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (horizontal scale ratio 0.25). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" bitfld.long 0x0 9. " CFG_HP_BYPASS ,This parameter is used by horizontal scaling. If cfg_auto_hs is 0, horizontal polyphase filter is always enabled. In this case, this register is DON?T CARE. If cfg_auto_hs is 1, 0 : The polyphase scaler is always used regardless of the scaling ratio. 1 : The polyphase scaler is bypassed only when (tar_w == src_w) or (tar_w == src_w/2) or (tar_w == src_w/4)" "0,1" textline " " bitfld.long 0x0 10. " CFG_INTERLACE_I ,This parameter is used by both horizontal and vertical scaling 0: the input video format is progressive 1: the input video format is interlace" "0,1" bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 14. " CFG_Y_PK_EN ,This parameter is used by peaking block. 0: disable luma peaking 1: enable luma peaking" "0,1" bitfld.long 0x0 15. " CFG_TRIM ,Trimming enable. When 1, the input image whose size is specified by orgW and orgH registers is trimmed to the size with srcW and srcH from the offset specified by offW and offH. 0: disable trimming 1: enable trimming" "0,1" textline " " bitfld.long 0x0 16. " CFG_FID_SELFGEN ,FID self generate enable. When input is progressive and this bit is set, the SC generates self-toggling (top/bottom) output FID when performing interlacing." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_CFG_SC1,VIP_CFG_SC1" hexmask.long 0x0 0.--26. 1. " CFG_ROW_ACC_INC ,This parameter is used by vertical scaling. It defines the increment of the row accumulator in vertical poly-phase filter. It can be calculated by following formula: row_acc_inc = round(2^16 *(src_h)/(tar_h)) In case of interlaced input, srcH is input field height In case of interlaced output, tarH is output field height." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8++0x3 line.long 0x0 "VIP_CFG_SC2,VIP_CFG_SC2" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this offset will be applied to a frame. In interlace mode: this offset will be applied to the top field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC++0x3 line.long 0x0 "VIP_CFG_SC3,VIP_CFG_SC3" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this parameter will not be used. In interlace mode: this offset will be applied to the bottom field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10++0x3 line.long 0x0 "VIP_CFG_SC4,VIP_CFG_SC4" hexmask.long.word 0x0 0.--10. 1. " CFG_TAR_H ,This parameter is a general purpose. Scaled target picture height.. unit is line... This parameter defines the final output picture size. For the interlace output.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_TAR_W ,This parameter is a general purpose. Scaled target picture width. unit is pixel. This parameter defines the final output picture size" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_LIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'lin_acc_inc' that is defined in CFG_SC9" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " CFG_NLIN_ACC_INIT_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'nlin_acc_init' that is defined in CFG_SC10" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "VIP_CFG_SC5,VIP_CFG_SC5" hexmask.long.word 0x0 0.--10. 1. " CFG_SRC_H ,This parameter is a general purpose. This parameter defines the height of the source image. For the interlace input.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_SRC_W ,This parameter is a general purpose. This parameter defines the width of the source image" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_NLIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of ?nlin_acc_inc? that is defined in CFG_SC11" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x18++0x3 line.long 0x0 "VIP_CFG_SC6,VIP_CFG_SC6" hexmask.long.word 0x0 0.--9. 1. " CFG_ROW_ACC_INIT_RAV ,This parameter is used by vertical scaling. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for progressive format or top field of interlace format)" hexmask.long.word 0x0 10.--19. 1. " CFG_ROW_ACC_INIT_RAV_B ,This parameter is used by vertical scaling. it is used only when the input is interlace format. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for bottom field of interlace format)" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_CFG_SC8,VIP_CFG_SC8" hexmask.long.word 0x0 0.--10. 1. " CFG_NLIN_LEFT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on left-hand side. In other words. it defines the location of the last pixel in the left-sidenonlinear strip. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_NLIN_RIGHT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on right-hand side. In other words. it defines the location of the last pixel where the linear scaling is ended. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VIP_CFG_SC9,VIP_CFG_SC9" hexmask.long 0x0 0.--31. 1. " CFG_LIN_ACC_INC ,This parameter is used by horizontal scaling. It defines the increment of the linear accumulator. if SR 0.5 then lin_acc_inc = round(2^24*(srcWi -1) /(tarWi -1)) else if 0.25 SR ? 0.5 lin_acc_inc = round(2^24*(srcWi/2 -1) /(tarWi - 1)) else if SR ? 0.25 lin_acc_inc = round(2^24*(srcWi/4 -1) /(tarWi - 1)) where srcWi and tarWi are the inner source width and the inner target width respectively." group.byte 0x28++0x3 line.long 0x0 "VIP_CFG_SC10,VIP_CFG_SC10" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INIT ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the initialization value of the nonlinear accumulator. nlin_acc_init = K*(1-2*d) Here the definitions of K and d are the same as in CFG_SC11" group.byte 0x2C++0x3 line.long 0x0 "VIP_CFG_SC11,VIP_CFG_SC11" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INC ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the increment of the nonlinear accumulator. if upscaling then d = 0 if Ltar !=0 then K =round[2^24*Lsrc/(Ltar*Ltar) ] where Lsrc= (srcW-srcWi)/2 else K = 0 elseif downscaling d = (tarW-1)/2 if Ltar!=0 then K = round[ 2^24 * Lsrc / (Ltar*(Ltar-2d))] where Lsrc= (srcW-srcWi)/(2n) and n=1..2 or 4 else K = 0 nlin_acc_inc = 2*K (negative for downscaling)" group.byte 0x30++0x3 line.long 0x0 "VIP_CFG_SC12,VIP_CFG_SC12" hexmask.long 0x0 0.--24. 1. " CFG_COL_ACC_OFFSET ,This parameter is used in horizontal scaling. It defines the luma accumulator's offset. Normally this parameter can be set as 0 if no horizontal offset is involved. In some applications.. such as Pan and Scan.. a corresponding offset value should be set. The format is 1.24." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_CFG_SC13,VIP_CFG_SC13" hexmask.long.word 0x0 0.--9. 1. " CFG_SC_FACTOR_RAV ,This parameter is used by vertical scaling. Vertical scaling factor: It is defined as following: 1024*tarH/srcH. It is used for downscaling by the running average filter" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "VIP_CFG_SC18,VIP_CFG_SC18" hexmask.long.word 0x0 0.--9. 1. " CFG_HS_FACTOR ,This parameter is used by horizontal scaling. Horizontal-scaling-factor = tarWi/srcWi. Numerical format: 6.4 (6 bit integer and 4 bit fraction)" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "VIP_CFG_SC19,VIP_CFG_SC19" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF0 ,This parameter is used by the peaking block. Defines the coefficient 0 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF1 ,This parameter is used by the peaking block. Defines the coefficient 1 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_HPF_COEF2 ,This parameter is used by the peaking block. Defines the coefficient 2 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 24.--31. 1. " CFG_HPF_COEF3 ,This parameter is used by the peaking block. Defines the coefficient 3 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." group.byte 0x50++0x3 line.long 0x0 "VIP_CFG_SC20,VIP_CFG_SC20" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF4 ,This parameter is used by the peaking block. Defines the coefficient 4 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF5 ,This parameter is used by the peaking block. Defines the coefficient 5 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " bitfld.long 0x0 16.--18. " CFG_HPF_NORM_SHIFT ,This parameter is used by the peaking block. Defines the decimal point of the hpf coefficient." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 20.--28. 1. " CFG_NL_LIMIT ,This parameter is used by the peaking block. The maximum of clipping." bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x54++0x3 line.long 0x0 "VIP_CFG_SC21,VIP_CFG_SC21" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_LO_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be 0" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_NL_LO_SLOPE ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The format is fixed point 4.4." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "VIP_CFG_SC22,VIP_CFG_SC22" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_HI_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be nl_hi_thr." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The gain is 2^(nl_hi_slope_shift-3)." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "VIP_CFG_SC24,VIP_CFG_SC24" hexmask.long.word 0x0 0.--10. 1. " CFG_ORG_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_ORG_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_CFG_SC25,VIP_CFG_SC25" hexmask.long.word 0x0 0.--10. 1. " CFG_OFF_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_OFF_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "VIP2_Slice0_sc" base ad:0x48995800 width 14. group.byte 0x0++0x3 line.long 0x0 "VIP_CFG_SC0,VIP_CFG_SC0" bitfld.long 0x0 0. " CFG_INTERLACE_O ,This parameter is used by vertical scaling. 0: The output format of SC is progressive 1: The output format of SC is interlace" "0,1" bitfld.long 0x0 1. " CFG_LINEAR ,This parameter is used by horizontal scaling. 0: Anamorphic scaling 1: Linear scaling" "0,1" textline " " bitfld.long 0x0 2. " CFG_SC_BYPASS ,This parameter is a general purpose. 0: Scaling module will engaged 1: Scaling module will be bypassed" "0,1" bitfld.long 0x0 3. " CFG_INVT_FID ,This parameter is used by vertical scaling. 0: Progressive input 1: Interlaced input Must be set to 1 when CFG_INTERFACE_I = 1." "0,1" textline " " bitfld.long 0x0 4. " CFG_USE_RAV ,This parameter is used by vertical scaling. 0: Poly-phase filter will be used for the vertical scaling 1: Running average filter will be used for the vertical scaling (down scaling only)" "0,1" bitfld.long 0x0 5. " CFG_ENABLE_EV ,This parameter is used by the edge-detection block. 0: The output of edge-detection block will be force to ?0? 1: The calculation results of edge-detection block will be output normally" "0,1" textline " " bitfld.long 0x0 6. " CFG_AUTO_HS ,This parameter is used by horizontal scaling. 0: the cfg_dcm_2x and cfg_dcm_4x bits will enable appropriate decimation filters 1: HW will decide whether up-scaling or down-scaling is required based on horizontal scaling ratio (SR). SR 0.5 : horizontal polyphase filter is enabled, all decimation filters are disabled SR = 0.5 : dcm_2x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.5 SR 0.25 : dcm_2x and horizontal polyphase filter both are enabled SR = 0.25 : dcm_4x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.25 SR 0.125 : dcm_4x and horizontal polyphase filter are both enabled SR = 0.125 : Functionally supported, but not recommended in auto mode for image quality concerns" "0,1" bitfld.long 0x0 7. " CFG_DCM_2X ,This parameter is used by horizontal scaling. 0: the 2X decimation filter is disabled 1: the 2X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (0.25 horizontal scale ratio 0.5). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" textline " " bitfld.long 0x0 8. " CFG_DCM_4X ,This parameter is used by horizontal scaling. 0: the 4X decimation filter is disabled 1: the 4X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (horizontal scale ratio 0.25). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" bitfld.long 0x0 9. " CFG_HP_BYPASS ,This parameter is used by horizontal scaling. If cfg_auto_hs is 0, horizontal polyphase filter is always enabled. In this case, this register is DON?T CARE. If cfg_auto_hs is 1, 0 : The polyphase scaler is always used regardless of the scaling ratio. 1 : The polyphase scaler is bypassed only when (tar_w == src_w) or (tar_w == src_w/2) or (tar_w == src_w/4)" "0,1" textline " " bitfld.long 0x0 10. " CFG_INTERLACE_I ,This parameter is used by both horizontal and vertical scaling 0: the input video format is progressive 1: the input video format is interlace" "0,1" bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 14. " CFG_Y_PK_EN ,This parameter is used by peaking block. 0: disable luma peaking 1: enable luma peaking" "0,1" bitfld.long 0x0 15. " CFG_TRIM ,Trimming enable. When 1, the input image whose size is specified by orgW and orgH registers is trimmed to the size with srcW and srcH from the offset specified by offW and offH. 0: disable trimming 1: enable trimming" "0,1" textline " " bitfld.long 0x0 16. " CFG_FID_SELFGEN ,FID self generate enable. When input is progressive and this bit is set, the SC generates self-toggling (top/bottom) output FID when performing interlacing." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_CFG_SC1,VIP_CFG_SC1" hexmask.long 0x0 0.--26. 1. " CFG_ROW_ACC_INC ,This parameter is used by vertical scaling. It defines the increment of the row accumulator in vertical poly-phase filter. It can be calculated by following formula: row_acc_inc = round(2^16 *(src_h)/(tar_h)) In case of interlaced input, srcH is input field height In case of interlaced output, tarH is output field height." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8++0x3 line.long 0x0 "VIP_CFG_SC2,VIP_CFG_SC2" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this offset will be applied to a frame. In interlace mode: this offset will be applied to the top field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC++0x3 line.long 0x0 "VIP_CFG_SC3,VIP_CFG_SC3" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this parameter will not be used. In interlace mode: this offset will be applied to the bottom field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10++0x3 line.long 0x0 "VIP_CFG_SC4,VIP_CFG_SC4" hexmask.long.word 0x0 0.--10. 1. " CFG_TAR_H ,This parameter is a general purpose. Scaled target picture height.. unit is line... This parameter defines the final output picture size. For the interlace output.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_TAR_W ,This parameter is a general purpose. Scaled target picture width. unit is pixel. This parameter defines the final output picture size" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_LIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'lin_acc_inc' that is defined in CFG_SC9" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " CFG_NLIN_ACC_INIT_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'nlin_acc_init' that is defined in CFG_SC10" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "VIP_CFG_SC5,VIP_CFG_SC5" hexmask.long.word 0x0 0.--10. 1. " CFG_SRC_H ,This parameter is a general purpose. This parameter defines the height of the source image. For the interlace input.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_SRC_W ,This parameter is a general purpose. This parameter defines the width of the source image" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_NLIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of ?nlin_acc_inc? that is defined in CFG_SC11" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x18++0x3 line.long 0x0 "VIP_CFG_SC6,VIP_CFG_SC6" hexmask.long.word 0x0 0.--9. 1. " CFG_ROW_ACC_INIT_RAV ,This parameter is used by vertical scaling. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for progressive format or top field of interlace format)" hexmask.long.word 0x0 10.--19. 1. " CFG_ROW_ACC_INIT_RAV_B ,This parameter is used by vertical scaling. it is used only when the input is interlace format. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for bottom field of interlace format)" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_CFG_SC8,VIP_CFG_SC8" hexmask.long.word 0x0 0.--10. 1. " CFG_NLIN_LEFT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on left-hand side. In other words. it defines the location of the last pixel in the left-sidenonlinear strip. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_NLIN_RIGHT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on right-hand side. In other words. it defines the location of the last pixel where the linear scaling is ended. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VIP_CFG_SC9,VIP_CFG_SC9" hexmask.long 0x0 0.--31. 1. " CFG_LIN_ACC_INC ,This parameter is used by horizontal scaling. It defines the increment of the linear accumulator. if SR 0.5 then lin_acc_inc = round(2^24*(srcWi -1) /(tarWi -1)) else if 0.25 SR ? 0.5 lin_acc_inc = round(2^24*(srcWi/2 -1) /(tarWi - 1)) else if SR ? 0.25 lin_acc_inc = round(2^24*(srcWi/4 -1) /(tarWi - 1)) where srcWi and tarWi are the inner source width and the inner target width respectively." group.byte 0x28++0x3 line.long 0x0 "VIP_CFG_SC10,VIP_CFG_SC10" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INIT ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the initialization value of the nonlinear accumulator. nlin_acc_init = K*(1-2*d) Here the definitions of K and d are the same as in CFG_SC11" group.byte 0x2C++0x3 line.long 0x0 "VIP_CFG_SC11,VIP_CFG_SC11" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INC ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the increment of the nonlinear accumulator. if upscaling then d = 0 if Ltar !=0 then K =round[2^24*Lsrc/(Ltar*Ltar) ] where Lsrc= (srcW-srcWi)/2 else K = 0 elseif downscaling d = (tarW-1)/2 if Ltar!=0 then K = round[ 2^24 * Lsrc / (Ltar*(Ltar-2d))] where Lsrc= (srcW-srcWi)/(2n) and n=1..2 or 4 else K = 0 nlin_acc_inc = 2*K (negative for downscaling)" group.byte 0x30++0x3 line.long 0x0 "VIP_CFG_SC12,VIP_CFG_SC12" hexmask.long 0x0 0.--24. 1. " CFG_COL_ACC_OFFSET ,This parameter is used in horizontal scaling. It defines the luma accumulator's offset. Normally this parameter can be set as 0 if no horizontal offset is involved. In some applications.. such as Pan and Scan.. a corresponding offset value should be set. The format is 1.24." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_CFG_SC13,VIP_CFG_SC13" hexmask.long.word 0x0 0.--9. 1. " CFG_SC_FACTOR_RAV ,This parameter is used by vertical scaling. Vertical scaling factor: It is defined as following: 1024*tarH/srcH. It is used for downscaling by the running average filter" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "VIP_CFG_SC18,VIP_CFG_SC18" hexmask.long.word 0x0 0.--9. 1. " CFG_HS_FACTOR ,This parameter is used by horizontal scaling. Horizontal-scaling-factor = tarWi/srcWi. Numerical format: 6.4 (6 bit integer and 4 bit fraction)" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "VIP_CFG_SC19,VIP_CFG_SC19" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF0 ,This parameter is used by the peaking block. Defines the coefficient 0 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF1 ,This parameter is used by the peaking block. Defines the coefficient 1 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_HPF_COEF2 ,This parameter is used by the peaking block. Defines the coefficient 2 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 24.--31. 1. " CFG_HPF_COEF3 ,This parameter is used by the peaking block. Defines the coefficient 3 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." group.byte 0x50++0x3 line.long 0x0 "VIP_CFG_SC20,VIP_CFG_SC20" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF4 ,This parameter is used by the peaking block. Defines the coefficient 4 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF5 ,This parameter is used by the peaking block. Defines the coefficient 5 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " bitfld.long 0x0 16.--18. " CFG_HPF_NORM_SHIFT ,This parameter is used by the peaking block. Defines the decimal point of the hpf coefficient." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 20.--28. 1. " CFG_NL_LIMIT ,This parameter is used by the peaking block. The maximum of clipping." bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x54++0x3 line.long 0x0 "VIP_CFG_SC21,VIP_CFG_SC21" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_LO_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be 0" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_NL_LO_SLOPE ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The format is fixed point 4.4." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "VIP_CFG_SC22,VIP_CFG_SC22" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_HI_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be nl_hi_thr." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The gain is 2^(nl_hi_slope_shift-3)." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "VIP_CFG_SC24,VIP_CFG_SC24" hexmask.long.word 0x0 0.--10. 1. " CFG_ORG_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_ORG_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_CFG_SC25,VIP_CFG_SC25" hexmask.long.word 0x0 0.--10. 1. " CFG_OFF_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_OFF_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "VIP2_Slice1_sc" base ad:0x48995D00 width 14. group.byte 0x0++0x3 line.long 0x0 "VIP_CFG_SC0,VIP_CFG_SC0" bitfld.long 0x0 0. " CFG_INTERLACE_O ,This parameter is used by vertical scaling. 0: The output format of SC is progressive 1: The output format of SC is interlace" "0,1" bitfld.long 0x0 1. " CFG_LINEAR ,This parameter is used by horizontal scaling. 0: Anamorphic scaling 1: Linear scaling" "0,1" textline " " bitfld.long 0x0 2. " CFG_SC_BYPASS ,This parameter is a general purpose. 0: Scaling module will engaged 1: Scaling module will be bypassed" "0,1" bitfld.long 0x0 3. " CFG_INVT_FID ,This parameter is used by vertical scaling. 0: Progressive input 1: Interlaced input Must be set to 1 when CFG_INTERFACE_I = 1." "0,1" textline " " bitfld.long 0x0 4. " CFG_USE_RAV ,This parameter is used by vertical scaling. 0: Poly-phase filter will be used for the vertical scaling 1: Running average filter will be used for the vertical scaling (down scaling only)" "0,1" bitfld.long 0x0 5. " CFG_ENABLE_EV ,This parameter is used by the edge-detection block. 0: The output of edge-detection block will be force to ?0? 1: The calculation results of edge-detection block will be output normally" "0,1" textline " " bitfld.long 0x0 6. " CFG_AUTO_HS ,This parameter is used by horizontal scaling. 0: the cfg_dcm_2x and cfg_dcm_4x bits will enable appropriate decimation filters 1: HW will decide whether up-scaling or down-scaling is required based on horizontal scaling ratio (SR). SR 0.5 : horizontal polyphase filter is enabled, all decimation filters are disabled SR = 0.5 : dcm_2x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.5 SR 0.25 : dcm_2x and horizontal polyphase filter both are enabled SR = 0.25 : dcm_4x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.25 SR 0.125 : dcm_4x and horizontal polyphase filter are both enabled SR = 0.125 : Functionally supported, but not recommended in auto mode for image quality concerns" "0,1" bitfld.long 0x0 7. " CFG_DCM_2X ,This parameter is used by horizontal scaling. 0: the 2X decimation filter is disabled 1: the 2X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (0.25 horizontal scale ratio 0.5). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" textline " " bitfld.long 0x0 8. " CFG_DCM_4X ,This parameter is used by horizontal scaling. 0: the 4X decimation filter is disabled 1: the 4X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (horizontal scale ratio 0.25). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" bitfld.long 0x0 9. " CFG_HP_BYPASS ,This parameter is used by horizontal scaling. If cfg_auto_hs is 0, horizontal polyphase filter is always enabled. In this case, this register is DON?T CARE. If cfg_auto_hs is 1, 0 : The polyphase scaler is always used regardless of the scaling ratio. 1 : The polyphase scaler is bypassed only when (tar_w == src_w) or (tar_w == src_w/2) or (tar_w == src_w/4)" "0,1" textline " " bitfld.long 0x0 10. " CFG_INTERLACE_I ,This parameter is used by both horizontal and vertical scaling 0: the input video format is progressive 1: the input video format is interlace" "0,1" bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 14. " CFG_Y_PK_EN ,This parameter is used by peaking block. 0: disable luma peaking 1: enable luma peaking" "0,1" bitfld.long 0x0 15. " CFG_TRIM ,Trimming enable. When 1, the input image whose size is specified by orgW and orgH registers is trimmed to the size with srcW and srcH from the offset specified by offW and offH. 0: disable trimming 1: enable trimming" "0,1" textline " " bitfld.long 0x0 16. " CFG_FID_SELFGEN ,FID self generate enable. When input is progressive and this bit is set, the SC generates self-toggling (top/bottom) output FID when performing interlacing." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_CFG_SC1,VIP_CFG_SC1" hexmask.long 0x0 0.--26. 1. " CFG_ROW_ACC_INC ,This parameter is used by vertical scaling. It defines the increment of the row accumulator in vertical poly-phase filter. It can be calculated by following formula: row_acc_inc = round(2^16 *(src_h)/(tar_h)) In case of interlaced input, srcH is input field height In case of interlaced output, tarH is output field height." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8++0x3 line.long 0x0 "VIP_CFG_SC2,VIP_CFG_SC2" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this offset will be applied to a frame. In interlace mode: this offset will be applied to the top field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC++0x3 line.long 0x0 "VIP_CFG_SC3,VIP_CFG_SC3" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this parameter will not be used. In interlace mode: this offset will be applied to the bottom field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10++0x3 line.long 0x0 "VIP_CFG_SC4,VIP_CFG_SC4" hexmask.long.word 0x0 0.--10. 1. " CFG_TAR_H ,This parameter is a general purpose. Scaled target picture height.. unit is line... This parameter defines the final output picture size. For the interlace output.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_TAR_W ,This parameter is a general purpose. Scaled target picture width. unit is pixel. This parameter defines the final output picture size" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_LIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'lin_acc_inc' that is defined in CFG_SC9" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " CFG_NLIN_ACC_INIT_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'nlin_acc_init' that is defined in CFG_SC10" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "VIP_CFG_SC5,VIP_CFG_SC5" hexmask.long.word 0x0 0.--10. 1. " CFG_SRC_H ,This parameter is a general purpose. This parameter defines the height of the source image. For the interlace input.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_SRC_W ,This parameter is a general purpose. This parameter defines the width of the source image" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_NLIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of ?nlin_acc_inc? that is defined in CFG_SC11" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x18++0x3 line.long 0x0 "VIP_CFG_SC6,VIP_CFG_SC6" hexmask.long.word 0x0 0.--9. 1. " CFG_ROW_ACC_INIT_RAV ,This parameter is used by vertical scaling. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for progressive format or top field of interlace format)" hexmask.long.word 0x0 10.--19. 1. " CFG_ROW_ACC_INIT_RAV_B ,This parameter is used by vertical scaling. it is used only when the input is interlace format. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for bottom field of interlace format)" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_CFG_SC8,VIP_CFG_SC8" hexmask.long.word 0x0 0.--10. 1. " CFG_NLIN_LEFT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on left-hand side. In other words. it defines the location of the last pixel in the left-sidenonlinear strip. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_NLIN_RIGHT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on right-hand side. In other words. it defines the location of the last pixel where the linear scaling is ended. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VIP_CFG_SC9,VIP_CFG_SC9" hexmask.long 0x0 0.--31. 1. " CFG_LIN_ACC_INC ,This parameter is used by horizontal scaling. It defines the increment of the linear accumulator. if SR 0.5 then lin_acc_inc = round(2^24*(srcWi -1) /(tarWi -1)) else if 0.25 SR ? 0.5 lin_acc_inc = round(2^24*(srcWi/2 -1) /(tarWi - 1)) else if SR ? 0.25 lin_acc_inc = round(2^24*(srcWi/4 -1) /(tarWi - 1)) where srcWi and tarWi are the inner source width and the inner target width respectively." group.byte 0x28++0x3 line.long 0x0 "VIP_CFG_SC10,VIP_CFG_SC10" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INIT ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the initialization value of the nonlinear accumulator. nlin_acc_init = K*(1-2*d) Here the definitions of K and d are the same as in CFG_SC11" group.byte 0x2C++0x3 line.long 0x0 "VIP_CFG_SC11,VIP_CFG_SC11" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INC ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the increment of the nonlinear accumulator. if upscaling then d = 0 if Ltar !=0 then K =round[2^24*Lsrc/(Ltar*Ltar) ] where Lsrc= (srcW-srcWi)/2 else K = 0 elseif downscaling d = (tarW-1)/2 if Ltar!=0 then K = round[ 2^24 * Lsrc / (Ltar*(Ltar-2d))] where Lsrc= (srcW-srcWi)/(2n) and n=1..2 or 4 else K = 0 nlin_acc_inc = 2*K (negative for downscaling)" group.byte 0x30++0x3 line.long 0x0 "VIP_CFG_SC12,VIP_CFG_SC12" hexmask.long 0x0 0.--24. 1. " CFG_COL_ACC_OFFSET ,This parameter is used in horizontal scaling. It defines the luma accumulator's offset. Normally this parameter can be set as 0 if no horizontal offset is involved. In some applications.. such as Pan and Scan.. a corresponding offset value should be set. The format is 1.24." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_CFG_SC13,VIP_CFG_SC13" hexmask.long.word 0x0 0.--9. 1. " CFG_SC_FACTOR_RAV ,This parameter is used by vertical scaling. Vertical scaling factor: It is defined as following: 1024*tarH/srcH. It is used for downscaling by the running average filter" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "VIP_CFG_SC18,VIP_CFG_SC18" hexmask.long.word 0x0 0.--9. 1. " CFG_HS_FACTOR ,This parameter is used by horizontal scaling. Horizontal-scaling-factor = tarWi/srcWi. Numerical format: 6.4 (6 bit integer and 4 bit fraction)" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "VIP_CFG_SC19,VIP_CFG_SC19" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF0 ,This parameter is used by the peaking block. Defines the coefficient 0 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF1 ,This parameter is used by the peaking block. Defines the coefficient 1 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_HPF_COEF2 ,This parameter is used by the peaking block. Defines the coefficient 2 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 24.--31. 1. " CFG_HPF_COEF3 ,This parameter is used by the peaking block. Defines the coefficient 3 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." group.byte 0x50++0x3 line.long 0x0 "VIP_CFG_SC20,VIP_CFG_SC20" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF4 ,This parameter is used by the peaking block. Defines the coefficient 4 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF5 ,This parameter is used by the peaking block. Defines the coefficient 5 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " bitfld.long 0x0 16.--18. " CFG_HPF_NORM_SHIFT ,This parameter is used by the peaking block. Defines the decimal point of the hpf coefficient." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 20.--28. 1. " CFG_NL_LIMIT ,This parameter is used by the peaking block. The maximum of clipping." bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x54++0x3 line.long 0x0 "VIP_CFG_SC21,VIP_CFG_SC21" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_LO_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be 0" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_NL_LO_SLOPE ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The format is fixed point 4.4." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "VIP_CFG_SC22,VIP_CFG_SC22" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_HI_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be nl_hi_thr." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The gain is 2^(nl_hi_slope_shift-3)." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "VIP_CFG_SC24,VIP_CFG_SC24" hexmask.long.word 0x0 0.--10. 1. " CFG_ORG_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_ORG_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_CFG_SC25,VIP_CFG_SC25" hexmask.long.word 0x0 0.--10. 1. " CFG_OFF_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_OFF_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "VIP3_Slice0_sc" base ad:0x489B5800 width 14. group.byte 0x0++0x3 line.long 0x0 "VIP_CFG_SC0,VIP_CFG_SC0" bitfld.long 0x0 0. " CFG_INTERLACE_O ,This parameter is used by vertical scaling. 0: The output format of SC is progressive 1: The output format of SC is interlace" "0,1" bitfld.long 0x0 1. " CFG_LINEAR ,This parameter is used by horizontal scaling. 0: Anamorphic scaling 1: Linear scaling" "0,1" textline " " bitfld.long 0x0 2. " CFG_SC_BYPASS ,This parameter is a general purpose. 0: Scaling module will engaged 1: Scaling module will be bypassed" "0,1" bitfld.long 0x0 3. " CFG_INVT_FID ,This parameter is used by vertical scaling. 0: Progressive input 1: Interlaced input Must be set to 1 when CFG_INTERFACE_I = 1." "0,1" textline " " bitfld.long 0x0 4. " CFG_USE_RAV ,This parameter is used by vertical scaling. 0: Poly-phase filter will be used for the vertical scaling 1: Running average filter will be used for the vertical scaling (down scaling only)" "0,1" bitfld.long 0x0 5. " CFG_ENABLE_EV ,This parameter is used by the edge-detection block. 0: The output of edge-detection block will be force to ?0? 1: The calculation results of edge-detection block will be output normally" "0,1" textline " " bitfld.long 0x0 6. " CFG_AUTO_HS ,This parameter is used by horizontal scaling. 0: the cfg_dcm_2x and cfg_dcm_4x bits will enable appropriate decimation filters 1: HW will decide whether up-scaling or down-scaling is required based on horizontal scaling ratio (SR). SR 0.5 : horizontal polyphase filter is enabled, all decimation filters are disabled SR = 0.5 : dcm_2x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.5 SR 0.25 : dcm_2x and horizontal polyphase filter both are enabled SR = 0.25 : dcm_4x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.25 SR 0.125 : dcm_4x and horizontal polyphase filter are both enabled SR = 0.125 : Functionally supported, but not recommended in auto mode for image quality concerns" "0,1" bitfld.long 0x0 7. " CFG_DCM_2X ,This parameter is used by horizontal scaling. 0: the 2X decimation filter is disabled 1: the 2X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (0.25 horizontal scale ratio 0.5). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" textline " " bitfld.long 0x0 8. " CFG_DCM_4X ,This parameter is used by horizontal scaling. 0: the 4X decimation filter is disabled 1: the 4X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (horizontal scale ratio 0.25). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" bitfld.long 0x0 9. " CFG_HP_BYPASS ,This parameter is used by horizontal scaling. If cfg_auto_hs is 0, horizontal polyphase filter is always enabled. In this case, this register is DON?T CARE. If cfg_auto_hs is 1, 0 : The polyphase scaler is always used regardless of the scaling ratio. 1 : The polyphase scaler is bypassed only when (tar_w == src_w) or (tar_w == src_w/2) or (tar_w == src_w/4)" "0,1" textline " " bitfld.long 0x0 10. " CFG_INTERLACE_I ,This parameter is used by both horizontal and vertical scaling 0: the input video format is progressive 1: the input video format is interlace" "0,1" bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 14. " CFG_Y_PK_EN ,This parameter is used by peaking block. 0: disable luma peaking 1: enable luma peaking" "0,1" bitfld.long 0x0 15. " CFG_TRIM ,Trimming enable. When 1, the input image whose size is specified by orgW and orgH registers is trimmed to the size with srcW and srcH from the offset specified by offW and offH. 0: disable trimming 1: enable trimming" "0,1" textline " " bitfld.long 0x0 16. " CFG_FID_SELFGEN ,FID self generate enable. When input is progressive and this bit is set, the SC generates self-toggling (top/bottom) output FID when performing interlacing." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_CFG_SC1,VIP_CFG_SC1" hexmask.long 0x0 0.--26. 1. " CFG_ROW_ACC_INC ,This parameter is used by vertical scaling. It defines the increment of the row accumulator in vertical poly-phase filter. It can be calculated by following formula: row_acc_inc = round(2^16 *(src_h)/(tar_h)) In case of interlaced input, srcH is input field height In case of interlaced output, tarH is output field height." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8++0x3 line.long 0x0 "VIP_CFG_SC2,VIP_CFG_SC2" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this offset will be applied to a frame. In interlace mode: this offset will be applied to the top field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC++0x3 line.long 0x0 "VIP_CFG_SC3,VIP_CFG_SC3" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this parameter will not be used. In interlace mode: this offset will be applied to the bottom field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10++0x3 line.long 0x0 "VIP_CFG_SC4,VIP_CFG_SC4" hexmask.long.word 0x0 0.--10. 1. " CFG_TAR_H ,This parameter is a general purpose. Scaled target picture height.. unit is line... This parameter defines the final output picture size. For the interlace output.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_TAR_W ,This parameter is a general purpose. Scaled target picture width. unit is pixel. This parameter defines the final output picture size" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_LIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'lin_acc_inc' that is defined in CFG_SC9" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " CFG_NLIN_ACC_INIT_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'nlin_acc_init' that is defined in CFG_SC10" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "VIP_CFG_SC5,VIP_CFG_SC5" hexmask.long.word 0x0 0.--10. 1. " CFG_SRC_H ,This parameter is a general purpose. This parameter defines the height of the source image. For the interlace input.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_SRC_W ,This parameter is a general purpose. This parameter defines the width of the source image" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_NLIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of ?nlin_acc_inc? that is defined in CFG_SC11" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x18++0x3 line.long 0x0 "VIP_CFG_SC6,VIP_CFG_SC6" hexmask.long.word 0x0 0.--9. 1. " CFG_ROW_ACC_INIT_RAV ,This parameter is used by vertical scaling. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for progressive format or top field of interlace format)" hexmask.long.word 0x0 10.--19. 1. " CFG_ROW_ACC_INIT_RAV_B ,This parameter is used by vertical scaling. it is used only when the input is interlace format. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for bottom field of interlace format)" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_CFG_SC8,VIP_CFG_SC8" hexmask.long.word 0x0 0.--10. 1. " CFG_NLIN_LEFT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on left-hand side. In other words. it defines the location of the last pixel in the left-sidenonlinear strip. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_NLIN_RIGHT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on right-hand side. In other words. it defines the location of the last pixel where the linear scaling is ended. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VIP_CFG_SC9,VIP_CFG_SC9" hexmask.long 0x0 0.--31. 1. " CFG_LIN_ACC_INC ,This parameter is used by horizontal scaling. It defines the increment of the linear accumulator. if SR 0.5 then lin_acc_inc = round(2^24*(srcWi -1) /(tarWi -1)) else if 0.25 SR ? 0.5 lin_acc_inc = round(2^24*(srcWi/2 -1) /(tarWi - 1)) else if SR ? 0.25 lin_acc_inc = round(2^24*(srcWi/4 -1) /(tarWi - 1)) where srcWi and tarWi are the inner source width and the inner target width respectively." group.byte 0x28++0x3 line.long 0x0 "VIP_CFG_SC10,VIP_CFG_SC10" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INIT ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the initialization value of the nonlinear accumulator. nlin_acc_init = K*(1-2*d) Here the definitions of K and d are the same as in CFG_SC11" group.byte 0x2C++0x3 line.long 0x0 "VIP_CFG_SC11,VIP_CFG_SC11" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INC ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the increment of the nonlinear accumulator. if upscaling then d = 0 if Ltar !=0 then K =round[2^24*Lsrc/(Ltar*Ltar) ] where Lsrc= (srcW-srcWi)/2 else K = 0 elseif downscaling d = (tarW-1)/2 if Ltar!=0 then K = round[ 2^24 * Lsrc / (Ltar*(Ltar-2d))] where Lsrc= (srcW-srcWi)/(2n) and n=1..2 or 4 else K = 0 nlin_acc_inc = 2*K (negative for downscaling)" group.byte 0x30++0x3 line.long 0x0 "VIP_CFG_SC12,VIP_CFG_SC12" hexmask.long 0x0 0.--24. 1. " CFG_COL_ACC_OFFSET ,This parameter is used in horizontal scaling. It defines the luma accumulator's offset. Normally this parameter can be set as 0 if no horizontal offset is involved. In some applications.. such as Pan and Scan.. a corresponding offset value should be set. The format is 1.24." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_CFG_SC13,VIP_CFG_SC13" hexmask.long.word 0x0 0.--9. 1. " CFG_SC_FACTOR_RAV ,This parameter is used by vertical scaling. Vertical scaling factor: It is defined as following: 1024*tarH/srcH. It is used for downscaling by the running average filter" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "VIP_CFG_SC18,VIP_CFG_SC18" hexmask.long.word 0x0 0.--9. 1. " CFG_HS_FACTOR ,This parameter is used by horizontal scaling. Horizontal-scaling-factor = tarWi/srcWi. Numerical format: 6.4 (6 bit integer and 4 bit fraction)" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "VIP_CFG_SC19,VIP_CFG_SC19" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF0 ,This parameter is used by the peaking block. Defines the coefficient 0 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF1 ,This parameter is used by the peaking block. Defines the coefficient 1 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_HPF_COEF2 ,This parameter is used by the peaking block. Defines the coefficient 2 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 24.--31. 1. " CFG_HPF_COEF3 ,This parameter is used by the peaking block. Defines the coefficient 3 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." group.byte 0x50++0x3 line.long 0x0 "VIP_CFG_SC20,VIP_CFG_SC20" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF4 ,This parameter is used by the peaking block. Defines the coefficient 4 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF5 ,This parameter is used by the peaking block. Defines the coefficient 5 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " bitfld.long 0x0 16.--18. " CFG_HPF_NORM_SHIFT ,This parameter is used by the peaking block. Defines the decimal point of the hpf coefficient." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 20.--28. 1. " CFG_NL_LIMIT ,This parameter is used by the peaking block. The maximum of clipping." bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x54++0x3 line.long 0x0 "VIP_CFG_SC21,VIP_CFG_SC21" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_LO_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be 0" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_NL_LO_SLOPE ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The format is fixed point 4.4." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "VIP_CFG_SC22,VIP_CFG_SC22" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_HI_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be nl_hi_thr." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The gain is 2^(nl_hi_slope_shift-3)." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "VIP_CFG_SC24,VIP_CFG_SC24" hexmask.long.word 0x0 0.--10. 1. " CFG_ORG_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_ORG_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_CFG_SC25,VIP_CFG_SC25" hexmask.long.word 0x0 0.--10. 1. " CFG_OFF_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_OFF_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "VIP3_Slice1_sc" base ad:0x489B5D00 width 14. group.byte 0x0++0x3 line.long 0x0 "VIP_CFG_SC0,VIP_CFG_SC0" bitfld.long 0x0 0. " CFG_INTERLACE_O ,This parameter is used by vertical scaling. 0: The output format of SC is progressive 1: The output format of SC is interlace" "0,1" bitfld.long 0x0 1. " CFG_LINEAR ,This parameter is used by horizontal scaling. 0: Anamorphic scaling 1: Linear scaling" "0,1" textline " " bitfld.long 0x0 2. " CFG_SC_BYPASS ,This parameter is a general purpose. 0: Scaling module will engaged 1: Scaling module will be bypassed" "0,1" bitfld.long 0x0 3. " CFG_INVT_FID ,This parameter is used by vertical scaling. 0: Progressive input 1: Interlaced input Must be set to 1 when CFG_INTERFACE_I = 1." "0,1" textline " " bitfld.long 0x0 4. " CFG_USE_RAV ,This parameter is used by vertical scaling. 0: Poly-phase filter will be used for the vertical scaling 1: Running average filter will be used for the vertical scaling (down scaling only)" "0,1" bitfld.long 0x0 5. " CFG_ENABLE_EV ,This parameter is used by the edge-detection block. 0: The output of edge-detection block will be force to ?0? 1: The calculation results of edge-detection block will be output normally" "0,1" textline " " bitfld.long 0x0 6. " CFG_AUTO_HS ,This parameter is used by horizontal scaling. 0: the cfg_dcm_2x and cfg_dcm_4x bits will enable appropriate decimation filters 1: HW will decide whether up-scaling or down-scaling is required based on horizontal scaling ratio (SR). SR 0.5 : horizontal polyphase filter is enabled, all decimation filters are disabled SR = 0.5 : dcm_2x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.5 SR 0.25 : dcm_2x and horizontal polyphase filter both are enabled SR = 0.25 : dcm_4x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass 0.25 SR 0.125 : dcm_4x and horizontal polyphase filter are both enabled SR = 0.125 : Functionally supported, but not recommended in auto mode for image quality concerns" "0,1" bitfld.long 0x0 7. " CFG_DCM_2X ,This parameter is used by horizontal scaling. 0: the 2X decimation filter is disabled 1: the 2X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (0.25 horizontal scale ratio 0.5). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" textline " " bitfld.long 0x0 8. " CFG_DCM_4X ,This parameter is used by horizontal scaling. 0: the 4X decimation filter is disabled 1: the 4X decimation filter is enabled Note: (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (horizontal scale ratio 0.25). (3) This register is DON?T CARE when cfg_auto_hs = 1." "0,1" bitfld.long 0x0 9. " CFG_HP_BYPASS ,This parameter is used by horizontal scaling. If cfg_auto_hs is 0, horizontal polyphase filter is always enabled. In this case, this register is DON?T CARE. If cfg_auto_hs is 1, 0 : The polyphase scaler is always used regardless of the scaling ratio. 1 : The polyphase scaler is bypassed only when (tar_w == src_w) or (tar_w == src_w/2) or (tar_w == src_w/4)" "0,1" textline " " bitfld.long 0x0 10. " CFG_INTERLACE_I ,This parameter is used by both horizontal and vertical scaling 0: the input video format is progressive 1: the input video format is interlace" "0,1" bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 14. " CFG_Y_PK_EN ,This parameter is used by peaking block. 0: disable luma peaking 1: enable luma peaking" "0,1" bitfld.long 0x0 15. " CFG_TRIM ,Trimming enable. When 1, the input image whose size is specified by orgW and orgH registers is trimmed to the size with srcW and srcH from the offset specified by offW and offH. 0: disable trimming 1: enable trimming" "0,1" textline " " bitfld.long 0x0 16. " CFG_FID_SELFGEN ,FID self generate enable. When input is progressive and this bit is set, the SC generates self-toggling (top/bottom) output FID when performing interlacing." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VIP_CFG_SC1,VIP_CFG_SC1" hexmask.long 0x0 0.--26. 1. " CFG_ROW_ACC_INC ,This parameter is used by vertical scaling. It defines the increment of the row accumulator in vertical poly-phase filter. It can be calculated by following formula: row_acc_inc = round(2^16 *(src_h)/(tar_h)) In case of interlaced input, srcH is input field height In case of interlaced output, tarH is output field height." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8++0x3 line.long 0x0 "VIP_CFG_SC2,VIP_CFG_SC2" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this offset will be applied to a frame. In interlace mode: this offset will be applied to the top field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC++0x3 line.long 0x0 "VIP_CFG_SC3,VIP_CFG_SC3" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this parameter will not be used. In interlace mode: this offset will be applied to the bottom field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10++0x3 line.long 0x0 "VIP_CFG_SC4,VIP_CFG_SC4" hexmask.long.word 0x0 0.--10. 1. " CFG_TAR_H ,This parameter is a general purpose. Scaled target picture height.. unit is line... This parameter defines the final output picture size. For the interlace output.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_TAR_W ,This parameter is a general purpose. Scaled target picture width. unit is pixel. This parameter defines the final output picture size" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_LIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'lin_acc_inc' that is defined in CFG_SC9" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " CFG_NLIN_ACC_INIT_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'nlin_acc_init' that is defined in CFG_SC10" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "VIP_CFG_SC5,VIP_CFG_SC5" hexmask.long.word 0x0 0.--10. 1. " CFG_SRC_H ,This parameter is a general purpose. This parameter defines the height of the source image. For the interlace input.. it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_SRC_W ,This parameter is a general purpose. This parameter defines the width of the source image" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_NLIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of ?nlin_acc_inc? that is defined in CFG_SC11" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x18++0x3 line.long 0x0 "VIP_CFG_SC6,VIP_CFG_SC6" hexmask.long.word 0x0 0.--9. 1. " CFG_ROW_ACC_INIT_RAV ,This parameter is used by vertical scaling. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for progressive format or top field of interlace format)" hexmask.long.word 0x0 10.--19. 1. " CFG_ROW_ACC_INIT_RAV_B ,This parameter is used by vertical scaling. it is used only when the input is interlace format. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for bottom field of interlace format)" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VIP_CFG_SC8,VIP_CFG_SC8" hexmask.long.word 0x0 0.--10. 1. " CFG_NLIN_LEFT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on left-hand side. In other words. it defines the location of the last pixel in the left-sidenonlinear strip. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_NLIN_RIGHT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on right-hand side. In other words. it defines the location of the last pixel where the linear scaling is ended. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VIP_CFG_SC9,VIP_CFG_SC9" hexmask.long 0x0 0.--31. 1. " CFG_LIN_ACC_INC ,This parameter is used by horizontal scaling. It defines the increment of the linear accumulator. if SR 0.5 then lin_acc_inc = round(2^24*(srcWi -1) /(tarWi -1)) else if 0.25 SR ? 0.5 lin_acc_inc = round(2^24*(srcWi/2 -1) /(tarWi - 1)) else if SR ? 0.25 lin_acc_inc = round(2^24*(srcWi/4 -1) /(tarWi - 1)) where srcWi and tarWi are the inner source width and the inner target width respectively." group.byte 0x28++0x3 line.long 0x0 "VIP_CFG_SC10,VIP_CFG_SC10" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INIT ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the initialization value of the nonlinear accumulator. nlin_acc_init = K*(1-2*d) Here the definitions of K and d are the same as in CFG_SC11" group.byte 0x2C++0x3 line.long 0x0 "VIP_CFG_SC11,VIP_CFG_SC11" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INC ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the increment of the nonlinear accumulator. if upscaling then d = 0 if Ltar !=0 then K =round[2^24*Lsrc/(Ltar*Ltar) ] where Lsrc= (srcW-srcWi)/2 else K = 0 elseif downscaling d = (tarW-1)/2 if Ltar!=0 then K = round[ 2^24 * Lsrc / (Ltar*(Ltar-2d))] where Lsrc= (srcW-srcWi)/(2n) and n=1..2 or 4 else K = 0 nlin_acc_inc = 2*K (negative for downscaling)" group.byte 0x30++0x3 line.long 0x0 "VIP_CFG_SC12,VIP_CFG_SC12" hexmask.long 0x0 0.--24. 1. " CFG_COL_ACC_OFFSET ,This parameter is used in horizontal scaling. It defines the luma accumulator's offset. Normally this parameter can be set as 0 if no horizontal offset is involved. In some applications.. such as Pan and Scan.. a corresponding offset value should be set. The format is 1.24." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VIP_CFG_SC13,VIP_CFG_SC13" hexmask.long.word 0x0 0.--9. 1. " CFG_SC_FACTOR_RAV ,This parameter is used by vertical scaling. Vertical scaling factor: It is defined as following: 1024*tarH/srcH. It is used for downscaling by the running average filter" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "VIP_CFG_SC18,VIP_CFG_SC18" hexmask.long.word 0x0 0.--9. 1. " CFG_HS_FACTOR ,This parameter is used by horizontal scaling. Horizontal-scaling-factor = tarWi/srcWi. Numerical format: 6.4 (6 bit integer and 4 bit fraction)" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "VIP_CFG_SC19,VIP_CFG_SC19" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF0 ,This parameter is used by the peaking block. Defines the coefficient 0 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF1 ,This parameter is used by the peaking block. Defines the coefficient 1 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_HPF_COEF2 ,This parameter is used by the peaking block. Defines the coefficient 2 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 24.--31. 1. " CFG_HPF_COEF3 ,This parameter is used by the peaking block. Defines the coefficient 3 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." group.byte 0x50++0x3 line.long 0x0 "VIP_CFG_SC20,VIP_CFG_SC20" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF4 ,This parameter is used by the peaking block. Defines the coefficient 4 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF5 ,This parameter is used by the peaking block. Defines the coefficient 5 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " bitfld.long 0x0 16.--18. " CFG_HPF_NORM_SHIFT ,This parameter is used by the peaking block. Defines the decimal point of the hpf coefficient." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 20.--28. 1. " CFG_NL_LIMIT ,This parameter is used by the peaking block. The maximum of clipping." bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x54++0x3 line.long 0x0 "VIP_CFG_SC21,VIP_CFG_SC21" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_LO_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be 0" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_NL_LO_SLOPE ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The format is fixed point 4.4." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "VIP_CFG_SC22,VIP_CFG_SC22" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_HI_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be nl_hi_thr." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The gain is 2^(nl_hi_slope_shift-3)." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "VIP_CFG_SC24,VIP_CFG_SC24" hexmask.long.word 0x0 0.--10. 1. " CFG_ORG_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_ORG_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VIP_CFG_SC25,VIP_CFG_SC25" hexmask.long.word 0x0 0.--10. 1. " CFG_OFF_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_OFF_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "VPE_CSC" base ad:0x489D5700 width 11. group.byte 0x0++0x3 line.long 0x0 "VPE_CSC00,VPE_CSC00" hexmask.long.word 0x0 0.--12. 1. " A0 ,Its is represented as Q3.10 number. So the value ranges from -4 to +4. To convert a decimal number, multiply the number by 1024 and write it in the register in hex format. For example, to program 0.673, 0x2B1 should be written in the register. (int)(0.673 X 1024) = (int)689.152 = 689 = 0x2B1. If the real number is negative, then multiply it by 1024, and convert it to 2's compliment format in 12-bit. For example, if a coefficient is - 1.893, 0x186E needs to be written in the register. (int)(-1.893*1024)= -1938 = 0x186E (2'S compliment format of -1938 in 13-bit width)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B0 ,Coefficients of color space converter. This coefficient is a real number in the range of -4. to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 inVPE_CSC00)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x4++0x3 line.long 0x0 "VPE_CSC01,VPE_CSC01" hexmask.long.word 0x0 0.--12. 1. " C0 ,Coefficients of color space converter. This coefficient is a real number in the range of -4. to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 inVPE_CSC00)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " A1 ,Coefficients of color space converter. This coefficient is a real number in the range of -4. to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 inVPE_CSC00)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x8++0x3 line.long 0x0 "VPE_CSC02,VPE_CSC02" hexmask.long.word 0x0 0.--12. 1. " B1 ,Coefficients of color space converter. This coefficient is a real number in the range of -4. to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 inVPE_CSC00)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " C1 ,Coefficients of color space converter. This coefficient is a real number in the range of -4. to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 inVPE_CSC00)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0xC++0x3 line.long 0x0 "VPE_CSC03,VPE_CSC03" hexmask.long.word 0x0 0.--12. 1. " A2 ,Coefficients of color space converter. This coefficient is a real number in the range of -4. to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 inVPE_CSC00)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " B2 ,Coefficients of color space converter. This coefficient is a real number in the range of -4. to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 inVPE_CSC00)" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x10++0x3 line.long 0x0 "VPE_CSC04,VPE_CSC04" hexmask.long.word 0x0 0.--12. 1. " C2 ,Coefficients of color space converter. This coefficient is a real number in the range of -4. to +4 represent in Q3.10 format. The MSB is sign bit. (Same format conversion as A0 inVPE_CSC00)" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--27. 1. " D0 ,Coefficients of color space converter. This coefficient is an integer number in the range of 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. For example, if this coefficient is 749, then 0x2ED (hex format) should be assigned to this register. Another example, if this coefficient is -1021, then 0xC03 should be assigned to this register." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x14++0x3 line.long 0x0 "VPE_CSC05,VPE_CSC05" hexmask.long.word 0x0 0.--11. 1. " D1 ,Coefficients of color space converter. This coefficient is an integer number in the range of -2048 to 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0 inVPE_CSC04)" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--27. 1. " D2 ,Coefficients of color space converter. This coefficient is an integer number in the range of -2048 to 2048. It is in 12-bit wide 2's compliment format. The MSB is sign bit. (Same format conversion as D0 inVPE_CSC04)" bitfld.long 0x0 28. " BYPASS ,Full CSC bypass mode" "0,1" textline " " bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "VPE_SC" base ad:0x489D0700 width 14. group.byte 0x0++0x3 line.long 0x0 "VPE_CFG_SC0,VPE_CFG_SC0" bitfld.long 0x0 0. " CFG_INTERLACE_O ,This parameter is used by vertical scaling." "0,1" bitfld.long 0x0 1. " CFG_LINEAR ,This parameter is used by horizontal scaling." "0,1" textline " " bitfld.long 0x0 2. " CFG_SC_BYPASS ,This parameter is general purpose." "0,1" bitfld.long 0x0 3. " CFG_INVT_FID ,This parameter is used by vertical scaling." "0,1" textline " " bitfld.long 0x0 4. " CFG_USE_RAV ,This parameter is used by vertical scaling." "0,1" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " CFG_AUTO_HS ,This parameter is used by horizontal scaling.SR > 0.5 : horizontal polyphase filter is enabled, all decimation filters are disabled . SR = 0.5 : dcm_2x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass . 0.5 > SR > 0.25 : dcm_2x and horizontal polyphase filter both are enabled . SR = 0.25 : dcm_4x is enabled, horizontal polyphase filter is enabled or disabled based on cfg_hp_bypass . 0.25 > SR > 0.125 : dcm_4x and horizontal polyphase filter are both enabled . SR <= 0.125 : Functionally supported, but not recommended in auto mode for image quality concerns ." "0,1" bitfld.long 0x0 7. " CFG_DCM_2X ,This parameter is used by horizontal scaling.Note: . (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. . (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (0.25 < horizontal scale ratio < 0.5). . (3) This register is DON'T CARE when cfg_auto_hs = 1. ." "0,1" textline " " bitfld.long 0x0 8. " CFG_DCM_4X ,This parameter is used by horizontal scaling.Note: . (1) Either 2X or 4X can be enabled, but they cannot be enabled simultaneously. . (2) This register is only set to 1 when it makes sense to do so. Typically, it is used when (horizontal scale ratio < 0.25). . (3) This register is DON'T CARE when cfg_auto_hs = 1 ." "0,1" bitfld.long 0x0 9. " CFG_HP_BYPASS ,This parameter is used by horizontal scaling. If cfg_auto_hs is 0, horizontal polyphase filter is always enabled. In this case, this register is DON'T CARE. If cfg_auto_hs is 1, then:" "0,1" textline " " bitfld.long 0x0 10. " CFG_INTERLACE_I ,This parameter is used by horizontal and vertical scaling." "0,1" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" bitfld.long 0x0 14. " CFG_Y_PK_EN ,This parameter is used by peaking block." "0,1" textline " " bitfld.long 0x0 15. " CFG_TRIM ,Trimming enable. When 1, the input image whose size is specified by orgW and orgH registers is trimmed to the size with srcW and srcH from the offset specified by offW and offH." "0,1" bitfld.long 0x0 16. " CFG_FID_SELFGEN ,FID self generate enable. When input is progressive and this bit is set, the SC generates self-toggling (top/bottom) output FID when performing interlacing." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "VPE_CFG_SC1,VPE_CFG_SC1" hexmask.long 0x0 0.--26. 1. " CFG_ROW_ACC_INC ,This parameter is used by vertical scaling. It defines the increment of the row accumulator in vertical poly-phase filter. It can be calculated by following formulas:For progressive in/progressive out row_acc_inc = round(2^16*(src_h-1)/(tar_h - 1)) . For progressive_in/interlace_out row_acc_inc = round(2^16*2*(src_h-1)/(2*tar_h - 1)) . For interlace_in/progressive_out row_acc_inc = round(2^16*(2*src_h-1)/(2*(tar_h - 1))) . For interlace_in/interlace_out row_acc_inc = round(2^16*(2*src_h - 1)/(2*tar_h - 1)) . In case of interlaced input, srcH is input field height (number of field lines), as specified in. In case of interlaced output, tarH is output field height (number of field lines), as specified in . ." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8++0x3 line.long 0x0 "VPE_CFG_SC2,VPE_CFG_SC2" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this offset will be applied to a frame. In interlace mode: this offset will be applied to the top field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC++0x3 line.long 0x0 "VPE_CFG_SC3,VPE_CFG_SC3" hexmask.long 0x0 0.--27. 1. " CFG_ROW_ACC_OFFSET_B ,This parameter is used by vertical scaling. It defines the vertical offset during vertical scaling. In progressive mode: this parameter will not be used. In interlace mode: this offset will be applied to the bottom field." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10++0x3 line.long 0x0 "VPE_CFG_SC4,VPE_CFG_SC4" hexmask.long.word 0x0 0.--10. 1. " CFG_TAR_H ,This parameter is a general purpose. Scaled target picture height (unit is line). This parameter defines the final output picture size. For the interlace output, it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_TAR_W ,This parameter is a general purpose. Scaled target picture width. unit is pixel. This parameter defines the final output picture size" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_LIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'lin_acc_inc' that is defined in CFG_SC9" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " CFG_NLIN_ACC_INIT_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'nlin_acc_init' that is defined in CFG_SC10" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "VPE_CFG_SC5,VPE_CFG_SC5" hexmask.long.word 0x0 0.--10. 1. " CFG_SRC_H ,This parameter is a general purpose. This parameter defines the height of the source image. For the interlace input, it should be the number of lines per field." bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_SRC_W ,This parameter is a general purpose. This parameter defines the width of the source image" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " CFG_NLIN_ACC_INC_U ,This parameter is used by horizontal scaling. The 3 MSBbits of 'nlin_acc_inc' that is defined in CFG_SC11" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x18++0x3 line.long 0x0 "VPE_CFG_SC6,VPE_CFG_SC6" hexmask.long.word 0x0 0.--9. 1. " CFG_ROW_ACC_INIT_RAV ,This parameter is used by vertical scaling. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for progressive format or top field of interlace format)" hexmask.long.word 0x0 10.--19. 1. " CFG_ROW_ACC_INIT_RAV_B ,This parameter is used by vertical scaling. it is used only when the input is interlace format. In vertical down scaling.. the running average filter is applied. This parameter sets the initialization value of the row accumulator in running average filter (for bottom field of interlace format)" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VPE_CFG_SC8,VPE_CFG_SC8" hexmask.long.word 0x0 0.--10. 1. " CFG_NLIN_LEFT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on left-hand side. In other words. it defines the location of the last pixel in the left-sidenonlinear strip. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 12.--22. 1. " CFG_NLIN_RIGHT ,This parameter is used by horizontal scaling. In anamorphic mode. this parameter defines the width of the strip on right-hand side. In other words. it defines the location of the last pixel where the linear scaling is ended. The unit is the 'pixel location' in an active video line. This parameter will not be used in linear scaling" hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VPE_CFG_SC9,VPE_CFG_SC9" hexmask.long 0x0 0.--31. 1. " CFG_LIN_ACC_INC ,This parameter is used by horizontal scaling. It defines the increment of the linear accumulator. if SR > 0.5, then else if 0.25 < SR <= 0.5 else if SR <= 0.25 where srcWi and tarWi are the inner source width and the inner target width respectively." group.byte 0x28++0x3 line.long 0x0 "VPE_CFG_SC10,VPE_CFG_SC10" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INIT ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the initialization value of the nonlinear accumulator. nlin_acc_init = K*(1-2*d) Here the definitions of K and d are the same as in CFG_SC11" group.byte 0x2C++0x3 line.long 0x0 "VPE_CFG_SC11,VPE_CFG_SC11" hexmask.long 0x0 0.--31. 1. " CFG_NLIN_ACC_INC ,This parameter is used by horizontal scaling. It is used by nonlinear scaling only. It defines the increment of the nonlinear accumulator. if upscaling then d = 0 if Ltar !=0 then K =round[2*Lsrc/(Ltar*Ltar) ] where Lsrc= (srcW-srcWi)/2 else K = 0 elseif downscaling d = (tarW-1)/2 if Ltar!=0 then K = round[ 2 * Lsrc / (Ltar*(Ltar-2d))] where Lsrc= (srcW-srcWi)/(2n) and n=1..2 or 4 else K = 0 nlin_acc_inc = 2*K (negative for downscaling)" group.byte 0x30++0x3 line.long 0x0 "VPE_CFG_SC12,VPE_CFG_SC12" hexmask.long 0x0 0.--24. 1. " CFG_COL_ACC_OFFSET ,This parameter is used in horizontal scaling. It defines the luma accumulator's offset. Normally this parameter can be set as 0 if no horizontal offset is involved. In some applications, such as Pan and Scan. A corresponding offset value should be set. The format is 1.24." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VPE_CFG_SC13,VPE_CFG_SC13" hexmask.long.word 0x0 0.--9. 1. " CFG_SC_FACTOR_RAV ,This parameter is used by vertical scaling. Vertical scaling factor: It is defined as following: 1024*tarH/srcH. It is used for downscaling by the running average filter" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "VPE_CFG_SC18,VPE_CFG_SC18" hexmask.long.word 0x0 0.--9. 1. " CFG_HS_FACTOR ,This parameter is used by horizontal scaling. Horizontal-scaling-factor = tarWi/srcWi. Numerical format: 6.4 (6 bit integer and 4 bit fraction)" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "VPE_CFG_SC19,VPE_CFG_SC19" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF0 ,This parameter is used by the peaking block. Defines the coefficient 0 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF1 ,This parameter is used by the peaking block. Defines the coefficient 1 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_HPF_COEF2 ,This parameter is used by the peaking block. Defines the coefficient 2 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 24.--31. 1. " CFG_HPF_COEF3 ,This parameter is used by the peaking block. Defines the coefficient 3 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." group.byte 0x50++0x3 line.long 0x0 "VPE_CFG_SC20,VPE_CFG_SC20" hexmask.long.byte 0x0 0.--7. 1. " CFG_HPF_COEF4 ,This parameter is used by the peaking block. Defines the coefficient 4 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." hexmask.long.byte 0x0 8.--15. 1. " CFG_HPF_COEF5 ,This parameter is used by the peaking block. Defines the coefficient 5 of the HPF used in the peaking filter. Signed. Decimal point is defined by hpf_norm_shift." textline " " bitfld.long 0x0 16.--18. " CFG_HPF_NORM_SHIFT ,This parameter is used by the peaking block. Defines the decimal point of the hpf coefficient." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 20.--28. 1. " CFG_NL_LIMIT ,This parameter is used by the peaking block. The maximum of clipping." bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x54++0x3 line.long 0x0 "VPE_CFG_SC21,VPE_CFG_SC21" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_LO_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be 0" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " CFG_NL_LO_SLOPE ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The format is fixed point 4.4." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "VPE_CFG_SC22,VPE_CFG_SC22" hexmask.long.word 0x0 0.--8. 1. " CFG_NL_HI_THR ,This parameter is used by the peaking block. Threshold for the nonlinear peaking function. Must be nl_hi_thr." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " CFG_NL_HI_SLOPE_SHIFT ,This parameter is used by the peaking block. Slope of the nonlinear peaking function. The gain is 2." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "VPE_CFG_SC24,VPE_CFG_SC24" hexmask.long.word 0x0 0.--10. 1. " CFG_ORG_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_ORG_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x64++0x3 line.long 0x0 "VPE_CFG_SC25,VPE_CFG_SC25" hexmask.long.word 0x0 0.--10. 1. " CFG_OFF_H ,This parameter is used by the trimmer. Vertical offset from the top of the original input image." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CFG_OFF_W ,This parameter is used by the trimmer. Horizontal offset from the left of the original input image." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "VPE_TOP_LEVEL" base ad:0x489D0000 width 28. group.byte 0x0++0x3 line.long 0x0 "VPE_CLKC_PID,VPE_CLKC_PID" hexmask.long 0x0 0.--31. 1. " PID ," group.byte 0x10++0x3 line.long 0x0 "VPE_SYSCONFIG,VPE_SYSCONFIG" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state 0x0: Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, i.e. regardless of the IP module's internal requirements. Backup mode, for debug only 0x1: No-idle mode: local target never enters idle state. Backup mode, for debug only 0x2: Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wakeup events 0x3: Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state. Mode is only relevant if the appropriate IP module 'swakeup' output(s) is (are) implemented" "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state 0x0: Force-standby mode: local initiator is unconditionally placed in standby state. Backup mode, for debug only 0x1: No-standby mode: local initiator is unconditionally placed out of standby state. Backup mode, for debug only 0x2: Same behavior as bit-field value of 0x1. 0x3: Reserved" "0,1,2,3" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "VPE_INTC_INTR0_STATUS_RAW0,VPE_INTC_INTR0_STATUS_RAW0" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_RAW ,VPDMA INT0 List0 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_RAW ,VPDMA INT0 List0 Notify Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_RAW ,VPDMA INT0 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_RAW ,VPDMA INT0 List1 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_RAW ,VPDMA INT0 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_RAW ,VPDMA INT0 List2 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_RAW ,VPDMA INT0 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_RAW ,VPDMA INT0 List3 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_RAW ,VPDMA INT0 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_RAW ,VPDMA INT0 List4 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_RAW ,VPDMA INT0 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_RAW ,VPDMA INT0 List5 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_RAW ,VPDMA INT0 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_RAW ,VPDMA INT0 List6 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_RAW ,VPDMA INT0 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_RAW ,VPDMA INT0 List7 Complete Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_RAW ,VPDMA INT0 Descriptor Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 17. " RESERVED ," "0,1" textline " " bitfld.long 0x0 18. " DEI_FMD_INT_RAW ,DEI Film Mode Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "VPE_INTC_INTR0_STATUS_RAW1,VPE_INTC_INTR0_STATUS_RAW1" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_RAW ,VPDMA INT0 Channel Group0 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_RAW ,VPDMA INT0 Channel Group1 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_RAW ,VPDMA INT0 Channel Group2 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_RAW ,VPDMA INT0 Channel Group3 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_RAW ,VPDMA INT0 Channel Group4 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_RAW ,VPDMA INT0 Channel Group5 Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_RAW ,VPDMA INT0 Client Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16. " DEI_ERROR_INT_RAW ,DEI Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 17.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_RAW ,VIP1 Chroma Downsampler 1 UV Error Interrupt Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "VPE_INTC_INTR0_STATUS_ENA0,VPE_INTC_INTR0_STATUS_ENA0" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA ,VPDMA INT0 List0 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA ,VPDMA INT0 List0 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA ,VPDMA INT0 List1 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA ,VPDMA INT0 List1 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA ,VPDMA INT0 List2 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA ,VPDMA INT0 List2 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA ,VPDMA INT0 List3 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA ,VPDMA INT0 List3 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA ,VPDMA INT0 List4 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA ,VPDMA INT0 List4 Notify Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA ,VPDMA INT0 List5 Complete Enabled Statust Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA ,VPDMA INT0 List5 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA ,VPDMA INT0 List6 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA ,VPDMA INT0 List6 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA ,VPDMA INT0 List7 Complete Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA ,VPDMA INT0 List7 Notify Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA ,VPDMA INT0 Descriptor Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17. " RESERVED ," "0,1" textline " " bitfld.long 0x0 18. " DEI_FMD_INT_ENA ,DEI Film Mode Enabled Status Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "VPE_INTC_INTR0_STATUS_ENA1,VPE_INTC_INTR0_STATUS_ENA1" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA ,VPDMA INT0 Channel Group0 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA ,VPDMA INT0 Channel Group1 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA ,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA ,VPDMA INT0 Channel Group3 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA ,VPDMA INT0 Channel Group4 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA ,VPDMA INT0 Channel Group5 Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA ,VPDMA INT0 Client Enabled Status Read indicates raw status 0 = inactive 1 = active Writing 1 will set status Writing 0 has no effect" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16. " DEI_ERROR_INT_ENA ,DEI Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 17.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA ,VIP1 Chroma Downsampler 1 UV Error Enabled Interrupt Status Read indicates enabled status 0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "VPE_INTC_INTR0_ENA_SET0,VPE_INTC_INTR0_ENA_SET0" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_SET ,VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_SET ,VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_SET ,VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_SET ,VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_SET ,VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_SET ,VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_SET ,VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_SET ,VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_SET ,VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_SET ,VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_SET ,VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_SET ,VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_SET ,VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_SET ,VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_SET ,VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_SET ,VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA_SET ,VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17. " RESERVED ," "0,1" textline " " bitfld.long 0x0 18. " DEI_FMD_INT_ENA_SET ,DEI Film Mode Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VPE_INTC_INTR0_ENA_SET1,VPE_INTC_INTR0_ENA_SET1" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_SET ,VPDMA INT0 Channel Group0 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_SET ,VPDMA INT0 Channel Group1 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_SET ,VPDMA INT0 Channel Group2 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_SET ,VPDMA INT0 Channel Group3 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_SET ,VPDMA INT0 Channel Group4 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_SET ,VPDMA INT0 Channel Group5 Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA_SET ,VPDMA INT0 Client Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16. " DEI_ERROR_INT_ENA_SET ,DEI Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 17.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_SET ,VIP1 Chroma Downsampler 1 UV Error Enable/Set Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "VPE_INTC_INTR0_ENA_CLR0,VPE_INTC_INTR0_ENA_CLR0" bitfld.long 0x0 0. " VPDMA_INT0_LIST0_COMPLETE_ENA_CLR ,VPDMA INT0 List0 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_LIST0_NOTIFY_ENA_CLR ,VPDMA INT0 List0 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_LIST1_COMPLETE_ENA_CLR ,VPDMA INT0 List1 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_LIST1_NOTIFY_ENA_CLR ,VPDMA INT0 List1 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_LIST2_COMPLETE_ENA_CLR ,VPDMA INT0 List2 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_LIST2_NOTIFY_ENA_CLR ,VPDMA INT0 List2 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " VPDMA_INT0_LIST3_COMPLETE_ENA_CLR ,VPDMA INT0 List3 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 7. " VPDMA_INT0_LIST3_NOTIFY_ENA_CLR ,VPDMA INT0 List3 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 8. " VPDMA_INT0_LIST4_COMPLETE_ENA_CLR ,VPDMA INT0 List4 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 9. " VPDMA_INT0_LIST4_NOTIFY_ENA_CLR ,VPDMA INT0 List4 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 10. " VPDMA_INT0_LIST5_COMPLETE_ENA_CLR ,VPDMA INT0 List5 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 11. " VPDMA_INT0_LIST5_NOTIFY_ENA_CLR ,VPDMA INT0 List5 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 12. " VPDMA_INT0_LIST6_COMPLETE_ENA_CLR ,VPDMA INT0 List6 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 13. " VPDMA_INT0_LIST6_NOTIFY_ENA_CLR ,VPDMA INT0 List6 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 14. " VPDMA_INT0_LIST7_COMPLETE_ENA_CLR ,VPDMA INT0 List7 Complete Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 15. " VPDMA_INT0_LIST7_NOTIFY_ENA_CLR ,VPDMA INT0 List7 Notify Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 16. " VPDMA_INT0_DESCRIPTOR_ENA_CLR ,VPDMA INT0 Descriptor Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 17. " RESERVED ," "0,1" textline " " bitfld.long 0x0 18. " DEI_FMD_INT_ENA_CLR ,DEI Film Mode Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "VPE_INTC_INTR0_ENA_CLR1,VPE_INTC_INTR0_ENA_CLR1" bitfld.long 0x0 0. " VPDMA_INT0_CHANNEL_GROUP0_ENA_CLR ,VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 1. " VPDMA_INT0_CHANNEL_GROUP1_ENA_CLR ,VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 2. " VPDMA_INT0_CHANNEL_GROUP2_ENA_CLR ,VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 3. " VPDMA_INT0_CHANNEL_GROUP3_ENA_CLR ,VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 4. " VPDMA_INT0_CHANNEL_GROUP4_ENA_CLR ,VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" bitfld.long 0x0 5. " VPDMA_INT0_CHANNEL_GROUP5_ENA_CLR ,VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " VPDMA_INT0_CLIENT_ENA_CLR ,VPDMA INT0 Client Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16. " DEI_ERROR_INT_ENA_CLR ,DEI Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " bitfld.long 0x0 17.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " VIP1_CHR_DS_1_UV_ERR_INT_ENA_CLR ,VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no effect" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "VPE_INTC_EOI,INTC EOI Register. This register contains the EOI vector register contents as defined by HL0.8" hexmask.long 0x0 0.--31. 1. " EOI_VECTOR ,Number associated with the ipgenericirq for intr output. There are 4 interrupt outputs:Any other write value is ignored. ." group.byte 0x100++0x3 line.long 0x0 "VPE_CLKC_CLKEN,VPE_CLKC_CLKEN" bitfld.long 0x0 0. " VPDMA_EN ,VPDMA Clock Enable" "0,1" bitfld.long 0x0 1. " PRIM_DP_EN ,Primary Video Data Path Clock Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "VPE_CLKC_RST,VPE_CLKC_RST" bitfld.long 0x0 0. " VPDMA_RST ,VPDMA Reset" "0,1" bitfld.long 0x0 1. " PRIM_DP_RST ,Primary Video Data Path Reset" "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ," bitfld.long 0x0 31. " MAIN_RST ,Reset for entire data path in VPE0" "0,1" group.byte 0x10C++0x3 line.long 0x0 "VPE_CLKC_DPS,VPE_CLKC_DPS" bitfld.long 0x0 0.--2. " CSC_SRC_SELECT ,CSC Source Select:" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " RGB_OUT_SELECT ,RGB Output Select" "0,1" bitfld.long 0x0 9.--11. " CHR_DS_SRC_SELECT ,Chroma Downsampler Source Select" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16. " CHR_DS_BYPASS ,Chroma Downsampler Bypass" "0,1" textline " " bitfld.long 0x0 17. " RESERVED ,RESERVED" "0,1" bitfld.long 0x0 18. " COLOR_SEPARATE_422 ,422 Color Separate SelectThis bit controls whether 422 output will be color separate or interleaved. This bit only applies IF chr_ds_bypass is 1 (means 422 output, not 420) and rgb_out_select is 0 (means 422 output, not RGB or 444). 420 is always coplanar, so this only applies if the output type is 422. . ." "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x11C++0x3 line.long 0x0 "VPE_RANGE_MAP,VPE_RANGE_MAP" bitfld.long 0x0 0.--2. " RANGE_MAPY_PRIM ,Range Map Y for Primary input" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " RANGE_MAPUV_PRIM ,Range Map UV for Primary input" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6. " RANGE_MAP_PRIM_ON ,Range Mapping ON for Primary input" "0,1" hexmask.long.tbyte 0x0 7.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " RANGE_REDUCTION_PRIM_ON ,Range Reduction ON for Primary input" "0,1" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "VPE_DEI" base ad:0x489D0600 width 15. group.byte 0x0++0x3 line.long 0x0 "VPE_DEI_REG0,VPE_DEI_REG0" hexmask.long.word 0x0 0.--10. 1. " WIDTH ,Frame Width" bitfld.long 0x0 11.--15. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " HEIGHT ,Frame Height" bitfld.long 0x0 27.--28. " RESERVED ,Always read as 0" "0,1,2,3" textline " " bitfld.long 0x0 29. " INTERLACE_BYPASS ,Interlace Bypass Mode" "0,1" bitfld.long 0x0 30. " FIELD_FLUSH ,Field Flush Mode" "0,1" textline " " bitfld.long 0x0 31. " PROGRESSIVE_BYPASS ,Progressive Mode" "0,1" group.byte 0x4++0x3 line.long 0x0 "VPE_DEI_REG1,VPE_DEI_REG1" bitfld.long 0x0 0. " MDT_TEMPMAX_BYPASS ,Spatio-temporal Maximum Filtering Bypass for motion valued used in EDI" "0,1" bitfld.long 0x0 1. " MDT_SPATMAX_BYPASS ,Spatial Maximum Filtering Bypass for motion values used in EDI" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "VPE_DEI_REG2,VPE_DEI_REG2" hexmask.long.byte 0x0 0.--7. 1. " MDT_SF_SC_THR1 ,Spatial frequency threshold It is used for adaptive scaling of motion values according to how busy the texture is. If the texture is flat, motion values need to be scaled up to reflect the sensitivity of motion values with respect to the detection error. Increasing the thresholds will make the motion value scaling more sensitive to the frequency of the texture. Note: 0 = mdt_sf_sc_thr1 = mdt_sf_sc_thr2 = mdt_sf_sc_thr3" hexmask.long.byte 0x0 8.--15. 1. " MDT_SF_SC_THR2 ,Spatial frequency threshold 2" textline " " hexmask.long.byte 0x0 16.--23. 1. " MDT_SF_SC_THR3 ,Spatial frequency threshold 3" bitfld.long 0x0 24.--27. " MDT_MV_COR_THR ,This threshold is for the coring for motion value, mv. MDT will become more noise robust if this value increases. But the picture may be washed out if this value is set to high. This threshold can be interpreted as the noise threshold for calculating motion values for all blocks." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " MDT_MVSTMAX_COR_THR ,This is used for increasing noise robustness. Increasing this threshold leads to more robustness to noise, but with the potential of introducing ghosting effect. Note that this threshold is used for motion values for EDI only, and it is in addition mdt_mv_cor_thr." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xC++0x3 line.long 0x0 "VPE_DEI_REG3,VPE_DEI_REG3" bitfld.long 0x0 0.--1. " EDI_INP_MODE ,Interpolation mode. Note that mode 00 and 01 are used for debug purpose" "0,1,2,3" bitfld.long 0x0 2. " EDI_ENABLE_3D ,3D Enable" "0,1" textline " " bitfld.long 0x0 3. " EDI_CHROMA_3D_ENABLE ,3D Chroma Enable" "0,1" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " EDI_CHROMA3D_COR_THR ,Correlation threshold used in 3D processing for chroma. Because the motion values used for chroma 3D processing are based on luma only. Extra protection is needed. Temporal interpolation is only performed for chroma, when there is strong spatial or temporal correlation for the chroma pixel being processed. When the pixel difference is less than this threshold, it is assumed that there exists strong correlation between these two pixels. Thus, increasing this value leads to more chroma pixels being processed in 3D" hexmask.long.byte 0x0 16.--23. 1. " EDI_DIR_COR_LOWER_THR ,Lower threshold used for correlation along detected edge" textline " " hexmask.long.byte 0x0 24.--31. 1. " EDI_COR_SCALE_FACTOR ,Scaling factor for correlation along detected edge" group.byte 0x10++0x3 line.long 0x0 "VPE_DEI_REG4,VPE_DEI_REG4" bitfld.long 0x0 0.--4. " EDI_LUT0 ,EDI Lookup Table 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " EDI_LUT1 ,EDI Lookup Table 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " EDI_LUT2 ,EDI Lookup Table 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " EDI_LUT3 ,EDI Lookup Table 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x14++0x3 line.long 0x0 "VPE_DEI_REG5,VPE_DEI_REG5" bitfld.long 0x0 0.--4. " EDI_LUT4 ,EDI Lookup Table 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " EDI_LUT5 ,EDI Lookup Table 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " EDI_LUT6 ,EDI Lookup Table 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " EDI_LUT7 ,EDI Lookup Table 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x18++0x3 line.long 0x0 "VPE_DEI_REG6,VPE_DEI_REG6" bitfld.long 0x0 0.--4. " EDI_LUT8 ,EDI Lookup Table 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " EDI_LUT9 ,EDI Lookup Table 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " EDI_LUT10 ,EDI Lookup Table 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " EDI_LUT11 ,EDI Lookup Table 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x1C++0x3 line.long 0x0 "VPE_DEI_REG7,VPE_DEI_REG7" bitfld.long 0x0 0.--4. " EDI_LUT12 ,EDI Lookup Table 12" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " EDI_LUT13 ,EDI Lookup Table 13" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " EDI_LUT14 ,EDI Lookup Table 14" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Always read as 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " EDI_LUT15 ,EDI Lookup Table 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x20++0x3 line.long 0x0 "VPE_DEI_REG8,VPE_DEI_REG8" hexmask.long.word 0x0 0.--10. 1. " FMD_WINDOW_MINX ,Left boundary of FMD operation window" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " FMD_WINDOW_MAXX ,Right boundary of FMD operation window Must be less than width" bitfld.long 0x0 27.--30. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 31. " FMD_WINDOW_ENABLE ,Enable FMD operation window" "0,1" group.byte 0x24++0x3 line.long 0x0 "VPE_DEI_REG9,VPE_DEI_REG9" hexmask.long.word 0x0 0.--10. 1. " FMD_WINDOW_MINY ,Top boundary of FMD operation window" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " FMD_WINDOW_MAXY ,Bottom boundary of FMD operation window Must be less than height/2" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x28++0x3 line.long 0x0 "VPE_DEI_REG10,VPE_DEI_REG10" bitfld.long 0x0 0. " FMD_ENABLE ,Enable film mode processing" "0,1" bitfld.long 0x0 1. " FMD_LOCK ,Film Mode Field Jamming Direction" "0,1" textline " " bitfld.long 0x0 2. " FMD_JAM_DIR ,Film Mode Field Jamming Direction" "0,1" bitfld.long 0x0 3. " FMD_BED_ENABLE ,Film Mode Bad Edit Detection" "0,1" textline " " hexmask.long.word 0x0 4.--15. 1. " RESERVED ," hexmask.long.byte 0x0 16.--23. 1. " FMD_CAF_FIELD_THR ,CAF threshold used for the pixels from two fields This is the threshold used for combing artifacts detection. The difference of two consecutive lines (when merging two fields into one progressive frame) is used to compare with this threshold. Increasing this threshold leads to be more conservative in detecting CAF." textline " " hexmask.long.byte 0x0 24.--31. 1. " FMD_CAF_LINE_THR ,CAF threshold used for the pixels from two lines in one field This is the threshold used for combing artifacts detection. The difference of two consecutive lines from the same field (so there is one line in between if two fields are merged into one progressive frame) is compared with this threshold. Decreasing this threshold leads to be more conservative in detecting CAF. Both fmd_caf_field_thr and fmd_caf_line_thr are close the values that two pixels differed by this value is observable." group.byte 0x2C++0x3 line.long 0x0 "VPE_DEI_REG11,VPE_DEI_REG11" hexmask.long.tbyte 0x0 0.--19. 1. " FMD_CAF_THR ,CAF threshold used for leaving film mode: If the combing artifacts is greater than this threshold, CAF is detected and thus the state machine will be forced to leave the film mode. If the user prefers to be more conservative in using film mode, decrease this threshold." hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "VPE_DEI_REG12,VPE_DEI_REG12" hexmask.long.tbyte 0x0 0.--20. 1. " FMD_CAF ,Detected combing artifacts" bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " FMD_RESET ,When 1, the film mode detection module needs to be reset by the software. This bit needs to be checked at each occurrence of the film mode detection interrupt" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VPE_DEI_REG13,VPE_DEI_REG13" hexmask.long 0x0 0.--27. 1. " FMD_FIELD_DIFF ,Field difference (difference between two neighboring fields, one top and one bottom)" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x38++0x3 line.long 0x0 "VPE_DEI_REG14,VPE_DEI_REG14" hexmask.long.tbyte 0x0 0.--19. 1. " FMD_FRAME_DIFF ,Frame difference (difference between two top or two bottom fields)" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," width 0x0B tree.end tree "VPE_CHR_US_INST_0" base ad:0x489D0300 width 10. group.byte 0x0++0x3 line.long 0x0 "VPE_PID,VPE_PID" hexmask.long 0x0 0.--31. 1. " PID ," group.byte 0x4++0x3 line.long 0x0 "VPE_REG0,VPE_REG0" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID0_C1 ,C1 coefficient for Anchor Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " CFG_MODE ,0x0 : Mode A" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID0_C0 ,C0 coefficient for Anchor Pixel. Use when field_id = 0" group.byte 0x8++0x3 line.long 0x0 "VPE_REG1,VPE_REG1" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID0_C3 ,C3 coefficient for Anchor Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID0_C2 ,C2 coefficient for Anchor Pixel. Use when field_id = 0" group.byte 0xC++0x3 line.long 0x0 "VPE_REG2,VPE_REG2" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID0_C1 ,C1 coefficient for Interpolated Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID0_C0 ,C0 coefficient for Interpolated Pixel. Use when field_id = 0" group.byte 0x10++0x3 line.long 0x0 "VPE_REG3,VPE_REG3" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID0_C3 ,C3 coefficient for Interpolated Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID0_C2 ,C2 coefficient for Interpolated Pixel. Use when field_id = 0" group.byte 0x14++0x3 line.long 0x0 "VPE_REG4,VPE_REG4" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID1_C1 ,C1 coefficient for Anchor Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID1_C0 ,C0 coefficient for Anchor Pixel. Use when field_id = 1" group.byte 0x18++0x3 line.long 0x0 "VPE_REG5,VPE_REG5" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID1_C3 ,C3 coefficient for Anchor Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID1_C2 ,C2 coefficient for Anchor Pixel. Use when field_id = 1" group.byte 0x1C++0x3 line.long 0x0 "VPE_REG6,VPE_REG6" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID1_C1 ,C1 coefficient for Interpolated Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID1_C0 ,C0 coefficient for Interpolated Pixel. Use when field_id = 1" group.byte 0x20++0x3 line.long 0x0 "VPE_REG7,VPE_REG7" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID1_C3 ,C3 coefficient for Interpolated Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID1_C2 ,C2 coefficient for Interpolated Pixel. Use when field_id = 1" width 0x0B tree.end tree "VPE_CHR_US_INST_1" base ad:0x489D0400 width 10. group.byte 0x0++0x3 line.long 0x0 "VPE_PID,VPE_PID" hexmask.long 0x0 0.--31. 1. " PID ," group.byte 0x4++0x3 line.long 0x0 "VPE_REG0,VPE_REG0" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID0_C1 ,C1 coefficient for Anchor Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " CFG_MODE ,0x0 : Mode A" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID0_C0 ,C0 coefficient for Anchor Pixel. Use when field_id = 0" group.byte 0x8++0x3 line.long 0x0 "VPE_REG1,VPE_REG1" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID0_C3 ,C3 coefficient for Anchor Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID0_C2 ,C2 coefficient for Anchor Pixel. Use when field_id = 0" group.byte 0xC++0x3 line.long 0x0 "VPE_REG2,VPE_REG2" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID0_C1 ,C1 coefficient for Interpolated Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID0_C0 ,C0 coefficient for Interpolated Pixel. Use when field_id = 0" group.byte 0x10++0x3 line.long 0x0 "VPE_REG3,VPE_REG3" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID0_C3 ,C3 coefficient for Interpolated Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID0_C2 ,C2 coefficient for Interpolated Pixel. Use when field_id = 0" group.byte 0x14++0x3 line.long 0x0 "VPE_REG4,VPE_REG4" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID1_C1 ,C1 coefficient for Anchor Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID1_C0 ,C0 coefficient for Anchor Pixel. Use when field_id = 1" group.byte 0x18++0x3 line.long 0x0 "VPE_REG5,VPE_REG5" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID1_C3 ,C3 coefficient for Anchor Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID1_C2 ,C2 coefficient for Anchor Pixel. Use when field_id = 1" group.byte 0x1C++0x3 line.long 0x0 "VPE_REG6,VPE_REG6" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID1_C1 ,C1 coefficient for Interpolated Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID1_C0 ,C0 coefficient for Interpolated Pixel. Use when field_id = 1" group.byte 0x20++0x3 line.long 0x0 "VPE_REG7,VPE_REG7" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID1_C3 ,C3 coefficient for Interpolated Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID1_C2 ,C2 coefficient for Interpolated Pixel. Use when field_id = 1" width 0x0B tree.end tree "VPE_CHR_US_INST_2" base ad:0x489D0500 width 10. group.byte 0x0++0x3 line.long 0x0 "VPE_PID,VPE_PID" hexmask.long 0x0 0.--31. 1. " PID ," group.byte 0x4++0x3 line.long 0x0 "VPE_REG0,VPE_REG0" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID0_C1 ,C1 coefficient for Anchor Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " CFG_MODE ,0x0 : Mode A" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID0_C0 ,C0 coefficient for Anchor Pixel. Use when field_id = 0" group.byte 0x8++0x3 line.long 0x0 "VPE_REG1,VPE_REG1" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID0_C3 ,C3 coefficient for Anchor Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID0_C2 ,C2 coefficient for Anchor Pixel. Use when field_id = 0" group.byte 0xC++0x3 line.long 0x0 "VPE_REG2,VPE_REG2" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID0_C1 ,C1 coefficient for Interpolated Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID0_C0 ,C0 coefficient for Interpolated Pixel. Use when field_id = 0" group.byte 0x10++0x3 line.long 0x0 "VPE_REG3,VPE_REG3" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID0_C3 ,C3 coefficient for Interpolated Pixel. Use when field_id = 0" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID0_C2 ,C2 coefficient for Interpolated Pixel. Use when field_id = 0" group.byte 0x14++0x3 line.long 0x0 "VPE_REG4,VPE_REG4" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID1_C1 ,C1 coefficient for Anchor Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID1_C0 ,C0 coefficient for Anchor Pixel. Use when field_id = 1" group.byte 0x18++0x3 line.long 0x0 "VPE_REG5,VPE_REG5" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " ANCHOR_FID1_C3 ,C3 coefficient for Anchor Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " ANCHOR_FID1_C2 ,C2 coefficient for Anchor Pixel. Use when field_id = 1" group.byte 0x1C++0x3 line.long 0x0 "VPE_REG6,VPE_REG6" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID1_C1 ,C1 coefficient for Interpolated Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID1_C0 ,C0 coefficient for Interpolated Pixel. Use when field_id = 1" group.byte 0x20++0x3 line.long 0x0 "VPE_REG7,VPE_REG7" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " INTERP_FID1_C3 ,C3 coefficient for Interpolated Pixel. Use when field_id = 1" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " INTERP_FID1_C2 ,C2 coefficient for Interpolated Pixel. Use when field_id = 1" width 0x0B tree.end tree "VPE_VPDMA" base ad:0x489DD000 width 28. group.byte 0x0++0x3 line.long 0x0 "VPE_VPDMA_PID,This register follows the format described in PDR3.5" bitfld.long 0x0 0.--5. " MINOR ,Minor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " VPDMA_ACCESS_TYPE ,After bootup this bit states how DMA transaction are setup by lists or through register access." "0,1" textline " " bitfld.long 0x0 7. " VPDMA_LOAD_COMPLETE ,This bit will be 1 when the VPDMA state machines image and data image have successfuly been fetched and loaded." "0,1" bitfld.long 0x0 8.--10. " MAJOR ,Major Release Number" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--15. " RTL ,RTL Release Version The PDR release number of this IP. After Bootup this value becomes the firmware Revision ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--29. 1. " FUNC ,The funcition of the module being used. The value is for vpe0_vayu_vpdma." textline " " bitfld.long 0x0 30.--31. " SCHEME ,The scheme of the register used. Currently this is PDR 3.5 Scheme" "0,1,2,3" group.byte 0x4++0x3 line.long 0x0 "VPE_LIST_ADDR,The location of a new list to begin processing." hexmask.long 0x0 0.--31. 1. " LIST_ADDR ,Location of a new list of descriptors. This register must be written with the VPDMA Configuration Location after reset." group.byte 0x8++0x3 line.long 0x0 "VPE_LIST_ATTR,The attributes of a new list. This register should always be written after list_addr." hexmask.long.word 0x0 0.--15. 1. " LIST_SIZE ,Number of 128 bit word in the new list of descriptors. Writes to this register will activate the list in the list stack of the list manager and begin transfer of the list into VPDMA. This size can not be 0." bitfld.long 0x0 16.--18. " LIST_TYPE ,The type of list that has been generated." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RDY ,This bit is low when a new list cannot be written to theVPE_LIST_ADDR register. The reasons this bit would be low are at initial startup if the LIST_MANAGER State Machine image has not completed loading. It also would be low if the last write to the LIST_ATTR attempted to start a list that is currently active. When this bit is low any writes to the list address register will cause access to not be accepted until this bit has set by the previous list having completed." "0,1" bitfld.long 0x0 20. " STOP ,This bit is written with the LIST_NUMBER field to stop a self-modifying list. When this bit is written a one the list specified by the LIST_NUMBER is sent a stop signal and will finish the current frame of transfers and then free the list resources." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " LIST_NUM ,The list number that should be assigned to the list located at LIST_ADDR. If the list is still active this will block all future list writes until the list is available." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xC++0x3 line.long 0x0 "VPE_LIST_STAT_SYNC,The register is used for processor to List Manager syncronization and status registers for the list." bitfld.long 0x0 0. " SYNC_LISTS0 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 0 waiting on it." "0,1" bitfld.long 0x0 1. " SYNC_LISTS1 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 1 waiting on it." "0,1" textline " " bitfld.long 0x0 2. " SYNC_LISTS2 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 2 waiting on it." "0,1" bitfld.long 0x0 3. " SYNC_LISTS3 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 3 waiting on it." "0,1" textline " " bitfld.long 0x0 4. " SYNC_LISTS4 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 4 waiting on it." "0,1" bitfld.long 0x0 5. " SYNC_LISTS5 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 5 waiting on it." "0,1" textline " " bitfld.long 0x0 6. " SYNC_LISTS6 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 6 waiting on it." "0,1" bitfld.long 0x0 7. " SYNC_LISTS7 ,Writing a 1 to this field causes a sync event to fire that clears a Control Descriptor in List 7 waiting on it." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16. " LIST0_BUSY ,The list 0 is currently running. Any attempt to load a new list to list 0 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 17. " LIST1_BUSY ,The list 1 is currently running. Any attempt to load a new list to list 1 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 18. " LIST2_BUSY ,The list 2 is currently running. Any attempt to load a new list to list 2 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 19. " LIST3_BUSY ,The list 3 is currently running. Any attempt to load a new list to list 3 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 20. " LIST4_BUSY ,The list 4 is currently running. Any attempt to load a new list to list 4 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 21. " LIST5_BUSY ,The list 5 is currently running. Any attempt to load a new list to list 5 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" bitfld.long 0x0 22. " LIST6_BUSY ,The list 6 is currently running. Any attempt to load a new list to list 6 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" textline " " bitfld.long 0x0 23. " LIST7_BUSY ,The list 7 is currently running. Any attempt to load a new list to list 7 will result in the LM_ADDR and LM_ATTR registers to be locked until the list is complete and this value goes to 0." "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "VPE_BG_RGB,The registers used to set the background color for RGB" hexmask.long.byte 0x0 0.--7. 1. " BLEND ,The blend value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 8.--15. 1. " BLUE ,The blue value to give on an RGB data port for a blank pixel when using virtual video buffering" textline " " hexmask.long.byte 0x0 16.--23. 1. " GREEN ,The green value to give on an RGB data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 24.--31. 1. " RED ,The red value to give on an RGB data port for a blank pixel when using virtual video buffering" group.byte 0x1C++0x3 line.long 0x0 "VPE_BG_YUV,The registers used to set the background color for YUV" hexmask.long.byte 0x0 0.--7. 1. " CB ,The Cb value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 8.--15. 1. " CR ,The Cr value to give on a YUV data port for a blank pixel when using virtual video buffering" textline " " hexmask.long.byte 0x0 16.--23. 1. " Y ,The Y value to give on a YUV data port for a blank pixel when using virtual video buffering" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "VPE_VPDMA_SETUP,Configures global parameters that are shared by all clients." bitfld.long 0x0 0. " SEC_BASE_CH ,Use Secondary Channels for Mosaic mode" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "VPE_MAX_SIZE1,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 1 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 1 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 1 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x38++0x3 line.long 0x0 "VPE_MAX_SIZE2,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 2 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 2 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 2 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x3C++0x3 line.long 0x0 "VPE_MAX_SIZE3,Configures maximum width and maximum height global parameters that are shared by all clients to allow for configurable max width and max height when setting is 3 in write descriptor." hexmask.long.word 0x0 0.--15. 1. " MAX_HEIGHT ,The maximum height to use for setting of max_height 3 in a write descriptor. The value is the number of lines + 1 so if 1024 lines are required then set the value to 1023." hexmask.long.word 0x0 16.--31. 1. " MAX_WIDTH ,The maximum width to use for setting of max_width 3 in a write descriptor. The value is the number of pixels + 1 so if 1024 pixels are required then set the value to 1023." group.byte 0x40++0x3 line.long 0x0 "VPE_INT0_CHANNEL0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_HQ_VID1_LUMA ,The last write DMA transaction has completed for channel hq_vid1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_HQ_VID1_CHROMA ,The last write DMA transaction has completed for channel hq_vid1_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_HQ_VID2_LUMA ,The last write DMA transaction has completed for channel hq_vid2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_HQ_VID2_CHROMA ,The last write DMA transaction has completed for channel hq_vid2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_HQ_VID3_LUMA ,The last write DMA transaction has completed for channel hq_vid3_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_HQ_VID3_CHROMA ,The last write DMA transaction has completed for channel hq_vid3_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_HQ_MV ,The last read DMA transaction has occurred for channel hq_mv and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client dei_hq_mv_in will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_HQ_MV_OUT ,The last write DMA transaction has completed for channel hq_mv_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_hq_mv_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_HQ_SCALER ,The last write DMA transaction has completed for channel hq_scaler. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client dei_sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_SCALER_LUMA ,The last write DMA transaction has completed for channel scaler_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SCALER_CHROMA ,The last write DMA transaction has completed for channel scaler_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_STAT_SCALER_OUT ,The last write DMA transaction has completed for channel scaler_out. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client sc_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value" "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_GRPX1 ,The last read DMA transaction has occurred for channel grpx1 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx1_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_GRPX2 ,The last read DMA transaction has occurred for channel grpx2 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx2_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX3 ,The last read DMA transaction has occurred for channel grpx3 and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client grpx3_data will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x44++0x3 line.long 0x0 "VPE_INT0_CHANNEL0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_HQ_VID1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_HQ_VID1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_HQ_VID2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_HQ_VID2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_HQ_VID3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_HQ_VID3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_HQ_MV ,The interrupt for Low Cost DEI Motion Vector should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_HQ_MV_OUT ,The interrupt for Low Cost DEI Motion Vector Write should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_HQ_SCALER ,The interrupt for High Quality DEI Scaler Write to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_SCALER_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SCALER_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " hexmask.long.byte 0x0 20.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28. " INT_MASK_SCALER_OUT ,The interrupt for Low Cost DEI Scalar Write to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_GRPX1 ,The interrupt for Graphics 0 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_GRPX2 ,The interrupt for Graphics 1 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX3 ,The interrupt for Graphcis 2 Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x48++0x3 line.long 0x0 "VPE_INT0_CHANNEL1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x4C++0x3 line.long 0x0 "VPE_INT0_CHANNEL1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_PORTA_SRC0 ,The interrupt for Video Input 1 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_PORTA_SRC1 ,The interrupt for Video Input 1 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_PORTA_SRC2 ,The interrupt for Video Input 1 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_PORTA_SRC3 ,The interrupt for Video Input 1 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_PORTA_SRC4 ,The interrupt for Video Input 1 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_PORTA_SRC5 ,The interrupt for Video Input 1 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_PORTA_SRC6 ,The interrupt for Video Input 1 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_PORTA_SRC7 ,The interrupt for Video Input 1 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_PORTA_SRC8 ,The interrupt for Video Input 1 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_PORTA_SRC9 ,The interrupt for Video Input 1 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_PORTA_SRC10 ,The interrupt for Video Input 1 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_PORTA_SRC11 ,The interrupt for Video Input 1 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_PORTA_SRC12 ,The interrupt for Video Input 1 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_PORTA_SRC13 ,The interrupt for Video Input 1 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_PORTA_SRC14 ,The interrupt for Video Input 1 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_PORTA_SRC15 ,The interrupt for Video Input 1 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_PORTB_SRC0 ,The interrupt for Video Input 1 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_PORTB_SRC1 ,The interrupt for Video Input 1 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_PORTB_SRC2 ,The interrupt for Video Input 1 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_PORTB_SRC3 ,The interrupt for Video Input 1 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_PORTB_SRC4 ,The interrupt for Video Input 1 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_PORTB_SRC5 ,The interrupt for Video Input 1 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_PORTB_SRC6 ,The interrupt for Video Input 1 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_PORTB_SRC7 ,The interrupt for Video Input 1 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_PORTB_SRC8 ,The interrupt for Video Input 1 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_PORTB_SRC9 ,The interrupt for Video Input 1 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x50++0x3 line.long 0x0 "VPE_INT0_CHANNEL2_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP1_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP1_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP1_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP1_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP1_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP1_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP1_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP1_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP1_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP1_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP1_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP1_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP1_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP1_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP1_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP1_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP1_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP1_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x54++0x3 line.long 0x0 "VPE_INT0_CHANNEL2_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_PORTB_SRC10 ,The interrupt for Video Input 1 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_PORTB_SRC11 ,The interrupt for Video Input 1 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_PORTB_SRC12 ,The interrupt for Video Input 1 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_PORTB_SRC13 ,The interrupt for Video Input 1 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_PORTB_SRC14 ,The interrupt for Video Input 1 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_PORTB_SRC15 ,The interrupt for Video Input 1 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_MULT_ANCA_SRC0 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_MULT_ANCA_SRC1 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_MULT_ANCA_SRC2 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_MULT_ANCA_SRC3 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_MULT_ANCA_SRC4 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_MULT_ANCA_SRC5 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP1_MULT_ANCA_SRC6 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP1_MULT_ANCA_SRC7 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP1_MULT_ANCA_SRC8 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP1_MULT_ANCA_SRC9 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP1_MULT_ANCA_SRC10 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP1_MULT_ANCA_SRC11 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP1_MULT_ANCA_SRC12 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP1_MULT_ANCA_SRC13 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP1_MULT_ANCA_SRC14 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP1_MULT_ANCA_SRC15 ,The interrupt for Video Input 1 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP1_MULT_ANCB_SRC0 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP1_MULT_ANCB_SRC1 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP1_MULT_ANCB_SRC2 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP1_MULT_ANCB_SRC3 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_MULT_ANCB_SRC4 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_MULT_ANCB_SRC5 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP1_MULT_ANCB_SRC6 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP1_MULT_ANCB_SRC7 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP1_MULT_ANCB_SRC8 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP1_MULT_ANCB_SRC9 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x58++0x3 line.long 0x0 "VPE_INT0_CHANNEL3_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP1_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP1_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip1_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP1_PORTA_LUMA ,The last write DMA transaction has completed for channel vip1_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP1_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip1_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP1_PORTB_LUMA ,The last write DMA transaction has completed for channel vip1_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP1_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip1_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP1_PORTA_RGB ,The last write DMA transaction has completed for channel vip1_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP1_PORTB_RGB ,The last write DMA transaction has completed for channel vip1_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip1_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_PORTA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_porta_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_PORTA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_porta_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_PORTA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_porta_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_PORTA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_porta_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_PORTA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_porta_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_PORTA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_porta_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_PORTA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_porta_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_PORTA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_porta_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_PORTA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_porta_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_PORTA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_porta_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_PORTA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_porta_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_PORTA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_porta_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_PORTA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_porta_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_PORTA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_porta_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_PORTA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_porta_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_PORTA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_porta_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_PORTB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_portb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_PORTB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_portb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_PORTB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_portb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_PORTB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_portb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x5C++0x3 line.long 0x0 "VPE_INT0_CHANNEL3_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP1_MULT_ANCB_SRC10 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP1_MULT_ANCB_SRC11 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_MULT_ANCB_SRC12 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_MULT_ANCB_SRC13 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_MULT_ANCB_SRC14 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_MULT_ANCB_SRC15 ,The interrupt for Video Input 1 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP1_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP1_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP1_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP1_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP1_PORTA_RGB ,The interrupt for Video Input 1 Port A RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP1_PORTB_RGB ,The interrupt for Video Input 1 Port B RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_PORTA_SRC0 ,The interrupt for Video Input 2 Port A Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_PORTA_SRC1 ,The interrupt for Video Input 2 Port A Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_PORTA_SRC2 ,The interrupt for Video Input 2 Port A Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_PORTA_SRC3 ,The interrupt for Video Input 2 Port A Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_PORTA_SRC4 ,The interrupt for Video Input 2 Port A Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_PORTA_SRC5 ,The interrupt for Video Input 2 Port A Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_PORTA_SRC6 ,The interrupt for Video Input 2 Port A Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_PORTA_SRC7 ,The interrupt for Video Input 2 Port A Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_PORTA_SRC8 ,The interrupt for Video Input 2 Port A Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_PORTA_SRC9 ,The interrupt for Video Input 2 Port A Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_PORTA_SRC10 ,The interrupt for Video Input 2 Port A Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_PORTA_SRC11 ,The interrupt for Video Input 2 Port A Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_PORTA_SRC12 ,The interrupt for Video Input 2 Port A Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_PORTA_SRC13 ,The interrupt for Video Input 2 Port A Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_PORTA_SRC14 ,The interrupt for Video Input 2 Port A Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_PORTA_SRC15 ,The interrupt for Video Input 2 Port A Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_PORTB_SRC0 ,The interrupt for Video Input 2 Port B Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_PORTB_SRC1 ,The interrupt for Video Input 2 Port B Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_PORTB_SRC2 ,The interrupt for Video Input 2 Port B Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_PORTB_SRC3 ,The interrupt for Video Input 2 Port B Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x60++0x3 line.long 0x0 "VPE_INT0_CHANNEL4_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_PORTB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_portb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_PORTB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_portb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_PORTB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_portb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_PORTB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_portb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_PORTB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_portb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_PORTB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_portb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_PORTB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_portb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_PORTB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_portb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_PORTB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_portb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_PORTB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_portb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_PORTB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_portb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_PORTB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_portb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_uv then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_MULT_ANCA_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_anca_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_MULT_ANCA_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_anca_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_MULT_ANCA_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_anca_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_MULT_ANCA_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_anca_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_MULT_ANCA_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_anca_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_MULT_ANCA_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_anca_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_VIP2_MULT_ANCA_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_anca_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_VIP2_MULT_ANCA_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_anca_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VIP2_MULT_ANCA_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_anca_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_VIP2_MULT_ANCA_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_anca_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_VIP2_MULT_ANCA_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_anca_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_VIP2_MULT_ANCA_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_anca_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VIP2_MULT_ANCA_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_anca_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_VIP2_MULT_ANCA_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_anca_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP2_MULT_ANCA_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_anca_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP2_MULT_ANCA_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_anca_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_a then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_MULT_ANCB_SRC0 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src0. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_MULT_ANCB_SRC1 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src1. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_VIP2_MULT_ANCB_SRC2 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src2. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_VIP2_MULT_ANCB_SRC3 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src3. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x64++0x3 line.long 0x0 "VPE_INT0_CHANNEL4_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_PORTB_SRC4 ,The interrupt for Video Input 2 Port B Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_PORTB_SRC5 ,The interrupt for Video Input 2 Port B Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_PORTB_SRC6 ,The interrupt for Video Input 2 Port B Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_PORTB_SRC7 ,The interrupt for Video Input 2 Port B Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_PORTB_SRC8 ,The interrupt for Video Input 2 Port B Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_PORTB_SRC9 ,The interrupt for Video Input 2 Port B Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_PORTB_SRC10 ,The interrupt for Video Input 2 Port B Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_PORTB_SRC11 ,The interrupt for Video Input 2 Port B Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_PORTB_SRC12 ,The interrupt for Video Input 2 Port B Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_PORTB_SRC13 ,The interrupt for Video Input 2 Port B Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_PORTB_SRC14 ,The interrupt for Video Input 2 Port B Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_PORTB_SRC15 ,The interrupt for Video Input 2 Port B Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_MULT_ANCA_SRC0 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_MULT_ANCA_SRC1 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_MULT_ANCA_SRC2 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_MULT_ANCA_SRC3 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_MULT_ANCA_SRC4 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_MULT_ANCA_SRC5 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_VIP2_MULT_ANCA_SRC6 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_VIP2_MULT_ANCA_SRC7 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VIP2_MULT_ANCA_SRC8 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_VIP2_MULT_ANCA_SRC9 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_VIP2_MULT_ANCA_SRC10 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_VIP2_MULT_ANCA_SRC11 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VIP2_MULT_ANCA_SRC12 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_VIP2_MULT_ANCA_SRC13 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP2_MULT_ANCA_SRC14 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP2_MULT_ANCA_SRC15 ,The interrupt for Video Input 2 Port A Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_MULT_ANCB_SRC0 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 0 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_MULT_ANCB_SRC1 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 1 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_VIP2_MULT_ANCB_SRC2 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 2 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_VIP2_MULT_ANCB_SRC3 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 3 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x68++0x3 line.long 0x0 "VPE_INT0_CHANNEL5_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_VIP2_MULT_ANCB_SRC4 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src4. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_VIP2_MULT_ANCB_SRC5 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src5. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP2_MULT_ANCB_SRC6 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src6. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP2_MULT_ANCB_SRC7 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src7. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP2_MULT_ANCB_SRC8 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src8. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP2_MULT_ANCB_SRC9 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src9. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_MULT_ANCB_SRC10 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src10. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_MULT_ANCB_SRC11 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src11. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_MULT_ANCB_SRC12 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src12. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_MULT_ANCB_SRC13 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src13. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_VIP2_MULT_ANCB_SRC14 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src14. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_VIP2_MULT_ANCB_SRC15 ,The last write DMA transaction has completed for channel vip2_mult_ancb_src15. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_anc_b then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_VIP2_PORTA_LUMA ,The last write DMA transaction has completed for channel vip2_porta_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_VIP2_PORTA_CHROMA ,The last write DMA transaction has completed for channel vip2_porta_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_VIP2_PORTB_LUMA ,The last write DMA transaction has completed for channel vip2_portb_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_VIP2_PORTB_CHROMA ,The last write DMA transaction has completed for channel vip2_portb_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_VIP2_PORTA_RGB ,The last write DMA transaction has completed for channel vip2_porta_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_up_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_VIP2_PORTB_RGB ,The last write DMA transaction has completed for channel vip2_portb_rgb. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client vip2_lo_y then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_OTHER ,This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_NF_WRITE_LUMA ,The last write DMA transaction has completed for channel nf_write_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_NF_WRITE_CHROMA ,The last write DMA transaction has completed for channel nf_write_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_NF_LAST_LUMA ,The last write DMA transaction has completed for channel nf_last_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_NF_LAST_CHROMA ,The last write DMA transaction has completed for channel nf_last_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_VBI_SD_VENC ,The last read DMA transaction has occurred for channel vbi_sd_venc and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client vbi_sdvenc will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_POST_COMP_WR ,The last write DMA transaction has completed for channel post_comp_wr. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client hdmi_wrbk_out then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_PIP_FRAME ,The last read DMA transaction has occurred for channel pip_frame and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client pip_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_AUX_IN ,The last read DMA transaction has occurred for channel aux_in and the channel is free to be updated for the next transfer. This will fire before the destination has received the data as it will have just been stored in the internal buffer. The client comp_wrbk will now accept a new descriptor from the List Manager. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_TRANSCODE1_LUMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_TRANSCODE1_CHROMA ,The last write DMA transaction has completed for channel transcode1_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_TRANSCODE2_LUMA ,The last write DMA transaction has completed for channel transcode2_luma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_TRANSCODE2_CHROMA ,The last write DMA transaction has completed for channel transcode2_chroma. All data from the channel has been sent and received by the external memory. If a new channel has not been setup for the client then the client will be fully empty at this point. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x6C++0x3 line.long 0x0 "VPE_INT0_CHANNEL5_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_VIP2_MULT_ANCB_SRC4 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 4 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_VIP2_MULT_ANCB_SRC5 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 5 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP2_MULT_ANCB_SRC6 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 6 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP2_MULT_ANCB_SRC7 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 7 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP2_MULT_ANCB_SRC8 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 8 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP2_MULT_ANCB_SRC9 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 9 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_MULT_ANCB_SRC10 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 10 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_MULT_ANCB_SRC11 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 11 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_MULT_ANCB_SRC12 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 12 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_MULT_ANCB_SRC13 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 13 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_VIP2_MULT_ANCB_SRC14 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 14 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_VIP2_MULT_ANCB_SRC15 ,The interrupt for Video Input 2 Port B Ancillary Data Channel 15 should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_VIP2_PORTA_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_VIP2_PORTA_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_VIP2_PORTB_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_VIP2_PORTB_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_VIP2_PORTA_RGB ,The interrupt for Video Input 2 Port A RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_VIP2_PORTB_RGB ,The interrupt for Video Input 2 Port B RGB Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_OTHER ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_NF_WRITE_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_NF_WRITE_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_NF_LAST_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_NF_LAST_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_VBI_SD_VENC ,The interrupt for SD Video Encoder VBI Data should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_POST_COMP_WR ,The interrupt for Post Compositer Writeback to Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_PIP_FRAME ,The interrupt for PIP Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_AUX_IN ,The interrupt for Auxilary Data for the Compositor Frame From Memory should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_TRANSCODE1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_TRANSCODE1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_TRANSCODE2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_TRANSCODE2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x78++0x3 line.long 0x0 "VPE_INT0_CLIENT0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_DEI_HQ_1_CHROMA ,The client interface dei_hq_1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_DEI_HQ_1_LUMA ,The client interface dei_hq_1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_DEI_HQ_2_LUMA ,The client interface dei_hq_2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_DEI_HQ_2_CHROMA ,The client interface dei_hq_2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_DEI_HQ_3_LUMA ,The client interface dei_hq_3_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_DEI_HQ_3_CHROMA ,The client interface dei_hq_3_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_STAT_DEI_HQ_MV_IN ,The client interface dei_hq_mv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_STAT_DEI_HQ_MV_OUT ,The client interface dei_hq_mv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_STAT_DEI_SC_OUT ,The client interface dei_sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_PIP_WRBK ,The client interface pip_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_SC_IN_CHROMA ,The client interface sc_in_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_SC_IN_LUMA ,The client interface sc_in_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_STAT_SC_OUT ,The client interface sc_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 30. " INT_STAT_COMP_WRBK ,The client interface comp_wrbk has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 31. " INT_STAT_GRPX1_DATA ,The client interface grpx1_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x7C++0x3 line.long 0x0 "VPE_INT0_CLIENT0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_DEI_HQ_1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_DEI_HQ_1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_DEI_HQ_2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_DEI_HQ_2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_DEI_HQ_3_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_DEI_HQ_3_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " INT_MASK_DEI_HQ_MV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 15. " INT_MASK_DEI_HQ_MV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 17. " INT_MASK_DEI_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_PIP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_SC_IN_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_SC_IN_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" hexmask.long.byte 0x0 21.--28. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 29. " INT_MASK_SC_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 30. " INT_MASK_COMP_WRBK ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 31. " INT_MASK_GRPX1_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x80++0x3 line.long 0x0 "VPE_INT0_CLIENT1_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_GRPX2_DATA ,The client interface grpx2_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_GRPX3_DATA ,The client interface grpx3_data has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_VIP1_LO_Y ,The client interface vip1_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_VIP1_LO_UV ,The client interface vip1_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_VIP1_UP_Y ,The client interface vip1_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_VIP1_UP_UV ,The client interface vip1_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_VIP2_LO_Y ,The client interface vip2_lo_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_VIP2_LO_UV ,The client interface vip2_lo_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_VIP2_UP_Y ,The client interface vip2_up_y has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_VIP2_UP_UV ,The client interface vip2_up_uv has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_GRPX1_ST ,The client interface grpx1_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_GRPX2_ST ,The client interface grpx2_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_GRPX3_ST ,The client interface grpx3_st has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_NF_422_IN ,The client interface nf_422_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_NF_420_Y_IN ,The client interface nf_420_y_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_NF_420_UV_IN ,The client interface nf_420_uv_in has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_NF_420_Y_OUT ,The client interface nf_420_y_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_NF_420_UV_OUT ,The client interface nf_420_uv_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_STAT_VBI_SDVENC ,The client interface vbi_sdvenc has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_VPI_CTL ,The client interface vpi_ctl has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_HDMI_WRBK_OUT ,The client interface hdmi_wrbk_out has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_TRANS1_CHROMA ,The client interface trans1_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_TRANS1_LUMA ,The client interface trans1_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_TRANS2_CHROMA ,The client interface trans2_chroma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_TRANS2_LUMA ,The client interface trans2_luma has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having sent the End of Frame signal to the receiving module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_VIP1_ANC_A ,The client interface vip1_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_VIP1_ANC_B ,The client interface vip1_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_VIP2_ANC_A ,The client interface vip2_anc_a has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_VIP2_ANC_B ,The client interface vip2_anc_b has reached its current configured interrupt event as specified by the last received control descriptor for this client. If no control descriptor has been configured this will default to having received the End of Frame signal from the transmitting module. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x84++0x3 line.long 0x0 "VPE_INT0_CLIENT1_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_GRPX2_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_GRPX3_DATA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_VIP1_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_VIP1_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_VIP1_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_VIP1_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_VIP2_LO_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_VIP2_LO_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_VIP2_UP_Y ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_VIP2_UP_UV ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_GRPX1_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_GRPX2_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_GRPX3_ST ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_NF_422_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_NF_420_Y_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_NF_420_UV_IN ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_NF_420_Y_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_NF_420_UV_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " INT_MASK_VBI_SDVENC ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_VPI_CTL ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_HDMI_WRBK_OUT ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_TRANS1_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_TRANS1_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_TRANS2_CHROMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_TRANS2_LUMA ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_VIP1_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_VIP1_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_VIP2_ANC_A ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_VIP2_ANC_B ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x88++0x3 line.long 0x0 "VPE_INT0_LIST0_INT_STAT,This register gives the information of the interrupts that have triggered since last cleared by the process that is servicing vpdma_int0." bitfld.long 0x0 0. " INT_STAT_LIST0_COMPLETE ,List 0 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 1. " INT_STAT_LIST0_NOTIFY ,A channel set by List 0 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 2. " INT_STAT_LIST1_COMPLETE ,List 1 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 3. " INT_STAT_LIST1_NOTIFY ,A channel set by List 1 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 4. " INT_STAT_LIST2_COMPLETE ,List 2 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 5. " INT_STAT_LIST2_NOTIFY ,A channel set by List 2 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 6. " INT_STAT_LIST3_COMPLETE ,List 3 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 7. " INT_STAT_LIST3_NOTIFY ,A channel set by List 3 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 8. " INT_STAT_LIST4_COMPLETE ,List 4 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 9. " INT_STAT_LIST4_NOTIFY ,A channel set by List 4 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 10. " INT_STAT_LIST5_COMPLETE ,List 5 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 11. " INT_STAT_LIST5_NOTIFY ,A channel set by List 5 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 12. " INT_STAT_LIST6_COMPLETE ,List 6 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 13. " INT_STAT_LIST6_NOTIFY ,A channel set by List 6 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 14. " INT_STAT_LIST7_COMPLETE ,List 7 has completed and a new list can be loaded. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 15. " INT_STAT_LIST7_NOTIFY ,A channel set by List 7 has completed and the Notify bit had been set in the descriptor for that channel. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 16. " INT_STAT_CONTROL_DESCRIPTOR_INT0 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 0. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 17. " INT_STAT_CONTROL_DESCRIPTOR_INT1 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 1. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 18. " INT_STAT_CONTROL_DESCRIPTOR_INT2 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 2. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 19. " INT_STAT_CONTROL_DESCRIPTOR_INT3 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 3. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 20. " INT_STAT_CONTROL_DESCRIPTOR_INT4 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 4. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 21. " INT_STAT_CONTROL_DESCRIPTOR_INT5 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 5. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 22. " INT_STAT_CONTROL_DESCRIPTOR_INT6 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 6. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 23. " INT_STAT_CONTROL_DESCRIPTOR_INT7 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 7. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 24. " INT_STAT_CONTROL_DESCRIPTOR_INT8 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 8. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 25. " INT_STAT_CONTROL_DESCRIPTOR_INT9 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 9. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 26. " INT_STAT_CONTROL_DESCRIPTOR_INT10 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 10. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 27. " INT_STAT_CONTROL_DESCRIPTOR_INT11 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 11. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 28. " INT_STAT_CONTROL_DESCRIPTOR_INT12 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 12. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 29. " INT_STAT_CONTROL_DESCRIPTOR_INT13 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 13. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" textline " " bitfld.long 0x0 30. " INT_STAT_CONTROL_DESCRIPTOR_INT14 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 14. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" bitfld.long 0x0 31. " INT_STAT_CONTROL_DESCRIPTOR_INT15 ,A Send Interrupt Control Descriptor has been received by the list manager with a source value of 15. This event will cause a one to be set in this register until cleared by software. Write a 1 to this field to clear the value." "0,1" group.byte 0x8C++0x3 line.long 0x0 "VPE_INT0_LIST0_INT_MASK,The register gives the information of the interrupts that should be masked and not generate an interrupt for vpdma_int0." bitfld.long 0x0 0. " INT_MASK_LIST0_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 1. " INT_MASK_LIST0_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 2. " INT_MASK_LIST1_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 3. " INT_MASK_LIST1_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 4. " INT_MASK_LIST2_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 5. " INT_MASK_LIST2_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 6. " INT_MASK_LIST3_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 7. " INT_MASK_LIST3_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 8. " INT_MASK_LIST4_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 9. " INT_MASK_LIST4_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 10. " INT_MASK_LIST5_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 11. " INT_MASK_LIST5_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 12. " INT_MASK_LIST6_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 13. " INT_MASK_LIST6_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 14. " INT_MASK_LIST7_COMPLETE ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 15. " INT_MASK_LIST7_NOTIFY ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 16. " INT_MASK_CONTROL_DESCRIPTOR_INT0 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 17. " INT_MASK_CONTROL_DESCRIPTOR_INT1 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 18. " INT_MASK_CONTROL_DESCRIPTOR_INT2 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 19. " INT_MASK_CONTROL_DESCRIPTOR_INT3 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 20. " INT_MASK_CONTROL_DESCRIPTOR_INT4 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 21. " INT_MASK_CONTROL_DESCRIPTOR_INT5 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 22. " INT_MASK_CONTROL_DESCRIPTOR_INT6 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 23. " INT_MASK_CONTROL_DESCRIPTOR_INT7 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 24. " INT_MASK_CONTROL_DESCRIPTOR_INT8 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 25. " INT_MASK_CONTROL_DESCRIPTOR_INT9 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 26. " INT_MASK_CONTROL_DESCRIPTOR_INT10 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 27. " INT_MASK_CONTROL_DESCRIPTOR_INT11 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 28. " INT_MASK_CONTROL_DESCRIPTOR_INT12 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 29. " INT_MASK_CONTROL_DESCRIPTOR_INT13 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" textline " " bitfld.long 0x0 30. " INT_MASK_CONTROL_DESCRIPTOR_INT14 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" bitfld.long 0x0 31. " INT_MASK_CONTROL_DESCRIPTOR_INT15 ,The interrupt for should generate an interrupt on interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt signal." "0,1" group.byte 0x200++0x3 line.long 0x0 "VPE_PERF_MON0,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x204++0x3 line.long 0x0 "VPE_PERF_MON1,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x208++0x3 line.long 0x0 "VPE_PERF_MON2,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x20C++0x3 line.long 0x0 "VPE_PERF_MON3,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x210++0x3 line.long 0x0 "VPE_PERF_MON4,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x214++0x3 line.long 0x0 "VPE_PERF_MON5,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x218++0x3 line.long 0x0 "VPE_PERF_MON6,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x21C++0x3 line.long 0x0 "VPE_PERF_MON7,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x220++0x3 line.long 0x0 "VPE_PERF_MON8,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x224++0x3 line.long 0x0 "VPE_PERF_MON9,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x228++0x3 line.long 0x0 "VPE_PERF_MON10,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x22C++0x3 line.long 0x0 "VPE_PERF_MON11,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x230++0x3 line.long 0x0 "VPE_PERF_MON12,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x234++0x3 line.long 0x0 "VPE_PERF_MON13,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x238++0x3 line.long 0x0 "VPE_PERF_MON14,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x23C++0x3 line.long 0x0 "VPE_PERF_MON15,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x240++0x3 line.long 0x0 "VPE_PERF_MON16,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x244++0x3 line.long 0x0 "VPE_PERF_MON17,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x248++0x3 line.long 0x0 "VPE_PERF_MON18,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x24C++0x3 line.long 0x0 "VPE_PERF_MON19,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x250++0x3 line.long 0x0 "VPE_PERF_MON20,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x254++0x3 line.long 0x0 "VPE_PERF_MON21,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x258++0x3 line.long 0x0 "VPE_PERF_MON22,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x25C++0x3 line.long 0x0 "VPE_PERF_MON23,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x260++0x3 line.long 0x0 "VPE_PERF_MON24,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x264++0x3 line.long 0x0 "VPE_PERF_MON25,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x268++0x3 line.long 0x0 "VPE_PERF_MON26,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x26C++0x3 line.long 0x0 "VPE_PERF_MON27,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x270++0x3 line.long 0x0 "VPE_PERF_MON28,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x274++0x3 line.long 0x0 "VPE_PERF_MON29,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x278++0x3 line.long 0x0 "VPE_PERF_MON30,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x27C++0x3 line.long 0x0 "VPE_PERF_MON31,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x280++0x3 line.long 0x0 "VPE_PERF_MON32,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x284++0x3 line.long 0x0 "VPE_PERF_MON33,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x288++0x3 line.long 0x0 "VPE_PERF_MON34,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x28C++0x3 line.long 0x0 "VPE_PERF_MON35,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x290++0x3 line.long 0x0 "VPE_PERF_MON36,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x294++0x3 line.long 0x0 "VPE_PERF_MON37,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x298++0x3 line.long 0x0 "VPE_PERF_MON38,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x29C++0x3 line.long 0x0 "VPE_PERF_MON39,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A0++0x3 line.long 0x0 "VPE_PERF_MON40,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A4++0x3 line.long 0x0 "VPE_PERF_MON41,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2A8++0x3 line.long 0x0 "VPE_PERF_MON42,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2AC++0x3 line.long 0x0 "VPE_PERF_MON43,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B0++0x3 line.long 0x0 "VPE_PERF_MON44,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B4++0x3 line.long 0x0 "VPE_PERF_MON45,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2B8++0x3 line.long 0x0 "VPE_PERF_MON46,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2BC++0x3 line.long 0x0 "VPE_PERF_MON47,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C0++0x3 line.long 0x0 "VPE_PERF_MON48,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C4++0x3 line.long 0x0 "VPE_PERF_MON49,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value. 0: Running Average 1: Minimum Value 2: Maximum Value 3: Last Value" "0,1,2,3" group.byte 0x2C8++0x3 line.long 0x0 "VPE_PERF_MON50,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x2CC++0x3 line.long 0x0 "VPE_PERF_MON51,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x2D0++0x3 line.long 0x0 "VPE_PERF_MON52,The register can be used to capture timing differences between events in the VPDMA" hexmask.long.word 0x0 0.--15. 1. " CURR_COUNT ,The current value of the perfomance monitor counter" bitfld.long 0x0 16.--18. " START_COUNT ,Sets the value that starts the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20.--21. " START_CLIENT ,Sets the client whose event starts the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24.--26. " STOP_COUNT ,Sets the value that stops the performance monitor counter." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28.--29. " STOP_CLIENT ,Sets the client whose event stops the performance monitor counter." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " CAPTURE_MODE ,Sets how the counter should be updated. Updating this value will also clear the current counter stored value." "0,1,2,3" group.byte 0x300++0x3 line.long 0x0 "VPE_PRI_CHROMA_CSTAT,The register holds status information and control for the client." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8.--9. " LINE_MODE ,Selects the output mode of the line buffer." "0,1,2,3" textline " " bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" textline " " bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." textline " " hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x304++0x3 line.long 0x0 "VPE_PRI_LUMA_CSTAT,The register holds status information and control for the client." hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x308++0x3 line.long 0x0 "VPE_PRI_FLD1_LUMA_CSTAT,The register holds status information and control for the client." hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x30C++0x3 line.long 0x0 "VPE_PRI_FLD1_CHROMA_CSTAT,The register holds status information and control for the client." hexmask.long.byte 0x0 0.--7. 1. " _3_each_line_once_only_on_one_line_Each_data_line_gets_number_of_frame_lines_divided_by_number_of_buffered_lines ," bitfld.long 0x0 8.--9. " LINE_MODE ,Selects the output mode of the line buffer." "0,1,2,3" textline " " bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" textline " " bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." textline " " hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x310++0x3 line.long 0x0 "VPE_PRI_FLD2_LUMA_CSTAT,The register holds status information and control for the client." hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x314++0x3 line.long 0x0 "VPE_PRI_FLD2_CHROMA_CSTAT,The register holds status information and control for the client." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8.--9. " LINE_MODE ,Selects the output mode of the line buffer." "0,1,2,3" textline " " bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" textline " " bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." textline " " hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x330++0x3 line.long 0x0 "VPE_PRI_MV0_CSTAT,The register holds status information and control for the client." hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x33C++0x3 line.long 0x0 "VPE_PRI_MV_OUT_CSTAT,The register holds status information and control for the client." hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x390++0x3 line.long 0x0 "VPE_VIP0_UP_Y_CSTAT,The register holds status information and control for the client." hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x394++0x3 line.long 0x0 "VPE_VIP0_UP_UV_CSTAT,The register holds status information and control for the client." hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." group.byte 0x3D0++0x3 line.long 0x0 "VPE_VPI_CTL_CSTAT,The register holds status information and control for the client." hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10.--13. " FRAME_START ,The source of the start frame event for the client." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 14. " DMA_ACTIVE ,Signals if the client is currently actively sending DMA requests" "0,1" bitfld.long 0x0 15. " BUSY ,Signals if the client is currently active. This bit is set as soon as we the channel is received by the client from the list manager and is cleared when the channel is cleared from the shared memory." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " REQ_RATE ,The number of clock cycles between the last two requests issued. This value is multiplied by 32 to get the actual number of cycles.This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins." hexmask.long.byte 0x0 24.--31. 1. " REQ_DELAY ,The minimum number of clock cycles between requests being issued. This value is multiplied by 32 to get the actual number of cycles..This value is only accurate for the current frame. The internal counters used to calculate the rate are reset when a new frame begins and the first request of a frame will go as soon as possible." width 0x0B tree.end tree "HDMI_WP_L3_MAIN" base ad:0x58040000 width 18. group.byte 0x40++0x3 line.long 0x0 "HDMI_WP_PWR_CTRL,Power control" bitfld.long 0x0 0.--1. " PLL_PWR_STATUS ,Status of the power control of the HDMI PLL Control module" "0,1,2,3" bitfld.long 0x0 2.--3. " PLL_PWR_CMD ,Command for power control of the HDMI PLL Control module" "0,1,2,3" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved." group.byte 0x70++0x3 line.long 0x0 "HDMI_WP_CLK,Configuration of clocks" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8.--10. " SCP_PWR_DIV ,Defines the divisor value to be used for the generation of the SCP_PWR clock (up to 66.5MHz) from the input interface clock (up to 266MHz). 0x0 means gated 0x1 means free-running The valid values are from 0 to 7. In case of interface access to register through SCP interface, if the SCP_PWR clock is gated, the HW automatically generates the clock by using a divisor of 7 and updates the bit-field with the value 7. It is then software responsibility to change the value at any time in order to improve SCP latency when accessing the registers in the HDMI_PHY and PLLCTRL_HDMI by reducing the value." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," width 0x0B tree.end tree "DPLL_HDMI_L4_CFG" base ad:0x4A0A6000 width 33. group.byte 0x0++0x3 line.long 0x0 "PLLCTRL_HDMI_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x0 0.--2. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " PLL_SYSRESETN ,Force SYSRESETN." "0,1" textline " " bitfld.long 0x0 4. " HSDIV_SYSRESETN ,Force HSDIVIDER SYSRESETN." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reads as zero." group.byte 0x4++0x3 line.long 0x0 "PLLCTRL_HDMI_STATUS,This register contains the status information" bitfld.long 0x0 0. " PLLCTRL_RESET_DONE ,DPLL_HDMI reset done status" "0,1" bitfld.long 0x0 1. " PLL_LOCK ,DPLL_HDMI Lock status See the programming guide for the use of this bit" "0,1" textline " " bitfld.long 0x0 2. " PLL_RECAL ,DPLL_HDMI re-calibration status If this bit is active, the DPLL_HDMI needs to be re-calibrated" "0,1" bitfld.long 0x0 3. " PLL_LOSSREF ,DPLL_HDMI Reference Loss status" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 5. " PLL_HIGHJITTER ,DPLL_HDMI High Jitter status" "0,1" textline " " bitfld.long 0x0 6. " PLL_BYPASS ,DPLL_HDMI Bypass status" "0,1" bitfld.long 0x0 7.--8. " RESERVED ,Read returns zero." "0,1,2,3" textline " " bitfld.long 0x0 9. " BYPASSACKZ_MERGED ,Merged state of bypass mode on HDMI_PHY" "0,1" bitfld.long 0x0 10.--11. " RESERVED ,Read returns zero." "0,1,2,3" textline " " bitfld.long 0x0 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledgeNote: SSC feature is not supported enum=SSC_ACT ." "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reads as zero." group.byte 0x8++0x3 line.long 0x0 "PLLCTRL_HDMI_GO,This register contains the GO bit" bitfld.long 0x0 0. " PLL_GO ,Request (re-)locking sequence of the DPLL_HDMI. If the AutoMode bit is set, then this will be deferred until DISPC Update Sync goes active" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Wirte only zero for future compatibility. Reads return zero." group.byte 0xC++0x3 line.long 0x0 "PLLCTRL_HDMI_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0 0. " RESERVED ,Reserved." "0,1" hexmask.long.byte 0x0 1.--8. 1. " PLL_REGN ,N Divider for DPLL_HDMI (Reference). Divider value = PLL_REGN+1." textline " " hexmask.long.word 0x0 9.--20. 1. " PLL_REGM ,M Divider for DPLL_HDMI." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x10++0x3 line.long 0x0 "PLLCTRL_HDMI_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0 0. " PLL_IDLE ,DPLL_HDMI IDLE:" "0,1" bitfld.long 0x0 1.--3. " PLL_SELFREQDCO ,DCO frequency range selector for DPLL_HDMIOthers: Reserved ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " RESERVED ,Reads as zero." "0,1" bitfld.long 0x0 5. " PLL_PLLLPMODE ,Select the power / performance of the DPLL_HDMI" "0,1" textline " " bitfld.long 0x0 6. " PLL_LOWCURRSTBY ,DPLL_HDMI LOW CURRENT STANDBY" "0,1" bitfld.long 0x0 7. " RESERVED ,Reserved." "0,1" textline " " bitfld.long 0x0 8. " PLL_DRIFTGUARDEN ,DPLL_HDMI DRIFTGUARDEN" "0,1" bitfld.long 0x0 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the DPLL_HDMI" "0,1,2,3" textline " " bitfld.long 0x0 11. " PLL_CLKSEL ,Reference clock selection" "0,1" bitfld.long 0x0 12. " PLL_HIGHFREQ ,Enables a division of pixel clock by 2 before input to the DPLL_HDMI Required for pixel clock frequencies above 32 MHz (21 MHZ if N = 0)" "0,1" textline " " bitfld.long 0x0 13. " PLL_REFEN ,DPLL_HDMI reference clock control" "0,1" bitfld.long 0x0 14. " PHY_CLKINEN ,PHY clock control" "0,1" textline " " bitfld.long 0x0 15. " BYPASSEN ,Selects sub-system functional clock as PHY clock source" "0,1" bitfld.long 0x0 16.--19. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20. " HSDIVBYPASS ,Forces HSDIVIDER to bypass mode" "0,1" bitfld.long 0x0 21.--22. " REFSEL ,Selects the reference clock with optional divide by 2" "0,1,2,3" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved." group.byte 0x14++0x3 line.long 0x0 "PLLCTRL_HDMI_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 10.--17. 1. " PLL_SD ,Sigma delta divider setting for DPLL_HDMI based on the DPLL_HDMI lock configuration." textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved." group.byte 0x18++0x3 line.long 0x0 "PLLCTRL_HDMI_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation. Note: SSC feature is not supported." bitfld.long 0x0 0. " EN_SSC ,Spread Spectrum Clocking enable" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved." "0,1" textline " " bitfld.long 0x0 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved." group.byte 0x1C++0x3 line.long 0x0 "PLLCTRL_HDMI_SSC_CONFIGURATION2,Note: SSC feature is not supported." hexmask.long.tbyte 0x0 0.--19. 1. " DELTAM ,DeltaM control for dithering. Split into integer and fractional part.Bits [19:18] define the integer part . Bits [17:0] define the fractional part ." hexmask.long.word 0x0 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider (ModFreqDivider) control for dithering.The ModFreqDivider is split into Mantissa and 2(ModFreqDivider = ModFreqDividerMantissa * 2).Bits [29:23] define the Mantissa . Bits [22:20] define the Exponent ." textline " " bitfld.long 0x0 30. " DELTAM2 ,MSB of DeltaM control bus." "0,1" bitfld.long 0x0 31. " RESERVED ,Reads as zero" "0,1" group.byte 0x20++0x3 line.long 0x0 "PLLCTRL_HDMI_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL." hexmask.long.tbyte 0x0 0.--17. 1. " PLL_REGM_F ,Fractional part of M divider." hexmask.long.byte 0x0 18.--24. 1. " PLL_REGM2 ,M2 divider to configure DPLL_HDMI M2 divider factor." textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reads as zero." width 0x0B tree.end tree "DPLL_HDMI_L3_MAIN" base ad:0x58040200 width 33. group.byte 0x0++0x3 line.long 0x0 "PLLCTRL_HDMI_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x0 0.--2. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " PLL_SYSRESETN ,Force SYSRESETN." "0,1" textline " " bitfld.long 0x0 4. " HSDIV_SYSRESETN ,Force HSDIVIDER SYSRESETN." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reads as zero." group.byte 0x4++0x3 line.long 0x0 "PLLCTRL_HDMI_STATUS,This register contains the status information" bitfld.long 0x0 0. " PLLCTRL_RESET_DONE ,DPLL_HDMI reset done status" "0,1" bitfld.long 0x0 1. " PLL_LOCK ,DPLL_HDMI Lock status See the programming guide for the use of this bit" "0,1" textline " " bitfld.long 0x0 2. " PLL_RECAL ,DPLL_HDMI re-calibration status If this bit is active, the DPLL_HDMI needs to be re-calibrated" "0,1" bitfld.long 0x0 3. " PLL_LOSSREF ,DPLL_HDMI Reference Loss status" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 5. " PLL_HIGHJITTER ,DPLL_HDMI High Jitter status" "0,1" textline " " bitfld.long 0x0 6. " PLL_BYPASS ,DPLL_HDMI Bypass status" "0,1" bitfld.long 0x0 7.--8. " RESERVED ,Read returns zero." "0,1,2,3" textline " " bitfld.long 0x0 9. " BYPASSACKZ_MERGED ,Merged state of bypass mode on HDMI_PHY" "0,1" bitfld.long 0x0 10.--11. " RESERVED ,Read returns zero." "0,1,2,3" textline " " bitfld.long 0x0 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledgeNote: SSC feature is not supported enum=SSC_ACT ." "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reads as zero." group.byte 0x8++0x3 line.long 0x0 "PLLCTRL_HDMI_GO,This register contains the GO bit" bitfld.long 0x0 0. " PLL_GO ,Request (re-)locking sequence of the DPLL_HDMI. If the AutoMode bit is set, then this will be deferred until DISPC Update Sync goes active" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Wirte only zero for future compatibility. Reads return zero." group.byte 0xC++0x3 line.long 0x0 "PLLCTRL_HDMI_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0 0. " RESERVED ,Reserved." "0,1" hexmask.long.byte 0x0 1.--8. 1. " PLL_REGN ,N Divider for DPLL_HDMI (Reference). Divider value = PLL_REGN+1." textline " " hexmask.long.word 0x0 9.--20. 1. " PLL_REGM ,M Divider for DPLL_HDMI." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved." group.byte 0x10++0x3 line.long 0x0 "PLLCTRL_HDMI_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0 0. " PLL_IDLE ,DPLL_HDMI IDLE:" "0,1" bitfld.long 0x0 1.--3. " PLL_SELFREQDCO ,DCO frequency range selector for DPLL_HDMIOthers: Reserved ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " RESERVED ,Reads as zero." "0,1" bitfld.long 0x0 5. " PLL_PLLLPMODE ,Select the power / performance of the DPLL_HDMI" "0,1" textline " " bitfld.long 0x0 6. " PLL_LOWCURRSTBY ,DPLL_HDMI LOW CURRENT STANDBY" "0,1" bitfld.long 0x0 7. " RESERVED ,Reserved." "0,1" textline " " bitfld.long 0x0 8. " PLL_DRIFTGUARDEN ,DPLL_HDMI DRIFTGUARDEN" "0,1" bitfld.long 0x0 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the DPLL_HDMI" "0,1,2,3" textline " " bitfld.long 0x0 11. " PLL_CLKSEL ,Reference clock selection" "0,1" bitfld.long 0x0 12. " PLL_HIGHFREQ ,Enables a division of pixel clock by 2 before input to the DPLL_HDMI Required for pixel clock frequencies above 32 MHz (21 MHZ if N = 0)" "0,1" textline " " bitfld.long 0x0 13. " PLL_REFEN ,DPLL_HDMI reference clock control" "0,1" bitfld.long 0x0 14. " PHY_CLKINEN ,PHY clock control" "0,1" textline " " bitfld.long 0x0 15. " BYPASSEN ,Selects sub-system functional clock as PHY clock source" "0,1" bitfld.long 0x0 16.--19. " RESERVED ,Reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20. " HSDIVBYPASS ,Forces HSDIVIDER to bypass mode" "0,1" bitfld.long 0x0 21.--22. " REFSEL ,Selects the reference clock with optional divide by 2" "0,1,2,3" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved." group.byte 0x14++0x3 line.long 0x0 "PLLCTRL_HDMI_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reserved." hexmask.long.byte 0x0 10.--17. 1. " PLL_SD ,Sigma delta divider setting for DPLL_HDMI based on the DPLL_HDMI lock configuration." textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved." group.byte 0x18++0x3 line.long 0x0 "PLLCTRL_HDMI_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation. Note: SSC feature is not supported." bitfld.long 0x0 0. " EN_SSC ,Spread Spectrum Clocking enable" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved." "0,1" textline " " bitfld.long 0x0 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved." group.byte 0x1C++0x3 line.long 0x0 "PLLCTRL_HDMI_SSC_CONFIGURATION2,Note: SSC feature is not supported." hexmask.long.tbyte 0x0 0.--19. 1. " DELTAM ,DeltaM control for dithering. Split into integer and fractional part.Bits [19:18] define the integer part . Bits [17:0] define the fractional part ." hexmask.long.word 0x0 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider (ModFreqDivider) control for dithering.The ModFreqDivider is split into Mantissa and 2(ModFreqDivider = ModFreqDividerMantissa * 2).Bits [29:23] define the Mantissa . Bits [22:20] define the Exponent ." textline " " bitfld.long 0x0 30. " DELTAM2 ,MSB of DeltaM control bus." "0,1" bitfld.long 0x0 31. " RESERVED ,Reads as zero" "0,1" group.byte 0x20++0x3 line.long 0x0 "PLLCTRL_HDMI_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL." hexmask.long.tbyte 0x0 0.--17. 1. " PLL_REGM_F ,Fractional part of M divider." hexmask.long.byte 0x0 18.--24. 1. " PLL_REGM2 ,M2 divider to configure DPLL_HDMI M2 divider factor." textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reads as zero." width 0x0B tree.end tree "DPLL_VIDEO1_L4_CFG" base ad:0x4A0A4000 width 24. group.byte 0x0++0x3 line.long 0x0 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x0 0. " PLL_AUTOMODE ,Automatic update mode. If this bit is set then the configuration updates will be synchronized to DISPCUpdateSync. If this bit is clear configuration updates will be done immediately. Reserved when PLLCTRL_AUTO is 0." "0,1" bitfld.long 0x0 1. " PLL_GATEMODE ,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0." "0,1" textline " " bitfld.long 0x0 2. " PLL_HALTMODE ,Allow PLL to be halted if no activity. Reserved when PLLCTRL_AUTO is 0." "0,1" bitfld.long 0x0 3. " PLL_SYSRESET ,Force DPLL SYSRESETN. Reserved when DBGSSV is 1." "0,1" textline " " bitfld.long 0x0 4. " HSDIV_SYSRESET ,Force HSDIVIDER SYSRESETN. Reserved when DBGSSV is 1." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reads as zero." group.byte 0x4++0x3 line.long 0x0 "PLL_STATUS,This register contains the status information" bitfld.long 0x0 0. " PLLCTRL_RESET_DONE ,PLLCTRL reset done status" "0,1" bitfld.long 0x0 1. " PLL_LOCK ,PLL Lock status See the programming guide for the use of this bit" "0,1" textline " " bitfld.long 0x0 2. " PLL_RECAL ,PLL re-calibration status If this bit is active, the PLL needs to be re-calibrated" "0,1" bitfld.long 0x0 3. " PLL_LOSSREF ,PLL Reference Loss status" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 5. " PLL_HIGHJITTER ,PLL High Jitter status" "0,1" textline " " bitfld.long 0x0 6. " PLL_BYPASS ,PLL Bypass status" "0,1" bitfld.long 0x0 7. " M4_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ,Reads as zero." "0,1" bitfld.long 0x0 9. " BYPASSACKZ_MERGED ,Merged state of bypass mode on PHY and HSDIVIDER" "0,1" textline " " bitfld.long 0x0 10. " M6_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" bitfld.long 0x0 11. " M7_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" textline " " bitfld.long 0x0 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledgeNote: enum=SSC_inact ." "0,1" bitfld.long 0x0 13.--14. " BYPASSACKZ ,State of bypass mode on PHY and HSDIVIDER. The status is shown separately for each source." "0,1,2,3" textline " " bitfld.long 0x0 15. " PLL_LDOPWDN ,PLL LDOPWDN status." "0,1" bitfld.long 0x0 16. " PLL_TICOPWDN ,PLL TICOPWDN status." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reads as zero." group.byte 0x8++0x3 line.long 0x0 "PLL_GO,This register contains the GO bit" bitfld.long 0x0 0. " PLL_GO ,Request (re-)locking sequence of the PLL. If the AutoMode bit is set, then this will be deferred until DISPCUpdate Sync goes active" "0,1" bitfld.long 0x0 1. " HSDIVLOAD ,In manual mode start HSDIVIDER update sequence." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved. Write only zero for future compatibility. Reads return zero." group.byte 0xC++0x3 line.long 0x0 "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0 0. " RESERVED ,Read returns zero." "0,1" hexmask.long.byte 0x0 1.--8. 1. " PLL_REGN ,N Divider for PLL (Reference). Divider value = PLL_REGN+1. Valid values range is from 0 to 127. Values 128 and above are reserved and must not be used." textline " " hexmask.long.word 0x0 9.--20. 1. " PLL_REGM ,M Divider for PLL. Valid values range is from 1 to 2047. Values 2048 and above are reserved and must not be used. When the PLL_REGM bit field is set to 1, the PLL enters a MN-Bypass mode. The DCOCLK clock output goes low and remains low until the PLL exits MN-Bypass mode (by changing the PLL_REGM bit field to a value other than 0 or 1)." bitfld.long 0x0 21.--25. " M4_CLOCK_DIV ,Divider value for clock source M4REG Divider value = M4_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 31. " RESERVED ,Read returns zero." "0,1" group.byte 0x10++0x3 line.long 0x0 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0 0. " PLL_IDLE ,PLL IDLE:" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " RESERVED ,Reads as zero." "0,1" bitfld.long 0x0 5. " PLL_PLLLPMODE ,Select the power / performance of the PLL" "0,1" textline " " bitfld.long 0x0 6. " PLL_LOWCURRSTBY ,PLL LOW CURRENT STANDBY" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " PLL_DRIFTGUARDEN ,PLL DRIFTGUARDEN" "0,1" bitfld.long 0x0 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the PLL" "0,1,2,3" textline " " bitfld.long 0x0 11. " PLL_CLKSEL ,Reference clock selection" "0,1" bitfld.long 0x0 12. " PLL_HIGHFREQ ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N = 0)" "0,1" textline " " bitfld.long 0x0 13. " PLL_REFEN ,PLL reference clock control" "0,1" bitfld.long 0x0 14. " PHY_CLKINEN ,PHY clock control" "0,1" textline " " bitfld.long 0x0 15. " BYPASSEN ,Selects sub-system functional clock as PHY clock source" "0,1" bitfld.long 0x0 16. " M4_CLOCK_EN ,Enable for M4 clock source" "0,1" textline " " bitfld.long 0x0 17. " RESERVED ,Read returns zero" "0,1" bitfld.long 0x0 18. " RESERVED ,Read returns zero." "0,1" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 20. " HSDIVBYPASS ,Forces HSDIVIDER to bypass mode" "0,1" textline " " bitfld.long 0x0 21.--22. " REFSEL ,Selects the reference clock with optional divide by 2" "0,1,2,3" bitfld.long 0x0 23. " M6_CLOCK_EN ,Enable for M6 clock source" "0,1" textline " " bitfld.long 0x0 24. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 25. " M7_CLOCK_EN ,Enable for M7 clock source" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Read as zero." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14++0x3 line.long 0x0 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x0 0.--4. " M6_CLOCK_DIV ,Divider value for M6 divider. Divider value = M6_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " M7_CLOCK_DIV ,Divider value for M7 divider. Divider value = M7_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation. Note:" bitfld.long 0x0 0. " EN_SSC ,Spread Spectrum Clocking enable 0x0: Spread Spectrum Clocking disabled 0x1: Spread Spectrum Clocking enabled" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved. Reads return 0." "0,1" textline " " bitfld.long 0x0 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,RESERVED" group.byte 0x1C++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation. Note:" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAM ,DeltaM control for SSC. Split into integer and fractional parts. - Bits [19:18] define the integer part. - Bits [17:0] define the fractional part." hexmask.long.word 0x0 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider (ModFreqDivider) control for SSC. The ModFreqDivider is split into Mantissa and 2^Exponent(ModFreqDivider = ModFreqDividerMantissa * 2^ModFreqDividerExponent). - Bits [29:23] define the Mantissa. - Bits [22:20] define the Exponent." textline " " bitfld.long 0x0 30. " DELTAM2 ,MSB of DeltaM control bus." "0,1" bitfld.long 0x0 31. " RESERVED ,Reads as zero" "0,1" group.byte 0x20++0x3 line.long 0x0 "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL." hexmask.long.tbyte 0x0 0.--17. 1. " PLL_REGM_F ,Fractional part of M divider. NOTE: The feature is not supported in this device." hexmask.long.byte 0x0 18.--24. 1. " PLL_REGM2 ,M2 divider to configure PLL REGM2. NOTE: In this device, M2 divider is hardcoded in HW at 31 (0x1F)." textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reads as zero" width 0x0B tree.end tree "DPLL_VIDEO2_L4_CFG" base ad:0x4A0A5000 width 24. group.byte 0x0++0x3 line.long 0x0 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x0 0. " PLL_AUTOMODE ,Automatic update mode. If this bit is set then the configuration updates will be synchronized to DISPCUpdateSync. If this bit is clear configuration updates will be done immediately. Reserved when PLLCTRL_AUTO is 0." "0,1" bitfld.long 0x0 1. " PLL_GATEMODE ,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0." "0,1" textline " " bitfld.long 0x0 2. " PLL_HALTMODE ,Allow PLL to be halted if no activity. Reserved when PLLCTRL_AUTO is 0." "0,1" bitfld.long 0x0 3. " PLL_SYSRESET ,Force DPLL SYSRESETN. Reserved when DBGSSV is 1." "0,1" textline " " bitfld.long 0x0 4. " HSDIV_SYSRESET ,Force HSDIVIDER SYSRESETN. Reserved when DBGSSV is 1." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reads as zero." group.byte 0x4++0x3 line.long 0x0 "PLL_STATUS,This register contains the status information" bitfld.long 0x0 0. " PLLCTRL_RESET_DONE ,PLLCTRL reset done status" "0,1" bitfld.long 0x0 1. " PLL_LOCK ,PLL Lock status See the programming guide for the use of this bit" "0,1" textline " " bitfld.long 0x0 2. " PLL_RECAL ,PLL re-calibration status If this bit is active, the PLL needs to be re-calibrated" "0,1" bitfld.long 0x0 3. " PLL_LOSSREF ,PLL Reference Loss status" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 5. " PLL_HIGHJITTER ,PLL High Jitter status" "0,1" textline " " bitfld.long 0x0 6. " PLL_BYPASS ,PLL Bypass status" "0,1" bitfld.long 0x0 7. " M4_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ,Reads as zero." "0,1" bitfld.long 0x0 9. " BYPASSACKZ_MERGED ,Merged state of bypass mode on PHY and HSDIVIDER" "0,1" textline " " bitfld.long 0x0 10. " M6_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" bitfld.long 0x0 11. " M7_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" textline " " bitfld.long 0x0 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledgeNote: enum=SSC_inact ." "0,1" bitfld.long 0x0 13.--14. " BYPASSACKZ ,State of bypass mode on PHY and HSDIVIDER. The status is shown separately for each source." "0,1,2,3" textline " " bitfld.long 0x0 15. " PLL_LDOPWDN ,PLL LDOPWDN status." "0,1" bitfld.long 0x0 16. " PLL_TICOPWDN ,PLL TICOPWDN status." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reads as zero." group.byte 0x8++0x3 line.long 0x0 "PLL_GO,This register contains the GO bit" bitfld.long 0x0 0. " PLL_GO ,Request (re-)locking sequence of the PLL. If the AutoMode bit is set, then this will be deferred until DISPCUpdate Sync goes active" "0,1" bitfld.long 0x0 1. " HSDIVLOAD ,In manual mode start HSDIVIDER update sequence." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved. Write only zero for future compatibility. Reads return zero." group.byte 0xC++0x3 line.long 0x0 "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0 0. " RESERVED ,Read returns zero." "0,1" hexmask.long.byte 0x0 1.--8. 1. " PLL_REGN ,N Divider for PLL (Reference). Divider value = PLL_REGN+1. Valid values range is from 0 to 127. Values 128 and above are reserved and must not be used." textline " " hexmask.long.word 0x0 9.--20. 1. " PLL_REGM ,M Divider for PLL. Valid values range is from 1 to 2047. Values 2048 and above are reserved and must not be used. When the PLL_REGM bit field is set to 1, the PLL enters a MN-Bypass mode. The DCOCLK clock output goes low and remains low until the PLL exits MN-Bypass mode (by changing the PLL_REGM bit field to a value other than 0 or 1)." bitfld.long 0x0 21.--25. " M4_CLOCK_DIV ,Divider value for clock source M4REG Divider value = M4_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 31. " RESERVED ,Read returns zero." "0,1" group.byte 0x10++0x3 line.long 0x0 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0 0. " PLL_IDLE ,PLL IDLE:" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " RESERVED ,Reads as zero." "0,1" bitfld.long 0x0 5. " PLL_PLLLPMODE ,Select the power / performance of the PLL" "0,1" textline " " bitfld.long 0x0 6. " PLL_LOWCURRSTBY ,PLL LOW CURRENT STANDBY" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " PLL_DRIFTGUARDEN ,PLL DRIFTGUARDEN" "0,1" bitfld.long 0x0 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the PLL" "0,1,2,3" textline " " bitfld.long 0x0 11. " PLL_CLKSEL ,Reference clock selection" "0,1" bitfld.long 0x0 12. " PLL_HIGHFREQ ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N = 0)" "0,1" textline " " bitfld.long 0x0 13. " PLL_REFEN ,PLL reference clock control" "0,1" bitfld.long 0x0 14. " PHY_CLKINEN ,PHY clock control" "0,1" textline " " bitfld.long 0x0 15. " BYPASSEN ,Selects sub-system functional clock as PHY clock source" "0,1" bitfld.long 0x0 16. " M4_CLOCK_EN ,Enable for M4 clock source" "0,1" textline " " bitfld.long 0x0 17. " RESERVED ,Read returns zero" "0,1" bitfld.long 0x0 18. " RESERVED ,Read returns zero." "0,1" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 20. " HSDIVBYPASS ,Forces HSDIVIDER to bypass mode" "0,1" textline " " bitfld.long 0x0 21.--22. " REFSEL ,Selects the reference clock with optional divide by 2" "0,1,2,3" bitfld.long 0x0 23. " M6_CLOCK_EN ,Enable for M6 clock source" "0,1" textline " " bitfld.long 0x0 24. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 25. " M7_CLOCK_EN ,Enable for M7 clock source" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Read as zero." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14++0x3 line.long 0x0 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x0 0.--4. " M6_CLOCK_DIV ,Divider value for M6 divider. Divider value = M6_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " M7_CLOCK_DIV ,Divider value for M7 divider. Divider value = M7_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation. Note:" bitfld.long 0x0 0. " EN_SSC ,Spread Spectrum Clocking enable 0x0: Spread Spectrum Clocking disabled 0x1: Spread Spectrum Clocking enabled" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved. Reads return 0." "0,1" textline " " bitfld.long 0x0 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,RESERVED" group.byte 0x1C++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation. Note:" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAM ,DeltaM control for SSC. Split into integer and fractional parts. - Bits [19:18] define the integer part. - Bits [17:0] define the fractional part." hexmask.long.word 0x0 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider (ModFreqDivider) control for SSC. The ModFreqDivider is split into Mantissa and 2^Exponent(ModFreqDivider = ModFreqDividerMantissa * 2^ModFreqDividerExponent). - Bits [29:23] define the Mantissa. - Bits [22:20] define the Exponent." textline " " bitfld.long 0x0 30. " DELTAM2 ,MSB of DeltaM control bus." "0,1" bitfld.long 0x0 31. " RESERVED ,Reads as zero" "0,1" group.byte 0x20++0x3 line.long 0x0 "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL." hexmask.long.tbyte 0x0 0.--17. 1. " PLL_REGM_F ,Fractional part of M divider. NOTE: The feature is not supported in this device." hexmask.long.byte 0x0 18.--24. 1. " PLL_REGM2 ,M2 divider to configure PLL REGM2. NOTE: In this device, M2 divider is hardcoded in HW at 31 (0x1F)." textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reads as zero" width 0x0B tree.end tree "DPLL_VIDEO1_L3_MAIN" base ad:0x58004300 width 24. group.byte 0x0++0x3 line.long 0x0 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x0 0. " PLL_AUTOMODE ,Automatic update mode. If this bit is set then the configuration updates will be synchronized to DISPCUpdateSync. If this bit is clear configuration updates will be done immediately. Reserved when PLLCTRL_AUTO is 0." "0,1" bitfld.long 0x0 1. " PLL_GATEMODE ,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0." "0,1" textline " " bitfld.long 0x0 2. " PLL_HALTMODE ,Allow PLL to be halted if no activity. Reserved when PLLCTRL_AUTO is 0." "0,1" bitfld.long 0x0 3. " PLL_SYSRESET ,Force DPLL SYSRESETN. Reserved when DBGSSV is 1." "0,1" textline " " bitfld.long 0x0 4. " HSDIV_SYSRESET ,Force HSDIVIDER SYSRESETN. Reserved when DBGSSV is 1." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reads as zero." group.byte 0x4++0x3 line.long 0x0 "PLL_STATUS,This register contains the status information" bitfld.long 0x0 0. " PLLCTRL_RESET_DONE ,PLLCTRL reset done status" "0,1" bitfld.long 0x0 1. " PLL_LOCK ,PLL Lock status See the programming guide for the use of this bit" "0,1" textline " " bitfld.long 0x0 2. " PLL_RECAL ,PLL re-calibration status If this bit is active, the PLL needs to be re-calibrated" "0,1" bitfld.long 0x0 3. " PLL_LOSSREF ,PLL Reference Loss status" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 5. " PLL_HIGHJITTER ,PLL High Jitter status" "0,1" textline " " bitfld.long 0x0 6. " PLL_BYPASS ,PLL Bypass status" "0,1" bitfld.long 0x0 7. " M4_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ,Reads as zero." "0,1" bitfld.long 0x0 9. " BYPASSACKZ_MERGED ,Merged state of bypass mode on PHY and HSDIVIDER" "0,1" textline " " bitfld.long 0x0 10. " M6_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" bitfld.long 0x0 11. " M7_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" textline " " bitfld.long 0x0 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledgeNote: enum=SSC_inact ." "0,1" bitfld.long 0x0 13.--14. " BYPASSACKZ ,State of bypass mode on PHY and HSDIVIDER. The status is shown separately for each source." "0,1,2,3" textline " " bitfld.long 0x0 15. " PLL_LDOPWDN ,PLL LDOPWDN status." "0,1" bitfld.long 0x0 16. " PLL_TICOPWDN ,PLL TICOPWDN status." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reads as zero." group.byte 0x8++0x3 line.long 0x0 "PLL_GO,This register contains the GO bit" bitfld.long 0x0 0. " PLL_GO ,Request (re-)locking sequence of the PLL. If the AutoMode bit is set, then this will be deferred until DISPCUpdate Sync goes active" "0,1" bitfld.long 0x0 1. " HSDIVLOAD ,In manual mode start HSDIVIDER update sequence." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved. Write only zero for future compatibility. Reads return zero." group.byte 0xC++0x3 line.long 0x0 "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0 0. " RESERVED ,Read returns zero." "0,1" hexmask.long.byte 0x0 1.--8. 1. " PLL_REGN ,N Divider for PLL (Reference). Divider value = PLL_REGN+1. Valid values range is from 0 to 127. Values 128 and above are reserved and must not be used." textline " " hexmask.long.word 0x0 9.--20. 1. " PLL_REGM ,M Divider for PLL. Valid values range is from 1 to 2047. Values 2048 and above are reserved and must not be used. When the PLL_REGM bit field is set to 1, the PLL enters a MN-Bypass mode. The DCOCLK clock output goes low and remains low until the PLL exits MN-Bypass mode (by changing the PLL_REGM bit field to a value other than 0 or 1)." bitfld.long 0x0 21.--25. " M4_CLOCK_DIV ,Divider value for clock source M4REG Divider value = M4_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 31. " RESERVED ,Read returns zero." "0,1" group.byte 0x10++0x3 line.long 0x0 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0 0. " PLL_IDLE ,PLL IDLE:" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " RESERVED ,Reads as zero." "0,1" bitfld.long 0x0 5. " PLL_PLLLPMODE ,Select the power / performance of the PLL" "0,1" textline " " bitfld.long 0x0 6. " PLL_LOWCURRSTBY ,PLL LOW CURRENT STANDBY" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " PLL_DRIFTGUARDEN ,PLL DRIFTGUARDEN" "0,1" bitfld.long 0x0 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the PLL" "0,1,2,3" textline " " bitfld.long 0x0 11. " PLL_CLKSEL ,Reference clock selection" "0,1" bitfld.long 0x0 12. " PLL_HIGHFREQ ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N = 0)" "0,1" textline " " bitfld.long 0x0 13. " PLL_REFEN ,PLL reference clock control" "0,1" bitfld.long 0x0 14. " PHY_CLKINEN ,PHY clock control" "0,1" textline " " bitfld.long 0x0 15. " BYPASSEN ,Selects sub-system functional clock as PHY clock source" "0,1" bitfld.long 0x0 16. " M4_CLOCK_EN ,Enable for M4 clock source" "0,1" textline " " bitfld.long 0x0 17. " RESERVED ,Read returns zero" "0,1" bitfld.long 0x0 18. " RESERVED ,Read returns zero." "0,1" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 20. " HSDIVBYPASS ,Forces HSDIVIDER to bypass mode" "0,1" textline " " bitfld.long 0x0 21.--22. " REFSEL ,Selects the reference clock with optional divide by 2" "0,1,2,3" bitfld.long 0x0 23. " M6_CLOCK_EN ,Enable for M6 clock source" "0,1" textline " " bitfld.long 0x0 24. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 25. " M7_CLOCK_EN ,Enable for M7 clock source" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Read as zero." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14++0x3 line.long 0x0 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x0 0.--4. " M6_CLOCK_DIV ,Divider value for M6 divider. Divider value = M6_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " M7_CLOCK_DIV ,Divider value for M7 divider. Divider value = M7_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation. Note:" bitfld.long 0x0 0. " EN_SSC ,Spread Spectrum Clocking enable 0x0: Spread Spectrum Clocking disabled 0x1: Spread Spectrum Clocking enabled" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved. Reads return 0." "0,1" textline " " bitfld.long 0x0 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,RESERVED" group.byte 0x1C++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation. Note:" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAM ,DeltaM control for SSC. Split into integer and fractional parts. - Bits [19:18] define the integer part. - Bits [17:0] define the fractional part." hexmask.long.word 0x0 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider (ModFreqDivider) control for SSC. The ModFreqDivider is split into Mantissa and 2^Exponent(ModFreqDivider = ModFreqDividerMantissa * 2^ModFreqDividerExponent). - Bits [29:23] define the Mantissa. - Bits [22:20] define the Exponent." textline " " bitfld.long 0x0 30. " DELTAM2 ,MSB of DeltaM control bus." "0,1" bitfld.long 0x0 31. " RESERVED ,Reads as zero" "0,1" group.byte 0x20++0x3 line.long 0x0 "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL." hexmask.long.tbyte 0x0 0.--17. 1. " PLL_REGM_F ,Fractional part of M divider. NOTE: The feature is not supported in this device." hexmask.long.byte 0x0 18.--24. 1. " PLL_REGM2 ,M2 divider to configure PLL REGM2. NOTE: In this device, M2 divider is hardcoded in HW at 31 (0x1F)." textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reads as zero" width 0x0B tree.end tree "DPLL_VIDEO2_L3_MAIN" base ad:0x58009300 width 24. group.byte 0x0++0x3 line.long 0x0 "PLL_CONTROL,This register controls the PLL reset/power and modes" bitfld.long 0x0 0. " PLL_AUTOMODE ,Automatic update mode. If this bit is set then the configuration updates will be synchronized to DISPCUpdateSync. If this bit is clear configuration updates will be done immediately. Reserved when PLLCTRL_AUTO is 0." "0,1" bitfld.long 0x0 1. " PLL_GATEMODE ,Allow PLL clock gating for power saving Reserved when PLLCTRL_AUTO is 0." "0,1" textline " " bitfld.long 0x0 2. " PLL_HALTMODE ,Allow PLL to be halted if no activity. Reserved when PLLCTRL_AUTO is 0." "0,1" bitfld.long 0x0 3. " PLL_SYSRESET ,Force DPLL SYSRESETN. Reserved when DBGSSV is 1." "0,1" textline " " bitfld.long 0x0 4. " HSDIV_SYSRESET ,Force HSDIVIDER SYSRESETN. Reserved when DBGSSV is 1." "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reads as zero." group.byte 0x4++0x3 line.long 0x0 "PLL_STATUS,This register contains the status information" bitfld.long 0x0 0. " PLLCTRL_RESET_DONE ,PLLCTRL reset done status" "0,1" bitfld.long 0x0 1. " PLL_LOCK ,PLL Lock status See the programming guide for the use of this bit" "0,1" textline " " bitfld.long 0x0 2. " PLL_RECAL ,PLL re-calibration status If this bit is active, the PLL needs to be re-calibrated" "0,1" bitfld.long 0x0 3. " PLL_LOSSREF ,PLL Reference Loss status" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 5. " PLL_HIGHJITTER ,PLL High Jitter status" "0,1" textline " " bitfld.long 0x0 6. " PLL_BYPASS ,PLL Bypass status" "0,1" bitfld.long 0x0 7. " M4_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ,Reads as zero." "0,1" bitfld.long 0x0 9. " BYPASSACKZ_MERGED ,Merged state of bypass mode on PHY and HSDIVIDER" "0,1" textline " " bitfld.long 0x0 10. " M6_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" bitfld.long 0x0 11. " M7_CLOCK_ACK ,Acknowledge for enable of sub-system clock Verify the status before selecting this source in the sub-system clock mux" "0,1" textline " " bitfld.long 0x0 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledgeNote: enum=SSC_inact ." "0,1" bitfld.long 0x0 13.--14. " BYPASSACKZ ,State of bypass mode on PHY and HSDIVIDER. The status is shown separately for each source." "0,1,2,3" textline " " bitfld.long 0x0 15. " PLL_LDOPWDN ,PLL LDOPWDN status." "0,1" bitfld.long 0x0 16. " PLL_TICOPWDN ,PLL TICOPWDN status." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reads as zero." group.byte 0x8++0x3 line.long 0x0 "PLL_GO,This register contains the GO bit" bitfld.long 0x0 0. " PLL_GO ,Request (re-)locking sequence of the PLL. If the AutoMode bit is set, then this will be deferred until DISPCUpdate Sync goes active" "0,1" bitfld.long 0x0 1. " HSDIVLOAD ,In manual mode start HSDIVIDER update sequence." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved. Write only zero for future compatibility. Reads return zero." group.byte 0xC++0x3 line.long 0x0 "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0 0. " RESERVED ,Read returns zero." "0,1" hexmask.long.byte 0x0 1.--8. 1. " PLL_REGN ,N Divider for PLL (Reference). Divider value = PLL_REGN+1. Valid values range is from 0 to 127. Values 128 and above are reserved and must not be used." textline " " hexmask.long.word 0x0 9.--20. 1. " PLL_REGM ,M Divider for PLL. Valid values range is from 1 to 2047. Values 2048 and above are reserved and must not be used. When the PLL_REGM bit field is set to 1, the PLL enters a MN-Bypass mode. The DCOCLK clock output goes low and remains low until the PLL exits MN-Bypass mode (by changing the PLL_REGM bit field to a value other than 0 or 1)." bitfld.long 0x0 21.--25. " M4_CLOCK_DIV ,Divider value for clock source M4REG Divider value = M4_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 31. " RESERVED ,Read returns zero." "0,1" group.byte 0x10++0x3 line.long 0x0 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0 0. " PLL_IDLE ,PLL IDLE:" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " RESERVED ,Reads as zero." "0,1" bitfld.long 0x0 5. " PLL_PLLLPMODE ,Select the power / performance of the PLL" "0,1" textline " " bitfld.long 0x0 6. " PLL_LOWCURRSTBY ,PLL LOW CURRENT STANDBY" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " PLL_DRIFTGUARDEN ,PLL DRIFTGUARDEN" "0,1" bitfld.long 0x0 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the PLL" "0,1,2,3" textline " " bitfld.long 0x0 11. " PLL_CLKSEL ,Reference clock selection" "0,1" bitfld.long 0x0 12. " PLL_HIGHFREQ ,Enables a division of pixel clock by 2 before input to the PLL Required for pixel clock frequencies above 32 MHz (21 MHZ if N = 0)" "0,1" textline " " bitfld.long 0x0 13. " PLL_REFEN ,PLL reference clock control" "0,1" bitfld.long 0x0 14. " PHY_CLKINEN ,PHY clock control" "0,1" textline " " bitfld.long 0x0 15. " BYPASSEN ,Selects sub-system functional clock as PHY clock source" "0,1" bitfld.long 0x0 16. " M4_CLOCK_EN ,Enable for M4 clock source" "0,1" textline " " bitfld.long 0x0 17. " RESERVED ,Read returns zero" "0,1" bitfld.long 0x0 18. " RESERVED ,Read returns zero." "0,1" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 20. " HSDIVBYPASS ,Forces HSDIVIDER to bypass mode" "0,1" textline " " bitfld.long 0x0 21.--22. " REFSEL ,Selects the reference clock with optional divide by 2" "0,1,2,3" bitfld.long 0x0 23. " M6_CLOCK_EN ,Enable for M6 clock source" "0,1" textline " " bitfld.long 0x0 24. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 25. " M7_CLOCK_EN ,Enable for M7 clock source" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Read as zero." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14++0x3 line.long 0x0 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" bitfld.long 0x0 0.--4. " M6_CLOCK_DIV ,Divider value for M6 divider. Divider value = M6_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " M7_CLOCK_DIV ,Divider value for M7 divider. Divider value = M7_CLOCK_DIV + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation. Note:" bitfld.long 0x0 0. " EN_SSC ,Spread Spectrum Clocking enable 0x0: Spread Spectrum Clocking disabled 0x1: Spread Spectrum Clocking enabled" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved. Reads return 0." "0,1" textline " " bitfld.long 0x0 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,RESERVED" group.byte 0x1C++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION2,Configuration for PLL Spread Spectrum Clocking modulation. Note:" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAM ,DeltaM control for SSC. Split into integer and fractional parts. - Bits [19:18] define the integer part. - Bits [17:0] define the fractional part." hexmask.long.word 0x0 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider (ModFreqDivider) control for SSC. The ModFreqDivider is split into Mantissa and 2^Exponent(ModFreqDivider = ModFreqDividerMantissa * 2^ModFreqDividerExponent). - Bits [29:23] define the Mantissa. - Bits [22:20] define the Exponent." textline " " bitfld.long 0x0 30. " DELTAM2 ,MSB of DeltaM control bus." "0,1" bitfld.long 0x0 31. " RESERVED ,Reads as zero" "0,1" group.byte 0x20++0x3 line.long 0x0 "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL." hexmask.long.tbyte 0x0 0.--17. 1. " PLL_REGM_F ,Fractional part of M divider. NOTE: The feature is not supported in this device." hexmask.long.byte 0x0 18.--24. 1. " PLL_REGM2 ,M2 divider to configure PLL REGM2. NOTE: In this device, M2 divider is hardcoded in HW at 31 (0x1F)." textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reads as zero" width 0x0B tree.end tree "OCP2SCP2_L4_CFG" base ad:0x4A0A0000 width 19. group.byte 0x0++0x3 line.long 0x0 "OCP2SCP_REVISION,IP Revision Identifier (X.Y.R)" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "OCP2SCP_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x0 0. " AUTOIDLE ,OCP clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software Reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,00 Force Idle. An idle request is acknowledged unconditionally. 01 No Idle. An idle request is never acknowledged. 10 Smart Idle. The acknowledgement to an idle request is given based on the internal activity (see 4.1.2). 11 Smart Idle Wakeup." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "OCP2SCP_SYSSTATUS,System Status register." bitfld.long 0x0 0. " RESETDONE ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "OCP2SCP_TIMING,Timing constraints for the OCP2SCP module." bitfld.long 0x0 0.--3. " SYNC2 ,Number of SCPclock cycles defining SYNC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " SYNC1 ,Number of SCPclock cycles defining SYNC1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7.--9. " DIVISIONRATIO ,Division Ration of the SCP clock in relation to OCP input clock." "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved." width 0x0B tree.end tree "DSI1_A_L3_MAIN" base ad:0x58004000 width 14. group.byte 0x54++0x3 line.long 0x0 "DSI_CLK_CTRL,CLOCK CONTROL This register controls the CLOCK GENERATION. The register can be modified only when IF_EN is reset." hexmask.long.word 0x0 0.--13. 1. " RESERVED ,Reserved" bitfld.long 0x0 14. " CIO_CLK_ICG ,Gates SCPClk clock provided to DSI-PHY and PLL-CTRL module. 0x0: Disabled. SCPClk is not generated. It remains at 0. 0x1: Enabled. SCPClk is generated (OCP_CLK/4)" "0,1" textline " " hexmask.long.word 0x0 15.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28.--29. " PLL_PWR_STATUS ,Status of the power control of the DSI PLL Control module Read 0x0: DSI PLL Control module in OFF state Read 0x1: DSI PLL Control module in ON state for PLL only (HSDIVISER is OFF) Read 0x2: DSI PLL Control module in ON state for both PLL and HSDIVISER Read 0x3: DSI PLL Control module in ON state for both PLL and HSDIVISER (no clock output to the DSI PHY)" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " PLL_PWR_CMD ,Command for power control of the DSI PLL Control Module 0x0: Command to change to OFF state 0x1: Command to change to ON state for PLL only (HSDIVISER is OFF) 0x2: Command to change to ON state for both PLL and HSDIVISER 0x3: Command to change to ON state for both PLL and HSDIVISER (no clock output to the DSI PHY)" "0,1,2,3" width 0x0B tree.end tree "DSI1_C_L3_MAIN" base ad:0x58009000 width 14. group.byte 0x54++0x3 line.long 0x0 "DSI_CLK_CTRL,CLOCK CONTROL This register controls the CLOCK GENERATION. The register can be modified only when IF_EN is reset." hexmask.long.word 0x0 0.--13. 1. " RESERVED ,Reserved" bitfld.long 0x0 14. " CIO_CLK_ICG ,Gates SCPClk clock provided to DSI-PHY and PLL-CTRL module. 0x0: Disabled. SCPClk is not generated. It remains at 0. 0x1: Enabled. SCPClk is generated (OCP_CLK/4)" "0,1" textline " " hexmask.long.word 0x0 15.--27. 1. " RESERVED ,Reserved" bitfld.long 0x0 28.--29. " PLL_PWR_STATUS ,Status of the power control of the DSI PLL Control module Read 0x0: DSI PLL Control module in OFF state Read 0x1: DSI PLL Control module in ON state for PLL only (HSDIVISER is OFF) Read 0x2: DSI PLL Control module in ON state for both PLL and HSDIVISER Read 0x3: DSI PLL Control module in ON state for both PLL and HSDIVISER (no clock output to the DSI PHY)" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " PLL_PWR_CMD ,Command for power control of the DSI PLL Control Module 0x0: Command to change to OFF state 0x1: Command to change to ON state for PLL only (HSDIVISER is OFF) 0x2: Command to change to ON state for both PLL and HSDIVISER 0x3: Command to change to ON state for both PLL and HSDIVISER (no clock output to the DSI PHY)" "0,1,2,3" width 0x0B tree.end tree "DSS_L3_MAIN" base ad:0x58000000 width 15. group.byte 0x0++0x3 line.long 0x0 "DSS_REVISION,This register contains the DSS revision number." hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x14++0x3 line.long 0x0 "DSS_SYSSTATUS,This register provides status information about the module." bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "DSS_CTRL,This register contains the DSS control bits." bitfld.long 0x0 0. " LCD1_CLK_SWITCH ,DSS_CLK/DPLL_DSI1_A_CLK1 clock switch (multiplexer 2) Selects the clock source for the DISPC LCD1_CLK clock" "0,1" bitfld.long 0x0 1.--6. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7.--9. " F_CLK_SWITCH ,Selects the clock source for the DISPC functional clock F_CLK" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10.--11. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 12. " LCD2_CLK_SWITCH ,DSS_CLK clock switch (multiplexer 3) Selects the clock source for the DISPC LCD2_CLK clock" "0,1" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--17. " PARALLEL_SEL ,Selection between LCD1, LCD2, LCD3 and TV channel out on the parallel output (multiplexer 13)" "0,1,2,3" bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 19. " LCD3_CLK_SWITCH ,DSS_CLK/DPLL_DSI1_C_CLK1 clock switch (multiplexer 10) Selects the clock source for the DISPC LCD3_CLK clock" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "DSS_STATUS,This register contains the DSS status." bitfld.long 0x0 0.--1. " LCD1_CLK_STATUS ,LCD1_CLK clock selection status (multiplexer 2) indicates which clock is used by the glitch free mux selecting the source of LCD1_CLK. It is required to have the current clock and the new selected clock being running in order to be able to switch. Both clocks are used at the same time while the switch is on going." "0,1,2,3" hexmask.long.word 0x0 2.--10. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 11.--12. " LCD2_CLK_STATUS ,LCD2_CLK clock selection status (multiplexer 3) indicates which clock is used by the glitch free mux selecting the source of LCD2_CLK. It is required to have the current clock and the new selected clock being running in order to be able to switch. Both clocks are used at the same time while the switch is on going." "0,1,2,3" bitfld.long 0x0 13.--14. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 15.--19. " F_CLK_STATUS ,F_CLK clock selection status (multiplexer 1) indicates which clock is used by the glitch free mux selecting the source of F_CLK. It is required to have the current clock and the new selected clock being running in order to be able to switch. Both clocks are used at the same time while the switch is on going." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--25. " LCD3_CLK_STATUS ,LCD3_CLK clock selection status (multiplexer 10) indicates which clock is used by the glitch free mux selecting the source of LCD3_CLK. It is required to have the current clock and the new selected clock being running in order to be able to switch. Both clocks are used at the same time while the switch is on going." "0,1,2,3" bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree "DISPC" base ad:0x58001000 width 30. group.byte 0x0++0x3 line.long 0x0 "DISPC_REVISION,IP Revision" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "DISPC_SYSCONFIG,This register allows to control various parameters of the OCP interface." bitfld.long 0x0 0. " AUTOIDLE ,Internal interface clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENWAKEUP ,WakeUp feature control" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Slave interface power management, Idle req/ack control" "0,1,2,3" textline " " bitfld.long 0x0 5. " WARMRESET ,Warm reset. Set this bit to 1 triggers a module warm reset. The bit is automatically reset by the hardware. During reads, it always returns 0. The warm reset keep the configuration registers unchanged." "0,1" bitfld.long 0x0 6.--7. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " MIDLEMODE ,Master interface power management, standby/wait control" "0,1,2,3" hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads returns 0." group.byte 0x14++0x3 line.long 0x0 "DISPC_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information." bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x18++0x3 line.long 0x0 "DISPC_IRQSTATUS,This register regroups all the status of the module internal events that generate an interrupt. Write 1 to a given bit resets this bit" bitfld.long 0x0 0. " FRAME_DONE1_IRQ ,Frame done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent." "0,1" bitfld.long 0x0 1. " VSYNC1_IRQ ,Vertical synchronization for the primary LCD." "0,1" textline " " bitfld.long 0x0 2. " EVSYNC_EVEN_IRQ ,VSYNC for even field from the TV encoder (HDMI)" "0,1" bitfld.long 0x0 3. " EVSYNC_ODD_IRQ ,VSYNC for odd field from the TV encoder (HDMI)" "0,1" textline " " bitfld.long 0x0 4. " ACBIASCOUNT_STATUS1_IRQ ,AC bias count status for the primary LCD" "0,1" bitfld.long 0x0 5. " PROGRAMMED_LINENUMBER_IRQ ,Programmed line number. It indicates that the scan of the primary LCD has reached the programmed user line number." "0,1" textline " " bitfld.long 0x0 6. " GFXBUFFER_UNDERFLOW_IRQ ,Graphics DMA buffer underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)" "0,1" bitfld.long 0x0 7. " GFXEND_WINDOW_IRQ ,The end of the graphics wndow has been reached. It is detected by the overlay manager when the full graphics has been displayed." "0,1" textline " " bitfld.long 0x0 8. " PALETTEGAMMA_LOADING_IRQ ,Palette Gamma loading status. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded successfully.NOTE: CLUT and BITMAP formats are not supported in this family of devices. ." "0,1" bitfld.long 0x0 9. " OCPERROR_IRQ ,OCP error. L3_MAIN Interconnect has sent SResp=ERR." "0,1" textline " " bitfld.long 0x0 10. " VID1BUFFER_UNDERFLOW_IRQ ,Video 1 DMA buffer underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)" "0,1" bitfld.long 0x0 11. " VID1END_WINDOW_IRQ ,The end of the video 1 Window has been reached. It is detected by the overlay manager when the full video 1 has been displayed." "0,1" textline " " bitfld.long 0x0 12. " VID2BUFFER_UNDERFLOW_IRQ ,Video 2 DMA buffer underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)" "0,1" bitfld.long 0x0 13. " VID2END_WINDOW_IRQ ,The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed." "0,1" textline " " bitfld.long 0x0 14. " SYNC_LOST1_IRQ ,Synchronizationl ost on the primary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the primary LCD output." "0,1" bitfld.long 0x0 15. " SYNCLOST_TV_IRQ ,Synchronization lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output." "0,1" textline " " bitfld.long 0x0 16. " WAKEUP_IRQ ,Wakeup" "0,1" bitfld.long 0x0 17. " SYNC_LOST2_IRQ ,Synchronization lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output." "0,1" textline " " bitfld.long 0x0 18. " VSYNC2_IRQ ,Vertical synchronization for the secondary LCD" "0,1" bitfld.long 0x0 19. " VID3END_WINDOW_IRQ ,The end of the video 3 window has been reached. It is detected by the overlay manager when the full video 3 has been displayed." "0,1" textline " " bitfld.long 0x0 20. " VID3BUFFER_UNDERFLOW_IRQ ,Video 3 DMA buffer underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)" "0,1" bitfld.long 0x0 21. " ACBIASCOUNT_STATUS2_IRQ ,AC bias count status for the secondary LCD" "0,1" textline " " bitfld.long 0x0 22. " FRAME_DONE2_IRQ ,Frame done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent." "0,1" bitfld.long 0x0 23. " FRAME_DONEWB_IRQ ,Frame done for the write-back channel. The write-back channel has output the frame. All the data of the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-back channel to be transferred to memory. It is available only when the write-back pipeline transfers back to memory the output of one of the pipelines. In case of overlay capture, the interrupt is not generated and the user shall use the FrameDone for the corresponding captured output." "0,1" textline " " bitfld.long 0x0 24. " FRAME_DONETV_IRQ ,Frame done for the TV. The TV output has been disabled by user. All the data have been sent." "0,1" bitfld.long 0x0 25. " WBBUFFER_OVERFLOW_IRQ ,Write-back DMA buffer overflow. The DMA buffer is full." "0,1" textline " " bitfld.long 0x0 26. " WBUNCOMPLETE_ERROR_IRQ ,Write-back DMA buffer is flushed before it is completely drained.In WB capture mode, if the new frame starts before the WB DMA buffers are fully drained (onto external memory), then the contents of the WB DMA buffers are lost (implying last few pixels/lines are corrupted in the captured frame in memory). This interrupt is an indication of that case and will trigger every frame ." "0,1" bitfld.long 0x0 27. " SYNCLOST3_IRQ ,Synchronization lost on the third LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the third LCD output." "0,1" textline " " bitfld.long 0x0 28. " VSYNC3_IRQ ,Vertical synchronization for the third LCD" "0,1" bitfld.long 0x0 29. " ACBIASCOUNT_STATUS3_IRQ ,AC bias count status for the third LCD" "0,1" textline " " bitfld.long 0x0 30. " FRAMEDONE3_IRQ ,Frame done for the third LCD. The third LCD output has been disabled by user. All the data have been sent." "0,1" bitfld.long 0x0 31. " FLIPIMMEDIATEDONE_IRQ ,Flip Immediate Done. The DMA engine has acknowledged the immediate BA change, and software can write the new BA0." "0,1" group.byte 0x1C++0x3 line.long 0x0 "DISPC_IRQENABLE,This register allows to mask/unmask the module internal sources of interrupt, on an event-by-event basis" bitfld.long 0x0 0. " FRAMEDONE_EN ,Frame done for the primary LCD. The primary LCD output has been disabled by user. All the data have been sent." "0,1" bitfld.long 0x0 1. " VSYNC1_EN ,Vertical synchronization for the primary LCD." "0,1" textline " " bitfld.long 0x0 2. " EVSYNC_EVEN_EN ,VSYNC for even field from the TV encoder (HDMI)" "0,1" bitfld.long 0x0 3. " EVSYNC_ODD_EN ,VSYNC for odd field from the TV encoder (HDMI)" "0,1" textline " " bitfld.long 0x0 4. " ACBIASCOUNT_STATUS1_EN ,AC Bias count status for the primary LCD" "0,1" bitfld.long 0x0 5. " PROGRAMMED_LINENUMBER_EN ,Programmed Line Number. It indicates that the scan of the primary LCD has reached the programmed user line number." "0,1" textline " " bitfld.long 0x0 6. " GFXBUFFER_UNDERFLOW_EN ,Graphics DMA Buffer Underflow. The DMA buffer is not necessarily empty but required data are not present in the DMA buffer (due to out of order responses)" "0,1" bitfld.long 0x0 7. " GFXEND_WINDOW_EN ,The end of the graphics Window has been reached. It is detected by the overlay manager when the full graphics has been displayed." "0,1" textline " " bitfld.long 0x0 8. " PALETTE_GAMMA_EN ,Palette gamma loading mask. The palette used as Color Look Up Table (CLUT) for the graphics BITMAP formats (1-, 2-, 4-, or 4-bpp) or as gamma table for the overlay output for the primary LCD output has been loaded successfully.NOTE: CLUT and BITMAP formats are not supported in this family of devices. ." "0,1" bitfld.long 0x0 9. " OCPERROR_EN ,OCP Error. L3_MAIN Interconnect has sent SResp=ERR." "0,1" textline " " bitfld.long 0x0 10. " VID1BUFFER_UNDERFLOW_EN ,Video 1 DMA buffer underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)" "0,1" bitfld.long 0x0 11. " ENDVID1_WINDOW_EN ,The end of the video 1 window has been reached. It is detected by the overlay manager when the full video 1 has been displayed." "0,1" textline " " bitfld.long 0x0 12. " VID2BUFFER_UNDERFLOW_EN ,Video 2 DMA buffer underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)" "0,1" bitfld.long 0x0 13. " VID2END_WINDOW_EN ,The end of the video 2 Window has been reached. It is detected by the overlay manager when the full video 2 has been displayed." "0,1" textline " " bitfld.long 0x0 14. " SYNC_LOST1_EN ,Synchronization lost for the primary LCD" "0,1" bitfld.long 0x0 15. " SYNC_LOSTTV_EN ,Synchronization lost on the TV output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the TV output." "0,1" textline " " bitfld.long 0x0 16. " WAKEUP_EN ,Wake up mask" "0,1" bitfld.long 0x0 17. " SYNC_LOST2_EN ,Synchronization lost on the secondary LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the secondary LCD output." "0,1" textline " " bitfld.long 0x0 18. " VSYNC2_EN ,Vertical synchronization for the secondary LCD" "0,1" bitfld.long 0x0 19. " VID3END_WINDOW_EN ,The end of the video 3 window has been reached. It is detected by the overlay manager when the full video 3 has been displayed." "0,1" textline " " bitfld.long 0x0 20. " VID3BUFFER_UNDERFLOW_EN ,Video 3 DMA Buffer Underflow. The DMA buffer is not necessary empty but required data are not present in the DMA buffer (due to out of order responses)" "0,1" bitfld.long 0x0 21. " ACBIASCOUNT_STATUS2_EN ,AC Bias count status for the secondary LCD" "0,1" textline " " bitfld.long 0x0 22. " FRAME_DONE2_EN ,Frame done for the secondary LCD. The secondary LCD output has been disabled by user. All the data have been sent." "0,1" bitfld.long 0x0 23. " FRAME_DONEWB_EN ,Frame done for the write-back channel. The write-back channel has output the frame. All the data have been sent for the frame have been sent to the memory. There is no pending data inside the DMA engine for the write-back channel to be transferred to memory." "0,1" textline " " bitfld.long 0x0 24. " FRAME_DONETV_EN ,Frame done for the TV. The TV output has been disabled by user. All the data have been sent." "0,1" bitfld.long 0x0 25. " WBBUFFER_OVERFLOW_EN ,Write-back DMA buffer overflow. The DMA buffer is full." "0,1" textline " " bitfld.long 0x0 26. " WBUNCOMPLETE_ERROR_EN ,The write back buffer has been flushed before been fully drained. Enable." "0,1" bitfld.long 0x0 27. " SYNC_LOST3_EN ,Synchronization lost on the third LCD output. The required data are not output at the correct time due to too short blanking periods or stall of at least one pipelines associated with the third LCD output." "0,1" textline " " bitfld.long 0x0 28. " VSYNC3_EN ,Vertical synchronization for the third LCD" "0,1" bitfld.long 0x0 29. " ACBIASCOUNT_STATUS3_EN ,AC Bias count status for the third LCD" "0,1" textline " " bitfld.long 0x0 30. " FRAME_DONE3_EN ,Frame done for the third LCD. The third LCD output has been disabled by user. All the data have been sent." "0,1" bitfld.long 0x0 31. " FLIPIMMEDIATEDONE_EN ,Flip Immediate Done. The DMA engine has acknowledged the immediate BA change, and software can write the new BA0." "0,1" group.byte 0x40++0x3 line.long 0x0 "DISPC_CONTROL1,The control register configures the Display Controller module for the primary LCD and TV outputs." bitfld.long 0x0 0. " LCDENABLE ,Enable the primary LCD outputs wr: immediate Effect only occurs at the end of the current frame" "0,1" bitfld.long 0x0 1. " TVENABLE ,Enable the TV output wr: immediate effect only occurs at the end of the current frame." "0,1" textline " " bitfld.long 0x0 2. " MONOCOLOR ,Monochrome/color selection for the primary LCD WR: VFP start period of primary LCD output" "0,1" bitfld.long 0x0 3. " STNTFT ,LCD Display type of the primary LCD WR: VFP start period of primary LCD output" "0,1" textline " " bitfld.long 0x0 4. " M8B ,Mono 8-bit mode of the primary LCD wr: VFP start period of primary LCD output" "0,1" bitfld.long 0x0 5. " GOLCD ,GO command for the primary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the primary LCD output. WR: immediate" "0,1" textline " " bitfld.long 0x0 6. " GOTV ,GO command for the TV output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the TV output. WR: immediate" "0,1" bitfld.long 0x0 7. " STDITHERENABLE ,Spatial temporal dithering enable for the primary LCD output WR: VFP start period of primary LCD" "0,1" textline " " bitfld.long 0x0 8.--9. " TFTDATALINES ,Number of lines of the primary LCD interface WR: VFP start period of primary LCD" "0,1,2,3" bitfld.long 0x0 10. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 11. " STALLMODE ,STALL mode for the primary LCD output wr: VFP start period of primary LCD" "0,1" bitfld.long 0x0 12. " OVERLAYOPTI_MIZATION ,Overlay optimization for the primary LCD output WR: VFP start period of the primary LCD" "0,1" textline " " bitfld.long 0x0 13. " GPIN0 ,General purpose input signal WR: immediately" "0,1" bitfld.long 0x0 14. " GPIN1 ,General purpose input signal WR: immediately" "0,1" textline " " bitfld.long 0x0 15. " GPOUT0 ,General Purpose Output Signal WR:immediate" "0,1" bitfld.long 0x0 16. " GPOUT1 ,General purpose output signal l WR: immediate" "0,1" textline " " bitfld.long 0x0 17.--19. " HT ,Hold time for TV output WR: EVSYNC Encoded value (from 1 to 8) to specify the number of external digital clock periods to hold the data (programmed value = value minus 1)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. " TDMENABLE ,Enable the multiple cycle format for the primary LCD output. WR: VFP start period of primary LCD" "0,1" textline " " bitfld.long 0x0 21.--22. " TDMPARALLELMODE ,Output interface width (TDM mode only) for the primary LCD output WR: VFP start period of primary LCD" "0,1,2,3" bitfld.long 0x0 23.--24. " TDMCYCLEFORMAT ,Cycle format (TDM mode only) for the primary LCD output WR: VFP start period of primary LCD" "0,1,2,3" textline " " bitfld.long 0x0 25.--26. " TDMUNUSEDBITS ,State of unused bits (TDM mode only) for the primary LCD output. wr: VFP start period of primary LCD" "0,1,2,3" bitfld.long 0x0 27. " PCKFREEENABLE ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 28. " LCDENABLESIGNAL ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x0 29. " LCDENABLEPOL ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 30.--31. " SPATIALTEMPORAL_DITHERINGFRAMES ,Spatial/temporal dithering number of frames for the primary LCD output wr: VFP start period of primary LCD" "0,1,2,3" group.byte 0x44++0x3 line.long 0x0 "DISPC_CONFIG1,The control register configures the Display Controller module for the primary LCD output and TV output. Shadow register, updated on VFP start period of primary LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" bitfld.long 0x0 0. " PIXELGATED ,Pixel gated enable (only for TFT) (primary LCD output) wr: VFP start period of primary LCD output" "0,1" bitfld.long 0x0 1.--2. " LOADMODE ,Loading mode for the palette/gamma table wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" "0,1,2,3" textline " " bitfld.long 0x0 3. " PALETTEGAMMA_TABLE ,Palette/gamma table selection wr: VFP start period of primary LCD output or VFP start period of secondary LCD output or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the graphics pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory. In case of the table is used as gamma table, it is used for the primary LCD output only.NOTE: CLUT and BITMAP formats are not supported in this family of devices. ." "0,1" bitfld.long 0x0 4. " PIXELDATAGATED ,Pixel data gated enabled (primary LCD output) wr: VFP start period of primary LCD output" "0,1" textline " " bitfld.long 0x0 5. " PIXELCLOCK_GATED ,Pixel Clock Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output" "0,1" bitfld.long 0x0 6. " HSYNCGATED ,HSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output" "0,1" textline " " bitfld.long 0x0 7. " VSYNCGATED ,VSYNC Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output" "0,1" bitfld.long 0x0 8. " ACBIASGATED ,ACBias Gated Enabled (primary LCD output) wr: VFP start period of primary LCD output" "0,1" textline " " bitfld.long 0x0 9. " GAMATABLE_ENABLE ,For backward compatibility, an enable bit has been added on the 2 additional gamma tables (secondary display and TV). Gamma table of LCD1 is always enabled." "0,1" bitfld.long 0x0 10. " TCKLCDENABLE ,Transparency color key enabled (primary LCD output) wr: VFP start period of primary LCD output" "0,1" textline " " bitfld.long 0x0 11. " TCKLCD_SELECTION ,Transparency color key selection (primary LCD output) wr: VFP start period of primary LCD output" "0,1" bitfld.long 0x0 12. " TCKTVENABLE ,Transparency color key enabled (TV output) WR: EVSYNC" "0,1" textline " " bitfld.long 0x0 13. " TCKTV_SELECTION ,Transparency color key selection (TV output) wr: EVSYNC" "0,1" bitfld.long 0x0 14. " BUFFERMERGE ,Buffer merge control wr: EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory or VFP When enabled, the DISPC_GLOBAL_BUFFER register is ignored. This bit must be set to zero when the write back channel is used. When DISPC_CONTROL2.GOWB is used BUFFERMERGE MUST be zero. When DISPC_CONTROL2.GOWB is used BUFFERMERGE MUST be zero. WR: immediate" "0,1" textline " " bitfld.long 0x0 15. " CPR ,Color phase rotation control (primary LCD output). It shall be reset when ColorConvEnable bit field is set to 1 wr: VFP start period of primary LCD output" "0,1" bitfld.long 0x0 16. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 17. " BUFFERFILLING ,Controls if the DMA buffers are refilled only when the LOW threshold is reached or if all DMA buffers are refilled when at least one of them reaches the LOW threshold. wr: immediate" "0,1" bitfld.long 0x0 18. " LCDALPHABLENDER_ENABLE ,Selects the alpha blender overlay manager for the primary LCD output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility only. When it is enabled, the Z-order defined in each ATTRIBUTES registers for only the pipelines associated with the primary LCD output are invalid and replaced by the following: graphics z-order = 3, video3 z-order = 2, video2 z-order =1 and video1 z-order=0 If it disabled, the z-order and z-order enable bit fields defined in each ATTRIBUTES register are used. wr: VFP start of primary LCD" "0,1" textline " " bitfld.long 0x0 19. " TVALPHABLENDER_ENABLE ,Selects the alpha blender overlay manager for the TV output instead of the color key alpha blender (LCD output). The bit field is deprecated. It is present for software backward compatibility only. When it is enabled, the Z-order defined in each ATTRIBUTES registers for only the pipelines associated pipeline connected to the TV output are invalid and replaced by the following: graphics z-order = 3, video3 z-order = 2, video2 z-order =1 and video1 z-order=0 If it disabled, the z-order and z-order enable bit fields defined in each ATTRIBUTES register are used. wr: EVSYNC start of primary LCD" "0,1" bitfld.long 0x0 20. " BT656ENABLE ,Selects BT.656 format on the primary LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time one the same LCD output. wr: VFP start of primary LCD" "0,1" textline " " bitfld.long 0x0 21. " BT1120ENABLE ,Selects BT.1120 format on the primary LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time one the same LCD output. wr: VFP start of primary LCD" "0,1" bitfld.long 0x0 22. " OUTPUTMODE_ENABLE ,Selects between progressive and interlace mode for the primary LCD output. wr: VFP start of primary LCD" "0,1" textline " " bitfld.long 0x0 23. " FIDFIRST ,Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used. wr: VFP start of primary LCD" "0,1" bitfld.long 0x0 24. " COLORCONV_ENABLE ,Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1. wr: VFP start of primary LCD" "0,1" textline " " bitfld.long 0x0 25. " FULLRANGE ,Color Space Conversion full range setting. wr: VFP start of primary LCD" "0,1" bitfld.long 0x0 26.--27. " PLCDINTERLEAVE ,pLCD Interleave Pattern" "0,1,2,3" textline " " bitfld.long 0x0 28.--29. " TVINTERLEAVE ,TV Interleave Pattern" "0,1,2,3" bitfld.long 0x0 30.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" group.byte 0x4C++0x3 line.long 0x0 "DISPC_DEFAULT_COLOR0,The control register allows to configure the default solid background color for the primary LCD. Shadow register, updated on VFP start period of the primary LCD" hexmask.long.tbyte 0x0 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x50++0x3 line.long 0x0 "DISPC_DEFAULT_COLOR1,The control register allows to configure the default solid background color for the TV output. Shadow register, updated on EVSYNC" hexmask.long.tbyte 0x0 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x54++0x3 line.long 0x0 "DISPC_TRANS_COLOR0,The register sets the transparency color value for the video/graphics overlays for the primary LCD output. Shadow register, updated on VFP start period of the primary LCD" hexmask.long.tbyte 0x0 0.--23. 1. " TRANSCOLORKEY ,Transparency color key value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24NOTE: CLUT and BITMAP formats are not supported in this family of devices. ." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x58++0x3 line.long 0x0 "DISPC_TRANS_COLOR1,The register sets the transparency color value for the video/graphics overlays for the TV output. Shadow register, updated on EVSYNC" hexmask.long.tbyte 0x0 0.--23. 1. " TRANSCOLORKEY ,Transparency color key value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24NOTE: CLUT and BITMAP formats are not supported in this family of devices. ." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x5C++0x3 line.long 0x0 "DISPC_LINE_STATUS,The control register indicates the current primary LCD panel display line number." hexmask.long.word 0x0 0.--11. 1. " LINENUMBER ,Current LCD panel line number Current display line number. The first active line has the value 0. During blanking lines the line number is not incremented." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x60++0x3 line.long 0x0 "DISPC_LINE_NUMBER,The control register indicates the primary LCD panel display line number for the interrupt and the DMA request. Shadow register, updated on VFP start period of primary LCD." hexmask.long.word 0x0 0.--11. 1. " LINENUMBER ,LCD panel line number programming LCD line number defines the line on which the programmable interrupt is generated and the DMA request occurs." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x64++0x3 line.long 0x0 "DISPC_TIMING_H1,The register configures the timing logic for the HSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.byte 0x0 0.--7. 1. " HSW ,Horizontal synchronization pulse width. Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1). When in BT mode, this field corresponds to the horizontal blanking" hexmask.long.word 0x0 8.--19. 1. " HFP ,Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1). When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Even Field." textline " " hexmask.long.word 0x0 20.--31. 1. " HBP ,Horizontal Back Porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1). When in BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Even Field." group.byte 0x68++0x3 line.long 0x0 "DISPC_TIMING_V1,The register configures the timing logic for the VSYNC signal. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.byte 0x0 0.--7. 1. " VSW ,Vertical synchronization pulse width. In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode." hexmask.long.word 0x0 8.--19. 1. " VFP ,Vertical front porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame." textline " " hexmask.long.word 0x0 20.--31. 1. " VBP ,Vertical back porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame." group.byte 0x6C++0x3 line.long 0x0 "DISPC_POL_FREQ1,The register configures the signal configuration. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD." hexmask.long.byte 0x0 0.--7. 1. " ACB ,AC Bias pin frequency value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display." bitfld.long 0x0 8.--11. " ACBI ,AC Bias pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12. " IVS ,Invert VSYNC" "0,1" bitfld.long 0x0 13. " IHS ,Invert HSYNC" "0,1" textline " " bitfld.long 0x0 14. " IPC ,Invert pixel clockNote: Control module register CTRL_CORE_SMA_SW_1[19]DSS_CH0_IPC must be set to match enum=DfPCk ." "0,1" bitfld.long 0x0 15. " IEO ,Invert output enable" "0,1" textline " " bitfld.long 0x0 16. " RF ,Program HSYNC/VSYNC Rise or FallNote: Control module register CTRL_CORE_SMA_SW_1[16]DSS_CH0_RF must be set to match enum=DRiEdPCk ." "0,1" bitfld.long 0x0 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/OffNote: Control module register CTRL_CORE_SMA_SW_1[22]DSS_CH0_ON_OFF must be set to match enum=DBit16 ." "0,1" textline " " bitfld.long 0x0 18. " ALIGN ,Defines the alignment between HSYNC and VSYNC assertion." "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x70++0x3 line.long 0x0 "DISPC_DIVISOR1,The register configures the divisors. It is used for the primary LCD output Shadow register, updated on VFP start period of primary LCD" hexmask.long.byte 0x0 0.--7. 1. " PCD ,Pixel clock divisor value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD1_CLK divided byDISPC_DIVISOR1.LCD value. The values 0 is invalid." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." textline " " hexmask.long.byte 0x0 16.--23. 1. " LCD ,Display controller logic clock divisor value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD1_CLK. The value 0 is invalid." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x74++0x3 line.long 0x0 "DISPC_GLOBAL_ALPHA,The register defines the global alpha value for the graphics and three video pipelines. Shadow register, updated on VFP start period of primary LCD or VFP start period of the third LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory for each bit field depending on the association of the each pipeline with the primary LCD, secondary LCD or TV output." hexmask.long.byte 0x0 0.--7. 1. " GFXGLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." hexmask.long.byte 0x0 8.--15. 1. " VID1GLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." textline " " hexmask.long.byte 0x0 16.--23. 1. " VID2GLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." hexmask.long.byte 0x0 24.--31. 1. " VID3GLOBALALPHA ,Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque." group.byte 0x78++0x3 line.long 0x0 "DISPC_SIZE_TV,The register configures the size of the TV output field (interlace), frame (progressive) (horizontal and vertical). Shadow register, updated on EVSYNC. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.word 0x0 0.--11. 1. " PPL ,Pixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display." bitfld.long 0x0 12.--13. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 14.--15. " DELTA_LPP ,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. " LPP ,Lines per panel encoded value (from 1 to 4096) to specify the number of lines per panel." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x7C++0x3 line.long 0x0 "DISPC_SIZE_LCD1,The register configures the panel size (horizontal and vertical). Shadow register, updated on VFP start period of primary LCD. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.word 0x0 0.--11. 1. " PPL ,Pixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only values multiple of 8 pixels are valid." bitfld.long 0x0 12.--13. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 14.--15. " DELTA_LPP ,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. " LPP ,Lines per panel encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1)." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x80++0x3 line.long 0x0 "DISPC_GFX_BA_j_0,The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output and 0 and 1 when on the TV output). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Graphics base address Base address of the graphics buffer (aligned on pixel size boundary) (in case 1-, 2-, and 4-bpp, byte alignment is required, in case of RGB24 packed format, 4-pixel alignment is required) When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x84++0x3 line.long 0x0 "DISPC_GFX_BA_j_1,The register configures the base address of the graphics buffer displayed in the graphics window (0 and 1 :for ping-pong mechanism with external trigger, based on the field polarity, 0 only used when graphics pipeline on the LCD output and 0 and 1 when on the TV output). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Graphics base address Base address of the graphics buffer (aligned on pixel size boundary) (in case 1-, 2-, and 4-bpp, byte alignment is required, in case of RGB24 packed format, 4-pixel alignment is required) When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x88++0x3 line.long 0x0 "DISPC_GFX_POSITION,The register configures the position of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " POSX ,X position of the graphics window. Encoded value (from 0 to 2047) to specify the X position of the graphics window on the screen. The first pixel on the left of the screen has the X-position 0." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " POSY ,Y position of the graphics window. Encoded value (from 0 to 2047) to specify the Y position of the graphics window on the screen. The line at the top has the Y-position 0." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x8C++0x3 line.long 0x0 "DISPC_GFX_SIZE,The register configures the size of the graphics window. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " SIZEX ,Number of pixels of the graphics window. Encoded value (from 1 to 2048) to specify the number of pixels per line of the graphics window (program to value minus 1)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " SIZEY ,Number of lines of the graphics window. Encoded value (from 1 to 4096) to specify the number of lines of the graphics window (program to value minus 1)." bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xA0++0x3 line.long 0x0 "DISPC_GFX_ATTRIBUTES,The register configures the graphics attributes. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" bitfld.long 0x0 0. " ENABLE ,Graphics enable" "0,1" bitfld.long 0x0 1.--4. " FORMAT ,Graphics format. It defines the pixel format when fetching the graphics picture into memory." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5. " REPLICATIONENABLE ,Graphics replication enabled: RGB . ARGB, and RGBA formats are converted into ARGB32-8888 using replication of the MSBs or 0s" "0,1" bitfld.long 0x0 6.--7. " BURSTSIZE ,Graphics DMA burst size" "0,1,2,3" textline " " bitfld.long 0x0 8. " CHANNELOUT ,Graphics Channel Out configuration: LCD, WB or TV. wr: immediate" "0,1" bitfld.long 0x0 9. " NIBBLEMODE ,Graphics nibble mode (only for 1-, 2- and 4 bpp)NOTE: BITMAP formats and associated Nibble Mode are not supported in this family of devices. ." "0,1" textline " " bitfld.long 0x0 10. " FRAMEPACKINGMODE ,Frame packing mode control." "0,1" bitfld.long 0x0 11. " BUFPRELOAD ,Graphics preload value" "0,1" textline " " bitfld.long 0x0 12.--13. " ROTATION ,Graphics rotation flag" "0,1,2,3" bitfld.long 0x0 14. " ARBITRATION ,Determines the priority of the graphics pipeline. When the graphics pipeline is one of the high priority pipelines. The arbitration wheel gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them." "0,1" textline " " bitfld.long 0x0 15. " SELFREFRESH ,Enables the self refresh of the graphics window from its own DMA buffer. This bit should be set only after having set the GO bit of the channel and read back a zero in its field." "0,1" bitfld.long 0x0 16. " FORCE1DTILEDMODE ,Force TILED regions access to 1D or 2D." "0,1" textline " " bitfld.long 0x0 17. " SELFREFRESHAUTO ,Automatic self-refresh mode" "0,1" bitfld.long 0x0 18.--20. " SUBSAMPLINGPATTERN ,Subsampling pattern setting." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. " ANTIFLICKER ,Antiflicker filtering using a 3-tap filter with hardcoded coefficients (1/4, 1/2, 1/4)" "0,1" textline " " bitfld.long 0x0 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled." "0,1" bitfld.long 0x0 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0." "0,1,2,3" textline " " bitfld.long 0x0 28. " PREMULTIPLYALPHA ,The field configures the DISPC GFX to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data." "0,1" bitfld.long 0x0 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine. (It does not apply to the palette loading OCP requests using INCR burst only)" "0,1" textline " " bitfld.long 0x0 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should set to zero) wr: immediate" "0,1,2,3" group.byte 0xA4++0x3 line.long 0x0 "DISPC_GFX_BUF_THRESHOLD,The register configures the graphics buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer low threshold number of 128 bits defining the threshold value. The value put in this register must always be greater than zero." hexmask.long.word 0x0 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer high threshold number of 128 bits defining the threshold value" group.byte 0xA8++0x3 line.long 0x0 "DISPC_GFX_BUF_SIZE_STATUS,The register defines the Graphics buffer size" hexmask.long.word 0x0 0.--15. 1. " BUFSIZE ,DMA buffer size in number of 128 bits" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0xAC++0x3 line.long 0x0 "DISPC_GFX_ROW_INC,The register configures the number of bytes to increment at the end of the row. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded unsigned value to specify the number of bytes to increment at the end of the row in the graphics buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels. The value 1- (n+1)*bpp means decrement of n pixels." group.byte 0xB0++0x3 line.long 0x0 "DISPC_GFX_PIXEL_INC,The register configures the number of bytes to increment between two pixels. For more information, see, Predecimation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the graphics buffer. The value 0 is invalid. The value 1 means next pixel. The value 1+n*bpp means increment of n pixels." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0xB8++0x3 line.long 0x0 "DISPC_GFX_TABLE_BA,The register configures the base address of the palette buffer or the gamma table buffer. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory. NOTE: CLUT and BITMAP formats, and associated palette buffer, are not supported in this family of devices." hexmask.long 0x0 0.--31. 1. " TABLEBA ,Base address of the palette/gamma table buffer (24-bit entries in 32-bit containers, aligned on 32-bit boundary).NOTE: CLUT and BITMAP formats, and associated palette buffer, are not supported in this family of devices. ." group.byte 0xBC++0x3 line.long 0x0 "DISPC_VID1_BA_j_0,The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is supported)). It case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0xC0++0x3 line.long 0x0 "DISPC_VID1_BA_j_1,The register configures the base address of the video buffer for the video window 1 (DISPC_VID1_BA_0 and DISPC_VID1_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_0 is used). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is supported)). It case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0xC4++0x3 line.long 0x0 "DISPC_VID1_POSITION,The register configures the position of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " POSX ,X position of the video window 1 Encoded value (from 0 to 2047) to specify the X position of the video window 1. The first pixel on the left of the display screen has the X-position 0." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " POSY ,Y position of the video window 1 Encoded value (from 0 to 2047) to specify the Y position of the video window 1 .The line at the top has the Y-position 0." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xC8++0x3 line.long 0x0 "DISPC_VID1_SIZE,The register configures the size of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD, orEVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " SIZEX ,Number of pixels of the video window 1 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 1. Program to value minus 1." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " SIZEY ,Number of lines of the video 1 Encoded value (from 1 to 4096) to specify the number of lines of the video window 1. Program to value minus 1." bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xCC++0x3 line.long 0x0 "DISPC_VID1_ATTRIBUTES,The register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" bitfld.long 0x0 0. " ENABLE ,Video Enable" "0,1" bitfld.long 0x0 1.--4. " FORMAT ,Video Format. It defines the pixel format when fetching the video 1 picture into memory." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5.--6. " RESIZEENABLE ,Video Resize Enable" "0,1,2,3" bitfld.long 0x0 7. " HRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 8. " FRAMEPACKINGMODE ,Frame packing mode control." "0,1" bitfld.long 0x0 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV." "0,1" textline " " bitfld.long 0x0 10. " REPLICATIONENABLE ,Replication enable" "0,1" bitfld.long 0x0 11. " FULLRANGE ,Color space conversion full range setting." "0,1" textline " " bitfld.long 0x0 12.--13. " ROTATION ,Video rotation flag" "0,1,2,3" bitfld.long 0x0 14.--15. " BURSTSIZE ,Video DMA burst size" "0,1,2,3" textline " " bitfld.long 0x0 16. " CHANNELOUT ,Video channel out configuration: LCD, WB or TV. wr: immediate" "0,1" bitfld.long 0x0 17. " SELFREFRESHAUTO ,Automatic self-refresh mode" "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x0 19. " BUFPRELOAD ,Video Preload Value" "0,1" textline " " bitfld.long 0x0 20. " FORCE1DTILEDMODE ,Force TILED regions access to 1D or 2D." "0,1" bitfld.long 0x0 21. " VERTICALTAPS ,Video vertical resize tap number. The vertical polyphase filter can be configured in 3-tap or 5-tap configuration. According to the number of taps, the maximum input picture width is double while using 3-tap compared to 5-tap." "0,1" textline " " bitfld.long 0x0 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0." "0,1" bitfld.long 0x0 23. " ARBITRATION ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them." "0,1" textline " " bitfld.long 0x0 24. " SELFREFRESH ,Enables the self refresh of the video window from its own DMA buffer only." "0,1" bitfld.long 0x0 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled." "0,1" textline " " bitfld.long 0x0 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0." "0,1,2,3" bitfld.long 0x0 28. " PREMULTIPHYALPHA ,The field configures the DISPC VID1 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data." "0,1" textline " " bitfld.long 0x0 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine." "0,1" bitfld.long 0x0 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero) wr: immediate" "0,1,2,3" group.byte 0xD0++0x3 line.long 0x0 "DISPC_VID1_BUF_THRESHOLD,The register configures the video buffer associated with the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer low threshold number of 128 bits defining the threshold value" hexmask.long.word 0x0 16.--31. 1. " BUFHIGHTHRESHOLD ,Video DMA buffer high threshold number of 128 bits defining the threshold value" group.byte 0xD4++0x3 line.long 0x0 "DISPC_VID1_BUF_SIZE_STATUS,The register defines the Video buffer size for the video pipeline 1." hexmask.long.word 0x0 0.--15. 1. " BUFSIZE ,Video 1 DMA buffer size in number of 128-bits" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0xD8++0x3 line.long 0x0 "DISPC_VID1_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels. The value 1 (n + 1)* bpp means decrement of n pixels." group.byte 0xDC++0x3 line.long 0x0 "DISPC_VID1_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see, Predecimation.The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD orEVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels. For YUV4:2:0, maximum supported value is 128." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0xE0++0x3 line.long 0x0 "DISPC_VID1_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" group.byte 0xE4++0x3 line.long 0x0 "DISPC_VID1_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 1 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD, EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " MEMSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded to 2." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " MEMSIZEY ,Number of lines of the video picture. Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded to 2." bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xE8++0x3 line.long 0x0 "DISPC_VID1_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accumulator value encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accumulator value encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xEC++0x3 line.long 0x0 "DISPC_VID1_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU_0 and DISPC_VID1_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accumulator value encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accumulator value encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xF0++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VPF start pertiod of the third LCD, EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0xF8++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VPF start pertiod of the third LCD, EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x100++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VPF start pertiod of the third LCD, EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x108++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VPF start pertiod of the third LCD, EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x110++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VPF start pertiod of the third LCD, EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x118++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VPF start pertiod of the third LCD, EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x120++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VPF start pertiod of the third LCD, EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x128++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VPF start pertiod of the third LCD, EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0xF4++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0xFC++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x104++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x10C++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x114++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x11C++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x124++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x12C++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x130++0x3 line.long 0x0 "DISPC_VID1_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " RY ,RY coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " RCR ,RCr coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x134++0x3 line.long 0x0 "DISPC_VID1_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " RCB ,RCb coefficient encoded signed value (from -1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " GY ,GY coefficient encoded signed value (from -1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x138++0x3 line.long 0x0 "DISPC_VID1_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " GCR ,GCr coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " GCB ,GCb coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x13C++0x3 line.long 0x0 "DISPC_VID1_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " BY ,BY coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " BCR ,BCr coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x140++0x3 line.long 0x0 "DISPC_VID1_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " BCB ,BCb coefficient encoded signed value (from 1024 to 1023)." hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x14C++0x3 line.long 0x0 "DISPC_VID2_BA_j_0,The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is supported)). In case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x150++0x3 line.long 0x0 "DISPC_VID2_BA_j_1,The register configures the base address of the video buffer for the video window 2 (DISPC_VID2_BA_0 and DISPC_VID2_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is supported)). In case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x154++0x3 line.long 0x0 "DISPC_VID2_POSITION,The register configures the position of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " POSX ,X position of the video window 2 encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " POSY ,Y position of the video window 2 encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x158++0x3 line.long 0x0 "DISPC_VID2_SIZE,The register configures the size of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " SIZEX ,Number of pixels of the video window 2 encoded value (from 1 to 2048) to specify the number of pixels of the video window 2. Program to value minus 1." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " SIZEY ,Number of lines of the video 2 encoded value (from 1 to 4096) to specify the number of lines of the video window 2. Program to value minus 1." bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x15C++0x3 line.long 0x0 "DISPC_VID2_ATTRIBUTES,The register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" bitfld.long 0x0 0. " ENABLE ,VidEnable" "0,1" bitfld.long 0x0 1.--4. " FORMAT ,Video Format. It defines the pixel format when fetching the video 2 picture into memory." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5.--6. " RESIZEENABLE ,Video Resize Enable" "0,1,2,3" bitfld.long 0x0 7. " HRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 8. " FRAMEPACKINGMODE ,Frame packing mode control." "0,1" bitfld.long 0x0 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV." "0,1" textline " " bitfld.long 0x0 10. " REPLICATIONENABLE ,Replication Enable" "0,1" bitfld.long 0x0 11. " FULLRANGE ,Color space conversion full range setting." "0,1" textline " " bitfld.long 0x0 12.--13. " ROTATION ,Video Rotation Flag" "0,1,2,3" bitfld.long 0x0 14.--15. " BURSTSIZE ,Video DMA burst size" "0,1,2,3" textline " " bitfld.long 0x0 16. " CHANNELOUT ,Video Channel Out configuration: LCD, WB or TV. wr: immediate" "0,1" bitfld.long 0x0 17. " SELFREFRESHAUTO ,Automatic self-refresh mode" "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x0 19. " BUFPRELOAD ,Video Preload Value" "0,1" textline " " bitfld.long 0x0 20. " FORCE1DTILEDMODE ,Force TILED regions access to 1D or 2D." "0,1" bitfld.long 0x0 21. " VERTICALTAPS ,Video Vertical Resize Tap Number" "0,1" textline " " bitfld.long 0x0 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0." "0,1" bitfld.long 0x0 23. " ARBITRATION ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them." "0,1" textline " " bitfld.long 0x0 24. " SELFREFRESH ,Enables the self refresh of the video window from its own DMA buffer only." "0,1" bitfld.long 0x0 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is only used when the Z-order is enabled." "0,1" textline " " bitfld.long 0x0 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0." "0,1,2,3" bitfld.long 0x0 28. " PREMULTIPLYALPHA ,The field configures the DISPC VID2 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data." "0,1" textline " " bitfld.long 0x0 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine." "0,1" bitfld.long 0x0 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (must be set to zero) wr: immediate" "0,1,2,3" group.byte 0x160++0x3 line.long 0x0 "DISPC_VID2_BUF_THRESHOLD,The register configures the DMA buffer associated with the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer low threshold number of 128 bits defining the threshold value" hexmask.long.word 0x0 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer high threshold number of 128 bits defining the threshold value" group.byte 0x164++0x3 line.long 0x0 "DISPC_VID2_BUF_SIZE_STATUS,The register defines the DMA buffer size for the video pipeline 2." hexmask.long.word 0x0 0.--15. 1. " BUFSIZE ,DMA buffer size in number of 128 bits" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x168++0x3 line.long 0x0 "DISPC_VID2_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels. The value 1 (n + 1) * bpp means decrement of n pixels." group.byte 0x16C++0x3 line.long 0x0 "DISPC_VID2_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 2. For more information, see, Predecimation.The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between2 pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels. For YUV4:2:0, maximum supported value is 128." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x170++0x3 line.long 0x0 "DISPC_VID2_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" group.byte 0x174++0x3 line.long 0x0 "DISPC_VID2_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 2 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " MEMSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " MEMSIZEY ,Number of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the maximum size of the unpredecimated image size in memory is still bounded 2." bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x178++0x3 line.long 0x0 "DISPC_VID2_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accumulator value encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accumulator value encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x17C++0x3 line.long 0x0 "DISPC_VID2_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU_0 and DISPC_VID2_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accumulator value encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accumulator value encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x180++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x188++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x190++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x198++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x1A0++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x1A8++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x1B0++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x1B8++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x184++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x18C++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x194++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x19C++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x1A4++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x1AC++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x1B4++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x1BC++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x1C0++0x3 line.long 0x0 "DISPC_VID2_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " RY ,RY coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " RCR ,RCr coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x1C4++0x3 line.long 0x0 "DISPC_VID2_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " RCB ,RCb coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " GY ,GY coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x1C8++0x3 line.long 0x0 "DISPC_VID2_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " GCR ,GCr coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " GCB ,GCb coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x1CC++0x3 line.long 0x0 "DISPC_VID2_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " BY ,BY coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " BCR ,BCr coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x1D0++0x3 line.long 0x0 "DISPC_VID2_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " BCB ,BCb coefficient encoded signed value (from 1024 to 1023)." hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x1D4++0x3 line.long 0x0 "DISPC_DATA1_CYCLE1,The control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of primary LCD" bitfld.long 0x0 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1D8++0x3 line.long 0x0 "DISPC_DATA1_CYCLE2,The control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of primary LCD" bitfld.long 0x0 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1DC++0x3 line.long 0x0 "DISPC_DATA1_CYCLE3,The control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of primary LCD" bitfld.long 0x0 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1E0++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x1E4++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x1E8++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x1EC++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x1F0++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x1F4++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x1F8++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x1FC++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x200++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x204++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x208++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x20C++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x210++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x214++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x218++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x21C++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x220++0x3 line.long 0x0 "DISPC_CPR1_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x0 0.--9. 1. " RB ,RB coefficient encoded signed value (from 512 to 511)" bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 11.--20. 1. " RG ,RG coefficient encoded signed value (from 512 to 511)" bitfld.long 0x0 21. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RR ,RR coefficient encoded signed value (from 512 to 511)" group.byte 0x224++0x3 line.long 0x0 "DISPC_CPR1_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x0 0.--9. 1. " GB ,GB coefficient encoded signed value (from 512 to 511)" bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 11.--20. 1. " GG ,GG coefficient encoded signed value (from 512 to 511)" bitfld.long 0x0 21. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " GR ,GR coefficient encoded signed value (from 512 to 511)" group.byte 0x228++0x3 line.long 0x0 "DISPC_CPR1_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component. It is used for the primary LCD output. Shadow register, updated on VFP start period of primary LCD" hexmask.long.word 0x0 0.--9. 1. " BB ,BB coefficient encoded signed value (from 512 to 511)" bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 11.--20. 1. " BG ,BG coefficient encoded signed value (from 512 to 511" bitfld.long 0x0 21. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " BR ,BR coefficient encoded signed value (from 512 to 511)" group.byte 0x22C++0x3 line.long 0x0 "DISPC_GFX_PRELOAD,The register configures the graphics DMA buffer Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--11. 1. " PRELOAD ,DMA buffer preload value number of 128-bit words defining the preload value." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x230++0x3 line.long 0x0 "DISPC_VID1_PRELOAD,The register configures the DMA buffer of the video 1 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--11. 1. " PRELOAD ,DMA buffer preload value number of 128-bit words defining the preload value." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x234++0x3 line.long 0x0 "DISPC_VID2_PRELOAD,The register configures the DMA buffer of the video 2 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--11. 1. " PRELOAD ,DMA buffer preload value Number of 128-bit words defining the preload value." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x238++0x3 line.long 0x0 "DISPC_CONTROL2,The control register configures the Display Controller module for the secondary LCD output. Shadow registers are updated during the VFP start period of the secondary LCD, EVSYNC, or when.GOWB is set to 1 by software and the current WB frame is complete (that is, has no more data in the write-back pipeline)." bitfld.long 0x0 0. " LCDENABLE ,Enable the secondary LCD output wr:immediate" "0,1" bitfld.long 0x0 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 2. " MONOCOLOR ,Monochrome/Color selection for the secondary LCD wr: VFP start period of secondary LCD output" "0,1" bitfld.long 0x0 3. " STNTFT ,LCD Display type of the secondary LCD wr: VFP start period of secondary LCD output" "0,1" textline " " bitfld.long 0x0 4. " M8B ,Mono 8-bit mode of the secondary LCD wr: VFP start period of secondary LCD output" "0,1" bitfld.long 0x0 5. " GOLCD ,GO command for the secondary LCD output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the secondary LCD output. wr:immediate" "0,1" textline " " bitfld.long 0x0 6. " GOWB ,GO command for the write-back output. It is used to synchronized the pipelines (graphics and/or video ones) associated with the write-back output to the memory. wr:immediate" "0,1" bitfld.long 0x0 7. " STDITHER_ENABLE ,Spatial temporal dithering enable for the secondary LCD output wr: VFP start period of secondary LCD output" "0,1" textline " " bitfld.long 0x0 8.--9. " TFTDATALINES ,Number of lines of the secondary LCD interface wr: VFP start period of secondary LCD output" "0,1,2,3" bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 11. " STALLMODE ,STALL mode for the secondary LCD output wr: VFP start period of secondary LCD output" "0,1" bitfld.long 0x0 12. " OVERLAY_OPTIMIZATION ,Overlay optimization for the secondary LCD output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" "0,1" textline " " bitfld.long 0x0 13. " TVOVERLAY_OPTIMIZATION ,Overlay optimization for the TV output wr: VFP or EVSYNC or whenDISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" "0,1" bitfld.long 0x0 14.--19. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 20. " TDMENABLE ,Enable the multiple cycle format for the secondary LCD output wr: VFP start period of secondary LCD output" "0,1" bitfld.long 0x0 21.--22. " TDMPARALLEL_MODE ,Output Interface width (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output" "0,1,2,3" textline " " bitfld.long 0x0 23.--24. " TDMCYCLE_FORMAT ,Cycle format (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output" "0,1,2,3" bitfld.long 0x0 25.--26. " TDMUNUSED_BITS ,State of unused bits (TDM mode only) for the secondary LCD output wr: VFP start period of secondary LCD output" "0,1,2,3" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SPATIALTEMPORAL_DITHERINGFRAMES ,Spatial/temporal dithering number of frames for the secondary LCD output wr: VFP start period of secondary LCD output" "0,1,2,3" group.byte 0x240++0x3 line.long 0x0 "DISPC_GFX_POSITION2,The register configures the position of the 2nd graphics window in FramePacking mode. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when [6] GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory." hexmask.long.word 0x0 0.--10. 1. " POSX ,X position of the 2nd graphics window. Encoded value (from 0 to 2047) to specify the X position of the graphics window on the screen. The first pixel on the left of the screen has the X-position 0." bitfld.long 0x0 11.--15. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " POSY ,Y position of the 2nd graphics window. Encoded value (from 0 to 2047) to specify the Y position of the graphics window on the screen. The line at the top has the Y-position 0." bitfld.long 0x0 27.--31. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x244++0x3 line.long 0x0 "DISPC_VID1_POSITION2,The register configures the position of the 2nd video window #1 in FramePacking mode. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when [6] GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory." hexmask.long.word 0x0 0.--10. 1. " POSX ,X position of the 2nd video window #1 Encoded value (from 0 to 2047) to specify the X position of the video window #1. The first pixel on the left of the display screen has the X-position 0." bitfld.long 0x0 11.--15. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " POSY ,Y position of the 2nd video window #1 Encoded value (from 0 to 2047) to specify the Y position of the video window #1 .The line at the top has the Y-position 0." bitfld.long 0x0 27.--31. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x248++0x3 line.long 0x0 "DISPC_VID2_POSITION2,The register configures the position of the 2nd video window #2 in FramePacking mode. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when [6] GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory." hexmask.long.word 0x0 0.--10. 1. " POSX ,X position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the X position of the video window #2. The first pixel on the left of the display screen has the X-position 0." bitfld.long 0x0 11.--15. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " POSY ,Y position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the Y position of the video window #2 .The line at the top has the Y-position 0." bitfld.long 0x0 27.--31. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x24C++0x3 line.long 0x0 "DISPC_VID3_POSITION2,The register configures the position of the 2nd video window #3 in FramePacking mode. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when [6] GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory." hexmask.long.word 0x0 0.--10. 1. " POSX ,X position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the X position of the video window #2. The first pixel on the left of the display screen has the X-position 0." bitfld.long 0x0 11.--15. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " POSY ,Y position of the 2nd video window #2 Encoded value (from 0 to 2047) to specify the Y position of the video window #2 .The line at the top has the Y-position 0." bitfld.long 0x0 27.--31. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x300++0x3 line.long 0x0 "DISPC_VID3_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x304++0x3 line.long 0x0 "DISPC_VID3_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU_0 and DISPC_VID3_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x308++0x3 line.long 0x0 "DISPC_VID3_BA_j_0,The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is supported)). It case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x30C++0x3 line.long 0x0 "DISPC_VID3_BA_j_1,The register configures the base address of the video buffer for the video window 3 (DISPC_VID3_BA_0 and DISPC_VID3_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address Base address of the video buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2:0, byte alignment is supported)). It case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x310++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x318++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x320++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x328++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x330++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x338++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x340++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x348++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x314++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x31C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x324++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x32C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x334++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x33C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x344++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x34C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x350++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x354++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x358++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x35C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x360++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x364++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x368++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x36C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x370++0x3 line.long 0x0 "DISPC_VID3_ATTRIBUTES,The register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" bitfld.long 0x0 0. " ENABLE ,Video Enable" "0,1" bitfld.long 0x0 1.--4. " FORMAT ,Video format. It defines the pixel format when fetching the video 3 picture into memory." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5.--6. " RESIZEENABLE ,Video resize enable" "0,1,2,3" bitfld.long 0x0 7. " HRESIZECONF ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 8. " FRAMEPACKINGMODE ,Frame packing mode control." "0,1" bitfld.long 0x0 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV." "0,1" textline " " bitfld.long 0x0 10. " REPLICATIONENABLE ,Replication enable" "0,1" bitfld.long 0x0 11. " FULLRANGE ,Color Space Conversion full range setting." "0,1" textline " " bitfld.long 0x0 12.--13. " ROTATION ,Video rotation flag" "0,1,2,3" bitfld.long 0x0 14.--15. " BURSTSIZE ,Video DMA burst size" "0,1,2,3" textline " " bitfld.long 0x0 16. " CHANNELOUT ,Video channel out configuration: LCD, WB or TV. wr: immediate" "0,1" bitfld.long 0x0 17. " SELFREFRESHAUTO ,Automatic self-refresh mode" "0,1" textline " " bitfld.long 0x0 18. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x0 19. " BUFPRELOAD ,Video Preload Value" "0,1" textline " " bitfld.long 0x0 20. " FORCE1DTILEDMODE ,Force TILED regions access to 1D or 2D." "0,1" bitfld.long 0x0 21. " VERTICALTAPS ,Video vertical resize tap number" "0,1" textline " " bitfld.long 0x0 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0." "0,1" bitfld.long 0x0 23. " ARBITRATION ,Determines the priority of the video pipeline. The video pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them." "0,1" textline " " bitfld.long 0x0 24. " SELFREFRESH ,Enables the self refresh of the video window from its own DMA buffer only." "0,1" bitfld.long 0x0 25. " ZORDERENABLE ,Z-order Enable. The bit field ZORDER is used only when the Z-order is enabled." "0,1" textline " " bitfld.long 0x0 26.--27. " ZORDER ,Z-Order defining the priority of the layer compared to others when overlaying. It is software responsibility to ensure that each layer connected to the same overlay manager has a different z-order value. If bit 25 is set to 0, the ZORDER bit field is ignored and replaced by the value 0." "0,1,2,3" bitfld.long 0x0 28. " PREMULTIPLYALPHA ,The field configures the DISPC VID3 to process incoming data as premultiplied alpha data or non premultiplied alpha data. Default setting is non premultiplied alpha data." "0,1" textline " " bitfld.long 0x0 29. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine." "0,1" bitfld.long 0x0 30.--31. " CHANNELOUT2 ,It is not used if CHANNELOUT is set to TV. Reserved when CHANNELOUT = 1 (should be set to zero) wr: immediate" "0,1,2,3" group.byte 0x374++0x3 line.long 0x0 "DISPC_VID3_CONV_COEF0,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " RY ,RY coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " RCR ,RCr coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x378++0x3 line.long 0x0 "DISPC_VID3_CONV_COEF1,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " RCB ,RCb coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " GY ,GY coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x37C++0x3 line.long 0x0 "DISPC_VID3_CONV_COEF2,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " GCR ,GCr coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " GCB ,GCb coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x380++0x3 line.long 0x0 "DISPC_VID3_CONV_COEF3,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " BY ,BY coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " BCR ,BCr coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x384++0x3 line.long 0x0 "DISPC_VID3_CONV_COEF4,The register configures the color space conversion matrix coefficients for the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " BCB ,BCb coefficient encoded signed value (from 1024 to 1023)." hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x388++0x3 line.long 0x0 "DISPC_VID3_BUF_SIZE_STATUS,The register defines the DMA buffer size for the video pipeline 3." hexmask.long.word 0x0 0.--15. 1. " BUFSIZE ,DMA buffer Size in number of 128 bits." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x38C++0x3 line.long 0x0 "DISPC_VID3_BUF_THRESHOLD,The register configures the DMA buffer associated with the video pipeline 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer low threshold number of 128 bits defining the threshold value" hexmask.long.word 0x0 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer high threshold number of 128 bits defining the threshold value" group.byte 0x390++0x3 line.long 0x0 "DISPC_VID3_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for ARGB and Y setting. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" group.byte 0x394++0x3 line.long 0x0 "DISPC_VID3_PICTURE_SIZE,The register configures the size of the video picture associated with the video layer 3 before up/down-scaling. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " MEMSIZEX ,Number of pixels of the video picture Encoded value (from 1 to 2048) to specify the number of pixels of the video picture in memory (program to value minus 1). The size is limited to the size of the line buffer of the vertical sampling block in case the video picture is processed by the vertical filtering unit. (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " MEMSIZEY ,Number of lines of the video picture Encoded value (from 1 to 4096) to specify the number of lines of the video picture in memory (program to value minus 1). When predecimation is set, the value represents the size of the image after predecimation but the max size of the unpredecimated image size in memory is still bounded 2." bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x398++0x3 line.long 0x0 "DISPC_VID3_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the video window 3. For more information, see, Predecimation.The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " PIXELINC ,Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels. For YUV4:2:0, maximum supported value is 128." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x39C++0x3 line.long 0x0 "DISPC_VID3_POSITION,The register configures the position of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " POSX ,X position of the video window 2 Encoded value (from 0 to 2047) to specify the X position of the video window 2. The first pixel on the left of the display screen has the X-position 0." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " POSY ,Y position of the video window 2 Encoded value (from 0 to 2047) to specify the Y position of the video window 2 .The line at the top has the Y-position 0." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x3A0++0x3 line.long 0x0 "DISPC_VID3_PRELOAD,The register configures the DMA buffer of the video 3 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--11. 1. " PRELOAD ,DMA buffer preload value Number of 128-bit words defining the preload value." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x3A4++0x3 line.long 0x0 "DISPC_VID3_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n * bpp means increment of n pixels. The value 1 (n + 1) * bpp means decrement of n pixels." group.byte 0x3A8++0x3 line.long 0x0 "DISPC_VID3_SIZE,The register configures the size of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " SIZEX ,Number of pixels of the video window 3 Encoded value (from 1 to 2048) to specify the number of pixels of the video window 3. Program to value minus 1." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " SIZEY ,Number of lines of the video 3 Encoded value (from 1 to 4096) to specify the number of lines of the video window 3. Program to value minus 1." bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3AC++0x3 line.long 0x0 "DISPC_DEFAULT_COLOR2,The control register allows to configure the default solid background color for the secondary LCD Shadow register, updated on VFP start period of secondary LCD" hexmask.long.tbyte 0x0 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x3B0++0x3 line.long 0x0 "DISPC_TRANS_COLOR2,The register sets the transparency color value for the video/graphics overlays for the secondary LCD output. Shadow register, updated on VFP start period of the secondary LCD" hexmask.long.tbyte 0x0 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24NOTE: CLUT and BITMAP formats are not supported in this family of devices. ." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x3B4++0x3 line.long 0x0 "DISPC_CPR2_COEF_B,The register configures the color phase rotation matrix coefficients for the Blue component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x0 0.--9. 1. " BB ,BB coefficient encoded signed value (from 512 to 511)." bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 11.--20. 1. " BG ,BG coefficient encoded signed value (from 512 to 511)." bitfld.long 0x0 21. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " BR ,BR coefficient encoded signed value (from 512 to 511)." group.byte 0x3B8++0x3 line.long 0x0 "DISPC_CPR2_COEF_G,The register configures the color phase rotation matrix coefficients for the Green component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x0 0.--9. 1. " GB ,GB coefficient encoded signed value (from 512 to 511)." bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 11.--20. 1. " GG ,GG coefficient encoded signed value (from 512 to 511)." bitfld.long 0x0 21. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " GR ,GR coefficient encoded signed value (from 512 to 511)." group.byte 0x3BC++0x3 line.long 0x0 "DISPC_CPR2_COEF_R,The register configures the color phase rotation matrix coefficients for the Red component. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.word 0x0 0.--9. 1. " RB ,RB coefficient encoded signed value (from 512 to 511)." bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 11.--20. 1. " RG ,RG coefficient encoded signed value (from 512 to 511)." bitfld.long 0x0 21. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RR ,RR coefficient encoded signed value (from 512 to 511)." group.byte 0x3C0++0x3 line.long 0x0 "DISPC_DATA2_CYCLE1,The control register configures the output data format for 1st cycle. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x0 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3C4++0x3 line.long 0x0 "DISPC_DATA2_CYCLE2,The control register configures the output data format for 2nd cycle. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x0 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3C8++0x3 line.long 0x0 "DISPC_DATA2_CYCLE3,The control register configures the output data format for 3rd cycle. Shadow register, updated on VFP start period of secondary LCD" bitfld.long 0x0 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment. Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment. Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3CC++0x3 line.long 0x0 "DISPC_SIZE_LCD2,The register configures the panel size (horizontal and vertical). It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD. A delta value is used to indicate if the odd field has same vertical size as the even field or +/- one line." hexmask.long.word 0x0 0.--11. 1. " PPL ,Pixels per line encoded value (from 1 to 4096) to specify the number of pixels contains within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non STALL mode, only values multiple of 8 pixels are valid." bitfld.long 0x0 12.--13. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 14.--15. " DELTA_LPP ,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. " LPP ,Lines per panel encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1)." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x400++0x3 line.long 0x0 "DISPC_TIMING_H2,The register configures the timing logic for the HSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.byte 0x0 0.--7. 1. " HSW ,Horizontal synchronization pulse width. Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1)." hexmask.long.word 0x0 8.--19. 1. " HFP ,Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before line clock is asserted (program to value minus 1)." textline " " hexmask.long.word 0x0 20.--31. 1. " HBP ,Horizontal back porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1)." group.byte 0x404++0x3 line.long 0x0 "DISPC_TIMING_V2,The register configures the timing logic for the VSYNC signal. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.byte 0x0 0.--7. 1. " VSW ,Vertical synchronization pulse width. In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode." hexmask.long.word 0x0 8.--19. 1. " VFP ,Vertical front porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame." textline " " hexmask.long.word 0x0 20.--31. 1. " VBP ,Vertical back porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display." group.byte 0x408++0x3 line.long 0x0 "DISPC_POL_FREQ2,The register configures the signal configuration. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.byte 0x0 0.--7. 1. " ACB ,AC Bias Pin Frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC Bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge build-up within the display." bitfld.long 0x0 8.--11. " ACBI ,AC Bias Pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC Bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12. " IVS ,Invert VSYNC" "0,1" bitfld.long 0x0 13. " IHS ,Invert HSYNC" "0,1" textline " " bitfld.long 0x0 14. " IPC ,Invert pixel clockNote: Control module register CTRL_CORE_SMA_SW_1[20]DSS_CH1_IPC must be set to match enum=DfPCk ." "0,1" bitfld.long 0x0 15. " IEO ,Invert output enable" "0,1" textline " " bitfld.long 0x0 16. " RF ,Program HSYNC/VSYNC Rise or FallNote: Control module register CTRL_CORE_SMA_SW_1[17]DSS_CH1_RF must be set to match enum=DRiEdPCk ." "0,1" bitfld.long 0x0 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/OffNote: Control module register CTRL_CORE_SMA_SW_1[23]DSS_CH1_ON_OFF must be set to match enum=DBit16 ." "0,1" textline " " bitfld.long 0x0 18. " ALIGN ,Defines the alignment between HSYNC and VSYNC assertion." "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x40C++0x3 line.long 0x0 "DISPC_DIVISOR2,The register configures the divisors. It is used for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD" hexmask.long.byte 0x0 0.--7. 1. " PCD ,Pixel clock divisor value (from 1 to 255) to specify the frequency of the pixel clock based on the LCD2_CLK divided byDISPC_DIVISOR2.LCD value. The value 0 is invalid." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." textline " " hexmask.long.byte 0x0 16.--23. 1. " LCD ,Display controller logic clock divisor value (from 1 to 255) to specify the intermediate pixel clock frequency based on the LCD2_CLK. The value 0 is invalid." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x500++0x3 line.long 0x0 "DISPC_WB_ACCU_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accumulator value encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accumulator value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x504++0x3 line.long 0x0 "DISPC_WB_ACCU_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU_0 and DISPC_WB_ACCU_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accumulator value encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accumulator value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x508++0x3 line.long 0x0 "DISPC_WB_BA_j_0,The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long 0x0 0.--31. 1. " BA ,Write-back base address Base address of the WB buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2;0, byte alignment is supported)). It case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x50C++0x3 line.long 0x0 "DISPC_WB_BA_j_1,The register configures the base address of the WB buffer (DISPC_WB_BA_0 and DISPC_WB_BA_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_0 is used). Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long 0x0 0.--31. 1. " BA ,Write-back base address Base address of the WB buffer (aligned on pixel size boundary except in case of RGB24 packed format, 4-pixel alignment is required; in case of YUV4:2:2, 2-pixel alignment is required, and YUV4:2;0, byte alignment is supported)). It case of YUV4:2:0 format, it indicates the base address of the Y buffer. When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x510++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x518++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x520++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x528++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x530++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x538++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x540++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x548++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x514++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x51C++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x524++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x52C++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x534++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x53C++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x544++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x54C++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x550++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x554++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x558++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x55C++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x560++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x564++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x568++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x56C++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x570++0x3 line.long 0x0 "DISPC_WB_ATTRIBUTES,The register configures the attributes of the viwrite back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." bitfld.long 0x0 0. " ENABLE ,Write-back enable. wr: immediate" "0,1" bitfld.long 0x0 1.--4. " FORMAT ,Write-back format. It defines the pixel format when storing the write-back picture into memory." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5.--6. " RESIZEENABLE ,Resize Enable" "0,1,2,3" bitfld.long 0x0 7. " ALPHAENABLE ,Premultiplied alpha enable Read 0x1: Enabled Read 0x0: Disabled. This bit also disable the logic present in the associated channel out that compute the alpha component sent to the WB pipe. When the WB is configured to copy back one of the output channels (output of overlay), the following configurations are available: 0x1: The WB pipe copies back to memory the premultiplied alpha calculated through the overlay. 0x0: The alpha value is not written back." "0,1" textline " " bitfld.long 0x0 8. " BURSTTYPE ,The type of burst can be INCR (incremental) or BLCK (2D block). The 2D block is required when the TILER is targeted by the DMA engine." "0,1" bitfld.long 0x0 9. " COLORCONVENABLE ,Enable the color space conversion. The hardware does not enable/disable the conversion based on the pixel format. The bit field shall be reset when the format is not YUV." "0,1" textline " " bitfld.long 0x0 10. " TRUNCATIONENABLE ,It applies only when the input format to the write-back pipeline from the overlay or directly from one of the pipelines is ARGB32. If the format is one of the YUV supported formats, the bit field is ignored." "0,1" bitfld.long 0x0 11. " FULLRANGE ,Color Space Conversion full range setting." "0,1" textline " " bitfld.long 0x0 12.--13. " RESERVED ,Reserved . . . ." "0,1,2,3" bitfld.long 0x0 14.--15. " BURSTSIZE ,Write-back DMA Burst Size" "0,1,2,3" textline " " bitfld.long 0x0 16.--18. " CHANNELIN ,Video Channel In configuration WR: immediate" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " WRITEBACKMODE ,When connected to the overlay output of a channel the write back can operate as a simple transfer from memory to memory (composition engine) or as a capture channel. 0x0: Capture mode (default mode) 0x1: Memory-to-memory mode" "0,1" textline " " bitfld.long 0x0 20. " FORCE1DTILEDMODE ,Force TILED regions access to 1D or 2D." "0,1" bitfld.long 0x0 21. " VERTICALTAPS ,Video Vertical Resize Tap Number" "0,1" textline " " bitfld.long 0x0 22. " DOUBLESTRIDE ,Determines if the stride for CbCr buffer is the 1x or 2x of the Y buffer stride. It is only used in case of YUV4:2:0." "0,1" bitfld.long 0x0 23. " ARBITRATION ,Determines the priority of the write-back pipeline. The write-back pipeline is one of the high priority pipeline. The arbitration gives always the priority first to the high priority pipelines using round-robin between them. When there is only normal priority pipelines sending requests, the round-robin applies between them." "0,1" textline " " bitfld.long 0x0 24.--26. " CAPTUREMODE ,Defines the frame rate capture." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " IDLESIZE ,Determines if the IDLENUMBER corresponds to a number of bursts or singles." "0,1" textline " " bitfld.long 0x0 28.--31. " IDLENUMBER ,Determines the number of idles between requests on the L3_MAIN interconnect. It is only used when the write-back pipeline does data transfer from memory to memory. When the output of an overlay is stored in memory through the write-back pipeline in capture mode, the bit field IDLENUMBER is ignored since a timing generator is used to time the transfer. The number of IDLE cycles is IDLENUMBER (from 0 to 15) if IDLESIZE = 0. The number of IDLE cycles is IDLENUMBERx8 (from 0 to 120) if IDLESIZE = 1 and BURSTSIZE = 2. The number of IDLE cycles is IDLENUMBERx4 (from 0 to 60) if IDLESIZE = 1 and BURSTSIZE = 1. The number of IDLE cycles is IDLENUMBERx2 (from 0 to 30) if IDLESIZE = 1 and BURSTSIZE = 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x574++0x3 line.long 0x0 "DISPC_WB_CONV_COEF0,The register configures the color space conversion matrix coefficients for the write back pipeline (YUV4:4:4 to RGB24). Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " YR ,YR coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " YG ,YG coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x578++0x3 line.long 0x0 "DISPC_WB_CONV_COEF1,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " YB ,YB coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CRR ,CrR coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x57C++0x3 line.long 0x0 "DISPC_WB_CONV_COEF2,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " CRG ,CrG coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CRB ,CrB coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x580++0x3 line.long 0x0 "DISPC_WB_CONV_COEF3,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " CBR ,CbR coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " CBG ,CbG coefficient encoded signed value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x584++0x3 line.long 0x0 "DISPC_WB_CONV_COEF4,The register configures the color space conversion matrix coefficients for the write back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " CBB ,CbB coefficient encoded signed value (from 1024 to 1023)." hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x588++0x3 line.long 0x0 "DISPC_WB_BUF_SIZE_STATUS,The register defines the DMA buffer size for the write back pipeline." hexmask.long.word 0x0 0.--15. 1. " BUFSIZE ,DMA buffer Size in number of 128 bits" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x58C++0x3 line.long 0x0 "DISPC_WB_BUF_THRESHOLD,The register configures the DMA buffer associated with the write-back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--15. 1. " BUFLOWTHRESHOLD ,DMA buffer low threshold number of 128 bits defining the threshold value" hexmask.long.word 0x0 16.--31. 1. " BUFHIGHTHRESHOLD ,DMA buffer high threshold number of 128 bits defining the threshold value" group.byte 0x590++0x3 line.long 0x0 "DISPC_WB_FIR,The register configures the resize factors for horizontal and vertical up/downsampling of the write back pipeline. It is used for ARGB and Y setting. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" group.byte 0x594++0x3 line.long 0x0 "DISPC_WB_PICTURE_SIZE,The register configures the size of the write-back picture associated with the write back pipeline after up/down-scaling. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " MEMSIZEX ,Number of pixels of the wb picture in memory. Encoded value (from 1 to 2048) to specify the number of pixels of the picture in memory (program to value minus 1)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " MEMSIZEY ,Number of lines of the wb picture in memory. Encoded value (from 1 to 4096) to specify the number of lines of the picture in memory (program to value minus 1)." bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x598++0x3 line.long 0x0 "DISPC_WB_PIXEL_INC,The register configures the number of bytes to increment between two pixels for the buffer associated with the write back pipeline. The register is used only when the TILER is not present in the system in order to perform low performance rotation. When the TILER IP is present it is highly recommended to use it for performing the rotation. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " PIXELINC ,Values other than 1 are invalid" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x5A4++0x3 line.long 0x0 "DISPC_WB_ROW_INC,The register configures the number of bytes to increment at the end of the row for the buffer associated with the vwrite back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long 0x0 0.--31. 1. " ROWINC ,Number of bytes to increment at the end of the row Encoded signed value (from 21 to 2) to specify the number of bytes to increment at the end of the row in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n *bpp means increment of n pixels. The value 1 (n + 1) * bpp means decrement of n pixels." group.byte 0x5A8++0x3 line.long 0x0 "DISPC_WB_SIZE,The register configures the size of the output of overlay connected to the write-back pipeline when the overlay output is only used by the write-back pipeline. When the overlay is output on the primary LCD or secondary LCD or TV outputs, the size of the frame is defined in the, , and respectively. Shadow register, updated when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " SIZEX ,Number of pixels of the Write-back picture Encoded value (from 1 to 2048) to specify the number of pixels of the write-back picture from overlay or pipeline. Program to value minus 1." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " SIZEY ,Number of lines of the Write-back picture Encoded value (from 1 to 4096) to specify the number of lines of the write-back picture from overlay or pipeline. Program to value minus 1." bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x600++0x3 line.long 0x0 "DISPC_VID1_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x604++0x3 line.long 0x0 "DISPC_VID1_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 1. (DISPC_VID1_BA_UV_0 and DISPC_VID1_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID1_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x608++0x3 line.long 0x0 "DISPC_VID2_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x60C++0x3 line.long 0x0 "DISPC_VID2_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 2. (DISPC_VID2_BA_UV_0 and DISPC_VID2_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID2_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address aligned on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x610++0x3 line.long 0x0 "DISPC_VID3_BA_UV_j_0,The register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x614++0x3 line.long 0x0 "DISPC_VID3_BA_UV_j_1,The register configures the base address of the UV buffer for the video window 3. (DISPC_VID3_BA_UV_0 and DISPC_VID3_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_VID3_BA_UV_0 is used)). Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long 0x0 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x618++0x3 line.long 0x0 "DISPC_WB_BA_UV_j_0,The register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 is used)). Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long 0x0 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x61C++0x3 line.long 0x0 "DISPC_WB_BA_UV_j_1,The register configures the base address of the UV buffer for the write-back pipeline. (DISPC_WB_BA_UV_0 and DISPC_WB_BA_UV_1 for ping-pong mechanism with external trigger, based on the field polarity otherwise only DISPC_WB_BA_UV_0 is used)). Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long 0x0 0.--31. 1. " BA ,Video base address alinged on 16-bit boundary Base address of the UV video buffer used only in case of YUV4:2:0-NV12 When the TILER is addressed, the bits: [28:27] = 0x0 for 8-bit tiled [28:27] = 0x1 for 16-bit tiled [28:27] = 0x2 for 32-bit tiled [28:27] = 0x3 for page mode [31:29] = 0x0 for 0-degree view [31:29] = 0x1 for 180-degree view + mirroring [31:29] = 0x2 for 0-degree view + mirroring [31:29] = 0x3 for 180-degree view [31:29] = 0x4 for 270-degree view + mirroring [31:29] = 0x5 for 270-degree view [31:29] = 0x6 for 90-degree view [31:29] = 0x7 for 90-degree view + mirroring Otherwise the bits indicated the corresponding bit address to access the SDRAM." group.byte 0x620++0x3 line.long 0x0 "DISPC_CONFIG2,The control register configures the Display Controller module for the secondary LCD output. Shadow register, updated on VFP start period of secondary LCD or VFP start period of the third LCD or EVSYNC" bitfld.long 0x0 0. " PIXELGATED ,Pixel gated enable (only for active matrix) (secondary LCD output) wr: VFP start period of secondary LCD output" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " PIXELDATA_GATED ,Pixel data gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output" "0,1" bitfld.long 0x0 5. " PIXELCLOCK_GATED ,Pixel clock gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output" "0,1" textline " " bitfld.long 0x0 6. " HSYNCGATED ,HSYNC gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output" "0,1" bitfld.long 0x0 7. " VSYNCGATED ,VSYNC gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output" "0,1" textline " " bitfld.long 0x0 8. " ACBIASGATED ,ACBias gated enabled (secondary LCD output) wr: VFP start period of secondary LCD output" "0,1" bitfld.long 0x0 9. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 10. " TCKLCDENABLE ,Transparency color key enabled (secondary LCD output) wr: VFP start period of secondary LCD output" "0,1" bitfld.long 0x0 11. " TCKLCD_SELECTION ,Transparency color key selection (secondary LCD output) wr: VFP start period of secondary LCD output" "0,1" textline " " bitfld.long 0x0 12.--14. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " CPR ,Color Phase Rotation Control secondary LCD output). It shall be reset when ColorConvEnable bit field is set to 1. wr: VFP start period of secondary LCD output" "0,1" textline " " bitfld.long 0x0 16.--19. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20. " BT656ENABLE ,Selects BT.656 format on the primary LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time one the same LCD output. wr: VFP start of primary LCD" "0,1" textline " " bitfld.long 0x0 21. " BT1120ENABLE ,Selects BT.1120 format on the primary LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time one the same LCD output. wr: VFP start of primary LCD" "0,1" bitfld.long 0x0 22. " OUTPUTMODE_ENABLE ,Selects between progressive and interlace mode for the secondary LCD output." "0,1" textline " " bitfld.long 0x0 23. " FIDFIRST ,Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used." "0,1" bitfld.long 0x0 24. " COLORCONV_ENABLE ,Enable the color space conversion. It shall be reset when CPR bit field is set to 0x1." "0,1" textline " " bitfld.long 0x0 25. " FULLRANGE ,Color space conversion full range setting." "0,1" bitfld.long 0x0 26.--27. " SLCDINTERLEAVE ,sLCD Interleave Pattern" "0,1,2,3" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x624++0x3 line.long 0x0 "DISPC_VID1_ATTRIBUTES2,The register configures the attributes of the video window 1. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" bitfld.long 0x0 0. " VC1ENABLE ,Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats." "0,1" bitfld.long 0x0 1.--3. " VC1_RANGE_Y ,Defines the VC-1 range value for the Y component from 0 to 7." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " VC1_RANGE_CBCR ,Defines the VC-1 range value for the CbCr component from 0 to 7." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 8. " YUVCHROMARE_SAMPLING ,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe." "0,1" bitfld.long 0x0 9.--11. " SUBSAMPLINGPATTERN ,Subsampling pattern setting." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x628++0x3 line.long 0x0 "DISPC_VID2_ATTRIBUTES2,The register configures the attributes of the video window 2. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" bitfld.long 0x0 0. " VC1ENABLE ,Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats." "0,1" bitfld.long 0x0 1.--3. " VC1_RANGE_Y ,Defines the VC-1 range value for the Y component from 0 to 7." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " VC1_RANGE_CBCR ,Defines the VC-1 range value for the CbCr component from 0 to 7." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 8. " YUVCHROMARE_SAMPLING ,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe." "0,1" bitfld.long 0x0 9.--11. " SUBSAMPLINGPATTERN ,Subsampling pattern setting." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x62C++0x3 line.long 0x0 "DISPC_VID3_ATTRIBUTES2,The register configures the attributes of the video window 3. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" bitfld.long 0x0 0. " VC1ENABLE ,Enable/disable the VC-1 range mapping processing. The bit field is ignored if the format is not one of the supported YUV formats." "0,1" bitfld.long 0x0 1.--3. " VC1_RANGE_Y ,Defines the VC-1 range value for the Y component from 0 to 7." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " VC1_RANGE_CBCR ,Defines the VC-1 range value for the CbCr component from 0 to 7." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 8. " YUVCHROMARE_SAMPLING ,The YUV chrominance can be resampled using averaging of the adjacent chrominance samples, without using the polyphase filter for 4:2:2 input or can be calculated using the polyphase filter for 4:2:2/4:2:0. The polyphase filter is mandatory for the 4:2:0 format. This bit controls the order in which the processing is done on the video pipe." "0,1" bitfld.long 0x0 9.--11. " SUBSAMPLINGPATTERN ,Subsampling pattern setting." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x630++0x3 line.long 0x0 "DISPC_GAMMA_TABLE0,The register configures the look up table used as color look up table for BITMAP formats (1-, 2-, 4, and 8-bpp) on the graphics pipeline or as gamma table on the primary LCD output. NOTE: CLUT and BITMAP formats are not supported in this family of devices." hexmask.long.byte 0x0 0.--7. 1. " VALUE_B ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" hexmask.long.byte 0x0 8.--15. 1. " VALUE_G ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" textline " " hexmask.long.byte 0x0 16.--23. 1. " VALUE_R ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" hexmask.long.byte 0x0 24.--31. 1. " INDEX ,Defines the location in the table where the bit field VALUE is stored." group.byte 0x634++0x3 line.long 0x0 "DISPC_GAMMA_TABLE1,The register configures the gamma table on the secondary LCD output." hexmask.long.byte 0x0 0.--7. 1. " VALUE_B ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" hexmask.long.byte 0x0 8.--15. 1. " VALUE_G ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" textline " " hexmask.long.byte 0x0 16.--23. 1. " VALUE_R ,8-bit value used to defined the value to store at the location in the table defined by the bit field INDEX" hexmask.long.byte 0x0 24.--31. 1. " INDEX ,Defines the location in the table where the bit field VALUE is stored." group.byte 0x638++0x3 line.long 0x0 "DISPC_GAMMA_TABLE2,The register configures the gamma table on the TV output." hexmask.long.word 0x0 0.--9. 1. " VALUE_B ,10-bit color component value to store in the table" hexmask.long.word 0x0 10.--19. 1. " VALUE_G ,10-bit color component value to store in the table" textline " " hexmask.long.word 0x0 20.--29. 1. " VALUE_R ,10-bit color component value to store in the table" bitfld.long 0x0 30. " RESERVED ," "0,1" textline " " bitfld.long 0x0 31. " INDEX ,Setting this bit to 1 resets the internal index counter to zero. Each subsequent access to the register (with the INDEX bit kept at 0) increments the address for the next storage location into the table memory." "0,1" group.byte 0x63C++0x3 line.long 0x0 "DISPC_VID1_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 1. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "DISPC_VID1_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x644++0x3 line.long 0x0 "DISPC_VID1_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 1 (DISPC_VID1_ACCU2_0 and DISPC_VID1_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity) It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x648++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x650++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x658++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x660++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x668++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x670++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x678++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x680++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x64C++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x654++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x65C++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x664++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x66C++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x674++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x67C++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x684++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x688++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x68C++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x690++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x694++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x698++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x69C++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x6A0++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x6A4++0x3 line.long 0x0 "DISPC_VID1_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 1 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x6A8++0x3 line.long 0x0 "DISPC_VID2_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 2. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" group.byte 0x6AC++0x3 line.long 0x0 "DISPC_VID2_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x6B0++0x3 line.long 0x0 "DISPC_VID2_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 2 (DISPC_VID2_ACCU2_0 and DISPC_VID2_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x6B4++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x6BC++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x6C4++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x6CC++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x6D4++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x6DC++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x6E4++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x6EC++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x6B8++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x6C0++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x6C8++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x6D0++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x6D8++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x6E0++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x6E8++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x6F0++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x6F4++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x6F8++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x6FC++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x700++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x704++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x708++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x70C++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x710++0x3 line.long 0x0 "DISPC_VID2_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 2 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x724++0x3 line.long 0x0 "DISPC_VID3_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the video window 3. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" group.byte 0x728++0x3 line.long 0x0 "DISPC_VID3_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x72C++0x3 line.long 0x0 "DISPC_VID3_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the video window 3 (DISPC_VID3_ACCU2_0 and DISPC_VID3_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x730++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x738++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x740++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x748++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x750++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x758++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x760++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x768++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x734++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x73C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x744++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x74C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x754++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x75C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x764++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x76C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x770++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x774++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x778++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x77C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x780++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x784++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x788++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x78C++0x3 line.long 0x0 "DISPC_VID3_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the video window 3 for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or VFP start period of the third LCD or EVSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output or write-back to the memory" hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x790++0x3 line.long 0x0 "DISPC_WB_FIR2,The register configures the resize factors for horizontal and vertical up/downsampling of the write-back pipeline. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--12. 1. " FIRHINC ,Horizontal increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--28. 1. " FIRVINC ,Vertical increment of the up/downsampling filter for Cb and Cr. Encoded value (from 1 to 4096). The value 0 is invalid. The values greater than 4096 are invalid." bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" group.byte 0x794++0x3 line.long 0x0 "DISPC_WB_ACCU2_j_0,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x798++0x3 line.long 0x0 "DISPC_WB_ACCU2_j_1,The register configures the resize accumulator init values for horizontal and vertical up/downsampling of the write back pipeline (DISPC_WB_ACCU2_0 and DISPC_WB_ACCU2_1 for ping-pong mechanism with external trigger, based on the field polarity). It is used for Cb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--10. 1. " HORIZONTALACCU ,Horizontal initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 11.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " VERTICALACCU ,Vertical initialization accu value Encoded value (from 1024 to 1023)." bitfld.long 0x0 27.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x7A0++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H2_i_0,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x7A8++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H2_i_1,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x7B0++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H2_i_2,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x7B8++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H2_i_3,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x7C0++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H2_i_4,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x7C8++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H2_i_5,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x7D0++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H2_i_6,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x7D8++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_H2_i_7,The bank of registers configure the up/down-scaling coefficients for the horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC0 ,Signed coefficient C0 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRHC1 ,Signed coefficient C1 for the horizontal up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRHC2 ,Unsigned coefficient C2 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRHC3 ,Signed coefficient C3 for the horizontal up/down-scaling with the phase n" group.byte 0x7A4++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x7AC++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x7B4++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x7BC++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x7C4++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x7CC++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x7D4++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x7DC++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_HV2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical and horizontal resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRHC4 ,Signed coefficient C4 for the horizontal up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC0 ,Signed coefficient C0 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.byte 0x0 16.--23. 1. " FIRVC1 ,Unsigned coefficient C1 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 24.--31. 1. " FIRVC2 ,Signed coefficient C2 for the vertical up/down-scaling with the phase n" group.byte 0x7E0++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V2_i_0,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x7E4++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V2_i_1,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x7E8++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V2_i_2,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x7EC++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V2_i_3,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x7F0++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V2_i_4,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x7F4++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V2_i_5,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x7F8++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V2_i_6,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x7FC++0x3 line.long 0x0 "DISPC_WB_FIR_COEF_V2_i_7,The bank of registers configure the down/up/down-scaling coefficients for the vertical resize of the video picture associated with the write back pipeline for the phases from 0 to 7. It is used for Crb and Cr setting. It is used only when the pixel format at the input of the filter is one of the YUV formats. If the pixel format at the input of the filter is ARGB (all ARGB, RGB, RGBA are converted to ARGB32-8888 by the color space conversion before going to the filter is the color space conversion is done before the filter). When the register is not used by the hardware, any value can be used for the bit fields. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " FIRVC00 ,Signed coefficient C00 for the vertical up/down-scaling with the phase n" hexmask.long.byte 0x0 8.--15. 1. " FIRVC22 ,Signed coefficient C22 for the vertical up/down-scaling with the phase n" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x800++0x3 line.long 0x0 "DISPC_GLOBAL_BUFFER,The register configures the DMA buffers allocations to the pipeline (graphics, video1, video2, video3 and write-back). Both TOP and BOTTOM must be allocated to the same pipeline." bitfld.long 0x0 0.--5. " GFX_BUFFER ,Graphics DMA buffer allocation to one of the pipelines. By default to graphics pipeline." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--11. " VID1_BUFFER ,Video1 DMA buffer allocation to one of the pipelines. By default to video 1 pipeline." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 12.--17. " VID2_BUFFER ,Video2 DMA buffer allocation to one of the pipelines. By default to video2 pipeline." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 18.--23. " VID3_BUFFER ,Video3 DMA buffer allocation to one of the pipelines. By default to video3 pipeline." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24.--29. " WB_BUFFER ,Write-back DMA buffer allocation to one of the pipelines. By default to write-back pipeline." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3" group.byte 0x804++0x3 line.long 0x0 "DISPC_DIVISOR,The register configures the divisor value for generating the core functional clock. There is a backward compatibility mode enabled by default in order to use.LCD value instead of .LCD bit field for generating the core functional clock." bitfld.long 0x0 0. " ENABLE ,When the bit field is set to 1, the bit field LCD is used to generated the core functional clock from the input clock. When the bit field is set to 0, the valueDISPC_DIVISOR1.LCD is used instead." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." textline " " hexmask.long.byte 0x0 16.--23. 1. " LCD ,Display Controller Logic Clock Divisor Value (from 1 to 255) to specify the frequency of the Display Controller logic clock based on the function clock. The value 0 is invalid." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x810++0x3 line.long 0x0 "DISPC_WB_ATTRIBUTES2,The register set the counter to control the delay to flush the WB pipe after the end of the frame in capture mode. Shadow register, updated when .GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.byte 0x0 0.--7. 1. " WBDELAYCOUNT ,Delays the WB pipe flush after the end of the frame. Delay = n (number of lines), where n = 0:255. If n = 0, the WB is re-initialized just at the end of the last line of a frame at the beginning of the VFP signal. If n = 1:255, the write buffers DMA are flushed n lines later." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x814++0x3 line.long 0x0 "DISPC_DEFAULT_COLOR3,The control register allows to configure the default solid background color for the third LCD. Shadow register, updated on VFP start period of third LCD" hexmask.long.tbyte 0x0 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display when there is no data from the overlays" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x818++0x3 line.long 0x0 "DISPC_TRANS_COLOR3,The register sets the transparency color value for the video/graphics overlays for the third LCD output. Shadow register, updated on VFP start period of the third LCD" hexmask.long.tbyte 0x0 0.--23. 1. " TRANSCOLORKEY ,Transparency color key value in RGB format [0] BITMAP 1 (CLUT), [23,1] set to 0s [1:0] BITMAP 2 (CLUT), [23,2] set to 0s [3:0] BITMAP 4 (CLUT), [23,4] set to 0s [7:0] BITMAP 8 (CLUT), [23,8] set to 0s [11:0] RGB 12, [23,12] set to 0s [15:0] RGB 16, [23,16] set to 0s [23:0] RGB 24 NOTE: CLUT and BITMAP formats are not supported in this family of devices." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x81C++0x3 line.long 0x0 "DISPC_CPR3_COEF_B,The register configures the color phase rotation matrix coefficients for the blue component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of third LCD" hexmask.long.word 0x0 0.--9. 1. " BB ,BB coefficient Encoded signed value (from 512 to 511)" bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 11.--20. 1. " BG ,BG coefficient Encoded signed value (from 512 to 511)" bitfld.long 0x0 21. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " BR ,BR coefficient Encoded signed value (from 512 to 511)" group.byte 0x820++0x3 line.long 0x0 "DISPC_CPR3_COEF_G,The register configures the color phase rotation matrix coefficients for the green component. It is used for the secondary LCD output. Shadow register, updated on VFP start period of third LCD" hexmask.long.word 0x0 0.--9. 1. " GB ,GB coefficient Encoded signed value (from 512 to 511)" bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 11.--20. 1. " GG ,GG coefficient Encoded signed value (from 512 to 511)" bitfld.long 0x0 21. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " GR ,GRcoefficient Encoded signed value (from 512 to 511)" group.byte 0x824++0x3 line.long 0x0 "DISPC_CPR3_COEF_R,The register configures the color phase rotation matrix coefficients for the red component. Shadow register, updated on VFP start period of third LCD" hexmask.long.word 0x0 0.--9. 1. " RB ,RB coefficient Encoded signed value (from 512 to 511)" bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 11.--20. 1. " RG ,RG coefficient Encoded signed value (from 512 to 511)" bitfld.long 0x0 21. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RR ,RR coefficient Encoded signed value (from 512 to 511)" group.byte 0x828++0x3 line.long 0x0 "DISPC_DATA3_CYCLE1,The control register configures the output data format for the first cycle. Shadow register, updated on VFP start period of third LCD" bitfld.long 0x0 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x82C++0x3 line.long 0x0 "DISPC_DATA3_CYCLE2,The control register configures the output data format for the second cycle. Shadow register, updated on VFP start period of third LCD" bitfld.long 0x0 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x830++0x3 line.long 0x0 "DISPC_DATA3_CYCLE3,The control register configures the output data format for the third cycle. Shadow register, updated on VFP start period of third LCD" bitfld.long 0x0 0.--4. " NBBITSPIXEL1 ,Number of bits Number of bits from the pixel 1 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment Alignment of the bits from pixel 1 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " NBBITSPIXEL2 ,Number of bits Number of bits from the pixel 2 (value from 0 to 16 bits). The values from 17 to 31 are invalid." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment Alignment of the bits from pixel 2 on the output interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x834++0x3 line.long 0x0 "DISPC_SIZE_LCD3,The register configures the panel size (horizontal and vertical). It is used for the third LCD output. Shadow register, updated on VFP start period of the third LCD. A delta value is used to indicate if the odd field is the same vertical size as the even field or 1 one line." hexmask.long.word 0x0 0.--11. 1. " PPL ,Pixels per line Encoded value (from 1 to 4096) to specify the number of pixels contained within each line on the display (program to value minus 1). In STALL mode, any value is valid. In non-STALL mode, only values of multiples of 8 pixels are valiid." bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14.--15. " DELTA_LPP ,Indicates the delta size value of the odd field compared to the even field" "0,1,2,3" hexmask.long.word 0x0 16.--27. 1. " LPP ,Lines per panel Encoded value (from 1 to 4096) to specify the number of lines per panel (program to value minus 1)." textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x838++0x3 line.long 0x0 "DISPC_DIVISOR3,The register configures the divisors. It is used for the third LCD output. Shadow register, updated on VFP start period of the third LCD" hexmask.long.byte 0x0 0.--7. 1. " PCD ,Pixel clock divisor Value (from 1 to 255) to specify the frequency of the pixel clock based on LCD2_CLK divided by the value of DISPC_DIVISOR2.LCD. The value 0 is invalid." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." textline " " hexmask.long.byte 0x0 16.--23. 1. " LCD ,Display controller logic clock divisor Value (from 1 to 255) to specify the intermediate pixel clock frequency based on LCD2_CLK. The value 0 is invalid." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x83C++0x3 line.long 0x0 "DISPC_POL_FREQ3,The register configures the signal configuration. It is used for the third LCD output. Shadow register, updated on VFP start period of the third LCD" hexmask.long.byte 0x0 0.--7. 1. " ACB ,AC bias pin frequency Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge buildup within the display." bitfld.long 0x0 8.--11. " ACBI ,AC bias pin transitions per interrupt Value (from 0 to 15) used to specify the number of AC bias pin transitions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12. " IVS ,Invert VSYNC" "0,1" bitfld.long 0x0 13. " IHS ,Invert HSYNC" "0,1" textline " " bitfld.long 0x0 14. " IPC ,Invert pixel clockNote: Control module register CTRL_CORE_SMA_SW_1[21] DSS_CH2_IPC must be set to match enum=DfPCk ." "0,1" bitfld.long 0x0 15. " IEO ,Invert output enable" "0,1" textline " " bitfld.long 0x0 16. " RF ,Program HSYNC/VSYNC rise or fallNote: Control module register CTRL_CORE_SMA_SW_1[18] DSS_CH2_RF must be set to match enum=DRiEdPCk ." "0,1" bitfld.long 0x0 17. " ONOFF ,HSYNC/VSYNC pixel clock control on/offNote: Control module register CTRL_CORE_SMA_SW_1[24] DSS_CH2_ON_OFF must be set to match enum=DBit16 ." "0,1" textline " " bitfld.long 0x0 18. " ALIGN ,Defines the alignment betwwen HSYNC and VSYNC assertion" "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x840++0x3 line.long 0x0 "DISPC_TIMING_H3,The register configures the timing logic for the HSYNC signal. It is used for the third LCD output. Shadow register, updated on VFP start period of the third LCD" hexmask.long.byte 0x0 0.--7. 1. " HSW ,Horizontal synchronization pulse width. Encoded value (from 1 to 256) to specify the number of pixel clock periods to pulse the line clock at the end of each line (program to value minus 1)." hexmask.long.word 0x0 8.--19. 1. " HFP ,Horizontal front porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the end of a line transmission before the line clock is asserted (program to value minus 1)." textline " " hexmask.long.word 0x0 20.--31. 1. " HBP ,Horizontal back porch. Encoded value (from 1 to 4096) to specify the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display (program to value minus 1)." group.byte 0x844++0x3 line.long 0x0 "DISPC_TIMING_V3,The register configures the timing logic for the VSYNC signal. It is used for the third LCD output. Shadow register, updated on VFP start period of the third LCD" hexmask.long.byte 0x0 0.--7. 1. " VSW ,Vertical synchronization pulse width. In active mode, encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode." hexmask.long.word 0x0 8.--19. 1. " VFP ,Vertical front porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame" textline " " hexmask.long.word 0x0 20.--31. 1. " VBP ,Vertical back porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame before the first set of pixels is output to the display" group.byte 0x848++0x3 line.long 0x0 "DISPC_CONTROL3,The control register configures the display controller module for the third LCD output." bitfld.long 0x0 0. " LCDENABLE ,Enable the third LCD output wr: Immediate" "0,1" bitfld.long 0x0 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 2. " MONOCOLOR ,Monochrome/color selection for the third LCD wr: VFP start period of the third LCD output" "0,1" bitfld.long 0x0 3. " STNTFT ,LCD Display type of the third LCD wr: VFP start period of the third LCD output" "0,1" textline " " bitfld.long 0x0 4. " M8B ,Mono 8-bit mode of the third LCD wr: VFP start period of the third LCD output" "0,1" bitfld.long 0x0 5. " GOLCD ,GO command for the third LCD output. It is used to synchronized the pipelines (graphics and/or video) associated with the third LCD output. wr: Immediate" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " STDITHERENABLE ,Spatial temporal dithering enable for the third LCD output wr: VFP start period of the third LCD output" "0,1" textline " " bitfld.long 0x0 8.--9. " TFTDATALINES ,Number of lines of the third LCD interface wr: VFP start period of the third LCD output" "0,1,2,3" bitfld.long 0x0 10. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 11. " STALLMODE ,STALL mode for the third LCD output wr: VFP start period of the third LCD output" "0,1" bitfld.long 0x0 12. " OVERLAYOPTIMIZATION ,Overlay optimization for the third LCD output wr: VFP or EVSYNC or when DISPC_CONTROL2.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, third LCD, TV output, or write-back to the memory." "0,1" textline " " bitfld.long 0x0 13. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 14.--19. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 20. " TDMENABLE ,Enable the multiple cycle format for the third LCD output wr: VFP start period of third LCD output" "0,1" bitfld.long 0x0 21.--22. " TDMPARALLELMODE ,Output interface width (TDM mode only) for the third LCD output wr: VFP start period of the third LCD output" "0,1,2,3" textline " " bitfld.long 0x0 23.--24. " TDMCYCLEFORMAT ,Cycle format (TDM mode only) for the third LCD output wr: VFP start period of third LCD output" "0,1,2,3" bitfld.long 0x0 25.--26. " TDMUNUSEDBITS ,State of unused bits (TDM mode only) for the third LCD output wr: VFP start period of the third LCD output" "0,1,2,3" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SPATIALTEMPORALDITHERINGFRAMES ,Spatial/temporal dithering number of frames for the third LCD output wr: VFP start period of the third LCD output" "0,1,2,3" group.byte 0x84C++0x3 line.long 0x0 "DISPC_CONFIG3,The control register configures the display controller module for the third LCD output. Shadow register, updated on VFP start period of the third LCD or EVSYNC" bitfld.long 0x0 0. " PIXELGATED ,Pixel gated enable (only for TFT) (third LCD output) wr: VFP start period of the third LCD output" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " PIXELDATAGATED ,Pixel data gated enabled (third LCD output) wr: VFP start period of the third LCD output" "0,1" bitfld.long 0x0 5. " PIXELCLOCKGATED ,Pixel clock gated enabled (third LCD output) wr: VFP start period of the third LCD output" "0,1" textline " " bitfld.long 0x0 6. " HSYNCGATED ,HSYNC gated enabled (third LCD output) wr: VFP start period of the third LCD output" "0,1" bitfld.long 0x0 7. " VSYNCGATED ,VSYNC gated enabled (third LCD output) wr: VFP start period of the third LCD output" "0,1" textline " " bitfld.long 0x0 8. " ACBIASGATED ,ACBias gated enabled (third LCD output) wr: VFP start period of the third LCD output" "0,1" bitfld.long 0x0 9. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" textline " " bitfld.long 0x0 10. " TCKLCDENABLE ,Transparency color key enabled (third LCD output) wr: VFP start period of the third LCD output" "0,1" bitfld.long 0x0 11. " TCKLCDSELECTION ,Transparency color key selection (third LCD output) wr: VFP start period of the third LCD output" "0,1" textline " " bitfld.long 0x0 12.--14. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " CPR ,Color phase rotation control ( third LCD output). It must be reset when the ColorConvEnable bit field is set to 1. wr: VFP start period of the third LCD output" "0,1" textline " " bitfld.long 0x0 16.--19. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20. " BT656ENABLE ,Selects BT.656 format on the third LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time on the same LCD output." "0,1" textline " " bitfld.long 0x0 21. " BT1120ENABLE ,Selects BT.1120 format on the third LCD output. It is not posssible to enable BT.656 and BT.1120 at the same time on the same LCD output." "0,1" bitfld.long 0x0 22. " OUTPUTMODEENABLE ,Selects between progressive and interlace mode for the third LCD output" "0,1" textline " " bitfld.long 0x0 23. " FIDFIRST ,Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used." "0,1" bitfld.long 0x0 24. " COLORCONVENABLE ,Enable the color space conversion. It must be reset when the CPR bit field is set to 0x1." "0,1" textline " " bitfld.long 0x0 25. " FULLRANGE ,Color space conversion full range setting" "0,1" bitfld.long 0x0 26.--27. " TLCDINTERLEAVE ,tLCD interleave Pattern" "0,1,2,3" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x850++0x3 line.long 0x0 "DISPC_GAMMA_TABLE3,The register configures the gamma table on the third LCD output." hexmask.long.byte 0x0 0.--7. 1. " VALUE_B ,8-bit value used to define the value to store at the location in the table defined by the INDEX bit field" hexmask.long.byte 0x0 8.--15. 1. " VALUE_G ,8-bit value used to define the value to store at the location in the table defined by the INDEX bit field" textline " " hexmask.long.byte 0x0 16.--23. 1. " VALUE_R ,8-bit value used to define the value to store at the location in the table defined by the INDEX bit field" hexmask.long.byte 0x0 24.--31. 1. " INDEX ,Defines the location in the table where the VALUE bit field is stored." group.byte 0x854++0x3 line.long 0x0 "DISPC_BA0_FLIPIMMEDIATE_EN,This register enables the flip immediate." bitfld.long 0x0 0. " GFX ,Enable flip immediate for gfx pipeline" "0,1" bitfld.long 0x0 1. " VID1 ,Enable flip immediate for video1 pipeline" "0,1" textline " " bitfld.long 0x0 2. " VID2 ,Enable flip immediate for video2 pipeline" "0,1" bitfld.long 0x0 3. " VID3 ,Enable flip immediate for video3 pipeline" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved." group.byte 0x858++0x3 line.long 0x0 "DISABLE_MSTANDBY_ENHANCEMENT,This register disables the DISPC DMA Mstandby behavior enhancement." bitfld.long 0x0 0. " DISABLE_MSTANDBY_ENHANCEMENT ,0: DISPC DMA Mstandby behavior enhancement is enabled. 1: Disable DISPC DMA Mstandby behavior enhancement. This is the recommended setting." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved." group.byte 0x85C++0x3 line.long 0x0 "DISPC_GLOBAL_MFLAG_ATTRIBUTE,Global MFLAG atrribute control register." bitfld.long 0x0 0.--1. " MFLAG_CTRL ,MFLAG control" "0,1,2,3" bitfld.long 0x0 2. " MFLAG_START ,MFLAG Start" "0,1" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved." group.byte 0x860++0x3 line.long 0x0 "DISPC_GFX_MFLAG_THRESHOLD,MFLAG thresholds for graphics pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or external VSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory." hexmask.long.word 0x0 0.--15. 1. " LT_MFLAG ,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level, MFLAG is set to 1" hexmask.long.word 0x0 16.--31. 1. " HT_MFLAG ,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level, MFLAG is reset to 0" group.byte 0x864++0x3 line.long 0x0 "DISPC_VID1_MFLAG_THRESHOLD,MFLAG thresholds for video1 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or external VSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory." hexmask.long.word 0x0 0.--15. 1. " LT_MFLAG ,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level, MFLAG is set to 1" hexmask.long.word 0x0 16.--31. 1. " HT_MFLAG ,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level, MFLAG is reset to 0" group.byte 0x868++0x3 line.long 0x0 "DISPC_VID2_MFLAG_THRESHOLD,MFLAG thresholds for video2 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or external VSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory." hexmask.long.word 0x0 0.--15. 1. " LT_MFLAG ,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level, MFLAG is set to 1" hexmask.long.word 0x0 16.--31. 1. " HT_MFLAG ,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level, MFLAG is reset to 0" group.byte 0x86C++0x3 line.long 0x0 "DISPC_VID3_MFLAG_THRESHOLD,MFLAG thresholds for video3 pipeline. Shadow register, updated on VFP start period of primary LCD or VFP start period of the secondary LCD or external VSYNC or when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline). The synchronization event is defined based on the output using the pipeline: primary LCD, secondary LCD, TV output or write-back to the memory." hexmask.long.word 0x0 0.--15. 1. " LT_MFLAG ,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level, MFLAG is set to 1" hexmask.long.word 0x0 16.--31. 1. " HT_MFLAG ,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level, MFLAG is reset to 0" group.byte 0x870++0x3 line.long 0x0 "DISPC_WB_MFLAG_THRESHOLD,MFLAG thresholds for write-back pipeline. Shadow register, updated when.GOWB is set to 1 by software and current WB frame is finished (no more data in the write-back pipeline), when the WB pipeline is directly connected to one of the pipelines (graphics or video), combined with the synchronization event of the channel overlay output selected as an input to the WB pipeline (that is, VFP start period of primary LCD, or VFP start period of secondary LCD, or VFP start period of the third LCD, or EVSYNC), for all registers associated with the selected channel out and further delayed by the .WBDELAYCOUNT bit-field, for all registers of the Write back and DMA. In WB capture mode, both .GOWB and DISPC_CONTROL#.GOLCD/TV corresponding to the selected output channel shall be set. It is not required to set the GOWB bit when WB memory-to-memory mode is used." hexmask.long.word 0x0 0.--15. 1. " LT_MFLAG ,Low Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches LT_MFLAG level, MFLAG is set to 1" hexmask.long.word 0x0 16.--31. 1. " HT_MFLAG ,High Thresholds (in 128bits) for MFLAG generation: when FIFO fullness reaches HT_MFLAG level, MFLAG is reset to 0" width 0x0B tree.end tree "GPU_WRAPPER" base ad:0x5600FE00 width 17. group.byte 0x0++0x3 line.long 0x0 "REVISION,Revision register" hexmask.long 0x0 0.--31. 1. " REVISIONID ,Revision value" group.byte 0x4++0x3 line.long 0x0 "HWINFO,Hardware implementation information" bitfld.long 0x0 0.--1. " SYS_BUS_WIDTH ,System bus width Read 0x0: 32 bits Read 0x1: 64 bits Read 0x2: 128 bits Read 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 2. " MEM_BUS_WIDTH ,Memory bus width Read 0x0: 64 bits Read 0x1: 128 bits" "0,1" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "SYSCONFIG,System configuration register" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLE_MODE ,Clock idle mode: 0x0: Force-standby 0x1: No-standby 0x2: Smart-standby 0x3: Reserved" "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBY_MODE ,Clock standby mode: 0x0: Force-standby 0x1: No-standby 0x2: Smart-standby 0x3: Reserved" "0,1,2,3" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW_0,Raw IRQ 0 status" bitfld.long 0x0 0. " INIT_MINTERRUPT_RAW ,Interrupt 0 raw event: Write 0x0: No action Write 0x1: Set event (used for debug) Read 0x0: No event pending Read 0x1: Event pending" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS_RAW_1,Raw IRQ 1 status. Slave port interrupt." bitfld.long 0x0 0. " TARGET_SINTERRUPT_RAW ,Interrupt 1 raw event: Write 0x0: No action Write 0x1: Set event (used for debug) Read 0x0: No event pending Read 0x1: Event pending" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "IRQSTATUS_RAW_2,Raw IRQ 2 status. Core interrupt." bitfld.long 0x0 0. " THALIA_IRQ_RAW ,Interrupt 0 raw event: Write 0x0: No action Write 0x1: Set event (used for debug) Read 0x0: No event pending Read 0x1: Event pending" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "IRQSTATUS_0,Interrupt 0 status event. Master port interrupt." bitfld.long 0x0 0. " INIT_MINTERRUPT_STATUS ,Interrupt 0 raw event: Write 0x0: No action Write 0x1: Clear event Read 0x0: No event pending Read 0x1: Event pending and interrupt enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "IRQSTATUS_1,Interrupt 1 - slave port status event" bitfld.long 0x0 0. " TARGET_SINTERRUPT_STATUS ,Interrupt 0 raw event: Write 0x0: No action Write 0x1: Clear event Read 0x0: No event pending Read 0x1: Event pending and interrupt enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "IRQSTATUS_2,Interrupt 2 - Core status event" bitfld.long 0x0 0. " THALIA_IRQ_STATUS ,Interrupt 0 raw event: Write 0x0: No action Write 0x1: Clear event Read 0x0: No event pending Read 0x1: Event pending and interrupt enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "IRQENABLE_SET_0,Enable Interrupt 0 - Master port." bitfld.long 0x0 0. " INIT_MINTERRUPT_ENABLE ,To enable interrupt: Write 0x0: No action Write 0x1: Enable interrupt Read 0x0: Interrupt is disabled Read 0x1: Interrupt is enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "IRQENABLE_SET_1,Enable Interrupt 1. Core interrupt." bitfld.long 0x0 0. " TARGET_SINTERRUPT_ENABLE ,To enable interrupt: Write 0x0: No action Write 0x1: Enable interrupt Read 0x0: Interrupt is disabled Read 0x1: Interrupt is enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "IRQENABLE_SET_2,Enable Interrupt 2. Core interrupt." bitfld.long 0x0 0. " THALIA_IRQ_ENABLE ,To enable interrupt: Write 0x0: No action Write 0x1: Enable interrupt Read 0x0: Interrupt is disabled Read 0x1: Interrupt is enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "IRQENABLE_CLR_0,Disable Interrupt 0 - Master port." bitfld.long 0x0 0. " INIT_MINTERRUPT_DISABLE ,To disable interrupt: Write 0x0: No action Write 0x1: Disable interrupt Read 0x0: Interrupt is disabled Read 0x1: Interrupt is enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "IRQENABLE_CLR_1,Disable Interrupt 2 - Core interrupt." bitfld.long 0x0 0. " TARGET_SINTERRUPT_DISABLE ,To disable interrupt: Write 0x0: No action Write 0x1: Disable interrupt Read 0x0: Interrupt is disabled Read 0x1: Interrupt is enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "IRQENABLE_CLR_2,Disable Interrupt 2 - Core interrupt." bitfld.long 0x0 0. " THALIA_IRQ_DISABLE ,To disable interrupt: Write 0x0: No action Write 0x1: Disable interrupt Read 0x0: Interrupt is disabled Read 0x1: Interrupt is enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "PAGE_CONFIG,Configure memory pages." bitfld.long 0x0 0.--1. " MEM_PAGE_SIZE ,Defines the page size on internal memory interface: 0x0: 4 KiB 0x1: 2 KiB 0x2: 1 KiB 0x3: 512B" "0,1,2,3" bitfld.long 0x0 2. " MEM_PAGE_CHECK_EN ,To enable page boundary checking: 0x0: Disabled 0x1: Enabled" "0,1" textline " " bitfld.long 0x0 3.--4. " OCP_PAGE_SIZE ,Defines the page size on OCP memory interface: 0x0: 4 KiB 0x1: 2 KiB 0x2: 1 KiB 0x3: 512B" "0,1,2,3" hexmask.long 0x0 5.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " THALIA_INT_BYPASS ,Bypass OCP IPG interrupt logic 0x0: Do not bypass 0x1 Bypass core interrupt to I/O pin; that is, disregard the interrupt enable setting in the IPG register." "0,1" group.byte 0x104++0x3 line.long 0x0 "INTERRUPT_EVENT,Interrupt events" bitfld.long 0x0 0. " INIT_RESP_UNEXPECTED_0 ,Receiving response when not expected: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" bitfld.long 0x0 1. " INIT_RESP_UNUSED_TAG_0 ,Receiving response on an unused OCP TAG: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" textline " " bitfld.long 0x0 2. " INIT_RESP_ERROR_0 ,Receiving error response: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" bitfld.long 0x0 3. " INIT_PAGE_CROSS_ERROR_0 ,Memory page had been crossed during a burst. Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" textline " " bitfld.long 0x0 4. " INIT_READ_TAG_FIFO_OVERRUN_0 ,Read tag FIFO overrun: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" bitfld.long 0x0 5. " INIT_MEM_REQ_FIFO_OVERRUN_0 ,Memory request FIFO overrun; Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8. " INIT_RESP_UNEXPECTED_1 ,Receiving response when not expected: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" textline " " bitfld.long 0x0 9. " INIT_RESP_UNUSED_TAG_1 ,Receiving response on an unused OCP TAG: Write 0x0: Clear the event Write 0x1: Set the event and interrupt if enabled (debug only) Read 0x0: No event pending Read 0x1: Event pending" "0,1" bitfld.long 0x0 10. " INIT_RESP_ERROR_1 ,Receiving error response: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" textline " " bitfld.long 0x0 11. " INIT_PAGE_CROSS_ERROR_1 ,Memory page had been crossed during a burst: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" bitfld.long 0x0 12. " INIT_READ_TAG_FIFO_OVERRUN_1 ,Read tag FIFO overrun: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" textline " " bitfld.long 0x0 13. " INT_MEM_REQ_FIFO_OVERRUN_1 ,Memory request FIFO overrun: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16. " TARGET_RESP_FIFO_FULL ,Response FIFO full: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" bitfld.long 0x0 17. " TARGET_CMD_FIFO_FULL ,Command FIFO full: Write 0x0: Clear the event. Write 0x1: Set the event and interrupt if enabled (debug only). Read 0x0: No event pending Read 0x1: Event pending" "0,1" textline " " bitfld.long 0x0 18. " TARGET_INVALID_OCP_CMD ,Invalid command from OCP: Write 0x0: Clear the event Write 0x1: Set the event and interrupt if enabled (debug only) Read 0x0: No event pending Read 0x1: Event pending" "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "DEBUG_CONFIG,Configuration of debug modes" bitfld.long 0x0 0.--1. " FORCE_TARGET_IDLE ,Forces target idle: 0x0, 0x3: Do not force, normal operation 0x1: Always idle 0x2: Never idle" "0,1,2,3" bitfld.long 0x0 2.--3. " FORCE_INIT_IDLE ,Forces initiator idle: 0x0, 0x3: Do not force, normal operation 0x1: Always idle 0x2: Never idle" "0,1,2,3" textline " " bitfld.long 0x0 4. " FORCE_PASS_DATA ,Forces the initiator to pass data independent of disconnect protocol: 0x0: Do not force, normal operation 0x1: Never fence request to OCP" "0,1" bitfld.long 0x0 5. " SELECT_INT_IDLE ,To select which idle the disconnect protocol should act on: 0x0: Whole SGX idle 0x1: OCP initiator idle" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "DEBUG_STATUS_0,Port0 debug status register" bitfld.long 0x0 0.--1. " TARGET_MCONNECT ,Target MConnect state: 0x0: M_OFF 0x1: M_WAIT 0x2: M_DISC 0x3: M_CON" "0,1,2,3" bitfld.long 0x0 2. " TARGET_SCONNECT ,Target SConnect bit 0 state: 0x0: Disconnect interface 0x1: Connect OCP interface" "0,1" textline " " bitfld.long 0x0 3. " TARGET_SIDLEREQ ,Request the target to go idle: 0 Do not go idle, or go active 1 Go idle" "0,1" bitfld.long 0x0 4.--5. " TARGET_SDISCACK ,Acknowledge the SDiscAck state-machine: 0x0: FUNCT 0x1: TRANS 0x2: Reserved 0x3: IDLE" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " TARGET_SIDLEACK ,Acknowledge the SIdleAck state-machine: 0x0: FUNCT 0x1: SLEEP TRANS 0x2: Reserved 0x3: IDLE" "0,1,2,3" bitfld.long 0x0 8.--9. " INIT_MCONNECT ,Initiator MConnect state: 0x0: M_OFF 0x1: M_WAIT 0x2: M_DISC 0x3: M_CON" "0,1,2,3" textline " " bitfld.long 0x0 10. " INIT_SCONNECT_0 ,Disconnect from slave: 0x0: Disconnect request from slave 0x1: Connect request from slave" "0,1" bitfld.long 0x0 11. " INIT_SCONNECT_1 ,Defines the busy-ness state of the slave: 0x0: Slave is drained 0x1: Slave is loaded" "0,1" textline " " bitfld.long 0x0 12. " INIT_SCONNECT_2 ,Defines whether to wait in M_WAIT state for MConnect FSM: 0x0: Skip M_WAIT state 0x1: Wait in M_WAIT state" "0,1" bitfld.long 0x0 13.--14. " INIT_MDISCACK ,Disconnect status of the OCP interface: 0x0: FUNCT 0x1: TRANS 0x2: Reserved 0x3: IDLE" "0,1,2,3" textline " " bitfld.long 0x0 15. " INIT_MDISCREQ ,Request to disconnect from OCP interface" "0,1" bitfld.long 0x0 16. " INIT_MWAIT ,Status of init_MWait signal" "0,1" textline " " bitfld.long 0x0 17. " INIT_MSTANDBY ,Status of init_MStandby signal" "0,1" bitfld.long 0x0 18.--20. " TARGET_CMD_OUT ,Command received from OCP: 0x0: CMD_WRSYS 0x1: CMD_RDSYS 0x2: CMD_WR_ERROR 0x3: CMD_RD_ERROR 0x4: CMD_CHK_WRADDR_PAGE (not used) 0x5: CMD_CHK_RDADDR_PAGE (not used) 0x6: CMD_TARGET_REG_WRITE 0x7: CMD_TARGET_REG_READ" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 21.--25. " WHICH_TARGET_REGISTER ,Indicates which OCP target registers to read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26. " RESP_ERROR ,Respond to OCP with error, which could be caused by either address misalignment or invalid byte enable." "0,1" textline " " bitfld.long 0x0 27. " CMD_FIFO_FULL ,Target command FIFO full" "0,1" bitfld.long 0x0 28. " RESP_FIFO_FULL ,Target response FIFO full" "0,1" textline " " bitfld.long 0x0 29. " TARGET_IDLE ,Target idle" "0,1" bitfld.long 0x0 30. " CMD_RESP_DEBUG_STATE ,Target response state-machine: 0x0: Send accept 0x1: Wait accept" "0,1" textline " " bitfld.long 0x0 31. " CMD_DEBUG_STATE ,Target command state-machine: 0x0: IDLE 0x1: Accept command" "0,1" group.byte 0x110++0x3 line.long 0x0 "DEBUG_STATUS_1,Port1 debug status register" bitfld.long 0x0 0.--1. " TARGET_MCONNECT ,Target MConnect state: 0x0: M_OFF 0x1: M_WAIT 0x2: M_DISC 0x3: M_CON" "0,1,2,3" bitfld.long 0x0 2. " TARGET_SCONNECT ,Target SConnect bit 0 state: 0x0: Disconnect interface 0x1: Connect OCP interface" "0,1" textline " " bitfld.long 0x0 3. " TARGET_SIDLEREQ ,Request the target to go idle: 0x0: Do not go idle, or go active 0x1: Go idle" "0,1" bitfld.long 0x0 4.--5. " TARGET_SDISCACK ,Acknowledge the SDiscAck state-machine: 0x0: FUNCT 0x1: TRANS 0x2: Reserved 0x3: IDLE" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " TARGET_SIDLEACK ,Acknowledge the SIdleAck state-machine: 0x0: FUNCT 0x1: SLEEP TRANS 0x2: Reserved 0x3: IDLE" "0,1,2,3" bitfld.long 0x0 8.--9. " INIT_MCONNECT ,Initiator MConnect state: 0x0: M_OFF 0x1: M_WAIT 0x2: M_DISC 0x3: M_CON" "0,1,2,3" textline " " bitfld.long 0x0 10. " INIT_SCONNECT_0 ,Disconnect from slave: 0x0: Disconnect request from slave 0x1: Connect request from slave" "0,1" bitfld.long 0x0 11. " INIT_SCONNECT_1 ,Defines the busy-ness state of the slave: 0x0: Slave is drained. 0x1: Slave is loaded." "0,1" textline " " bitfld.long 0x0 12. " INIT_SCONNECT_2 ,Defines whether to wait in M_WAIT state for MConnect FSM: 0x0: Skip M_WAIT state. 0x1: Wait in M_WAIT state." "0,1" bitfld.long 0x0 13.--14. " INIT_MDISCACK ,Disconnect status of the OCP interface: 0x0: FUNCT 0x1: SLEEP TRANS 0x2: Reserved 0x3: IDLE" "0,1,2,3" textline " " bitfld.long 0x0 15. " INIT_MDISCREQ ,Request to disconnect from OCP interface" "0,1" bitfld.long 0x0 16. " INIT_MWAIT ,Status of init_MWait signal" "0,1" textline " " bitfld.long 0x0 17. " INIT_MSTANDBY ,Status of init_MStandby signal" "0,1" bitfld.long 0x0 18.--20. " TARGET_CMD_OUT ,Command received from OCP: 0x0: CMD_WRSYS 0x1: CMD_RDSYS 0x2: CMD_WR_ERROR 0x3: CMD_RD_ERROR 0x4: CMD_CHK_WRADDR_PAGE (not used) 0x5: CMD_CHK_RDADDR_PAGE (not used) 0x6: CMD_TARGET_REG_WRITE 0x7: CMD_TARGET_REG_READ" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 21.--25. " WHICH_TARGET_REGISTER ,Indicates which OCP target registers to read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26. " RESP_ERROR ,Respond to OCP with error, which could be caused by either address misalignment or invalid byte enable." "0,1" textline " " bitfld.long 0x0 27. " CMD_FIFO_FULL ,Target command FIFO full" "0,1" bitfld.long 0x0 28. " RESP_FIFO_FULL ,Target response FIFO full" "0,1" textline " " bitfld.long 0x0 29. " TARGET_IDLE ,Target idle" "0,1" bitfld.long 0x0 30. " CMD_RESP_DEBUG_STATE ,Target response state-machine: 0x0: Send accept 0x1: Wait accept" "0,1" textline " " bitfld.long 0x0 31. " CMD_DEBUG_STATE ,Target command state-machine: 0x0: IDLE 0x1: Accept command" "0,1" width 0x0B tree.end tree "CLK2_STATCOLL1" base ad:0x45002000 width 41. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_EN,L3_STCOL_EN" bitfld.long 0x0 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_SOFTEN,L3_STCOL_SOFTEN" bitfld.long 0x0 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_STCOL_IGNORESUSPEND,L3_STCOL_IGNORESUSPEND" bitfld.long 0x0 0. " IGNORESUSPEND ,Ignore suspend if set to one for suspend mechanism Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_STCOL_TRIGEN,L3_STCOL_TRIGEN" bitfld.long 0x0 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "L3_STCOL_REQEVT,L3_STCOL_REQEVT" bitfld.long 0x0 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "L3_STCOL_RSPEVT,L3_STCOL_RSPEVT" bitfld.long 0x0 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL0,L3_STCOL_EVTMUX_SEL0" bitfld.long 0x0 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL1,L3_STCOL_EVTMUX_SEL1" bitfld.long 0x0 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL2,L3_STCOL_EVTMUX_SEL2" bitfld.long 0x0 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL3,L3_STCOL_EVTMUX_SEL3" bitfld.long 0x0 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL4,L3_STCOL_EVTMUX_SEL4" bitfld.long 0x0 0.--2. " EVTMUX_SEL4 ,The select of the mux 4 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL5,L3_STCOL_EVTMUX_SEL5" bitfld.long 0x0 0.--2. " EVTMUX_SEL5 ,The select of the mux 5 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_STCOL_DUMP_IDENTIFIER,L3_STCOL_DUMP_IDENTIFIER" bitfld.long 0x0 0.--3. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_STCOL_DUMP_COLLECTTIME,L3_STCOL_DUMP_COLLECTTIME" hexmask.long 0x0 0.--31. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." group.byte 0x48++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVADDR,L3_STCOL_DUMP_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "L3_STCOL_DUMP_MSTADDR,L3_STCOL_DUMP_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVOFS,L3_STCOL_DUMP_SLVOFS" hexmask.long 0x0 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.byte 0x54++0x3 line.long 0x0 "L3_STCOL_DUMP_MODE,L3_STCOL_DUMP_MODE" bitfld.long 0x0 0. " DUMP_MODE_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x0 1. " DUMP_MODE_CONDITIONAL ,Define the stat conditional dump, if one a dump will be generated when alarm is trigged Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_STCOL_DUMP_SEND,L3_STCOL_DUMP_SEND" bitfld.long 0x0 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_STCOL_DUMP_DISABLE,L3_STCOL_DUMP_DISABLE" bitfld.long 0x0 0. " DUMP_DISABLE ,If 1, the dump frame will be disabled, but counters still active.This is typically used when counters monitoring is enabled Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_TRIG,L3_STCOL_DUMP_ALARM_TRIG" bitfld.long 0x0 0. " DUMP_ALARM_TRIG ,In Alarm Mode, is used to reset Alarm Type: Take. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MINVAL,L3_STCOL_DUMP_ALARM_MINVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MINVAL ,In Alarm Mode, used to trig an alert if any of counter value is less than AlarmMinVal Type: Control. Reset value: 0x0." group.byte 0x68++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MAXVAL,L3_STCOL_DUMP_ALARM_MAXVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MAXVAL ,In Alarm Mode, used to trig an alert if any of counter value is larger or equal to AlarmMaxVal Type: Control. Reset value: 0x0." group.byte 0x6C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE0,L3_STCOL_DUMP_ALARM_MODE0" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE0 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE1,L3_STCOL_DUMP_ALARM_MODE1" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE1 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE2,L3_STCOL_DUMP_ALARM_MODE2" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE2 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE3,L3_STCOL_DUMP_ALARM_MODE3" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE3 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE4,L3_STCOL_DUMP_ALARM_MODE4" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE4 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE5,L3_STCOL_DUMP_ALARM_MODE5" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE5 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT0,L3_STCOL_DUMP_CNT0" hexmask.long 0x0 0.--31. 1. " DUMP_CNT0 ,Dump counter value Type: Status. Reset value: X." group.byte 0x90++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT1,L3_STCOL_DUMP_CNT1" hexmask.long 0x0 0.--31. 1. " DUMP_CNT1 ,Dump counter value Type: Status. Reset value: X." group.byte 0x94++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT2,L3_STCOL_DUMP_CNT2" hexmask.long 0x0 0.--31. 1. " DUMP_CNT2 ,Dump counter value Type: Status. Reset value: X." group.byte 0x98++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT3,L3_STCOL_DUMP_CNT3" hexmask.long 0x0 0.--31. 1. " DUMP_CNT3 ,Dump counter value Type: Status. Reset value: X." group.byte 0x9C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT4,L3_STCOL_DUMP_CNT4" hexmask.long 0x0 0.--31. 1. " DUMP_CNT4 ,Dump counter value Type: Status. Reset value: X." group.byte 0xA0++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT5,L3_STCOL_DUMP_CNT5" hexmask.long 0x0 0.--31. 1. " DUMP_CNT5 ,Dump counter value Type: Status. Reset value: X." group.byte 0xAC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_0,L3_STCOL_FILTER_i_GLOBALEN_0" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_1,L3_STCOL_FILTER_i_GLOBALEN_1" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x35C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_2,L3_STCOL_FILTER_i_GLOBALEN_2" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4B4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_3,L3_STCOL_FILTER_i_GLOBALEN_3" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x60C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_4,L3_STCOL_FILTER_i_GLOBALEN_4" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x764++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_5,L3_STCOL_FILTER_i_GLOBALEN_5" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_0,L3_STCOL_FILTER_i_ADDRMIN_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_1,L3_STCOL_FILTER_i_ADDRMIN_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_2,L3_STCOL_FILTER_i_ADDRMIN_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_3,L3_STCOL_FILTER_i_ADDRMIN_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x610++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_4,L3_STCOL_FILTER_i_ADDRMIN_4" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x768++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_5,L3_STCOL_FILTER_i_ADDRMIN_5" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_0,L3_STCOL_FILTER_i_ADDRMAX_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_1,L3_STCOL_FILTER_i_ADDRMAX_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_2,L3_STCOL_FILTER_i_ADDRMAX_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_3,L3_STCOL_FILTER_i_ADDRMAX_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x614++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_4,L3_STCOL_FILTER_i_ADDRMAX_4" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x76C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_5,L3_STCOL_FILTER_i_ADDRMAX_5" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_0,L3_STCOL_FILTER_i_ADDREN_0" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_1,L3_STCOL_FILTER_i_ADDREN_1" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_2,L3_STCOL_FILTER_i_ADDREN_2" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_3,L3_STCOL_FILTER_i_ADDREN_3" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x618++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_4,L3_STCOL_FILTER_i_ADDREN_4" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x770++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_5,L3_STCOL_FILTER_i_ADDREN_5" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_0,L3_STCOL_FILTER_i_EN_k_0" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_1,L3_STCOL_FILTER_i_EN_k_1" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x36C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_2,L3_STCOL_FILTER_i_EN_k_2" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_3,L3_STCOL_FILTER_i_EN_k_3" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x61C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_4,L3_STCOL_FILTER_i_EN_k_4" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x774++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_5,L3_STCOL_FILTER_i_EN_k_5" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_0,L3_STCOL_FILTER_i_MASK_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_1,L3_STCOL_FILTER_i_MASK_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x370++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_2,L3_STCOL_FILTER_i_MASK_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_3,L3_STCOL_FILTER_i_MASK_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_4,L3_STCOL_FILTER_i_MASK_m_RD_4" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x778++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_5,L3_STCOL_FILTER_i_MASK_m_RD_5" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_0,L3_STCOL_FILTER_i_MASK_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_1,L3_STCOL_FILTER_i_MASK_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x374++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_2,L3_STCOL_FILTER_i_MASK_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_3,L3_STCOL_FILTER_i_MASK_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x624++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_4,L3_STCOL_FILTER_i_MASK_m_WR_4" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x77C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_5,L3_STCOL_FILTER_i_MASK_m_WR_5" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0,L3_STCOL_FILTER_i_MASK_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1,L3_STCOL_FILTER_i_MASK_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x378++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2,L3_STCOL_FILTER_i_MASK_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3,L3_STCOL_FILTER_i_MASK_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x628++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_4,L3_STCOL_FILTER_i_MASK_m_MSTADDR_4" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x780++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_5,L3_STCOL_FILTER_i_MASK_m_MSTADDR_5" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xCC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0,L3_STCOL_FILTER_i_MASK_m_SLVADDR_0" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1,L3_STCOL_FILTER_i_MASK_m_SLVADDR_1" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x37C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2,L3_STCOL_FILTER_i_MASK_m_SLVADDR_2" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x4D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3,L3_STCOL_FILTER_i_MASK_m_SLVADDR_3" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x62C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_4,L3_STCOL_FILTER_i_MASK_m_SLVADDR_4" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x784++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_5,L3_STCOL_FILTER_i_MASK_m_SLVADDR_5" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_0,L3_STCOL_FILTER_i_MASK_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_1,L3_STCOL_FILTER_i_MASK_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_2,L3_STCOL_FILTER_i_MASK_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_3,L3_STCOL_FILTER_i_MASK_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x630++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_4,L3_STCOL_FILTER_i_MASK_m_ERR_4" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x788++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_5,L3_STCOL_FILTER_i_MASK_m_ERR_5" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x634++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_4,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_4" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x78C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_5,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_5" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x388++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x638++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_4,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_4" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x790++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_5,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_5" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_0,L3_STCOL_FILTER_i_MATCH_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_1,L3_STCOL_FILTER_i_MATCH_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_2,L3_STCOL_FILTER_i_MATCH_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_3,L3_STCOL_FILTER_i_MATCH_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x640++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_4,L3_STCOL_FILTER_i_MATCH_m_RD_4" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x798++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_5,L3_STCOL_FILTER_i_MATCH_m_RD_5" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_0,L3_STCOL_FILTER_i_MATCH_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_1,L3_STCOL_FILTER_i_MATCH_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_2,L3_STCOL_FILTER_i_MATCH_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4EC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_3,L3_STCOL_FILTER_i_MATCH_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x644++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_4,L3_STCOL_FILTER_i_MATCH_m_WR_4" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x79C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_5,L3_STCOL_FILTER_i_MATCH_m_WR_5" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x648++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_4,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_4" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x7A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_5,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_5" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xEC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x244++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x39C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x4F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x64C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_4,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_4" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x7A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_5,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_5" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_0,L3_STCOL_FILTER_i_MATCH_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_1,L3_STCOL_FILTER_i_MATCH_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x3A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_2,L3_STCOL_FILTER_i_MATCH_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_3,L3_STCOL_FILTER_i_MATCH_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x650++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_4,L3_STCOL_FILTER_i_MATCH_m_ERR_4" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x7A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_5,L3_STCOL_FILTER_i_MATCH_m_ERR_5" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xF4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x24C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x654++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_4,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_4" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x7AC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_5,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_5" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xF8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x3A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x658++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_4,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_4" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x7B0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_5,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_5" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0,L3_STCOL_OP_i_THRESHOLD_MINVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x348++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1,L3_STCOL_OP_i_THRESHOLD_MINVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2,L3_STCOL_OP_i_THRESHOLD_MINVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5F8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3,L3_STCOL_OP_i_THRESHOLD_MINVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x750++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_4,L3_STCOL_OP_i_THRESHOLD_MINVAL_4" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8A8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_5,L3_STCOL_OP_i_THRESHOLD_MINVAL_5" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0,L3_STCOL_OP_i_THRESHOLD_MAXVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x34C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1,L3_STCOL_OP_i_THRESHOLD_MAXVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2,L3_STCOL_OP_i_THRESHOLD_MAXVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5FC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3,L3_STCOL_OP_i_THRESHOLD_MAXVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x754++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_4,L3_STCOL_OP_i_THRESHOLD_MAXVAL_4" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8AC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_5,L3_STCOL_OP_i_THRESHOLD_MAXVAL_5" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_0,L3_STCOL_OP_i_EVTINFOSEL_0" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x350++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_1,L3_STCOL_OP_i_EVTINFOSEL_1" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4A8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_2,L3_STCOL_OP_i_EVTINFOSEL_2" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_3,L3_STCOL_OP_i_EVTINFOSEL_3" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x758++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_4,L3_STCOL_OP_i_EVTINFOSEL_4" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x8B0++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_5,L3_STCOL_OP_i_EVTINFOSEL_5" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_0,L3_STCOL_OP_i_SEL_0" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_1,L3_STCOL_OP_i_SEL_1" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_2,L3_STCOL_OP_i_SEL_2" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_3,L3_STCOL_OP_i_SEL_3" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x75C++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_4,L3_STCOL_OP_i_SEL_4" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x8B4++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_5,L3_STCOL_OP_i_SEL_5" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK2_STATCOLL0" base ad:0x45001000 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_EN,L3_STCOL_EN" bitfld.long 0x0 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_SOFTEN,L3_STCOL_SOFTEN" bitfld.long 0x0 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_STCOL_IGNORESUSPEND,L3_STCOL_IGNORESUSPEND" bitfld.long 0x0 0. " IGNORESUSPEND ,Ignore suspend if set to one for suspend mechanism Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_STCOL_TRIGEN,L3_STCOL_TRIGEN" bitfld.long 0x0 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "L3_STCOL_REQEVT,L3_STCOL_REQEVT" bitfld.long 0x0 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "L3_STCOL_RSPEVT,L3_STCOL_RSPEVT" bitfld.long 0x0 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL0,L3_STCOL_EVTMUX_SEL0" bitfld.long 0x0 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL1,L3_STCOL_EVTMUX_SEL1" bitfld.long 0x0 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL2,L3_STCOL_EVTMUX_SEL2" bitfld.long 0x0 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL3,L3_STCOL_EVTMUX_SEL3" bitfld.long 0x0 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL4,L3_STCOL_EVTMUX_SEL4" bitfld.long 0x0 0.--2. " EVTMUX_SEL4 ,The select of the mux 4 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL5,L3_STCOL_EVTMUX_SEL5" bitfld.long 0x0 0.--2. " EVTMUX_SEL5 ,The select of the mux 5 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL6,L3_STCOL_EVTMUX_SEL6" bitfld.long 0x0 0.--2. " EVTMUX_SEL6 ,The select of the mux 6 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL7,L3_STCOL_EVTMUX_SEL7" bitfld.long 0x0 0.--2. " EVTMUX_SEL7 ,The select of the mux 7 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_STCOL_DUMP_IDENTIFIER,L3_STCOL_DUMP_IDENTIFIER" bitfld.long 0x0 0.--3. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_STCOL_DUMP_COLLECTTIME,L3_STCOL_DUMP_COLLECTTIME" hexmask.long 0x0 0.--31. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." group.byte 0x48++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVADDR,L3_STCOL_DUMP_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "L3_STCOL_DUMP_MSTADDR,L3_STCOL_DUMP_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVOFS,L3_STCOL_DUMP_SLVOFS" hexmask.long 0x0 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.byte 0x54++0x3 line.long 0x0 "L3_STCOL_DUMP_MODE,L3_STCOL_DUMP_MODE" bitfld.long 0x0 0. " DUMP_MODE_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x0 1. " DUMP_MODE_CONDITIONAL ,Define the stat conditional dump, if one a dump will be generated when alarm is trigged Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_STCOL_DUMP_SEND,L3_STCOL_DUMP_SEND" bitfld.long 0x0 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_STCOL_DUMP_DISABLE,L3_STCOL_DUMP_DISABLE" bitfld.long 0x0 0. " DUMP_DISABLE ,If 1, the dump frame will be disabled, but counters still active.This is typically used when counters monitoring is enabled Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_TRIG,L3_STCOL_DUMP_ALARM_TRIG" bitfld.long 0x0 0. " DUMP_ALARM_TRIG ,In Alarm Mode, is used to reset Alarm Type: Take. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MINVAL,L3_STCOL_DUMP_ALARM_MINVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MINVAL ,In Alarm Mode, used to trig an alert if any of counter value is less than AlarmMinVal Type: Control. Reset value: 0x0." group.byte 0x68++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MAXVAL,L3_STCOL_DUMP_ALARM_MAXVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MAXVAL ,In Alarm Mode, used to trig an alert if any of counter value is larger or equal to AlarmMaxVal Type: Control. Reset value: 0x0." group.byte 0x6C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE0,L3_STCOL_DUMP_ALARM_MODE0" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE0 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE1,L3_STCOL_DUMP_ALARM_MODE1" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE1 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE2,L3_STCOL_DUMP_ALARM_MODE2" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE2 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE3,L3_STCOL_DUMP_ALARM_MODE3" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE3 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE4,L3_STCOL_DUMP_ALARM_MODE4" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE4 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE5,L3_STCOL_DUMP_ALARM_MODE5" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE5 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE6,L3_STCOL_DUMP_ALARM_MODE6" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE6 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE7,L3_STCOL_DUMP_ALARM_MODE7" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE7 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT0,L3_STCOL_DUMP_CNT0" hexmask.long 0x0 0.--31. 1. " DUMP_CNT0 ,Dump counter value Type: Status. Reset value: X." group.byte 0x90++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT1,L3_STCOL_DUMP_CNT1" hexmask.long 0x0 0.--31. 1. " DUMP_CNT1 ,Dump counter value Type: Status. Reset value: X." group.byte 0x94++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT2,L3_STCOL_DUMP_CNT2" hexmask.long 0x0 0.--31. 1. " DUMP_CNT2 ,Dump counter value Type: Status. Reset value: X." group.byte 0x98++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT3,L3_STCOL_DUMP_CNT3" hexmask.long 0x0 0.--31. 1. " DUMP_CNT3 ,Dump counter value Type: Status. Reset value: X." group.byte 0x9C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT4,L3_STCOL_DUMP_CNT4" hexmask.long 0x0 0.--31. 1. " DUMP_CNT4 ,Dump counter value Type: Status. Reset value: X." group.byte 0xA0++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT5,L3_STCOL_DUMP_CNT5" hexmask.long 0x0 0.--31. 1. " DUMP_CNT5 ,Dump counter value Type: Status. Reset value: X." group.byte 0xA4++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT6,L3_STCOL_DUMP_CNT6" hexmask.long 0x0 0.--31. 1. " DUMP_CNT6 ,Dump counter value Type: Status. Reset value: X." group.byte 0xA8++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT7,L3_STCOL_DUMP_CNT7" hexmask.long 0x0 0.--31. 1. " DUMP_CNT7 ,Dump counter value Type: Status. Reset value: X." group.byte 0xAC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_0,L3_STCOL_FILTER_i_GLOBALEN_0" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_1,L3_STCOL_FILTER_i_GLOBALEN_1" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x35C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_2,L3_STCOL_FILTER_i_GLOBALEN_2" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4B4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_3,L3_STCOL_FILTER_i_GLOBALEN_3" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x60C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_4,L3_STCOL_FILTER_i_GLOBALEN_4" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x764++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_5,L3_STCOL_FILTER_i_GLOBALEN_5" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_6,L3_STCOL_FILTER_i_GLOBALEN_6" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA14++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_7,L3_STCOL_FILTER_i_GLOBALEN_7" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_0,L3_STCOL_FILTER_i_ADDRMIN_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_1,L3_STCOL_FILTER_i_ADDRMIN_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_2,L3_STCOL_FILTER_i_ADDRMIN_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_3,L3_STCOL_FILTER_i_ADDRMIN_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x610++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_4,L3_STCOL_FILTER_i_ADDRMIN_4" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x768++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_5,L3_STCOL_FILTER_i_ADDRMIN_5" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x8C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_6,L3_STCOL_FILTER_i_ADDRMIN_6" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xA18++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_7,L3_STCOL_FILTER_i_ADDRMIN_7" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_0,L3_STCOL_FILTER_i_ADDRMAX_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_1,L3_STCOL_FILTER_i_ADDRMAX_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_2,L3_STCOL_FILTER_i_ADDRMAX_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_3,L3_STCOL_FILTER_i_ADDRMAX_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x614++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_4,L3_STCOL_FILTER_i_ADDRMAX_4" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x76C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_5,L3_STCOL_FILTER_i_ADDRMAX_5" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x8C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_6,L3_STCOL_FILTER_i_ADDRMAX_6" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xA1C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_7,L3_STCOL_FILTER_i_ADDRMAX_7" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_0,L3_STCOL_FILTER_i_ADDREN_0" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_1,L3_STCOL_FILTER_i_ADDREN_1" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_2,L3_STCOL_FILTER_i_ADDREN_2" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_3,L3_STCOL_FILTER_i_ADDREN_3" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x618++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_4,L3_STCOL_FILTER_i_ADDREN_4" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x770++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_5,L3_STCOL_FILTER_i_ADDREN_5" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_6,L3_STCOL_FILTER_i_ADDREN_6" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xA20++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_7,L3_STCOL_FILTER_i_ADDREN_7" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_0,L3_STCOL_FILTER_i_EN_k_0" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_1,L3_STCOL_FILTER_i_EN_k_1" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x36C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_2,L3_STCOL_FILTER_i_EN_k_2" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_3,L3_STCOL_FILTER_i_EN_k_3" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x61C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_4,L3_STCOL_FILTER_i_EN_k_4" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x774++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_5,L3_STCOL_FILTER_i_EN_k_5" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_6,L3_STCOL_FILTER_i_EN_k_6" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA24++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_7,L3_STCOL_FILTER_i_EN_k_7" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_0,L3_STCOL_FILTER_i_MASK_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_1,L3_STCOL_FILTER_i_MASK_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x370++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_2,L3_STCOL_FILTER_i_MASK_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_3,L3_STCOL_FILTER_i_MASK_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_4,L3_STCOL_FILTER_i_MASK_m_RD_4" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x778++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_5,L3_STCOL_FILTER_i_MASK_m_RD_5" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_6,L3_STCOL_FILTER_i_MASK_m_RD_6" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA28++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_7,L3_STCOL_FILTER_i_MASK_m_RD_7" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_0,L3_STCOL_FILTER_i_MASK_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_1,L3_STCOL_FILTER_i_MASK_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x374++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_2,L3_STCOL_FILTER_i_MASK_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_3,L3_STCOL_FILTER_i_MASK_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x624++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_4,L3_STCOL_FILTER_i_MASK_m_WR_4" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x77C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_5,L3_STCOL_FILTER_i_MASK_m_WR_5" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_6,L3_STCOL_FILTER_i_MASK_m_WR_6" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA2C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_7,L3_STCOL_FILTER_i_MASK_m_WR_7" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0,L3_STCOL_FILTER_i_MASK_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1,L3_STCOL_FILTER_i_MASK_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x378++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2,L3_STCOL_FILTER_i_MASK_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3,L3_STCOL_FILTER_i_MASK_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x628++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_4,L3_STCOL_FILTER_i_MASK_m_MSTADDR_4" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x780++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_5,L3_STCOL_FILTER_i_MASK_m_MSTADDR_5" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_6,L3_STCOL_FILTER_i_MASK_m_MSTADDR_6" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xA30++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_7,L3_STCOL_FILTER_i_MASK_m_MSTADDR_7" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xD0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_0,L3_STCOL_FILTER_i_MASK_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_1,L3_STCOL_FILTER_i_MASK_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_2,L3_STCOL_FILTER_i_MASK_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_3,L3_STCOL_FILTER_i_MASK_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x630++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_4,L3_STCOL_FILTER_i_MASK_m_ERR_4" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x788++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_5,L3_STCOL_FILTER_i_MASK_m_ERR_5" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_6,L3_STCOL_FILTER_i_MASK_m_ERR_6" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA38++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_7,L3_STCOL_FILTER_i_MASK_m_ERR_7" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_USERINFO_0,L3_STCOL_FILTER_i_MASK_m_USERINFO_0" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MASK_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x22C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_USERINFO_1,L3_STCOL_FILTER_i_MASK_m_USERINFO_1" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MASK_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_USERINFO_2,L3_STCOL_FILTER_i_MASK_m_USERINFO_2" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MASK_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x4DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_USERINFO_3,L3_STCOL_FILTER_i_MASK_m_USERINFO_3" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MASK_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x634++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_USERINFO_4,L3_STCOL_FILTER_i_MASK_m_USERINFO_4" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MASK_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x78C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_USERINFO_5,L3_STCOL_FILTER_i_MASK_m_USERINFO_5" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MASK_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x8E4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_USERINFO_6,L3_STCOL_FILTER_i_MASK_m_USERINFO_6" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MASK_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xA3C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_USERINFO_7,L3_STCOL_FILTER_i_MASK_m_USERINFO_7" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MASK_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xE0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_0,L3_STCOL_FILTER_i_MATCH_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_1,L3_STCOL_FILTER_i_MATCH_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_2,L3_STCOL_FILTER_i_MATCH_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_3,L3_STCOL_FILTER_i_MATCH_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x640++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_4,L3_STCOL_FILTER_i_MATCH_m_RD_4" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x798++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_5,L3_STCOL_FILTER_i_MATCH_m_RD_5" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_6,L3_STCOL_FILTER_i_MATCH_m_RD_6" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA48++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_7,L3_STCOL_FILTER_i_MATCH_m_RD_7" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_0,L3_STCOL_FILTER_i_MATCH_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_1,L3_STCOL_FILTER_i_MATCH_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_2,L3_STCOL_FILTER_i_MATCH_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4EC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_3,L3_STCOL_FILTER_i_MATCH_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x644++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_4,L3_STCOL_FILTER_i_MATCH_m_WR_4" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x79C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_5,L3_STCOL_FILTER_i_MATCH_m_WR_5" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_6,L3_STCOL_FILTER_i_MATCH_m_WR_6" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA4C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_7,L3_STCOL_FILTER_i_MATCH_m_WR_7" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x648++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_4,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_4" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x7A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_5,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_5" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_6,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_6" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xA50++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_7,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_7" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xF0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_0,L3_STCOL_FILTER_i_MATCH_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_1,L3_STCOL_FILTER_i_MATCH_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x3A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_2,L3_STCOL_FILTER_i_MATCH_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_3,L3_STCOL_FILTER_i_MATCH_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x650++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_4,L3_STCOL_FILTER_i_MATCH_m_ERR_4" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x7A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_5,L3_STCOL_FILTER_i_MATCH_m_ERR_5" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x900++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_6,L3_STCOL_FILTER_i_MATCH_m_ERR_6" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA58++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_7,L3_STCOL_FILTER_i_MATCH_m_ERR_7" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xF4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_0,L3_STCOL_FILTER_i_MATCH_m_USERINFO_0" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MATCH_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x24C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_1,L3_STCOL_FILTER_i_MATCH_m_USERINFO_1" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MATCH_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x3A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_2,L3_STCOL_FILTER_i_MATCH_m_USERINFO_2" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MATCH_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x4FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_3,L3_STCOL_FILTER_i_MATCH_m_USERINFO_3" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MATCH_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x654++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_4,L3_STCOL_FILTER_i_MATCH_m_USERINFO_4" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MATCH_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x7AC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_5,L3_STCOL_FILTER_i_MATCH_m_USERINFO_5" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MATCH_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x904++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_6,L3_STCOL_FILTER_i_MATCH_m_USERINFO_6" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MATCH_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xA5C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_USERINFO_7,L3_STCOL_FILTER_i_MATCH_m_USERINFO_7" hexmask.long.tbyte 0x0 0.--17. 1. " FILTER_i_MATCH_m_USERINFO ,Mask/Match of UserInfo Type: Control. Reset value: 0x0." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x1F0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0,L3_STCOL_OP_i_THRESHOLD_MINVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x348++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1,L3_STCOL_OP_i_THRESHOLD_MINVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2,L3_STCOL_OP_i_THRESHOLD_MINVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5F8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3,L3_STCOL_OP_i_THRESHOLD_MINVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x750++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_4,L3_STCOL_OP_i_THRESHOLD_MINVAL_4" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8A8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_5,L3_STCOL_OP_i_THRESHOLD_MINVAL_5" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA00++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_6,L3_STCOL_OP_i_THRESHOLD_MINVAL_6" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB58++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_7,L3_STCOL_OP_i_THRESHOLD_MINVAL_7" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0,L3_STCOL_OP_i_THRESHOLD_MAXVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x34C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1,L3_STCOL_OP_i_THRESHOLD_MAXVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2,L3_STCOL_OP_i_THRESHOLD_MAXVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5FC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3,L3_STCOL_OP_i_THRESHOLD_MAXVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x754++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_4,L3_STCOL_OP_i_THRESHOLD_MAXVAL_4" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8AC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_5,L3_STCOL_OP_i_THRESHOLD_MAXVAL_5" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA04++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_6,L3_STCOL_OP_i_THRESHOLD_MAXVAL_6" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB5C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_7,L3_STCOL_OP_i_THRESHOLD_MAXVAL_7" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_0,L3_STCOL_OP_i_EVTINFOSEL_0" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x350++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_1,L3_STCOL_OP_i_EVTINFOSEL_1" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4A8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_2,L3_STCOL_OP_i_EVTINFOSEL_2" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_3,L3_STCOL_OP_i_EVTINFOSEL_3" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x758++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_4,L3_STCOL_OP_i_EVTINFOSEL_4" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x8B0++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_5,L3_STCOL_OP_i_EVTINFOSEL_5" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0xA08++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_6,L3_STCOL_OP_i_EVTINFOSEL_6" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0xB60++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_7,L3_STCOL_OP_i_EVTINFOSEL_7" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_0,L3_STCOL_OP_i_SEL_0" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_1,L3_STCOL_OP_i_SEL_1" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_2,L3_STCOL_OP_i_SEL_2" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_3,L3_STCOL_OP_i_SEL_3" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x75C++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_4,L3_STCOL_OP_i_SEL_4" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x8B4++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_5,L3_STCOL_OP_i_SEL_5" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0C++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_6,L3_STCOL_OP_i_SEL_6" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xB64++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_7,L3_STCOL_OP_i_SEL_7" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK2_STATCOLL3" base ad:0x45004000 width 41. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_EN,L3_STCOL_EN" bitfld.long 0x0 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_SOFTEN,L3_STCOL_SOFTEN" bitfld.long 0x0 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_STCOL_IGNORESUSPEND,L3_STCOL_IGNORESUSPEND" bitfld.long 0x0 0. " IGNORESUSPEND ,Ignore suspend if set to one for suspend mechanism Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_STCOL_TRIGEN,L3_STCOL_TRIGEN" bitfld.long 0x0 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "L3_STCOL_REQEVT,L3_STCOL_REQEVT" bitfld.long 0x0 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "L3_STCOL_RSPEVT,L3_STCOL_RSPEVT" bitfld.long 0x0 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL0,L3_STCOL_EVTMUX_SEL0" bitfld.long 0x0 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL1,L3_STCOL_EVTMUX_SEL1" bitfld.long 0x0 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL2,L3_STCOL_EVTMUX_SEL2" bitfld.long 0x0 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL3,L3_STCOL_EVTMUX_SEL3" bitfld.long 0x0 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL4,L3_STCOL_EVTMUX_SEL4" bitfld.long 0x0 0.--2. " EVTMUX_SEL4 ,The select of the mux 4 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL5,L3_STCOL_EVTMUX_SEL5" bitfld.long 0x0 0.--2. " EVTMUX_SEL5 ,The select of the mux 5 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL6,L3_STCOL_EVTMUX_SEL6" bitfld.long 0x0 0.--2. " EVTMUX_SEL6 ,The select of the mux 6 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL7,L3_STCOL_EVTMUX_SEL7" bitfld.long 0x0 0.--2. " EVTMUX_SEL7 ,The select of the mux 7 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_STCOL_DUMP_IDENTIFIER,L3_STCOL_DUMP_IDENTIFIER" bitfld.long 0x0 0.--3. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_STCOL_DUMP_COLLECTTIME,L3_STCOL_DUMP_COLLECTTIME" hexmask.long 0x0 0.--31. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." group.byte 0x48++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVADDR,L3_STCOL_DUMP_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "L3_STCOL_DUMP_MSTADDR,L3_STCOL_DUMP_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVOFS,L3_STCOL_DUMP_SLVOFS" hexmask.long 0x0 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.byte 0x54++0x3 line.long 0x0 "L3_STCOL_DUMP_MODE,L3_STCOL_DUMP_MODE" bitfld.long 0x0 0. " DUMP_MODE_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x0 1. " DUMP_MODE_CONDITIONAL ,Define the stat conditional dump, if one a dump will be generated when alarm is trigged Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_STCOL_DUMP_SEND,L3_STCOL_DUMP_SEND" bitfld.long 0x0 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_STCOL_DUMP_DISABLE,L3_STCOL_DUMP_DISABLE" bitfld.long 0x0 0. " DUMP_DISABLE ,If 1, the dump frame will be disabled, but counters still active.This is typically used when counters monitoring is enabled Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_TRIG,L3_STCOL_DUMP_ALARM_TRIG" bitfld.long 0x0 0. " DUMP_ALARM_TRIG ,In Alarm Mode, is used to reset Alarm Type: Take. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MINVAL,L3_STCOL_DUMP_ALARM_MINVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MINVAL ,In Alarm Mode, used to trig an alert if any of counter value is less than AlarmMinVal Type: Control. Reset value: 0x0." group.byte 0x68++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MAXVAL,L3_STCOL_DUMP_ALARM_MAXVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MAXVAL ,In Alarm Mode, used to trig an alert if any of counter value is larger or equal to AlarmMaxVal Type: Control. Reset value: 0x0." group.byte 0x6C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE0,L3_STCOL_DUMP_ALARM_MODE0" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE0 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE1,L3_STCOL_DUMP_ALARM_MODE1" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE1 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE2,L3_STCOL_DUMP_ALARM_MODE2" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE2 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE3,L3_STCOL_DUMP_ALARM_MODE3" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE3 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE4,L3_STCOL_DUMP_ALARM_MODE4" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE4 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE5,L3_STCOL_DUMP_ALARM_MODE5" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE5 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE6,L3_STCOL_DUMP_ALARM_MODE6" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE6 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE7,L3_STCOL_DUMP_ALARM_MODE7" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE7 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT0,L3_STCOL_DUMP_CNT0" hexmask.long 0x0 0.--31. 1. " DUMP_CNT0 ,Dump counter value Type: Status. Reset value: X." group.byte 0x90++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT1,L3_STCOL_DUMP_CNT1" hexmask.long 0x0 0.--31. 1. " DUMP_CNT1 ,Dump counter value Type: Status. Reset value: X." group.byte 0x94++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT2,L3_STCOL_DUMP_CNT2" hexmask.long 0x0 0.--31. 1. " DUMP_CNT2 ,Dump counter value Type: Status. Reset value: X." group.byte 0x98++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT3,L3_STCOL_DUMP_CNT3" hexmask.long 0x0 0.--31. 1. " DUMP_CNT3 ,Dump counter value Type: Status. Reset value: X." group.byte 0x9C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT4,L3_STCOL_DUMP_CNT4" hexmask.long 0x0 0.--31. 1. " DUMP_CNT4 ,Dump counter value Type: Status. Reset value: X." group.byte 0xA0++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT5,L3_STCOL_DUMP_CNT5" hexmask.long 0x0 0.--31. 1. " DUMP_CNT5 ,Dump counter value Type: Status. Reset value: X." group.byte 0xA4++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT6,L3_STCOL_DUMP_CNT6" hexmask.long 0x0 0.--31. 1. " DUMP_CNT6 ,Dump counter value Type: Status. Reset value: X." group.byte 0xA8++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT7,L3_STCOL_DUMP_CNT7" hexmask.long 0x0 0.--31. 1. " DUMP_CNT7 ,Dump counter value Type: Status. Reset value: X." group.byte 0xAC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_0,L3_STCOL_FILTER_i_GLOBALEN_0" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_1,L3_STCOL_FILTER_i_GLOBALEN_1" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x35C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_2,L3_STCOL_FILTER_i_GLOBALEN_2" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4B4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_3,L3_STCOL_FILTER_i_GLOBALEN_3" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x60C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_4,L3_STCOL_FILTER_i_GLOBALEN_4" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x764++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_5,L3_STCOL_FILTER_i_GLOBALEN_5" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_6,L3_STCOL_FILTER_i_GLOBALEN_6" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA14++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_7,L3_STCOL_FILTER_i_GLOBALEN_7" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_0,L3_STCOL_FILTER_i_ADDRMIN_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_1,L3_STCOL_FILTER_i_ADDRMIN_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_2,L3_STCOL_FILTER_i_ADDRMIN_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_3,L3_STCOL_FILTER_i_ADDRMIN_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x610++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_4,L3_STCOL_FILTER_i_ADDRMIN_4" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x768++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_5,L3_STCOL_FILTER_i_ADDRMIN_5" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x8C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_6,L3_STCOL_FILTER_i_ADDRMIN_6" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xA18++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_7,L3_STCOL_FILTER_i_ADDRMIN_7" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_0,L3_STCOL_FILTER_i_ADDRMAX_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_1,L3_STCOL_FILTER_i_ADDRMAX_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_2,L3_STCOL_FILTER_i_ADDRMAX_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_3,L3_STCOL_FILTER_i_ADDRMAX_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x614++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_4,L3_STCOL_FILTER_i_ADDRMAX_4" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x76C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_5,L3_STCOL_FILTER_i_ADDRMAX_5" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x8C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_6,L3_STCOL_FILTER_i_ADDRMAX_6" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xA1C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_7,L3_STCOL_FILTER_i_ADDRMAX_7" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_0,L3_STCOL_FILTER_i_ADDREN_0" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_1,L3_STCOL_FILTER_i_ADDREN_1" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_2,L3_STCOL_FILTER_i_ADDREN_2" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_3,L3_STCOL_FILTER_i_ADDREN_3" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x618++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_4,L3_STCOL_FILTER_i_ADDREN_4" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x770++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_5,L3_STCOL_FILTER_i_ADDREN_5" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_6,L3_STCOL_FILTER_i_ADDREN_6" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xA20++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_7,L3_STCOL_FILTER_i_ADDREN_7" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_0,L3_STCOL_FILTER_i_EN_k_0" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_1,L3_STCOL_FILTER_i_EN_k_1" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x36C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_2,L3_STCOL_FILTER_i_EN_k_2" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_3,L3_STCOL_FILTER_i_EN_k_3" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x61C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_4,L3_STCOL_FILTER_i_EN_k_4" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x774++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_5,L3_STCOL_FILTER_i_EN_k_5" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_6,L3_STCOL_FILTER_i_EN_k_6" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA24++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_7,L3_STCOL_FILTER_i_EN_k_7" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_0,L3_STCOL_FILTER_i_MASK_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_1,L3_STCOL_FILTER_i_MASK_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x370++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_2,L3_STCOL_FILTER_i_MASK_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_3,L3_STCOL_FILTER_i_MASK_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_4,L3_STCOL_FILTER_i_MASK_m_RD_4" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x778++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_5,L3_STCOL_FILTER_i_MASK_m_RD_5" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_6,L3_STCOL_FILTER_i_MASK_m_RD_6" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA28++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_7,L3_STCOL_FILTER_i_MASK_m_RD_7" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_0,L3_STCOL_FILTER_i_MASK_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_1,L3_STCOL_FILTER_i_MASK_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x374++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_2,L3_STCOL_FILTER_i_MASK_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_3,L3_STCOL_FILTER_i_MASK_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x624++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_4,L3_STCOL_FILTER_i_MASK_m_WR_4" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x77C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_5,L3_STCOL_FILTER_i_MASK_m_WR_5" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_6,L3_STCOL_FILTER_i_MASK_m_WR_6" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA2C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_7,L3_STCOL_FILTER_i_MASK_m_WR_7" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0,L3_STCOL_FILTER_i_MASK_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1,L3_STCOL_FILTER_i_MASK_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x378++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2,L3_STCOL_FILTER_i_MASK_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3,L3_STCOL_FILTER_i_MASK_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x628++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_4,L3_STCOL_FILTER_i_MASK_m_MSTADDR_4" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x780++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_5,L3_STCOL_FILTER_i_MASK_m_MSTADDR_5" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_6,L3_STCOL_FILTER_i_MASK_m_MSTADDR_6" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xA30++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_7,L3_STCOL_FILTER_i_MASK_m_MSTADDR_7" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xCC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0,L3_STCOL_FILTER_i_MASK_m_SLVADDR_0" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1,L3_STCOL_FILTER_i_MASK_m_SLVADDR_1" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x37C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2,L3_STCOL_FILTER_i_MASK_m_SLVADDR_2" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x4D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3,L3_STCOL_FILTER_i_MASK_m_SLVADDR_3" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x62C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_4,L3_STCOL_FILTER_i_MASK_m_SLVADDR_4" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x784++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_5,L3_STCOL_FILTER_i_MASK_m_SLVADDR_5" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x8DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_6,L3_STCOL_FILTER_i_MASK_m_SLVADDR_6" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xA34++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_7,L3_STCOL_FILTER_i_MASK_m_SLVADDR_7" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_0,L3_STCOL_FILTER_i_MASK_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_1,L3_STCOL_FILTER_i_MASK_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_2,L3_STCOL_FILTER_i_MASK_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_3,L3_STCOL_FILTER_i_MASK_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x630++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_4,L3_STCOL_FILTER_i_MASK_m_ERR_4" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x788++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_5,L3_STCOL_FILTER_i_MASK_m_ERR_5" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_6,L3_STCOL_FILTER_i_MASK_m_ERR_6" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA38++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_7,L3_STCOL_FILTER_i_MASK_m_ERR_7" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x634++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_4,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_4" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x78C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_5,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_5" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x8E4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_6,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_6" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xA3C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_7,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_7" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x388++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x638++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_4,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_4" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x790++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_5,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_5" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x8E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_6,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_6" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xA40++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_7,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_7" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_0,L3_STCOL_FILTER_i_MATCH_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_1,L3_STCOL_FILTER_i_MATCH_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_2,L3_STCOL_FILTER_i_MATCH_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_3,L3_STCOL_FILTER_i_MATCH_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x640++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_4,L3_STCOL_FILTER_i_MATCH_m_RD_4" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x798++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_5,L3_STCOL_FILTER_i_MATCH_m_RD_5" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_6,L3_STCOL_FILTER_i_MATCH_m_RD_6" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA48++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_7,L3_STCOL_FILTER_i_MATCH_m_RD_7" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_0,L3_STCOL_FILTER_i_MATCH_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_1,L3_STCOL_FILTER_i_MATCH_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_2,L3_STCOL_FILTER_i_MATCH_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4EC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_3,L3_STCOL_FILTER_i_MATCH_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x644++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_4,L3_STCOL_FILTER_i_MATCH_m_WR_4" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x79C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_5,L3_STCOL_FILTER_i_MATCH_m_WR_5" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_6,L3_STCOL_FILTER_i_MATCH_m_WR_6" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA4C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_7,L3_STCOL_FILTER_i_MATCH_m_WR_7" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x648++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_4,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_4" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x7A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_5,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_5" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_6,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_6" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xA50++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_7,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_7" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xEC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x244++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x39C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x4F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x64C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_4,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_4" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x7A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_5,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_5" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x8FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_6,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_6" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xA54++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_7,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_7" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_0,L3_STCOL_FILTER_i_MATCH_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_1,L3_STCOL_FILTER_i_MATCH_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x3A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_2,L3_STCOL_FILTER_i_MATCH_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_3,L3_STCOL_FILTER_i_MATCH_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x650++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_4,L3_STCOL_FILTER_i_MATCH_m_ERR_4" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x7A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_5,L3_STCOL_FILTER_i_MATCH_m_ERR_5" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x900++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_6,L3_STCOL_FILTER_i_MATCH_m_ERR_6" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA58++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_7,L3_STCOL_FILTER_i_MATCH_m_ERR_7" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xF4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x24C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x654++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_4,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_4" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x7AC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_5,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_5" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x904++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_6,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_6" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xA5C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_7,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_7" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xF8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x3A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x658++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_4,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_4" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x7B0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_5,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_5" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x908++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_6,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_6" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xA60++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_7,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_7" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0,L3_STCOL_OP_i_THRESHOLD_MINVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x348++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1,L3_STCOL_OP_i_THRESHOLD_MINVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2,L3_STCOL_OP_i_THRESHOLD_MINVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5F8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3,L3_STCOL_OP_i_THRESHOLD_MINVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x750++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_4,L3_STCOL_OP_i_THRESHOLD_MINVAL_4" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8A8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_5,L3_STCOL_OP_i_THRESHOLD_MINVAL_5" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA00++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_6,L3_STCOL_OP_i_THRESHOLD_MINVAL_6" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB58++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_7,L3_STCOL_OP_i_THRESHOLD_MINVAL_7" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0,L3_STCOL_OP_i_THRESHOLD_MAXVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x34C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1,L3_STCOL_OP_i_THRESHOLD_MAXVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2,L3_STCOL_OP_i_THRESHOLD_MAXVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5FC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3,L3_STCOL_OP_i_THRESHOLD_MAXVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x754++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_4,L3_STCOL_OP_i_THRESHOLD_MAXVAL_4" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8AC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_5,L3_STCOL_OP_i_THRESHOLD_MAXVAL_5" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA04++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_6,L3_STCOL_OP_i_THRESHOLD_MAXVAL_6" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB5C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_7,L3_STCOL_OP_i_THRESHOLD_MAXVAL_7" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_0,L3_STCOL_OP_i_EVTINFOSEL_0" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x350++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_1,L3_STCOL_OP_i_EVTINFOSEL_1" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4A8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_2,L3_STCOL_OP_i_EVTINFOSEL_2" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_3,L3_STCOL_OP_i_EVTINFOSEL_3" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x758++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_4,L3_STCOL_OP_i_EVTINFOSEL_4" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x8B0++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_5,L3_STCOL_OP_i_EVTINFOSEL_5" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0xA08++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_6,L3_STCOL_OP_i_EVTINFOSEL_6" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0xB60++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_7,L3_STCOL_OP_i_EVTINFOSEL_7" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_0,L3_STCOL_OP_i_SEL_0" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_1,L3_STCOL_OP_i_SEL_1" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_2,L3_STCOL_OP_i_SEL_2" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_3,L3_STCOL_OP_i_SEL_3" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x75C++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_4,L3_STCOL_OP_i_SEL_4" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x8B4++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_5,L3_STCOL_OP_i_SEL_5" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0C++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_6,L3_STCOL_OP_i_SEL_6" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xB64++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_7,L3_STCOL_OP_i_SEL_7" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK2_STATCOLL2" base ad:0x45003000 width 41. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_EN,L3_STCOL_EN" bitfld.long 0x0 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_SOFTEN,L3_STCOL_SOFTEN" bitfld.long 0x0 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_STCOL_IGNORESUSPEND,L3_STCOL_IGNORESUSPEND" bitfld.long 0x0 0. " IGNORESUSPEND ,Ignore suspend if set to one for suspend mechanism Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_STCOL_TRIGEN,L3_STCOL_TRIGEN" bitfld.long 0x0 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "L3_STCOL_REQEVT,L3_STCOL_REQEVT" bitfld.long 0x0 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "L3_STCOL_RSPEVT,L3_STCOL_RSPEVT" bitfld.long 0x0 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL0,L3_STCOL_EVTMUX_SEL0" bitfld.long 0x0 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL1,L3_STCOL_EVTMUX_SEL1" bitfld.long 0x0 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL2,L3_STCOL_EVTMUX_SEL2" bitfld.long 0x0 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL3,L3_STCOL_EVTMUX_SEL3" bitfld.long 0x0 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_STCOL_DUMP_IDENTIFIER,L3_STCOL_DUMP_IDENTIFIER" bitfld.long 0x0 0.--3. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_STCOL_DUMP_COLLECTTIME,L3_STCOL_DUMP_COLLECTTIME" hexmask.long 0x0 0.--31. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." group.byte 0x48++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVADDR,L3_STCOL_DUMP_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "L3_STCOL_DUMP_MSTADDR,L3_STCOL_DUMP_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVOFS,L3_STCOL_DUMP_SLVOFS" hexmask.long 0x0 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.byte 0x54++0x3 line.long 0x0 "L3_STCOL_DUMP_MODE,L3_STCOL_DUMP_MODE" bitfld.long 0x0 0. " DUMP_MODE_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x0 1. " DUMP_MODE_CONDITIONAL ,Define the stat conditional dump, if one a dump will be generated when alarm is trigged Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_STCOL_DUMP_SEND,L3_STCOL_DUMP_SEND" bitfld.long 0x0 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_STCOL_DUMP_DISABLE,L3_STCOL_DUMP_DISABLE" bitfld.long 0x0 0. " DUMP_DISABLE ,If 1, the dump frame will be disabled, but counters still active.This is typically used when counters monitoring is enabled Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_TRIG,L3_STCOL_DUMP_ALARM_TRIG" bitfld.long 0x0 0. " DUMP_ALARM_TRIG ,In Alarm Mode, is used to reset Alarm Type: Take. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MINVAL,L3_STCOL_DUMP_ALARM_MINVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MINVAL ,In Alarm Mode, used to trig an alert if any of counter value is less than AlarmMinVal Type: Control. Reset value: 0x0." group.byte 0x68++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MAXVAL,L3_STCOL_DUMP_ALARM_MAXVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MAXVAL ,In Alarm Mode, used to trig an alert if any of counter value is larger or equal to AlarmMaxVal Type: Control. Reset value: 0x0." group.byte 0x6C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE0,L3_STCOL_DUMP_ALARM_MODE0" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE0 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE1,L3_STCOL_DUMP_ALARM_MODE1" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE1 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE2,L3_STCOL_DUMP_ALARM_MODE2" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE2 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE3,L3_STCOL_DUMP_ALARM_MODE3" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE3 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT0,L3_STCOL_DUMP_CNT0" hexmask.long 0x0 0.--31. 1. " DUMP_CNT0 ,Dump counter value Type: Status. Reset value: X." group.byte 0x90++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT1,L3_STCOL_DUMP_CNT1" hexmask.long 0x0 0.--31. 1. " DUMP_CNT1 ,Dump counter value Type: Status. Reset value: X." group.byte 0x94++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT2,L3_STCOL_DUMP_CNT2" hexmask.long 0x0 0.--31. 1. " DUMP_CNT2 ,Dump counter value Type: Status. Reset value: X." group.byte 0x98++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT3,L3_STCOL_DUMP_CNT3" hexmask.long 0x0 0.--31. 1. " DUMP_CNT3 ,Dump counter value Type: Status. Reset value: X." group.byte 0xAC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_0,L3_STCOL_FILTER_i_GLOBALEN_0" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_1,L3_STCOL_FILTER_i_GLOBALEN_1" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x35C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_2,L3_STCOL_FILTER_i_GLOBALEN_2" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4B4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_3,L3_STCOL_FILTER_i_GLOBALEN_3" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_0,L3_STCOL_FILTER_i_ADDRMIN_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_1,L3_STCOL_FILTER_i_ADDRMIN_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_2,L3_STCOL_FILTER_i_ADDRMIN_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_3,L3_STCOL_FILTER_i_ADDRMIN_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_0,L3_STCOL_FILTER_i_ADDRMAX_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_1,L3_STCOL_FILTER_i_ADDRMAX_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_2,L3_STCOL_FILTER_i_ADDRMAX_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_3,L3_STCOL_FILTER_i_ADDRMAX_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_0,L3_STCOL_FILTER_i_ADDREN_0" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_1,L3_STCOL_FILTER_i_ADDREN_1" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_2,L3_STCOL_FILTER_i_ADDREN_2" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_3,L3_STCOL_FILTER_i_ADDREN_3" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_0,L3_STCOL_FILTER_i_EN_k_0" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_1,L3_STCOL_FILTER_i_EN_k_1" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x36C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_2,L3_STCOL_FILTER_i_EN_k_2" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_3,L3_STCOL_FILTER_i_EN_k_3" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_0,L3_STCOL_FILTER_i_MASK_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_1,L3_STCOL_FILTER_i_MASK_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x370++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_2,L3_STCOL_FILTER_i_MASK_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_3,L3_STCOL_FILTER_i_MASK_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_0,L3_STCOL_FILTER_i_MASK_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_1,L3_STCOL_FILTER_i_MASK_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x374++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_2,L3_STCOL_FILTER_i_MASK_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_3,L3_STCOL_FILTER_i_MASK_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0,L3_STCOL_FILTER_i_MASK_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1,L3_STCOL_FILTER_i_MASK_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x378++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2,L3_STCOL_FILTER_i_MASK_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3,L3_STCOL_FILTER_i_MASK_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xCC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0,L3_STCOL_FILTER_i_MASK_m_SLVADDR_0" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1,L3_STCOL_FILTER_i_MASK_m_SLVADDR_1" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x37C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2,L3_STCOL_FILTER_i_MASK_m_SLVADDR_2" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x4D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3,L3_STCOL_FILTER_i_MASK_m_SLVADDR_3" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_0,L3_STCOL_FILTER_i_MASK_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_1,L3_STCOL_FILTER_i_MASK_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_2,L3_STCOL_FILTER_i_MASK_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_3,L3_STCOL_FILTER_i_MASK_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x388++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_0,L3_STCOL_FILTER_i_MATCH_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_1,L3_STCOL_FILTER_i_MATCH_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_2,L3_STCOL_FILTER_i_MATCH_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_3,L3_STCOL_FILTER_i_MATCH_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_0,L3_STCOL_FILTER_i_MATCH_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_1,L3_STCOL_FILTER_i_MATCH_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_2,L3_STCOL_FILTER_i_MATCH_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4EC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_3,L3_STCOL_FILTER_i_MATCH_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xEC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x244++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x39C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x4F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_0,L3_STCOL_FILTER_i_MATCH_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_1,L3_STCOL_FILTER_i_MATCH_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x3A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_2,L3_STCOL_FILTER_i_MATCH_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_3,L3_STCOL_FILTER_i_MATCH_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xF4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x24C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xF8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x3A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0,L3_STCOL_OP_i_THRESHOLD_MINVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x348++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1,L3_STCOL_OP_i_THRESHOLD_MINVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2,L3_STCOL_OP_i_THRESHOLD_MINVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5F8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3,L3_STCOL_OP_i_THRESHOLD_MINVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0,L3_STCOL_OP_i_THRESHOLD_MAXVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x34C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1,L3_STCOL_OP_i_THRESHOLD_MAXVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2,L3_STCOL_OP_i_THRESHOLD_MAXVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5FC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3,L3_STCOL_OP_i_THRESHOLD_MAXVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_0,L3_STCOL_OP_i_EVTINFOSEL_0" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x350++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_1,L3_STCOL_OP_i_EVTINFOSEL_1" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4A8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_2,L3_STCOL_OP_i_EVTINFOSEL_2" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_3,L3_STCOL_OP_i_EVTINFOSEL_3" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_0,L3_STCOL_OP_i_SEL_0" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_1,L3_STCOL_OP_i_SEL_1" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_2,L3_STCOL_OP_i_SEL_2" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_3,L3_STCOL_OP_i_SEL_3" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK2_STATCOLL4" base ad:0x45005000 width 41. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_EN,L3_STCOL_EN" bitfld.long 0x0 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_SOFTEN,L3_STCOL_SOFTEN" bitfld.long 0x0 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_STCOL_IGNORESUSPEND,L3_STCOL_IGNORESUSPEND" bitfld.long 0x0 0. " IGNORESUSPEND ,Ignore suspend if set to one for suspend mechanism Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_STCOL_TRIGEN,L3_STCOL_TRIGEN" bitfld.long 0x0 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "L3_STCOL_REQEVT,L3_STCOL_REQEVT" bitfld.long 0x0 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "L3_STCOL_RSPEVT,L3_STCOL_RSPEVT" bitfld.long 0x0 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL0,L3_STCOL_EVTMUX_SEL0" bitfld.long 0x0 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL1,L3_STCOL_EVTMUX_SEL1" bitfld.long 0x0 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL2,L3_STCOL_EVTMUX_SEL2" bitfld.long 0x0 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL3,L3_STCOL_EVTMUX_SEL3" bitfld.long 0x0 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_STCOL_DUMP_IDENTIFIER,L3_STCOL_DUMP_IDENTIFIER" bitfld.long 0x0 0.--3. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_STCOL_DUMP_COLLECTTIME,L3_STCOL_DUMP_COLLECTTIME" hexmask.long 0x0 0.--31. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." group.byte 0x48++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVADDR,L3_STCOL_DUMP_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "L3_STCOL_DUMP_MSTADDR,L3_STCOL_DUMP_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVOFS,L3_STCOL_DUMP_SLVOFS" hexmask.long 0x0 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.byte 0x54++0x3 line.long 0x0 "L3_STCOL_DUMP_MODE,L3_STCOL_DUMP_MODE" bitfld.long 0x0 0. " DUMP_MODE_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x0 1. " DUMP_MODE_CONDITIONAL ,Define the stat conditional dump, if one a dump will be generated when alarm is trigged Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_STCOL_DUMP_SEND,L3_STCOL_DUMP_SEND" bitfld.long 0x0 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_STCOL_DUMP_DISABLE,L3_STCOL_DUMP_DISABLE" bitfld.long 0x0 0. " DUMP_DISABLE ,If 1, the dump frame will be disabled, but counters still active.This is typically used when counters monitoring is enabled Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_TRIG,L3_STCOL_DUMP_ALARM_TRIG" bitfld.long 0x0 0. " DUMP_ALARM_TRIG ,In Alarm Mode, is used to reset Alarm Type: Take. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MINVAL,L3_STCOL_DUMP_ALARM_MINVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MINVAL ,In Alarm Mode, used to trig an alert if any of counter value is less than AlarmMinVal Type: Control. Reset value: 0x0." group.byte 0x68++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MAXVAL,L3_STCOL_DUMP_ALARM_MAXVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MAXVAL ,In Alarm Mode, used to trig an alert if any of counter value is larger or equal to AlarmMaxVal Type: Control. Reset value: 0x0." group.byte 0x6C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE0,L3_STCOL_DUMP_ALARM_MODE0" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE0 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE1,L3_STCOL_DUMP_ALARM_MODE1" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE1 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE2,L3_STCOL_DUMP_ALARM_MODE2" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE2 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE3,L3_STCOL_DUMP_ALARM_MODE3" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE3 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT0,L3_STCOL_DUMP_CNT0" hexmask.long 0x0 0.--31. 1. " DUMP_CNT0 ,Dump counter value Type: Status. Reset value: X." group.byte 0x90++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT1,L3_STCOL_DUMP_CNT1" hexmask.long 0x0 0.--31. 1. " DUMP_CNT1 ,Dump counter value Type: Status. Reset value: X." group.byte 0x94++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT2,L3_STCOL_DUMP_CNT2" hexmask.long 0x0 0.--31. 1. " DUMP_CNT2 ,Dump counter value Type: Status. Reset value: X." group.byte 0x98++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT3,L3_STCOL_DUMP_CNT3" hexmask.long 0x0 0.--31. 1. " DUMP_CNT3 ,Dump counter value Type: Status. Reset value: X." group.byte 0xAC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_0,L3_STCOL_FILTER_i_GLOBALEN_0" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_1,L3_STCOL_FILTER_i_GLOBALEN_1" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x35C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_2,L3_STCOL_FILTER_i_GLOBALEN_2" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4B4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_3,L3_STCOL_FILTER_i_GLOBALEN_3" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_0,L3_STCOL_FILTER_i_ADDRMIN_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_1,L3_STCOL_FILTER_i_ADDRMIN_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_2,L3_STCOL_FILTER_i_ADDRMIN_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_3,L3_STCOL_FILTER_i_ADDRMIN_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_0,L3_STCOL_FILTER_i_ADDRMAX_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_1,L3_STCOL_FILTER_i_ADDRMAX_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_2,L3_STCOL_FILTER_i_ADDRMAX_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_3,L3_STCOL_FILTER_i_ADDRMAX_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_0,L3_STCOL_FILTER_i_ADDREN_0" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_1,L3_STCOL_FILTER_i_ADDREN_1" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_2,L3_STCOL_FILTER_i_ADDREN_2" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_3,L3_STCOL_FILTER_i_ADDREN_3" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_0,L3_STCOL_FILTER_i_EN_k_0" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_1,L3_STCOL_FILTER_i_EN_k_1" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x36C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_2,L3_STCOL_FILTER_i_EN_k_2" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_3,L3_STCOL_FILTER_i_EN_k_3" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_0,L3_STCOL_FILTER_i_MASK_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_1,L3_STCOL_FILTER_i_MASK_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x370++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_2,L3_STCOL_FILTER_i_MASK_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_3,L3_STCOL_FILTER_i_MASK_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_0,L3_STCOL_FILTER_i_MASK_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_1,L3_STCOL_FILTER_i_MASK_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x374++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_2,L3_STCOL_FILTER_i_MASK_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_3,L3_STCOL_FILTER_i_MASK_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0,L3_STCOL_FILTER_i_MASK_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1,L3_STCOL_FILTER_i_MASK_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x378++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2,L3_STCOL_FILTER_i_MASK_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3,L3_STCOL_FILTER_i_MASK_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xCC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0,L3_STCOL_FILTER_i_MASK_m_SLVADDR_0" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1,L3_STCOL_FILTER_i_MASK_m_SLVADDR_1" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x37C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2,L3_STCOL_FILTER_i_MASK_m_SLVADDR_2" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x4D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3,L3_STCOL_FILTER_i_MASK_m_SLVADDR_3" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_0,L3_STCOL_FILTER_i_MASK_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_1,L3_STCOL_FILTER_i_MASK_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_2,L3_STCOL_FILTER_i_MASK_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_3,L3_STCOL_FILTER_i_MASK_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x388++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_0,L3_STCOL_FILTER_i_MATCH_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_1,L3_STCOL_FILTER_i_MATCH_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_2,L3_STCOL_FILTER_i_MATCH_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_3,L3_STCOL_FILTER_i_MATCH_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_0,L3_STCOL_FILTER_i_MATCH_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_1,L3_STCOL_FILTER_i_MATCH_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_2,L3_STCOL_FILTER_i_MATCH_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4EC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_3,L3_STCOL_FILTER_i_MATCH_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xEC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x244++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x39C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x4F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_0,L3_STCOL_FILTER_i_MATCH_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_1,L3_STCOL_FILTER_i_MATCH_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x3A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_2,L3_STCOL_FILTER_i_MATCH_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_3,L3_STCOL_FILTER_i_MATCH_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xF4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x24C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xF8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x3A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0,L3_STCOL_OP_i_THRESHOLD_MINVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x348++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1,L3_STCOL_OP_i_THRESHOLD_MINVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2,L3_STCOL_OP_i_THRESHOLD_MINVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5F8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3,L3_STCOL_OP_i_THRESHOLD_MINVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0,L3_STCOL_OP_i_THRESHOLD_MAXVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x34C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1,L3_STCOL_OP_i_THRESHOLD_MAXVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2,L3_STCOL_OP_i_THRESHOLD_MAXVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5FC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3,L3_STCOL_OP_i_THRESHOLD_MAXVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_0,L3_STCOL_OP_i_EVTINFOSEL_0" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x350++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_1,L3_STCOL_OP_i_EVTINFOSEL_1" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4A8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_2,L3_STCOL_OP_i_EVTINFOSEL_2" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_3,L3_STCOL_OP_i_EVTINFOSEL_3" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_0,L3_STCOL_OP_i_SEL_0" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_1,L3_STCOL_OP_i_SEL_1" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_2,L3_STCOL_OP_i_SEL_2" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_3,L3_STCOL_OP_i_SEL_3" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK2_STATCOLL6" base ad:0x45007000 width 41. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_EN,L3_STCOL_EN" bitfld.long 0x0 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_SOFTEN,L3_STCOL_SOFTEN" bitfld.long 0x0 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_STCOL_IGNORESUSPEND,L3_STCOL_IGNORESUSPEND" bitfld.long 0x0 0. " IGNORESUSPEND ,Ignore suspend if set to one for suspend mechanism Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_STCOL_TRIGEN,L3_STCOL_TRIGEN" bitfld.long 0x0 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "L3_STCOL_REQEVT,L3_STCOL_REQEVT" bitfld.long 0x0 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "L3_STCOL_RSPEVT,L3_STCOL_RSPEVT" bitfld.long 0x0 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL0,L3_STCOL_EVTMUX_SEL0" bitfld.long 0x0 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL1,L3_STCOL_EVTMUX_SEL1" bitfld.long 0x0 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL2,L3_STCOL_EVTMUX_SEL2" bitfld.long 0x0 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL3,L3_STCOL_EVTMUX_SEL3" bitfld.long 0x0 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_STCOL_DUMP_IDENTIFIER,L3_STCOL_DUMP_IDENTIFIER" bitfld.long 0x0 0.--3. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_STCOL_DUMP_COLLECTTIME,L3_STCOL_DUMP_COLLECTTIME" hexmask.long 0x0 0.--31. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." group.byte 0x48++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVADDR,L3_STCOL_DUMP_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "L3_STCOL_DUMP_MSTADDR,L3_STCOL_DUMP_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVOFS,L3_STCOL_DUMP_SLVOFS" hexmask.long 0x0 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.byte 0x54++0x3 line.long 0x0 "L3_STCOL_DUMP_MODE,L3_STCOL_DUMP_MODE" bitfld.long 0x0 0. " DUMP_MODE_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x0 1. " DUMP_MODE_CONDITIONAL ,Define the stat conditional dump, if one a dump will be generated when alarm is trigged Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_STCOL_DUMP_SEND,L3_STCOL_DUMP_SEND" bitfld.long 0x0 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_STCOL_DUMP_DISABLE,L3_STCOL_DUMP_DISABLE" bitfld.long 0x0 0. " DUMP_DISABLE ,If 1, the dump frame will be disabled, but counters still active.This is typically used when counters monitoring is enabled Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_TRIG,L3_STCOL_DUMP_ALARM_TRIG" bitfld.long 0x0 0. " DUMP_ALARM_TRIG ,In Alarm Mode, is used to reset Alarm Type: Take. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MINVAL,L3_STCOL_DUMP_ALARM_MINVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MINVAL ,In Alarm Mode, used to trig an alert if any of counter value is less than AlarmMinVal Type: Control. Reset value: 0x0." group.byte 0x68++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MAXVAL,L3_STCOL_DUMP_ALARM_MAXVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MAXVAL ,In Alarm Mode, used to trig an alert if any of counter value is larger or equal to AlarmMaxVal Type: Control. Reset value: 0x0." group.byte 0x6C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE0,L3_STCOL_DUMP_ALARM_MODE0" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE0 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE1,L3_STCOL_DUMP_ALARM_MODE1" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE1 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE2,L3_STCOL_DUMP_ALARM_MODE2" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE2 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE3,L3_STCOL_DUMP_ALARM_MODE3" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE3 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT0,L3_STCOL_DUMP_CNT0" hexmask.long 0x0 0.--31. 1. " DUMP_CNT0 ,Dump counter value Type: Status. Reset value: X." group.byte 0x90++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT1,L3_STCOL_DUMP_CNT1" hexmask.long 0x0 0.--31. 1. " DUMP_CNT1 ,Dump counter value Type: Status. Reset value: X." group.byte 0x94++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT2,L3_STCOL_DUMP_CNT2" hexmask.long 0x0 0.--31. 1. " DUMP_CNT2 ,Dump counter value Type: Status. Reset value: X." group.byte 0x98++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT3,L3_STCOL_DUMP_CNT3" hexmask.long 0x0 0.--31. 1. " DUMP_CNT3 ,Dump counter value Type: Status. Reset value: X." group.byte 0xAC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_0,L3_STCOL_FILTER_i_GLOBALEN_0" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_1,L3_STCOL_FILTER_i_GLOBALEN_1" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x35C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_2,L3_STCOL_FILTER_i_GLOBALEN_2" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4B4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_3,L3_STCOL_FILTER_i_GLOBALEN_3" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_0,L3_STCOL_FILTER_i_ADDRMIN_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_1,L3_STCOL_FILTER_i_ADDRMIN_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_2,L3_STCOL_FILTER_i_ADDRMIN_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_3,L3_STCOL_FILTER_i_ADDRMIN_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_0,L3_STCOL_FILTER_i_ADDRMAX_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_1,L3_STCOL_FILTER_i_ADDRMAX_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_2,L3_STCOL_FILTER_i_ADDRMAX_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_3,L3_STCOL_FILTER_i_ADDRMAX_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_0,L3_STCOL_FILTER_i_ADDREN_0" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_1,L3_STCOL_FILTER_i_ADDREN_1" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_2,L3_STCOL_FILTER_i_ADDREN_2" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_3,L3_STCOL_FILTER_i_ADDREN_3" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_0,L3_STCOL_FILTER_i_EN_k_0" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_1,L3_STCOL_FILTER_i_EN_k_1" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x36C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_2,L3_STCOL_FILTER_i_EN_k_2" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_3,L3_STCOL_FILTER_i_EN_k_3" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_0,L3_STCOL_FILTER_i_MASK_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_1,L3_STCOL_FILTER_i_MASK_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x370++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_2,L3_STCOL_FILTER_i_MASK_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_3,L3_STCOL_FILTER_i_MASK_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_0,L3_STCOL_FILTER_i_MASK_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_1,L3_STCOL_FILTER_i_MASK_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x374++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_2,L3_STCOL_FILTER_i_MASK_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_3,L3_STCOL_FILTER_i_MASK_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0,L3_STCOL_FILTER_i_MASK_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1,L3_STCOL_FILTER_i_MASK_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x378++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2,L3_STCOL_FILTER_i_MASK_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3,L3_STCOL_FILTER_i_MASK_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xCC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0,L3_STCOL_FILTER_i_MASK_m_SLVADDR_0" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1,L3_STCOL_FILTER_i_MASK_m_SLVADDR_1" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x37C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2,L3_STCOL_FILTER_i_MASK_m_SLVADDR_2" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x4D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3,L3_STCOL_FILTER_i_MASK_m_SLVADDR_3" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_0,L3_STCOL_FILTER_i_MASK_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_1,L3_STCOL_FILTER_i_MASK_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_2,L3_STCOL_FILTER_i_MASK_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_3,L3_STCOL_FILTER_i_MASK_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x388++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_0,L3_STCOL_FILTER_i_MATCH_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_1,L3_STCOL_FILTER_i_MATCH_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_2,L3_STCOL_FILTER_i_MATCH_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_3,L3_STCOL_FILTER_i_MATCH_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_0,L3_STCOL_FILTER_i_MATCH_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_1,L3_STCOL_FILTER_i_MATCH_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_2,L3_STCOL_FILTER_i_MATCH_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4EC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_3,L3_STCOL_FILTER_i_MATCH_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xEC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x244++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x39C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x4F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_0,L3_STCOL_FILTER_i_MATCH_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_1,L3_STCOL_FILTER_i_MATCH_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x3A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_2,L3_STCOL_FILTER_i_MATCH_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_3,L3_STCOL_FILTER_i_MATCH_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xF4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x24C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xF8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x3A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0,L3_STCOL_OP_i_THRESHOLD_MINVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x348++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1,L3_STCOL_OP_i_THRESHOLD_MINVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2,L3_STCOL_OP_i_THRESHOLD_MINVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5F8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3,L3_STCOL_OP_i_THRESHOLD_MINVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0,L3_STCOL_OP_i_THRESHOLD_MAXVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x34C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1,L3_STCOL_OP_i_THRESHOLD_MAXVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2,L3_STCOL_OP_i_THRESHOLD_MAXVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5FC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3,L3_STCOL_OP_i_THRESHOLD_MAXVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_0,L3_STCOL_OP_i_EVTINFOSEL_0" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x350++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_1,L3_STCOL_OP_i_EVTINFOSEL_1" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4A8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_2,L3_STCOL_OP_i_EVTINFOSEL_2" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_3,L3_STCOL_OP_i_EVTINFOSEL_3" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_0,L3_STCOL_OP_i_SEL_0" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_1,L3_STCOL_OP_i_SEL_1" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_2,L3_STCOL_OP_i_SEL_2" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_3,L3_STCOL_OP_i_SEL_3" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK2_STATCOLL7" base ad:0x45008000 width 41. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_EN,L3_STCOL_EN" bitfld.long 0x0 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_SOFTEN,L3_STCOL_SOFTEN" bitfld.long 0x0 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_STCOL_IGNORESUSPEND,L3_STCOL_IGNORESUSPEND" bitfld.long 0x0 0. " IGNORESUSPEND ,Ignore suspend if set to one for suspend mechanism Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_STCOL_TRIGEN,L3_STCOL_TRIGEN" bitfld.long 0x0 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "L3_STCOL_REQEVT,L3_STCOL_REQEVT" bitfld.long 0x0 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "L3_STCOL_RSPEVT,L3_STCOL_RSPEVT" bitfld.long 0x0 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL0,L3_STCOL_EVTMUX_SEL0" bitfld.long 0x0 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL1,L3_STCOL_EVTMUX_SEL1" bitfld.long 0x0 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL2,L3_STCOL_EVTMUX_SEL2" bitfld.long 0x0 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL3,L3_STCOL_EVTMUX_SEL3" bitfld.long 0x0 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_STCOL_DUMP_IDENTIFIER,L3_STCOL_DUMP_IDENTIFIER" bitfld.long 0x0 0.--3. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_STCOL_DUMP_COLLECTTIME,L3_STCOL_DUMP_COLLECTTIME" hexmask.long 0x0 0.--31. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." group.byte 0x48++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVADDR,L3_STCOL_DUMP_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "L3_STCOL_DUMP_MSTADDR,L3_STCOL_DUMP_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVOFS,L3_STCOL_DUMP_SLVOFS" hexmask.long 0x0 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.byte 0x54++0x3 line.long 0x0 "L3_STCOL_DUMP_MODE,L3_STCOL_DUMP_MODE" bitfld.long 0x0 0. " DUMP_MODE_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x0 1. " DUMP_MODE_CONDITIONAL ,Define the stat conditional dump, if one a dump will be generated when alarm is trigged Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_STCOL_DUMP_SEND,L3_STCOL_DUMP_SEND" bitfld.long 0x0 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_STCOL_DUMP_DISABLE,L3_STCOL_DUMP_DISABLE" bitfld.long 0x0 0. " DUMP_DISABLE ,If 1, the dump frame will be disabled, but counters still active.This is typically used when counters monitoring is enabled Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_TRIG,L3_STCOL_DUMP_ALARM_TRIG" bitfld.long 0x0 0. " DUMP_ALARM_TRIG ,In Alarm Mode, is used to reset Alarm Type: Take. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MINVAL,L3_STCOL_DUMP_ALARM_MINVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MINVAL ,In Alarm Mode, used to trig an alert if any of counter value is less than AlarmMinVal Type: Control. Reset value: 0x0." group.byte 0x68++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MAXVAL,L3_STCOL_DUMP_ALARM_MAXVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MAXVAL ,In Alarm Mode, used to trig an alert if any of counter value is larger or equal to AlarmMaxVal Type: Control. Reset value: 0x0." group.byte 0x6C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE0,L3_STCOL_DUMP_ALARM_MODE0" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE0 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE1,L3_STCOL_DUMP_ALARM_MODE1" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE1 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE2,L3_STCOL_DUMP_ALARM_MODE2" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE2 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE3,L3_STCOL_DUMP_ALARM_MODE3" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE3 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT0,L3_STCOL_DUMP_CNT0" hexmask.long 0x0 0.--31. 1. " DUMP_CNT0 ,Dump counter value Type: Status. Reset value: X." group.byte 0x90++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT1,L3_STCOL_DUMP_CNT1" hexmask.long 0x0 0.--31. 1. " DUMP_CNT1 ,Dump counter value Type: Status. Reset value: X." group.byte 0x94++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT2,L3_STCOL_DUMP_CNT2" hexmask.long 0x0 0.--31. 1. " DUMP_CNT2 ,Dump counter value Type: Status. Reset value: X." group.byte 0x98++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT3,L3_STCOL_DUMP_CNT3" hexmask.long 0x0 0.--31. 1. " DUMP_CNT3 ,Dump counter value Type: Status. Reset value: X." group.byte 0xAC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_0,L3_STCOL_FILTER_i_GLOBALEN_0" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_1,L3_STCOL_FILTER_i_GLOBALEN_1" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x35C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_2,L3_STCOL_FILTER_i_GLOBALEN_2" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4B4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_3,L3_STCOL_FILTER_i_GLOBALEN_3" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_0,L3_STCOL_FILTER_i_ADDRMIN_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_1,L3_STCOL_FILTER_i_ADDRMIN_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_2,L3_STCOL_FILTER_i_ADDRMIN_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_3,L3_STCOL_FILTER_i_ADDRMIN_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_0,L3_STCOL_FILTER_i_ADDRMAX_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_1,L3_STCOL_FILTER_i_ADDRMAX_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_2,L3_STCOL_FILTER_i_ADDRMAX_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_3,L3_STCOL_FILTER_i_ADDRMAX_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_0,L3_STCOL_FILTER_i_ADDREN_0" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_1,L3_STCOL_FILTER_i_ADDREN_1" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_2,L3_STCOL_FILTER_i_ADDREN_2" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_3,L3_STCOL_FILTER_i_ADDREN_3" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_0,L3_STCOL_FILTER_i_EN_k_0" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_1,L3_STCOL_FILTER_i_EN_k_1" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x36C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_2,L3_STCOL_FILTER_i_EN_k_2" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_3,L3_STCOL_FILTER_i_EN_k_3" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_0,L3_STCOL_FILTER_i_MASK_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_1,L3_STCOL_FILTER_i_MASK_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x370++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_2,L3_STCOL_FILTER_i_MASK_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_3,L3_STCOL_FILTER_i_MASK_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_0,L3_STCOL_FILTER_i_MASK_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_1,L3_STCOL_FILTER_i_MASK_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x374++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_2,L3_STCOL_FILTER_i_MASK_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_3,L3_STCOL_FILTER_i_MASK_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0,L3_STCOL_FILTER_i_MASK_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1,L3_STCOL_FILTER_i_MASK_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x378++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2,L3_STCOL_FILTER_i_MASK_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3,L3_STCOL_FILTER_i_MASK_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xCC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0,L3_STCOL_FILTER_i_MASK_m_SLVADDR_0" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1,L3_STCOL_FILTER_i_MASK_m_SLVADDR_1" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x37C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2,L3_STCOL_FILTER_i_MASK_m_SLVADDR_2" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x4D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3,L3_STCOL_FILTER_i_MASK_m_SLVADDR_3" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_0,L3_STCOL_FILTER_i_MASK_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_1,L3_STCOL_FILTER_i_MASK_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_2,L3_STCOL_FILTER_i_MASK_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_3,L3_STCOL_FILTER_i_MASK_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x388++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_0,L3_STCOL_FILTER_i_MATCH_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_1,L3_STCOL_FILTER_i_MATCH_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_2,L3_STCOL_FILTER_i_MATCH_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_3,L3_STCOL_FILTER_i_MATCH_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_0,L3_STCOL_FILTER_i_MATCH_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_1,L3_STCOL_FILTER_i_MATCH_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_2,L3_STCOL_FILTER_i_MATCH_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4EC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_3,L3_STCOL_FILTER_i_MATCH_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xEC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x244++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x39C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x4F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_0,L3_STCOL_FILTER_i_MATCH_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_1,L3_STCOL_FILTER_i_MATCH_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x3A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_2,L3_STCOL_FILTER_i_MATCH_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_3,L3_STCOL_FILTER_i_MATCH_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xF4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x24C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xF8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x3A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0,L3_STCOL_OP_i_THRESHOLD_MINVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x348++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1,L3_STCOL_OP_i_THRESHOLD_MINVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2,L3_STCOL_OP_i_THRESHOLD_MINVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5F8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3,L3_STCOL_OP_i_THRESHOLD_MINVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0,L3_STCOL_OP_i_THRESHOLD_MAXVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x34C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1,L3_STCOL_OP_i_THRESHOLD_MAXVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2,L3_STCOL_OP_i_THRESHOLD_MAXVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5FC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3,L3_STCOL_OP_i_THRESHOLD_MAXVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_0,L3_STCOL_OP_i_EVTINFOSEL_0" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x350++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_1,L3_STCOL_OP_i_EVTINFOSEL_1" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4A8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_2,L3_STCOL_OP_i_EVTINFOSEL_2" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_3,L3_STCOL_OP_i_EVTINFOSEL_3" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_0,L3_STCOL_OP_i_SEL_0" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_1,L3_STCOL_OP_i_SEL_1" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_2,L3_STCOL_OP_i_SEL_2" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_3,L3_STCOL_OP_i_SEL_3" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK2_STATCOLL8" base ad:0x45009000 width 41. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_EN,L3_STCOL_EN" bitfld.long 0x0 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_SOFTEN,L3_STCOL_SOFTEN" bitfld.long 0x0 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_STCOL_IGNORESUSPEND,L3_STCOL_IGNORESUSPEND" bitfld.long 0x0 0. " IGNORESUSPEND ,Ignore suspend if set to one for suspend mechanism Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_STCOL_TRIGEN,L3_STCOL_TRIGEN" bitfld.long 0x0 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "L3_STCOL_REQEVT,L3_STCOL_REQEVT" bitfld.long 0x0 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "L3_STCOL_RSPEVT,L3_STCOL_RSPEVT" bitfld.long 0x0 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL0,L3_STCOL_EVTMUX_SEL0" bitfld.long 0x0 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL1,L3_STCOL_EVTMUX_SEL1" bitfld.long 0x0 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL2,L3_STCOL_EVTMUX_SEL2" bitfld.long 0x0 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL3,L3_STCOL_EVTMUX_SEL3" bitfld.long 0x0 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_STCOL_DUMP_IDENTIFIER,L3_STCOL_DUMP_IDENTIFIER" bitfld.long 0x0 0.--3. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_STCOL_DUMP_COLLECTTIME,L3_STCOL_DUMP_COLLECTTIME" hexmask.long 0x0 0.--31. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." group.byte 0x48++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVADDR,L3_STCOL_DUMP_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "L3_STCOL_DUMP_MSTADDR,L3_STCOL_DUMP_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVOFS,L3_STCOL_DUMP_SLVOFS" hexmask.long 0x0 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.byte 0x54++0x3 line.long 0x0 "L3_STCOL_DUMP_MODE,L3_STCOL_DUMP_MODE" bitfld.long 0x0 0. " DUMP_MODE_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x0 1. " DUMP_MODE_CONDITIONAL ,Define the stat conditional dump, if one a dump will be generated when alarm is trigged Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_STCOL_DUMP_SEND,L3_STCOL_DUMP_SEND" bitfld.long 0x0 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_STCOL_DUMP_DISABLE,L3_STCOL_DUMP_DISABLE" bitfld.long 0x0 0. " DUMP_DISABLE ,If 1, the dump frame will be disabled, but counters still active.This is typically used when counters monitoring is enabled Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_TRIG,L3_STCOL_DUMP_ALARM_TRIG" bitfld.long 0x0 0. " DUMP_ALARM_TRIG ,In Alarm Mode, is used to reset Alarm Type: Take. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MINVAL,L3_STCOL_DUMP_ALARM_MINVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MINVAL ,In Alarm Mode, used to trig an alert if any of counter value is less than AlarmMinVal Type: Control. Reset value: 0x0." group.byte 0x68++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MAXVAL,L3_STCOL_DUMP_ALARM_MAXVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MAXVAL ,In Alarm Mode, used to trig an alert if any of counter value is larger or equal to AlarmMaxVal Type: Control. Reset value: 0x0." group.byte 0x6C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE0,L3_STCOL_DUMP_ALARM_MODE0" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE0 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE1,L3_STCOL_DUMP_ALARM_MODE1" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE1 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE2,L3_STCOL_DUMP_ALARM_MODE2" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE2 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE3,L3_STCOL_DUMP_ALARM_MODE3" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE3 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT0,L3_STCOL_DUMP_CNT0" hexmask.long 0x0 0.--31. 1. " DUMP_CNT0 ,Dump counter value Type: Status. Reset value: X." group.byte 0x90++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT1,L3_STCOL_DUMP_CNT1" hexmask.long 0x0 0.--31. 1. " DUMP_CNT1 ,Dump counter value Type: Status. Reset value: X." group.byte 0x94++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT2,L3_STCOL_DUMP_CNT2" hexmask.long 0x0 0.--31. 1. " DUMP_CNT2 ,Dump counter value Type: Status. Reset value: X." group.byte 0x98++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT3,L3_STCOL_DUMP_CNT3" hexmask.long 0x0 0.--31. 1. " DUMP_CNT3 ,Dump counter value Type: Status. Reset value: X." group.byte 0xAC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_0,L3_STCOL_FILTER_i_GLOBALEN_0" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_1,L3_STCOL_FILTER_i_GLOBALEN_1" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x35C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_2,L3_STCOL_FILTER_i_GLOBALEN_2" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4B4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_3,L3_STCOL_FILTER_i_GLOBALEN_3" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_0,L3_STCOL_FILTER_i_ADDRMIN_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_1,L3_STCOL_FILTER_i_ADDRMIN_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_2,L3_STCOL_FILTER_i_ADDRMIN_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_3,L3_STCOL_FILTER_i_ADDRMIN_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_0,L3_STCOL_FILTER_i_ADDRMAX_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_1,L3_STCOL_FILTER_i_ADDRMAX_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_2,L3_STCOL_FILTER_i_ADDRMAX_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_3,L3_STCOL_FILTER_i_ADDRMAX_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_0,L3_STCOL_FILTER_i_ADDREN_0" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_1,L3_STCOL_FILTER_i_ADDREN_1" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_2,L3_STCOL_FILTER_i_ADDREN_2" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_3,L3_STCOL_FILTER_i_ADDREN_3" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_0,L3_STCOL_FILTER_i_EN_k_0" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_1,L3_STCOL_FILTER_i_EN_k_1" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x36C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_2,L3_STCOL_FILTER_i_EN_k_2" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_3,L3_STCOL_FILTER_i_EN_k_3" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_0,L3_STCOL_FILTER_i_MASK_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_1,L3_STCOL_FILTER_i_MASK_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x370++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_2,L3_STCOL_FILTER_i_MASK_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_3,L3_STCOL_FILTER_i_MASK_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_0,L3_STCOL_FILTER_i_MASK_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_1,L3_STCOL_FILTER_i_MASK_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x374++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_2,L3_STCOL_FILTER_i_MASK_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_3,L3_STCOL_FILTER_i_MASK_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0,L3_STCOL_FILTER_i_MASK_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1,L3_STCOL_FILTER_i_MASK_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x378++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2,L3_STCOL_FILTER_i_MASK_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3,L3_STCOL_FILTER_i_MASK_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xCC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0,L3_STCOL_FILTER_i_MASK_m_SLVADDR_0" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1,L3_STCOL_FILTER_i_MASK_m_SLVADDR_1" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x37C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2,L3_STCOL_FILTER_i_MASK_m_SLVADDR_2" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x4D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3,L3_STCOL_FILTER_i_MASK_m_SLVADDR_3" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_0,L3_STCOL_FILTER_i_MASK_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_1,L3_STCOL_FILTER_i_MASK_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_2,L3_STCOL_FILTER_i_MASK_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_3,L3_STCOL_FILTER_i_MASK_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x388++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_0,L3_STCOL_FILTER_i_MATCH_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_1,L3_STCOL_FILTER_i_MATCH_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_2,L3_STCOL_FILTER_i_MATCH_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_3,L3_STCOL_FILTER_i_MATCH_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_0,L3_STCOL_FILTER_i_MATCH_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_1,L3_STCOL_FILTER_i_MATCH_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_2,L3_STCOL_FILTER_i_MATCH_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4EC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_3,L3_STCOL_FILTER_i_MATCH_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xEC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x244++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x39C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x4F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_0,L3_STCOL_FILTER_i_MATCH_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_1,L3_STCOL_FILTER_i_MATCH_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x3A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_2,L3_STCOL_FILTER_i_MATCH_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_3,L3_STCOL_FILTER_i_MATCH_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xF4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x24C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xF8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x3A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0,L3_STCOL_OP_i_THRESHOLD_MINVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x348++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1,L3_STCOL_OP_i_THRESHOLD_MINVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2,L3_STCOL_OP_i_THRESHOLD_MINVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5F8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3,L3_STCOL_OP_i_THRESHOLD_MINVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0,L3_STCOL_OP_i_THRESHOLD_MAXVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x34C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1,L3_STCOL_OP_i_THRESHOLD_MAXVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2,L3_STCOL_OP_i_THRESHOLD_MAXVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5FC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3,L3_STCOL_OP_i_THRESHOLD_MAXVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_0,L3_STCOL_OP_i_EVTINFOSEL_0" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x350++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_1,L3_STCOL_OP_i_EVTINFOSEL_1" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4A8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_2,L3_STCOL_OP_i_EVTINFOSEL_2" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_3,L3_STCOL_OP_i_EVTINFOSEL_3" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_0,L3_STCOL_OP_i_SEL_0" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_1,L3_STCOL_OP_i_SEL_1" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_2,L3_STCOL_OP_i_SEL_2" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_3,L3_STCOL_OP_i_SEL_3" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK2_STATCOLL9" base ad:0x4500A000 width 41. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_EN,L3_STCOL_EN" bitfld.long 0x0 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_SOFTEN,L3_STCOL_SOFTEN" bitfld.long 0x0 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_STCOL_IGNORESUSPEND,L3_STCOL_IGNORESUSPEND" bitfld.long 0x0 0. " IGNORESUSPEND ,Ignore suspend if set to one for suspend mechanism Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_STCOL_TRIGEN,L3_STCOL_TRIGEN" bitfld.long 0x0 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "L3_STCOL_REQEVT,L3_STCOL_REQEVT" bitfld.long 0x0 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "L3_STCOL_RSPEVT,L3_STCOL_RSPEVT" bitfld.long 0x0 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL0,L3_STCOL_EVTMUX_SEL0" bitfld.long 0x0 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL1,L3_STCOL_EVTMUX_SEL1" bitfld.long 0x0 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL2,L3_STCOL_EVTMUX_SEL2" bitfld.long 0x0 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL3,L3_STCOL_EVTMUX_SEL3" bitfld.long 0x0 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_STCOL_DUMP_IDENTIFIER,L3_STCOL_DUMP_IDENTIFIER" bitfld.long 0x0 0.--3. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_STCOL_DUMP_COLLECTTIME,L3_STCOL_DUMP_COLLECTTIME" hexmask.long 0x0 0.--31. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." group.byte 0x48++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVADDR,L3_STCOL_DUMP_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "L3_STCOL_DUMP_MSTADDR,L3_STCOL_DUMP_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVOFS,L3_STCOL_DUMP_SLVOFS" hexmask.long 0x0 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.byte 0x54++0x3 line.long 0x0 "L3_STCOL_DUMP_MODE,L3_STCOL_DUMP_MODE" bitfld.long 0x0 0. " DUMP_MODE_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x0 1. " DUMP_MODE_CONDITIONAL ,Define the stat conditional dump, if one a dump will be generated when alarm is trigged Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_STCOL_DUMP_SEND,L3_STCOL_DUMP_SEND" bitfld.long 0x0 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_STCOL_DUMP_DISABLE,L3_STCOL_DUMP_DISABLE" bitfld.long 0x0 0. " DUMP_DISABLE ,If 1, the dump frame will be disabled, but counters still active.This is typically used when counters monitoring is enabled Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_TRIG,L3_STCOL_DUMP_ALARM_TRIG" bitfld.long 0x0 0. " DUMP_ALARM_TRIG ,In Alarm Mode, is used to reset Alarm Type: Take. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MINVAL,L3_STCOL_DUMP_ALARM_MINVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MINVAL ,In Alarm Mode, used to trig an alert if any of counter value is less than AlarmMinVal Type: Control. Reset value: 0x0." group.byte 0x68++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MAXVAL,L3_STCOL_DUMP_ALARM_MAXVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MAXVAL ,In Alarm Mode, used to trig an alert if any of counter value is larger or equal to AlarmMaxVal Type: Control. Reset value: 0x0." group.byte 0x6C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE0,L3_STCOL_DUMP_ALARM_MODE0" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE0 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE1,L3_STCOL_DUMP_ALARM_MODE1" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE1 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE2,L3_STCOL_DUMP_ALARM_MODE2" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE2 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE3,L3_STCOL_DUMP_ALARM_MODE3" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE3 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT0,L3_STCOL_DUMP_CNT0" hexmask.long 0x0 0.--31. 1. " DUMP_CNT0 ,Dump counter value Type: Status. Reset value: X." group.byte 0x90++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT1,L3_STCOL_DUMP_CNT1" hexmask.long 0x0 0.--31. 1. " DUMP_CNT1 ,Dump counter value Type: Status. Reset value: X." group.byte 0x94++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT2,L3_STCOL_DUMP_CNT2" hexmask.long 0x0 0.--31. 1. " DUMP_CNT2 ,Dump counter value Type: Status. Reset value: X." group.byte 0x98++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT3,L3_STCOL_DUMP_CNT3" hexmask.long 0x0 0.--31. 1. " DUMP_CNT3 ,Dump counter value Type: Status. Reset value: X." group.byte 0xAC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_0,L3_STCOL_FILTER_i_GLOBALEN_0" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_1,L3_STCOL_FILTER_i_GLOBALEN_1" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x35C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_2,L3_STCOL_FILTER_i_GLOBALEN_2" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4B4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_3,L3_STCOL_FILTER_i_GLOBALEN_3" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_0,L3_STCOL_FILTER_i_ADDRMIN_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_1,L3_STCOL_FILTER_i_ADDRMIN_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_2,L3_STCOL_FILTER_i_ADDRMIN_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_3,L3_STCOL_FILTER_i_ADDRMIN_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_0,L3_STCOL_FILTER_i_ADDRMAX_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_1,L3_STCOL_FILTER_i_ADDRMAX_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_2,L3_STCOL_FILTER_i_ADDRMAX_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_3,L3_STCOL_FILTER_i_ADDRMAX_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_0,L3_STCOL_FILTER_i_ADDREN_0" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_1,L3_STCOL_FILTER_i_ADDREN_1" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_2,L3_STCOL_FILTER_i_ADDREN_2" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_3,L3_STCOL_FILTER_i_ADDREN_3" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_0,L3_STCOL_FILTER_i_EN_k_0" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_1,L3_STCOL_FILTER_i_EN_k_1" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x36C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_2,L3_STCOL_FILTER_i_EN_k_2" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_3,L3_STCOL_FILTER_i_EN_k_3" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_0,L3_STCOL_FILTER_i_MASK_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_1,L3_STCOL_FILTER_i_MASK_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x370++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_2,L3_STCOL_FILTER_i_MASK_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_3,L3_STCOL_FILTER_i_MASK_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_0,L3_STCOL_FILTER_i_MASK_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_1,L3_STCOL_FILTER_i_MASK_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x374++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_2,L3_STCOL_FILTER_i_MASK_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_3,L3_STCOL_FILTER_i_MASK_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0,L3_STCOL_FILTER_i_MASK_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1,L3_STCOL_FILTER_i_MASK_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x378++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2,L3_STCOL_FILTER_i_MASK_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3,L3_STCOL_FILTER_i_MASK_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xCC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0,L3_STCOL_FILTER_i_MASK_m_SLVADDR_0" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1,L3_STCOL_FILTER_i_MASK_m_SLVADDR_1" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x37C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2,L3_STCOL_FILTER_i_MASK_m_SLVADDR_2" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x4D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3,L3_STCOL_FILTER_i_MASK_m_SLVADDR_3" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_0,L3_STCOL_FILTER_i_MASK_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_1,L3_STCOL_FILTER_i_MASK_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_2,L3_STCOL_FILTER_i_MASK_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_3,L3_STCOL_FILTER_i_MASK_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x388++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_0,L3_STCOL_FILTER_i_MATCH_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_1,L3_STCOL_FILTER_i_MATCH_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_2,L3_STCOL_FILTER_i_MATCH_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_3,L3_STCOL_FILTER_i_MATCH_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_0,L3_STCOL_FILTER_i_MATCH_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_1,L3_STCOL_FILTER_i_MATCH_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_2,L3_STCOL_FILTER_i_MATCH_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4EC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_3,L3_STCOL_FILTER_i_MATCH_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xEC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x244++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x39C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x4F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_0,L3_STCOL_FILTER_i_MATCH_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_1,L3_STCOL_FILTER_i_MATCH_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x3A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_2,L3_STCOL_FILTER_i_MATCH_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_3,L3_STCOL_FILTER_i_MATCH_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xF4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x24C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xF8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x3A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0,L3_STCOL_OP_i_THRESHOLD_MINVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x348++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1,L3_STCOL_OP_i_THRESHOLD_MINVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2,L3_STCOL_OP_i_THRESHOLD_MINVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5F8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3,L3_STCOL_OP_i_THRESHOLD_MINVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0,L3_STCOL_OP_i_THRESHOLD_MAXVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x34C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1,L3_STCOL_OP_i_THRESHOLD_MAXVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2,L3_STCOL_OP_i_THRESHOLD_MAXVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5FC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3,L3_STCOL_OP_i_THRESHOLD_MAXVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_0,L3_STCOL_OP_i_EVTINFOSEL_0" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x350++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_1,L3_STCOL_OP_i_EVTINFOSEL_1" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4A8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_2,L3_STCOL_OP_i_EVTINFOSEL_2" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_3,L3_STCOL_OP_i_EVTINFOSEL_3" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_0,L3_STCOL_OP_i_SEL_0" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_1,L3_STCOL_OP_i_SEL_1" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_2,L3_STCOL_OP_i_SEL_2" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_3,L3_STCOL_OP_i_SEL_3" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK2_STATCOLL5" base ad:0x45006000 width 41. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_SOFTEN,L3_STCOL_SOFTEN" bitfld.long 0x0 0. " SOFTEN ,Software enable for performance monitoring Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_STCOL_IGNORESUSPEND,L3_STCOL_IGNORESUSPEND" bitfld.long 0x0 0. " IGNORESUSPEND ,Ignore suspend if set to one for suspend mechanism Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_STCOL_TRIGEN,L3_STCOL_TRIGEN" bitfld.long 0x0 0. " TRIGEN ,TrigEn when set, it enable the external trigger start and stop Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "L3_STCOL_REQEVT,L3_STCOL_REQEVT" bitfld.long 0x0 0.--3. " REQEVT ,Req event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "L3_STCOL_RSPEVT,L3_STCOL_RSPEVT" bitfld.long 0x0 0.--3. " RSPEVT ,Rsp event select Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL0,L3_STCOL_EVTMUX_SEL0" bitfld.long 0x0 0.--2. " EVTMUX_SEL0 ,The select of the mux 0 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL1,L3_STCOL_EVTMUX_SEL1" bitfld.long 0x0 0.--2. " EVTMUX_SEL1 ,The select of the mux 1 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL2,L3_STCOL_EVTMUX_SEL2" bitfld.long 0x0 0.--2. " EVTMUX_SEL2 ,The select of the mux 2 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "L3_STCOL_EVTMUX_SEL3,L3_STCOL_EVTMUX_SEL3" bitfld.long 0x0 0.--2. " EVTMUX_SEL3 ,The select of the mux 3 Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_STCOL_DUMP_IDENTIFIER,L3_STCOL_DUMP_IDENTIFIER" bitfld.long 0x0 0.--3. " DUMP_IDENTIFIER ,Probe identifier Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_STCOL_DUMP_COLLECTTIME,L3_STCOL_DUMP_COLLECTTIME" hexmask.long 0x0 0.--31. 1. " DUMP_COLLECTTIME ,Number of cycle to wait between two statistics frame Type: Control. Reset value: 0x0." group.byte 0x48++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVADDR,L3_STCOL_DUMP_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " DUMP_SLVADDR ,Dump slave address Type: Control. Reset value: 0x19." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "L3_STCOL_DUMP_MSTADDR,L3_STCOL_DUMP_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " DUMP_MSTADDR ,Dump master address Type: Control. Reset value: 0xE0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "L3_STCOL_DUMP_SLVOFS,L3_STCOL_DUMP_SLVOFS" hexmask.long 0x0 0.--31. 1. " DUMP_SLVOFS ,Dump slave offset Type: Control. Reset value: 0x800." group.byte 0x54++0x3 line.long 0x0 "L3_STCOL_DUMP_MODE,L3_STCOL_DUMP_MODE" bitfld.long 0x0 0. " DUMP_MODE_MANUAL ,Define the dump mode: if != 0 the dump is controlled by the Send register. Type: Control. Reset value: 0x0." "0,1" bitfld.long 0x0 1. " DUMP_MODE_CONDITIONAL ,Define the stat conditional dump, if one a dump will be generated when alarm is trigged Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_STCOL_DUMP_SEND,L3_STCOL_DUMP_SEND" bitfld.long 0x0 0. " DUMP_SEND ,In manual mode, is used to send the dump content and initialize the counters. Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_STCOL_DUMP_DISABLE,L3_STCOL_DUMP_DISABLE" bitfld.long 0x0 0. " DUMP_DISABLE ,If 1, the dump frame will be disabled, but counters still active.This is typically used when counters monitoring is enabled Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_TRIG,L3_STCOL_DUMP_ALARM_TRIG" bitfld.long 0x0 0. " DUMP_ALARM_TRIG ,In Alarm Mode, is used to reset Alarm Type: Take. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MINVAL,L3_STCOL_DUMP_ALARM_MINVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MINVAL ,In Alarm Mode, used to trig an alert if any of counter value is less than AlarmMinVal Type: Control. Reset value: 0x0." group.byte 0x68++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MAXVAL,L3_STCOL_DUMP_ALARM_MAXVAL" hexmask.long 0x0 0.--31. 1. " DUMP_ALARM_MAXVAL ,In Alarm Mode, used to trig an alert if any of counter value is larger or equal to AlarmMaxVal Type: Control. Reset value: 0x0." group.byte 0x6C++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE0,L3_STCOL_DUMP_ALARM_MODE0" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE0 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE1,L3_STCOL_DUMP_ALARM_MODE1" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE1 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE2,L3_STCOL_DUMP_ALARM_MODE2" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE2 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "L3_STCOL_DUMP_ALARM_MODE3,L3_STCOL_DUMP_ALARM_MODE3" bitfld.long 0x0 0.--1. " DUMP_ALARM_MODE3 ,Alarm Mode off/min/max/both Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT0,L3_STCOL_DUMP_CNT0" hexmask.long 0x0 0.--31. 1. " DUMP_CNT0 ,Dump counter value Type: Status. Reset value: X." group.byte 0x90++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT1,L3_STCOL_DUMP_CNT1" hexmask.long 0x0 0.--31. 1. " DUMP_CNT1 ,Dump counter value Type: Status. Reset value: X." group.byte 0x94++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT2,L3_STCOL_DUMP_CNT2" hexmask.long 0x0 0.--31. 1. " DUMP_CNT2 ,Dump counter value Type: Status. Reset value: X." group.byte 0x98++0x3 line.long 0x0 "L3_STCOL_DUMP_CNT3,L3_STCOL_DUMP_CNT3" hexmask.long 0x0 0.--31. 1. " DUMP_CNT3 ,Dump counter value Type: Status. Reset value: X." group.byte 0xAC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_0,L3_STCOL_FILTER_i_GLOBALEN_0" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_1,L3_STCOL_FILTER_i_GLOBALEN_1" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x35C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_2,L3_STCOL_FILTER_i_GLOBALEN_2" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4B4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_GLOBALEN_3,L3_STCOL_FILTER_i_GLOBALEN_3" bitfld.long 0x0 0. " FILTER_i_GLOBALEN ,Filter global enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_0,L3_STCOL_FILTER_i_ADDRMIN_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_1,L3_STCOL_FILTER_i_ADDRMIN_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_2,L3_STCOL_FILTER_i_ADDRMIN_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMIN_3,L3_STCOL_FILTER_i_ADDRMIN_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMIN ,Min addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_0,L3_STCOL_FILTER_i_ADDRMAX_0" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_1,L3_STCOL_FILTER_i_ADDRMAX_1" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_2,L3_STCOL_FILTER_i_ADDRMAX_2" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDRMAX_3,L3_STCOL_FILTER_i_ADDRMAX_3" hexmask.long.tbyte 0x0 0.--22. 1. " FILTER0_ADDRMAX ,Max addr range Type: Control. Reset value: 0x0." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_0,L3_STCOL_FILTER_i_ADDREN_0" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_1,L3_STCOL_FILTER_i_ADDREN_1" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_2,L3_STCOL_FILTER_i_ADDREN_2" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_ADDREN_3,L3_STCOL_FILTER_i_ADDREN_3" bitfld.long 0x0 0. " FILTER0_ADDREN ,max filtering enable Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_0,L3_STCOL_FILTER_i_EN_k_0" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_1,L3_STCOL_FILTER_i_EN_k_1" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x36C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_2,L3_STCOL_FILTER_i_EN_k_2" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_EN_k_3,L3_STCOL_FILTER_i_EN_k_3" bitfld.long 0x0 0. " FILTER_i_EN0 ,Enable filter stage 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_0,L3_STCOL_FILTER_i_MASK_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_1,L3_STCOL_FILTER_i_MASK_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x370++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_2,L3_STCOL_FILTER_i_MASK_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RD_3,L3_STCOL_FILTER_i_MASK_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_0,L3_STCOL_FILTER_i_MASK_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_1,L3_STCOL_FILTER_i_MASK_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x374++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_2,L3_STCOL_FILTER_i_MASK_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_WR_3,L3_STCOL_FILTER_i_MASK_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_0,L3_STCOL_FILTER_i_MASK_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_1,L3_STCOL_FILTER_i_MASK_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x378++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_2,L3_STCOL_FILTER_i_MASK_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4D0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_MSTADDR_3,L3_STCOL_FILTER_i_MASK_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MASK_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xCC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_0,L3_STCOL_FILTER_i_MASK_m_SLVADDR_0" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_1,L3_STCOL_FILTER_i_MASK_m_SLVADDR_1" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x37C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_2,L3_STCOL_FILTER_i_MASK_m_SLVADDR_2" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x4D4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_SLVADDR_3,L3_STCOL_FILTER_i_MASK_m_SLVADDR_3" hexmask.long.byte 0x0 0.--6. 1. " FILTER_i_MASK_m_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_0,L3_STCOL_FILTER_i_MASK_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_1,L3_STCOL_FILTER_i_MASK_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_2,L3_STCOL_FILTER_i_MASK_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_ERR_3,L3_STCOL_FILTER_i_MASK_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MASK_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x388++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x4E0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MASK_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_0,L3_STCOL_FILTER_i_MATCH_m_RD_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_1,L3_STCOL_FILTER_i_MATCH_m_RD_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_2,L3_STCOL_FILTER_i_MATCH_m_RD_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4E8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RD_3,L3_STCOL_FILTER_i_MATCH_m_RD_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_RD ,Mask/Match of Rd Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_0,L3_STCOL_FILTER_i_MATCH_m_WR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_1,L3_STCOL_FILTER_i_MATCH_m_WR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_2,L3_STCOL_FILTER_i_MATCH_m_WR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4EC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_WR_3,L3_STCOL_FILTER_i_MATCH_m_WR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_WR ,Mask/Match of Wr Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xE8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_0" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_1" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_2" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4F0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3,L3_STCOL_FILTER_i_MATCH_m_MSTADDR_3" hexmask.long.byte 0x0 0.--7. 1. " FILTER_i_MATCH_m_MSTADDR ,Mask/Match of MstAddr Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xEC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_0" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x244++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_1" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x39C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_2" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x4F4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3,L3_STCOL_FILTER_i_MATCH_m_SLVADDR_3" bitfld.long 0x0 0.--4. " FILTER0_MATCH0_SLVADDR ,Mask/Match of SlvAddr Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_0,L3_STCOL_FILTER_i_MATCH_m_ERR_0" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_1,L3_STCOL_FILTER_i_MATCH_m_ERR_1" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x3A0++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_2,L3_STCOL_FILTER_i_MATCH_m_ERR_2" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x4F8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_ERR_3,L3_STCOL_FILTER_i_MATCH_m_ERR_3" bitfld.long 0x0 0. " FILTER_i_MATCH_m_ERR ,Mask/Match of Err Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xF8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_0" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_1" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x3A8++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_2" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_RSPUSERINFO_3" bitfld.long 0x0 0.--2. " FILTER_i_MASK_m_RSPUSERINFO ,Mask/Match of RspUserInfo Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_0,L3_STCOL_OP_i_THRESHOLD_MINVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x348++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_1,L3_STCOL_OP_i_THRESHOLD_MINVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A0++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_2,L3_STCOL_OP_i_THRESHOLD_MINVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5F8++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MINVAL_3,L3_STCOL_OP_i_THRESHOLD_MINVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MINVAL ,Min value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_0,L3_STCOL_OP_i_THRESHOLD_MAXVAL_0" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x34C++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_1,L3_STCOL_OP_i_THRESHOLD_MAXVAL_1" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x4A4++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_2,L3_STCOL_OP_i_THRESHOLD_MAXVAL_2" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x5FC++0x3 line.long 0x0 "L3_STCOL_OP_i_THRESHOLD_MAXVAL_3,L3_STCOL_OP_i_THRESHOLD_MAXVAL_3" hexmask.long.word 0x0 0.--12. 1. " OP_i_THRESHOLD_MAXVAL ,Max value Type: Control. Reset value: 0x0." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_0,L3_STCOL_OP_i_EVTINFOSEL_0" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x350++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_1,L3_STCOL_OP_i_EVTINFOSEL_1" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x4A8++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_2,L3_STCOL_OP_i_EVTINFOSEL_2" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "L3_STCOL_OP_i_EVTINFOSEL_3,L3_STCOL_OP_i_EVTINFOSEL_3" bitfld.long 0x0 0.--1. " OP_i_EVTINFOSEL ,Select event info data to add to counter (len/press or latency) Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_0,L3_STCOL_OP_i_SEL_0" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_1,L3_STCOL_OP_i_SEL_1" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x4AC++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_2,L3_STCOL_OP_i_SEL_2" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "L3_STCOL_OP_i_SEL_3,L3_STCOL_OP_i_SEL_3" bitfld.long 0x0 0.--3. " OP_i_SEL ,Select logical operation Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xF4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_0" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x24C++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_1" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_2" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3,L3_STCOL_FILTER_i_MATCH_m_REQUSERINFO_3" hexmask.long 0x0 0.--27. 1. " FILTER_i_MASK_m_REQUSERINFO ,Mask/Match of ReqUserInfo Type: Control. Reset value: 0x0." bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_EN,L3_STCOL_EN" bitfld.long 0x0 0. " EN ,Enable performance monitoring, this will also shut down the clock if En = 0 Type: Control. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_MMU2_BW_REGULATOR" base ad:0x44803B00 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_EVE1_TC0_BW_REGULATOR" base ad:0x44804200 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_EVE2_TC0_BW_REGULATOR" base ad:0x44804300 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_EVE3_TC0_BW_REGULATOR" base ad:0x44804400 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_EVE4_TC0_BW_REGULATOR" base ad:0x44804500 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_EVE1_TC1_BW_REGULATOR" base ad:0x44804600 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_EVE2_TC1_BW_REGULATOR" base ad:0x44804700 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_EVE3_TC1_BW_REGULATOR" base ad:0x44804800 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_EVE4_TC1_BW_REGULATOR" base ad:0x44804900 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_DSP2_EDMA_BW_REGULATOR" base ad:0x44804A00 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_DSP1_EDMA_BW_REGULATOR" base ad:0x44804B00 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_DSP1_MDMA_BW_REGULATOR" base ad:0x44804C00 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_DSP2_MDMA_BW_REGULATOR" base ad:0x44804D00 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_BB2D_P1_BW_REGULATOR" base ad:0x44804E00 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_IVA_BW_REGULATOR" base ad:0x44805000 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_BB2D_P2_BW_REGULATOR" base ad:0x44805100 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_GPU_P1_BW_REGULATOR" base ad:0x44805200 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_GPU_P2_BW_REGULATOR" base ad:0x44805300 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_PCIESS2_BW_REGULATOR" base ad:0x44805400 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_PCIESS1_BW_REGULATOR" base ad:0x44805500 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_2_GMAC_SW_BW_REGULATOR" base ad:0x44805600 width 39. group.byte 0x0++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_COREREG,L3_BW_REGULATOR_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x31." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG,L3_BW_REGULATOR_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_REGULATOR_BANDWIDTH,L3_BW_REGULATOR_BANDWIDTH" hexmask.long.word 0x0 0.--15. 1. " BANDWIDTH ,Bandwidth in bytes per second. Type: Control. Reset value: 0x0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "L3_BW_REGULATOR_WATERMARK,L3_BW_REGULATOR_WATERMARK" hexmask.long.word 0x0 0.--11. 1. " WATERMARK ,Peak permissible bandwidth, in bytes. Type: Control. Reset value: 0x1." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_BW_REGULATOR_PRESS,L3_BW_REGULATOR_PRESS" bitfld.long 0x0 0.--1. " PRESS_HIGH ,Pressure value inserted if the measured bandwidth is under the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x1." "0,1,2,3" bitfld.long 0x0 2.--3. " PRESS_LOW ,Pressure value inserted if the measured bandwidth is over the watermark. The pressure is bar graph encoded. Type: Control. Reset value: 0x0." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "L3_BW_REGULATOR_CLEARHISTORY,L3_BW_REGULATOR_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1_1" base ad:0x44803500 width 34. group.byte 0x0++0x3 line.long 0x0 "L3_FLAGMUX_STDHOSTHDR_COREREG,L3_FLAGMUX_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG,L3_FLAGMUX_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_FLAGMUX_MASK0,L3_FLAGMUX_MASK0" hexmask.long 0x0 0.--31. 1. " MASK0 ,Mask flag inputs 0 Type: Control." group.byte 0xC++0x3 line.long 0x0 "L3_FLAGMUX_REGERR0,L3_FLAGMUX_REGERR0" hexmask.long 0x0 0.--31. 1. " REGERR0 ,Flag inputs 0 Type: Status. Reset value: X." group.byte 0x10++0x3 line.long 0x0 "L3_FLAGMUX_MASK1,L3_FLAGMUX_MASK1" hexmask.long 0x0 0.--31. 1. " MASK1 ,Mask flag inputs 1 Type: Control. Reset value: 0x7FFFFF." group.byte 0x14++0x3 line.long 0x0 "L3_FLAGMUX_REGERR1,L3_FLAGMUX_REGERR1" hexmask.long 0x0 0.--31. 1. " REGERR1 ,Flag inputs 1 Type: Status. Reset value: X." width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1_2" base ad:0x44803600 width 34. group.byte 0x0++0x3 line.long 0x0 "L3_FLAGMUX_STDHOSTHDR_COREREG,L3_FLAGMUX_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG,L3_FLAGMUX_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_FLAGMUX_MASK0,L3_FLAGMUX_MASK0" hexmask.long 0x0 0.--31. 1. " MASK0 ,Mask flag inputs 0 Type: Control." group.byte 0xC++0x3 line.long 0x0 "L3_FLAGMUX_REGERR0,L3_FLAGMUX_REGERR0" hexmask.long 0x0 0.--31. 1. " REGERR0 ,Flag inputs 0 Type: Status. Reset value: X." group.byte 0x10++0x3 line.long 0x0 "L3_FLAGMUX_MASK1,L3_FLAGMUX_MASK1" hexmask.long 0x0 0.--31. 1. " MASK1 ,Mask flag inputs 1 Type: Control. Reset value: 0x7FFFFF." group.byte 0x14++0x3 line.long 0x0 "L3_FLAGMUX_REGERR1,L3_FLAGMUX_REGERR1" hexmask.long 0x0 0.--31. 1. " REGERR1 ,Flag inputs 1 Type: Status. Reset value: X." width 0x0B tree.end tree "CLK2_FLAGMUX_CLK2_1" base ad:0x45000200 width 34. group.byte 0x0++0x3 line.long 0x0 "L3_FLAGMUX_STDHOSTHDR_COREREG,L3_FLAGMUX_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_FLAGMUX_STDHOSTHDR_VERSIONREG,L3_FLAGMUX_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_FLAGMUX_MASK0,L3_FLAGMUX_MASK0" hexmask.long 0x0 0.--31. 1. " MASK0 ,Mask flag inputs 0 Type: Control." group.byte 0xC++0x3 line.long 0x0 "L3_FLAGMUX_REGERR0,L3_FLAGMUX_REGERR0" hexmask.long 0x0 0.--31. 1. " REGERR0 ,Flag inputs 0 Type: Status. Reset value: X." group.byte 0x10++0x3 line.long 0x0 "L3_FLAGMUX_MASK1,L3_FLAGMUX_MASK1" hexmask.long 0x0 0.--31. 1. " MASK1 ,Mask flag inputs 1 Type: Control. Reset value: 0x7FFFFF." group.byte 0x14++0x3 line.long 0x0 "L3_FLAGMUX_REGERR1,L3_FLAGMUX_REGERR1" hexmask.long 0x0 0.--31. 1. " REGERR1 ,Flag inputs 1 Type: Status. Reset value: X." width 0x0B tree.end tree "TPTC_FW" base ad:0x4A163000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k_0,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x10++0x3 line.long 0x0 "ERROR_LOG_k_1,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x14++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "CLK1_HOST_CLK1_1" base ad:0x44000000 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_HOST_STDHOSTHDR_COREREG,L3_HOST_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x1A." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_HOST_STDHOSTHDR_VERSIONREG,L3_HOST_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_HOST_STDHOSTHDR_MAINCTLREG,L3_HOST_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Fault is asserted when the Fault Control register field indicates a Fault, and de-asserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SVRTSTDLVL,L3_HOST_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL,L3_HOST_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "L3_HOST_STDERRLOG_MAIN,L3_HOST_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ," bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_HOST_STDERRLOG_HDR,L3_HOST_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_HOST_STDERRLOG_MSTADDR,L3_HOST_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SLVADDR,L3_HOST_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "L3_HOST_STDERRLOG_INFO,L3_HOST_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SLVOFSLSB,L3_HOST_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SLVOFSMSB,L3_HOST_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR,L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO,L3_HOST_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_WR,L3_HOST_STDERRLOG_CUSTOMINFO_WR" bitfld.long 0x0 0. " STDERRLOG_CUSTOMINFO_WR ,Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR,L3_HOST_STDERRLOG_CUSTOMINFO_ADDR" hexmask.long.tbyte 0x0 0.--20. 1. " STDERRLOG_CUSTOMINFO_ADDR ,Type: Status. Reset value: X." hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR,L3_HOST_STDERRLOG_CUSTOMINFO_DECERR" bitfld.long 0x0 0. " STDERRLOG_CUSTOMINFO_DECERR ,Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_HOST_CLK1_2" base ad:0x44800000 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_HOST_STDHOSTHDR_COREREG,L3_HOST_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x1A." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_HOST_STDHOSTHDR_VERSIONREG,L3_HOST_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_HOST_STDHOSTHDR_MAINCTLREG,L3_HOST_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Fault is asserted when the Fault Control register field indicates a Fault, and de-asserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SVRTSTDLVL,L3_HOST_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL,L3_HOST_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "L3_HOST_STDERRLOG_MAIN,L3_HOST_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ," bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_HOST_STDERRLOG_HDR,L3_HOST_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_HOST_STDERRLOG_MSTADDR,L3_HOST_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SLVADDR,L3_HOST_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "L3_HOST_STDERRLOG_INFO,L3_HOST_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SLVOFSLSB,L3_HOST_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SLVOFSMSB,L3_HOST_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR,L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO,L3_HOST_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_WR,L3_HOST_STDERRLOG_CUSTOMINFO_WR" bitfld.long 0x0 0. " STDERRLOG_CUSTOMINFO_WR ,Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR,L3_HOST_STDERRLOG_CUSTOMINFO_ADDR" hexmask.long.tbyte 0x0 0.--20. 1. " STDERRLOG_CUSTOMINFO_ADDR ,Type: Status. Reset value: X." hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR,L3_HOST_STDERRLOG_CUSTOMINFO_DECERR" bitfld.long 0x0 0. " STDERRLOG_CUSTOMINFO_DECERR ,Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK2_HOST_CLK2_1" base ad:0x45000000 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_HOST_STDHOSTHDR_COREREG,L3_HOST_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x1A." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_HOST_STDHOSTHDR_VERSIONREG,L3_HOST_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_HOST_STDHOSTHDR_MAINCTLREG,L3_HOST_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Fault is asserted when the Fault Control register field indicates a Fault, and de-asserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SVRTSTDLVL,L3_HOST_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SVRTCUSTOMLVL,L3_HOST_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "L3_HOST_STDERRLOG_MAIN,L3_HOST_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ," bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_HOST_STDERRLOG_HDR,L3_HOST_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_HOST_STDERRLOG_MSTADDR,L3_HOST_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SLVADDR,L3_HOST_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "L3_HOST_STDERRLOG_INFO,L3_HOST_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SLVOFSLSB,L3_HOST_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_HOST_STDERRLOG_SLVOFSMSB,L3_HOST_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR,L3_HOST_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_INFO,L3_HOST_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_WR,L3_HOST_STDERRLOG_CUSTOMINFO_WR" bitfld.long 0x0 0. " STDERRLOG_CUSTOMINFO_WR ,Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_ADDR,L3_HOST_STDERRLOG_CUSTOMINFO_ADDR" hexmask.long.tbyte 0x0 0.--20. 1. " STDERRLOG_CUSTOMINFO_ADDR ,Type: Status. Reset value: X." hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "L3_HOST_STDERRLOG_CUSTOMINFO_DECERR,L3_HOST_STDERRLOG_CUSTOMINFO_DECERR" bitfld.long 0x0 0. " STDERRLOG_CUSTOMINFO_DECERR ,Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "IPU1_FW" base ad:0x4A15B000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "IPU2_FW" base ad:0x4A218000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "IVA_SL2IF_FW" base ad:0x4A21E000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1" base ad:0x44000000 width 43. group.byte 0x805700++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_COREREG,L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x805704++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_VERSIONREG,L3_FLAGMUX_TIMEOUT1_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x805708++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT1_MASK0,L3_FLAGMUX_TIMEOUT1_MASK0" hexmask.long 0x0 0.--29. 1. " MASK0 ,mask flag inputs 0 Type: Control. Reset value: 0x0." bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x80570C++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT1_REGERR0,L3_FLAGMUX_TIMEOUT1_REGERR0" hexmask.long 0x0 0.--24. 1. " REGERR0 ,flag inputs 0 Type: Status. Reset value: X." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x805800++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_COREREG,L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x805804++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_VERSIONREG,L3_FLAGMUX_TIMEOUT2_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x805808++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT2_MASK0,L3_FLAGMUX_TIMEOUT2_MASK0" hexmask.long.tbyte 0x0 0.--20. 1. " MASK0 ,mask flag inputs 0 Type: Control. Reset value: 0x0." hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x80580C++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT2_REGERR0,L3_FLAGMUX_TIMEOUT2_REGERR0" hexmask.long.tbyte 0x0 0.--20. 1. " REGERR0 ,flag inputs 0 Type: Status. Reset value: X." hexmask.long.word 0x0 21.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIESS2_FW" base ad:0x4A159000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xC0++0x3 line.long 0x0 "START_REGION_i_4,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xD0++0x3 line.long 0x0 "START_REGION_i_5,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xE0++0x3 line.long 0x0 "START_REGION_i_6,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xF0++0x3 line.long 0x0 "START_REGION_i_7,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xC4++0x3 line.long 0x0 "END_REGION_i_4,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xD4++0x3 line.long 0x0 "END_REGION_i_5,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xE4++0x3 line.long 0x0 "END_REGION_i_6,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xF4++0x3 line.long 0x0 "END_REGION_i_7,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xC8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xD8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xE8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xF8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xCC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xDC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xEC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xFC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "CLK2_FLAGMUX_STATCOLL" base ad:0x45000500 width 32. group.byte 0x0++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_COREREG,L3_STCOL_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x3A. (When the instance is CLK2_FLAGMUX_STATCOLL reset value is 0x37)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "L3_STCOL_STDHOSTHDR_VERSIONREG,L3_STCOL_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x1." group.byte 0x8++0x3 line.long 0x0 "L3_STCOL_MASK0,L3_STCOL_MASK0" hexmask.long.word 0x0 0.--9. 1. " MASK0 ,mask flag inputs 0 Type: Control. Reset value: 0x7." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_STCOL_REGERR0,L3_STCOL_REGERR0" hexmask.long.word 0x0 0.--9. 1. " REGERR0 ,flag inputs 0 Type: Status. Reset value: X." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "EVE1_FW" base ad:0x4A151000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "EVE2_FW" base ad:0x4A153000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "EVE3_FW" base ad:0x4A155000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "EVE4_FW" base ad:0x4A157000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "VCP1_FW" base ad:0x4A15D000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "VCP2_FW" base ad:0x4A15F000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "EDMA_TPCC_FW" base ad:0x4A161000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "MCASP1_FW" base ad:0x4A167000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "MCASP2_FW" base ad:0x4A169000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "DSP1_SDMA_FW" base ad:0x4A171000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "DSP2_SDMA_FW" base ad:0x4A173000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "PRUSS1_FW" base ad:0x4A175000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "PRUSS2_FW" base ad:0x4A177000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "QSPI_FW" base ad:0x4A179000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "GPU_FW" base ad:0x4A214000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "BB2D_FW" base ad:0x4A21A000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "IVA_CONFIG_FW" base ad:0x4A220000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "DEBUGSS_CT_TBR_FW" base ad:0x4A224000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "L3_INSTR_FW" base ad:0x4A226000 width 30. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "CLK2_FLAGMUX_CLK2" base ad:0x45000000 width 42. group.byte 0x400++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT_STDHOSTHDR_COREREG,L3_FLAGMUX_TIMEOUT_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x404++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT_STDHOSTHDR_VERSIONREG,L3_FLAGMUX_TIMEOUT_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x408++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT_MASK0,L3_FLAGMUX_TIMEOUT_MASK0" bitfld.long 0x0 0.--1. " MASK0 ,mask flag inputs 0 Type: Control. Reset value: 0x0." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40C++0x3 line.long 0x0 "L3_FLAGMUX_TIMEOUT_REGERR0,L3_FLAGMUX_TIMEOUT_REGERR0" bitfld.long 0x0 0.--1. " REGERR0 ,flag inputs 0 Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_FLAGMUX_CLK1MERGE" base ad:0x44000000 width 44. group.byte 0x800400++0x3 line.long 0x0 "L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_COREREG,L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x37." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x800404++0x3 line.long 0x0 "L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_VERSIONREG,L3_FLAGMUX_CLK1MERGE_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x800408++0x3 line.long 0x0 "L3_FLAGMUX_CLK1MERGE_MASK0,L3_FLAGMUX_CLK1MERGE_MASK0" bitfld.long 0x0 0.--1. " MASK0 ,Mask flag inputs 0 Type: Control. Reset value: 0x3" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x80040C++0x3 line.long 0x0 "L3_FLAGMUX_CLK1MERGE_REGERR0,L3_FLAGMUX_CLK1MERGE_REGERR0" bitfld.long 0x0 0.--1. " REGERR0 ,Flag inputs 0 Type: Control. Reset value: X" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x800410++0x3 line.long 0x0 "L3_FLAGMUX_CLK1MERGE_MASK1,L3_FLAGMUX_CLK1MERGE_MASK1" bitfld.long 0x0 0.--1. " MASK1 ,Mask flag inputs 0 Type: Control. Reset value: 0x3" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x800414++0x3 line.long 0x0 "L3_FLAGMUX_CLK1MERGE_REGERR1,L3_FLAGMUX_CLK1MERGE_REGERR1" bitfld.long 0x0 0.--1. " REGERR1 ,Flag inputs 0 Type: Control. Reset value: X" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," width 0x0B tree.end tree "MCASP3_FW" base ad:0x4A16B000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xC8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xD8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xE8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xF8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xCC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xDC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xEC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xFC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "MA_MPU_NTTP_FW" base ad:0x4A20A000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k_0,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x10++0x3 line.long 0x0 "ERROR_LOG_k_1,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x14++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xC0++0x3 line.long 0x0 "START_REGION_i_4,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xD0++0x3 line.long 0x0 "START_REGION_i_5,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xE0++0x3 line.long 0x0 "START_REGION_i_6,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xF0++0x3 line.long 0x0 "START_REGION_i_7,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xC4++0x3 line.long 0x0 "END_REGION_i_4,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xD4++0x3 line.long 0x0 "END_REGION_i_5,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xE4++0x3 line.long 0x0 "END_REGION_i_6,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xF4++0x3 line.long 0x0 "END_REGION_i_7,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xC8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xD8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xE8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xF8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xCC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xDC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xEC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xFC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "EMIF_FW" base ad:0x4A20C000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k_0,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x10++0x3 line.long 0x0 "ERROR_LOG_k_1,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k_0,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x14++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k_1,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xC0++0x3 line.long 0x0 "START_REGION_i_4,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xD0++0x3 line.long 0x0 "START_REGION_i_5,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xE0++0x3 line.long 0x0 "START_REGION_i_6,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xF0++0x3 line.long 0x0 "START_REGION_i_7,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xC4++0x3 line.long 0x0 "END_REGION_i_4,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xD4++0x3 line.long 0x0 "END_REGION_i_5,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xE4++0x3 line.long 0x0 "END_REGION_i_6,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xF4++0x3 line.long 0x0 "END_REGION_i_7,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xC8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xD8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xE8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xF8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xCC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xDC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xEC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xFC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "GPMC_TARG" base ad:0x44000100 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DMM_P1_TARG" base ad:0x44000200 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_SDMA_TARG" base ad:0x44000300 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_CFG_TARG" base ad:0x44000500 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_SDMA_TARG" base ad:0x44000600 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "VCP1_TARG" base ad:0x44000700 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "VCP2_TARG" base ad:0x44000800 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "BB2D_TARG" base ad:0x44000900 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE1_TARG" base ad:0x44000A00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE2_TARG" base ad:0x44000B00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE3_TARG" base ad:0x44000C00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE4_TARG" base ad:0x44000D00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_PER3_P3_TARG" base ad:0x44000E00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "OCMC_RAM1_TARG" base ad:0x44000F00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "IPU1_TARG" base ad:0x44001000 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "IPU2_TARG" base ad:0x44001100 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "GPU_TARG" base ad:0x44001200 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DMM_P2_TARG" base ad:0x44001300 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "PRUSS1_TARG" base ad:0x44001400 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "PRUSS2_TARG" base ad:0x44001500 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "IVA_CONFIG_TARG" base ad:0x44001600 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "OCMC_RAM2_TARG" base ad:0x44001700 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "IVA_SL2IF_TARG" base ad:0x44001800 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "OCMC_RAM3_TARG" base ad:0x44001900 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_PER1_P1_TARG" base ad:0x44001C00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_WKUP_TARG" base ad:0x44001D00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_PER1_P2_TARG" base ad:0x44001F00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "TPCC_TARG" base ad:0x44002000 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_PER1_P3_TARG" base ad:0x44002100 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MMU1_TARG" base ad:0x44002200 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_PER2_P1_TARG" base ad:0x44002300 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_PER2_P2_TARG" base ad:0x44002400 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_PER2_P3_TARG" base ad:0x44002500 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_PER3_P1_TARG" base ad:0x44002600 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L4_PER3_P2_TARG" base ad:0x44002700 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MMU2_TARG" base ad:0x44002800 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSS_TARG" base ad:0x44002900 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "TPTC2_TARG" base ad:0x44002B00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "TPTC1_TARG" base ad:0x44002E00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCASP1_TARG" base ad:0x44002F00 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCASP2_TARG" base ad:0x44003000 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCASP3_TARG" base ad:0x44003100 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "PCIE1_TARG" base ad:0x44003700 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "PCIE2_TARG" base ad:0x44003800 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "QSPI_TARG" base ad:0x44003900 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "L3_INSTR" base ad:0x45000100 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DEBUGSS_CT_TBR_TARG" base ad:0x45000300 width 38. group.byte 0x0++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_COREREG,L3_TARG_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constant reporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constant reporting a vendor-specific core generator code. Type: Constant. Reset value: 0x13." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_VERSIONREG,L3_TARG_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constant reporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_MAINCTLREG,L3_TARG_STDHOSTHDR_MAINCTLREG" bitfld.long 0x0 0. " STDHOSTHDR_MAINCTLREG_EN ,Sets the global core enable. Note: A disabled master does not generate any NTTP requests, and a disabled slave replies with an error packet to any request it receives. Type: Control. Reset value: 0x1." "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " STDHOSTHDR_MAINCTLREG_FLT ,Asserted when a Fault condition is detected: if the unit includes Error Logging, Flt is asserted when the FltCnt register field indicates a Fault, and deasserted when FltCnt is reset. If no Error Logging is implemented, this bit becomes unit-dependent. In all cases, Flt bit and Flt pin (service network) have the same logical level. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 3. " STDHOSTHDR_MAINCTLREG_CM ,Reserved for internal testing. Must be set to 0. Type: Control. Reset value: 0x0." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "L3_TARG_STDHOSTHDR_NTTPADDR_0,L3_TARG_STDHOSTHDR_NTTPADDR_0" hexmask.long.byte 0x0 0.--6. 1. " STDHOSTHDR_NTTPADDR_0 ,Shows the Rx port address. Type: Control. Reset value: 0x15." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTSTDLVL,L3_TARG_STDERRLOG_SVRTSTDLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTSTDLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SVRTCUSTOMLVL,L3_TARG_STDERRLOG_SVRTCUSTOMLVL" bitfld.long 0x0 0.--1. " STDERRLOG_SVRTCUSTOMLVL_0 ,Severity level parameters Type: Control. Reset value: 0x2." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MAIN,L3_TARG_STDERRLOG_MAIN" bitfld.long 0x0 0. " STDERRLOG_MAIN_ERRLOGVLD ,Error Logging Valid. Asserted when logging information is valid(indicates that an error has been logged). Type: Status. Reset value: X." "0,1" bitfld.long 0x0 1. " STDERRLOG_MAIN_ERRTYPE ,Indicates logging type. Type: Status. Reset value: X." "0,1" textline " " hexmask.long.word 0x0 2.--17. 1. " RESERVED ,Reserved" bitfld.long 0x0 18. " STDERRLOG_MAIN_ERRCNT ,Asserted when at least one error with severity level ERROR is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" textline " " bitfld.long 0x0 19. " STDERRLOG_MAIN_FLTCNT ,Asserted when at least one error with severity level FAULT is detected. Reset when written to 1. Type: Take. Reset value: 0x0." "0,1" hexmask.long.word 0x0 20.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " STDERRLOG_MAIN_CLRLOG ,Clears 'Error Logging Valid' bit when written to 1. Type: Give_AutoCleared. Reset value: 0x0." "0,1" group.byte 0x4C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_HDR,L3_TARG_STDERRLOG_HDR" bitfld.long 0x0 0.--3. " STDERRLOG_HDR_OPCODE ,Opcode of the logged packet. Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 6.--7. " STDERRLOG_HDR_PRESSURE ,Pressure field of the logged packet. Type: Status. Reset value: X." "0,1,2,3" bitfld.long 0x0 8.--10. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " STDERRLOG_HDR_ERR ,Err bit of the logged packet. Type: Status. Reset value: X." "0,1" bitfld.long 0x0 12.--15. " STDERRLOG_HDR_STOPOFSWRPSZ ,StopOfs or WrapSize field of the logged packet (meaning depends on Wrp bit of logged opcode). Type: Status. Reset value: X." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--27. 1. " STDERRLOG_HDR_LEN1 ,This field contains the number of payload cell(s) minus one of the logged packet. Type: Status. Reset value: X." textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "L3_TARG_STDERRLOG_MSTADDR,L3_TARG_STDERRLOG_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_MSTADDR ,Master Address field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVADDR,L3_TARG_STDERRLOG_SLVADDR" hexmask.long.byte 0x0 0.--6. 1. " STDERRLOG_SLVADDR ,Slave Address field of the logged packet. Type: Status. Reset value: X." hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "L3_TARG_STDERRLOG_INFO,L3_TARG_STDERRLOG_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_INFO ,Info field of the logged packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x5C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSLSB,L3_TARG_STDERRLOG_SLVOFSLSB" hexmask.long 0x0 0.--31. 1. " STDERRLOG_SLVOFSLSB ,LSB of the 'slave offset' field, concatenated with 'start offset' field of the logged packet. Type: Status. Reset value: X." group.byte 0x60++0x3 line.long 0x0 "L3_TARG_STDERRLOG_SLVOFSMSB,L3_TARG_STDERRLOG_SLVOFSMSB" bitfld.long 0x0 0. " STDERRLOG_SLVOFSMSB ,MSB of the 'slave offset' field of the logged packet (according to NTTP packet format, this register field may exceed the actual 'slave offset' size. Unused bits are stuck at 0, if any). Type: Status. Reset value: X." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x64++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_INFO,L3_TARG_STDERRLOG_CUSTOMINFO_INFO" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_INFO ,Info field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x68++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR,L3_TARG_STDERRLOG_CUSTOMINFO_MSTADDR" hexmask.long.byte 0x0 0.--7. 1. " STDERRLOG_CUSTOMINFO_MSTADDR ,MstAddr field of the response packet. Type: Status. Reset value: X." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x6C++0x3 line.long 0x0 "L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE,L3_TARG_STDERRLOG_CUSTOMINFO_OPCODE" bitfld.long 0x0 0.--1. " STDERRLOG_CUSTOMINFO_OPCODE ,Opcode of the response packet. Type: Status. Reset value: X." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "L3_TARG_ADDRSPACESIZELOG,L3_TARG_ADDRSPACESIZELOG" bitfld.long 0x0 0.--4. " ADDRSPACESIZELOG ,The address space size is equal to 2**AddrSpaceSizeLog * 4K in bytes. Type: Control. Reset value: 0x1F." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "OCMC_RAM2_FW" base ad:0x4A20E000 width 33. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xC0++0x3 line.long 0x0 "START_REGION_i_4,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xD0++0x3 line.long 0x0 "START_REGION_i_5,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xE0++0x3 line.long 0x0 "START_REGION_i_6,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xF0++0x3 line.long 0x0 "START_REGION_i_7,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x100++0x3 line.long 0x0 "START_REGION_i_8,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x110++0x3 line.long 0x0 "START_REGION_i_9,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x120++0x3 line.long 0x0 "START_REGION_i_10,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x130++0x3 line.long 0x0 "START_REGION_i_11,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x140++0x3 line.long 0x0 "START_REGION_i_12,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x150++0x3 line.long 0x0 "START_REGION_i_13,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x160++0x3 line.long 0x0 "START_REGION_i_14,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x170++0x3 line.long 0x0 "START_REGION_i_15,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xC4++0x3 line.long 0x0 "END_REGION_i_4,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xD4++0x3 line.long 0x0 "END_REGION_i_5,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xE4++0x3 line.long 0x0 "END_REGION_i_6,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xF4++0x3 line.long 0x0 "END_REGION_i_7,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x104++0x3 line.long 0x0 "END_REGION_i_8,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x114++0x3 line.long 0x0 "END_REGION_i_9,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x124++0x3 line.long 0x0 "END_REGION_i_10,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x134++0x3 line.long 0x0 "END_REGION_i_11,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x144++0x3 line.long 0x0 "END_REGION_i_12,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x154++0x3 line.long 0x0 "END_REGION_i_13,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x164++0x3 line.long 0x0 "END_REGION_i_14,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x174++0x3 line.long 0x0 "END_REGION_i_15,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xC8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xD8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xE8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xF8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x108++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x118++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x128++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_10,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x138++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_11,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x148++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_12,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x158++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_13,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x168++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_14,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x178++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_15,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xCC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xDC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xEC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xFC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_10,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_11,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x14C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_12,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x15C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_13,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x16C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_14,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x17C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_15,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "OCMC_RAM1_FW" base ad:0x4A212000 width 33. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xC0++0x3 line.long 0x0 "START_REGION_i_4,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xD0++0x3 line.long 0x0 "START_REGION_i_5,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xE0++0x3 line.long 0x0 "START_REGION_i_6,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xF0++0x3 line.long 0x0 "START_REGION_i_7,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x100++0x3 line.long 0x0 "START_REGION_i_8,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x110++0x3 line.long 0x0 "START_REGION_i_9,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x120++0x3 line.long 0x0 "START_REGION_i_10,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x130++0x3 line.long 0x0 "START_REGION_i_11,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x140++0x3 line.long 0x0 "START_REGION_i_12,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x150++0x3 line.long 0x0 "START_REGION_i_13,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x160++0x3 line.long 0x0 "START_REGION_i_14,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x170++0x3 line.long 0x0 "START_REGION_i_15,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xC4++0x3 line.long 0x0 "END_REGION_i_4,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xD4++0x3 line.long 0x0 "END_REGION_i_5,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xE4++0x3 line.long 0x0 "END_REGION_i_6,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xF4++0x3 line.long 0x0 "END_REGION_i_7,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x104++0x3 line.long 0x0 "END_REGION_i_8,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x114++0x3 line.long 0x0 "END_REGION_i_9,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x124++0x3 line.long 0x0 "END_REGION_i_10,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x134++0x3 line.long 0x0 "END_REGION_i_11,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x144++0x3 line.long 0x0 "END_REGION_i_12,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x154++0x3 line.long 0x0 "END_REGION_i_13,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x164++0x3 line.long 0x0 "END_REGION_i_14,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x174++0x3 line.long 0x0 "END_REGION_i_15,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xC8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xD8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xE8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xF8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x108++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x118++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x128++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_10,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x138++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_11,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x148++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_12,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x158++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_13,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x168++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_14,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x178++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_15,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xCC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xDC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xEC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xFC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_10,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_11,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x14C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_12,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x15C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_13,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x16C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_14,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x17C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_15,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "OCMC_RAM3_FW" base ad:0x4A22A000 width 33. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xC0++0x3 line.long 0x0 "START_REGION_i_4,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xD0++0x3 line.long 0x0 "START_REGION_i_5,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xE0++0x3 line.long 0x0 "START_REGION_i_6,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xF0++0x3 line.long 0x0 "START_REGION_i_7,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x100++0x3 line.long 0x0 "START_REGION_i_8,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x110++0x3 line.long 0x0 "START_REGION_i_9,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x120++0x3 line.long 0x0 "START_REGION_i_10,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x130++0x3 line.long 0x0 "START_REGION_i_11,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x140++0x3 line.long 0x0 "START_REGION_i_12,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x150++0x3 line.long 0x0 "START_REGION_i_13,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x160++0x3 line.long 0x0 "START_REGION_i_14,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x170++0x3 line.long 0x0 "START_REGION_i_15,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xC4++0x3 line.long 0x0 "END_REGION_i_4,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xD4++0x3 line.long 0x0 "END_REGION_i_5,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xE4++0x3 line.long 0x0 "END_REGION_i_6,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xF4++0x3 line.long 0x0 "END_REGION_i_7,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x104++0x3 line.long 0x0 "END_REGION_i_8,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x114++0x3 line.long 0x0 "END_REGION_i_9,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x124++0x3 line.long 0x0 "END_REGION_i_10,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x134++0x3 line.long 0x0 "END_REGION_i_11,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x144++0x3 line.long 0x0 "END_REGION_i_12,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x154++0x3 line.long 0x0 "END_REGION_i_13,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x164++0x3 line.long 0x0 "END_REGION_i_14,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x174++0x3 line.long 0x0 "END_REGION_i_15,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xC8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xD8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xE8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xF8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x108++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_8,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x118++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_9,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x128++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_10,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x138++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_11,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x148++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_12,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x158++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_13,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x168++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_14,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x178++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_15,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xCC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xDC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xEC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xFC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_8,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_9,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_10,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_11,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x14C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_12,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x15C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_13,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x16C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_14,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x17C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_15,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "PCIE1_FW" base ad:0x4A165000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xC0++0x3 line.long 0x0 "START_REGION_i_4,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xD0++0x3 line.long 0x0 "START_REGION_i_5,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xE0++0x3 line.long 0x0 "START_REGION_i_6,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xF0++0x3 line.long 0x0 "START_REGION_i_7,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xC4++0x3 line.long 0x0 "END_REGION_i_4,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xD4++0x3 line.long 0x0 "END_REGION_i_5,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xE4++0x3 line.long 0x0 "END_REGION_i_6,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xF4++0x3 line.long 0x0 "END_REGION_i_7,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xC8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xD8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xE8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xF8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xCC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xDC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xEC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xFC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "GPMC_FW" base ad:0x4A210000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xC0++0x3 line.long 0x0 "START_REGION_i_4,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xD0++0x3 line.long 0x0 "START_REGION_i_5,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xE0++0x3 line.long 0x0 "START_REGION_i_6,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xF0++0x3 line.long 0x0 "START_REGION_i_7,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xC4++0x3 line.long 0x0 "END_REGION_i_4,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xD4++0x3 line.long 0x0 "END_REGION_i_5,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xE4++0x3 line.long 0x0 "END_REGION_i_6,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xF4++0x3 line.long 0x0 "END_REGION_i_7,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xC8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xD8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xE8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xF8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xCC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xDC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xEC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xFC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "DSS_FW" base ad:0x4A21C000 width 32. group.byte 0x0++0x3 line.long 0x0 "ERROR_LOG_k,Error log register for port k" hexmask.long.word 0x0 0.--11. 1. " REQINFO_ERRLOG ,Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" bitfld.long 0x0 12.--16. " REGION_END_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--21. " REGION_START_ERRLOG ,Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 22. " RESERVED ,Reads return 0s." "0,1" textline " " bitfld.long 0x0 23. " BLK_BURST_VIOLATION ,Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x4++0x3 line.long 0x0 "LOGICAL_ADDR_ERRLOG_k,Logical Physical Address Error log register for port k" hexmask.long 0x0 0.--31. 1. " SLVOFS_LOGICAL ,Address generated by the Initiator before being translated" group.byte 0x40++0x3 line.long 0x0 "REGUPDATE_CONTROL,Register update control register" bitfld.long 0x0 0. " BUSY_REQ ,Busy request 0x0: Allow transactions to reach the slave NIU (resume) 0x1: No transaction can reach the slave NIU (suspend)" "0,1" bitfld.long 0x0 1. " FW_LOAD_REQ ,Writing '1' to this bit causes the bit to self-clear and triggers the reload of L3 firewall default values. This bit will subsequently self-set when the reload procedure is complete. Writing '0' has no effect." "0,1" textline " " hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16.--19. " FW_ADDR_SPACE_MSB ,Address space size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reads return 0s." group.byte 0x90++0x3 line.long 0x0 "START_REGION_i_1,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xA0++0x3 line.long 0x0 "START_REGION_i_2,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xB0++0x3 line.long 0x0 "START_REGION_i_3,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xC0++0x3 line.long 0x0 "START_REGION_i_4,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xD0++0x3 line.long 0x0 "START_REGION_i_5,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xE0++0x3 line.long 0x0 "START_REGION_i_6,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0xF0++0x3 line.long 0x0 "START_REGION_i_7,Start physical address of region i" hexmask.long.word 0x0 0.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " START_REGION ,Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 0.The programmed address is included in the region i boundary." group.byte 0x94++0x3 line.long 0x0 "END_REGION_i_1,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xA4++0x3 line.long 0x0 "END_REGION_i_2,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xB4++0x3 line.long 0x0 "END_REGION_i_3,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xC4++0x3 line.long 0x0 "END_REGION_i_4,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xD4++0x3 line.long 0x0 "END_REGION_i_5,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xE4++0x3 line.long 0x0 "END_REGION_i_6,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0xF4++0x3 line.long 0x0 "END_REGION_i_7,End physical address of region i" bitfld.long 0x0 0. " END_REGION_i_ENABLE_CORE0 ,Enable this region for port 0." "0,1" bitfld.long 0x0 1. " END_REGION_i_ENABLE_CORE1 ,Enable this region for port 1." "0,1" textline " " hexmask.long.byte 0x0 2.--9. 1. " RESERVED ,Reads return 0s." hexmask.long.tbyte 0x0 10.--31. 1. " END_REGION ,Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:10]. See. Each of the LSbits is assumed to be 1.The programmed address is included in the region i boundary." group.byte 0x88++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_0,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x98++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_1,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xA8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_2,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xB8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_3,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xC8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_4,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xD8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_5,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xE8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_6,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0xF8++0x3 line.long 0x0 "MRM_PERMISSION_REGION_LOW_j_7,Region j Permission Low" bitfld.long 0x0 0.--5. " RESERVED ,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " PUB_USR_EXE ,Public User Exe Access Allowed" "0,1" textline " " bitfld.long 0x0 7. " PUB_USR_WRITE ,Public User Write Access Allowed" "0,1" bitfld.long 0x0 8. " PUB_USR_READ ,Public User Read Access Allowed" "0,1" textline " " bitfld.long 0x0 9. " PUB_PRV_EXE ,Public Privilege Exe Allowed" "0,1" bitfld.long 0x0 10. " PUB_PRV_READ ,Public Privilege Read Allowed" "0,1" textline " " bitfld.long 0x0 11. " PUB_PRV_WRITE ,Public Privilege Write Allowed" "0,1" bitfld.long 0x0 12.--13. " RESERVED ,RESERVED" "0,1,2,3" textline " " bitfld.long 0x0 14. " PUB_USR_DEBUG ,Public User Debug Allowed" "0,1" bitfld.long 0x0 15. " PUB_PRV_DEBUG ,Public Privilege Debug Allowed" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x8C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_0,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0x9C++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_1,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xAC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_2,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xBC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_3,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xCC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_4,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xDC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_5,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xEC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_6,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" group.byte 0xFC++0x3 line.long 0x0 "MRM_PERMISSION_REGION_HIGH_j_7,Region j Permission High" bitfld.long 0x0 0. " R0 ,Master NIU ConnID = 0 read permission" "0,1" bitfld.long 0x0 1. " W0 ,Master NIU ConnID = 0 write permission" "0,1" textline " " bitfld.long 0x0 2. " R1 ,Master NIU ConnID = 1 read permission" "0,1" bitfld.long 0x0 3. " W1 ,Master NIU ConnID = 1 write permission" "0,1" textline " " bitfld.long 0x0 4. " R2 ,Master NIU ConnID = 2 read permission" "0,1" bitfld.long 0x0 5. " W2 ,Master NIU ConnID = 2 write permission" "0,1" textline " " bitfld.long 0x0 6. " R3 ,Master NIU ConnID = 3 read permission" "0,1" bitfld.long 0x0 7. " W3 ,Master NIU ConnID = 3 write permission" "0,1" textline " " bitfld.long 0x0 8. " R4 ,Master NIU ConnID = 4 read permission" "0,1" bitfld.long 0x0 9. " W4 ,Master NIU ConnID = 4 write permission" "0,1" textline " " bitfld.long 0x0 10. " R5 ,Master NIU ConnID = 5 read permission" "0,1" bitfld.long 0x0 11. " W5 ,Master NIU ConnID = 5 write permission" "0,1" textline " " bitfld.long 0x0 12. " R6 ,Master NIU ConnID = 6 read permission" "0,1" bitfld.long 0x0 13. " W6 ,Master NIU ConnID = 6 write permission" "0,1" textline " " bitfld.long 0x0 14. " R7 ,Master NIU ConnID = 7 read permission" "0,1" bitfld.long 0x0 15. " W7 ,Master NIU ConnID = 7 write permission" "0,1" textline " " bitfld.long 0x0 16. " R8 ,Master NIU ConnID = 8 read permission" "0,1" bitfld.long 0x0 17. " W8 ,Master NIU ConnID = 8 write permission" "0,1" textline " " bitfld.long 0x0 18. " R9 ,Master NIU ConnID = 9 read permission" "0,1" bitfld.long 0x0 19. " W9 ,Master NIU ConnID = 9 write permission" "0,1" textline " " bitfld.long 0x0 20. " R10 ,Master NIU ConnID = 10 read permission" "0,1" bitfld.long 0x0 21. " W10 ,Master NIU ConnID = 10 write permission" "0,1" textline " " bitfld.long 0x0 22. " R11 ,Master NIU ConnID = 11 read permission" "0,1" bitfld.long 0x0 23. " W11 ,Master NIU ConnID = 11 write permission" "0,1" textline " " bitfld.long 0x0 24. " R12 ,Master NIU ConnID = 12 read permission" "0,1" bitfld.long 0x0 25. " W12 ,Master NIU ConnID = 12 write permission" "0,1" textline " " bitfld.long 0x0 26. " R13 ,Master NIU ConnID = 13 read permission" "0,1" bitfld.long 0x0 27. " W13 ,Master NIU ConnID = 13 write permission" "0,1" textline " " bitfld.long 0x0 28. " R14 ,Master NIU ConnID = 14 read permission" "0,1" bitfld.long 0x0 29. " W14 ,Master NIU ConnID = 14 write permission" "0,1" textline " " bitfld.long 0x0 30. " R15 ,Master NIU ConnID = 115 read permission" "0,1" bitfld.long 0x0 31. " W15 ,Master NIU ConnID = 115 write permission" "0,1" width 0x0B tree.end tree "CLK1_2_MMU1_BW_LIMITER" base ad:0x44803A00 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_2_TPTC1_RD_BW_LIMITER" base ad:0x44803C00 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_2_TPTC2_RD_BW_LIMITER" base ad:0x44803D00 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_2_TPTC1_WR_BW_LIMITER" base ad:0x44803E00 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_2_TPTC2_WR_BW_LIMITER" base ad:0x44803F00 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_2_VPE_P2_BW_LIMITER" base ad:0x44804000 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_2_VPE_P1_BW_LIMITER" base ad:0x44804100 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_2_BB2D_P1_BW_LIMITER" base ad:0x44805900 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_2_BB2D_P2_BW_LIMITER" base ad:0x44805A00 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_2_GPU_P1_BW_LIMITER" base ad:0x44805B00 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "CLK1_2_GPU_P2_BW_LIMITER" base ad:0x44805C00 width 37. group.byte 0x0++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_COREREG,L3_BW_LIMITER_STDHOSTHDR_COREREG" bitfld.long 0x0 0. " STDHOSTHDR_COREREG_VENDORCODE ,The Vendor Code field is a constantreporting the core generator vendor code. Type: Constant. Reset value: 0x1." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--21. " STDHOSTHDR_COREREG_CORECODE ,The Core Code field is a constantreporting a vendor-specific core generator code. Type: Constant. Reset value: 0x2C." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "L3_BW_LIMITER_STDHOSTHDR_VERSIONREG,L3_BW_LIMITER_STDHOSTHDR_VERSIONREG" hexmask.long.tbyte 0x0 0.--23. 1. " STDHOSTHDR_VERSIONREG_COREPARAMSCHECKSUM ,Reserved. Type: Reserved. Reset value: Reserved." hexmask.long.byte 0x0 24.--31. 1. " STDHOSTHDR_VERSIONREG_REVISIONID ,The Revision Identifier field is a constantreporting the core generator revision number. Type: Constant. Reset value: 0x0." group.byte 0x8++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_FRACTIONAL,L3_BW_LIMITER_BANDWIDTH_FRACTIONAL" bitfld.long 0x0 0.--4. " BANDWIDTH_FRACTIONAL ,Fractional part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "L3_BW_LIMITER_BANDWIDTH_INTEGER,L3_BW_LIMITER_BANDWIDTH_INTEGER" bitfld.long 0x0 0.--3. " BANDWIDTH_INTEGER ,Integer part of bandwitdh in terms of bytes per second Type: Control. Reset value: 0x0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "L3_BW_LIMITER_WATERMARK_0,L3_BW_LIMITER_WATERMARK_0" hexmask.long.word 0x0 0.--13. 1. " WATERMARK_0 ,Peak bandwidth allowed Type: Control. Reset value: 0x3FF." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "L3_BW_LIMITER_CLEARHISTORY,L3_BW_LIMITER_CLEARHISTORY" bitfld.long 0x0 0. " CLEARHISTORY ,Write a 1 clear the traffic counter Type: Give_AutoCleared. Reset value: 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "UART3_TARG" base ad:0x48021000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER2_TARG" base ad:0x48033000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER3_TARG" base ad:0x48035000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER4_TARG" base ad:0x48037000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER9_TARG" base ad:0x4803F000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GPIO7_TARG" base ad:0x48052000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GPIO8_TARG" base ad:0x48054000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GPIO2_TARG" base ad:0x48056000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GPIO3_TARG" base ad:0x48058000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GPIO4_TARG" base ad:0x4805A000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GPIO5_TARG" base ad:0x4805C000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GPIO6_TARG" base ad:0x4805E000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "I2C3_TARG" base ad:0x48061000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "UART5_TARG" base ad:0x48067000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "UART6_TARG" base ad:0x48069000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "UART1_TARG" base ad:0x4806B000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "UART2_TARG" base ad:0x4806D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "UART4_TARG" base ad:0x4806F000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "I2C1_TARG" base ad:0x48071000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "I2C2_TARG" base ad:0x48073000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "ELM_TARG" base ad:0x48079000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "I2C4_TARG" base ad:0x4807B000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "I2C5_TARG" base ad:0x4807D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER10_TARG" base ad:0x48087000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER11_TARG" base ad:0x48089000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCSPI1_TARG" base ad:0x48099000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCSPI2_TARG" base ad:0x4809B000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MMC1_TARG" base ad:0x4809D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MMC3_TARG" base ad:0x480AE000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "HDQ1W_TARG" base ad:0x480B3000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MMC2_TARG" base ad:0x480B5000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCSPI3_TARG" base ad:0x480B9000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCSPI4_TARG" base ad:0x480BB000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MMC4_TARG" base ad:0x480D2000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "UART7_TARG" base ad:0x48421000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "UART8_TARG" base ad:0x48423000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "UART9_TARG" base ad:0x48425000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MLB_TARG" base ad:0x4842D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP4_DAT_TARG" base ad:0x48437000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP5_DAT_TARG" base ad:0x4843B000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "ATL_TARG" base ad:0x4843D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "PWM1_TARG" base ad:0x4843F000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "PWM2_TARG" base ad:0x48441000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "PWM3_TARG" base ad:0x48443000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "VCP1_CFG_TARG" base ad:0x48447000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "VCP2_CFG_TARG" base ad:0x48449000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP6_DAT_TARG" base ad:0x4844D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP7_DAT_TARG" base ad:0x48451000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP8_DAT_TARG" base ad:0x48455000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP1_CFG_TARG" base ad:0x48462000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP2_CFG_TARG" base ad:0x48466000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP3_CFG_TARG" base ad:0x4846A000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP4_CFG_TARG" base ad:0x4846E000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP5_CFG_TARG" base ad:0x48472000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP6_CFG_TARG" base ad:0x48476000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP7_CFG_TARG" base ad:0x4847A000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "DCAN2_TARG" base ad:0x48482000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GMAC_TARG" base ad:0x48488000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX13_TARG" base ad:0x48803000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "OCMC_RAM1_TARG" base ad:0x48805000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "OCMC_RAM2_TARG" base ad:0x4880B000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MMU1_TARG" base ad:0x4881D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MMU2_TARG" base ad:0x4881F000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER5_TARG" base ad:0x48821000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER6_TARG" base ad:0x48823000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER7_TARG" base ad:0x48825000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER8_TARG" base ad:0x48827000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER13_TARG" base ad:0x48829000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER14_TARG" base ad:0x4882B000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER15_TARG" base ad:0x4882D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER16_TARG" base ad:0x4882F000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "RTC_TARG" base ad:0x48839000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX2_TARG" base ad:0x4883B000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX3_TARG" base ad:0x4883D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX4_TARG" base ad:0x4883F000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX5_TARG" base ad:0x48841000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX6_TARG" base ad:0x48843000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX7_TARG" base ad:0x48845000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX8_TARG" base ad:0x48847000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX9_TARG" base ad:0x4885F000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX10_TARG" base ad:0x48861000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX11_TARG" base ad:0x48863000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MBX12_TARG" base ad:0x48865000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "USB1_TARG" base ad:0x488A0000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "USB2_TARG" base ad:0x488E0000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "USB3_TARG" base ad:0x48920000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "USB4_TARG" base ad:0x48960000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "VIP1_TARG" base ad:0x48980000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "VIP2_TARG" base ad:0x489A0000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "VIP3_TARG" base ad:0x489C0000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "VPE_TARG" base ad:0x489E0000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "CTRL_MODULE_CORE_TARG" base ad:0x4A004000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "CM_CORE_AON_TARG" base ad:0x4A006000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "CM_CORE_TARG" base ad:0x4A00A000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "DMA_SYSTEM_TARG" base ad:0x4A057000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "SCP1_TARG" base ad:0x4A088000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "SCP3_TARG" base ad:0x4A098000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "SCP2_TARG" base ad:0x4A0A8000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "EVE1_FW_CFG_TARG" base ad:0x4A152000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "EVE2_FW_CFG_TARG" base ad:0x4A154000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "EVE3_FW_CFG_TARG" base ad:0x4A156000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "EVE4_FW_CFG_TARG" base ad:0x4A158000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "PCIESS2_FW_CFG_TARG" base ad:0x4A15A000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "IPU1_FW_CFG_TARG" base ad:0x4A15C000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "VCP1_FW_CFG_TARG" base ad:0x4A15E000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "VCP2_FW_CFG_TARG" base ad:0x4A160000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TPCC_FW_CFG_TARG" base ad:0x4A162000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TPTC_FW_CFG_TARG" base ad:0x4A164000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "PCIESS1_FW_CFG_TARG" base ad:0x4A166000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP1_FW_CFG_TARG" base ad:0x4A168000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP2_FW_CFG_TARG" base ad:0x4A16A000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP3_FW_CFG_TARG" base ad:0x4A16C000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "DSP1_SDMA_FW_CFG_TARG" base ad:0x4A172000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "DSP2_SDMA_FW_CFG_TARG" base ad:0x4A174000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "PRUSS1_FW_CFG_TARG" base ad:0x4A176000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "PRUSS2_FW_CFG_TARG" base ad:0x4A178000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "QSPI_FW_CFG_TARG" base ad:0x4A17A000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MA_MPU_NTTP_FW_CFG_TARG" base ad:0x4A20B000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "EMIF_OCP_FW_CFG_TARG" base ad:0x4A20D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "OCMC_RAM2_FW_CFG_TARG" base ad:0x4A20F000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GPMC_FW_CFG_TARG" base ad:0x4A211000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "OCMC_RAM1_FW_CFG_TARG" base ad:0x4A213000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GPU_FW_CFG_TARG" base ad:0x4A215000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "IPU2_FW_CFG_TARG" base ad:0x4A219000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "DSS_FW_CFG_TARG" base ad:0x4A21D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "IVA_SL2IF_FW_CFG_TARG" base ad:0x4A21F000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "IVA_CONFIG_FW_CFG_TARG" base ad:0x4A221000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "DEBUGSS_CT_TBR_FW_CFG_TARG" base ad:0x4A225000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "L3_INSTR_FW_CFG_TARG" base ad:0x4A227000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "OCMC_RAM3_FW_CFG_TARG" base ad:0x4A22B000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "COUNTER_32K_TARG" base ad:0x4AE05000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "PRM_TARG" base ad:0x4AE08000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "CTRL_MODULE_WKUP_TARG" base ad:0x4AE0D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "GPIO1_TARG" base ad:0x4AE11000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "WD_TIMER2_TARG" base ad:0x4AE15000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER1_TARG" base ad:0x4AE19000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "KBD_TARG" base ad:0x4AE1D000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "TIMER12_TARG" base ad:0x4AE21000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "UART10_TARG" base ad:0x4AE2C000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "DCAN1_TARG" base ad:0x4AE3E000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "MCASP8_CFG_TARG" base ad:0x4847E000 width 23. group.byte 0xA000++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0xA004++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0xA018++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0xA01C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xA020++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0xA024++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0xA028++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0xA02C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "OCMC_RAM3_TARG" base ad:0x48811000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x2004++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x2018++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x201C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x2020++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2024++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2028++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x202C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "CFG_LA" base ad:0x4A000800 width 25. group.byte 0x0++0x3 line.long 0x0 "L4_LA_COMPONENT_L,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_LA_COMPONENT_H,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x10++0x3 line.long 0x0 "L4_LA_NETWORK_L,Identify the interconnect" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x14++0x3 line.long 0x0 "L4_LA_NETWORK_H,Identify the interconnect" hexmask.long 0x0 0.--31. 1. " ID ,The ID field uniquely identifies this interconnect." group.byte 0x18++0x3 line.long 0x0 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information." bitfld.long 0x0 0.--3. " SEGMENTS ,Number of segments in the current L4 0x0: Reserved 0x1: 1 segment 0x2: 2 segments .... 0x8: 8 segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 16.--23. 1. " NUMBER_REGIONS ,Number of regions in the current L4 0x0: Reserved 0x1: 1 region 0x2: 2 regions .... Max regions +1 to 0xFF: Reserved, maximum regions is listed in" bitfld.long 0x0 24.--27. " PROT_GROUPS ,Number of protection group of in the current L4 0x0: No protection group 0x1: 1 protection group 0x2: 2 protection groups .... 0x8: 8 protection groups 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1C++0x3 line.long 0x0 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information." bitfld.long 0x0 0.--5. " ADDR_WIDTH ,This field specifies the initiator subsystem address width. The ADDR_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " RESERVED ,Read returns 0." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " BYTE_DATA_WIDTH_EXP ,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem. 0x1: 16-bit data width is specified 0x2: 32-bit data width is specified" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--14. " CONNID_WIDTH ,The initiator subsystem ConnID width. The CONNID_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Read returns 0." "0,1" textline " " bitfld.long 0x0 16.--18. " THREADS ,The THREADS field specifies the number of initiator threads connected to the interconnect. The field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ,Read returns 0." group.byte 0x20++0x3 line.long 0x0 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8.--10. " TIMEOUT_BASE ,The TIMEOUT_BASE field indicates the time-out period (that is, base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled. Values for the field are: 0 - Time-out disabled 1 - L4 interconnect clock cycles divided by 64 2 - L4 interconnect clock cycles divided by 256 3 - L4 interconnect clock cycles divided by 1024 4 - L4 interconnect clock cycles divided by 4096" "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,Global external clock control. When set to 1, the ext_clk_off_i signal on the initiator subsystem instructs the entire L4 to shut off." "0,1" textline " " hexmask.long.word 0x0 9.--19. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 20. " THREAD0_PRI ,Sets thread priority. If the field is set to 0, the default, all initiator threads are treated the same. Setting the THREAD0_PRI field to 1 assigns a higher arbitration priority to thread 0 of the first initiator OCP interface. To avoid starvation, arbitration is imposed by the initiator subsystem. When multiple requests from different initiator threads are dispatched to targets simultaneously, the oldest request is dispatched first. If thread 0 is assigned a higher priority, a request on thread 0 always wins arbitration. Assigning thread 0 of the first initiator OCP the highest priority on a request or response can result in the starvation of other threads." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. " CLOCK_GATE_DISABLE ,When set to 1 this field disables all clock gating." "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "WKUP_LA" base ad:0x4AE00800 width 25. group.byte 0x0++0x3 line.long 0x0 "L4_LA_COMPONENT_L,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_LA_COMPONENT_H,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x10++0x3 line.long 0x0 "L4_LA_NETWORK_L,Identify the interconnect" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x14++0x3 line.long 0x0 "L4_LA_NETWORK_H,Identify the interconnect" hexmask.long 0x0 0.--31. 1. " ID ,The ID field uniquely identifies this interconnect." group.byte 0x18++0x3 line.long 0x0 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information." bitfld.long 0x0 0.--3. " SEGMENTS ,Number of segments in the current L4 0x0: Reserved 0x1: 1 segment 0x2: 2 segments .... 0x8: 8 segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 16.--23. 1. " NUMBER_REGIONS ,Number of regions in the current L4 0x0: Reserved 0x1: 1 region 0x2: 2 regions .... Max regions +1 to 0xFF: Reserved, maximum regions is listed in" bitfld.long 0x0 24.--27. " PROT_GROUPS ,Number of protection group of in the current L4 0x0: No protection group 0x1: 1 protection group 0x2: 2 protection groups .... 0x8: 8 protection groups 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1C++0x3 line.long 0x0 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information." bitfld.long 0x0 0.--5. " ADDR_WIDTH ,This field specifies the initiator subsystem address width. The ADDR_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " RESERVED ,Read returns 0." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " BYTE_DATA_WIDTH_EXP ,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem. 0x1: 16-bit data width is specified 0x2: 32-bit data width is specified" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--14. " CONNID_WIDTH ,The initiator subsystem ConnID width. The CONNID_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Read returns 0." "0,1" textline " " bitfld.long 0x0 16.--18. " THREADS ,The THREADS field specifies the number of initiator threads connected to the interconnect. The field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ,Read returns 0." group.byte 0x20++0x3 line.long 0x0 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8.--10. " TIMEOUT_BASE ,The TIMEOUT_BASE field indicates the time-out period (that is, base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled. Values for the field are: 0 - Time-out disabled 1 - L4 interconnect clock cycles divided by 64 2 - L4 interconnect clock cycles divided by 256 3 - L4 interconnect clock cycles divided by 1024 4 - L4 interconnect clock cycles divided by 4096" "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,Global external clock control. When set to 1, the ext_clk_off_i signal on the initiator subsystem instructs the entire L4 to shut off." "0,1" textline " " hexmask.long.word 0x0 9.--19. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 20. " THREAD0_PRI ,Sets thread priority. If the field is set to 0, the default, all initiator threads are treated the same. Setting the THREAD0_PRI field to 1 assigns a higher arbitration priority to thread 0 of the first initiator OCP interface. To avoid starvation, arbitration is imposed by the initiator subsystem. When multiple requests from different initiator threads are dispatched to targets simultaneously, the oldest request is dispatched first. If thread 0 is assigned a higher priority, a request on thread 0 always wins arbitration. Assigning thread 0 of the first initiator OCP the highest priority on a request or response can result in the starvation of other threads." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. " CLOCK_GATE_DISABLE ,When set to 1 this field disables all clock gating." "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "PER1_LA" base ad:0x48000800 width 25. group.byte 0x0++0x3 line.long 0x0 "L4_LA_COMPONENT_L,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_LA_COMPONENT_H,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x10++0x3 line.long 0x0 "L4_LA_NETWORK_L,Identify the interconnect" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x14++0x3 line.long 0x0 "L4_LA_NETWORK_H,Identify the interconnect" hexmask.long 0x0 0.--31. 1. " ID ,The ID field uniquely identifies this interconnect." group.byte 0x18++0x3 line.long 0x0 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information." bitfld.long 0x0 0.--3. " SEGMENTS ,Number of segments in the current L4 0x0: Reserved 0x1: 1 segment 0x2: 2 segments .... 0x8: 8 segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 16.--23. 1. " NUMBER_REGIONS ,Number of regions in the current L4 0x0: Reserved 0x1: 1 region 0x2: 2 regions .... Max regions +1 to 0xFF: Reserved, maximum regions is listed in" bitfld.long 0x0 24.--27. " PROT_GROUPS ,Number of protection group of in the current L4 0x0: No protection group 0x1: 1 protection group 0x2: 2 protection groups .... 0x8: 8 protection groups 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1C++0x3 line.long 0x0 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information." bitfld.long 0x0 0.--5. " ADDR_WIDTH ,This field specifies the initiator subsystem address width. The ADDR_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " RESERVED ,Read returns 0." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " BYTE_DATA_WIDTH_EXP ,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem. 0x1: 16-bit data width is specified 0x2: 32-bit data width is specified" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--14. " CONNID_WIDTH ,The initiator subsystem ConnID width. The CONNID_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Read returns 0." "0,1" textline " " bitfld.long 0x0 16.--18. " THREADS ,The THREADS field specifies the number of initiator threads connected to the interconnect. The field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ,Read returns 0." group.byte 0x20++0x3 line.long 0x0 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8.--10. " TIMEOUT_BASE ,The TIMEOUT_BASE field indicates the time-out period (that is, base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled. Values for the field are: 0 - Time-out disabled 1 - L4 interconnect clock cycles divided by 64 2 - L4 interconnect clock cycles divided by 256 3 - L4 interconnect clock cycles divided by 1024 4 - L4 interconnect clock cycles divided by 4096" "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,Global external clock control. When set to 1, the ext_clk_off_i signal on the initiator subsystem instructs the entire L4 to shut off." "0,1" textline " " hexmask.long.word 0x0 9.--19. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 20. " THREAD0_PRI ,Sets thread priority. If the field is set to 0, the default, all initiator threads are treated the same. Setting the THREAD0_PRI field to 1 assigns a higher arbitration priority to thread 0 of the first initiator OCP interface. To avoid starvation, arbitration is imposed by the initiator subsystem. When multiple requests from different initiator threads are dispatched to targets simultaneously, the oldest request is dispatched first. If thread 0 is assigned a higher priority, a request on thread 0 always wins arbitration. Assigning thread 0 of the first initiator OCP the highest priority on a request or response can result in the starvation of other threads." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. " CLOCK_GATE_DISABLE ,When set to 1 this field disables all clock gating." "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x100++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" bitfld.long 0x0 0.--3. " MASK ,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x120++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" bitfld.long 0x0 0.--3. " MASK ,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x104++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_H_0,Status of composite sideband flag(0)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x124++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_H_1,Status of composite sideband flag(0)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x110++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" bitfld.long 0x0 0.--3. " STATUS ,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x130++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" bitfld.long 0x0 0.--3. " STATUS ,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x114++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_H_0,Status of composite sideband flag(1)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x134++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_H_1,Status of composite sideband flag(1)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "PER2_LA" base ad:0x48400800 width 25. group.byte 0x0++0x3 line.long 0x0 "L4_LA_COMPONENT_L,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_LA_COMPONENT_H,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x10++0x3 line.long 0x0 "L4_LA_NETWORK_L,Identify the interconnect" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x14++0x3 line.long 0x0 "L4_LA_NETWORK_H,Identify the interconnect" hexmask.long 0x0 0.--31. 1. " ID ,The ID field uniquely identifies this interconnect." group.byte 0x18++0x3 line.long 0x0 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information." bitfld.long 0x0 0.--3. " SEGMENTS ,Number of segments in the current L4 0x0: Reserved 0x1: 1 segment 0x2: 2 segments .... 0x8: 8 segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 16.--23. 1. " NUMBER_REGIONS ,Number of regions in the current L4 0x0: Reserved 0x1: 1 region 0x2: 2 regions .... Max regions +1 to 0xFF: Reserved, maximum regions is listed in" bitfld.long 0x0 24.--27. " PROT_GROUPS ,Number of protection group of in the current L4 0x0: No protection group 0x1: 1 protection group 0x2: 2 protection groups .... 0x8: 8 protection groups 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1C++0x3 line.long 0x0 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information." bitfld.long 0x0 0.--5. " ADDR_WIDTH ,This field specifies the initiator subsystem address width. The ADDR_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " RESERVED ,Read returns 0." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " BYTE_DATA_WIDTH_EXP ,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem. 0x1: 16-bit data width is specified 0x2: 32-bit data width is specified" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--14. " CONNID_WIDTH ,The initiator subsystem ConnID width. The CONNID_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Read returns 0." "0,1" textline " " bitfld.long 0x0 16.--18. " THREADS ,The THREADS field specifies the number of initiator threads connected to the interconnect. The field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ,Read returns 0." group.byte 0x20++0x3 line.long 0x0 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8.--10. " TIMEOUT_BASE ,The TIMEOUT_BASE field indicates the time-out period (that is, base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled. Values for the field are: 0 - Time-out disabled 1 - L4 interconnect clock cycles divided by 64 2 - L4 interconnect clock cycles divided by 256 3 - L4 interconnect clock cycles divided by 1024 4 - L4 interconnect clock cycles divided by 4096" "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,Global external clock control. When set to 1, the ext_clk_off_i signal on the initiator subsystem instructs the entire L4 to shut off." "0,1" textline " " hexmask.long.word 0x0 9.--19. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 20. " THREAD0_PRI ,Sets thread priority. If the field is set to 0, the default, all initiator threads are treated the same. Setting the THREAD0_PRI field to 1 assigns a higher arbitration priority to thread 0 of the first initiator OCP interface. To avoid starvation, arbitration is imposed by the initiator subsystem. When multiple requests from different initiator threads are dispatched to targets simultaneously, the oldest request is dispatched first. If thread 0 is assigned a higher priority, a request on thread 0 always wins arbitration. Assigning thread 0 of the first initiator OCP the highest priority on a request or response can result in the starvation of other threads." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. " CLOCK_GATE_DISABLE ,When set to 1 this field disables all clock gating." "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x100++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" bitfld.long 0x0 0.--3. " MASK ,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x120++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" bitfld.long 0x0 0.--3. " MASK ,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x104++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_H_0,Status of composite sideband flag(0)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x124++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_H_1,Status of composite sideband flag(0)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x110++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" bitfld.long 0x0 0.--3. " STATUS ,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x130++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" bitfld.long 0x0 0.--3. " STATUS ,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x114++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_H_0,Status of composite sideband flag(1)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x134++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_H_1,Status of composite sideband flag(1)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "PER3_LA" base ad:0x48800800 width 25. group.byte 0x0++0x3 line.long 0x0 "L4_LA_COMPONENT_L,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_LA_COMPONENT_H,Contain a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x10++0x3 line.long 0x0 "L4_LA_NETWORK_L,Identify the interconnect" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x14++0x3 line.long 0x0 "L4_LA_NETWORK_H,Identify the interconnect" hexmask.long 0x0 0.--31. 1. " ID ,The ID field uniquely identifies this interconnect." group.byte 0x18++0x3 line.long 0x0 "L4_LA_INITIATOR_INFO_L,Contain initiator subsystem information." bitfld.long 0x0 0.--3. " SEGMENTS ,Number of segments in the current L4 0x0: Reserved 0x1: 1 segment 0x2: 2 segments .... 0x8: 8 segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 16.--23. 1. " NUMBER_REGIONS ,Number of regions in the current L4 0x0: Reserved 0x1: 1 region 0x2: 2 regions .... Max regions +1 to 0xFF: Reserved, maximum regions is listed in" bitfld.long 0x0 24.--27. " PROT_GROUPS ,Number of protection group of in the current L4 0x0: No protection group 0x1: 1 protection group 0x2: 2 protection groups .... 0x8: 8 protection groups 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1C++0x3 line.long 0x0 "L4_LA_INITIATOR_INFO_H,Contain initiator subsystem information." bitfld.long 0x0 0.--5. " ADDR_WIDTH ,This field specifies the initiator subsystem address width. The ADDR_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " RESERVED ,Read returns 0." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " BYTE_DATA_WIDTH_EXP ,This field specifies the initiator subsystem data width.The BYTE_DATA_WIDTH_EXP field contains read-only configuration information for the initiator subsystem. 0x1: 16-bit data width is specified 0x2: 32-bit data width is specified" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--14. " CONNID_WIDTH ,The initiator subsystem ConnID width. The CONNID_WIDTH field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Read returns 0." "0,1" textline " " bitfld.long 0x0 16.--18. " THREADS ,The THREADS field specifies the number of initiator threads connected to the interconnect. The field contains read-only configuration information for the initiator subsystem." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ,Read returns 0." group.byte 0x20++0x3 line.long 0x0 "L4_LA_NETWORK_CONTROL_L,Control interconnect minimum timeout values." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8.--10. " TIMEOUT_BASE ,The TIMEOUT_BASE field indicates the time-out period (that is, base cycles) for the highest frequency time-base signal sent from the L4 initiator subsystem to all target agents that have time-out enabled. Values for the field are: 0 - Time-out disabled 1 - L4 interconnect clock cycles divided by 64 2 - L4 interconnect clock cycles divided by 256 3 - L4 interconnect clock cycles divided by 1024 4 - L4 interconnect clock cycles divided by 4096" "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_LA_NETWORK_CONTROL_H,Control interconnect global power control" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,Global external clock control. When set to 1, the ext_clk_off_i signal on the initiator subsystem instructs the entire L4 to shut off." "0,1" textline " " hexmask.long.word 0x0 9.--19. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 20. " THREAD0_PRI ,Sets thread priority. If the field is set to 0, the default, all initiator threads are treated the same. Setting the THREAD0_PRI field to 1 assigns a higher arbitration priority to thread 0 of the first initiator OCP interface. To avoid starvation, arbitration is imposed by the initiator subsystem. When multiple requests from different initiator threads are dispatched to targets simultaneously, the oldest request is dispatched first. If thread 0 is assigned a higher priority, a request on thread 0 always wins arbitration. Assigning thread 0 of the first initiator OCP the highest priority on a request or response can result in the starvation of other threads." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. " CLOCK_GATE_DISABLE ,When set to 1 this field disables all clock gating." "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x100++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_L_0,Mask of composite sideband flag(0)" bitfld.long 0x0 0.--3. " MASK ,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x120++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_L_1,Mask of composite sideband flag(0)" bitfld.long 0x0 0.--3. " MASK ,Number of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x104++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_H_0,Status of composite sideband flag(0)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x124++0x3 line.long 0x0 "L4_LA_FLAG_MASK_j_H_1,Status of composite sideband flag(0)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x110++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_L_0,Mask of composite sideband flag(1)" bitfld.long 0x0 0.--3. " STATUS ,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x130++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_L_1,Mask of composite sideband flag(1)" bitfld.long 0x0 0.--3. " STATUS ,Status of input sideband signals" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Read returns 0" group.byte 0x114++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_H_0,Status of composite sideband flag(1)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x134++0x3 line.long 0x0 "L4_LA_FLAG_STATUS_j_H_1,Status of composite sideband flag(1)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" width 0x0B tree.end tree "WKUP_AP" base ad:0x4AE00000 width 32. group.byte 0x0++0x3 line.long 0x0 "L4_AP_COMPONENT_L,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_AP_COMPONENT_H,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x100++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x108++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L_1,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x110++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L_2,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x118++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L_3,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x104++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x10C++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H_1,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x114++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H_2,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x11C++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H_3,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x200++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x20C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x214++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x21C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x224++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x22C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x234++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x23C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x280++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x288++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x290++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x298++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A0++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A8++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B0++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B8++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x284++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x28C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x294++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x29C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A4++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2AC++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B4++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2BC++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x300++0x3 line.long 0x0 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x308++0x3 line.long 0x0 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x310++0x3 line.long 0x0 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x318++0x3 line.long 0x0 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x320++0x3 line.long 0x0 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x328++0x3 line.long 0x0 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x330++0x3 line.long 0x0 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x338++0x3 line.long 0x0 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x340++0x3 line.long 0x0 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x348++0x3 line.long 0x0 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x350++0x3 line.long 0x0 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x358++0x3 line.long 0x0 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x360++0x3 line.long 0x0 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x368++0x3 line.long 0x0 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x370++0x3 line.long 0x0 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x378++0x3 line.long 0x0 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x380++0x3 line.long 0x0 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x388++0x3 line.long 0x0 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x390++0x3 line.long 0x0 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x398++0x3 line.long 0x0 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x400++0x3 line.long 0x0 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x408++0x3 line.long 0x0 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x410++0x3 line.long 0x0 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x418++0x3 line.long 0x0 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x420++0x3 line.long 0x0 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x428++0x3 line.long 0x0 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x430++0x3 line.long 0x0 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x438++0x3 line.long 0x0 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x440++0x3 line.long 0x0 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x448++0x3 line.long 0x0 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x450++0x3 line.long 0x0 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x458++0x3 line.long 0x0 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x304++0x3 line.long 0x0 "L4_AP_REGION_l_H_0,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x30C++0x3 line.long 0x0 "L4_AP_REGION_l_H_1,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x314++0x3 line.long 0x0 "L4_AP_REGION_l_H_2,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x31C++0x3 line.long 0x0 "L4_AP_REGION_l_H_3,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x324++0x3 line.long 0x0 "L4_AP_REGION_l_H_4,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x32C++0x3 line.long 0x0 "L4_AP_REGION_l_H_5,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x334++0x3 line.long 0x0 "L4_AP_REGION_l_H_6,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x33C++0x3 line.long 0x0 "L4_AP_REGION_l_H_7,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x344++0x3 line.long 0x0 "L4_AP_REGION_l_H_8,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x34C++0x3 line.long 0x0 "L4_AP_REGION_l_H_9,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x354++0x3 line.long 0x0 "L4_AP_REGION_l_H_10,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x35C++0x3 line.long 0x0 "L4_AP_REGION_l_H_11,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x364++0x3 line.long 0x0 "L4_AP_REGION_l_H_12,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x36C++0x3 line.long 0x0 "L4_AP_REGION_l_H_13,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x374++0x3 line.long 0x0 "L4_AP_REGION_l_H_14,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x37C++0x3 line.long 0x0 "L4_AP_REGION_l_H_15,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L4_AP_REGION_l_H_16,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x38C++0x3 line.long 0x0 "L4_AP_REGION_l_H_17,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x394++0x3 line.long 0x0 "L4_AP_REGION_l_H_18,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x39C++0x3 line.long 0x0 "L4_AP_REGION_l_H_19,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_20,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_21,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_22,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_23,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_24,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_25,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_26,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_27,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_28,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_29,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_30,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_31,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x404++0x3 line.long 0x0 "L4_AP_REGION_l_H_32,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40C++0x3 line.long 0x0 "L4_AP_REGION_l_H_33,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x414++0x3 line.long 0x0 "L4_AP_REGION_l_H_34,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x41C++0x3 line.long 0x0 "L4_AP_REGION_l_H_35,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x424++0x3 line.long 0x0 "L4_AP_REGION_l_H_36,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x42C++0x3 line.long 0x0 "L4_AP_REGION_l_H_37,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x434++0x3 line.long 0x0 "L4_AP_REGION_l_H_38,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x43C++0x3 line.long 0x0 "L4_AP_REGION_l_H_39,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x444++0x3 line.long 0x0 "L4_AP_REGION_l_H_40,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x44C++0x3 line.long 0x0 "L4_AP_REGION_l_H_41,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x454++0x3 line.long 0x0 "L4_AP_REGION_l_H_42,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x45C++0x3 line.long 0x0 "L4_AP_REGION_l_H_43,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "PER3_AP" base ad:0x48800000 width 32. group.byte 0x0++0x3 line.long 0x0 "L4_AP_COMPONENT_L,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_AP_COMPONENT_H,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x100++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x104++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x200++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x20C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x214++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x21C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x224++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x22C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x234++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x23C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x280++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x288++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x290++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x298++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A0++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A8++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B0++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B8++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x284++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x28C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x294++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x29C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A4++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2AC++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B4++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2BC++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x300++0x3 line.long 0x0 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x308++0x3 line.long 0x0 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x310++0x3 line.long 0x0 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x318++0x3 line.long 0x0 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x320++0x3 line.long 0x0 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x328++0x3 line.long 0x0 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x330++0x3 line.long 0x0 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x338++0x3 line.long 0x0 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x340++0x3 line.long 0x0 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x348++0x3 line.long 0x0 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x350++0x3 line.long 0x0 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x358++0x3 line.long 0x0 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x360++0x3 line.long 0x0 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x368++0x3 line.long 0x0 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x370++0x3 line.long 0x0 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x378++0x3 line.long 0x0 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x380++0x3 line.long 0x0 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x388++0x3 line.long 0x0 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x390++0x3 line.long 0x0 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x398++0x3 line.long 0x0 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x400++0x3 line.long 0x0 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x408++0x3 line.long 0x0 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x410++0x3 line.long 0x0 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x418++0x3 line.long 0x0 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x420++0x3 line.long 0x0 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x428++0x3 line.long 0x0 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x430++0x3 line.long 0x0 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x438++0x3 line.long 0x0 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x440++0x3 line.long 0x0 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x448++0x3 line.long 0x0 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x450++0x3 line.long 0x0 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x458++0x3 line.long 0x0 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x460++0x3 line.long 0x0 "L4_AP_REGION_l_L_44,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x468++0x3 line.long 0x0 "L4_AP_REGION_l_L_45,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x470++0x3 line.long 0x0 "L4_AP_REGION_l_L_46,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x478++0x3 line.long 0x0 "L4_AP_REGION_l_L_47,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x480++0x3 line.long 0x0 "L4_AP_REGION_l_L_48,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x488++0x3 line.long 0x0 "L4_AP_REGION_l_L_49,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x490++0x3 line.long 0x0 "L4_AP_REGION_l_L_50,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x498++0x3 line.long 0x0 "L4_AP_REGION_l_L_51,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_52,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_53,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_54,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_55,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_57,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_58,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_59,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_60,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_61,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_62,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_63,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x500++0x3 line.long 0x0 "L4_AP_REGION_l_L_64,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x508++0x3 line.long 0x0 "L4_AP_REGION_l_L_65,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x510++0x3 line.long 0x0 "L4_AP_REGION_l_L_66,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x518++0x3 line.long 0x0 "L4_AP_REGION_l_L_67,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x520++0x3 line.long 0x0 "L4_AP_REGION_l_L_68,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x528++0x3 line.long 0x0 "L4_AP_REGION_l_L_69,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x530++0x3 line.long 0x0 "L4_AP_REGION_l_L_70,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x538++0x3 line.long 0x0 "L4_AP_REGION_l_L_71,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x540++0x3 line.long 0x0 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x548++0x3 line.long 0x0 "L4_AP_REGION_l_L_73,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x550++0x3 line.long 0x0 "L4_AP_REGION_l_L_74,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x558++0x3 line.long 0x0 "L4_AP_REGION_l_L_75,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x560++0x3 line.long 0x0 "L4_AP_REGION_l_L_76,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x568++0x3 line.long 0x0 "L4_AP_REGION_l_L_77,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x570++0x3 line.long 0x0 "L4_AP_REGION_l_L_78,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x578++0x3 line.long 0x0 "L4_AP_REGION_l_L_79,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x580++0x3 line.long 0x0 "L4_AP_REGION_l_L_80,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x588++0x3 line.long 0x0 "L4_AP_REGION_l_L_81,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x590++0x3 line.long 0x0 "L4_AP_REGION_l_L_82,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x598++0x3 line.long 0x0 "L4_AP_REGION_l_L_83,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_84,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_85,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_86,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_87,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_88,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_89,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_90,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_91,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_92,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_93,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_94,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_95,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x600++0x3 line.long 0x0 "L4_AP_REGION_l_L_96,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x304++0x3 line.long 0x0 "L4_AP_REGION_l_H_0,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x30C++0x3 line.long 0x0 "L4_AP_REGION_l_H_1,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x314++0x3 line.long 0x0 "L4_AP_REGION_l_H_2,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x31C++0x3 line.long 0x0 "L4_AP_REGION_l_H_3,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x324++0x3 line.long 0x0 "L4_AP_REGION_l_H_4,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x32C++0x3 line.long 0x0 "L4_AP_REGION_l_H_5,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x334++0x3 line.long 0x0 "L4_AP_REGION_l_H_6,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x33C++0x3 line.long 0x0 "L4_AP_REGION_l_H_7,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x344++0x3 line.long 0x0 "L4_AP_REGION_l_H_8,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x34C++0x3 line.long 0x0 "L4_AP_REGION_l_H_9,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x354++0x3 line.long 0x0 "L4_AP_REGION_l_H_10,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x35C++0x3 line.long 0x0 "L4_AP_REGION_l_H_11,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x364++0x3 line.long 0x0 "L4_AP_REGION_l_H_12,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x36C++0x3 line.long 0x0 "L4_AP_REGION_l_H_13,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x374++0x3 line.long 0x0 "L4_AP_REGION_l_H_14,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x37C++0x3 line.long 0x0 "L4_AP_REGION_l_H_15,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L4_AP_REGION_l_H_16,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x38C++0x3 line.long 0x0 "L4_AP_REGION_l_H_17,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x394++0x3 line.long 0x0 "L4_AP_REGION_l_H_18,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x39C++0x3 line.long 0x0 "L4_AP_REGION_l_H_19,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_20,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_21,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_22,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_23,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_24,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_25,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_26,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_27,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_28,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_29,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_30,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_31,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x404++0x3 line.long 0x0 "L4_AP_REGION_l_H_32,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40C++0x3 line.long 0x0 "L4_AP_REGION_l_H_33,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x414++0x3 line.long 0x0 "L4_AP_REGION_l_H_34,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x41C++0x3 line.long 0x0 "L4_AP_REGION_l_H_35,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x424++0x3 line.long 0x0 "L4_AP_REGION_l_H_36,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x42C++0x3 line.long 0x0 "L4_AP_REGION_l_H_37,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x434++0x3 line.long 0x0 "L4_AP_REGION_l_H_38,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x43C++0x3 line.long 0x0 "L4_AP_REGION_l_H_39,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x444++0x3 line.long 0x0 "L4_AP_REGION_l_H_40,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x44C++0x3 line.long 0x0 "L4_AP_REGION_l_H_41,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x454++0x3 line.long 0x0 "L4_AP_REGION_l_H_42,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x45C++0x3 line.long 0x0 "L4_AP_REGION_l_H_43,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x464++0x3 line.long 0x0 "L4_AP_REGION_l_H_44,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x46C++0x3 line.long 0x0 "L4_AP_REGION_l_H_45,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x474++0x3 line.long 0x0 "L4_AP_REGION_l_H_46,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x47C++0x3 line.long 0x0 "L4_AP_REGION_l_H_47,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x484++0x3 line.long 0x0 "L4_AP_REGION_l_H_48,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x48C++0x3 line.long 0x0 "L4_AP_REGION_l_H_49,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x494++0x3 line.long 0x0 "L4_AP_REGION_l_H_50,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x49C++0x3 line.long 0x0 "L4_AP_REGION_l_H_51,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_52,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_53,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_54,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_55,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_56,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_57,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_58,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_59,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_60,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_61,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_62,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_63,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x504++0x3 line.long 0x0 "L4_AP_REGION_l_H_64,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50C++0x3 line.long 0x0 "L4_AP_REGION_l_H_65,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x514++0x3 line.long 0x0 "L4_AP_REGION_l_H_66,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x51C++0x3 line.long 0x0 "L4_AP_REGION_l_H_67,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x524++0x3 line.long 0x0 "L4_AP_REGION_l_H_68,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x52C++0x3 line.long 0x0 "L4_AP_REGION_l_H_69,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x534++0x3 line.long 0x0 "L4_AP_REGION_l_H_70,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x53C++0x3 line.long 0x0 "L4_AP_REGION_l_H_71,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x544++0x3 line.long 0x0 "L4_AP_REGION_l_H_72,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x54C++0x3 line.long 0x0 "L4_AP_REGION_l_H_73,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x554++0x3 line.long 0x0 "L4_AP_REGION_l_H_74,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x55C++0x3 line.long 0x0 "L4_AP_REGION_l_H_75,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x564++0x3 line.long 0x0 "L4_AP_REGION_l_H_76,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x56C++0x3 line.long 0x0 "L4_AP_REGION_l_H_77,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x574++0x3 line.long 0x0 "L4_AP_REGION_l_H_78,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x57C++0x3 line.long 0x0 "L4_AP_REGION_l_H_79,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x584++0x3 line.long 0x0 "L4_AP_REGION_l_H_80,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x58C++0x3 line.long 0x0 "L4_AP_REGION_l_H_81,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x594++0x3 line.long 0x0 "L4_AP_REGION_l_H_82,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x59C++0x3 line.long 0x0 "L4_AP_REGION_l_H_83,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_84,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_85,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_86,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_87,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_88,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_89,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_90,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_91,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_92,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_93,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_94,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_95,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x604++0x3 line.long 0x0 "L4_AP_REGION_l_H_96,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "PER1_IA_IP0" base ad:0x48001000 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "PER1_IA_IP1" base ad:0x48001400 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "PER1_IA_IP2" base ad:0x48001800 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "PER2_IA_IP0" base ad:0x48401000 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "PER2_IA_IP1" base ad:0x48401400 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "PER2_IA_IP2" base ad:0x48401800 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "PER3_IA_IP0" base ad:0x48801000 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "PER3_IA_IP1" base ad:0x48801400 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "PER3_IA_IP2" base ad:0x48801800 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "CFG_IA_IP0" base ad:0x4A001000 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "WKUP_IA_IP0" base ad:0x4AE01000 width 24. group.byte 0x0++0x3 line.long 0x0 "L4_IA_COMPONENT_L,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_IA_COMPONENT_H,COMPONENT register identifies the component to which this register block belongs. The register contains a component code and revision, which are used to identify the hardware of the component. The COMPONENT register is read-only." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "L4_IA_CORE_L,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_IA_CORE_H,Provide information about the core initiator" hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_L,Core control for an initiator OCP interface" hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ," bitfld.long 0x0 24. " MERROR_REP ,OCP MError reporting control. The out-of-band OCP MError reporting mechanism is enabled when the MERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR_REP ,Setting this field to 1 reports on in-band errors using the INBAND_ERROR log bit of IA.AGENT_STATUS register. The error reporting mechanism is enabled when the INBAND_ERROR_REP bit field is set to 1." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY_REP ,Out-of-band reporting of protection mechanism primary errors" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY_REP ,Out-of-band reporting of protection mechanism secondary errors" "0,1" group.byte 0x24++0x3 line.long 0x0 "L4_IA_AGENT_CONTROL_H,Enable error reporting on an initiator interface." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_L,Stores status information for an initiator. The INBAND_ERROR and MERROR fields are read/write and are implemented as log bits." hexmask.long.tbyte 0x0 0.--23. 1. " RESERVED ,Read returns 0" bitfld.long 0x0 24. " MERROR ,Value of the OCP MError signal" "0,1" textline " " bitfld.long 0x0 25.--26. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 27. " INBAND_ERROR ,0x0 No In-Band error present.0x1 In-Band error present." "0,1" textline " " bitfld.long 0x0 28.--29. " RESERVED ,Read returns 0." "0,1,2,3" bitfld.long 0x0 30. " PROT_ERROR_PRIMARY ,0x0: Primary Protection error not present.0x1: Primary Protection error present" "0,1" textline " " bitfld.long 0x0 31. " PROT_ERROR_SECONDARY ,0x0: Secondary Protection error not present.0x1: Secondary Protection error present" "0,1" group.byte 0x2C++0x3 line.long 0x0 "L4_IA_AGENT_STATUS_H,Stores status information for an initiator." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." group.byte 0x58++0x3 line.long 0x0 "L4_IA_ERROR_LOG_L,Log information about error conditions. The CODE field logs any protection violation or address hole errors detected by the initiator subsystem while decoding a request." bitfld.long 0x0 0.--2. " CMD ,Command that caused error" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--13. " CONNID ,ConnID of request causing the error, refer to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 14.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24.--25. " CODE ,The error code of an initiator request. 0x00: No errors 0x01: Reserved 0x10: Address hole 0x11: Protection violation" "0,1,2,3" bitfld.long 0x0 26.--29. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30. " SECONDARY ,Indicates whether protection violation was a primary or secondary error" "0,1" bitfld.long 0x0 31. " MULTI ,Multiple errors detected" "0,1" group.byte 0x5C++0x3 line.long 0x0 "L4_IA_ERROR_LOG_H,Log information about error conditions." hexmask.long.word 0x0 0.--15. 1. " REQ_INFO ,MReqInfo bits of request that caused the error REQ_INFO[0] = supervisor, REQ_INFO[1] = Debug" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x60++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_L,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " ADDR ,Address of request that caused the error. N is the number MAddr bits." group.byte 0x64++0x3 line.long 0x0 "L4_IA_ERROR_LOG_ADDR_H,Extended error log (address information)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "CFG_AP" base ad:0x4A000000 width 32. group.byte 0x0++0x3 line.long 0x0 "L4_AP_COMPONENT_L,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_AP_COMPONENT_H,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x100++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x108++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L_1,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x110++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L_2,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x104++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x10C++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H_1,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x114++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H_2,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x200++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x20C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x214++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x21C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x224++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x22C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x234++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x23C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x280++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x288++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x290++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x298++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A0++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A8++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B0++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B8++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x284++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x28C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x294++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x29C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A4++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2AC++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B4++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2BC++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x300++0x3 line.long 0x0 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x308++0x3 line.long 0x0 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x310++0x3 line.long 0x0 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x318++0x3 line.long 0x0 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x320++0x3 line.long 0x0 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x328++0x3 line.long 0x0 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x330++0x3 line.long 0x0 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x338++0x3 line.long 0x0 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x340++0x3 line.long 0x0 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x348++0x3 line.long 0x0 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x350++0x3 line.long 0x0 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x358++0x3 line.long 0x0 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x360++0x3 line.long 0x0 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x368++0x3 line.long 0x0 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x370++0x3 line.long 0x0 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x378++0x3 line.long 0x0 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x380++0x3 line.long 0x0 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x388++0x3 line.long 0x0 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x390++0x3 line.long 0x0 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x398++0x3 line.long 0x0 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x400++0x3 line.long 0x0 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x408++0x3 line.long 0x0 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x410++0x3 line.long 0x0 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x418++0x3 line.long 0x0 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x420++0x3 line.long 0x0 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x428++0x3 line.long 0x0 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x430++0x3 line.long 0x0 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x438++0x3 line.long 0x0 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x440++0x3 line.long 0x0 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x448++0x3 line.long 0x0 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x450++0x3 line.long 0x0 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x458++0x3 line.long 0x0 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x460++0x3 line.long 0x0 "L4_AP_REGION_l_L_44,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x468++0x3 line.long 0x0 "L4_AP_REGION_l_L_45,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x470++0x3 line.long 0x0 "L4_AP_REGION_l_L_46,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x478++0x3 line.long 0x0 "L4_AP_REGION_l_L_47,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x480++0x3 line.long 0x0 "L4_AP_REGION_l_L_48,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x488++0x3 line.long 0x0 "L4_AP_REGION_l_L_49,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x490++0x3 line.long 0x0 "L4_AP_REGION_l_L_50,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x498++0x3 line.long 0x0 "L4_AP_REGION_l_L_51,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_52,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_53,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_54,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_55,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_57,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_58,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_59,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_60,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_61,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_62,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_63,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x500++0x3 line.long 0x0 "L4_AP_REGION_l_L_64,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x508++0x3 line.long 0x0 "L4_AP_REGION_l_L_65,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x510++0x3 line.long 0x0 "L4_AP_REGION_l_L_66,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x518++0x3 line.long 0x0 "L4_AP_REGION_l_L_67,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x520++0x3 line.long 0x0 "L4_AP_REGION_l_L_68,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x528++0x3 line.long 0x0 "L4_AP_REGION_l_L_69,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x530++0x3 line.long 0x0 "L4_AP_REGION_l_L_70,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x538++0x3 line.long 0x0 "L4_AP_REGION_l_L_71,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x540++0x3 line.long 0x0 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x548++0x3 line.long 0x0 "L4_AP_REGION_l_L_73,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x550++0x3 line.long 0x0 "L4_AP_REGION_l_L_74,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x558++0x3 line.long 0x0 "L4_AP_REGION_l_L_75,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x560++0x3 line.long 0x0 "L4_AP_REGION_l_L_76,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x568++0x3 line.long 0x0 "L4_AP_REGION_l_L_77,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x570++0x3 line.long 0x0 "L4_AP_REGION_l_L_78,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x578++0x3 line.long 0x0 "L4_AP_REGION_l_L_79,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x580++0x3 line.long 0x0 "L4_AP_REGION_l_L_80,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x588++0x3 line.long 0x0 "L4_AP_REGION_l_L_81,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x590++0x3 line.long 0x0 "L4_AP_REGION_l_L_82,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x598++0x3 line.long 0x0 "L4_AP_REGION_l_L_83,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_84,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_85,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_86,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_87,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_88,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_89,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_90,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_91,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_92,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_93,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_94,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_95,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x600++0x3 line.long 0x0 "L4_AP_REGION_l_L_96,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x608++0x3 line.long 0x0 "L4_AP_REGION_l_L_97,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x610++0x3 line.long 0x0 "L4_AP_REGION_l_L_98,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x618++0x3 line.long 0x0 "L4_AP_REGION_l_L_99,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x620++0x3 line.long 0x0 "L4_AP_REGION_l_L_100,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x628++0x3 line.long 0x0 "L4_AP_REGION_l_L_101,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x630++0x3 line.long 0x0 "L4_AP_REGION_l_L_102,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x638++0x3 line.long 0x0 "L4_AP_REGION_l_L_103,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x640++0x3 line.long 0x0 "L4_AP_REGION_l_L_104,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x648++0x3 line.long 0x0 "L4_AP_REGION_l_L_105,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x650++0x3 line.long 0x0 "L4_AP_REGION_l_L_106,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x658++0x3 line.long 0x0 "L4_AP_REGION_l_L_107,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x660++0x3 line.long 0x0 "L4_AP_REGION_l_L_108,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x668++0x3 line.long 0x0 "L4_AP_REGION_l_L_109,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x670++0x3 line.long 0x0 "L4_AP_REGION_l_L_110,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x678++0x3 line.long 0x0 "L4_AP_REGION_l_L_111,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x680++0x3 line.long 0x0 "L4_AP_REGION_l_L_112,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x688++0x3 line.long 0x0 "L4_AP_REGION_l_L_113,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x690++0x3 line.long 0x0 "L4_AP_REGION_l_L_114,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x698++0x3 line.long 0x0 "L4_AP_REGION_l_L_115,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_116,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_117,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_118,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_119,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_120,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_121,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_122,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_123,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_124,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_125,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_126,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_127,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x700++0x3 line.long 0x0 "L4_AP_REGION_l_L_128,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x304++0x3 line.long 0x0 "L4_AP_REGION_l_H_0,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x30C++0x3 line.long 0x0 "L4_AP_REGION_l_H_1,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x314++0x3 line.long 0x0 "L4_AP_REGION_l_H_2,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x31C++0x3 line.long 0x0 "L4_AP_REGION_l_H_3,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x324++0x3 line.long 0x0 "L4_AP_REGION_l_H_4,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x32C++0x3 line.long 0x0 "L4_AP_REGION_l_H_5,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x334++0x3 line.long 0x0 "L4_AP_REGION_l_H_6,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x33C++0x3 line.long 0x0 "L4_AP_REGION_l_H_7,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x344++0x3 line.long 0x0 "L4_AP_REGION_l_H_8,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x34C++0x3 line.long 0x0 "L4_AP_REGION_l_H_9,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x354++0x3 line.long 0x0 "L4_AP_REGION_l_H_10,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x35C++0x3 line.long 0x0 "L4_AP_REGION_l_H_11,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x364++0x3 line.long 0x0 "L4_AP_REGION_l_H_12,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x36C++0x3 line.long 0x0 "L4_AP_REGION_l_H_13,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x374++0x3 line.long 0x0 "L4_AP_REGION_l_H_14,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x37C++0x3 line.long 0x0 "L4_AP_REGION_l_H_15,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L4_AP_REGION_l_H_16,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x38C++0x3 line.long 0x0 "L4_AP_REGION_l_H_17,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x394++0x3 line.long 0x0 "L4_AP_REGION_l_H_18,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x39C++0x3 line.long 0x0 "L4_AP_REGION_l_H_19,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_20,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_21,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_22,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_23,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_24,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_25,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_26,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_27,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_28,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_29,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_30,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_31,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x404++0x3 line.long 0x0 "L4_AP_REGION_l_H_32,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40C++0x3 line.long 0x0 "L4_AP_REGION_l_H_33,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x414++0x3 line.long 0x0 "L4_AP_REGION_l_H_34,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x41C++0x3 line.long 0x0 "L4_AP_REGION_l_H_35,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x424++0x3 line.long 0x0 "L4_AP_REGION_l_H_36,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x42C++0x3 line.long 0x0 "L4_AP_REGION_l_H_37,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x434++0x3 line.long 0x0 "L4_AP_REGION_l_H_38,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x43C++0x3 line.long 0x0 "L4_AP_REGION_l_H_39,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x444++0x3 line.long 0x0 "L4_AP_REGION_l_H_40,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x44C++0x3 line.long 0x0 "L4_AP_REGION_l_H_41,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x454++0x3 line.long 0x0 "L4_AP_REGION_l_H_42,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x45C++0x3 line.long 0x0 "L4_AP_REGION_l_H_43,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x464++0x3 line.long 0x0 "L4_AP_REGION_l_H_44,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x46C++0x3 line.long 0x0 "L4_AP_REGION_l_H_45,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x474++0x3 line.long 0x0 "L4_AP_REGION_l_H_46,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x47C++0x3 line.long 0x0 "L4_AP_REGION_l_H_47,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x484++0x3 line.long 0x0 "L4_AP_REGION_l_H_48,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x48C++0x3 line.long 0x0 "L4_AP_REGION_l_H_49,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x494++0x3 line.long 0x0 "L4_AP_REGION_l_H_50,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x49C++0x3 line.long 0x0 "L4_AP_REGION_l_H_51,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_52,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_53,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_54,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_55,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_56,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_57,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_58,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_59,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_60,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_61,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_62,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_63,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x504++0x3 line.long 0x0 "L4_AP_REGION_l_H_64,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50C++0x3 line.long 0x0 "L4_AP_REGION_l_H_65,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x514++0x3 line.long 0x0 "L4_AP_REGION_l_H_66,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x51C++0x3 line.long 0x0 "L4_AP_REGION_l_H_67,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x524++0x3 line.long 0x0 "L4_AP_REGION_l_H_68,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x52C++0x3 line.long 0x0 "L4_AP_REGION_l_H_69,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x534++0x3 line.long 0x0 "L4_AP_REGION_l_H_70,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x53C++0x3 line.long 0x0 "L4_AP_REGION_l_H_71,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x544++0x3 line.long 0x0 "L4_AP_REGION_l_H_72,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x54C++0x3 line.long 0x0 "L4_AP_REGION_l_H_73,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x554++0x3 line.long 0x0 "L4_AP_REGION_l_H_74,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x55C++0x3 line.long 0x0 "L4_AP_REGION_l_H_75,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x564++0x3 line.long 0x0 "L4_AP_REGION_l_H_76,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x56C++0x3 line.long 0x0 "L4_AP_REGION_l_H_77,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x574++0x3 line.long 0x0 "L4_AP_REGION_l_H_78,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x57C++0x3 line.long 0x0 "L4_AP_REGION_l_H_79,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x584++0x3 line.long 0x0 "L4_AP_REGION_l_H_80,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x58C++0x3 line.long 0x0 "L4_AP_REGION_l_H_81,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x594++0x3 line.long 0x0 "L4_AP_REGION_l_H_82,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x59C++0x3 line.long 0x0 "L4_AP_REGION_l_H_83,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_84,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_85,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_86,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_87,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_88,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_89,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_90,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_91,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_92,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_93,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_94,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_95,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x604++0x3 line.long 0x0 "L4_AP_REGION_l_H_96,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x60C++0x3 line.long 0x0 "L4_AP_REGION_l_H_97,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x614++0x3 line.long 0x0 "L4_AP_REGION_l_H_98,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x61C++0x3 line.long 0x0 "L4_AP_REGION_l_H_99,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x624++0x3 line.long 0x0 "L4_AP_REGION_l_H_100,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x62C++0x3 line.long 0x0 "L4_AP_REGION_l_H_101,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x634++0x3 line.long 0x0 "L4_AP_REGION_l_H_102,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x63C++0x3 line.long 0x0 "L4_AP_REGION_l_H_103,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x644++0x3 line.long 0x0 "L4_AP_REGION_l_H_104,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x64C++0x3 line.long 0x0 "L4_AP_REGION_l_H_105,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x654++0x3 line.long 0x0 "L4_AP_REGION_l_H_106,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x65C++0x3 line.long 0x0 "L4_AP_REGION_l_H_107,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x664++0x3 line.long 0x0 "L4_AP_REGION_l_H_108,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x66C++0x3 line.long 0x0 "L4_AP_REGION_l_H_109,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x674++0x3 line.long 0x0 "L4_AP_REGION_l_H_110,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x67C++0x3 line.long 0x0 "L4_AP_REGION_l_H_111,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x684++0x3 line.long 0x0 "L4_AP_REGION_l_H_112,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x68C++0x3 line.long 0x0 "L4_AP_REGION_l_H_113,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x694++0x3 line.long 0x0 "L4_AP_REGION_l_H_114,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x69C++0x3 line.long 0x0 "L4_AP_REGION_l_H_115,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_116,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_117,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_118,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_119,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_120,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_121,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_122,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_123,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_124,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_125,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_126,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x6FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_127,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x704++0x3 line.long 0x0 "L4_AP_REGION_l_H_128,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "PER2_AP" base ad:0x48400000 width 32. group.byte 0x0++0x3 line.long 0x0 "L4_AP_COMPONENT_L,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_AP_COMPONENT_H,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x100++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x104++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x200++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x20C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x214++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x21C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x224++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x22C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x234++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x23C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x280++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x288++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x290++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x298++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A0++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A8++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B0++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B8++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x284++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x28C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x294++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x29C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A4++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2AC++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B4++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2BC++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x300++0x3 line.long 0x0 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x308++0x3 line.long 0x0 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x310++0x3 line.long 0x0 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x318++0x3 line.long 0x0 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x320++0x3 line.long 0x0 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x328++0x3 line.long 0x0 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x330++0x3 line.long 0x0 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x338++0x3 line.long 0x0 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x340++0x3 line.long 0x0 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x348++0x3 line.long 0x0 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x350++0x3 line.long 0x0 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x358++0x3 line.long 0x0 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x360++0x3 line.long 0x0 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x368++0x3 line.long 0x0 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x370++0x3 line.long 0x0 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x378++0x3 line.long 0x0 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x380++0x3 line.long 0x0 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x388++0x3 line.long 0x0 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x390++0x3 line.long 0x0 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x398++0x3 line.long 0x0 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x400++0x3 line.long 0x0 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x408++0x3 line.long 0x0 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x410++0x3 line.long 0x0 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x418++0x3 line.long 0x0 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x420++0x3 line.long 0x0 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x428++0x3 line.long 0x0 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x430++0x3 line.long 0x0 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x438++0x3 line.long 0x0 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x440++0x3 line.long 0x0 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x448++0x3 line.long 0x0 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x450++0x3 line.long 0x0 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x458++0x3 line.long 0x0 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x460++0x3 line.long 0x0 "L4_AP_REGION_l_L_44,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x468++0x3 line.long 0x0 "L4_AP_REGION_l_L_45,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x470++0x3 line.long 0x0 "L4_AP_REGION_l_L_46,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x478++0x3 line.long 0x0 "L4_AP_REGION_l_L_47,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x480++0x3 line.long 0x0 "L4_AP_REGION_l_L_48,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x488++0x3 line.long 0x0 "L4_AP_REGION_l_L_49,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x490++0x3 line.long 0x0 "L4_AP_REGION_l_L_50,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x498++0x3 line.long 0x0 "L4_AP_REGION_l_L_51,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_52,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_53,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_54,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_55,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_57,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_58,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_59,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_60,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_61,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_62,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x304++0x3 line.long 0x0 "L4_AP_REGION_l_H_0,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x30C++0x3 line.long 0x0 "L4_AP_REGION_l_H_1,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x314++0x3 line.long 0x0 "L4_AP_REGION_l_H_2,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x31C++0x3 line.long 0x0 "L4_AP_REGION_l_H_3,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x324++0x3 line.long 0x0 "L4_AP_REGION_l_H_4,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x32C++0x3 line.long 0x0 "L4_AP_REGION_l_H_5,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x334++0x3 line.long 0x0 "L4_AP_REGION_l_H_6,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x33C++0x3 line.long 0x0 "L4_AP_REGION_l_H_7,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x344++0x3 line.long 0x0 "L4_AP_REGION_l_H_8,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x34C++0x3 line.long 0x0 "L4_AP_REGION_l_H_9,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x354++0x3 line.long 0x0 "L4_AP_REGION_l_H_10,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x35C++0x3 line.long 0x0 "L4_AP_REGION_l_H_11,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x364++0x3 line.long 0x0 "L4_AP_REGION_l_H_12,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x36C++0x3 line.long 0x0 "L4_AP_REGION_l_H_13,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x374++0x3 line.long 0x0 "L4_AP_REGION_l_H_14,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x37C++0x3 line.long 0x0 "L4_AP_REGION_l_H_15,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L4_AP_REGION_l_H_16,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x38C++0x3 line.long 0x0 "L4_AP_REGION_l_H_17,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x394++0x3 line.long 0x0 "L4_AP_REGION_l_H_18,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x39C++0x3 line.long 0x0 "L4_AP_REGION_l_H_19,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_20,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_21,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_22,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_23,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_24,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_25,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_26,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_27,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_28,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_29,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_30,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_31,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x404++0x3 line.long 0x0 "L4_AP_REGION_l_H_32,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40C++0x3 line.long 0x0 "L4_AP_REGION_l_H_33,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x414++0x3 line.long 0x0 "L4_AP_REGION_l_H_34,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x41C++0x3 line.long 0x0 "L4_AP_REGION_l_H_35,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x424++0x3 line.long 0x0 "L4_AP_REGION_l_H_36,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x42C++0x3 line.long 0x0 "L4_AP_REGION_l_H_37,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x434++0x3 line.long 0x0 "L4_AP_REGION_l_H_38,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x43C++0x3 line.long 0x0 "L4_AP_REGION_l_H_39,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x444++0x3 line.long 0x0 "L4_AP_REGION_l_H_40,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x44C++0x3 line.long 0x0 "L4_AP_REGION_l_H_41,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x454++0x3 line.long 0x0 "L4_AP_REGION_l_H_42,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x45C++0x3 line.long 0x0 "L4_AP_REGION_l_H_43,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x464++0x3 line.long 0x0 "L4_AP_REGION_l_H_44,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x46C++0x3 line.long 0x0 "L4_AP_REGION_l_H_45,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x474++0x3 line.long 0x0 "L4_AP_REGION_l_H_46,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x47C++0x3 line.long 0x0 "L4_AP_REGION_l_H_47,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x484++0x3 line.long 0x0 "L4_AP_REGION_l_H_48,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x48C++0x3 line.long 0x0 "L4_AP_REGION_l_H_49,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x494++0x3 line.long 0x0 "L4_AP_REGION_l_H_50,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x49C++0x3 line.long 0x0 "L4_AP_REGION_l_H_51,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_52,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_53,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_54,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_55,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_56,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_57,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_58,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_59,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_60,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_61,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_62,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "PER1_AP" base ad:0x48000000 width 32. group.byte 0x0++0x3 line.long 0x0 "L4_AP_COMPONENT_L,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code" hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code" group.byte 0x4++0x3 line.long 0x0 "L4_AP_COMPONENT_H,Contains a component code and revision, which are used to identify the hardware of the component." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x100++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L_0,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x108++0x3 line.long 0x0 "L4_AP_SEGMENT_i_L_1,Define the base address of each segments" hexmask.long 0x0 0.--31. 1. " BASE ,The base address of the segment (with 0s from bit 0 to bit SIZE-1)." group.byte 0x104++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H_0,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x10C++0x3 line.long 0x0 "L4_AP_SEGMENT_i_H_1,Define the size of each segments" bitfld.long 0x0 0.--4. " SIZE ,Segment size is a power of 2, where 2 is the byte size of a segment (all segment registers use the same size)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ,Read returns 0." group.byte 0x200++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_0,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_1,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_2,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_3,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_4,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_5,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_6,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_L_7,Define ConnID bit vectors for a protection group." hexmask.long.word 0x0 0.--15. 1. " CONNID_BIT_VECTOR ,Specifies protection group members N is 2**W, where W is the connID width" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x20C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x214++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x21C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x224++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x22C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x234++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x23C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_MEMBERS_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0's" group.byte 0x280++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_0,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x288++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_1,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x290++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_2,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x298++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_3,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A0++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_4,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A8++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_5,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B0++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_6,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B8++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_L_7,Define MReqInfo bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x284++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_0,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x28C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_1,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x294++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_2,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x29C++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_3,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2A4++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_4,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2AC++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_5,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2B4++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_6,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x2BC++0x3 line.long 0x0 "L4_AP_PROT_GROUP_ROLES_k_H_7,Define ConnID bit vectors for a protection group." hexmask.long 0x0 0.--31. 1. " ENABLE ,Enabled bits N is 2**W, where W (W is less than or equal to 6) is the number of MReqInfo bits configured for role checking" group.byte 0x300++0x3 line.long 0x0 "L4_AP_REGION_l_L_0,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x308++0x3 line.long 0x0 "L4_AP_REGION_l_L_1,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x310++0x3 line.long 0x0 "L4_AP_REGION_l_L_2,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x318++0x3 line.long 0x0 "L4_AP_REGION_l_L_3,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x320++0x3 line.long 0x0 "L4_AP_REGION_l_L_4,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x328++0x3 line.long 0x0 "L4_AP_REGION_l_L_5,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x330++0x3 line.long 0x0 "L4_AP_REGION_l_L_6,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x338++0x3 line.long 0x0 "L4_AP_REGION_l_L_7,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x340++0x3 line.long 0x0 "L4_AP_REGION_l_L_8,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x348++0x3 line.long 0x0 "L4_AP_REGION_l_L_9,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x350++0x3 line.long 0x0 "L4_AP_REGION_l_L_10,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x358++0x3 line.long 0x0 "L4_AP_REGION_l_L_11,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x360++0x3 line.long 0x0 "L4_AP_REGION_l_L_12,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x368++0x3 line.long 0x0 "L4_AP_REGION_l_L_13,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x370++0x3 line.long 0x0 "L4_AP_REGION_l_L_14,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x378++0x3 line.long 0x0 "L4_AP_REGION_l_L_15,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x380++0x3 line.long 0x0 "L4_AP_REGION_l_L_16,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x388++0x3 line.long 0x0 "L4_AP_REGION_l_L_17,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x390++0x3 line.long 0x0 "L4_AP_REGION_l_L_18,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x398++0x3 line.long 0x0 "L4_AP_REGION_l_L_19,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_20,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_21,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_22,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_23,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_24,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_25,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_26,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_27,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_28,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_29,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_30,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_31,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x400++0x3 line.long 0x0 "L4_AP_REGION_l_L_32,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x408++0x3 line.long 0x0 "L4_AP_REGION_l_L_33,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x410++0x3 line.long 0x0 "L4_AP_REGION_l_L_34,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x418++0x3 line.long 0x0 "L4_AP_REGION_l_L_35,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x420++0x3 line.long 0x0 "L4_AP_REGION_l_L_36,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x428++0x3 line.long 0x0 "L4_AP_REGION_l_L_37,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x430++0x3 line.long 0x0 "L4_AP_REGION_l_L_38,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x438++0x3 line.long 0x0 "L4_AP_REGION_l_L_39,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x440++0x3 line.long 0x0 "L4_AP_REGION_l_L_40,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x448++0x3 line.long 0x0 "L4_AP_REGION_l_L_41,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x450++0x3 line.long 0x0 "L4_AP_REGION_l_L_42,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x458++0x3 line.long 0x0 "L4_AP_REGION_l_L_43,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x460++0x3 line.long 0x0 "L4_AP_REGION_l_L_44,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x468++0x3 line.long 0x0 "L4_AP_REGION_l_L_45,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x470++0x3 line.long 0x0 "L4_AP_REGION_l_L_46,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x478++0x3 line.long 0x0 "L4_AP_REGION_l_L_47,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x480++0x3 line.long 0x0 "L4_AP_REGION_l_L_48,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x488++0x3 line.long 0x0 "L4_AP_REGION_l_L_49,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x490++0x3 line.long 0x0 "L4_AP_REGION_l_L_50,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x498++0x3 line.long 0x0 "L4_AP_REGION_l_L_51,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_52,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4A8++0x3 line.long 0x0 "L4_AP_REGION_l_L_53,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4B0++0x3 line.long 0x0 "L4_AP_REGION_l_L_54,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4B8++0x3 line.long 0x0 "L4_AP_REGION_l_L_55,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4C0++0x3 line.long 0x0 "L4_AP_REGION_l_L_56,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4C8++0x3 line.long 0x0 "L4_AP_REGION_l_L_57,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4D0++0x3 line.long 0x0 "L4_AP_REGION_l_L_58,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4D8++0x3 line.long 0x0 "L4_AP_REGION_l_L_59,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4E0++0x3 line.long 0x0 "L4_AP_REGION_l_L_60,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4E8++0x3 line.long 0x0 "L4_AP_REGION_l_L_61,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4F0++0x3 line.long 0x0 "L4_AP_REGION_l_L_62,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x4F8++0x3 line.long 0x0 "L4_AP_REGION_l_L_63,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x500++0x3 line.long 0x0 "L4_AP_REGION_l_L_64,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x508++0x3 line.long 0x0 "L4_AP_REGION_l_L_65,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x510++0x3 line.long 0x0 "L4_AP_REGION_l_L_66,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x518++0x3 line.long 0x0 "L4_AP_REGION_l_L_67,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x520++0x3 line.long 0x0 "L4_AP_REGION_l_L_68,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x528++0x3 line.long 0x0 "L4_AP_REGION_l_L_69,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x530++0x3 line.long 0x0 "L4_AP_REGION_l_L_70,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x538++0x3 line.long 0x0 "L4_AP_REGION_l_L_71,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x540++0x3 line.long 0x0 "L4_AP_REGION_l_L_72,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x548++0x3 line.long 0x0 "L4_AP_REGION_l_L_73,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x550++0x3 line.long 0x0 "L4_AP_REGION_l_L_74,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x558++0x3 line.long 0x0 "L4_AP_REGION_l_L_75,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x560++0x3 line.long 0x0 "L4_AP_REGION_l_L_76,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x568++0x3 line.long 0x0 "L4_AP_REGION_l_L_77,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x570++0x3 line.long 0x0 "L4_AP_REGION_l_L_78,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x578++0x3 line.long 0x0 "L4_AP_REGION_l_L_79,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x580++0x3 line.long 0x0 "L4_AP_REGION_l_L_80,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x588++0x3 line.long 0x0 "L4_AP_REGION_l_L_81,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x590++0x3 line.long 0x0 "L4_AP_REGION_l_L_82,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x598++0x3 line.long 0x0 "L4_AP_REGION_l_L_83,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5A0++0x3 line.long 0x0 "L4_AP_REGION_l_L_84,Define the base address of the region in respect to the segment it belongs to." hexmask.long.tbyte 0x0 0.--20. 1. " BASE ,Sets the base address of the region relative to its segment base." hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Read returns 0." group.byte 0x304++0x3 line.long 0x0 "L4_AP_REGION_l_H_0,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x30C++0x3 line.long 0x0 "L4_AP_REGION_l_H_1,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x314++0x3 line.long 0x0 "L4_AP_REGION_l_H_2,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x31C++0x3 line.long 0x0 "L4_AP_REGION_l_H_3,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x324++0x3 line.long 0x0 "L4_AP_REGION_l_H_4,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x32C++0x3 line.long 0x0 "L4_AP_REGION_l_H_5,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x334++0x3 line.long 0x0 "L4_AP_REGION_l_H_6,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x33C++0x3 line.long 0x0 "L4_AP_REGION_l_H_7,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x344++0x3 line.long 0x0 "L4_AP_REGION_l_H_8,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x34C++0x3 line.long 0x0 "L4_AP_REGION_l_H_9,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x354++0x3 line.long 0x0 "L4_AP_REGION_l_H_10,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x35C++0x3 line.long 0x0 "L4_AP_REGION_l_H_11,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x364++0x3 line.long 0x0 "L4_AP_REGION_l_H_12,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x36C++0x3 line.long 0x0 "L4_AP_REGION_l_H_13,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x374++0x3 line.long 0x0 "L4_AP_REGION_l_H_14,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x37C++0x3 line.long 0x0 "L4_AP_REGION_l_H_15,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x384++0x3 line.long 0x0 "L4_AP_REGION_l_H_16,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x38C++0x3 line.long 0x0 "L4_AP_REGION_l_H_17,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x394++0x3 line.long 0x0 "L4_AP_REGION_l_H_18,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x39C++0x3 line.long 0x0 "L4_AP_REGION_l_H_19,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_20,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_21,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_22,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_23,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_24,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_25,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_26,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_27,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_28,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_29,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_30,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x3FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_31,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x404++0x3 line.long 0x0 "L4_AP_REGION_l_H_32,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40C++0x3 line.long 0x0 "L4_AP_REGION_l_H_33,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x414++0x3 line.long 0x0 "L4_AP_REGION_l_H_34,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x41C++0x3 line.long 0x0 "L4_AP_REGION_l_H_35,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x424++0x3 line.long 0x0 "L4_AP_REGION_l_H_36,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x42C++0x3 line.long 0x0 "L4_AP_REGION_l_H_37,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x434++0x3 line.long 0x0 "L4_AP_REGION_l_H_38,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x43C++0x3 line.long 0x0 "L4_AP_REGION_l_H_39,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x444++0x3 line.long 0x0 "L4_AP_REGION_l_H_40,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x44C++0x3 line.long 0x0 "L4_AP_REGION_l_H_41,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x454++0x3 line.long 0x0 "L4_AP_REGION_l_H_42,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x45C++0x3 line.long 0x0 "L4_AP_REGION_l_H_43,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x464++0x3 line.long 0x0 "L4_AP_REGION_l_H_44,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x46C++0x3 line.long 0x0 "L4_AP_REGION_l_H_45,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x474++0x3 line.long 0x0 "L4_AP_REGION_l_H_46,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x47C++0x3 line.long 0x0 "L4_AP_REGION_l_H_47,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x484++0x3 line.long 0x0 "L4_AP_REGION_l_H_48,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x48C++0x3 line.long 0x0 "L4_AP_REGION_l_H_49,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x494++0x3 line.long 0x0 "L4_AP_REGION_l_H_50,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x49C++0x3 line.long 0x0 "L4_AP_REGION_l_H_51,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_52,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4AC++0x3 line.long 0x0 "L4_AP_REGION_l_H_53,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4B4++0x3 line.long 0x0 "L4_AP_REGION_l_H_54,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4BC++0x3 line.long 0x0 "L4_AP_REGION_l_H_55,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4C4++0x3 line.long 0x0 "L4_AP_REGION_l_H_56,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4CC++0x3 line.long 0x0 "L4_AP_REGION_l_H_57,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4D4++0x3 line.long 0x0 "L4_AP_REGION_l_H_58,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4DC++0x3 line.long 0x0 "L4_AP_REGION_l_H_59,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4E4++0x3 line.long 0x0 "L4_AP_REGION_l_H_60,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4EC++0x3 line.long 0x0 "L4_AP_REGION_l_H_61,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4F4++0x3 line.long 0x0 "L4_AP_REGION_l_H_62,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4FC++0x3 line.long 0x0 "L4_AP_REGION_l_H_63,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x504++0x3 line.long 0x0 "L4_AP_REGION_l_H_64,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50C++0x3 line.long 0x0 "L4_AP_REGION_l_H_65,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x514++0x3 line.long 0x0 "L4_AP_REGION_l_H_66,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x51C++0x3 line.long 0x0 "L4_AP_REGION_l_H_67,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x524++0x3 line.long 0x0 "L4_AP_REGION_l_H_68,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x52C++0x3 line.long 0x0 "L4_AP_REGION_l_H_69,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x534++0x3 line.long 0x0 "L4_AP_REGION_l_H_70,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x53C++0x3 line.long 0x0 "L4_AP_REGION_l_H_71,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x544++0x3 line.long 0x0 "L4_AP_REGION_l_H_72,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x54C++0x3 line.long 0x0 "L4_AP_REGION_l_H_73,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x554++0x3 line.long 0x0 "L4_AP_REGION_l_H_74,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x55C++0x3 line.long 0x0 "L4_AP_REGION_l_H_75,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x564++0x3 line.long 0x0 "L4_AP_REGION_l_H_76,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x56C++0x3 line.long 0x0 "L4_AP_REGION_l_H_77,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x574++0x3 line.long 0x0 "L4_AP_REGION_l_H_78,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x57C++0x3 line.long 0x0 "L4_AP_REGION_l_H_79,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x584++0x3 line.long 0x0 "L4_AP_REGION_l_H_80,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x58C++0x3 line.long 0x0 "L4_AP_REGION_l_H_81,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x594++0x3 line.long 0x0 "L4_AP_REGION_l_H_82,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x59C++0x3 line.long 0x0 "L4_AP_REGION_l_H_83,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x5A4++0x3 line.long 0x0 "L4_AP_REGION_l_H_84,Define the size, protection group and segment ID of the region" bitfld.long 0x0 0. " ENABLE ,0x0: Disable the region, no access allows 0x1: Enable the region, with access as define in registers" "0,1" bitfld.long 0x0 1.--6. " SIZE ,Define the size of the region in bytes. 2 equals the region." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 7. " RESERVED ,Read returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. " PHY_TARGET_ID ,Physical target ID" textline " " bitfld.long 0x0 15.--16. " RESERVED ,Read returns 0" "0,1,2,3" bitfld.long 0x0 17.--18. " BYTE_DATA_WIDTH_EXP ,Target data byte width" "0,1,2,3" textline " " bitfld.long 0x0 19. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 20.--22. " PROT_GROUP_ID ,Protection group ID" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 24.--26. " SEGMENT_ID ,Segment ID of the region" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Read returns 0" "0,1" bitfld.long 0x0 28.--31. " MADDRSPACE ,Target interconnect MAddrSpace" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "MAILBOX_TARG" base ad:0x4A0F5000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "SPINLOCK_TARG" base ad:0x4A0F7000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "OCP_WP_NOC_TARG" base ad:0x4A103000 width 23. group.byte 0x0++0x3 line.long 0x0 "L4_TA_COMPONENT_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " REV ,Component revision code." hexmask.long.word 0x0 16.--31. 1. " CODE ,Interconnect code." group.byte 0x4++0x3 line.long 0x0 "L4_TA_COMPONENT_H,Contains a component code and revision." hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x18++0x3 line.long 0x0 "L4_TA_CORE_L,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " CORE_REV ,Component revision code code" hexmask.long.word 0x0 16.--31. 1. " CORE_CODE ,Interconnect core code" group.byte 0x1C++0x3 line.long 0x0 "L4_TA_CORE_H,Contains a component code and revision." hexmask.long.word 0x0 0.--15. 1. " VENDOR_CODE ,Vendor revision core code" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_L,Enable error reporting" bitfld.long 0x0 0. " OCP_RESET ,The OCP_RESET field controls the OCP reset signal to the attached core. Setting this bit clears any pending transfers and resets the OCP interface. The bit must be cleared to deassert the OCP reset signal. When the software reset feature is available on a target agent, the target agent OCP must also have a reset signal directed to the target core." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8.--10. " REQ_TIMEOUT ,Time-out Bound. Values are: 0 - No time-out 1 - 1x base cycles. 2 - 4x base cycles. 3 - 16x base cycles. 4 - 64x base cycles." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 11.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR_REP ,Enable logging of error" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." group.byte 0x24++0x3 line.long 0x0 "L4_TA_AGENT_CONTROL_H,Enable clock power management" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Read returns 0." bitfld.long 0x0 8. " EXT_CLOCK ,When set to 1, the ext_clk_off_i signal on a target agent indicates when the target agent should shut off." "0,1" textline " " bitfld.long 0x0 9. " AUTO_WAKEUP_RESP_CODE ," "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_H,Error reporting" hexmask.long 0x0 0.--31. 1. " RESERVED ,Read returns 0" group.byte 0x2C++0x3 line.long 0x0 "L4_TA_AGENT_STATUS_L,Error reporting" bitfld.long 0x0 0. " OCP_RESET ,L3 Reset" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 8. " REQ_TIMEOUT ,Time-out status: 0x0: No request time-out 0x1: A request time-out has occurred" "0,1" hexmask.long.word 0x0 9.--23. 1. " RESERVED ,Read returns 0." textline " " bitfld.long 0x0 24. " SERROR ,Value of OCP SError signal" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Read returns 0." width 0x0B tree.end tree "BB2D" base ad:0x59000000 width 34. group.byte 0x0++0x3 line.long 0x0 "AQHICLOCKCONTROL,Clock control register." bitfld.long 0x0 0. " CLK3D_DIS ,Disable 3D clock" "0,1" bitfld.long 0x0 1. " CLK2D_DIS ,Disable 2D clock" "0,1" textline " " hexmask.long.byte 0x0 2.--8. 1. " FSCALE_VAL ," bitfld.long 0x0 9. " FSCALE_CMD_LOAD ," "0,1" textline " " bitfld.long 0x0 10. " DISABLE_RAM_CLOCK_GATING ,Disables clock gating for RAMs" "0,1" bitfld.long 0x0 11. " DISABLE_DEBUG_REGISTERS ,Disable debug registers. If this bit is 1, debug registers are clock gated" "0,1" textline " " bitfld.long 0x0 12. " SOFT_RESET ,Soft resets the subsystem" "0,1" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " IDLE3_D ,3D pipe is idle" "0,1" bitfld.long 0x0 17. " IDLE2_D ,2D pipe is idle" "0,1" textline " " bitfld.long 0x0 18. " IDLE_VG ,VG pipe is idle" "0,1" bitfld.long 0x0 19. " ISOLATE_GPU ,Isolate GPU bit" "0,1" textline " " bitfld.long 0x0 20.--23. " MULTI_PIPE_REG_SELECT ,Determines which HI/MC to use while reading registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24.--27. " MULTI_PIPE_USE_SINGLE_AXI ,Force all the transactions to go to one AXI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4++0x3 line.long 0x0 "AQHIIDLE,Idle status register." bitfld.long 0x0 0. " IDLE_FE ,FE is idle" "0,1" bitfld.long 0x0 1. " IDLE_DE ,DE is idle" "0,1" textline " " bitfld.long 0x0 2. " IDLE_PE ,PE is idle" "0,1" bitfld.long 0x0 3. " IDLE_SH ,SH is idle" "0,1" textline " " bitfld.long 0x0 4. " IDLE_PA ,PA is idle" "0,1" bitfld.long 0x0 5. " IDLE_SE ,SE is idle" "0,1" textline " " bitfld.long 0x0 6. " IDLE_RA ,RA is idle" "0,1" bitfld.long 0x0 7. " IDLE_TX ,TX is idle" "0,1" textline " " bitfld.long 0x0 8. " IDLE_VG ,VG is idle" "0,1" bitfld.long 0x0 9. " IDLE_IM ,IM is idle" "0,1" textline " " bitfld.long 0x0 10. " IDLE_FP ,FP is idle" "0,1" bitfld.long 0x0 11. " IDLE_TS ,TS is idle" "0,1" textline " " hexmask.long.tbyte 0x0 12.--30. 1. " RESERVED ,Unused bits reserved for future expansion" bitfld.long 0x0 31. " AXI_LP ,AXI is in low power mode" "0,1" group.byte 0x8++0x3 line.long 0x0 "AQAXICONFIG,AXI config" bitfld.long 0x0 0.--3. " AWID ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " ARID ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " AWCACHE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " ARCACHE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "AQAXISTATUS,AXI status" bitfld.long 0x0 0.--3. " WR_ERR_ID ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RD_ERR_ID ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " DET_WR_ERR ," "0,1" bitfld.long 0x0 9. " DET_RD_ERR ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "AQINTRACKNOWLEDGE,Interrupt acknowledge register. Each bit represents a corresponding event being triggered. Reading from this register clears the outstanding interrupt." hexmask.long 0x0 0.--31. 1. " INTR_VEC ," group.byte 0x14++0x3 line.long 0x0 "AQINTRENBL,Interrupt enable register. Each bit enables a corresponding event." hexmask.long 0x0 0.--31. 1. " INTR_ENBL_VEC ," group.byte 0x18++0x3 line.long 0x0 "AQIDENT,Identification register." hexmask.long.byte 0x0 0.--7. 1. " CUSTOMER ,Customer value" bitfld.long 0x0 8.--11. " TECHNOLOGY ,Technology value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12.--15. " REVISION ,Revision value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0 16.--23. 1. " PRODUCT ,Product value" textline " " hexmask.long.byte 0x0 24.--31. 1. " FAMILY ,Family value 0x1: GC500 0x2: GC520 0x3: GC530 0x4: GC400 0x5: GC450 0x8: GC600 0x9: GC700 0xA: GC350 0xB: GC380 0xC: GC800 0x10: GC1000 0x14: GC2000" group.byte 0x1C++0x3 line.long 0x0 "GCFEATURES,Shows which features are enabled in current subsystem implementation. 0 : NONE 1 : AVAILABLE" bitfld.long 0x0 0. " FAST_CLEAR ,Fast clear." "0,1" bitfld.long 0x0 1. " SPECIAL_ANTI_ALIASING ,Full-screen anti-aliasing." "0,1" textline " " bitfld.long 0x0 2. " PIPE_3D ,3D pipe." "0,1" bitfld.long 0x0 3. " DXT_TEXTURE_COMPRESSION ,DXT texture compression." "0,1" textline " " bitfld.long 0x0 4. " DEBUG_MODE ,Debug registers." "0,1" bitfld.long 0x0 5. " ZCOMPRESSION ,Depth and color compression." "0,1" textline " " bitfld.long 0x0 6. " YUV420_FILTER ,YUV 4:2:0 support in filter blit." "0,1" bitfld.long 0x0 7. " MSAA ,MSAA support." "0,1" textline " " bitfld.long 0x0 8. " DC ,Shows if there is a display controller." "0,1" bitfld.long 0x0 9. " PIPE_2D ,Shows if there is 2D engine." "0,1" textline " " bitfld.long 0x0 10. " ETC1_TEXTURE_COMPRESSION ,ETC1 texture compression." "0,1" bitfld.long 0x0 11. " FAST_SCALER ,Shows if there is HD scaler." "0,1" textline " " bitfld.long 0x0 12. " HIGH_DYNAMIC_RANGE ,Shows if there is HDR support." "0,1" bitfld.long 0x0 13. " YUV420_TILER ,YUV 4:2:0 tiler is available." "0,1" textline " " bitfld.long 0x0 14. " MODULE_CG ,Second level clock gating is available." "0,1" bitfld.long 0x0 15. " MIN_AREA ,Configured to have minimum area." "0,1" textline " " bitfld.long 0x0 16. " NO_EZ ,No early-Z." "0,1" bitfld.long 0x0 17. " NO422_TEXTURE ,No 422 texture input format." "0,1" textline " " bitfld.long 0x0 18. " BUFFER_INTERLEAVING ,Supports interleaving depth and color buffers." "0,1" bitfld.long 0x0 19. " BYTE_WRITE_2D ,Supports byte write in 2D." "0,1" textline " " bitfld.long 0x0 20. " NO_SCALER ,No 2D scaler." "0,1" bitfld.long 0x0 21. " YUY2_AVERAGING ,YUY2 averaging support in resolve." "0,1" textline " " bitfld.long 0x0 22. " HALF_PE_CACHE ,PE cache is half." "0,1" bitfld.long 0x0 23. " HALF_TX_CACHE ,TX cache is half." "0,1" textline " " bitfld.long 0x0 24. " YUY2_RENDER_TARGET ,YUY2 support in PE and YUY2 to RGB conversion in resolve." "0,1" bitfld.long 0x0 25. " MEM32_BIT_SUPPORT ,32 bit memory address support." "0,1" textline " " bitfld.long 0x0 26. " PIPE_VG ,VG pipe is present." "0,1" bitfld.long 0x0 27. " VGTS ,VG tesselator is present." "0,1" textline " " bitfld.long 0x0 28. " FE20 ,FE 2.0 is present." "0,1" bitfld.long 0x0 29. " BYTE_WRITE_3D ,3D PE has byte write capability." "0,1" textline " " bitfld.long 0x0 30. " RS_YUV_TARGET ,Supports resolveing into YUV target." "0,1" bitfld.long 0x0 31. " FE20_BIT_INDEX ,Supports 20 bit index." "0,1" group.byte 0x20++0x3 line.long 0x0 "GCCHIPID,Shows the ID for the subsystem in BCD." hexmask.long 0x0 0.--31. 1. " ID ,Subsystem ID in BCD" group.byte 0x24++0x3 line.long 0x0 "GCCHIPREV,Shows the revision for the subsystem in BCD." hexmask.long 0x0 0.--31. 1. " REV ,Revision in BCD" group.byte 0x28++0x3 line.long 0x0 "GCCHIPDATE,Shows the release date for the subsystem." hexmask.long 0x0 0.--31. 1. " DATE ,Release date" group.byte 0x2C++0x3 line.long 0x0 "GCCHIPTIME,Shows the release time for the subsystem." hexmask.long 0x0 0.--31. 1. " TIME ,Release time" group.byte 0x30++0x3 line.long 0x0 "GCCHIPCUSTOMER,Shows the customer and group for the subsystem." hexmask.long.word 0x0 0.--15. 1. " GROUP ,Group" hexmask.long.word 0x0 16.--31. 1. " COMPANY ,Company" group.byte 0x34++0x3 line.long 0x0 "GCMINORFEATURES0,Shows which minor features are enabled in the subsystem. 0 : NONE 1 : AVAILABLE" bitfld.long 0x0 0. " FLIP_Y ,Y flipping capability is added to resolve." "0,1" bitfld.long 0x0 1. " DUAL_RETURN_BUS ,Dual Return Bus from HI to clients." "0,1" textline " " bitfld.long 0x0 2. " ENDIANNESS_CONFIG ,Configurable endianness support." "0,1" bitfld.long 0x0 3. " TEXTURE8_K ,Supports 8K W 8K textures." "0,1" textline " " bitfld.long 0x0 4. " CORRECT_TEXTURE_CONVERTER ,Driver hack is not needed." "0,1" bitfld.long 0x0 5. " SPECIAL_MSAA_LOD ,Special LOD calculation when MSAA is on." "0,1" textline " " bitfld.long 0x0 6. " FAST_CLEAR_FLUSH ,Proper flush is done in fast clear cache." "0,1" bitfld.long 0x0 7. " PE20_2D ,2D PE 2.0 is present." "0,1" textline " " bitfld.long 0x0 8. " CORRECT_AUTO_DISABLE ,Reserved." "0,1" bitfld.long 0x0 9. " RENDER_8K ,Supports 8K render target." "0,1" textline " " bitfld.long 0x0 10. " TILE_STATUS_2BITS ,2 bits are used instead of 4 bits for tile status." "0,1" bitfld.long 0x0 11. " SEPARATE_TILE_STATUS_WHEN_INTERLEAVED ,Use 2 separate tile status buffers in interleaved mode." "0,1" textline " " bitfld.long 0x0 12. " SUPER_TILED_32X32 ,32 W 32 super tile is available." "0,1" bitfld.long 0x0 13. " VG_20 ,Major updates to VG pipe (TS buffer tiling. State masking.)." "0,1" textline " " bitfld.long 0x0 14. " TS_EXTENDED_COMMANDS ,New commands added to the tessellator." "0,1" bitfld.long 0x0 15. " COMPRESSION_FIFO_FIXED ,If this bit is not set, the FIFO counter should be set to 50. Else, the default should remain." "0,1" textline " " bitfld.long 0x0 16. " EXTRA_SHADER_INSTRUCTIONS0 ,Floor, ceil, and sign instructions are available." "0,1" bitfld.long 0x0 17. " VG_FILTER ,VG filter is available." "0,1" textline " " bitfld.long 0x0 18. " VG_21 ,Minor updates to VG pipe (Event generation from VG, TS, PE). Tiled image support." "0,1" bitfld.long 0x0 19. " SHADER_GETS_W ,W is sent to SH from RA." "0,1" textline " " bitfld.long 0x0 20. " EXTRA_SHADER_INSTRUCTIONS1 ,Sqrt, sin, cos instructions are available." "0,1" bitfld.long 0x0 21. " DEFAULT_REG0 ,Unavailable registers will return 0." "0,1" textline " " bitfld.long 0x0 22. " MC_20 ,New style MC with separate paths for color and depth." "0,1" bitfld.long 0x0 23. " SHADER_MSAA_SIDEBAND ,Put the MSAA data into sideband fifo." "0,1" textline " " bitfld.long 0x0 24. " BUG_FIXES0 ," "0,1" bitfld.long 0x0 25. " VAA ,VAA is available or not." "0,1" textline " " bitfld.long 0x0 26. " BYPASS_IN_MSAA ,Shader supports bypass mode when MSAA is enabled." "0,1" bitfld.long 0x0 27. " HIERARCHICAL_Z ,Hierarchiccal Z is supported." "0,1" textline " " bitfld.long 0x0 28. " NEW_TEXTURE ,New texture unit is available." "0,1" bitfld.long 0x0 29. " A8_TARGET_SUPPORT ,2D engine supports A8 target." "0,1" textline " " bitfld.long 0x0 30. " CORRECT_STENCIL ,Correct stencil behavior in depth only." "0,1" bitfld.long 0x0 31. " ENHANCE_VR ,Enhance VR and add a mode to walk 16 pixels in 16-bit mode in vertical pass to improve cache hit rate when rotating 90/270." "0,1" group.byte 0x3C++0x3 line.long 0x0 "GCRESETMEMCOUNTERS,Writing 1 will reset the counters and stop counting. Write 0 to start counting again." bitfld.long 0x0 0. " RESET ,1: reset the counters and stop counting 0: start counting" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "GCTOTALREADS,Total reads in terms of 64 bits." hexmask.long 0x0 0.--31. 1. " COUNT ,Total reads in terms of 64 bits" group.byte 0x44++0x3 line.long 0x0 "GCTOTALWRITES,Total writes in terms of 64 bits." hexmask.long 0x0 0.--31. 1. " COUNT ,Total writes in terms of 64 bits" group.byte 0x48++0x3 line.long 0x0 "GCCHIPSPECS,Specs for the subsystem." bitfld.long 0x0 0.--3. " STREAMS ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " TEMP_REGISTERS ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " THREAD_COUNT ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--16. " VERTEX_CACHE_SIZE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--24. " NUM_SHADER_CORES ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25.--27. " NUM_PIXEL_PIPES ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 28.--31. " VERTEX_OUTPUT_BUFFER_SIZE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x4C++0x3 line.long 0x0 "GCTOTALWRITEBURSTS,Total write data count in terms of 64 bits." hexmask.long 0x0 0.--31. 1. " COUNT ,Total write data count in terms of 64 bits" group.byte 0x50++0x3 line.long 0x0 "GCTOTALWRITEREQS,Total write request count." hexmask.long 0x0 0.--31. 1. " COUNT ,Total write request count" group.byte 0x54++0x3 line.long 0x0 "GCTOTALWRITELASTS,Total WLAST count. This is used to match with" hexmask.long 0x0 0.--31. 1. " COUNT ,Total WLAST count" group.byte 0x58++0x3 line.long 0x0 "GCTOTALREADBURSTS,Total read data count in terms of 64 bits." hexmask.long 0x0 0.--31. 1. " COUNT ,Total read data count in terms of 64 bits" group.byte 0x5C++0x3 line.long 0x0 "GCTOTALREADREQS,Total read request count." hexmask.long 0x0 0.--31. 1. " COUNT ,Total read request count" group.byte 0x60++0x3 line.long 0x0 "GCTOTALREADLASTS,Total RLAST count. This is used to match with" hexmask.long 0x0 0.--31. 1. " COUNT ,Total RLAST count" group.byte 0x64++0x3 line.long 0x0 "GCGPOUT0,General purpose output register." bitfld.long 0x0 0. " GCHOLD ,1 : Low power mode" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x70++0x3 line.long 0x0 "GCAXICONTROL,Special handling on AXI Bus" bitfld.long 0x0 0. " WR_FULL_BURST_MODE ,0: NO_BURST_RESET_VALUE 1: BURST_RESET_VALUE" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "GCMINORFEATURES1,Shows which features are enabled in the subsystem. 0 : NONE 1 : AVAILABLE" bitfld.long 0x0 0. " RSUV_SWIZZLE ,Resolve UV swizzle." "0,1" bitfld.long 0x0 1. " V2_COMPRESSION ,V2 compression." "0,1" textline " " bitfld.long 0x0 2. " VG_DOUBLE_BUFFER ,Double buffering support for VG (second TS-->VG semaphore is present)." "0,1" bitfld.long 0x0 3. " BUG_FIXES1 ," "0,1" textline " " bitfld.long 0x0 4. " BUG_FIXES2 ," "0,1" bitfld.long 0x0 5. " TEXTURE_STRIDE ,Texture has stride and memory addressing." "0,1" textline " " bitfld.long 0x0 6. " BUG_FIXES3 ," "0,1" bitfld.long 0x0 7. " CORRECT_AUTO_DISABLE ," "0,1" textline " " bitfld.long 0x0 8. " AUTO_RESTART_TS ," "0,1" bitfld.long 0x0 9. " BUG_FIXES4 ," "0,1" textline " " bitfld.long 0x0 10. " L2_WINDOWING ," "0,1" bitfld.long 0x0 11. " HALF_FLOAT_PIPE ," "0,1" textline " " bitfld.long 0x0 12. " PIXEL_DITHER ," "0,1" bitfld.long 0x0 13. " TWO_STENCIL_REFERENCE ," "0,1" textline " " bitfld.long 0x0 14. " EXTENDED_PIXEL_FORMAT ," "0,1" bitfld.long 0x0 15. " CORRECT_MIN_MAX_DEPTH ,EEZ and HZ are correct." "0,1" textline " " bitfld.long 0x0 16. " DITHER_AND_FILTER_PLUS_ALPHA_2D ,Dither and filter+alpha available." "0,1" bitfld.long 0x0 17. " BUG_FIXES5 ," "0,1" textline " " bitfld.long 0x0 18. " NEW_2D ," "0,1" bitfld.long 0x0 19. " NEW_FLOATING_POINT_ARITHMETIC ," "0,1" textline " " bitfld.long 0x0 20. " TEXTURE_HORIZONTAL_ALIGNMENT_SELECT ," "0,1" bitfld.long 0x0 21. " NON_POWER_OF_TWO ," "0,1" textline " " bitfld.long 0x0 22. " LINEAR_TEXTURE_SUPPORT ," "0,1" bitfld.long 0x0 23. " HALTI0 ," "0,1" textline " " bitfld.long 0x0 24. " CORRECT_OVERFLOW_VG ," "0,1" bitfld.long 0x0 25. " NEGATIVE_LOG_FIX ," "0,1" textline " " bitfld.long 0x0 26. " RESOLVE_OFFSET ," "0,1" bitfld.long 0x0 27. " OK_TO_GATE_AXI_CLOCK ," "0,1" textline " " bitfld.long 0x0 28. " MMU ," "0,1" bitfld.long 0x0 29. " WIDE_LINE ," "0,1" textline " " bitfld.long 0x0 30. " BUG_FIXES6 ," "0,1" bitfld.long 0x0 31. " FC_FLUSH_STALL ," "0,1" group.byte 0x78++0x3 line.long 0x0 "GCTOTALCYCLES,Total cycles. This register is a free running counter. It can be reset by writing 0 to it." hexmask.long 0x0 0.--31. 1. " CYCLES ,Total cycles" group.byte 0x7C++0x3 line.long 0x0 "GCTOTALIDLECYCLES,Total cycles where the GPU is idle. It is reset when register is written to. It looks at all the blocks but FE when determining the subsystem is idle." hexmask.long 0x0 0.--31. 1. " CYCLES ,Total cycles where the GPU is idle" group.byte 0x80++0x3 line.long 0x0 "GCCHIPSPECS2,Specs for the subsystem" hexmask.long.byte 0x0 0.--7. 1. " BUFFER_SIZE ," hexmask.long.byte 0x0 8.--15. 1. " INSTRUCTION_COUNT ," textline " " hexmask.long.word 0x0 16.--31. 1. " NUMBER_OF_CONSTANTS ," group.byte 0x84++0x3 line.long 0x0 "GCMINORFEATURES2,Shows which features are enabled in the subsystem 0 : NONE 1 : AVAILABLE" bitfld.long 0x0 0. " LINE_LOOP ," "0,1" bitfld.long 0x0 1. " LOGIC_OP ," "0,1" textline " " bitfld.long 0x0 2. " SEAMLESS_CUBE_MAP ," "0,1" bitfld.long 0x0 3. " SUPER_TILED_TEXTURE ," "0,1" textline " " bitfld.long 0x0 4. " LINEAR_PE ," "0,1" bitfld.long 0x0 5. " RECT_PRIMITIVE ," "0,1" textline " " bitfld.long 0x0 6. " COMPOSITION ," "0,1" bitfld.long 0x0 7. " CORRECT_AUTO_DISABLE_COUNT_WIDTH ," "0,1" textline " " bitfld.long 0x0 8. " PE_SWIZZLE ," "0,1" bitfld.long 0x0 9. " END_EVENT ," "0,1" textline " " bitfld.long 0x0 10. " S1S8 ," "0,1" bitfld.long 0x0 11. " HALTI1 ," "0,1" textline " " bitfld.long 0x0 12. " RGB888 ," "0,1" bitfld.long 0x0 13. " TX_YUV_ASSEMBLER ," "0,1" textline " " bitfld.long 0x0 14. " DYNAMIC_FREQUENCY_SCALING ," "0,1" bitfld.long 0x0 15. " TX_FILTER ," "0,1" textline " " bitfld.long 0x0 16. " FULL_DIRECT_FB ," "0,1" bitfld.long 0x0 17. " ONE_PASS_2D_FILTER ," "0,1" textline " " bitfld.long 0x0 18. " THREAD_WALKER_IN_PS ," "0,1" bitfld.long 0x0 19. " TILE_FILLER ," "0,1" textline " " bitfld.long 0x0 20. " YUV_STANDARD ," "0,1" bitfld.long 0x0 21. " MULTI_SOURCE_BLT ," "0,1" textline " " bitfld.long 0x0 22. " YUV_CONVERSION ," "0,1" bitfld.long 0x0 23. " FLUSH_FIXED_2D ," "0,1" textline " " bitfld.long 0x0 24. " INTERLEAVER ," "0,1" bitfld.long 0x0 25. " MIXED_STREAMS ," "0,1" textline " " bitfld.long 0x0 26. " NOT_USED ," "0,1" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28. " NO_INDEX_PATTERN ," "0,1" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x100++0x3 line.long 0x0 "GCMODULEPOWERCONTROLS,Control register for module level power controls." bitfld.long 0x0 0. " ENABLE_MODULE_CLOCK_GATING ,Enables module level clock gating" "0,1" bitfld.long 0x0 1. " DISABLE_STALL_MODULE_CLOCK_GATING ,Disables module level clock gating for stall condition" "0,1" textline " " bitfld.long 0x0 2. " DISABLE_STARVE_MODULE_CLOCK_GATING ,Disables module level clock gating for starve/idle condition" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--7. " TURN_ON_COUNTER ,Number of clock cycles to wait after turning on the clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--31. 1. " TURN_OFF_COUNTER ,Counter value for clock gating the module if the module is idle for this amount of clock cycles" group.byte 0x104++0x3 line.long 0x0 "GCMODULEPOWERMODULECONTROL,Module level control registers." bitfld.long 0x0 0. " DISABLE_MODULE_CLOCK_GATING_FE ,Enables module level clock gating" "0,1" bitfld.long 0x0 1. " DISABLE_MODULE_CLOCK_GATING_DE ,Disables module level clock gating for stall condition" "0,1" textline " " bitfld.long 0x0 2. " DISABLE_MODULE_CLOCK_GATING_PE ,Disables module level clock gating for starve/idle condition" "0,1" bitfld.long 0x0 3. " DISABLE_MODULE_CLOCK_GATING_SH ,Number of clock cycles to wait after turning on the clock" "0,1" textline " " bitfld.long 0x0 4. " DISABLE_MODULE_CLOCK_GATING_PA ,Counter value for clock gating the module if the module is idle for this amount of clock cycles" "0,1" bitfld.long 0x0 5. " DISABLE_MODULE_CLOCK_GATING_SE ,Enables module level clock gating" "0,1" textline " " bitfld.long 0x0 6. " DISABLE_MODULE_CLOCK_GATING_RA ,Disables module level clock gating for stall condition" "0,1" bitfld.long 0x0 7. " DISABLE_MODULE_CLOCK_GATING_TX ,Disables module level clock gating for starve/idle condition" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "GCMODULEPOWERMODULESTATUS,Module level control status" bitfld.long 0x0 0. " MODULE_CLOCK_GATED_FE ,Module level clock gating is ON for FE" "0,1" bitfld.long 0x0 1. " MODULE_CLOCK_GATED_DE ,Module level clock gating is ON for DE" "0,1" textline " " bitfld.long 0x0 2. " MODULE_CLOCK_GATED_PE ,Module level clock gating is ON for PE" "0,1" bitfld.long 0x0 3. " MODULE_CLOCK_GATED_SH ,Module level clock gating is ON for SH" "0,1" textline " " bitfld.long 0x0 4. " MODULE_CLOCK_GATED_PA ,Module level clock gating is ON for PA" "0,1" bitfld.long 0x0 5. " MODULE_CLOCK_GATED_SE ,Module level clock gating is ON for SE" "0,1" textline " " bitfld.long 0x0 6. " MODULE_CLOCK_GATED_RA ,Module level clock gating is ON for RA" "0,1" bitfld.long 0x0 7. " MODULE_CLOCK_GATED_TX ,Module level clock gating is ON for TX" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x188++0x3 line.long 0x0 "GCREGMMUSTATUS,Status register that holds which MMU generated an exception" bitfld.long 0x0 0.--1. " EXCEPTION0 ,MMU 0 caused an exception and theGCREGMMUEXCEPTION0 holds the offending address: 0x1: SLAVE_NOT_PRESENT 0x2: PAGE_NOT_PRESENT 0x3: WRITE_VIOLATION" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ,NOT USED" "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " EXCEPTION1 ,MMU 1 caused an exception and theGCREGMMUEXCEPTION1 register holds the offending address. 0x1: SLAVE_NOT_PRESENT 0x2: PAGE_NOT_PRESENT 0x3: WRITE_VIOLATION" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,NOT USED" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " EXCEPTION2 ,MMU 2 caused an exception and theGCREGMMUEXCEPTION2 register holds the offending address. 0x1: SLAVE_NOT_PRESENT 0x2: PAGE_NOT_PRESENT 0x3: WRITE_VIOLATION" "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ,NOT USED" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " EXCEPTION3 ,MMU 3 caused an exception and theGCREGMMUEXCEPTION3 register holds the offending address. 0x1: SLAVE_NOT_PRESENT 0x2: PAGE_NOT_PRESENT 0x3: WRITE_VIOLATION" "0,1,2,3" hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,NOT USED" group.byte 0x18C++0x3 line.long 0x0 "GCREGMMUCONTROL,Control register that enables the MMU (one time shot)." bitfld.long 0x0 0. " ENABLE ,Enable the MMU. For security reasons, once the MMU is enabled it cannot be disabled until reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,NOT USED" group.byte 0x190++0x3 line.long 0x0 "GCREGMMUEXCEPTION0,Holds the original address that generated an exception" hexmask.long 0x0 0.--31. 1. " ADDRESS ,The original address that generated an exception" group.byte 0x194++0x3 line.long 0x0 "GCREGMMUEXCEPTION1,Holds the original address that generated an exception" hexmask.long 0x0 0.--31. 1. " ADDRESS ,The original address that generated an exception" group.byte 0x198++0x3 line.long 0x0 "GCREGMMUEXCEPTION2,Holds the original address that generated an exception" hexmask.long 0x0 0.--31. 1. " ADDRESS ,The original address that generated an exception" group.byte 0x19C++0x3 line.long 0x0 "GCREGMMUEXCEPTION3,Holds the original address that generated an exception" hexmask.long 0x0 0.--31. 1. " ADDRESS ,The original address that generated an exception" group.byte 0x414++0x3 line.long 0x0 "AQMEMORYDEBUG,AQMEMORYDEBUG" hexmask.long.byte 0x0 0.--7. 1. " MAX_OUTSTANDING_READS ,Limits the total number of outstanding read requests." bitfld.long 0x0 8.--13. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 14. " DISABLE_MINI_MMU_CACHE ," "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 17. " INTERLEAVE_BUFFER_LOW_LATENCY_MODE ," "0,1" bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 19. " LIMIT_CONTROL ,Limit control 0: REQUESTS 1: DATA" "0,1" bitfld.long 0x0 20.--21. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 22. " DISABLE_STALL_READS ," "0,1" bitfld.long 0x0 23. " DISABLE_WRITE_DATA_SPEEDUP ," "0,1" textline " " bitfld.long 0x0 24.--29. " ZCOMP_LIMIT ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 30. " DONT_STALL_WRITES_TO_SAME_ADDRESS ," "0,1" textline " " bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x42C++0x3 line.long 0x0 "AQREGISTERTIMINGCONTROL,AQREGISTERTIMINGCONTROL" hexmask.long.byte 0x0 0.--7. 1. " FOR_RF1P ," hexmask.long.byte 0x0 8.--15. 1. " FOR_RF2P ," textline " " bitfld.long 0x0 16.--17. " FAST_RTC ,RTC for fast RAMs" "0,1,2,3" bitfld.long 0x0 18.--19. " FAST_WTC ,WTC for fast RAMs" "0,1,2,3" textline " " bitfld.long 0x0 20. " POWER_DOWN ,Powerdown memory" "0,1" bitfld.long 0x0 21. " DEEP_SLEEP ,Deep sleep" "0,1" textline " " bitfld.long 0x0 22. " LIGHT_SLEEP ,Light sleep" "0,1" hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x434++0x3 line.long 0x0 "GCDISPLAYPRIORITY,Controls the priority of the display controller requests. This works like a PWM. One register gives the period, and the other gives the ON time. When PWM is ON, display requests are accepted if both display and the other request is valid. If it is OFF, the other request will be accepted. If only one request is valid, it takes the bus regardless of the PWM bit." hexmask.long.byte 0x0 0.--7. 1. " PERIOD ,Period" hexmask.long.byte 0x0 8.--15. 1. " HIGH ,'Duty cycle'" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x438++0x3 line.long 0x0 "GCDBGCYCLECOUNTER,Increments every cycle." hexmask.long 0x0 0.--31. 1. " COUNT ,Increments every cycle" group.byte 0x43C++0x3 line.long 0x0 "GCOUTSTANDINGREADS0,Number of outstanding reads per client in multiples of 8 bytes." hexmask.long.byte 0x0 0.--7. 1. " PEC ,Number of outstanding PEC reads in multiples of 8 bytes" hexmask.long.byte 0x0 8.--15. 1. " PEZ ,Number of outstanding PEZ reads in multiples of 8 bytes" textline " " hexmask.long.byte 0x0 16.--23. 1. " FE ,Number of outstanding FE reads in multiples of 8 bytes" hexmask.long.byte 0x0 24.--31. 1. " MMU ,Number of outstanding MMU reads in multiples of 8 bytes" group.byte 0x440++0x3 line.long 0x0 "GCOUTSTANDINGREADS1,Number of outstanding reads per client in multiples of 8 bytes." hexmask.long.byte 0x0 0.--7. 1. " RA ,Number of outstanding RA reads in multiples of 8 bytes" hexmask.long.byte 0x0 8.--15. 1. " TX ,Number of outstanding TX reads in multiples of 8 bytes" textline " " hexmask.long.byte 0x0 16.--23. 1. " FC ,Number of outstanding FC reads in multiples of 8 bytes" hexmask.long.byte 0x0 24.--31. 1. " TOTAL ,This field keeps the value of total read requests or total requested data (in 64 bits) depending on the value ofAQMEMORYDEBUG[19] LIMIT_CONTROL register field." group.byte 0x444++0x3 line.long 0x0 "GCOUTSTANDINGWRITES,Number of outstanding writes per client." hexmask.long.byte 0x0 0.--7. 1. " PEC ,Number of outstanding PEC writes in multiples of 8 bytes" hexmask.long.byte 0x0 8.--15. 1. " PEZ ,Number of outstanding PEZ writes in multiples of 8 bytes" textline " " hexmask.long.byte 0x0 16.--23. 1. " FC ,Number of outstanding FC writes in multiples of 8 bytes" hexmask.long.byte 0x0 24.--31. 1. " TOTAL ,This field keeps the value of total write requests or total requested data (in 64 bits) depending on the value ofAQMEMORYDEBUG[19] LIMIT_CONTROL register field." group.byte 0x448++0x3 line.long 0x0 "GCDEBUGSIGNALSRA,32 bit debug signal from RA." hexmask.long 0x0 0.--31. 1. " SIGNAL ,Signals according toGCDEBUGCONTROL1[19:16] RA: 0x0: Valid pixel count. 0x1: Total quad count (after EEZ). 0x2: Valid quad count (after EZ and EEZ). 0x3: Total primitive count. 0x4: Various signals from input stage. See GC320 spec for details. 0x5: Various signals from input stage. See GC320 spec for details. 0x6: Various signals from render pipe. See GC320 spec for details. 0x7: Various signals from render cache. See GC320 spec for details. 0x8: Various signals from raster engine. See GC320 spec for details. 0x9: Cache miss count (in the pipeline). 0xA: Cache miss count (in the prefetcher). 0xB: EEZ culled quads. 0xF: Signature = 0x12344321." group.byte 0x44C++0x3 line.long 0x0 "GCDEBUGSIGNALSTX,32 bit debug signal from TX." hexmask.long 0x0 0.--31. 1. " SIGNAL ,Signals according toGCDEBUGCONTROL1[27:24] TX : 0x0: Total bilinear texture requests. 0x1: Total trilinear texture requests. 0x2: Total discarded texture requests. 0x3: Total texture requests. 0x4: Various signals from input stage. See GC320 spec for details. 0x5: Memory read count. 0x6: Memory read count in 8B. 0x7: Cache miss count (in the pipeline). 0x8: Total hitting texels (in pre-fetcher). 0x9: Total missing texels (in pre-fetcher). 0xF: Signature = 0x12211221." group.byte 0x450++0x3 line.long 0x0 "GCDEBUGSIGNALSFE,32 bit debug signal from FE." hexmask.long 0x0 0.--31. 1. " SIGNAL ," group.byte 0x454++0x3 line.long 0x0 "GCDEBUGSIGNALSPE,32 bit debug signal from PE." hexmask.long 0x0 0.--31. 1. " SIGNAL ,Signals according toGCDEBUGCONTROL0[19:16] PE: 0x0: pixel count killed by color pipe 0x1: pixel count killed by depth pipe 0x2: pixel count drawn by color pipe 0x3: pixel count drawn by depth pipe 0x4: debug signals for 3d_io, 2d_filter, 2d_fsm 0x5: debug signals for cache2d_cntrl 0x6: debug signals for cache2d_tag_alloc 0x7: debug signals for cache3d_c_cntrl, cache3d_c_tag_alloc 0x8: debug signals for cache3d_z_cntrl, cache3d_z_tag_alloc 0x9: debug signals for pref_2d, pref_3d 0xA : debug signals for cmd_state 0xB: 2d pixel count drawn by 2d pipe 0xF: Signature = 0xBABEF00D." group.byte 0x458++0x3 line.long 0x0 "GCDEBUGSIGNALSDE,32 bit debug signal from DE." hexmask.long 0x0 0.--31. 1. " SIGNAL ," group.byte 0x45C++0x3 line.long 0x0 "GCDEBUGSIGNALSSH,32 bit debug signal from SH." hexmask.long 0x0 0.--31. 1. " SIGNAL ,Signals according toGCDEBUGCONTROL0[27:24] SH. Please refer to GC320 spec for bit position information for all the signals 0x0 : interface signals for debug 0x1 : Instruction Sequencing and vertex input state machine 0x2 : vertex input/output buffer full/empty. Context PC. Physical page valid 0x3 : vertex/pixel, output attribute counts. Some interface signals 0x4 : Shader cycle count, for determining the shader clock 0x5 : Current pixel XY value 0x6 : Last pixels XY value 0x7 : Total pixel instructions executed 0x8 : Total pixels shaded 0x9 : Total vertex instructions executed 0xA : Total vertices shaded 0xB : Total vertex branch instructions 0xC : Total vertex texture instructions 0xD : Total pixel branch instructions 0xE : Total pixel texture instructions 0xF : Reserved signature 0xDEADBEEF" group.byte 0x460++0x3 line.long 0x0 "GCDEBUGSIGNALSPA,32 bit debug signal from PA." hexmask.long 0x0 0.--31. 1. " SIGNAL ,Signals according toGCDEBUGCONTROL1[3:0] PA: 0x0: Various signals from input stage. See GC320 spec for details. 0x1: Various signals from input stage. See GC320 spec for details. 0x2: Various signals from input stage. See GC320 spec for details. 0x3: total vertex count 0x4: input primitive count 0x5: output primitive count 0x6: depth clipped primitive count 0x7: trivial rejected primitive count 0x8: culled primitive count 0xF: Signature = 0x0000AAAA" group.byte 0x464++0x3 line.long 0x0 "GCDEBUGSIGNALSSE,32 bit debug signal from SE." hexmask.long 0x0 0.--31. 1. " SIGNAL ,Signals according toGCDEBUGCONTROL1[11:8] SE: 0x0: culled triangles count. 0x1: culled lines count. 0x2: [31:18] goto signals, [17:8] main state machine state, [7:0] output state machine state. See GC320 spec for details. 0x3: [31:22] unused, [21] early_isTriangle, [20] isTriangle, [19] increment_pc_e0, [18:14] jump_to_signals. See GC320 spec for details. [13:12] max_x_p_e2, [11:10] mid_x_p_e2, [9:8] min_x_p_e2, [7:6] max_y_p_e2, [5:4] mid_y_p_e2. See GC320 spec for details. [3:2] min_y_p_e2, [1:0] min_z_p_e2. See GC320 spec for details. 0x4: area_e2. See GC320 spec for details. 0x5: x0_e2. See GC320 spec for details. 0x6: x1_e2. See GC320 spec for details. 0x7: x2_e2. See GC320 spec for details. 0x8: y0_e2. See GC320 spec for details. 0x9: y1_e2. See GC320 spec for details. 0xA: y2_e2. See GC320 spec for details. 0xB: init_y_e2. See GC320 spec for details. 0xC: init_y_e2. See GC320 spec for details. 0xD: y2_e2. See GC320 spec for details. 0xE: y2_e2. See GC320 spec for details. 0xF: Signature = 0x5E5E5E5E." group.byte 0x468++0x3 line.long 0x0 "GCDEBUGSIGNALSMC,32 bit debug signal from MC." hexmask.long 0x0 0.--31. 1. " SIGNAL ,Signals according toGCDEBUGCONTROL2[3:0] MC: 0x0: Various signals from FC block. See GC320 spec for details. 0x1: Total read req in terms of 8B from pipeline. 0x2: Total read req in terms of 8B sent out from the subsystem. 0x3: Total write req in terms of 8B from pipeline. 0xF: Signature = 0x12345678." group.byte 0x46C++0x3 line.long 0x0 "GCDEBUGSIGNALSHI,32 bit debug signal from HI." hexmask.long 0x0 0.--31. 1. " SIGNAL ,Signals according toGCDEBUGCONTROL2[11:8] HI: 0x0: Number of cycles AXI read request is stalled. 0x1: Number of cycles AXI write request is stalled. 0x2: Number of cycles AXI write data is stalled. 0xF: Signature = 0xAAAAAAAA" group.byte 0x470++0x3 line.long 0x0 "GCDEBUGCONTROL0,GCDEBUGCONTROL0" bitfld.long 0x0 0.--3. " FE ,Selects which set of 32 bit data to get from FE. Resets the counters if set to 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " DE ,Selects which set of 32 bit data to get from DE. Resets the counters if set to 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " PE ,Selects which set of 32 bit data to get from PE. Resets the counters if set to 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " SH ,Selects which set of 32 bit data to get from SH. Resets the counters if set to 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x474++0x3 line.long 0x0 "GCDEBUGCONTROL1,GCDEBUGCONTROL1" bitfld.long 0x0 0.--3. " PA ,Selects which set of 32 bit data to get from PA. Resets the counters if set to 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " SE ,Selects which set of 32 bit data to get from SE. Resets the counters if set to 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RA ,Selects which set of 32 bit data to get from RA. Resets the counters if set to 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " TX ,Selects which set of 32 bit data to get from TX. Resets the counters if set to 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x478++0x3 line.long 0x0 "GCDEBUGCONTROL2,GCDEBUGCONTROL2" bitfld.long 0x0 0.--3. " MC ,Selects which set of 32 bit data to get from MC. Resets the counters if set to 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HI ,Selects which set of 32 bit data to get from HI. Resets the counters if set to 0xF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x47C++0x3 line.long 0x0 "GCDEBUGCONTROL3,GCDEBUGCONTROL3" bitfld.long 0x0 0.--3. " PROBE0 ,Selects which module's output will be put in the LSB 32 bits of 64 bit debug signal. 0x0: FE 0x1: DE 0x2: PE 0x3: SH 0x4: PA 0x5: SE 0x6: RA 0x7: TX 0x8: MC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PROBE1 ,Selects which module's output will be put in the MSB 32 bits of 64 bit debug signal. 0x0: FE 0x1: DE 0x2: PE 0x3: SH 0x4: PA 0x5: SE 0x6: RA 0x7: TX 0x8: MC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x480++0x3 line.long 0x0 "GCBUSCONTROL,Shows which features are enabled in the subsystem. 0 : NONE 1 : AVAILABLE" bitfld.long 0x0 0. " PEC ,Select the return bus for PEC" "0,1" bitfld.long 0x0 1. " PEZ ,Select the return bus for PEZ" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ," "0,1" bitfld.long 0x0 3. " FE ,Select the return bus for FE" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5. " MMU ,Select the return bus for MMU" "0,1" textline " " bitfld.long 0x0 6. " FC ,Select the return bus for FC-Depth" "0,1" bitfld.long 0x0 7. " TX ,Select the return bus for TX" "0,1" textline " " bitfld.long 0x0 8. " FCC ,Select the return bus for FCC" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x484++0x3 line.long 0x0 "GCREGENDIANNESS0,GCREGENDIANNESS0" hexmask.long 0x0 0.--31. 1. " WORD_SWAP ,Flip the words of 32 bit data. 0x12345678 becomes 0x56781234" group.byte 0x488++0x3 line.long 0x0 "GCREGENDIANNESS1,GCREGENDIANNESS1" hexmask.long 0x0 0.--31. 1. " BYTE_SWAP ,Flip the bytes of 16 bit data. 0x12345678 becomes 0x34127856" group.byte 0x48C++0x3 line.long 0x0 "GCREGENDIANNESS2,GCREGENDIANNESS2" hexmask.long 0x0 0.--31. 1. " BIT_SWAP ,Flip the bits of 8 bit data. 0x12345678 becomes 0x84C2A6E1" group.byte 0x490++0x3 line.long 0x0 "GCREGDRAWPRIMITIVESTARTTIMESTAMP,GCREGDRAWPRIMITIVESTARTTIMESTAMP" hexmask.long 0x0 0.--31. 1. " START_TIME ,32-bit timestamp when PE received draw_primitive_start command" group.byte 0x494++0x3 line.long 0x0 "GCREGDRAWPRIMITIVEENDTIMESTAMP,GCREGDRAWPRIMITIVEENDTIMESTAMP" hexmask.long 0x0 0.--31. 1. " END_TIME ,32-bit timestamp when PE received draw_primitive_end command" group.byte 0x558++0x3 line.long 0x0 "GCREGCONTROL0,Composition trigger." bitfld.long 0x0 0. " ENABLE_READ_MERGE ," "0,1" bitfld.long 0x0 1. " ENABLE_UNALIGNED_MERGE ," "0,1" textline " " bitfld.long 0x0 2. " ENABLE_WRITE_MERGE ," "0,1" bitfld.long 0x0 3. " ENABLE_UNALIGNED_WRITE_MERGE ," "0,1" textline " " hexmask.long.word 0x0 4.--15. 1. " MISC0 ," hexmask.long.word 0x0 16.--25. 1. " OUTSTANDING_READS_PER_CHANNEL ," textline " " bitfld.long 0x0 26.--31. " MISC1 ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x654++0x3 line.long 0x0 "AQCMDBUFFERADDR,Base address for the command buffer. The address must be 64-bit aligned and it is always physical. To use addresses above 0x8000_0000, program AQMemoryFE with the appropriate offset. Also, this register cannot be read. To check the value of the current fetch address use." hexmask.long 0x0 0.--30. 1. " ADDRESS ,ADDRESS" bitfld.long 0x0 31. " TYPE ,0: SYSTEM 1: VIRTUAL_SYSTEM" "0,1" group.byte 0x658++0x3 line.long 0x0 "AQCMDBUFFERCTRL,Command buffer control" hexmask.long.word 0x0 0.--15. 1. " PREFETCH ,Number of 64-bit words to fetch from the command buffer." bitfld.long 0x0 16. " ENABLE ,Command buffer 0: DISABLE 1: ENABLE" "0,1" textline " " bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--21. " ENDIAN_CONTROL ,Endian control 0: NO_SWAP 1: SWAP_WORD 2: SWAP_DWORD" "0,1,2,3" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x65C++0x3 line.long 0x0 "AQFESTATUS,FE status" bitfld.long 0x0 0. " COMMAND_DATA ,Status of the command parser. 0: Idle 1: Busy" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x664++0x3 line.long 0x0 "AQFEDEBUGCURCMDADR,This is the command decoder address. The address is always physical so the MSB should always be 0." bitfld.long 0x0 0.--2. " RESERVED ," "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " CUR_CMD_ADR ," width 0x0B tree.end tree "DMM" base ad:0x4E000000 width 23. group.byte 0x0++0x3 line.long 0x0 "DMM_REVISION,DMM revision number" hexmask.long 0x0 0.--31. 1. " REVISION ,Revision number" group.byte 0x4++0x3 line.long 0x0 "DMM_HWINFO,DMM hardware configuration" bitfld.long 0x0 0.--4. " SECTION_CNT ,Number of DMM sections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " SDRC_CNT ,Number of attached SDRAM controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "DMM_LISA_HWINFO,DMM hardware configuration for LISA" bitfld.long 0x0 0.--4. " SECTION_CNT ,Number of DMM sections" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--11. " SDRC_CNT ,Number of attached SDRAM controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "DMM_SYSCONFIG,DMM clock management configuration" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " IDLE_MODE ,Configuration of the local target state management mode." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "DMM_LISA_LOCK,DMM memory mapping lock" bitfld.long 0x0 0. " LOCK ,DMM lock map" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Should be written as 0" group.byte 0x20++0x3 line.long 0x0 "DMM_EMERGENCY,DMM memory mapping register" bitfld.long 0x0 0. " ENABLE ,0: Emergency feature is disabled.The recommendation is to enable the feature (=1) after reset. enum=UNLOCKED ." "0,1" hexmask.long.word 0x0 1.--15. 1. " Reserved ,Reserved" textline " " bitfld.long 0x0 16.--20. " WEIGHT ,Weight for the LISA arbitration when any bit of the vector Mflag[63:0] is set.The recommendation is to set this field to 0x8 with ENABLE =1, after reset. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "DMM_LISA_MAP_i_0,DMM memory mapping register" hexmask.long.byte 0x0 0.--7. 1. " SDRC_ADDR ,SDRAM controller address MSB for view mapping i" bitfld.long 0x0 8.--9. " SDRC_MAP ,SDRAM controller mapping for view mapping i 0x0: Unmapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be 0x3 and SDRC_INTL must be a nonzero value." "0,1,2,3" textline " " bitfld.long 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 16.--17. " SDRC_ADDRSPC ,SDRAM controller address space for view mapping i" "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " SDRC_INTL ,SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled regions, interleaving is forced to 1kiB. SDRC_INTL is don't care if SDRC_MAP is not 0x3 (no interleaving)." "0,1,2,3" bitfld.long 0x0 20.--22. " SYS_SIZE ,DMM system section size for view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" hexmask.long.byte 0x0 24.--31. 1. " SYS_ADDR ,DMM system section address MSB for view mapping i" group.byte 0x44++0x3 line.long 0x0 "DMM_LISA_MAP_i_1,DMM memory mapping register" hexmask.long.byte 0x0 0.--7. 1. " SDRC_ADDR ,SDRAM controller address MSB for view mapping i" bitfld.long 0x0 8.--9. " SDRC_MAP ,SDRAM controller mapping for view mapping i 0x0: Unmapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be 0x3 and SDRC_INTL must be a nonzero value." "0,1,2,3" textline " " bitfld.long 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 16.--17. " SDRC_ADDRSPC ,SDRAM controller address space for view mapping i" "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " SDRC_INTL ,SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled regions, interleaving is forced to 1kiB. SDRC_INTL is don't care if SDRC_MAP is not 0x3 (no interleaving)." "0,1,2,3" bitfld.long 0x0 20.--22. " SYS_SIZE ,DMM system section size for view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" hexmask.long.byte 0x0 24.--31. 1. " SYS_ADDR ,DMM system section address MSB for view mapping i" group.byte 0x48++0x3 line.long 0x0 "DMM_LISA_MAP_i_2,DMM memory mapping register" hexmask.long.byte 0x0 0.--7. 1. " SDRC_ADDR ,SDRAM controller address MSB for view mapping i" bitfld.long 0x0 8.--9. " SDRC_MAP ,SDRAM controller mapping for view mapping i 0x0: Unmapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be 0x3 and SDRC_INTL must be a nonzero value." "0,1,2,3" textline " " bitfld.long 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 16.--17. " SDRC_ADDRSPC ,SDRAM controller address space for view mapping i" "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " SDRC_INTL ,SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled regions, interleaving is forced to 1kiB. SDRC_INTL is don't care if SDRC_MAP is not 0x3 (no interleaving)." "0,1,2,3" bitfld.long 0x0 20.--22. " SYS_SIZE ,DMM system section size for view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" hexmask.long.byte 0x0 24.--31. 1. " SYS_ADDR ,DMM system section address MSB for view mapping i" group.byte 0x4C++0x3 line.long 0x0 "DMM_LISA_MAP_i_3,DMM memory mapping register" hexmask.long.byte 0x0 0.--7. 1. " SDRC_ADDR ,SDRAM controller address MSB for view mapping i" bitfld.long 0x0 8.--9. " SDRC_MAP ,SDRAM controller mapping for view mapping i 0x0: Unmapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be 0x3 and SDRC_INTL must be a nonzero value." "0,1,2,3" textline " " bitfld.long 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 16.--17. " SDRC_ADDRSPC ,SDRAM controller address space for view mapping i" "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " SDRC_INTL ,SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled regions, interleaving is forced to 1kiB. SDRC_INTL is don't care if SDRC_MAP is not 0x3 (no interleaving)." "0,1,2,3" bitfld.long 0x0 20.--22. " SYS_SIZE ,DMM system section size for view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" hexmask.long.byte 0x0 24.--31. 1. " SYS_ADDR ,DMM system section address MSB for view mapping i" group.byte 0x208++0x3 line.long 0x0 "DMM_TILER_HWINFO,DMM hardware configuration for TILER" hexmask.long.byte 0x0 0.--6. 1. " OR_CNT ,Number of TILER orientation entries" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "DMM_TILER_OR0,DMM TILER orientation (initiators 0 to 7)" bitfld.long 0x0 0.--2. " OR0 ,Orientation for initiator 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W0 ,Write-enable for OR0 bit field" "0,1" textline " " bitfld.long 0x0 4.--6. " OR1 ,Orientation for initiator 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " W1 ,Write-enable for OR1 bit field" "0,1" textline " " bitfld.long 0x0 8.--10. " OR2 ,Orientation for initiator 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " W2 ,Write-enable for OR2 bit field" "0,1" textline " " bitfld.long 0x0 12.--14. " OR3 ,Orientation for initiator 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " W3 ,Write-enable for OR3 bit field" "0,1" textline " " bitfld.long 0x0 16.--18. " OR4 ,Orientation for initiator 4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " W4 ,Write-enable for OR4 bit field" "0,1" textline " " bitfld.long 0x0 20.--22. " OR5 ,Orientation for initiator 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " W5 ,Write-enable for OR5 bit field" "0,1" textline " " bitfld.long 0x0 24.--26. " OR6 ,Orientation for initiator 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " W6 ,Write-enable for OR6 bit field" "0,1" textline " " bitfld.long 0x0 28.--30. " OR7 ,Orientation for initiator 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " W7 ,Write-enable for OR7 bit field" "0,1" group.byte 0x224++0x3 line.long 0x0 "DMM_TILER_OR1,DMM TILER orientation (initiators 8 to 15)" bitfld.long 0x0 0.--2. " OR8 ,Orientation for initiator 8" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W8 ,Write-enable for OR8 bit field" "0,1" textline " " bitfld.long 0x0 4.--6. " OR9 ,Orientation for initiator 9" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " W9 ,Write-enable for OR9 bit field" "0,1" textline " " bitfld.long 0x0 8.--10. " OR10 ,Orientation for initiator 10" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " W10 ,Write-enable for OR10 bit field" "0,1" textline " " bitfld.long 0x0 12.--14. " OR11 ,Orientation for initiator 11" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " W11 ,Write-enable for OR11 bit field" "0,1" textline " " bitfld.long 0x0 16.--18. " OR12 ,Orientation for initiator 12" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " W12 ,Write-enable for OR12 bit field" "0,1" textline " " bitfld.long 0x0 20.--22. " OR13 ,Orientation for initiator 13" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " W13 ,Write-enable for OR13 bit field" "0,1" textline " " bitfld.long 0x0 24.--26. " OR14 ,Orientation for initiator 14" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " W14 ,Write-enable for OR14 bit field" "0,1" textline " " bitfld.long 0x0 28.--30. " OR15 ,Orientation for initiator 15" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " W15 ,Write-enable for OR15 bit field" "0,1" group.byte 0x408++0x3 line.long 0x0 "DMM_PAT_HWINFO,DMM hardware configuration for PAT" hexmask.long.byte 0x0 0.--6. 1. " VIEW_CNT ,Number of PAT view entries" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--11. " VIEW_MAP_CNT ,Number of internal PAT view mappings." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " LUT_CNT ,Number of PAT LUT for page-grained physical address translation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " ENGINE_CNT ,Number of PAT refill engines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x40C++0x3 line.long 0x0 "DMM_PAT_GEOMETRY,PAT geometry-related settings" bitfld.long 0x0 0.--4. " PAGE_SZ ,Page size in 4-kiB granularity" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " ADDR_RANGE ,PAT output physical address range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16.--19. " CONT_WDTH ,Container width in pages" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--26. " CONT_HGHT ,Container height in pages" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x410++0x3 line.long 0x0 "DMM_PAT_CONFIG,This is the PAT configuration register aimed at defining the major PAT configuration of each refill engine." bitfld.long 0x0 0. " MODE0 ,Mode of refill engine 0" "0,1" bitfld.long 0x0 1. " MODE1 ,Mode of refill engine 1" "0,1" textline " " bitfld.long 0x0 2. " MODE2 ,Mode of refill engine 2" "0,1" bitfld.long 0x0 3. " MODE3 ,Mode of refill engine 3" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x420++0x3 line.long 0x0 "DMM_PAT_VIEW0,DMM PAT View register (initiators 0 to 7)" bitfld.long 0x0 0.--1. " V0 ,PAT view for initiator 0" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 3. " W0 ,Write-enable for V0 bit field" "0,1" bitfld.long 0x0 4.--5. " V1 ,PAT view for initiator 1" "0,1,2,3" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " W1 ,Write-enable for V1 bit field" "0,1" textline " " bitfld.long 0x0 8.--9. " V2 ,PAT view for initiator 2" "0,1,2,3" bitfld.long 0x0 10. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 11. " W2 ,Write-enable for V2 bit field" "0,1" bitfld.long 0x0 12.--13. " V3 ,PAT view for initiator 3" "0,1,2,3" textline " " bitfld.long 0x0 14. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 15. " W3 ,Write-enable for V3 bit field" "0,1" textline " " bitfld.long 0x0 16.--17. " V4 ,PAT view for initiator 4" "0,1,2,3" bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 19. " W4 ,Write-enable for V4 bit field" "0,1" bitfld.long 0x0 20.--21. " V5 ,PAT view for initiator 5" "0,1,2,3" textline " " bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 23. " W5 ,Write-enable for V5 bit field" "0,1" textline " " bitfld.long 0x0 24.--25. " V6 ,PAT view for initiator 6" "0,1,2,3" bitfld.long 0x0 26. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 27. " W6 ,Write-enable for V6 bit field" "0,1" bitfld.long 0x0 28.--29. " V7 ,PAT view for initiator 7" "0,1,2,3" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " W7 ,Write-enable for V7 bit field" "0,1" group.byte 0x424++0x3 line.long 0x0 "DMM_PAT_VIEW1,DMM PAT view register (initiators 8 to 15)" bitfld.long 0x0 0.--1. " V8 ,PAT view for initiator 8" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 3. " W8 ,Write-enable for V8 bit field" "0,1" bitfld.long 0x0 4.--5. " V9 ,PAT view for initiator 9" "0,1,2,3" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " W9 ,Write-enable for V9 bit field" "0,1" textline " " bitfld.long 0x0 8.--9. " V10 ,PAT view for initiator 10" "0,1,2,3" bitfld.long 0x0 10. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 11. " W10 ,Write-enable for V10 bit field" "0,1" bitfld.long 0x0 12.--13. " V11 ,PAT view for initiator 11" "0,1,2,3" textline " " bitfld.long 0x0 14. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 15. " W11 ,Write-enable for V11 bit field" "0,1" textline " " bitfld.long 0x0 16.--17. " V12 ,PAT view for initiator 12" "0,1,2,3" bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 19. " W12 ,Write-enable for V12 bit field" "0,1" bitfld.long 0x0 20.--21. " V13 ,PAT view for initiator 13" "0,1,2,3" textline " " bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 23. " W13 ,Write-enable for V13 bit field" "0,1" textline " " bitfld.long 0x0 24.--25. " V14 ,PAT view for initiator 14" "0,1,2,3" bitfld.long 0x0 26. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 27. " W14 ,Write-enable for V14 bit field" "0,1" bitfld.long 0x0 28.--29. " V15 ,PAT view for initiator 15" "0,1,2,3" textline " " bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 31. " W15 ,Write-enable for V15 bit field" "0,1" group.byte 0x440++0x3 line.long 0x0 "DMM_PAT_VIEW_MAP_i_0,PAT view mapping register" bitfld.long 0x0 0.--2. " CONT_8 ,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--6. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 7. " ACCESS_8 ,Kind of access for this 8-bit mode container in view mapping i" "0,1" bitfld.long 0x0 8.--10. " CONT_16 ,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--14. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 15. " ACCESS_16 ,Kind of access for this 16-bit mode container in view mapping i" "0,1" textline " " bitfld.long 0x0 16.--18. " CONT_32 ,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19.--22. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 23. " ACCESS_32 ,Kind of access for this 32-bit mode container in view mapping i" "0,1" bitfld.long 0x0 24.--26. " CONT_PAGE ,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 31. " ACCESS_PAGE ,Kind of access for this page mode container in view mapping i" "0,1" group.byte 0x444++0x3 line.long 0x0 "DMM_PAT_VIEW_MAP_i_1,PAT view mapping register" bitfld.long 0x0 0.--2. " CONT_8 ,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--6. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 7. " ACCESS_8 ,Kind of access for this 8-bit mode container in view mapping i" "0,1" bitfld.long 0x0 8.--10. " CONT_16 ,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--14. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 15. " ACCESS_16 ,Kind of access for this 16-bit mode container in view mapping i" "0,1" textline " " bitfld.long 0x0 16.--18. " CONT_32 ,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19.--22. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 23. " ACCESS_32 ,Kind of access for this 32-bit mode container in view mapping i" "0,1" bitfld.long 0x0 24.--26. " CONT_PAGE ,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 31. " ACCESS_PAGE ,Kind of access for this page mode container in view mapping i" "0,1" group.byte 0x448++0x3 line.long 0x0 "DMM_PAT_VIEW_MAP_i_2,PAT view mapping register" bitfld.long 0x0 0.--2. " CONT_8 ,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--6. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 7. " ACCESS_8 ,Kind of access for this 8-bit mode container in view mapping i" "0,1" bitfld.long 0x0 8.--10. " CONT_16 ,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--14. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 15. " ACCESS_16 ,Kind of access for this 16-bit mode container in view mapping i" "0,1" textline " " bitfld.long 0x0 16.--18. " CONT_32 ,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19.--22. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 23. " ACCESS_32 ,Kind of access for this 32-bit mode container in view mapping i" "0,1" bitfld.long 0x0 24.--26. " CONT_PAGE ,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 31. " ACCESS_PAGE ,Kind of access for this page mode container in view mapping i" "0,1" group.byte 0x44C++0x3 line.long 0x0 "DMM_PAT_VIEW_MAP_i_3,PAT view mapping register" bitfld.long 0x0 0.--2. " CONT_8 ,Container for 8-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--6. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 7. " ACCESS_8 ,Kind of access for this 8-bit mode container in view mapping i" "0,1" bitfld.long 0x0 8.--10. " CONT_16 ,Container for 16-bit mode in view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--14. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 15. " ACCESS_16 ,Kind of access for this 16-bit mode container in view mapping i" "0,1" textline " " bitfld.long 0x0 16.--18. " CONT_32 ,Container for 32-bit mode in view mapping i" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19.--22. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 23. " ACCESS_32 ,Kind of access for this 32-bit mode container in view mapping i" "0,1" bitfld.long 0x0 24.--26. " CONT_PAGE ,Container for page mode in view mapping i" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 31. " ACCESS_PAGE ,Kind of access for this page mode container in view mapping i" "0,1" group.byte 0x460++0x3 line.long 0x0 "DMM_PAT_VIEW_MAP_BASE,Base address of all view mappings" hexmask.long 0x0 0.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " BASE_ADDR ,MSB of the PAT view mapping base address" "0,1" group.byte 0x478++0x3 line.long 0x0 "DMM_PAT_IRQ_EOI,PAT end of interrupt" bitfld.long 0x0 0. " EOI ,End of PAT interrupt" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x480++0x3 line.long 0x0 "DMM_PAT_IRQSTATUS_RAW,Per-event raw interrupt status vector. Raw status is set even if the related event is not enabled. Write 1 to set the (raw) status, mostly for debug. n = 0 for the first interrupt status raw register, n = 1 for the second interrupt status raw register." bitfld.long 0x0 0. " FILL_DSC0 ,End of refill event for any descriptor in area 4.n" "0,1" bitfld.long 0x0 1. " FILL_LST0 ,End of refill event for the last descriptor in area 4.n" "0,1" textline " " bitfld.long 0x0 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 4.n" "0,1" bitfld.long 0x0 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 4.n" "0,1" textline " " bitfld.long 0x0 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 4.n" "0,1" bitfld.long 0x0 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 4.n" "0,1" textline " " bitfld.long 0x0 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 4.n" "0,1" bitfld.long 0x0 7. " ERR_LUT_MISS0 ,Access to a yet-to-be-refilled area event in area 4.n" "0,1" textline " " bitfld.long 0x0 8. " FILL_DSC1 ,End of refill event for any descriptor in area 4.n+1" "0,1" bitfld.long 0x0 9. " FILL_LST1 ,End of refill event for the last descriptor in area 4.n+1" "0,1" textline " " bitfld.long 0x0 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 4.n+1" "0,1" bitfld.long 0x0 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 4.n+1" "0,1" textline " " bitfld.long 0x0 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 4.n+1" "0,1" bitfld.long 0x0 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 4.n+1" "0,1" textline " " bitfld.long 0x0 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 4.n+1" "0,1" bitfld.long 0x0 15. " ERR_LUT_MISS1 ,Access to a yet-to-be-refilled area event in area 4.n+1" "0,1" textline " " bitfld.long 0x0 16. " FILL_DSC2 ,End of refill event for any descriptor in area 4.n+2" "0,1" bitfld.long 0x0 17. " FILL_LST2 ,End of refill event for the last descriptor in area 4.n+2" "0,1" textline " " bitfld.long 0x0 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 4.n+2" "0,1" bitfld.long 0x0 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 4.n+2" "0,1" textline " " bitfld.long 0x0 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 4.n+2" "0,1" bitfld.long 0x0 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 4.n+2" "0,1" textline " " bitfld.long 0x0 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 4.n+2" "0,1" bitfld.long 0x0 23. " ERR_LUT_MISS2 ,Access to a yet-to-be-refilled area event in area 4.n+2" "0,1" textline " " bitfld.long 0x0 24. " FILL_DSC3 ,End of refill event for any descriptor in area 4.n+3" "0,1" bitfld.long 0x0 25. " FILL_LST3 ,End of refill event for the last descriptor in area 4.n+3" "0,1" textline " " bitfld.long 0x0 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 4.n+3" "0,1" bitfld.long 0x0 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 4.n+3" "0,1" textline " " bitfld.long 0x0 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 4.n+3" "0,1" bitfld.long 0x0 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 4.n+3" "0,1" textline " " bitfld.long 0x0 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 4.n+3" "0,1" bitfld.long 0x0 31. " ERR_LUT_MISS3 ,Access to a yet-to-be-refilled area event in area 4.n+3" "0,1" group.byte 0x490++0x3 line.long 0x0 "DMM_PAT_IRQSTATUS,Per-event 'enabled' interrupt status vector. Enabled status is not set unless the event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). n = 0 for the first interrupt status register, n = 1 for the second interrupt status register." bitfld.long 0x0 0. " FILL_DSC0 ,End of refill event for any descriptor in area 4.n" "0,1" bitfld.long 0x0 1. " FILL_LST0 ,End of refill event for the last descriptor in area 4.n" "0,1" textline " " bitfld.long 0x0 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 4.n" "0,1" bitfld.long 0x0 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 4.n" "0,1" textline " " bitfld.long 0x0 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 4.n" "0,1" bitfld.long 0x0 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 4.n" "0,1" textline " " bitfld.long 0x0 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 4.n" "0,1" bitfld.long 0x0 7. " ERR_LUT_MISS0 ,Access to a yet-to-be-refilled area event in area 4.n" "0,1" textline " " bitfld.long 0x0 8. " FILL_DSC1 ,End of refill event for any descriptor in area 4.n+1" "0,1" bitfld.long 0x0 9. " FILL_LST1 ,End of refill event for the last descriptor in area 4.n+1" "0,1" textline " " bitfld.long 0x0 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 4.n+1" "0,1" bitfld.long 0x0 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 4.n+1" "0,1" textline " " bitfld.long 0x0 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 4.n+1" "0,1" bitfld.long 0x0 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 4.n+1" "0,1" textline " " bitfld.long 0x0 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 4.n+1" "0,1" bitfld.long 0x0 15. " ERR_LUT_MISS1 ,Access to a yet-to-be-refilled area event in area 4.n+1" "0,1" textline " " bitfld.long 0x0 16. " FILL_DSC2 ,End of refill event for any descriptor in area 4.n+2" "0,1" bitfld.long 0x0 17. " FILL_LST2 ,End of refill event for the last descriptor in area 4.n+2" "0,1" textline " " bitfld.long 0x0 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 4.n+2" "0,1" bitfld.long 0x0 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 4.n+2" "0,1" textline " " bitfld.long 0x0 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 4.n+2" "0,1" bitfld.long 0x0 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 4.n+2" "0,1" textline " " bitfld.long 0x0 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "0,1" bitfld.long 0x0 23. " ERR_LUT_MISS2 ,Access to a yet-to-be-refilled area event in area 4.n+2" "0,1" textline " " bitfld.long 0x0 24. " FILL_DSC3 ,End of refill event for any descriptor in area 4.n+3" "0,1" bitfld.long 0x0 25. " FILL_LST3 ,End of refill event for the last descriptor in area 4.n+3" "0,1" textline " " bitfld.long 0x0 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 4.n+3" "0,1" bitfld.long 0x0 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 4.n+3" "0,1" textline " " bitfld.long 0x0 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 4.n+3" "0,1" bitfld.long 0x0 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 4.n+3" "0,1" textline " " bitfld.long 0x0 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 4.n+3" "0,1" bitfld.long 0x0 31. " ERR_LUT_MISS3 ,Access to a yet-to-be-refilled area event in area 4.n+3" "0,1" group.byte 0x4A0++0x3 line.long 0x0 "DMM_PAT_IRQENABLE_SET,Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. n = 0 for the first interrupt enable set register, n = 1 for the second interrupt enable set register." bitfld.long 0x0 0. " FILL_DSC0 ,End of refill interrupt source mask for any descriptior in area 4.n" "0,1" bitfld.long 0x0 1. " FILL_LST0 ,End of refill interrupt source mask for the last descriptior in area 4.n" "0,1" textline " " bitfld.long 0x0 2. " ERR_INV_DSC0 ,Invalid descriptor pointer interrupt source mask for area 4.n" "0,1" bitfld.long 0x0 3. " ERR_INV_DATA0 ,Invalid entry-table pointer interrupt source mask for area 4.n" "0,1" textline " " bitfld.long 0x0 4. " ERR_UPD_AREA0 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n" "0,1" bitfld.long 0x0 5. " ERR_UPD_CTRL0 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n" "0,1" textline " " bitfld.long 0x0 6. " ERR_UPD_DATA0 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n" "0,1" bitfld.long 0x0 7. " ERR_LUT_MISS0 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n" "0,1" textline " " bitfld.long 0x0 8. " FILL_DSC1 ,End of refill interrupt source mask for any descriptior in area 4.n+1" "0,1" bitfld.long 0x0 9. " FILL_LST1 ,End of refill interrupt source mask for the last descriptior in area 4.n+1" "0,1" textline " " bitfld.long 0x0 10. " ERR_INV_DSC1 ,Invalid descriptor pointer interrupt source mask for area 4.n+1" "0,1" bitfld.long 0x0 11. " ERR_INV_DATA1 ,Invalid entry-table pointer interrupt source mask for area 4.n+1" "0,1" textline " " bitfld.long 0x0 12. " ERR_UPD_AREA1 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n+1" "0,1" bitfld.long 0x0 13. " ERR_UPD_CTRL1 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n+1" "0,1" textline " " bitfld.long 0x0 14. " ERR_UPD_DATA1 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n+1" "0,1" bitfld.long 0x0 15. " ERR_LUT_MISS1 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n+1" "0,1" textline " " bitfld.long 0x0 16. " FILL_DSC2 ,End of refill interrupt source mask for any descriptior in area 4.n+2" "0,1" bitfld.long 0x0 17. " FILL_LST2 ,End of refill interrupt source mask for the last descriptior in area 4.n+2" "0,1" textline " " bitfld.long 0x0 18. " ERR_INV_DSC2 ,Invalid descriptor pointer interrupt source mask for area 4.n+2" "0,1" bitfld.long 0x0 19. " ERR_INV_DATA2 ,Invalid entry-table pointer interrupt source mask for area 4.n+2" "0,1" textline " " bitfld.long 0x0 20. " ERR_UPD_AREA2 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n+2" "0,1" bitfld.long 0x0 21. " ERR_UPD_CTRL2 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n+2" "0,1" textline " " bitfld.long 0x0 22. " ERR_UPD_DATA2 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n+2" "0,1" bitfld.long 0x0 23. " ERR_LUT_MISS2 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n+2" "0,1" textline " " bitfld.long 0x0 24. " FILL_DSC3 ,End of refill interrupt source mask for any descriptior in area 4.n+3" "0,1" bitfld.long 0x0 25. " FILL_LST3 ,End of refill interrupt source mask for the last descriptior in area 4.n+3" "0,1" textline " " bitfld.long 0x0 26. " ERR_INV_DSC3 ,Invalid descriptor pointer interrupt source mask for area 4.n+3" "0,1" bitfld.long 0x0 27. " ERR_INV_DATA3 ,Invalid entry-table pointer interrupt source mask for area 4.n+3" "0,1" textline " " bitfld.long 0x0 28. " ERR_UPD_AREA3 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n+3" "0,1" bitfld.long 0x0 29. " ERR_UPD_CTRL3 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n+3" "0,1" textline " " bitfld.long 0x0 30. " ERR_UPD_DATA3 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n+3" "0,1" bitfld.long 0x0 31. " ERR_LUT_MISS3 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n+3" "0,1" group.byte 0x4B0++0x3 line.long 0x0 "DMM_PAT_IRQENABLE_CLR,Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. n = 0 for the first interrupt enable clear register, n = 1 for the second interrupt enable clear register." bitfld.long 0x0 0. " FILL_DSC0 ,End of refill interrupt source mask for any descriptior in area 4.n" "0,1" bitfld.long 0x0 1. " FILL_LST0 ,End of refill interrupt source mask for the last descriptior in area 4.n" "0,1" textline " " bitfld.long 0x0 2. " ERR_INV_DSC0 ,Invalid descriptor pointer interrupt source mask for area 4.n" "0,1" bitfld.long 0x0 3. " ERR_INV_DATA0 ,Invalid entry-table pointer interrupt source mask for area 4.n" "0,1" textline " " bitfld.long 0x0 4. " ERR_UPD_AREA0 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n" "0,1" bitfld.long 0x0 5. " ERR_UPD_CTRL0 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n" "0,1" textline " " bitfld.long 0x0 6. " ERR_UPD_DATA0 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n" "0,1" bitfld.long 0x0 7. " ERR_LUT_MISS0 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n" "0,1" textline " " bitfld.long 0x0 8. " FILL_DSC1 ,End of refill interrupt source mask for any descriptior in area 4.n+1" "0,1" bitfld.long 0x0 9. " FILL_LST1 ,End of refill interrupt source mask for the last descriptior in area 4.n+1" "0,1" textline " " bitfld.long 0x0 10. " ERR_INV_DSC1 ,Invalid descriptor pointer interrupt source mask for area 4.n+1" "0,1" bitfld.long 0x0 11. " ERR_INV_DATA1 ,Invalid entry-table pointer interrupt source mask for area 4.n+1" "0,1" textline " " bitfld.long 0x0 12. " ERR_UPD_AREA1 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n+1" "0,1" bitfld.long 0x0 13. " ERR_UPD_CTRL1 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n+1" "0,1" textline " " bitfld.long 0x0 14. " ERR_UPD_DATA1 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n+1" "0,1" bitfld.long 0x0 15. " ERR_LUT_MISS1 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n+1" "0,1" textline " " bitfld.long 0x0 16. " FILL_DSC2 ,End of refill interrupt source mask for any descriptior in area 4.n+2" "0,1" bitfld.long 0x0 17. " FILL_LST2 ,End of refill interrupt source mask for the last descriptior in area 4.n+2" "0,1" textline " " bitfld.long 0x0 18. " ERR_INV_DSC2 ,Invalid descriptor pointer interrupt source mask for area 4.n+2" "0,1" bitfld.long 0x0 19. " ERR_INV_DATA2 ,Invalid entry-table pointer interrupt source mask for area 4.n+2" "0,1" textline " " bitfld.long 0x0 20. " ERR_UPD_AREA2 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n+2" "0,1" bitfld.long 0x0 21. " ERR_UPD_CTRL2 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n+2" "0,1" textline " " bitfld.long 0x0 22. " ERR_UPD_DATA2 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n+2" "0,1" bitfld.long 0x0 23. " ERR_LUT_MISS2 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n+2" "0,1" textline " " bitfld.long 0x0 24. " FILL_DSC3 ,End of refill interrupt source mask for any descriptior in area 4.n+3" "0,1" bitfld.long 0x0 25. " FILL_LST3 ,End of refill interrupt source mask for the last descriptior in area 4.n+3" "0,1" textline " " bitfld.long 0x0 26. " ERR_INV_DSC3 ,Invalid descriptor pointer interrupt source mask for area 4.n+3" "0,1" bitfld.long 0x0 27. " ERR_INV_DATA3 ,Invalid entry-table pointer interrupt source mask for area 4.n+3" "0,1" textline " " bitfld.long 0x0 28. " ERR_UPD_AREA3 ,Unexpected area register update whilst refilling interrupt source mask for area 4.n+3" "0,1" bitfld.long 0x0 29. " ERR_UPD_CTRL3 ,Unexpected control register update whilst refilling interrupt source mask for area 4.n+3" "0,1" textline " " bitfld.long 0x0 30. " ERR_UPD_DATA3 ,Unexpected data register update whilst refilling interrupt source mask for area 4.n+3" "0,1" bitfld.long 0x0 31. " ERR_LUT_MISS3 ,Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n+3" "0,1" group.byte 0x4C0++0x3 line.long 0x0 "DMM_PAT_STATUS_i_0,Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register." bitfld.long 0x0 0. " READY ,Area registers ready for engine n" "0,1" bitfld.long 0x0 1. " VALID ,Valid area description for engine n" "0,1" textline " " bitfld.long 0x0 2. " RUN ,Area currently reloading for engine n" "0,1" bitfld.long 0x0 3. " DONE ,Area reloading finished for engine n" "0,1" textline " " bitfld.long 0x0 4. " LINKED ,Area reconfiguration link asserted for engine n" "0,1" bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 7. " BYPASSED ,Engine n is bypassed. Direct access to the LUT is provided." "0,1" bitfld.long 0x0 8.--9. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 10.--15. " ERROR ,Error happened in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 16.--24. 1. " CNT ,Counter of remaining lines to reload for engine n" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x4C4++0x3 line.long 0x0 "DMM_PAT_STATUS_i_1,Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register." bitfld.long 0x0 0. " READY ,Area registers ready for engine n" "0,1" bitfld.long 0x0 1. " VALID ,Valid area description for engine n" "0,1" textline " " bitfld.long 0x0 2. " RUN ,Area currently reloading for engine n" "0,1" bitfld.long 0x0 3. " DONE ,Area reloading finished for engine n" "0,1" textline " " bitfld.long 0x0 4. " LINKED ,Area reconfiguration link asserted for engine n" "0,1" bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 7. " BYPASSED ,Engine n is bypassed. Direct access to the LUT is provided." "0,1" bitfld.long 0x0 8.--9. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 10.--15. " ERROR ,Error happened in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 16.--24. 1. " CNT ,Counter of remaining lines to reload for engine n" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x4C8++0x3 line.long 0x0 "DMM_PAT_STATUS_i_2,Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register." bitfld.long 0x0 0. " READY ,Area registers ready for engine n" "0,1" bitfld.long 0x0 1. " VALID ,Valid area description for engine n" "0,1" textline " " bitfld.long 0x0 2. " RUN ,Area currently reloading for engine n" "0,1" bitfld.long 0x0 3. " DONE ,Area reloading finished for engine n" "0,1" textline " " bitfld.long 0x0 4. " LINKED ,Area reconfiguration link asserted for engine n" "0,1" bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 7. " BYPASSED ,Engine n is bypassed. Direct access to the LUT is provided." "0,1" bitfld.long 0x0 8.--9. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 10.--15. " ERROR ,Error happened in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 16.--24. 1. " CNT ,Counter of remaining lines to reload for engine n" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x4CC++0x3 line.long 0x0 "DMM_PAT_STATUS_i_3,Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register." bitfld.long 0x0 0. " READY ,Area registers ready for engine n" "0,1" bitfld.long 0x0 1. " VALID ,Valid area description for engine n" "0,1" textline " " bitfld.long 0x0 2. " RUN ,Area currently reloading for engine n" "0,1" bitfld.long 0x0 3. " DONE ,Area reloading finished for engine n" "0,1" textline " " bitfld.long 0x0 4. " LINKED ,Area reconfiguration link asserted for engine n" "0,1" bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 7. " BYPASSED ,Engine n is bypassed. Direct access to the LUT is provided." "0,1" bitfld.long 0x0 8.--9. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 10.--15. " ERROR ,Error happened in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 16.--24. 1. " CNT ,Counter of remaining lines to reload for engine n" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x500++0x3 line.long 0x0 "DMM_PAT_DESCR_i_0,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine. Writing to this register aborts the current ongoing area reload and resets the corresponding, and registers." bitfld.long 0x0 0.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " ADDR ,Physical address of the next table refill descriptor of engine n" group.byte 0x510++0x3 line.long 0x0 "DMM_PAT_DESCR_i_1,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine. Writing to this register aborts the current ongoing area reload and resets the corresponding, and registers." bitfld.long 0x0 0.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " ADDR ,Physical address of the next table refill descriptor of engine n" group.byte 0x520++0x3 line.long 0x0 "DMM_PAT_DESCR_i_2,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine. Writing to this register aborts the current ongoing area reload and resets the corresponding, and registers." bitfld.long 0x0 0.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " ADDR ,Physical address of the next table refill descriptor of engine n" group.byte 0x530++0x3 line.long 0x0 "DMM_PAT_DESCR_i_3,Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine. Writing to this register aborts the current ongoing area reload and resets the corresponding, and registers." bitfld.long 0x0 0.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " ADDR ,Physical address of the next table refill descriptor of engine n" group.byte 0x504++0x3 line.long 0x0 "DMM_PAT_AREA_i_0,Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine." hexmask.long.byte 0x0 0.--7. 1. " X0 ,X-coordinate of the top-left corner of the PAT area for engine n" hexmask.long.byte 0x0 8.--15. 1. " Y0 ,Y-coordinate of the top-left corner of the PAT area for engine n" textline " " hexmask.long.byte 0x0 16.--23. 1. " X1 ,X-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x0 24.--31. 1. " Y1 ,Y-coordinate of the bottom-right corner of the PAT area for engine n" group.byte 0x514++0x3 line.long 0x0 "DMM_PAT_AREA_i_1,Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine." hexmask.long.byte 0x0 0.--7. 1. " X0 ,X-coordinate of the top-left corner of the PAT area for engine n" hexmask.long.byte 0x0 8.--15. 1. " Y0 ,Y-coordinate of the top-left corner of the PAT area for engine n" textline " " hexmask.long.byte 0x0 16.--23. 1. " X1 ,X-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x0 24.--31. 1. " Y1 ,Y-coordinate of the bottom-right corner of the PAT area for engine n" group.byte 0x524++0x3 line.long 0x0 "DMM_PAT_AREA_i_2,Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine." hexmask.long.byte 0x0 0.--7. 1. " X0 ,X-coordinate of the top-left corner of the PAT area for engine n" hexmask.long.byte 0x0 8.--15. 1. " Y0 ,Y-coordinate of the top-left corner of the PAT area for engine n" textline " " hexmask.long.byte 0x0 16.--23. 1. " X1 ,X-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x0 24.--31. 1. " Y1 ,Y-coordinate of the bottom-right corner of the PAT area for engine n" group.byte 0x534++0x3 line.long 0x0 "DMM_PAT_AREA_i_3,Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine." hexmask.long.byte 0x0 0.--7. 1. " X0 ,X-coordinate of the top-left corner of the PAT area for engine n" hexmask.long.byte 0x0 8.--15. 1. " Y0 ,Y-coordinate of the top-left corner of the PAT area for engine n" textline " " hexmask.long.byte 0x0 16.--23. 1. " X1 ,X-coordinate of the bottom-right corner of the PAT area for engine n" hexmask.long.byte 0x0 24.--31. 1. " Y1 ,Y-coordinate of the bottom-right corner of the PAT area for engine n" group.byte 0x508++0x3 line.long 0x0 "DMM_PAT_CTRL_i_0,DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine." bitfld.long 0x0 0. " START ,Starting a PAT table refill with engine n" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " DIRECTION ,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 7.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " SYNC ,DMM PAT table reload synchronization for engine n" "0,1" hexmask.long.word 0x0 17.--27. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 28.--31. " INITIATOR ,DMM PAT initiator for synchronization in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x518++0x3 line.long 0x0 "DMM_PAT_CTRL_i_1,DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine." bitfld.long 0x0 0. " START ,Starting a PAT table refill with engine n" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " DIRECTION ,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 7.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " SYNC ,DMM PAT table reload synchronization for engine n" "0,1" hexmask.long.word 0x0 17.--27. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 28.--31. " INITIATOR ,DMM PAT initiator for synchronization in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x528++0x3 line.long 0x0 "DMM_PAT_CTRL_i_2,DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine." bitfld.long 0x0 0. " START ,Starting a PAT table refill with engine n" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " DIRECTION ,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 7.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " SYNC ,DMM PAT table reload synchronization for engine n" "0,1" hexmask.long.word 0x0 17.--27. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 28.--31. " INITIATOR ,DMM PAT initiator for synchronization in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x538++0x3 line.long 0x0 "DMM_PAT_CTRL_i_3,DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine." bitfld.long 0x0 0. " START ,Starting a PAT table refill with engine n" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " DIRECTION ,Direction of this PAT table refill for engine n" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 7.--15. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 16. " SYNC ,DMM PAT table reload synchronization for engine n" "0,1" hexmask.long.word 0x0 17.--27. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 28.--31. " INITIATOR ,DMM PAT initiator for synchronization in engine n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50C++0x3 line.long 0x0 "DMM_PAT_DATA_i_0,Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine." bitfld.long 0x0 0.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.byte 0x51C++0x3 line.long 0x0 "DMM_PAT_DATA_i_1,Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine." bitfld.long 0x0 0.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.byte 0x52C++0x3 line.long 0x0 "DMM_PAT_DATA_i_2,Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine." bitfld.long 0x0 0.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.byte 0x53C++0x3 line.long 0x0 "DMM_PAT_DATA_i_3,Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine." bitfld.long 0x0 0.--3. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n" group.byte 0x608++0x3 line.long 0x0 "DMM_PEG_HWINFO,DMM hardware configuration for PEG" hexmask.long.byte 0x0 0.--6. 1. " PRIO_CNT ,Number of PEG priority entries" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "DMM_PEG_PRIO_k_0,DMM PEG Priority register" bitfld.long 0x0 0.--2. " P0 ,Priority for initiator ConnID = 8 W k" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W0 ,Write-enable for P0 bit field" "0,1" textline " " bitfld.long 0x0 4.--6. " P1 ,Priority for initiator ConnID = 8 W k + 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " W1 ,Write-enable for P1 bit field" "0,1" textline " " bitfld.long 0x0 8.--10. " P2 ,Priority for initiator ConnID = 8 W k + 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " W2 ,Write-enable for P2 bit field" "0,1" textline " " bitfld.long 0x0 12.--14. " P3 ,Priority for initiator ConnID = 8 W k + 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " W3 ,Write-enable for P3 bit field" "0,1" textline " " bitfld.long 0x0 16.--18. " P4 ,Priority for initiator ConnID = 8 W k + 4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " W4 ,Write-enable for P4 bit field" "0,1" textline " " bitfld.long 0x0 20.--22. " P5 ,Priority for initiator ConnID = 8 W k + 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " W5 ,Write-enable for P5 bit field" "0,1" textline " " bitfld.long 0x0 24.--26. " P6 ,Priority for initiator ConnID = 8 W k + 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " W6 ,Write-enable for P6 bit field" "0,1" textline " " bitfld.long 0x0 28.--30. " P7 ,Priority for initiator ConnID = 8 W k + 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " W7 ,Write-enable for P7 bit field" "0,1" group.byte 0x624++0x3 line.long 0x0 "DMM_PEG_PRIO_k_1,DMM PEG Priority register" bitfld.long 0x0 0.--2. " P0 ,Priority for initiator ConnID = 8 W k" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W0 ,Write-enable for P0 bit field" "0,1" textline " " bitfld.long 0x0 4.--6. " P1 ,Priority for initiator ConnID = 8 W k + 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " W1 ,Write-enable for P1 bit field" "0,1" textline " " bitfld.long 0x0 8.--10. " P2 ,Priority for initiator ConnID = 8 W k + 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " W2 ,Write-enable for P2 bit field" "0,1" textline " " bitfld.long 0x0 12.--14. " P3 ,Priority for initiator ConnID = 8 W k + 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " W3 ,Write-enable for P3 bit field" "0,1" textline " " bitfld.long 0x0 16.--18. " P4 ,Priority for initiator ConnID = 8 W k + 4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " W4 ,Write-enable for P4 bit field" "0,1" textline " " bitfld.long 0x0 20.--22. " P5 ,Priority for initiator ConnID = 8 W k + 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " W5 ,Write-enable for P5 bit field" "0,1" textline " " bitfld.long 0x0 24.--26. " P6 ,Priority for initiator ConnID = 8 W k + 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " W6 ,Write-enable for P6 bit field" "0,1" textline " " bitfld.long 0x0 28.--30. " P7 ,Priority for initiator ConnID = 8 W k + 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " W7 ,Write-enable for P7 bit field" "0,1" group.byte 0x628++0x3 line.long 0x0 "DMM_PEG_PRIO_k_2,DMM PEG Priority register" bitfld.long 0x0 0.--2. " P0 ,Priority for initiator ConnID = 8 W k" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W0 ,Write-enable for P0 bit field" "0,1" textline " " bitfld.long 0x0 4.--6. " P1 ,Priority for initiator ConnID = 8 W k + 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " W1 ,Write-enable for P1 bit field" "0,1" textline " " bitfld.long 0x0 8.--10. " P2 ,Priority for initiator ConnID = 8 W k + 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " W2 ,Write-enable for P2 bit field" "0,1" textline " " bitfld.long 0x0 12.--14. " P3 ,Priority for initiator ConnID = 8 W k + 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " W3 ,Write-enable for P3 bit field" "0,1" textline " " bitfld.long 0x0 16.--18. " P4 ,Priority for initiator ConnID = 8 W k + 4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " W4 ,Write-enable for P4 bit field" "0,1" textline " " bitfld.long 0x0 20.--22. " P5 ,Priority for initiator ConnID = 8 W k + 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " W5 ,Write-enable for P5 bit field" "0,1" textline " " bitfld.long 0x0 24.--26. " P6 ,Priority for initiator ConnID = 8 W k + 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " W6 ,Write-enable for P6 bit field" "0,1" textline " " bitfld.long 0x0 28.--30. " P7 ,Priority for initiator ConnID = 8 W k + 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " W7 ,Write-enable for P7 bit field" "0,1" group.byte 0x62C++0x3 line.long 0x0 "DMM_PEG_PRIO_k_3,DMM PEG Priority register" bitfld.long 0x0 0.--2. " P0 ,Priority for initiator ConnID = 8 W k" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W0 ,Write-enable for P0 bit field" "0,1" textline " " bitfld.long 0x0 4.--6. " P1 ,Priority for initiator ConnID = 8 W k + 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " W1 ,Write-enable for P1 bit field" "0,1" textline " " bitfld.long 0x0 8.--10. " P2 ,Priority for initiator ConnID = 8 W k + 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " W2 ,Write-enable for P2 bit field" "0,1" textline " " bitfld.long 0x0 12.--14. " P3 ,Priority for initiator ConnID = 8 W k + 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " W3 ,Write-enable for P3 bit field" "0,1" textline " " bitfld.long 0x0 16.--18. " P4 ,Priority for initiator ConnID = 8 W k + 4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " W4 ,Write-enable for P4 bit field" "0,1" textline " " bitfld.long 0x0 20.--22. " P5 ,Priority for initiator ConnID = 8 W k + 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " W5 ,Write-enable for P5 bit field" "0,1" textline " " bitfld.long 0x0 24.--26. " P6 ,Priority for initiator ConnID = 8 W k + 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " W6 ,Write-enable for P6 bit field" "0,1" textline " " bitfld.long 0x0 28.--30. " P7 ,Priority for initiator ConnID = 8 W k + 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " W7 ,Write-enable for P7 bit field" "0,1" group.byte 0x630++0x3 line.long 0x0 "DMM_PEG_PRIO_k_4,DMM PEG Priority register" bitfld.long 0x0 0.--2. " P0 ,Priority for initiator ConnID = 8 W k" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W0 ,Write-enable for P0 bit field" "0,1" textline " " bitfld.long 0x0 4.--6. " P1 ,Priority for initiator ConnID = 8 W k + 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " W1 ,Write-enable for P1 bit field" "0,1" textline " " bitfld.long 0x0 8.--10. " P2 ,Priority for initiator ConnID = 8 W k + 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " W2 ,Write-enable for P2 bit field" "0,1" textline " " bitfld.long 0x0 12.--14. " P3 ,Priority for initiator ConnID = 8 W k + 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " W3 ,Write-enable for P3 bit field" "0,1" textline " " bitfld.long 0x0 16.--18. " P4 ,Priority for initiator ConnID = 8 W k + 4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " W4 ,Write-enable for P4 bit field" "0,1" textline " " bitfld.long 0x0 20.--22. " P5 ,Priority for initiator ConnID = 8 W k + 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " W5 ,Write-enable for P5 bit field" "0,1" textline " " bitfld.long 0x0 24.--26. " P6 ,Priority for initiator ConnID = 8 W k + 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " W6 ,Write-enable for P6 bit field" "0,1" textline " " bitfld.long 0x0 28.--30. " P7 ,Priority for initiator ConnID = 8 W k + 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " W7 ,Write-enable for P7 bit field" "0,1" group.byte 0x634++0x3 line.long 0x0 "DMM_PEG_PRIO_k_5,DMM PEG Priority register" bitfld.long 0x0 0.--2. " P0 ,Priority for initiator ConnID = 8 W k" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W0 ,Write-enable for P0 bit field" "0,1" textline " " bitfld.long 0x0 4.--6. " P1 ,Priority for initiator ConnID = 8 W k + 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " W1 ,Write-enable for P1 bit field" "0,1" textline " " bitfld.long 0x0 8.--10. " P2 ,Priority for initiator ConnID = 8 W k + 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " W2 ,Write-enable for P2 bit field" "0,1" textline " " bitfld.long 0x0 12.--14. " P3 ,Priority for initiator ConnID = 8 W k + 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " W3 ,Write-enable for P3 bit field" "0,1" textline " " bitfld.long 0x0 16.--18. " P4 ,Priority for initiator ConnID = 8 W k + 4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " W4 ,Write-enable for P4 bit field" "0,1" textline " " bitfld.long 0x0 20.--22. " P5 ,Priority for initiator ConnID = 8 W k + 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " W5 ,Write-enable for P5 bit field" "0,1" textline " " bitfld.long 0x0 24.--26. " P6 ,Priority for initiator ConnID = 8 W k + 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " W6 ,Write-enable for P6 bit field" "0,1" textline " " bitfld.long 0x0 28.--30. " P7 ,Priority for initiator ConnID = 8 W k + 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " W7 ,Write-enable for P7 bit field" "0,1" group.byte 0x638++0x3 line.long 0x0 "DMM_PEG_PRIO_k_6,DMM PEG Priority register" bitfld.long 0x0 0.--2. " P0 ,Priority for initiator ConnID = 8 W k" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W0 ,Write-enable for P0 bit field" "0,1" textline " " bitfld.long 0x0 4.--6. " P1 ,Priority for initiator ConnID = 8 W k + 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " W1 ,Write-enable for P1 bit field" "0,1" textline " " bitfld.long 0x0 8.--10. " P2 ,Priority for initiator ConnID = 8 W k + 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " W2 ,Write-enable for P2 bit field" "0,1" textline " " bitfld.long 0x0 12.--14. " P3 ,Priority for initiator ConnID = 8 W k + 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " W3 ,Write-enable for P3 bit field" "0,1" textline " " bitfld.long 0x0 16.--18. " P4 ,Priority for initiator ConnID = 8 W k + 4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " W4 ,Write-enable for P4 bit field" "0,1" textline " " bitfld.long 0x0 20.--22. " P5 ,Priority for initiator ConnID = 8 W k + 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " W5 ,Write-enable for P5 bit field" "0,1" textline " " bitfld.long 0x0 24.--26. " P6 ,Priority for initiator ConnID = 8 W k + 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " W6 ,Write-enable for P6 bit field" "0,1" textline " " bitfld.long 0x0 28.--30. " P7 ,Priority for initiator ConnID = 8 W k + 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " W7 ,Write-enable for P7 bit field" "0,1" group.byte 0x63C++0x3 line.long 0x0 "DMM_PEG_PRIO_k_7,DMM PEG Priority register" bitfld.long 0x0 0.--2. " P0 ,Priority for initiator ConnID = 8 W k" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W0 ,Write-enable for P0 bit field" "0,1" textline " " bitfld.long 0x0 4.--6. " P1 ,Priority for initiator ConnID = 8 W k + 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " W1 ,Write-enable for P1 bit field" "0,1" textline " " bitfld.long 0x0 8.--10. " P2 ,Priority for initiator ConnID = 8 W k + 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " W2 ,Write-enable for P2 bit field" "0,1" textline " " bitfld.long 0x0 12.--14. " P3 ,Priority for initiator ConnID = 8 W k + 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " W3 ,Write-enable for P3 bit field" "0,1" textline " " bitfld.long 0x0 16.--18. " P4 ,Priority for initiator ConnID = 8 W k + 4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " W4 ,Write-enable for P4 bit field" "0,1" textline " " bitfld.long 0x0 20.--22. " P5 ,Priority for initiator ConnID = 8 W k + 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " W5 ,Write-enable for P5 bit field" "0,1" textline " " bitfld.long 0x0 24.--26. " P6 ,Priority for initiator ConnID = 8 W k + 6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " W6 ,Write-enable for P6 bit field" "0,1" textline " " bitfld.long 0x0 28.--30. " P7 ,Priority for initiator ConnID = 8 W k + 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " W7 ,Write-enable for P7 bit field" "0,1" group.byte 0x640++0x3 line.long 0x0 "DMM_PEG_PRIO_PAT,DMM PEG priority register for the internal PAT engine." bitfld.long 0x0 0.--2. " P_PAT ,Priority for PAT engine" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " W_PAT ,Write-enable for P_PAT bit field" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EMIF1" base ad:0x4C000000 width 50. group.byte 0x0++0x3 line.long 0x0 "EMIF_REVISION,Revision number register" hexmask.long 0x0 0.--31. 1. " REVISION ,Module revision" group.byte 0x4++0x3 line.long 0x0 "EMIF_STATUS,SDRAM Status Register (STATUS)" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2. " PHY_DLL_READY ,DDR PHY Ready. The DDR PHY is ready for normal operation, if set to 1." "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " WRLVLTO ,Write Leveling Timeout. Value of 1 indicates write leveling has timed out because write leveling done was not received from the PHY." "0,1" textline " " bitfld.long 0x0 5. " RDLVLTO ,Read Data Eye Training Timeout. Value of 1 indicates read data eye training has timed out because read data eye training done was not received from the PHY." "0,1" bitfld.long 0x0 6. " RDLVLGATETO ,Read DQS Gate Training Timeout. Value of 1 indicates read DQS gate training has timed out because read DQS gate training done was not received from the PHY." "0,1" textline " " hexmask.long.tbyte 0x0 7.--28. 1. " RESERVED ,Reserved" bitfld.long 0x0 29. " FAST_INIT ,Fast Init. Defines whether the EMIF fast initialization mode has been enabled. Fast initialization is enabled if set to 1." "0,1" textline " " bitfld.long 0x0 30. " DUAL_CLK_MODE ,Dual Clock mode. Defines whether the EMIFi_L3_ICLK and EMIF_FICLK clock are asynchronous. EMIFi_L3_ICLK and EMIF_FICLK clock are asynchronous, if set to 1." "0,1" bitfld.long 0x0 31. " BE ,Big endian mode select for 8 and 16-bit devices, set to 1 for big endian or 0 for little endian operation. In current implementation, only 32-bit devices are supported - this bit is don't care." "0,1" group.byte 0x8++0x3 line.long 0x0 "EMIF_SDRAM_CONFIG,SDRAM Config Register. A write to this register will cause the EMIF to start the SDRAM initialization sequence. CAUTION: This register is loaded with values by control module at device reset." bitfld.long 0x0 0.--2. " PAGESIZE ,Page Size. Defines the internal page size of connected SDRAM devices. Set to 0 for 256-word page (8 column bits), Set to 1 for 512-word page (9 column bits), Set to 2 for 1024-word page (10 column bits), Set to 3 for 2048-word page (11 column bits). All other values are reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " IBANK ,Internal Bank setup. Defines number of banks inside connected SDRAM devices. Set to 0 for 1 bank, Set to 1 for 2 banks, Set to 2 for 4 banks, Set to 3 for 8 banks. All other values are reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7.--9. " ROWSIZE ,Row Size. Defines the number of row address bits of connected SDRAM devices. Set to 0 for 9 row bits, Set to 1 for 10 row bits, Set to 2 for 11 row bits, Set to 3 for 12 row bits, Set to 4 for 13 row bits, Set to 5 for 14 row bits, Set to 6 for 15 row bits, Set to 7 for 16 row bits. This field is only used when EMIF_SDRAM_CONFIG[28:27] IBANK_POS field is set to 1, 2, or 3 or EBANK_POS field in EMIF_SDRAM_CONFIG_2 register is set to 1." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 10.--13. " CL ,CAS Latency (referred to as read latency (RL) in some SDRAM specs). The value of this field defines the CAS latency to be used when accessing connected SDRAM devices. Values of 2, 3, 4 and 5 (CAS latency of 2, 3, 4 and 5) are supported for DDR2. Values of 2, 4, 6, 8, 10, 12 and 14 (CAS latency of 5, 6, 7, 8, 9, 10 and 11) are supported for DDR3. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 14.--15. " NARROW_MODE ,SDRAM data bus width. Set to 0 for 32-bit data bus width. Set to 1 for 16-bit data bus width. All other values are reserved." "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " CWL ,DDR3 CAS Write latency. Value of 0, 1, 2, and 3 (CAS write latency of 5, 6, 7, and 8) are supported. Use the lowest value supported for best performance. All other values are reserved." "0,1,2,3" bitfld.long 0x0 18.--19. " SDRAM_DRIVE ,SDRAM drive strength.For DDR3, set to 0 for RZQ/6 and set to 1 for RZQ/7. All other values are reserved." "0,1,2,3" textline " " bitfld.long 0x0 20. " DDR_DISABLE_DLL ,Disable DLL select. Set to 1 to disable DLL inside SDRAM." "0,1" bitfld.long 0x0 21.--22. " DYN_ODT ,DDR3 Dynamic ODT. NOT SUPPORTED. Set to 0 to turn off dynamic ODT." "0,1,2,3" textline " " bitfld.long 0x0 23. " DDR2_DDQS ,DDR2 differential DDQS enable. NOT SUPPORTED. Set to 1 for compatibility." "0,1" bitfld.long 0x0 24.--26. " DDR_TERM ,DDR3 termination resistor value. Set to 0 to disable termination. For DDR3, set to 1 for RZQ/4, set to 2 for RZQ/2, set to 3 for RZQ/6, set to 4 for RZQ/12, and set to 5 for RZQ/8. All other values are reserved." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--28. " IBANK_POS ,Internal bank position. See , SDRAM Address Mapping." "0,1,2,3" bitfld.long 0x0 29.--31. " SDRAM_TYPE ,SDRAM Type selection. This field is loaded from e-fuse. Set to 2 for DDR2 Set to 3 for DDR3 All other values are reserved." "0,1,2,3,4,5,6,7" group.byte 0xC++0x3 line.long 0x0 "EMIF_SDRAM_CONFIG_2,SDRAM Config Register 2 CAUTION: This register is loaded with values by control module at device reset." hexmask.long 0x0 0.--26. 1. " RESERVED ," bitfld.long 0x0 27. " EBANK_POS ,External bank position. Set to 0 to assign external bank address bits from lower OCP address. Set to 1 to assign external bank address bits from higher OCP address bits. See, SDRAM Address Mapping." "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10++0x3 line.long 0x0 "EMIF_SDRAM_REFRESH_CONTROL,SDRAM Refresh Control Register" hexmask.long.word 0x0 0.--15. 1. " REFRESH_RATE ,Refresh Rate. Value in this field is used to define the rate at which connected SDRAM devices will be refreshed. SDRAM refresh rate = REFRESH_RATE / EMIF_PHY_FCLK. A 533-MHz DDR clock rate system that requires a 7.8 5s refresh rate would need 7.8 W 533 = 4157 or 0x103D value to be written. To avoid lock-up situations, the programmer must not program REFRESH_RATE < (6 W EMIF_SDRAM_TIMING_3[12:4] T_RFC)." hexmask.long.byte 0x0 16.--23. 1. " RESERVED ," textline " " bitfld.long 0x0 24.--26. " PASR ,Partial Array Self Refresh. These bits get loaded into the Extended Mode Register of DDR3 during initialization. For DDR3, set to 0 for full array, set to 1 or 5 for 1/2 array, set to 2 or 6 for 1/4 array, set to 3 or 7 for 1/8 array, and set to 4 for 3/4 array to be refreshed. All other values are reserved. A write to this field will cause the EMIF to start the SDRAM initialization sequence." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28. " ASR ,DDR3 Auto Self Refresh enable. Set to 1 for auto Self Refresh enable. Set to 0 for manual Self Refresh reference indicated by the SRT field. A write to this field will cause the EMIF to start the SDRAM initialization sequence." "0,1" bitfld.long 0x0 29. " SRT ,DDR3 Self Refresh temperature range. Set to 0 for normal operating temperature range and set to 1 for extended operating temperature range when the ASR field is set to 0. This bit must be set to 0 if the ASR field is set to 1. A write to this field will cause the EMIF to start the SDRAM initialization sequence." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ," "0,1" bitfld.long 0x0 31. " INITREF_DIS ,Initialization and Refresh disable. When set to 1, EMIF will disable SDRAM initialization and refreshes, but will carry out SDRAM write/read transactions." "0,1" group.byte 0x14++0x3 line.long 0x0 "EMIF_SDRAM_REFRESH_CONTROL_SHADOW,SDRAM Refresh Control Shadow Register" hexmask.long.word 0x0 0.--15. 1. " REFRESH_RATE_SHDW ,Shadow field for REFRESH_RATE. This field is loaded intoEMIF_SDRAM_REFRESH_CONTROL[15:0] REFRESH_RATE field when SIdleAck is asserted." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_1,SDRAM Timing 1 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x0 0.--2. " T_WTR ,Minimum number of DDR clock cycles from last Write to Read, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " T_RRD ,Minimum number of DDR clock cycles from Activate to Activate for a different bank, minus one. For an 8-bank, this field must be equal to ((tFAW / (4 W tCK)) - 1)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6.--11. " T_RC ,Minimum number of DDR clock cycles from Activate to Activate, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12.--16. " T_RAS ,Minimum number of DDR clock cycles from Activate to Precharge, minus one. T_RAS value needs to be bigger than or equal to T_RDC value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--20. " T_WR ,Minimum number of DDR clock cycles from last Write transfer to Precharge, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 21.--24. " T_RCD ,Minimum number of DDR clock cycles from Activate to Read or Write, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 25.--28. " T_RP ,Minimum number of DDR clock cycles from Precharge to Activate or Refresh, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 29.--31. " T_RTW ,Minimum number of DDR clock cycles between Read to Write data phases, minus one." "0,1,2,3,4,5,6,7" group.byte 0x1C++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_1_SHADOW,SDRAM Timing 1 Shadow Register" bitfld.long 0x0 0.--2. " T_WTR_SHDW ,Shadow field for T_WTR. This field is loaded intoEMIF_SDRAM_TIMING_1[2:0] T_WTR field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " T_RRD_SHDW ,Shadow field for T_RRD. This field is loaded intoEMIF_SDRAM_TIMING_1[5:3] T_RRD field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6.--11. " T_RC_SHDW ,Shadow field for T_RC. This field is loaded intoEMIF_SDRAM_TIMING_1[11:6] T_RC field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12.--16. " T_RAS_SHDW ,Shadow field for T_RAS. This field is loaded intoEMIF_SDRAM_TIMING_1[16:12] T_RAS field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--20. " T_WR_SHDW ,Shadow field for T_WR. This field is loaded intoEMIF_SDRAM_TIMING_1[20:17] T_WR field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 21.--24. " T_RCD_SHDW ,Shadow field for T_RCD. This field is loaded intoEMIF_SDRAM_TIMING_1[24:21] T_RCD field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 25.--28. " T_RP_SHDW ,Shadow field for T_RP. This field is loaded intoEMIF_SDRAM_TIMING_1[28:25] T_RP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 29.--31. " T_RTW_SHDW ,Shadow field for T_RTW. This field is loaded intoEMIF_SDRAM_TIMING_1[31:29] T_RTW field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" group.byte 0x20++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_2,SDRAM Timing 2 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x0 0.--2. " T_CKE ,Minimum number of DDR clock cycles between CKE pin changes, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " T_RTP ,Minimum number of DDR clock cycles for the last read command to a Precharge command, minus one." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 6.--15. 1. " T_XSRD ,Minimum number of DDR clock cycles from Self-Refresh exit to a Read command, minus one." hexmask.long.word 0x0 16.--24. 1. " T_XSNR ,Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command, minus one." textline " " bitfld.long 0x0 25.--27. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28.--30. " T_XP ,Minimum number of DDR clock cycles from power-down exit to any command other than a read command, minus one." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_2_SHADOW,SDRAM Timing 2 Shadow Register" bitfld.long 0x0 0.--2. " T_CKE_SHDW ,Shadow field for T_CKE. This field is loaded intoEMIF_SDRAM_TIMING_2[2:0] T_CKE field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " T_RTP_SHDW ,Shadow field for T_RTP. This field is loaded intoEMIF_SDRAM_TIMING_2[5:3] T_RTP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 6.--15. 1. " T_XSRD_SHDW ,Shadow field for T_XSRD. This field is loaded intoEMIF_SDRAM_TIMING_2[15:6] T_XSRD field when SIdleAck is asserted." hexmask.long.word 0x0 16.--24. 1. " T_XSNR_SHDW ,Shadow field for T_XSNR. This field is loaded intoEMIF_SDRAM_TIMING_2[24:16] T_XSNR field when SIdleAck is asserted." textline " " bitfld.long 0x0 25.--27. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28.--30. " T_XP_SHDW ,Shadow field for T_XP. This field is loaded intoEMIF_SDRAM_TIMING_2[30:28] T_XP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x28++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_3,SDRAM Timing 3 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x0 0.--3. " T_RAS_MAX ,Maximum number of REFRESH_RATE intervals from Activate to Precharge command. This field must be equal to ((tRASmax / tREFI)-1) rounded down to the next lower integer. Value for T_RAS_MAX can be calculated as follows: If tRASmax = 120 us and tREFI = 15.7 us, then T_RAS_MAX = ((120/15.7)-1) = 6.64. Round down to the next lower integer. Therefore, the programmed value must be 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--12. 1. " T_RFC ,Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate, minus one." textline " " bitfld.long 0x0 13.--14. " RESERVED ," "0,1,2,3" bitfld.long 0x0 15.--20. " ZQ_ZQCS ,Number of DDR clock cycles for a ZQCS command, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 21.--23. " T_CKESR ,Minimum number of DDR clock cycles for which SDRAM must remain in Self Refresh, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--27. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " T_PDLL_UL ,Minimum number of DDR clock cycles for PHY DLL to unlock. A value of N will be equal to N x 128 clocks." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x2C++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_3_SHADOW,SDRAM Timing 3 Shadow Register" bitfld.long 0x0 0.--3. " T_RAS_MAX_SHDW ,Shadow field for T_RAS_MAX. This field is loaded intoEMIF_SDRAM_TIMING_3[3:0] T_RAS_MAX field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--12. 1. " T_RFC_SHDW ,Shadow field for T_RFC. This field is loaded intoEMIF_SDRAM_TIMING_3[12:4] T_RFC when SIdleAck is asserted." textline " " bitfld.long 0x0 13.--14. " RESERVED ," "0,1,2,3" bitfld.long 0x0 15.--20. " ZQ_ZQCS_SHDW ,Shadow field for ZQ_ZQCS. This field is loaded into ZQ_ZQCS field inEMIF_SDRAM_TIMING_3 register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 21.--23. " T_CKESR_SHDW ,Shadow field for T_CKESR. This field is loaded into T_CKESR field inEMIF_SDRAM_TIMING_3 register when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--27. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " T_PDLL_UL_SHDW ,Shadow field for T_PDLL_UL. This field is loaded into T_PDLL_UL field inEMIF_SDRAM_TIMING_3 register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x30++0x3 line.long 0x0 "EMIF_LPDDR2_NVM_TIMING,NOTE: This register is not supported. It is kept only for code compatibility." hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "EMIF_LPDDR2_NVM_TIMING_SHADOW,NOTE: This register is not supported. It is kept only for code compatibility." hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "EMIF_POWER_MANAGEMENT_CONTROL,Power Management Control Register. Updating the *_TIM fields must be followed by at least one access to SDRAM for the new value to take an effect." bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SR_TIM ,Power Management timer for Self Refresh. The EMIF will put the external SDRAM in Self Refresh mode after the EMIF is idle for these number of DDR clock cycles and if LP_MODE field is set to 2. Set to 0 to immediately enter Self Refresh mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--10. " LP_MODE ,Automatic Power Management enable. 0x0: Disable automatic power management 0x1: Reserved 0x2: Self Refresh mode 0x3: Disable automatic power management 0x4: Power-Down mode All other values disable automatic power management." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--15. " PD_TIM ,Power Management timer for Power-Down. The EMIF will put the external SDRAM in Power-Down mode after the EMIF is idle for these number of DDR clock cycles and if LP_MODE field is set to 4. Set to 0 to immediately enter Power-Down mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "EMIF_POWER_MANAGEMENT_CONTROL_SHADOW,Power Management Control Shadow Register" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SR_TIM_SHDW ,Shadow field for SR_TIM. This field is loaded into SR_TIM field inEMIF_POWER_MANAGEMENT_CONTROL register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PD_TIM_SHDW ,Shadow field for PD_TIM. This field is loaded into PD_TIM field inEMIF_POWER_MANAGEMENT_CONTROL register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "EMIF_OCP_CONFIG,OCP Config Register" hexmask.long.tbyte 0x0 0.--19. 1. " RESERVED ," bitfld.long 0x0 20.--23. " MPU_THRESH_MAX ,MPU Threshold Maximum. The number of commands the MPU interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve no space for the associated interface. In the event the value is set to zero and a request is seen for that interface, the command FIFO will assume a value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " SYS_THRESH_MAX ,System OCP Threshold Maximum. The number of commands the system interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve no space for the associated interface. In the event the value is set to zero and a request is seen for that interface, the command FIFO will assume a value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x58++0x3 line.long 0x0 "EMIF_OCP_CONFIG_VALUE_1,OCP Config Value 1 Register" hexmask.long.byte 0x0 0.--7. 1. " CMD_FIFO_DEPTH ,Command FIFO depth" hexmask.long.byte 0x0 8.--15. 1. " WR_FIFO_DEPTH ,Write Data FIFO depth" textline " " hexmask.long.word 0x0 16.--29. 1. " RESERVED ," bitfld.long 0x0 30.--31. " SYS_BUS_WIDTH ,System OCP data bus width 0 = 32-bit wide, 1 = 64-bit wide, 2 = 128-bit wide, 3 = Reserved" "0,1,2,3" group.byte 0x5C++0x3 line.long 0x0 "EMIF_OCP_CONFIG_VALUE_2,OCP Config Value 2 Register" hexmask.long.byte 0x0 0.--7. 1. " RCMD_FIFO_DEPTH ,Read Command FIFO depth" hexmask.long.byte 0x0 8.--15. 1. " RSD_FIFO_DEPTH ,SDRAM Read Data FIFO depth" textline " " hexmask.long.byte 0x0 16.--23. 1. " RREG_FIFO_DEPTH ,Register Read Data FIFO depth" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "EMIF_IODFT_TLGC,EMIF_IODFT_TLGC" bitfld.long 0x0 0. " RESERVED ,Reserved. This bit must not be modified." "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Reserved. This field must not be modified." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--5. " RESERVED ,Reserved. This field must not be modified." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 8. " RESERVED ,Reserved. This bit must not be modified." "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 10. " RESET_PHY ,Reset the DDR PHY. Writing 1 to this bit resets the DDR PHY. This bit will self clear to 0." "0,1" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12. " RESERVED ,Reserved. This bit must not be modified." "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved. This bit must not be modified." "0,1" textline " " bitfld.long 0x0 14. " RESERVED ,Reserved. This bit must not be modified." "0,1" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved. This field must not be modified." group.byte 0x80++0x3 line.long 0x0 "EMIF_PERFORMANCE_COUNTER_1,Performance Counter 1 Register" hexmask.long 0x0 0.--31. 1. " COUNTER1 ,32-bit counter that can be configured as specified in theEMIF_PERFORMANCE_COUNTER_CONFIG register and EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT register." group.byte 0x84++0x3 line.long 0x0 "EMIF_PERFORMANCE_COUNTER_2,Performance Counter 2 Register" hexmask.long 0x0 0.--31. 1. " COUNTER2 ,32-bit counter that can be configured as specified in theEMIF_PERFORMANCE_COUNTER_CONFIG register and EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT register." group.byte 0x88++0x3 line.long 0x0 "EMIF_PERFORMANCE_COUNTER_CONFIG,Performance Counter Config Register" bitfld.long 0x0 0.--3. " CNTR1_CFG ,Filter configuration forEMIF_PERFORMANCE_COUNTER_1. Refer to for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--13. 1. " RESERVED ,Reserved for future use" textline " " bitfld.long 0x0 14. " CNTR1_REGION_EN ,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_1 register." "0,1" bitfld.long 0x0 15. " CNTR1_MCONNID_EN ,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_1 register." "0,1" textline " " bitfld.long 0x0 16.--19. " CNTR2_CFG ,Filter configuration forEMIF_PERFORMANCE_COUNTER_2. Refer to for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--29. 1. " RESERVED ,Reserved for future use" textline " " bitfld.long 0x0 30. " CNTR2_REGION_EN ,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_2 register." "0,1" bitfld.long 0x0 31. " CNTR2_MCONNID_EN ,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_2 register." "0,1" group.byte 0x8C++0x3 line.long 0x0 "EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT,Performance Counter Master Region Select Register The values programmed into the MCONNIDx fields are those in the ConnID Values table in , Interconnect." bitfld.long 0x0 0.--1. " REGION_SEL1 ,MAddrSpace forEMIF_PERFORMANCE_COUNTER_1 register." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x0 8.--15. 1. " MCONNID1 ,MConnID forEMIF_PERFORMANCE_COUNTER_1 register." bitfld.long 0x0 16.--17. " REGION_SEL2 ,MAddrSpace forEMIF_PERFORMANCE_COUNTER_2 register." "0,1,2,3" textline " " bitfld.long 0x0 18.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x0 24.--31. 1. " MCONNID2 ,MConnID forEMIF_PERFORMANCE_COUNTER_2 register." group.byte 0x90++0x3 line.long 0x0 "EMIF_PERFORMANCE_COUNTER_TIME,Performance Counter Time Register. This is a free running counter." hexmask.long 0x0 0.--31. 1. " TOTAL_TIME ,32-bit counter that continuously counts number for EMIF_FICLK clock cycles elapsed after EMIF is brought out of reset." group.byte 0x94++0x3 line.long 0x0 "EMIF_MISC_REG,EMIF_MISC_REG" bitfld.long 0x0 0. " DLL_CALIB_OS ,Phy_dll_calib one shot : Setting bit to 1 generates a phy_pll_calib pulse. Bit is self cleared when pll_calib gets generated and ack_wait has been satisfied. Software can poll to confirm completion. Uses the EMIF_DLL_CALIB_CTRL[19:16] ACK_WAIT bit field for time to wait after firing off the phy_dll_calib." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "EMIF_DLL_CALIB_CTRL,Control register to force idle window time to generate a phy_dll_calib that can be used for updating PHY DLLs during voltage ramps. NOTE: Should always be loaded via the shadow register." hexmask.long.word 0x0 0.--8. 1. " DLL_CALIB_INTERVAL ,This field determines the interval between phy_dll_calib generation. This value is multiplied by a precounter of 16 EMIF_FICLK cycles. Program this field one less the value you are targeting; program 1 to achieve interval of 2 (minimum interval supported). Programming zero turns off function. Note the final intervals between dll_calib generation is also a function of ACK_WAIT. Final periodic interval is calculated by: ((DLL_CALIB_INTERVAL + 1) W 16) + ACK_WAIT" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--19. " ACK_WAIT ,The ack_wait determines the required wait time after a phy_dll_calib is generated before another command can be sent. Value program is in terms of EMIF_FICLK cycle count. CAUTION: 5 must be the minimum value ever programmed." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "EMIF_DLL_CALIB_CTRL_SHADOW,Read Idle Control Shadow Register" hexmask.long.word 0x0 0.--8. 1. " DLL_CALIB_INTERVAL_SHDW ,Shadow field for DLL_CALIB_INTERVAL. This field is loaded into DLL_CALIB_INTERVAL field in theEMIF_DLL_CALIB_CTRL register when SIdleAck is asserted" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--19. " ACK_WAIT_SHDW ,Shadow field for ACK_WAIT. This field is loaded into ACK_WAIT field inEMIF_DLL_CALIB_CTRL register when SIdleAck is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "EMIF_END_OF_INTERRUPT,EMIF_END_OF_INTERRUPT" bitfld.long 0x0 0. " EOI ,Software End Of Interrupt (EOI) control. Write 0x0 for system OCP interrupt. This field always reads 0 (no EOI memory)." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS,System OCP Interrupt Raw Status Register" bitfld.long 0x0 0. " ERR_SYS ,Raw status of system OCP interrupt for command or address error. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1.--2. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 3. " WR_ECC_ERR_SYS ,Raw status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location." "0,1" bitfld.long 0x0 4. " TWOBIT_ECC_ERR_SYS ,Raw status of system ECC two bit error detection interrupt." "0,1" textline " " bitfld.long 0x0 5. " ONEBIT_ECC_ERR_SYS ,Raw status of system ECC one bit error correction interrupt." "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0xAC++0x3 line.long 0x0 "EMIF_SYSTEM_OCP_INTERRUPT_STATUS,System OCP Interrupt Status Register" bitfld.long 0x0 0. " ERR_SYS ,Enabled status of system OCP interrupt interrupt for command or address error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x0 1.--2. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 3. " WR_ECC_ERR_SYS ,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x0 4. " TWOBIT_ECC_ERR_SYS ,Enabled status of system ECC two bit error detection interrupt. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 5. " ONEBIT_ECC_ERR_SYS ,Enabled status of system ECC one bit error correction interrupt. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect" "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET,System OCP Interrupt Enable Set Register" bitfld.long 0x0 0. " EN_ERR_SYS ,Enable set for system OCP interrupt for command or address error. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1.--2. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 3. " WR_ECC_ERR_SYS ,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x0 4. " TWOBIT_ECC_ERR_SYS ,Enabled status of system ECC two bit error detection interrupt. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 5. " ONEBIT_ECC_ERR_SYS ,Enabled status of sysem ECC one bit error correction interrupt. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR,System OCP Interrupt Enable Clear Register" bitfld.long 0x0 0. " EN_ERR_SYS ,Enable clear for system OCP interrupt for command or address error. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1.--2. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 3. " WR_ECC_ERR_SYS ,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x0 4. " TWOBIT_ECC_ERR_SYS ,Enabled status of system ECC two bit error detection interrupt. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 5. " ONEBIT_ECC_ERR_SYS ,Enabled status of system ECC one bit error correction interrupt. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0xC8++0x3 line.long 0x0 "EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG,SDRAM Output Impedance Calibration Config Register" hexmask.long.word 0x0 0.--15. 1. " ZQ_REFINTERVAL ,Number of refresh periods between ZQCS commands. This field supports between one refresh period to 256 ms between ZQCS calibration commands. Refresh period is defined by REFRESH_RATE inEMIF_SDRAM_REFRESH_CONTROL register." bitfld.long 0x0 16.--17. " ZQ_ZQCL_MULT ,Indicates the number of ZQCS intervals that make up a ZQCL duration, minus one. ZQCS interval is defined by ZQ_ZQCS inEMIF_SDRAM_TIMING_3." "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " ZQ_ZQINIT_MULT ,Indicates the number of ZQCL durations that make up a ZQINIT duration, minus one." "0,1,2,3" hexmask.long.byte 0x0 20.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ZQ_SFEXITEN ,Writing a 1 enables the issuing of ZQCL on Self-Refresh, Active Power-Down, and Precharge Power-Down exit." "0,1" bitfld.long 0x0 29. " RESERVED ," "0,1" textline " " bitfld.long 0x0 30. " ZQ_CS0EN ,Writing a 1 enables ZQ calibration for CS0." "0,1" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xCC++0x3 line.long 0x0 "EMIF_TEMP_ALERT_CONFIG,Temperature Alert Configuration Register.NOTE: This register is only applicable to LPDDR2 memories and cannot be used in this device." hexmask.long.tbyte 0x0 0.--21. 1. " TA_REFINTERVAL ,Number of refresh periods between temperature alert polls. This field supports between one refresh period to 10 seconds between temperature alert polls. Refresh period is defined by REFRESH_RATE inEMIF_SDRAM_REFRESH_CONTROL register." bitfld.long 0x0 22.--23. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 24.--25. " TA_DEVCNT ,This field indicates which external byte lanes contain a device for temperature monitoring. A value of 0: one device, 1: two devices, 2: four devices. All other reserved." "0,1,2,3" bitfld.long 0x0 26.--27. " TA_DEVWDT ,This field indicates how wide a physical device is. It is used in conjunction with the TA_DEVCNT field to determine which byte lanes contain the temperature alert info. A value of 0: 8-bit wide, 1: 16-bit wide, 2: 32-bit wide. All others are reserved. If this field is set to 1 and the TA_DEVCNT field is set to 1 the byte mask for checking is 4'b0101." "0,1,2,3" textline " " bitfld.long 0x0 28. " TA_SFEXITEN ,Temperature Alert Poll on Self-Refresh, Active Power-Down, and Precharge Power-Down exit enable. Writing 1 enables the issuing of a temperature alert poll on Self-Refresh exit." "0,1" bitfld.long 0x0 29. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 30. " TA_CS0EN ,Writing 1 enables temperature alert polling for CS0." "0,1" bitfld.long 0x0 31. " TA_CS1EN ,Writing 1 enables temperature alert polling for CS1." "0,1" group.byte 0xD0++0x3 line.long 0x0 "EMIF_OCP_ERROR_LOG,OCP Error Log Register. This register is overwritten by any first error transaction once after the interrupt is serviced and cleared by writing 0x1 to the[0] ERR_SYS bit." hexmask.long.byte 0x0 0.--7. 1. " MCONNID ,Connection ID of the first errored transaction." bitfld.long 0x0 8.--10. " MCMD ,Command type of the first errored transaction. (see, L3_MAIN Interconnect for more information)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--13. " MBURSTSEQ ,Addressing mode of the first errored transaction. (see, L3_MAIN Interconnect for more information)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " MADDRSPACE ,Address space of the first errored transaction. 0x0: SDRAM 0x1: reserved 0x2: reserved 0x3: internal registers" "0,1,2,3" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved for future use." group.byte 0xD4++0x3 line.long 0x0 "EMIF_READ_WRITE_LEVELING_RAMP_WINDOW,Read/write leveling ramp window register" hexmask.long.word 0x0 0.--12. 1. " RDWRLVLINC_RMP_WIN ,Incremental leveling ramp window in number of refresh periods. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE inEMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xD8++0x3 line.long 0x0 "EMIF_READ_WRITE_LEVELING_RAMP_CONTROL,Read/write leveling ramp control register" hexmask.long.byte 0x0 0.--7. 1. " WRLVLINC_RMP_INT ,Incremental write leveling interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental write leveling during ramp window. A value of 0 will disable incremental write leveling.NOTE: Incremental leveling is not supported on this device." hexmask.long.byte 0x0 8.--15. 1. " RDLVLGATEINC_RMP_INT ,Incremental read DQS gate training interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental read DQS gate training during ramp window. A value of 0 will disable incremental read DQS gate training.NOTE: Incremental leveling is not supported on this device." textline " " hexmask.long.byte 0x0 16.--23. 1. " RDLVLINC_RMP_INT ,Incremental read data eye training interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental read data eye training during ramp window. A value of 0 will disable incremental read data eye training.NOTE: Incremental leveling is not supported on this device." hexmask.long.byte 0x0 24.--30. 1. " RDWRLVLINC_RMP_PRE ,Incremental leveling pre-scalar in number of refresh periods during ramp window. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE inEMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device." textline " " bitfld.long 0x0 31. " RDWRLVL_EN ,Read-Write Leveling enable. Set 1 to enable leveling. Set 0 to disable leveling." "0,1" group.byte 0xDC++0x3 line.long 0x0 "EMIF_READ_WRITE_LEVELING_CONTROL,Read/write leveling control register" hexmask.long.byte 0x0 0.--7. 1. " WRLVLINC_INT ,Incremental write leveling interval. Number of RDWRLVLINC_PRE intervals between incremental write leveling. A value of 0 will disable incremental write leveling.NOTE: Incremental leveling is not supported on this device." hexmask.long.byte 0x0 8.--15. 1. " RDLVLGATEINC_INT ,Incremental read DQS gate training interval. Number of RDWRLVLINC_PRE intervals between incremental read DQS gate training. A value of 0 will disable incremental read DQS gate training.NOTE: Incremental leveling is not supported on this device." textline " " hexmask.long.byte 0x0 16.--23. 1. " RDLVLINC_INT ,Incremental read data eye training interval. Number of RDWRLVLINC_PRE intervals between incremental read data eye training. A value of 0 will disable incremental read data eye training.NOTE: Incremental leveling is not supported on this device." hexmask.long.byte 0x0 24.--30. 1. " RDWRLVLINC_PRE ,Incremental leveling pre-scalar in number of refresh periods. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE inEMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device." textline " " bitfld.long 0x0 31. " RDWRLVLFULL_START ,Full leveling trigger. Writing a 1 to this field triggers full read and write leveling. This bit will self clear to 0." "0,1" group.byte 0xE4++0x3 line.long 0x0 "EMIF_DDR_PHY_CONTROL_1,PHY control register 1" bitfld.long 0x0 0.--4. " READ_LATENCY ,This field defines the read latency for the read data from SDRAM in number of DDR clock cycles. This field is used by the EMIF as well as the PHY. READ_LATENCY = RL + reg_phy_rdc_we_to_re -1. EMIF uses above equation to calculate reg_phy_rdc_we_to_re and forward it to the PHY. For DDR3, the true RL is used, not the decoded value. See JEDEC spec." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " PHY_FAST_DLL_LOCK ,Controls master DLL to lock fast or average logic must be part of locking process. Set to 1 before OPP transition commences, and set back to 0 after OPP transition completes. 1: MDLL lock is asserted based on single sample 0: MDLL lock is asserted based on average of 16 samples." "0,1" hexmask.long.byte 0x0 10.--17. 1. " PHY_DLL_LOCK_DIFF ,The maximum number of delay line taps variation while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by this field, the lock signal is de-asserted and a dll_calib signal is generated. To prevent the dll_calib signal from being asserted in the middle of traffic when the clock jitter exceeds the variation, this register needs to be set to a value which will ensure that the lock will not be lost. Recommended value is 16." textline " " bitfld.long 0x0 18. " PHY_INVERT_CLKOUT ,Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM" "0,1" bitfld.long 0x0 19. " PHY_DIS_CALIB_RST ,Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of data PHYs. Debug only. Note: dll_calib is generated by 1. EMIF_MISC_REG[0] DLL_CALIB_OS set to 1,or 2. by the PHY when it detects that the clock frequency variation has exceeded the bounds set by PHY_DLL_LOCK_DIFF or 3. periodically throughout the leveling process." "0,1" textline " " bitfld.long 0x0 20. " PHY_CLK_STALL_LEVEL ,Enable variable idle value for delay lines. Enable during normal operations to avoid differential aging in the delay lines." "0,1" bitfld.long 0x0 21. " PHY_HALF_DELAYS ,Adjust slave delay line delays to support 2W mode 1: 2W mode (MDLL clock is half the rate of PHY) 0: 1W mode (MDLL clock rate is same as PHY)" "0,1" textline " " bitfld.long 0x0 22.--24. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 25. " WRLVL_MASK ,Writing a 1 to this field will mask write leveling training during full leveling command, plus drives reg_phy_use_wr_level control low to allow user to use programmed ratio values." "0,1" textline " " bitfld.long 0x0 26. " RDLVLGATE_MASK ,Writing a 1 to this field will mask dqs gate training during full leveling command, plus drives reg_phy_use_rd_dqs_level control low to allow user to use programmed ratio values." "0,1" bitfld.long 0x0 27. " RDLVL_MASK ,Writing a 1 to this field will mask read data eye training during full leveling command, plus drives reg_phy_use_rd_data_eye_level control low to allow user to use programmed ratio values." "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xE8++0x3 line.long 0x0 "EMIF_DDR_PHY_CONTROL_1_SHADOW,EMIF_DDR_PHY_CONTROL_1_SHADOW" bitfld.long 0x0 0.--4. " READ_LATENCY_SHDW ,Shadow field for READ_LATENCY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " PHY_FAST_DLL_SHDW ,Shadow field for PHY_FAST_DLL" "0,1" hexmask.long.byte 0x0 10.--17. 1. " PHY_DLL_LOCK_DIFF_SHDW ,Shadow field for PHY_DLL_LOCK_DIFF" textline " " bitfld.long 0x0 18. " PHY_INVERT_CLKOUT_SHDW ,Shadow field for PHY_INVERT_CLKOUT" "0,1" bitfld.long 0x0 19. " PHY_DIS_CALIB_RST_SHDW ,Shadow field for PHY_DIS_CALIB_RST" "0,1" textline " " bitfld.long 0x0 20. " PHY_CLK_STALL_LEVEL_SHDW ,Shadow field for PHY_CLK_STALL_LEVEL" "0,1" bitfld.long 0x0 21. " PHY_HALF_DELAYS_SHDW ,Shadow field for PHY_HALF_DELAYS" "0,1" textline " " bitfld.long 0x0 22.--24. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 25. " WRLVL_MASK_SHDW ,Shadow field for WRLVL_MASK" "0,1" textline " " bitfld.long 0x0 26. " RDLVLGATE_MASK_SHDW ,Shadow field for RDLVLGATE_MASK" "0,1" bitfld.long 0x0 27. " RDLVL_MASK_SHDW ,Shadow field for RDLVL_MASK" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xEC++0x3 line.long 0x0 "EMIF_DDR_PHY_CONTROL_2,EMIF_DDR_PHY_CONTROL_2" hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING,EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING" bitfld.long 0x0 0.--1. " PRI_0_COS ,Class of service for commands with priority of 0. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" bitfld.long 0x0 2.--3. " PRI_1_COS ,Class of service for commands with priority of 1. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " PRI_2_COS ,Class of service for commands with priority of 2. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" bitfld.long 0x0 6.--7. " PRI_3_COS ,Class of service for commands with priority of 3. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " PRI_4_COS ,Class of service for commands with priority of 4. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" bitfld.long 0x0 10.--11. " PRI_5_COS ,Class of service for commands with priority of 5. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " PRI_6_COS ,Class of service for commands with priority of 6. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" bitfld.long 0x0 14.--15. " PRI_7_COS ,Class of service for commands with priority of 7. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--30. 1. " RESERVED ," bitfld.long 0x0 31. " PRI_COS_MAP_EN ,Set 1 to enable priority to class of service mapping. Set 0 to disable mapping." "0,1" group.byte 0x104++0x3 line.long 0x0 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING,EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING" bitfld.long 0x0 0.--1. " MSK_3_COS_1 ,Mask for Connection ID value 3 for class of service 1. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0." "0,1,2,3" hexmask.long.byte 0x0 2.--9. 1. " CONNID_3_COS_1 ,Connection ID value 3 for class of service 1." textline " " bitfld.long 0x0 10.--11. " MSK_2_COS_1 ,Mask for Connection ID value 2 for class of service 1. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0." "0,1,2,3" hexmask.long.byte 0x0 12.--19. 1. " CONNID_2_COS_1 ,Connection ID value 2 for class of service 1." textline " " bitfld.long 0x0 20.--22. " MSK_1_COS_1 ,Mask for Connection ID value 1 for class of service 1. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0. Value of 4 will mask Connection ID bits 3:0. Value of 5 will mask Connection ID bits 4:0. Value of 6 will mask Connection ID bits 5:0. Value of 7 will mask Connection ID bits 6:0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 23.--30. 1. " CONNID_1_COS_1 ,Connection ID value 1 for class of service 1." textline " " bitfld.long 0x0 31. " CONNID_COS_1_MAP_EN ,Set 1 to enable Connection ID to class of service 1 mapping. Set 0 to disable mapping." "0,1" group.byte 0x108++0x3 line.long 0x0 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING,EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING" bitfld.long 0x0 0.--1. " MSK_3_COS_2 ,Mask for Connection ID value 3 for class of service 2. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0." "0,1,2,3" hexmask.long.byte 0x0 2.--9. 1. " CONNID_3_COS_2 ,Connection ID value 3 for class of service 2." textline " " bitfld.long 0x0 10.--11. " MSK_2_COS_2 ,Mask for Connection ID value 2 for class of service 2. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0." "0,1,2,3" hexmask.long.byte 0x0 12.--19. 1. " CONNID_2_COS_2 ,Connection ID value 2 for class of service 2." textline " " bitfld.long 0x0 20.--22. " MSK_1_COS_2 ,Mask for Connection ID value 1 for class of service 2. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0. Value of 4 will mask Connection ID bits 3:0. Value of 5 will mask Connection ID bits 4:0. Value of 6 will mask Connection ID bits 5:0. Value of 7 will mask Connection ID bits 6:0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 23.--30. 1. " CONNID_1_COS_2 ,Connection ID value 1 for class of service 2." textline " " bitfld.long 0x0 31. " CONNID_COS_2_MAP_EN ,Set 1 to enable Connection ID to class of service 2 mapping. Set 0 to disable mapping." "0,1" group.byte 0x110++0x3 line.long 0x0 "EMIF_ECC_CTRL_REG,EMIF_ECC_CTRL_REG" bitfld.long 0x0 0. " REG_ECC_ADDR_RGN_1_EN ,Set 1 to enable ECC address range 1. Set 0 to disable ECC address range 1." "0,1" bitfld.long 0x0 1. " REG_ECC_ADDR_RGN_2_EN ,Set 1 to enable ECC address range 2. Set 0 to disable ECC address range 2." "0,1" textline " " hexmask.long 0x0 2.--29. 1. " RESERVED ," bitfld.long 0x0 30. " REG_ECC_ADDR_RGN_PROT ,Setting this field to 1 and reg_ecc_en to a 1 will enable ECC calculation for accesses within the address ranges and disable ECC calculation for accesses outside the address ranges. Setting this field to 0 and reg_ecc_en to a 1 will disable ECC calculation for accesses within the address ranges and enable ECC calculation for accesses outside the address ranges. The address ranges can be specified using the ECC Address Range 1 and 2 registers." "0,1" textline " " bitfld.long 0x0 31. " REG_ECC_EN ,Set 1 to enable ECC. Set 0 to disable ECC." "0,1" group.byte 0x114++0x3 line.long 0x0 "EMIF_ECC_ADDRESS_RANGE_1,EMIF_ECC_ADDRESS_RANGE_1" hexmask.long.word 0x0 0.--15. 1. " REG_ECC_STRT_ADDR_1 ,Start address[31:16] for ECC address range 1. If this bit field is set to 0x0000, this indicates that the SDRAM physical start address on which the ECC applies is 0x0000 0000. This bit field controls only the 16 MSbs of the physical start address of the ECC protected range. The other 16 LSbs are always 0x0000." hexmask.long.word 0x0 16.--31. 1. " REG_ECC_END_ADDR_1 ,End address[31:16] for ECC address range 1. If this bit field is set to 0x1000, this indicates that the SDRAM physical end address on which the ECC applies is 0x1000 FFFF. If this bit field is set to 0x0FFF the physical end address on which the ECC applies is 0x0FFF FFFF. This bit field controls only the 16 MSbs of the physical end address of the ECC protected range. The other 16 LSbs are always 0xFFFF." group.byte 0x118++0x3 line.long 0x0 "EMIF_ECC_ADDRESS_RANGE_2,EMIF_ECC_ADDRESS_RANGE_2" hexmask.long.word 0x0 0.--15. 1. " REG_ECC_STRT_ADDR_2 ,Start address[31:16] for ECC address range 2. If this bit field is set to 0x0000, this indicates that the SDRAM physical start address on which the ECC applies is 0x0000 0000. This bit field controls only the 16 MSbs of the physical start address of the ECC protected range. The other 16 LSbs are always 0x0000." hexmask.long.word 0x0 16.--31. 1. " REG_ECC_END_ADDR_2 ,End address[31:16] for ECC address range 2. If this bit field is set to 0x1000, this indicates that the SDRAM physical end address on which the ECC applies is 0x1000 FFFF. If this bit field is set to 0x0FFF the physical end address on which the ECC applies is 0x0FFF FFFF. This bit field controls only the 16 MSbs of the physical end address of the ECC protected range. The other 16 LSbs are always 0xFFFF." group.byte 0x120++0x3 line.long 0x0 "EMIF_READ_WRITE_EXECUTION_THRESHOLD,EMIF_READ_WRITE_EXECUTION_THRESHOLD" bitfld.long 0x0 0.--4. " RD_THRSH ,Read threshold. Number of SDRAM read bursts after which the EMIF arbitration will switch to executing write commands. The value that is programmed is always minus one the required number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " WR_THRSH ,Write Threshold. Number of SDRAM write bursts after which the EMIF arbitration will switch to executing read commands. The value programmed is always minus one the required number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x0 13.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " MFLAG_OVERRIDE ,Mflag override." "0,1" group.byte 0x124++0x3 line.long 0x0 "EMIF_COS_CONFIG,Priority Raise Counter Register." hexmask.long.byte 0x0 0.--7. 1. " PR_OLD_COUNT ,Priority Raise Old Counter. Number of EMIF_FICLK cycles after which the EMIF momentarily raises the priority of the oldest command in the Command FIFO. A value of N will be equal to N x 16 clocks." hexmask.long.byte 0x0 8.--15. 1. " COS_COUNT_2 ,Priority Raise Counter for class of service 2. Number of EMIF_FICLK cycles after which the EMIF momentarily raises the priority of the class of service 2 commands in the Command FIFO. A value of N will be equal to N x 16 clocks." textline " " hexmask.long.byte 0x0 16.--23. 1. " COS_COUNT_1 ,Priority Raise Counter for class of service 1. Number of EMIF_FICLK cycles after which the EMIF momentarily raises the priority of the class of service 1 commands in the Command FIFO. A value of N will be equal to N x 16 clocks." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "EMIF_1B_ECC_ERR_CNT,EMIF_1B_ECC_ERR_CNT" hexmask.long 0x0 0.--31. 1. " REG_1B_ECC_ERR_CNT ,32 bit counter that displays number of 1-bit ECC errors. Writing a value will decrement the count by that value. For example, if the count is 0x1234_ABF3, writing 0x1234_ABF3 to this register will clear it." group.byte 0x134++0x3 line.long 0x0 "EMIF_1B_ECC_ERR_THRSH,EMIF_1B_ECC_ERR_THRSH" hexmask.long.word 0x0 0.--15. 1. " REG_1B_ECC_ERR_WIN ,1-bit ECC error window in number of refresh periods. The EMIF will generate an interrupt when the 1-bit ECC error count is equal to or greater than the threshold within this window. A value of 0 will disable the window. Refresh period is defined by" hexmask.long.byte 0x0 16.--23. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 24.--31. 1. " REG_1B_ECC_ERR_THRSH ,1-bit ECC error threshold. The EMIF will generate an interrupt when the 1-bit ECC error count is greater than or equal to this threshold. A value of 0 will disable the generation of the interrupt." group.byte 0x138++0x3 line.long 0x0 "EMIF_1B_ECC_ERR_DIST_1,EMIF_1B_ECC_ERR_DIST_1" hexmask.long 0x0 0.--31. 1. " REG_1B_ECC_ERR_DIST_1 ,1-bit ECC error distribution over data bus bit 31:0. A value of 1 on a bit indicates 1-bit error on the corresponding bit on the data bus. Writing a 1 to any bit will clear that bit. Writing a 0 has no effect." group.byte 0x13C++0x3 line.long 0x0 "EMIF_1B_ECC_ERR_ADDR_LOG,EMIF_1B_ECC_ERR_ADDR_LOG" hexmask.long 0x0 0.--31. 1. " REG_1B_ECC_ERR_ADDR ,1-bit ECC error address. Most significant bits of the starting address(es) related to the SDRAM reads that had a 1-bit ECC error. This field displays up to four addresses logged in the 4 deep address logging FIFO. Writing a 0x1 will pop one element of the FIFO. Writing a 0x2 will pop all elements of the FIFO. Writing any other alue will have no effect." group.byte 0x140++0x3 line.long 0x0 "EMIF_2B_ECC_ERR_ADDR_LOG,EMIF_2B_ECC_ERR_ADDR_LOG" hexmask.long 0x0 0.--31. 1. " REG_2B_ECC_ERR_ADDR ,2-bit ECC error address. Most significant bits of the starting address of the first SDRAM burst that had the 2-bit ECC error. Writing a 1 will clear this field. Writing any other value has no effect." group.byte 0x144++0x3 line.long 0x0 "EMIF_PHY_STATUS_1,EMIF_PHY_STATUS_1" bitfld.long 0x0 0.--1. " PHY_REG_PHY_CTRL_DLL_LOCK ,Lock Status for Command DLLs" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--8. " PHY_REG_STATUS_DLL_LOCK ,Lock Status for Data DLLs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 12.--29. 1. " PHY_REG_PHY_CTRL_DLL_SLAVE_VALUE ,DLL Slave Value" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x148++0x3 line.long 0x0 "EMIF_PHY_STATUS_2,EMIF_PHY_STATUS_2" hexmask.long 0x0 0.--31. 1. " PHY_REG_STATUS_DLL_SLAVE_VALUE_LO ,Bits 31:0 of Phy_reg_status_dll_slave_value" group.byte 0x14C++0x3 line.long 0x0 "EMIF_PHY_STATUS_3,EMIF_PHY_STATUS_3" hexmask.long.word 0x0 0.--12. 1. " PHY_REG_STATUS_DLL_SLAVE_VALUE_HI ,Bits 44:32 of Phy_reg_status_dll_slave_value" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--30. 1. " PHY_REG_RDFIFO_RDPTR ,Read FIFO Read Pointer" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x150++0x3 line.long 0x0 "EMIF_PHY_STATUS_4,EMIF_PHY_STATUS_4" hexmask.long.word 0x0 0.--14. 1. " PHY_REG_RDFIFO_WRPTR ,Read FIFO Write Pointer" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--30. 1. " PHY_REG_GATELVL_FSM ,Gate Leveling FSM" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x154++0x3 line.long 0x0 "EMIF_PHY_STATUS_5,EMIF_PHY_STATUS_5" hexmask.long.tbyte 0x0 0.--19. 1. " PHY_REG_RD_LEVEL_FSM ,Read Leveling FSM" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x158++0x3 line.long 0x0 "EMIF_PHY_STATUS_6,EMIF_PHY_STATUS_6" hexmask.long.word 0x0 0.--14. 1. " PHY_REG_WR_LEVEL_FSM ,Write Leveling FSM" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x15C++0x3 line.long 0x0 "EMIF_PHY_STATUS_7,EMIF_PHY_STATUS_7" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO0 ,Read leveling DQS ratio0" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO1 ,Read leveling DQS ratio1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x160++0x3 line.long 0x0 "EMIF_PHY_STATUS_8,EMIF_PHY_STATUS_8" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO2 ,Read leveling DQS ratio2" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO3 ,Read leveling DQS ratio3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x164++0x3 line.long 0x0 "EMIF_PHY_STATUS_9,EMIF_PHY_STATUS_9" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO4 ,Read Leveling DQS ratio4" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO5 ,Read Leveling DQS ratio5" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x168++0x3 line.long 0x0 "EMIF_PHY_STATUS_10,EMIF_PHY_STATUS_10" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO6 ,Read leveling DQS ratio6" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO7 ,Read leveling DQS ratio7" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16C++0x3 line.long 0x0 "EMIF_PHY_STATUS_11,EMIF_PHY_STATUS_11" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO8 ,Read leveling DQS ratio8" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO9 ,Read leveling DQS ratio9" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x170++0x3 line.long 0x0 "EMIF_PHY_STATUS_12,EMIF_PHY_STATUS_12" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO0 ,Read leveling FIFO Write Enable Ratio0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO1 ,Read leveling FIFO Write Enable Ratio1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x174++0x3 line.long 0x0 "EMIF_PHY_STATUS_13,EMIF_PHY_STATUS_13" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO2 ,Read leveling FIFO Write Enable Ratio2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO3 ,Read leveling FIFO Write Enable Ratio3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x178++0x3 line.long 0x0 "EMIF_PHY_STATUS_14,EMIF_PHY_STATUS_14" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO4 ,Read leveling FIFO Write Enable Ratio4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO5 ,Read leveling FIFO Write Enable Ratio5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x17C++0x3 line.long 0x0 "EMIF_PHY_STATUS_15,EMIF_PHY_STATUS_15" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO6 ,Read leveling FIFO Wrie Enable Ratio6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO7 ,Read leveling FIFO Wrie Enable Ratio7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x180++0x3 line.long 0x0 "EMIF_PHY_STATUS_16,EMIF_PHY_STATUS_16" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO8 ,Read leveling FIFO Write Enable Ratio8" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO9 ,Read leveling FIFO Write Enable Ratio9" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x184++0x3 line.long 0x0 "EMIF_PHY_STATUS_17,EMIF_PHY_STATUS_17" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO0 ,Write leveling DQ ratio0" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO1 ,Write leveling DQ ratio1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x188++0x3 line.long 0x0 "EMIF_PHY_STATUS_18,EMIF_PHY_STATUS_18" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO2 ,Write leveling DQ ratio2" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO3 ,Write leveling DQ ratio3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x18C++0x3 line.long 0x0 "EMIF_PHY_STATUS_19,EMIF_PHY_STATUS_19" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO4 ,Write leveling DQ ratio4" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO5 ,Write leveling DQ ratio5" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x190++0x3 line.long 0x0 "EMIF_PHY_STATUS_20,EMIF_PHY_STATUS_20" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO6 ,Write leveling DQ ratio6" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO7 ,Write leveling DQ ratio7" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x194++0x3 line.long 0x0 "EMIF_PHY_STATUS_21,EMIF_PHY_STATUS_21" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO8 ,Write leveling DQ ratio8" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO9 ,Write leveling DQ ratio9" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x198++0x3 line.long 0x0 "EMIF_PHY_STATUS_22,EMIF_PHY_STATUS_22" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO0 ,Write leveling DQS ratio 0" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO1 ,Write leveling DQS ratio 1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19C++0x3 line.long 0x0 "EMIF_PHY_STATUS_23,EMIF_PHY_STATUS_23" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO2 ,Write leveling DQS ratio2" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO3 ,Write leveling DQS ratio3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1A0++0x3 line.long 0x0 "EMIF_PHY_STATUS_24,EMIF_PHY_STATUS_24" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO4 ,Write leveling DQS ratio4" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO5 ,Write leveling DQS ratio5" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1A4++0x3 line.long 0x0 "EMIF_PHY_STATUS_25,EMIF_PHY_STATUS_25" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO6 ,Write leveling DQS ratio6" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO7 ,Write leveling DQS ratio7" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1A8++0x3 line.long 0x0 "EMIF_PHY_STATUS_26,EMIF_PHY_STATUS_26" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO8 ,Write leveling DQS ratio8" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO9 ,Write leveling DQS ratio9" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1AC++0x3 line.long 0x0 "EMIF_PHY_STATUS_27,EMIF_PHY_STATUS_27" hexmask.long.tbyte 0x0 0.--19. 1. " PHY_REG_RDC_FIFO_RST_ERR_CNT ,RDC FIFO reset error count" bitfld.long 0x0 20.--24. " PHY_REG_STATUS_MDLL_UNLOCK_STICKY ,Phy data MDLL unlock sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25.--27. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 28.--29. " PHY_REG_PHY_CONTROL_MDLL_UNLOCK_STICKY ,Phy control MDLL unlock sticky" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x1B0++0x3 line.long 0x0 "EMIF_PHY_STATUS_28,EMIF_PHY_STATUS_28" bitfld.long 0x0 0.--4. " PHY_REG_FIFO_WE_IN_MIASALIGNED_STICKY ,FIFO write enable in misaligned sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " PHY_REG_RDLVL_INC_FAIL ,Read leveling failure.NOTE: Incremental leveling is not supported on this device." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " PHY_REG_WRLVL_INC_FAIL ,Write leveling failure.NOTE: Incremental leveling is not supported on this device." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " PHY_REG_GATELVL_INC_FAIL ,Gate leveling failure.NOTE: Incremental leveling is not supported on this device." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x200++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_1,Control DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_CTRL_SLAVE_RATIO0 ,The user programmable ratio value for address/command launch timing in PHY control macro 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Set to:" hexmask.long.word 0x0 10.--19. 1. " PHY_REG_CTRL_SLAVE_RATIO1 ,The user programmable ratio value for address/command launch timing in PHY control macro 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Set to:" textline " " hexmask.long.word 0x0 20.--29. 1. " PHY_REG_CTRL_SLAVE_RATIO2 ,The user programmable ratio value for address/command launch timing in PHY control macro 2. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x204++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_1_SHADOW,Control DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_CTRL_SLAVE_RATIO0 ,The user programmable ratio value for address/command launch timing in PHY control macro 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Set to:" hexmask.long.word 0x0 10.--19. 1. " PHY_REG_CTRL_SLAVE_RATIO1 ,The user programmable ratio value for address/command launch timing in PHY control macro 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Set to:" textline " " hexmask.long.word 0x0 20.--29. 1. " PHY_REG_CTRL_SLAVE_RATIO2 ,The user programmable ratio value for address/command launch timing in PHY control macro 2. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x208++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_2,Data macro 0, FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO0 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO1 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x20C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_2_SHADOW,Data macro 0, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO0 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO1 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x210++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_3,Data macro 1, FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO2 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO3 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x214++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_3_SHADOW,Data macro 1, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO2 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO3 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x218++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_4,Data macro 2, FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO4 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO5 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x21C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_4_SHADOW,Data macro 2, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO4 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO5 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x220++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_5,Data macro 3, FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO6 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO7 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x224++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_5_SHADOW,Data macro 3, FIFO write enable (read DQS gate) DLL Slave Ratio Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO6 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO7 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x228++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_6,ECC Data macro, FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO8 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO9 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x22C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_6_SHADOW,ECC Data macro, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO8 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO9 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x230++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_7,Data macro 0, read DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO0 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO1 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x234++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_7_SHADOW,Data macro 0, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO0 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO1 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x238++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_8,Data macro 1, read DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO2 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO3 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x23C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_8_SHADOW,Data macro 1, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO2 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO3 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x240++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_9,Data macro 2, read DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO4 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO5 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x244++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_9_SHADOW,Data macro 2, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO4 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO5 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x248++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_10,Data macro 3, read DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO6 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO7 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x24C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_10_SHADOW,Data macro 3, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO6 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO7 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x250++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_11,ECC Data macro, read DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO8 ,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO9 ,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x254++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_11_SHADOW,ECC Data macro, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO8 ,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO9 ,The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x258++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_12,Data macro 0, write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO0 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO1 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x25C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_12_SHADOW,Data macro 0, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO0 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO1 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x260++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_13,Data macro 1, write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO2 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO3 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x264++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_13_SHADOW,Data macro 1, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO2 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO3 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x268++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_14,Data macro 2, write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO4 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO5 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x26C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_14_SHADOW,Data macro 2, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO4 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO5 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x270++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_15,Data macro 3, write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO6 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO7 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x274++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_15_SHADOW,Data macro 3, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO6 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO7 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x278++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_16,ECC Data macro, write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO8 ,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO9 ,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x27C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_16_SHADOW,ECC Data macro, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO8 ,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO9 ,The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x280++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_17,Data macro 0, write DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO0 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO1 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x284++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_17_SHADOW,Data macro 0, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO0 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO1 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x288++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_18,Data macro 1, write DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO2 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO3 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x28C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_18_SHADOW,Data macro 1, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO2 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO3 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x290++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_19,Data macro 2, write DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO4 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO5 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x294++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_19_SHADOW,Data macro 2, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO4 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO5 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x298++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_20,Data macro 3, write DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO6 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO7 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x29C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_20_SHADOW,Data macro 3, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO6 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO7 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x2A0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_21,ECC Data macro, write DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO8 ,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO9 ,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x2A4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_21_SHADOW,ECC Data macro, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO8 ,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO9 ,The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x2A8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_22,EMIF_EXT_PHY_CONTROL_22" hexmask.long.word 0x0 0.--8. 1. " PHY_REG_CTRL_SLAVE_DELAY ,The user programmable command delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PHY_REG_FIFO_WE_IN_DELAY ,The user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x2AC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_22_SHADOW,EMIF_EXT_PHY_CONTROL_22_SHADOW" hexmask.long.word 0x0 0.--8. 1. " PHY_REG_CTRL_SLAVE_DELAY ,The user programmable command delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PHY_REG_FIFO_WE_IN_DELAY ,The user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x2B0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_23,EMIF_EXT_PHY_CONTROL_23" hexmask.long.word 0x0 0.--8. 1. " PHY_REG_RD_DQS_SLAVE_DELAY ,The user programmable read DQS delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PHY_REG_WR_DQS_SLAVE_DELAY ,The user programmable write DQS delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x2B4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_23_SHADOW,EMIF_EXT_PHY_CONTROL_23_SHADOW" hexmask.long.word 0x0 0.--8. 1. " PHY_REG_RD_DQS_SLAVE_DELAY ,The user programmable read DQS delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PHY_REG_WR_DQS_SLAVE_DELAY ,The user programmable write DQS delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x2B8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_24,EMIF_EXT_PHY_CONTROL_24" hexmask.long.word 0x0 0.--8. 1. " REG_PHY_WR_DATA_SLAVE_DELAY ,The user programmable write DQ delay value used when DLL_OVERRIDE = 1." bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12. " REG_PHY_USE_RANK0_DELAYS ,Delay selection. Chip select 0 delay line ratios are used for all chip selects when set to 1. Each chip select uses its own delays when set to 0." "0,1" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " REG_PHY_GATELVL_INIT_MODE ,The user programmable init ratio selection mode. Recommended value is 0x1." "0,1" hexmask.long.byte 0x0 17.--23. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 24.--30. 1. " REG_PHY_DQ_OFFSET_HI ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY ECC data macro. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x2BC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_24_SHADOW,EMIF_EXT_PHY_CONTROL_24_SHADOW" hexmask.long.word 0x0 0.--8. 1. " REG_PHY_WR_DATA_SLAVE_DELAY ,The user programmable write DQ delay value used when DLL_OVERRIDE = 1." bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12. " REG_PHY_USE_RANK0_DELAYS ,Delay selection. Chip select 0 delay line ratios are used for all chip selects when set to 1. Each chip select uses its own delays when set to 0." "0,1" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " REG_PHY_GATELVL_INIT_MODE ,The user programmable init ratio selection mode. Recommended value is 0x1." "0,1" hexmask.long.byte 0x0 17.--23. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 24.--30. 1. " REG_PHY_DQ_OFFSET_HI ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY ECC data macro. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x2C0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_25,DQ DLL Slave Ratio Offset Register" hexmask.long.byte 0x0 0.--6. 1. " REG_PHY_DQ_OFFSET0 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 0. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." hexmask.long.byte 0x0 7.--13. 1. " REG_PHY_DQ_OFFSET1 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 1. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." textline " " hexmask.long.byte 0x0 14.--20. 1. " REG_PHY_DQ_OFFSET2 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 2. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." hexmask.long.byte 0x0 21.--27. 1. " REG_PHY_DQ_OFFSET3 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 3. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x2C4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_25_SHADOW,DQ DLL Slave Ratio Offset Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.byte 0x0 0.--6. 1. " REG_PHY_DQ_OFFSET0 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 0. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." hexmask.long.byte 0x0 7.--13. 1. " REG_PHY_DQ_OFFSET1 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 1. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." textline " " hexmask.long.byte 0x0 14.--20. 1. " REG_PHY_DQ_OFFSET2 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 2. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." hexmask.long.byte 0x0 21.--27. 1. " REG_PHY_DQ_OFFSET3 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 3. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x2C8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_26,Data macro 0, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO0 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO1 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2CC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_26_SHADOW,Data macro 0, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO0 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO1 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2D0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_27,Data macro 1, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO2 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO3 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2D4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_27_SHADOW,Data macro 1, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO2 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO3 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2D8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_28,Data macro 2, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO4 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO5 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2DC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_28_SHADOW,Data macro 2, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO4 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO5 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2E0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_29,Data macro 3, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO6 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO7 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2E4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_29_SHADOW,Data macro 3, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO6 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO7 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2E8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_30,ECC Data macro, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO8 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO9 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2EC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_30_SHADOW,ECC Data macro, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO8 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO9 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2F0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_31,Data macro 0, write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO0 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO1 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x2F4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_31_SHADOW,Data macro 0, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO0 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO1 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x2F8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_32,Data macro 1, write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO2 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO3 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x2FC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_32_SHADOW,Data macro 1, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO2 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO3 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x300++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_33,Data macro 2, write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO4 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO5 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x304++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_33_SHADOW,Data macro 2, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO4 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO5 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x308++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_34,Data macro 3, write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO6 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO7 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x30C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_34_SHADOW,Data macro 3, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO6 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO7 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x310++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_35,ECC Data macro, write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO8 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO9 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x314++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_35_SHADOW,ECC Data macro, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO8 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO9 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x318++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_36,EMIF_EXT_PHY_CONTROL_36" bitfld.long 0x0 0.--3. " REG_PHY_GATELVL_NUM_OF_DQ0 ,Determines the number of samples fordq0_in for each ratio increment by the gate training finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " REG_PHY_WRLVL_NUM_OF_DQ0 ,Determines the number of samples fordq0_in for each ratio increment by the write leveling finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " REG_PHY_FIFO_WE_IN_MISALIGNED_CLR ,Clears the phy_reg_fifo_we_in_misaligned_sticky status flag. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" bitfld.long 0x0 9. " REG_PHY_MDLL_UNLOCK_CLR ,Clears the phy_reg_status_mdll_unlock_sticky flag. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" textline " " bitfld.long 0x0 10. " REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset the phy_reg_rdc_fifo_rst_err_cnt, phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x31C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_36_SHADOW,EMIF_EXT_PHY_CONTROL_36_SHADOW" bitfld.long 0x0 0.--3. " REG_PHY_GATELVL_NUM_OF_DQ0 ,Determines the number of samples fordq0_in for each ratio increment by the gate training finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " REG_PHY_WRLVL_NUM_OF_DQ0 ,Determines the number of samples fordq0_in for each ratio increment by the write leveling finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " REG_PHY_FIFO_WE_IN_MISALIGNED_CLR ,Clears the phy_reg_fifo_we_in_misaligned_sticky status flag. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" bitfld.long 0x0 9. " REG_PHY_MDLL_UNLOCK_CLR ,Clears the phy_reg_status_mdll_unlock_sticky flag. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" textline " " bitfld.long 0x0 10. " REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset the phy_reg_rdc_fifo_rst_err_cnt, phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," width 0x0B tree.end tree "EMIF2" base ad:0x4D000000 width 50. group.byte 0x0++0x3 line.long 0x0 "EMIF_REVISION,Revision number register" hexmask.long 0x0 0.--31. 1. " REVISION ,Module revision" group.byte 0x4++0x3 line.long 0x0 "EMIF_STATUS,SDRAM Status Register (STATUS)" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2. " PHY_DLL_READY ,DDR PHY Ready. The DDR PHY is ready for normal operation, if set to 1." "0,1" textline " " bitfld.long 0x0 3. " RESERVED ," "0,1" bitfld.long 0x0 4. " WRLVLTO ,Write Leveling Timeout. Value of 1 indicates write leveling has timed out because write leveling done was not received from the PHY." "0,1" textline " " bitfld.long 0x0 5. " RDLVLTO ,Read Data Eye Training Timeout. Value of 1 indicates read data eye training has timed out because read data eye training done was not received from the PHY." "0,1" bitfld.long 0x0 6. " RDLVLGATETO ,Read DQS Gate Training Timeout. Value of 1 indicates read DQS gate training has timed out because read DQS gate training done was not received from the PHY." "0,1" textline " " hexmask.long.tbyte 0x0 7.--28. 1. " RESERVED ,Reserved" bitfld.long 0x0 29. " FAST_INIT ,Fast Init. Defines whether the EMIF fast initialization mode has been enabled. Fast initialization is enabled if set to 1." "0,1" textline " " bitfld.long 0x0 30. " DUAL_CLK_MODE ,Dual Clock mode. Defines whether the EMIFi_L3_ICLK and EMIF_FICLK clock are asynchronous. EMIFi_L3_ICLK and EMIF_FICLK clock are asynchronous, if set to 1." "0,1" bitfld.long 0x0 31. " BE ,Big endian mode select for 8 and 16-bit devices, set to 1 for big endian or 0 for little endian operation. In current implementation, only 32-bit devices are supported - this bit is don't care." "0,1" group.byte 0x8++0x3 line.long 0x0 "EMIF_SDRAM_CONFIG,SDRAM Config Register. A write to this register will cause the EMIF to start the SDRAM initialization sequence. CAUTION: This register is loaded with values by control module at device reset." bitfld.long 0x0 0.--2. " PAGESIZE ,Page Size. Defines the internal page size of connected SDRAM devices. Set to 0 for 256-word page (8 column bits), Set to 1 for 512-word page (9 column bits), Set to 2 for 1024-word page (10 column bits), Set to 3 for 2048-word page (11 column bits). All other values are reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " IBANK ,Internal Bank setup. Defines number of banks inside connected SDRAM devices. Set to 0 for 1 bank, Set to 1 for 2 banks, Set to 2 for 4 banks, Set to 3 for 8 banks. All other values are reserved." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7.--9. " ROWSIZE ,Row Size. Defines the number of row address bits of connected SDRAM devices. Set to 0 for 9 row bits, Set to 1 for 10 row bits, Set to 2 for 11 row bits, Set to 3 for 12 row bits, Set to 4 for 13 row bits, Set to 5 for 14 row bits, Set to 6 for 15 row bits, Set to 7 for 16 row bits. This field is only used when EMIF_SDRAM_CONFIG[28:27] IBANK_POS field is set to 1, 2, or 3 or EBANK_POS field in EMIF_SDRAM_CONFIG_2 register is set to 1." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 10.--13. " CL ,CAS Latency (referred to as read latency (RL) in some SDRAM specs). The value of this field defines the CAS latency to be used when accessing connected SDRAM devices. Values of 2, 3, 4 and 5 (CAS latency of 2, 3, 4 and 5) are supported for DDR2. Values of 2, 4, 6, 8, 10, 12 and 14 (CAS latency of 5, 6, 7, 8, 9, 10 and 11) are supported for DDR3. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 14.--15. " NARROW_MODE ,SDRAM data bus width. Set to 0 for 32-bit data bus width. Set to 1 for 16-bit data bus width. All other values are reserved." "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " CWL ,DDR3 CAS Write latency. Value of 0, 1, 2, and 3 (CAS write latency of 5, 6, 7, and 8) are supported. Use the lowest value supported for best performance. All other values are reserved." "0,1,2,3" bitfld.long 0x0 18.--19. " SDRAM_DRIVE ,SDRAM drive strength.For DDR3, set to 0 for RZQ/6 and set to 1 for RZQ/7. All other values are reserved." "0,1,2,3" textline " " bitfld.long 0x0 20. " DDR_DISABLE_DLL ,Disable DLL select. Set to 1 to disable DLL inside SDRAM." "0,1" bitfld.long 0x0 21.--22. " DYN_ODT ,DDR3 Dynamic ODT. NOT SUPPORTED. Set to 0 to turn off dynamic ODT." "0,1,2,3" textline " " bitfld.long 0x0 23. " DDR2_DDQS ,DDR2 differential DDQS enable. NOT SUPPORTED. Set to 1 for compatibility." "0,1" bitfld.long 0x0 24.--26. " DDR_TERM ,DDR3 termination resistor value. Set to 0 to disable termination. For DDR3, set to 1 for RZQ/4, set to 2 for RZQ/2, set to 3 for RZQ/6, set to 4 for RZQ/12, and set to 5 for RZQ/8. All other values are reserved." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--28. " IBANK_POS ,Internal bank position. See , SDRAM Address Mapping." "0,1,2,3" bitfld.long 0x0 29.--31. " SDRAM_TYPE ,SDRAM Type selection. This field is loaded from e-fuse. Set to 2 for DDR2 Set to 3 for DDR3 All other values are reserved." "0,1,2,3,4,5,6,7" group.byte 0xC++0x3 line.long 0x0 "EMIF_SDRAM_CONFIG_2,SDRAM Config Register 2 CAUTION: This register is loaded with values by control module at device reset." hexmask.long 0x0 0.--26. 1. " RESERVED ," bitfld.long 0x0 27. " EBANK_POS ,External bank position. Set to 0 to assign external bank address bits from lower OCP address. Set to 1 to assign external bank address bits from higher OCP address bits. See, SDRAM Address Mapping." "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x10++0x3 line.long 0x0 "EMIF_SDRAM_REFRESH_CONTROL,SDRAM Refresh Control Register" hexmask.long.word 0x0 0.--15. 1. " REFRESH_RATE ,Refresh Rate. Value in this field is used to define the rate at which connected SDRAM devices will be refreshed. SDRAM refresh rate = REFRESH_RATE / EMIF_PHY_FCLK. A 533-MHz DDR clock rate system that requires a 7.8 5s refresh rate would need 7.8 W 533 = 4157 or 0x103D value to be written. To avoid lock-up situations, the programmer must not program REFRESH_RATE < (6 W EMIF_SDRAM_TIMING_3[12:4] T_RFC)." hexmask.long.byte 0x0 16.--23. 1. " RESERVED ," textline " " bitfld.long 0x0 24.--26. " PASR ,Partial Array Self Refresh. These bits get loaded into the Extended Mode Register of DDR3 during initialization. For DDR3, set to 0 for full array, set to 1 or 5 for 1/2 array, set to 2 or 6 for 1/4 array, set to 3 or 7 for 1/8 array, and set to 4 for 3/4 array to be refreshed. All other values are reserved. A write to this field will cause the EMIF to start the SDRAM initialization sequence." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28. " ASR ,DDR3 Auto Self Refresh enable. Set to 1 for auto Self Refresh enable. Set to 0 for manual Self Refresh reference indicated by the SRT field. A write to this field will cause the EMIF to start the SDRAM initialization sequence." "0,1" bitfld.long 0x0 29. " SRT ,DDR3 Self Refresh temperature range. Set to 0 for normal operating temperature range and set to 1 for extended operating temperature range when the ASR field is set to 0. This bit must be set to 0 if the ASR field is set to 1. A write to this field will cause the EMIF to start the SDRAM initialization sequence." "0,1" textline " " bitfld.long 0x0 30. " RESERVED ," "0,1" bitfld.long 0x0 31. " INITREF_DIS ,Initialization and Refresh disable. When set to 1, EMIF will disable SDRAM initialization and refreshes, but will carry out SDRAM write/read transactions." "0,1" group.byte 0x14++0x3 line.long 0x0 "EMIF_SDRAM_REFRESH_CONTROL_SHADOW,SDRAM Refresh Control Shadow Register" hexmask.long.word 0x0 0.--15. 1. " REFRESH_RATE_SHDW ,Shadow field for REFRESH_RATE. This field is loaded intoEMIF_SDRAM_REFRESH_CONTROL[15:0] REFRESH_RATE field when SIdleAck is asserted." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_1,SDRAM Timing 1 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x0 0.--2. " T_WTR ,Minimum number of DDR clock cycles from last Write to Read, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " T_RRD ,Minimum number of DDR clock cycles from Activate to Activate for a different bank, minus one. For an 8-bank, this field must be equal to ((tFAW / (4 W tCK)) - 1)." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6.--11. " T_RC ,Minimum number of DDR clock cycles from Activate to Activate, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12.--16. " T_RAS ,Minimum number of DDR clock cycles from Activate to Precharge, minus one. T_RAS value needs to be bigger than or equal to T_RDC value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--20. " T_WR ,Minimum number of DDR clock cycles from last Write transfer to Precharge, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 21.--24. " T_RCD ,Minimum number of DDR clock cycles from Activate to Read or Write, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 25.--28. " T_RP ,Minimum number of DDR clock cycles from Precharge to Activate or Refresh, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 29.--31. " T_RTW ,Minimum number of DDR clock cycles between Read to Write data phases, minus one." "0,1,2,3,4,5,6,7" group.byte 0x1C++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_1_SHADOW,SDRAM Timing 1 Shadow Register" bitfld.long 0x0 0.--2. " T_WTR_SHDW ,Shadow field for T_WTR. This field is loaded intoEMIF_SDRAM_TIMING_1[2:0] T_WTR field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " T_RRD_SHDW ,Shadow field for T_RRD. This field is loaded intoEMIF_SDRAM_TIMING_1[5:3] T_RRD field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6.--11. " T_RC_SHDW ,Shadow field for T_RC. This field is loaded intoEMIF_SDRAM_TIMING_1[11:6] T_RC field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12.--16. " T_RAS_SHDW ,Shadow field for T_RAS. This field is loaded intoEMIF_SDRAM_TIMING_1[16:12] T_RAS field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 17.--20. " T_WR_SHDW ,Shadow field for T_WR. This field is loaded intoEMIF_SDRAM_TIMING_1[20:17] T_WR field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 21.--24. " T_RCD_SHDW ,Shadow field for T_RCD. This field is loaded intoEMIF_SDRAM_TIMING_1[24:21] T_RCD field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 25.--28. " T_RP_SHDW ,Shadow field for T_RP. This field is loaded intoEMIF_SDRAM_TIMING_1[28:25] T_RP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 29.--31. " T_RTW_SHDW ,Shadow field for T_RTW. This field is loaded intoEMIF_SDRAM_TIMING_1[31:29] T_RTW field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" group.byte 0x20++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_2,SDRAM Timing 2 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x0 0.--2. " T_CKE ,Minimum number of DDR clock cycles between CKE pin changes, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " T_RTP ,Minimum number of DDR clock cycles for the last read command to a Precharge command, minus one." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 6.--15. 1. " T_XSRD ,Minimum number of DDR clock cycles from Self-Refresh exit to a Read command, minus one." hexmask.long.word 0x0 16.--24. 1. " T_XSNR ,Minimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command, minus one." textline " " bitfld.long 0x0 25.--27. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28.--30. " T_XP ,Minimum number of DDR clock cycles from power-down exit to any command other than a read command, minus one." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_2_SHADOW,SDRAM Timing 2 Shadow Register" bitfld.long 0x0 0.--2. " T_CKE_SHDW ,Shadow field for T_CKE. This field is loaded intoEMIF_SDRAM_TIMING_2[2:0] T_CKE field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " T_RTP_SHDW ,Shadow field for T_RTP. This field is loaded intoEMIF_SDRAM_TIMING_2[5:3] T_RTP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 6.--15. 1. " T_XSRD_SHDW ,Shadow field for T_XSRD. This field is loaded intoEMIF_SDRAM_TIMING_2[15:6] T_XSRD field when SIdleAck is asserted." hexmask.long.word 0x0 16.--24. 1. " T_XSNR_SHDW ,Shadow field for T_XSNR. This field is loaded intoEMIF_SDRAM_TIMING_2[24:16] T_XSNR field when SIdleAck is asserted." textline " " bitfld.long 0x0 25.--27. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28.--30. " T_XP_SHDW ,Shadow field for T_XP. This field is loaded intoEMIF_SDRAM_TIMING_2[30:28] T_XP field when SIdleAck is asserted." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x28++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_3,SDRAM Timing 3 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM." bitfld.long 0x0 0.--3. " T_RAS_MAX ,Maximum number of REFRESH_RATE intervals from Activate to Precharge command. This field must be equal to ((tRASmax / tREFI)-1) rounded down to the next lower integer. Value for T_RAS_MAX can be calculated as follows: If tRASmax = 120 us and tREFI = 15.7 us, then T_RAS_MAX = ((120/15.7)-1) = 6.64. Round down to the next lower integer. Therefore, the programmed value must be 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--12. 1. " T_RFC ,Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate, minus one." textline " " bitfld.long 0x0 13.--14. " RESERVED ," "0,1,2,3" bitfld.long 0x0 15.--20. " ZQ_ZQCS ,Number of DDR clock cycles for a ZQCS command, minus one." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 21.--23. " T_CKESR ,Minimum number of DDR clock cycles for which SDRAM must remain in Self Refresh, minus one." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--27. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " T_PDLL_UL ,Minimum number of DDR clock cycles for PHY DLL to unlock. A value of N will be equal to N x 128 clocks." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x2C++0x3 line.long 0x0 "EMIF_SDRAM_TIMING_3_SHADOW,SDRAM Timing 3 Shadow Register" bitfld.long 0x0 0.--3. " T_RAS_MAX_SHDW ,Shadow field for T_RAS_MAX. This field is loaded intoEMIF_SDRAM_TIMING_3[3:0] T_RAS_MAX field when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--12. 1. " T_RFC_SHDW ,Shadow field for T_RFC. This field is loaded intoEMIF_SDRAM_TIMING_3[12:4] T_RFC when SIdleAck is asserted." textline " " bitfld.long 0x0 13.--14. " RESERVED ," "0,1,2,3" bitfld.long 0x0 15.--20. " ZQ_ZQCS_SHDW ,Shadow field for ZQ_ZQCS. This field is loaded into ZQ_ZQCS field inEMIF_SDRAM_TIMING_3 register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 21.--23. " T_CKESR_SHDW ,Shadow field for T_CKESR. This field is loaded into T_CKESR field inEMIF_SDRAM_TIMING_3 register when SIdleAck is asserted." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--27. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28.--31. " T_PDLL_UL_SHDW ,Shadow field for T_PDLL_UL. This field is loaded into T_PDLL_UL field inEMIF_SDRAM_TIMING_3 register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x30++0x3 line.long 0x0 "EMIF_LPDDR2_NVM_TIMING,NOTE: This register is not supported. It is kept only for code compatibility." hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "EMIF_LPDDR2_NVM_TIMING_SHADOW,NOTE: This register is not supported. It is kept only for code compatibility." hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "EMIF_POWER_MANAGEMENT_CONTROL,Power Management Control Register. Updating the *_TIM fields must be followed by at least one access to SDRAM for the new value to take an effect." bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SR_TIM ,Power Management timer for Self Refresh. The EMIF will put the external SDRAM in Self Refresh mode after the EMIF is idle for these number of DDR clock cycles and if LP_MODE field is set to 2. Set to 0 to immediately enter Self Refresh mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--10. " LP_MODE ,Automatic Power Management enable. 0x0: Disable automatic power management 0x1: Reserved 0x2: Self Refresh mode 0x3: Disable automatic power management 0x4: Power-Down mode All other values disable automatic power management." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--15. " PD_TIM ,Power Management timer for Power-Down. The EMIF will put the external SDRAM in Power-Down mode after the EMIF is idle for these number of DDR clock cycles and if LP_MODE field is set to 4. Set to 0 to immediately enter Power-Down mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "EMIF_POWER_MANAGEMENT_CONTROL_SHADOW,Power Management Control Shadow Register" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SR_TIM_SHDW ,Shadow field for SR_TIM. This field is loaded into SR_TIM field inEMIF_POWER_MANAGEMENT_CONTROL register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PD_TIM_SHDW ,Shadow field for PD_TIM. This field is loaded into PD_TIM field inEMIF_POWER_MANAGEMENT_CONTROL register when SIdleAck is asserted." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "EMIF_OCP_CONFIG,OCP Config Register" hexmask.long.tbyte 0x0 0.--19. 1. " RESERVED ," bitfld.long 0x0 20.--23. " MPU_THRESH_MAX ,MPU Threshold Maximum. The number of commands the MPU interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve no space for the associated interface. In the event the value is set to zero and a request is seen for that interface, the command FIFO will assume a value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " SYS_THRESH_MAX ,System OCP Threshold Maximum. The number of commands the system interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve no space for the associated interface. In the event the value is set to zero and a request is seen for that interface, the command FIFO will assume a value of 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x58++0x3 line.long 0x0 "EMIF_OCP_CONFIG_VALUE_1,OCP Config Value 1 Register" hexmask.long.byte 0x0 0.--7. 1. " CMD_FIFO_DEPTH ,Command FIFO depth" hexmask.long.byte 0x0 8.--15. 1. " WR_FIFO_DEPTH ,Write Data FIFO depth" textline " " hexmask.long.word 0x0 16.--29. 1. " RESERVED ," bitfld.long 0x0 30.--31. " SYS_BUS_WIDTH ,System OCP data bus width 0 = 32-bit wide, 1 = 64-bit wide, 2 = 128-bit wide, 3 = Reserved" "0,1,2,3" group.byte 0x5C++0x3 line.long 0x0 "EMIF_OCP_CONFIG_VALUE_2,OCP Config Value 2 Register" hexmask.long.byte 0x0 0.--7. 1. " RCMD_FIFO_DEPTH ,Read Command FIFO depth" hexmask.long.byte 0x0 8.--15. 1. " RSD_FIFO_DEPTH ,SDRAM Read Data FIFO depth" textline " " hexmask.long.byte 0x0 16.--23. 1. " RREG_FIFO_DEPTH ,Register Read Data FIFO depth" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "EMIF_IODFT_TLGC,EMIF_IODFT_TLGC" bitfld.long 0x0 0. " RESERVED ,Reserved. This bit must not be modified." "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Reserved. This field must not be modified." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--5. " RESERVED ,Reserved. This field must not be modified." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 8. " RESERVED ,Reserved. This bit must not be modified." "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 10. " RESET_PHY ,Reset the DDR PHY. Writing 1 to this bit resets the DDR PHY. This bit will self clear to 0." "0,1" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12. " RESERVED ,Reserved. This bit must not be modified." "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved. This bit must not be modified." "0,1" textline " " bitfld.long 0x0 14. " RESERVED ,Reserved. This bit must not be modified." "0,1" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved. This field must not be modified." group.byte 0x80++0x3 line.long 0x0 "EMIF_PERFORMANCE_COUNTER_1,Performance Counter 1 Register" hexmask.long 0x0 0.--31. 1. " COUNTER1 ,32-bit counter that can be configured as specified in theEMIF_PERFORMANCE_COUNTER_CONFIG register and EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT register." group.byte 0x84++0x3 line.long 0x0 "EMIF_PERFORMANCE_COUNTER_2,Performance Counter 2 Register" hexmask.long 0x0 0.--31. 1. " COUNTER2 ,32-bit counter that can be configured as specified in theEMIF_PERFORMANCE_COUNTER_CONFIG register and EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT register." group.byte 0x88++0x3 line.long 0x0 "EMIF_PERFORMANCE_COUNTER_CONFIG,Performance Counter Config Register" bitfld.long 0x0 0.--3. " CNTR1_CFG ,Filter configuration forEMIF_PERFORMANCE_COUNTER_1. Refer to for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--13. 1. " RESERVED ,Reserved for future use" textline " " bitfld.long 0x0 14. " CNTR1_REGION_EN ,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_1 register." "0,1" bitfld.long 0x0 15. " CNTR1_MCONNID_EN ,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_1 register." "0,1" textline " " bitfld.long 0x0 16.--19. " CNTR2_CFG ,Filter configuration forEMIF_PERFORMANCE_COUNTER_2. Refer to for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--29. 1. " RESERVED ,Reserved for future use" textline " " bitfld.long 0x0 30. " CNTR2_REGION_EN ,Chip Select filter enable forEMIF_PERFORMANCE_COUNTER_2 register." "0,1" bitfld.long 0x0 31. " CNTR2_MCONNID_EN ,MConnID filter enable forEMIF_PERFORMANCE_COUNTER_2 register." "0,1" group.byte 0x8C++0x3 line.long 0x0 "EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT,Performance Counter Master Region Select Register The values programmed into the MCONNIDx fields are those in the ConnID Values table in , Interconnect." bitfld.long 0x0 0.--1. " REGION_SEL1 ,MAddrSpace forEMIF_PERFORMANCE_COUNTER_1 register." "0,1,2,3" bitfld.long 0x0 2.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x0 8.--15. 1. " MCONNID1 ,MConnID forEMIF_PERFORMANCE_COUNTER_1 register." bitfld.long 0x0 16.--17. " REGION_SEL2 ,MAddrSpace forEMIF_PERFORMANCE_COUNTER_2 register." "0,1,2,3" textline " " bitfld.long 0x0 18.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x0 24.--31. 1. " MCONNID2 ,MConnID forEMIF_PERFORMANCE_COUNTER_2 register." group.byte 0x90++0x3 line.long 0x0 "EMIF_PERFORMANCE_COUNTER_TIME,Performance Counter Time Register. This is a free running counter." hexmask.long 0x0 0.--31. 1. " TOTAL_TIME ,32-bit counter that continuously counts number for EMIF_FICLK clock cycles elapsed after EMIF is brought out of reset." group.byte 0x94++0x3 line.long 0x0 "EMIF_MISC_REG,EMIF_MISC_REG" bitfld.long 0x0 0. " DLL_CALIB_OS ,Phy_dll_calib one shot : Setting bit to 1 generates a phy_pll_calib pulse. Bit is self cleared when pll_calib gets generated and ack_wait has been satisfied. Software can poll to confirm completion. Uses the EMIF_DLL_CALIB_CTRL[19:16] ACK_WAIT bit field for time to wait after firing off the phy_dll_calib." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "EMIF_DLL_CALIB_CTRL,Control register to force idle window time to generate a phy_dll_calib that can be used for updating PHY DLLs during voltage ramps. NOTE: Should always be loaded via the shadow register." hexmask.long.word 0x0 0.--8. 1. " DLL_CALIB_INTERVAL ,This field determines the interval between phy_dll_calib generation. This value is multiplied by a precounter of 16 EMIF_FICLK cycles. Program this field one less the value you are targeting; program 1 to achieve interval of 2 (minimum interval supported). Programming zero turns off function. Note the final intervals between dll_calib generation is also a function of ACK_WAIT. Final periodic interval is calculated by: ((DLL_CALIB_INTERVAL + 1) W 16) + ACK_WAIT" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--19. " ACK_WAIT ,The ack_wait determines the required wait time after a phy_dll_calib is generated before another command can be sent. Value program is in terms of EMIF_FICLK cycle count. CAUTION: 5 must be the minimum value ever programmed." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "EMIF_DLL_CALIB_CTRL_SHADOW,Read Idle Control Shadow Register" hexmask.long.word 0x0 0.--8. 1. " DLL_CALIB_INTERVAL_SHDW ,Shadow field for DLL_CALIB_INTERVAL. This field is loaded into DLL_CALIB_INTERVAL field in theEMIF_DLL_CALIB_CTRL register when SIdleAck is asserted" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--19. " ACK_WAIT_SHDW ,Shadow field for ACK_WAIT. This field is loaded into ACK_WAIT field inEMIF_DLL_CALIB_CTRL register when SIdleAck is asserted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "EMIF_END_OF_INTERRUPT,EMIF_END_OF_INTERRUPT" bitfld.long 0x0 0. " EOI ,Software End Of Interrupt (EOI) control. Write 0x0 for system OCP interrupt. This field always reads 0 (no EOI memory)." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS,System OCP Interrupt Raw Status Register" bitfld.long 0x0 0. " ERR_SYS ,Raw status of system OCP interrupt for command or address error. Write 1 to set the (raw) status, mostly for debug. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1.--2. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 3. " WR_ECC_ERR_SYS ,Raw status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location." "0,1" bitfld.long 0x0 4. " TWOBIT_ECC_ERR_SYS ,Raw status of system ECC two bit error detection interrupt." "0,1" textline " " bitfld.long 0x0 5. " ONEBIT_ECC_ERR_SYS ,Raw status of system ECC one bit error correction interrupt." "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0xAC++0x3 line.long 0x0 "EMIF_SYSTEM_OCP_INTERRUPT_STATUS,System OCP Interrupt Status Register" bitfld.long 0x0 0. " ERR_SYS ,Enabled status of system OCP interrupt interrupt for command or address error. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x0 1.--2. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 3. " WR_ECC_ERR_SYS ,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect." "0,1" bitfld.long 0x0 4. " TWOBIT_ECC_ERR_SYS ,Enabled status of system ECC two bit error detection interrupt. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 5. " ONEBIT_ECC_ERR_SYS ,Enabled status of system ECC one bit error correction interrupt. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect" "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET,System OCP Interrupt Enable Set Register" bitfld.long 0x0 0. " EN_ERR_SYS ,Enable set for system OCP interrupt for command or address error. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1.--2. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 3. " WR_ECC_ERR_SYS ,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" bitfld.long 0x0 4. " TWOBIT_ECC_ERR_SYS ,Enabled status of system ECC two bit error detection interrupt. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 5. " ONEBIT_ECC_ERR_SYS ,Enabled status of sysem ECC one bit error correction interrupt. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect." "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR,System OCP Interrupt Enable Clear Register" bitfld.long 0x0 0. " EN_ERR_SYS ,Enable clear for system OCP interrupt for command or address error. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1.--2. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 3. " WR_ECC_ERR_SYS ,Enabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" bitfld.long 0x0 4. " TWOBIT_ECC_ERR_SYS ,Enabled status of system ECC two bit error detection interrupt. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 5. " ONEBIT_ECC_ERR_SYS ,Enabled status of system ECC one bit error correction interrupt. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect." "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0xC8++0x3 line.long 0x0 "EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG,SDRAM Output Impedance Calibration Config Register" hexmask.long.word 0x0 0.--15. 1. " ZQ_REFINTERVAL ,Number of refresh periods between ZQCS commands. This field supports between one refresh period to 256 ms between ZQCS calibration commands. Refresh period is defined by REFRESH_RATE inEMIF_SDRAM_REFRESH_CONTROL register." bitfld.long 0x0 16.--17. " ZQ_ZQCL_MULT ,Indicates the number of ZQCS intervals that make up a ZQCL duration, minus one. ZQCS interval is defined by ZQ_ZQCS inEMIF_SDRAM_TIMING_3." "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " ZQ_ZQINIT_MULT ,Indicates the number of ZQCL durations that make up a ZQINIT duration, minus one." "0,1,2,3" hexmask.long.byte 0x0 20.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " ZQ_SFEXITEN ,Writing a 1 enables the issuing of ZQCL on Self-Refresh, Active Power-Down, and Precharge Power-Down exit." "0,1" bitfld.long 0x0 29. " RESERVED ," "0,1" textline " " bitfld.long 0x0 30. " ZQ_CS0EN ,Writing a 1 enables ZQ calibration for CS0." "0,1" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xCC++0x3 line.long 0x0 "EMIF_TEMP_ALERT_CONFIG,Temperature Alert Configuration Register.NOTE: This register is only applicable to LPDDR2 memories and cannot be used in this device." hexmask.long.tbyte 0x0 0.--21. 1. " TA_REFINTERVAL ,Number of refresh periods between temperature alert polls. This field supports between one refresh period to 10 seconds between temperature alert polls. Refresh period is defined by REFRESH_RATE inEMIF_SDRAM_REFRESH_CONTROL register." bitfld.long 0x0 22.--23. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 24.--25. " TA_DEVCNT ,This field indicates which external byte lanes contain a device for temperature monitoring. A value of 0: one device, 1: two devices, 2: four devices. All other reserved." "0,1,2,3" bitfld.long 0x0 26.--27. " TA_DEVWDT ,This field indicates how wide a physical device is. It is used in conjunction with the TA_DEVCNT field to determine which byte lanes contain the temperature alert info. A value of 0: 8-bit wide, 1: 16-bit wide, 2: 32-bit wide. All others are reserved. If this field is set to 1 and the TA_DEVCNT field is set to 1 the byte mask for checking is 4'b0101." "0,1,2,3" textline " " bitfld.long 0x0 28. " TA_SFEXITEN ,Temperature Alert Poll on Self-Refresh, Active Power-Down, and Precharge Power-Down exit enable. Writing 1 enables the issuing of a temperature alert poll on Self-Refresh exit." "0,1" bitfld.long 0x0 29. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 30. " TA_CS0EN ,Writing 1 enables temperature alert polling for CS0." "0,1" bitfld.long 0x0 31. " TA_CS1EN ,Writing 1 enables temperature alert polling for CS1." "0,1" group.byte 0xD0++0x3 line.long 0x0 "EMIF_OCP_ERROR_LOG,OCP Error Log Register. This register is overwritten by any first error transaction once after the interrupt is serviced and cleared by writing 0x1 to the[0] ERR_SYS bit." hexmask.long.byte 0x0 0.--7. 1. " MCONNID ,Connection ID of the first errored transaction." bitfld.long 0x0 8.--10. " MCMD ,Command type of the first errored transaction. (see, L3_MAIN Interconnect for more information)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--13. " MBURSTSEQ ,Addressing mode of the first errored transaction. (see, L3_MAIN Interconnect for more information)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " MADDRSPACE ,Address space of the first errored transaction. 0x0: SDRAM 0x1: reserved 0x2: reserved 0x3: internal registers" "0,1,2,3" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved for future use." group.byte 0xD4++0x3 line.long 0x0 "EMIF_READ_WRITE_LEVELING_RAMP_WINDOW,Read/write leveling ramp window register" hexmask.long.word 0x0 0.--12. 1. " RDWRLVLINC_RMP_WIN ,Incremental leveling ramp window in number of refresh periods. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE inEMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device." hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xD8++0x3 line.long 0x0 "EMIF_READ_WRITE_LEVELING_RAMP_CONTROL,Read/write leveling ramp control register" hexmask.long.byte 0x0 0.--7. 1. " WRLVLINC_RMP_INT ,Incremental write leveling interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental write leveling during ramp window. A value of 0 will disable incremental write leveling.NOTE: Incremental leveling is not supported on this device." hexmask.long.byte 0x0 8.--15. 1. " RDLVLGATEINC_RMP_INT ,Incremental read DQS gate training interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental read DQS gate training during ramp window. A value of 0 will disable incremental read DQS gate training.NOTE: Incremental leveling is not supported on this device." textline " " hexmask.long.byte 0x0 16.--23. 1. " RDLVLINC_RMP_INT ,Incremental read data eye training interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental read data eye training during ramp window. A value of 0 will disable incremental read data eye training.NOTE: Incremental leveling is not supported on this device." hexmask.long.byte 0x0 24.--30. 1. " RDWRLVLINC_RMP_PRE ,Incremental leveling pre-scalar in number of refresh periods during ramp window. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE inEMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device." textline " " bitfld.long 0x0 31. " RDWRLVL_EN ,Read-Write Leveling enable. Set 1 to enable leveling. Set 0 to disable leveling." "0,1" group.byte 0xDC++0x3 line.long 0x0 "EMIF_READ_WRITE_LEVELING_CONTROL,Read/write leveling control register" hexmask.long.byte 0x0 0.--7. 1. " WRLVLINC_INT ,Incremental write leveling interval. Number of RDWRLVLINC_PRE intervals between incremental write leveling. A value of 0 will disable incremental write leveling.NOTE: Incremental leveling is not supported on this device." hexmask.long.byte 0x0 8.--15. 1. " RDLVLGATEINC_INT ,Incremental read DQS gate training interval. Number of RDWRLVLINC_PRE intervals between incremental read DQS gate training. A value of 0 will disable incremental read DQS gate training.NOTE: Incremental leveling is not supported on this device." textline " " hexmask.long.byte 0x0 16.--23. 1. " RDLVLINC_INT ,Incremental read data eye training interval. Number of RDWRLVLINC_PRE intervals between incremental read data eye training. A value of 0 will disable incremental read data eye training.NOTE: Incremental leveling is not supported on this device." hexmask.long.byte 0x0 24.--30. 1. " RDWRLVLINC_PRE ,Incremental leveling pre-scalar in number of refresh periods. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE inEMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device." textline " " bitfld.long 0x0 31. " RDWRLVLFULL_START ,Full leveling trigger. Writing a 1 to this field triggers full read and write leveling. This bit will self clear to 0." "0,1" group.byte 0xE4++0x3 line.long 0x0 "EMIF_DDR_PHY_CONTROL_1,PHY control register 1" bitfld.long 0x0 0.--4. " READ_LATENCY ,This field defines the read latency for the read data from SDRAM in number of DDR clock cycles. This field is used by the EMIF as well as the PHY. READ_LATENCY = RL + reg_phy_rdc_we_to_re -1. EMIF uses above equation to calculate reg_phy_rdc_we_to_re and forward it to the PHY. For DDR3, the true RL is used, not the decoded value. See JEDEC spec." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " PHY_FAST_DLL_LOCK ,Controls master DLL to lock fast or average logic must be part of locking process. Set to 1 before OPP transition commences, and set back to 0 after OPP transition completes. 1: MDLL lock is asserted based on single sample 0: MDLL lock is asserted based on average of 16 samples." "0,1" hexmask.long.byte 0x0 10.--17. 1. " PHY_DLL_LOCK_DIFF ,The maximum number of delay line taps variation while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by this field, the lock signal is de-asserted and a dll_calib signal is generated. To prevent the dll_calib signal from being asserted in the middle of traffic when the clock jitter exceeds the variation, this register needs to be set to a value which will ensure that the lock will not be lost. Recommended value is 16." textline " " bitfld.long 0x0 18. " PHY_INVERT_CLKOUT ,Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM" "0,1" bitfld.long 0x0 19. " PHY_DIS_CALIB_RST ,Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of data PHYs. Debug only. Note: dll_calib is generated by 1. EMIF_MISC_REG[0] DLL_CALIB_OS set to 1,or 2. by the PHY when it detects that the clock frequency variation has exceeded the bounds set by PHY_DLL_LOCK_DIFF or 3. periodically throughout the leveling process." "0,1" textline " " bitfld.long 0x0 20. " PHY_CLK_STALL_LEVEL ,Enable variable idle value for delay lines. Enable during normal operations to avoid differential aging in the delay lines." "0,1" bitfld.long 0x0 21. " PHY_HALF_DELAYS ,Adjust slave delay line delays to support 2W mode 1: 2W mode (MDLL clock is half the rate of PHY) 0: 1W mode (MDLL clock rate is same as PHY)" "0,1" textline " " bitfld.long 0x0 22.--24. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 25. " WRLVL_MASK ,Writing a 1 to this field will mask write leveling training during full leveling command, plus drives reg_phy_use_wr_level control low to allow user to use programmed ratio values." "0,1" textline " " bitfld.long 0x0 26. " RDLVLGATE_MASK ,Writing a 1 to this field will mask dqs gate training during full leveling command, plus drives reg_phy_use_rd_dqs_level control low to allow user to use programmed ratio values." "0,1" bitfld.long 0x0 27. " RDLVL_MASK ,Writing a 1 to this field will mask read data eye training during full leveling command, plus drives reg_phy_use_rd_data_eye_level control low to allow user to use programmed ratio values." "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xE8++0x3 line.long 0x0 "EMIF_DDR_PHY_CONTROL_1_SHADOW,EMIF_DDR_PHY_CONTROL_1_SHADOW" bitfld.long 0x0 0.--4. " READ_LATENCY_SHDW ,Shadow field for READ_LATENCY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " PHY_FAST_DLL_SHDW ,Shadow field for PHY_FAST_DLL" "0,1" hexmask.long.byte 0x0 10.--17. 1. " PHY_DLL_LOCK_DIFF_SHDW ,Shadow field for PHY_DLL_LOCK_DIFF" textline " " bitfld.long 0x0 18. " PHY_INVERT_CLKOUT_SHDW ,Shadow field for PHY_INVERT_CLKOUT" "0,1" bitfld.long 0x0 19. " PHY_DIS_CALIB_RST_SHDW ,Shadow field for PHY_DIS_CALIB_RST" "0,1" textline " " bitfld.long 0x0 20. " PHY_CLK_STALL_LEVEL_SHDW ,Shadow field for PHY_CLK_STALL_LEVEL" "0,1" bitfld.long 0x0 21. " PHY_HALF_DELAYS_SHDW ,Shadow field for PHY_HALF_DELAYS" "0,1" textline " " bitfld.long 0x0 22.--24. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 25. " WRLVL_MASK_SHDW ,Shadow field for WRLVL_MASK" "0,1" textline " " bitfld.long 0x0 26. " RDLVLGATE_MASK_SHDW ,Shadow field for RDLVLGATE_MASK" "0,1" bitfld.long 0x0 27. " RDLVL_MASK_SHDW ,Shadow field for RDLVL_MASK" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xEC++0x3 line.long 0x0 "EMIF_DDR_PHY_CONTROL_2,EMIF_DDR_PHY_CONTROL_2" hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING,EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING" bitfld.long 0x0 0.--1. " PRI_0_COS ,Class of service for commands with priority of 0. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" bitfld.long 0x0 2.--3. " PRI_1_COS ,Class of service for commands with priority of 1. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " PRI_2_COS ,Class of service for commands with priority of 2. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" bitfld.long 0x0 6.--7. " PRI_3_COS ,Class of service for commands with priority of 3. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " PRI_4_COS ,Class of service for commands with priority of 4. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" bitfld.long 0x0 10.--11. " PRI_5_COS ,Class of service for commands with priority of 5. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " PRI_6_COS ,Class of service for commands with priority of 6. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" bitfld.long 0x0 14.--15. " PRI_7_COS ,Class of service for commands with priority of 7. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--30. 1. " RESERVED ," bitfld.long 0x0 31. " PRI_COS_MAP_EN ,Set 1 to enable priority to class of service mapping. Set 0 to disable mapping." "0,1" group.byte 0x104++0x3 line.long 0x0 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING,EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING" bitfld.long 0x0 0.--1. " MSK_3_COS_1 ,Mask for Connection ID value 3 for class of service 1. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0." "0,1,2,3" hexmask.long.byte 0x0 2.--9. 1. " CONNID_3_COS_1 ,Connection ID value 3 for class of service 1." textline " " bitfld.long 0x0 10.--11. " MSK_2_COS_1 ,Mask for Connection ID value 2 for class of service 1. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0." "0,1,2,3" hexmask.long.byte 0x0 12.--19. 1. " CONNID_2_COS_1 ,Connection ID value 2 for class of service 1." textline " " bitfld.long 0x0 20.--22. " MSK_1_COS_1 ,Mask for Connection ID value 1 for class of service 1. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0. Value of 4 will mask Connection ID bits 3:0. Value of 5 will mask Connection ID bits 4:0. Value of 6 will mask Connection ID bits 5:0. Value of 7 will mask Connection ID bits 6:0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 23.--30. 1. " CONNID_1_COS_1 ,Connection ID value 1 for class of service 1." textline " " bitfld.long 0x0 31. " CONNID_COS_1_MAP_EN ,Set 1 to enable Connection ID to class of service 1 mapping. Set 0 to disable mapping." "0,1" group.byte 0x108++0x3 line.long 0x0 "EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING,EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING" bitfld.long 0x0 0.--1. " MSK_3_COS_2 ,Mask for Connection ID value 3 for class of service 2. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0." "0,1,2,3" hexmask.long.byte 0x0 2.--9. 1. " CONNID_3_COS_2 ,Connection ID value 3 for class of service 2." textline " " bitfld.long 0x0 10.--11. " MSK_2_COS_2 ,Mask for Connection ID value 2 for class of service 2. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0." "0,1,2,3" hexmask.long.byte 0x0 12.--19. 1. " CONNID_2_COS_2 ,Connection ID value 2 for class of service 2." textline " " bitfld.long 0x0 20.--22. " MSK_1_COS_2 ,Mask for Connection ID value 1 for class of service 2. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0. Value of 4 will mask Connection ID bits 3:0. Value of 5 will mask Connection ID bits 4:0. Value of 6 will mask Connection ID bits 5:0. Value of 7 will mask Connection ID bits 6:0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 23.--30. 1. " CONNID_1_COS_2 ,Connection ID value 1 for class of service 2." textline " " bitfld.long 0x0 31. " CONNID_COS_2_MAP_EN ,Set 1 to enable Connection ID to class of service 2 mapping. Set 0 to disable mapping." "0,1" group.byte 0x120++0x3 line.long 0x0 "EMIF_READ_WRITE_EXECUTION_THRESHOLD,EMIF_READ_WRITE_EXECUTION_THRESHOLD" bitfld.long 0x0 0.--4. " RD_THRSH ,Read threshold. Number of SDRAM read bursts after which the EMIF arbitration will switch to executing write commands. The value that is programmed is always minus one the required number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " WR_THRSH ,Write Threshold. Number of SDRAM write bursts after which the EMIF arbitration will switch to executing read commands. The value programmed is always minus one the required number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x0 13.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " MFLAG_OVERRIDE ,Mflag override." "0,1" group.byte 0x124++0x3 line.long 0x0 "EMIF_COS_CONFIG,Priority Raise Counter Register." hexmask.long.byte 0x0 0.--7. 1. " PR_OLD_COUNT ,Priority Raise Old Counter. Number of EMIF_FICLK cycles after which the EMIF momentarily raises the priority of the oldest command in the Command FIFO. A value of N will be equal to N x 16 clocks." hexmask.long.byte 0x0 8.--15. 1. " COS_COUNT_2 ,Priority Raise Counter for class of service 2. Number of EMIF_FICLK cycles after which the EMIF momentarily raises the priority of the class of service 2 commands in the Command FIFO. A value of N will be equal to N x 16 clocks." textline " " hexmask.long.byte 0x0 16.--23. 1. " COS_COUNT_1 ,Priority Raise Counter for class of service 1. Number of EMIF_FICLK cycles after which the EMIF momentarily raises the priority of the class of service 1 commands in the Command FIFO. A value of N will be equal to N x 16 clocks." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x144++0x3 line.long 0x0 "EMIF_PHY_STATUS_1,EMIF_PHY_STATUS_1" bitfld.long 0x0 0.--1. " PHY_REG_PHY_CTRL_DLL_LOCK ,Lock Status for Command DLLs" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--8. " PHY_REG_STATUS_DLL_LOCK ,Lock Status for Data DLLs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 12.--29. 1. " PHY_REG_PHY_CTRL_DLL_SLAVE_VALUE ,DLL Slave Value" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x148++0x3 line.long 0x0 "EMIF_PHY_STATUS_2,EMIF_PHY_STATUS_2" hexmask.long 0x0 0.--31. 1. " PHY_REG_STATUS_DLL_SLAVE_VALUE_LO ,Bits 31:0 of Phy_reg_status_dll_slave_value" group.byte 0x14C++0x3 line.long 0x0 "EMIF_PHY_STATUS_3,EMIF_PHY_STATUS_3" hexmask.long.word 0x0 0.--12. 1. " PHY_REG_STATUS_DLL_SLAVE_VALUE_HI ,Bits 44:32 of Phy_reg_status_dll_slave_value" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 16.--30. 1. " PHY_REG_RDFIFO_RDPTR ,Read FIFO Read Pointer" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x150++0x3 line.long 0x0 "EMIF_PHY_STATUS_4,EMIF_PHY_STATUS_4" hexmask.long.word 0x0 0.--14. 1. " PHY_REG_RDFIFO_WRPTR ,Read FIFO Write Pointer" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.word 0x0 16.--30. 1. " PHY_REG_GATELVL_FSM ,Gate Leveling FSM" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x154++0x3 line.long 0x0 "EMIF_PHY_STATUS_5,EMIF_PHY_STATUS_5" hexmask.long.tbyte 0x0 0.--19. 1. " PHY_REG_RD_LEVEL_FSM ,Read Leveling FSM" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x158++0x3 line.long 0x0 "EMIF_PHY_STATUS_6,EMIF_PHY_STATUS_6" hexmask.long.word 0x0 0.--14. 1. " PHY_REG_WR_LEVEL_FSM ,Write Leveling FSM" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x15C++0x3 line.long 0x0 "EMIF_PHY_STATUS_7,EMIF_PHY_STATUS_7" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO0 ,Read leveling DQS ratio0" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO1 ,Read leveling DQS ratio1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x160++0x3 line.long 0x0 "EMIF_PHY_STATUS_8,EMIF_PHY_STATUS_8" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO2 ,Read leveling DQS ratio2" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO3 ,Read leveling DQS ratio3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x164++0x3 line.long 0x0 "EMIF_PHY_STATUS_9,EMIF_PHY_STATUS_9" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO4 ,Read Leveling DQS ratio4" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO5 ,Read Leveling DQS ratio5" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x168++0x3 line.long 0x0 "EMIF_PHY_STATUS_10,EMIF_PHY_STATUS_10" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RDLVL_DQS_RATIO6 ,Read leveling DQS ratio6" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RDLVL_DQS_RATIO7 ,Read leveling DQS ratio7" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x170++0x3 line.long 0x0 "EMIF_PHY_STATUS_12,EMIF_PHY_STATUS_12" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO0 ,Read leveling FIFO Write Enable Ratio0" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO1 ,Read leveling FIFO Write Enable Ratio1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x174++0x3 line.long 0x0 "EMIF_PHY_STATUS_13,EMIF_PHY_STATUS_13" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO2 ,Read leveling FIFO Write Enable Ratio2" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO3 ,Read leveling FIFO Write Enable Ratio3" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x178++0x3 line.long 0x0 "EMIF_PHY_STATUS_14,EMIF_PHY_STATUS_14" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO4 ,Read leveling FIFO Write Enable Ratio4" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO5 ,Read leveling FIFO Write Enable Ratio5" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x17C++0x3 line.long 0x0 "EMIF_PHY_STATUS_15,EMIF_PHY_STATUS_15" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO6 ,Read leveling FIFO Wrie Enable Ratio6" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_RDLVL_FIFOWEIN_RATIO7 ,Read leveling FIFO Wrie Enable Ratio7" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x184++0x3 line.long 0x0 "EMIF_PHY_STATUS_17,EMIF_PHY_STATUS_17" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO0 ,Write leveling DQ ratio0" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO1 ,Write leveling DQ ratio1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x188++0x3 line.long 0x0 "EMIF_PHY_STATUS_18,EMIF_PHY_STATUS_18" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO2 ,Write leveling DQ ratio2" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO3 ,Write leveling DQ ratio3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x18C++0x3 line.long 0x0 "EMIF_PHY_STATUS_19,EMIF_PHY_STATUS_19" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO4 ,Write leveling DQ ratio4" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO5 ,Write leveling DQ ratio5" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x190++0x3 line.long 0x0 "EMIF_PHY_STATUS_20,EMIF_PHY_STATUS_20" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQ_RATIO6 ,Write leveling DQ ratio6" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQ_RATIO7 ,Write leveling DQ ratio7" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x198++0x3 line.long 0x0 "EMIF_PHY_STATUS_22,EMIF_PHY_STATUS_22" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO0 ,Write leveling DQS ratio 0" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO1 ,Write leveling DQS ratio 1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x19C++0x3 line.long 0x0 "EMIF_PHY_STATUS_23,EMIF_PHY_STATUS_23" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO2 ,Write leveling DQS ratio2" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO3 ,Write leveling DQS ratio3" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1A0++0x3 line.long 0x0 "EMIF_PHY_STATUS_24,EMIF_PHY_STATUS_24" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO4 ,Write leveling DQS ratio4" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO5 ,Write leveling DQS ratio5" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1A4++0x3 line.long 0x0 "EMIF_PHY_STATUS_25,EMIF_PHY_STATUS_25" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WRLVL_DQS_RATIO6 ,Write leveling DQS ratio6" bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WRLVL_DQS_RATIO7 ,Write leveling DQS ratio7" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1AC++0x3 line.long 0x0 "EMIF_PHY_STATUS_27,EMIF_PHY_STATUS_27" hexmask.long.tbyte 0x0 0.--19. 1. " PHY_REG_RDC_FIFO_RST_ERR_CNT ,RDC FIFO reset error count" bitfld.long 0x0 20.--24. " PHY_REG_STATUS_MDLL_UNLOCK_STICKY ,Phy data MDLL unlock sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25.--27. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 28.--29. " PHY_REG_PHY_CONTROL_MDLL_UNLOCK_STICKY ,Phy control MDLL unlock sticky" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x1B0++0x3 line.long 0x0 "EMIF_PHY_STATUS_28,EMIF_PHY_STATUS_28" bitfld.long 0x0 0.--4. " PHY_REG_FIFO_WE_IN_MIASALIGNED_STICKY ,FIFO write enable in misaligned sticky" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " PHY_REG_RDLVL_INC_FAIL ,Read leveling failure.NOTE: Incremental leveling is not supported on this device." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " PHY_REG_WRLVL_INC_FAIL ,Write leveling failure.NOTE: Incremental leveling is not supported on this device." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " PHY_REG_GATELVL_INC_FAIL ,Gate leveling failure.NOTE: Incremental leveling is not supported on this device." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x200++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_1,Control DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_CTRL_SLAVE_RATIO0 ,The user programmable ratio value for address/command launch timing in PHY control macro 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Set to:" hexmask.long.word 0x0 10.--19. 1. " PHY_REG_CTRL_SLAVE_RATIO1 ,The user programmable ratio value for address/command launch timing in PHY control macro 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Set to:" textline " " hexmask.long.word 0x0 20.--29. 1. " PHY_REG_CTRL_SLAVE_RATIO2 ,The user programmable ratio value for address/command launch timing in PHY control macro 2. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x204++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_1_SHADOW,Control DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_CTRL_SLAVE_RATIO0 ,The user programmable ratio value for address/command launch timing in PHY control macro 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Set to:" hexmask.long.word 0x0 10.--19. 1. " PHY_REG_CTRL_SLAVE_RATIO1 ,The user programmable ratio value for address/command launch timing in PHY control macro 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Set to:" textline " " hexmask.long.word 0x0 20.--29. 1. " PHY_REG_CTRL_SLAVE_RATIO2 ,The user programmable ratio value for address/command launch timing in PHY control macro 2. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x208++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_2,Data macro 0, FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO0 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO1 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x20C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_2_SHADOW,Data macro 0, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO0 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO1 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x210++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_3,Data macro 1, FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO2 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO3 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x214++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_3_SHADOW,Data macro 1, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO2 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO3 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x218++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_4,Data macro 2, FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO4 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO5 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x21C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_4_SHADOW,Data macro 2, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO4 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO5 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x220++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_5,Data macro 3, FIFO write enable (read DQS gate) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO6 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO7 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x224++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_5_SHADOW,Data macro 3, FIFO write enable (read DQS gate) DLL Slave Ratio Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO6 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " PHY_REG_FIFO_WE_SLAVE_RATIO7 ,The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x230++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_7,Data macro 0, read DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO0 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO1 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x234++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_7_SHADOW,Data macro 0, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO0 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO1 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x238++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_8,Data macro 1, read DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO2 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO3 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x23C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_8_SHADOW,Data macro 1, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO2 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO3 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x240++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_9,Data macro 2, read DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO4 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO5 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x244++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_9_SHADOW,Data macro 2, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO4 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO5 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x248++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_10,Data macro 3, read DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO6 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO7 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x24C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_10_SHADOW,Data macro 3, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_RD_DQS_SLAVE_RATIO6 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_RD_DQS_SLAVE_RATIO7 ,The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x258++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_12,Data macro 0, write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO0 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO1 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x25C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_12_SHADOW,Data macro 0, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO0 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO1 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x260++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_13,Data macro 1, write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO2 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO3 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x264++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_13_SHADOW,Data macro 1, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO2 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO3 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x268++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_14,Data macro 2, write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO4 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO5 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x26C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_14_SHADOW,Data macro 2, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO4 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO5 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x270++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_15,Data macro 3, write DQ (data) DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO6 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO7 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x274++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_15_SHADOW,Data macro 3, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DATA_SLAVE_RATIO6 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DATA_SLAVE_RATIO7 ,The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x280++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_17,Data macro 0, write DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO0 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO1 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x284++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_17_SHADOW,Data macro 0, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO0 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO1 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x288++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_18,Data macro 1, write DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO2 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO3 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x28C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_18_SHADOW,Data macro 1, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO2 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO3 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x290++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_19,Data macro 2, write DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO4 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO5 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x294++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_19_SHADOW,Data macro 2, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO4 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO5 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x298++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_20,Data macro 3, write DQS DLL Slave Ratio Register" hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO6 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO7 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x29C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_20_SHADOW,Data macro 3, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " PHY_REG_WR_DQS_SLAVE_RATIO6 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " PHY_REG_WR_DQS_SLAVE_RATIO7 ,The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x2A8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_22,EMIF_EXT_PHY_CONTROL_22" hexmask.long.word 0x0 0.--8. 1. " PHY_REG_CTRL_SLAVE_DELAY ,The user programmable command delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PHY_REG_FIFO_WE_IN_DELAY ,The user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x2AC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_22_SHADOW,EMIF_EXT_PHY_CONTROL_22_SHADOW" hexmask.long.word 0x0 0.--8. 1. " PHY_REG_CTRL_SLAVE_DELAY ,The user programmable command delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PHY_REG_FIFO_WE_IN_DELAY ,The user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x2B0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_23,EMIF_EXT_PHY_CONTROL_23" hexmask.long.word 0x0 0.--8. 1. " PHY_REG_RD_DQS_SLAVE_DELAY ,The user programmable read DQS delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PHY_REG_WR_DQS_SLAVE_DELAY ,The user programmable write DQS delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x2B4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_23_SHADOW,EMIF_EXT_PHY_CONTROL_23_SHADOW" hexmask.long.word 0x0 0.--8. 1. " PHY_REG_RD_DQS_SLAVE_DELAY ,The user programmable read DQS delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PHY_REG_WR_DQS_SLAVE_DELAY ,The user programmable write DQS delay value used when DLL_OVERRIDE = 1." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x2B8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_24,EMIF_EXT_PHY_CONTROL_24" hexmask.long.word 0x0 0.--8. 1. " REG_PHY_WR_DATA_SLAVE_DELAY ,The user programmable write DQ delay value used when DLL_OVERRIDE = 1." bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12. " REG_PHY_USE_RANK0_DELAYS ,Delay selection. Chip select 0 delay line ratios are used for all chip selects when set to 1. Each chip select uses its own delays when set to 0." "0,1" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " REG_PHY_GATELVL_INIT_MODE ,The user programmable init ratio selection mode. Recommended value is 0x1." "0,1" hexmask.long.byte 0x0 17.--23. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 24.--30. 1. " REG_PHY_DQ_OFFSET_HI ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY ECC data macro. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x2BC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_24_SHADOW,EMIF_EXT_PHY_CONTROL_24_SHADOW" hexmask.long.word 0x0 0.--8. 1. " REG_PHY_WR_DATA_SLAVE_DELAY ,The user programmable write DQ delay value used when DLL_OVERRIDE = 1." bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12. " REG_PHY_USE_RANK0_DELAYS ,Delay selection. Chip select 0 delay line ratios are used for all chip selects when set to 1. Each chip select uses its own delays when set to 0." "0,1" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " REG_PHY_GATELVL_INIT_MODE ,The user programmable init ratio selection mode. Recommended value is 0x1." "0,1" hexmask.long.byte 0x0 17.--23. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 24.--30. 1. " REG_PHY_DQ_OFFSET_HI ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY ECC data macro. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x2C0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_25,DQ DLL Slave Ratio Offset Register" hexmask.long.byte 0x0 0.--6. 1. " REG_PHY_DQ_OFFSET0 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 0. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." hexmask.long.byte 0x0 7.--13. 1. " REG_PHY_DQ_OFFSET1 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 1. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." textline " " hexmask.long.byte 0x0 14.--20. 1. " REG_PHY_DQ_OFFSET2 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 2. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." hexmask.long.byte 0x0 21.--27. 1. " REG_PHY_DQ_OFFSET3 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 3. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x2C4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_25_SHADOW,DQ DLL Slave Ratio Offset Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.byte 0x0 0.--6. 1. " REG_PHY_DQ_OFFSET0 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 0. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." hexmask.long.byte 0x0 7.--13. 1. " REG_PHY_DQ_OFFSET1 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 1. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." textline " " hexmask.long.byte 0x0 14.--20. 1. " REG_PHY_DQ_OFFSET2 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 2. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." hexmask.long.byte 0x0 21.--27. 1. " REG_PHY_DQ_OFFSET3 ,The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 3. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line." textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x2C8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_26,Data macro 0, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO0 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO1 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2CC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_26_SHADOW,Data macro 0, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO0 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO1 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2D0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_27,Data macro 1, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO2 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO3 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2D4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_27_SHADOW,Data macro 1, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO2 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO3 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2D8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_28,Data macro 2, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO4 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO5 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2DC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_28_SHADOW,Data macro 2, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO4 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO5 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2E0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_29,Data macro 3, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO6 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO7 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2E4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_29_SHADOW,Data macro 3, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--10. 1. " REG_PHY_GATELVL_INIT_RATIO6 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--26. 1. " REG_PHY_GATELVL_INIT_RATIO7 ,The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2F0++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_31,Data macro 0, write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO0 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO1 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x2F4++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_31_SHADOW,Data macro 0, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO0 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO1 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x2F8++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_32,Data macro 1, write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO2 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO3 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x2FC++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_32_SHADOW,Data macro 1, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO2 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO3 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x300++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_33,Data macro 2, write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO4 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO5 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x304++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_33_SHADOW,Data macro 2, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO4 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO5 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x308++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_34,Data macro 3, write DQS DLL Slave Init Ratio Register" hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO6 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO7 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x30C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_34_SHADOW,Data macro 3, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register on any frequency change." hexmask.long.word 0x0 0.--9. 1. " REG_PHY_WRLVL_INIT_RATIO6 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " REG_PHY_WRLVL_INIT_RATIO7 ,The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. NOTE: Chip select 1 is not supported on this device." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x318++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_36,EMIF_EXT_PHY_CONTROL_36" bitfld.long 0x0 0.--3. " REG_PHY_GATELVL_NUM_OF_DQ0 ,Determines the number of samples fordq0_in for each ratio increment by the gate training finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " REG_PHY_WRLVL_NUM_OF_DQ0 ,Determines the number of samples fordq0_in for each ratio increment by the write leveling finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " REG_PHY_FIFO_WE_IN_MISALIGNED_CLR ,Clears the phy_reg_fifo_we_in_misaligned_sticky status flag. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" bitfld.long 0x0 9. " REG_PHY_MDLL_UNLOCK_CLR ,Clears the phy_reg_status_mdll_unlock_sticky flag. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" textline " " bitfld.long 0x0 10. " REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset the phy_reg_rdc_fifo_rst_err_cnt, phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x31C++0x3 line.long 0x0 "EMIF_EXT_PHY_CONTROL_36_SHADOW,EMIF_EXT_PHY_CONTROL_36_SHADOW" bitfld.long 0x0 0.--3. " REG_PHY_GATELVL_NUM_OF_DQ0 ,Determines the number of samples fordq0_in for each ratio increment by the gate training finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " REG_PHY_WRLVL_NUM_OF_DQ0 ,Determines the number of samples fordq0_in for each ratio increment by the write leveling finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " REG_PHY_FIFO_WE_IN_MISALIGNED_CLR ,Clears the phy_reg_fifo_we_in_misaligned_sticky status flag. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" bitfld.long 0x0 9. " REG_PHY_MDLL_UNLOCK_CLR ,Clears the phy_reg_status_mdll_unlock_sticky flag. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" textline " " bitfld.long 0x0 10. " REG_PHY_RDC_FIFO_RST_ERR_CNT_CLR ,Clear/reset the phy_reg_rdc_fifo_rst_err_cnt, phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags. A value of 0x1 clears the flag. A value of 0x0 has no effect." "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," width 0x0B tree.end tree "GPMC" base ad:0x50000000 width 23. group.byte 0x0++0x3 line.long 0x0 "GPMC_REVISION,This register contains the IP revision code." hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "GPMC_SYSCONFIG,This register controls the various parameters of the interconnect." bitfld.long 0x0 0. " AUTOIDLE ,Internal interface clock-gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 triggers a module reset. This bit is automatically reset by hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0 for future compatibility Read returns 0." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,0x0: Force-idle. An idle request is acknowledged unconditionally." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0." group.byte 0x14++0x3 line.long 0x0 "GPMC_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information." bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0 (reserved for interconnect-socket status information)." textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "GPMC_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " FIFOEVENTSTATUS ,Status of the FIFOEvent interrupt" "0,1" bitfld.long 0x0 1. " TERMINALCOUNTSTATUS ,Status of the TerminalCountEvent interrupt" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " WAIT0EDGEDETECTIONSTATUS ,Status of the Wait0 Edge Detection interrupt" "0,1" textline " " bitfld.long 0x0 9. " WAIT1EDGEDETECTIONSTATUS ,Status of the Wait1 Edge Detection interrupt" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x1C++0x3 line.long 0x0 "GPMC_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " FIFOEVENTENABLE ,Enables the FIFOEvent interrupt" "0,1" bitfld.long 0x0 1. " TERMINALCOUNTEVENTENABLE ,Enables TerminalCountEvent interrupt issuing in prefetch or write-posting mode" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " WAIT0EDGEDETECTIONENABLE ,Enables the Wait0 Edge Detection interrupt" "0,1" textline " " bitfld.long 0x0 9. " WAIT1EDGEDETECTIONENABLE ,Enables the Wait1 Edge Detection interrupt" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x40++0x3 line.long 0x0 "GPMC_TIMEOUT_CONTROL,The register allows the user to set the start value of the timeout counter." bitfld.long 0x0 0. " TIMEOUTENABLE ,Enable bit of the TimeOut feature" "0,1" bitfld.long 0x0 1.--3. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 4.--12. 1. " TIMEOUTSTARTVALUE ,Start value of the time-out counter 0x000: Zero GPMC_FCLK cycle 0x001: One GPMC_FCLK cycle ... 0x1FF: 511 GPMC_FCLK cycles" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x44++0x3 line.long 0x0 "GPMC_ERR_ADDRESS,The register stores the address of the illegal access when an error occurs." hexmask.long 0x0 0.--30. 1. " ILLEGALADD ,Address of illegal access A30: 0 for memory region, 1 for GPMC register region A29-A0: 1 GiB maximum" bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x48++0x3 line.long 0x0 "GPMC_ERR_TYPE,The register stores the type of error when an error occurs." bitfld.long 0x0 0. " ERRORVALID ,Error validity status - Must be explicitly cleared with a write 1 transaction" "0,1" bitfld.long 0x0 1. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 2. " ERRORTIMEOUT ,Time-out error" "0,1" bitfld.long 0x0 3. " ERRORNOTSUPPMCMD ,Not supported command error" "0,1" textline " " bitfld.long 0x0 4. " ERRORNOTSUPPADD ,Not supported address error" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--10. " ILLEGALMCMD ,System command of the transaction that caused the error" "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x50++0x3 line.long 0x0 "GPMC_CONFIG,The configuration register allows global configuration of the GPMC." bitfld.long 0x0 0. " NANDFORCEPOSTEDWRITE ,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "0,1" bitfld.long 0x0 1. " RESERVED ,Write 0 for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " WAIT0PINPOLARITY ,Selects the polarity of input pin WAIT0" "0,1" textline " " bitfld.long 0x0 9. " WAIT1PINPOLARITY ,Selects the polarity of input pin WAIT1" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x54++0x3 line.long 0x0 "GPMC_STATUS,The status register provides global status bits of the GPMC." bitfld.long 0x0 0. " EMPTYWRITEBUFFERSTATUS ,Stores the empty status of the write buffer" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Write 0s for future compatibility. Reads returns 0" textline " " bitfld.long 0x0 8. " WAIT0STATUS ,Is a copy of input pin WAIT0. (Reset value is WAIT0 input pin sampled at device reset.)" "0,1" bitfld.long 0x0 9. " WAIT1STATUS ,Is a copy of input pin WAIT1. (Reset value is WAIT1 input pin sampled at device reset.)" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x60++0x3 line.long 0x0 "GPMC_CONFIG1_i_0,The configuration register 1 sets signal control parameters per chip-select." bitfld.long 0x0 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "0,1,2,3" bitfld.long 0x0 10.--11. " DEVICETYPE ,Selects the attached device type" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " WAITPINSELECT ,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2, 0x3: Reserved ." "0,1,2,3" bitfld.long 0x0 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "0,1,2,3" textline " " bitfld.long 0x0 20. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses" "0,1" textline " " bitfld.long 0x0 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "0,1" bitfld.long 0x0 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "0,1,2,3" textline " " bitfld.long 0x0 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "0,1,2,3" bitfld.long 0x0 27. " WRITETYPE ,Selects the write mode operation" "0,1" textline " " bitfld.long 0x0 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "0,1" bitfld.long 0x0 29. " READTYPE ,Selects the read mode operation" "0,1" textline " " bitfld.long 0x0 30. " READMULTIPLE ,Selects the read single or multiple access" "0,1" bitfld.long 0x0 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1" group.byte 0x90++0x3 line.long 0x0 "GPMC_CONFIG1_i_1,The configuration register 1 sets signal control parameters per chip-select." bitfld.long 0x0 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "0,1,2,3" bitfld.long 0x0 10.--11. " DEVICETYPE ,Selects the attached device type" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " WAITPINSELECT ,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2, 0x3: Reserved ." "0,1,2,3" bitfld.long 0x0 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "0,1,2,3" textline " " bitfld.long 0x0 20. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses" "0,1" textline " " bitfld.long 0x0 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "0,1" bitfld.long 0x0 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "0,1,2,3" textline " " bitfld.long 0x0 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "0,1,2,3" bitfld.long 0x0 27. " WRITETYPE ,Selects the write mode operation" "0,1" textline " " bitfld.long 0x0 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "0,1" bitfld.long 0x0 29. " READTYPE ,Selects the read mode operation" "0,1" textline " " bitfld.long 0x0 30. " READMULTIPLE ,Selects the read single or multiple access" "0,1" bitfld.long 0x0 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1" group.byte 0xC0++0x3 line.long 0x0 "GPMC_CONFIG1_i_2,The configuration register 1 sets signal control parameters per chip-select." bitfld.long 0x0 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "0,1,2,3" bitfld.long 0x0 10.--11. " DEVICETYPE ,Selects the attached device type" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " WAITPINSELECT ,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2, 0x3: Reserved ." "0,1,2,3" bitfld.long 0x0 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "0,1,2,3" textline " " bitfld.long 0x0 20. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses" "0,1" textline " " bitfld.long 0x0 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "0,1" bitfld.long 0x0 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "0,1,2,3" textline " " bitfld.long 0x0 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "0,1,2,3" bitfld.long 0x0 27. " WRITETYPE ,Selects the write mode operation" "0,1" textline " " bitfld.long 0x0 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "0,1" bitfld.long 0x0 29. " READTYPE ,Selects the read mode operation" "0,1" textline " " bitfld.long 0x0 30. " READMULTIPLE ,Selects the read single or multiple access" "0,1" bitfld.long 0x0 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1" group.byte 0xF0++0x3 line.long 0x0 "GPMC_CONFIG1_i_3,The configuration register 1 sets signal control parameters per chip-select." bitfld.long 0x0 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "0,1,2,3" bitfld.long 0x0 10.--11. " DEVICETYPE ,Selects the attached device type" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " WAITPINSELECT ,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2, 0x3: Reserved ." "0,1,2,3" bitfld.long 0x0 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "0,1,2,3" textline " " bitfld.long 0x0 20. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses" "0,1" textline " " bitfld.long 0x0 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "0,1" bitfld.long 0x0 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "0,1,2,3" textline " " bitfld.long 0x0 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "0,1,2,3" bitfld.long 0x0 27. " WRITETYPE ,Selects the write mode operation" "0,1" textline " " bitfld.long 0x0 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "0,1" bitfld.long 0x0 29. " READTYPE ,Selects the read mode operation" "0,1" textline " " bitfld.long 0x0 30. " READMULTIPLE ,Selects the read single or multiple access" "0,1" bitfld.long 0x0 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1" group.byte 0x120++0x3 line.long 0x0 "GPMC_CONFIG1_i_4,The configuration register 1 sets signal control parameters per chip-select." bitfld.long 0x0 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "0,1,2,3" bitfld.long 0x0 10.--11. " DEVICETYPE ,Selects the attached device type" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " WAITPINSELECT ,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2, 0x3: Reserved ." "0,1,2,3" bitfld.long 0x0 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "0,1,2,3" textline " " bitfld.long 0x0 20. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses" "0,1" textline " " bitfld.long 0x0 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "0,1" bitfld.long 0x0 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "0,1,2,3" textline " " bitfld.long 0x0 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "0,1,2,3" bitfld.long 0x0 27. " WRITETYPE ,Selects the write mode operation" "0,1" textline " " bitfld.long 0x0 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "0,1" bitfld.long 0x0 29. " READTYPE ,Selects the read mode operation" "0,1" textline " " bitfld.long 0x0 30. " READMULTIPLE ,Selects the read single or multiple access" "0,1" bitfld.long 0x0 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1" group.byte 0x150++0x3 line.long 0x0 "GPMC_CONFIG1_i_5,The configuration register 1 sets signal control parameters per chip-select." bitfld.long 0x0 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "0,1,2,3" bitfld.long 0x0 10.--11. " DEVICETYPE ,Selects the attached device type" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " WAITPINSELECT ,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2, 0x3: Reserved ." "0,1,2,3" bitfld.long 0x0 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "0,1,2,3" textline " " bitfld.long 0x0 20. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses" "0,1" textline " " bitfld.long 0x0 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "0,1" bitfld.long 0x0 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "0,1,2,3" textline " " bitfld.long 0x0 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "0,1,2,3" bitfld.long 0x0 27. " WRITETYPE ,Selects the write mode operation" "0,1" textline " " bitfld.long 0x0 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "0,1" bitfld.long 0x0 29. " READTYPE ,Selects the read mode operation" "0,1" textline " " bitfld.long 0x0 30. " READMULTIPLE ,Selects the read single or multiple access" "0,1" bitfld.long 0x0 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1" group.byte 0x180++0x3 line.long 0x0 "GPMC_CONFIG1_i_6,The configuration register 1 sets signal control parameters per chip-select." bitfld.long 0x0 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "0,1,2,3" bitfld.long 0x0 10.--11. " DEVICETYPE ,Selects the attached device type" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " WAITPINSELECT ,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2, 0x3: Reserved ." "0,1,2,3" bitfld.long 0x0 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "0,1,2,3" textline " " bitfld.long 0x0 20. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses" "0,1" textline " " bitfld.long 0x0 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "0,1" bitfld.long 0x0 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "0,1,2,3" textline " " bitfld.long 0x0 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "0,1,2,3" bitfld.long 0x0 27. " WRITETYPE ,Selects the write mode operation" "0,1" textline " " bitfld.long 0x0 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "0,1" bitfld.long 0x0 29. " READTYPE ,Selects the read mode operation" "0,1" textline " " bitfld.long 0x0 30. " READMULTIPLE ,Selects the read single or multiple access" "0,1" bitfld.long 0x0 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1" group.byte 0x1B0++0x3 line.long 0x0 "GPMC_CONFIG1_i_7,The configuration register 1 sets signal control parameters per chip-select." bitfld.long 0x0 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor (RD/WRCYCLETIME, RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME, OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE, WRDATAONADMUXBUS)" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--9. " MUXADDDATA ,Enables the address and data multiplexed protocol (Reset value iscs0muxdevice input pin sampled at device reset for CS0 and 0 for CS1-CS7)" "0,1,2,3" bitfld.long 0x0 10.--11. " DEVICETYPE ,Selects the attached device type" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " DEVICESIZE ,Selects the device size attached (Reset value isbootdevicesize input pin sampled at device reset for CS0 and 0x1 for CS1 to CS7)" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " WAITPINSELECT ,Selects the input wait pin for this chip-select (The reset value is HW fixed to 0x0 for CS0-CS7)0x2, 0x3: Reserved ." "0,1,2,3" bitfld.long 0x0 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "0,1,2,3" textline " " bitfld.long 0x0 20. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 21. " WAITWRITEMONITORING ,Selects the Wait monitoring configuration for Write accesses" "0,1" textline " " bitfld.long 0x0 22. " WAITREADMONITORING ,Selects the Wait monitoring configuration for Read accesses (Reset value isbootwaiten input pin sampled at device reset)" "0,1" bitfld.long 0x0 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "0,1,2,3" textline " " bitfld.long 0x0 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "0,1,2,3" bitfld.long 0x0 27. " WRITETYPE ,Selects the write mode operation" "0,1" textline " " bitfld.long 0x0 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "0,1" bitfld.long 0x0 29. " READTYPE ,Selects the read mode operation" "0,1" textline " " bitfld.long 0x0 30. " READMULTIPLE ,Selects the read single or multiple access" "0,1" bitfld.long 0x0 31. " WRAPBURST ,Enables the wrapping burst capability. Must be set if the attached device is configured in wrapping burst" "0,1" group.byte 0x64++0x3 line.long 0x0 "GPMC_CONFIG2_i_0,CS signal timing parameter configuration" bitfld.long 0x0 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " CSEXTRADELAY ,CS i Add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " CSWROFFTIME ,CS i deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x94++0x3 line.long 0x0 "GPMC_CONFIG2_i_1,CS signal timing parameter configuration" bitfld.long 0x0 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " CSEXTRADELAY ,CS i Add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " CSWROFFTIME ,CS i deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0xC4++0x3 line.long 0x0 "GPMC_CONFIG2_i_2,CS signal timing parameter configuration" bitfld.long 0x0 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " CSEXTRADELAY ,CS i Add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " CSWROFFTIME ,CS i deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0xF4++0x3 line.long 0x0 "GPMC_CONFIG2_i_3,CS signal timing parameter configuration" bitfld.long 0x0 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " CSEXTRADELAY ,CS i Add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " CSWROFFTIME ,CS i deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x124++0x3 line.long 0x0 "GPMC_CONFIG2_i_4,CS signal timing parameter configuration" bitfld.long 0x0 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " CSEXTRADELAY ,CS i Add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " CSWROFFTIME ,CS i deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x154++0x3 line.long 0x0 "GPMC_CONFIG2_i_5,CS signal timing parameter configuration" bitfld.long 0x0 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " CSEXTRADELAY ,CS i Add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " CSWROFFTIME ,CS i deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x184++0x3 line.long 0x0 "GPMC_CONFIG2_i_6,CS signal timing parameter configuration" bitfld.long 0x0 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " CSEXTRADELAY ,CS i Add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " CSWROFFTIME ,CS i deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x1B4++0x3 line.long 0x0 "GPMC_CONFIG2_i_7,CS signal timing parameter configuration" bitfld.long 0x0 0.--3. " CSONTIME ,CS i assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " CSEXTRADELAY ,CS i Add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " CSRDOFFTIME ,CS i de-assertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " CSWROFFTIME ,CS i deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x68++0x3 line.long 0x0 "GPMC_CONFIG3_i_0,nADV signal timing parameter configuration" bitfld.long 0x0 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " ADVEXTRADELAY ,nADV add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " ADVRDOFFTIME ,nADV deassertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " ADVWROFFTIME ,nADV deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" bitfld.long 0x0 28.--30. " ADVAADMUXWROFFTIME ,nADV deassertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" group.byte 0x98++0x3 line.long 0x0 "GPMC_CONFIG3_i_1,nADV signal timing parameter configuration" bitfld.long 0x0 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " ADVEXTRADELAY ,nADV add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " ADVRDOFFTIME ,nADV deassertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " ADVWROFFTIME ,nADV deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" bitfld.long 0x0 28.--30. " ADVAADMUXWROFFTIME ,nADV deassertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" group.byte 0xC8++0x3 line.long 0x0 "GPMC_CONFIG3_i_2,nADV signal timing parameter configuration" bitfld.long 0x0 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " ADVEXTRADELAY ,nADV add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " ADVRDOFFTIME ,nADV deassertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " ADVWROFFTIME ,nADV deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" bitfld.long 0x0 28.--30. " ADVAADMUXWROFFTIME ,nADV deassertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" group.byte 0xF8++0x3 line.long 0x0 "GPMC_CONFIG3_i_3,nADV signal timing parameter configuration" bitfld.long 0x0 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " ADVEXTRADELAY ,nADV add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " ADVRDOFFTIME ,nADV deassertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " ADVWROFFTIME ,nADV deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" bitfld.long 0x0 28.--30. " ADVAADMUXWROFFTIME ,nADV deassertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" group.byte 0x128++0x3 line.long 0x0 "GPMC_CONFIG3_i_4,nADV signal timing parameter configuration" bitfld.long 0x0 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " ADVEXTRADELAY ,nADV add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " ADVRDOFFTIME ,nADV deassertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " ADVWROFFTIME ,nADV deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" bitfld.long 0x0 28.--30. " ADVAADMUXWROFFTIME ,nADV deassertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" group.byte 0x158++0x3 line.long 0x0 "GPMC_CONFIG3_i_5,nADV signal timing parameter configuration" bitfld.long 0x0 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " ADVEXTRADELAY ,nADV add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " ADVRDOFFTIME ,nADV deassertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " ADVWROFFTIME ,nADV deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" bitfld.long 0x0 28.--30. " ADVAADMUXWROFFTIME ,nADV deassertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" group.byte 0x188++0x3 line.long 0x0 "GPMC_CONFIG3_i_6,nADV signal timing parameter configuration" bitfld.long 0x0 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " ADVEXTRADELAY ,nADV add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " ADVRDOFFTIME ,nADV deassertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " ADVWROFFTIME ,nADV deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" bitfld.long 0x0 28.--30. " ADVAADMUXWROFFTIME ,nADV deassertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" group.byte 0x1B8++0x3 line.long 0x0 "GPMC_CONFIG3_i_7,nADV signal timing parameter configuration" bitfld.long 0x0 0.--3. " ADVONTIME ,nADV assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ADVAADMUXONTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " ADVEXTRADELAY ,nADV add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " ADVRDOFFTIME ,nADV deassertion time from start cycle time for read accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--20. " ADVWROFFTIME ,nADV deassertion time from start cycle time for write accesses 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--26. " ADVAADMUXRDOFFTIME ,nADV assertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" bitfld.long 0x0 28.--30. " ADVAADMUXWROFFTIME ,nADV deassertion for first address phase when using the AAD-multiplexed protocol 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1" group.byte 0x6C++0x3 line.long 0x0 "GPMC_CONFIG4_i_0,nWE and nOE signals timing parameter configuration" bitfld.long 0x0 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " OEEXTRADELAY ,nOE add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " OEOFFTIME ,nOE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " OEAADMUX_OFFTIME ,nOE deassertion time for the first address phase in an AAD-multiplexed access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--22. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " WEEXTRADELAY ,nWE add extra half-GPMC_FCLK cycle" "0,1" textline " " bitfld.long 0x0 24.--28. " WEOFFTIME ,nWE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" group.byte 0x9C++0x3 line.long 0x0 "GPMC_CONFIG4_i_1,nWE and nOE signals timing parameter configuration" bitfld.long 0x0 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " OEEXTRADELAY ,nOE add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " OEOFFTIME ,nOE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " OEAADMUX_OFFTIME ,nOE deassertion time for the first address phase in an AAD-multiplexed access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--22. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " WEEXTRADELAY ,nWE add extra half-GPMC_FCLK cycle" "0,1" textline " " bitfld.long 0x0 24.--28. " WEOFFTIME ,nWE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" group.byte 0xCC++0x3 line.long 0x0 "GPMC_CONFIG4_i_2,nWE and nOE signals timing parameter configuration" bitfld.long 0x0 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " OEEXTRADELAY ,nOE add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " OEOFFTIME ,nOE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " OEAADMUX_OFFTIME ,nOE deassertion time for the first address phase in an AAD-multiplexed access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--22. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " WEEXTRADELAY ,nWE add extra half-GPMC_FCLK cycle" "0,1" textline " " bitfld.long 0x0 24.--28. " WEOFFTIME ,nWE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" group.byte 0xFC++0x3 line.long 0x0 "GPMC_CONFIG4_i_3,nWE and nOE signals timing parameter configuration" bitfld.long 0x0 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " OEEXTRADELAY ,nOE add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " OEOFFTIME ,nOE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " OEAADMUX_OFFTIME ,nOE deassertion time for the first address phase in an AAD-multiplexed access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--22. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " WEEXTRADELAY ,nWE add extra half-GPMC_FCLK cycle" "0,1" textline " " bitfld.long 0x0 24.--28. " WEOFFTIME ,nWE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" group.byte 0x12C++0x3 line.long 0x0 "GPMC_CONFIG4_i_4,nWE and nOE signals timing parameter configuration" bitfld.long 0x0 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " OEEXTRADELAY ,nOE add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " OEOFFTIME ,nOE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " OEAADMUX_OFFTIME ,nOE deassertion time for the first address phase in an AAD-multiplexed access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--22. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " WEEXTRADELAY ,nWE add extra half-GPMC_FCLK cycle" "0,1" textline " " bitfld.long 0x0 24.--28. " WEOFFTIME ,nWE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" group.byte 0x15C++0x3 line.long 0x0 "GPMC_CONFIG4_i_5,nWE and nOE signals timing parameter configuration" bitfld.long 0x0 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " OEEXTRADELAY ,nOE add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " OEOFFTIME ,nOE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " OEAADMUX_OFFTIME ,nOE deassertion time for the first address phase in an AAD-multiplexed access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--22. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " WEEXTRADELAY ,nWE add extra half-GPMC_FCLK cycle" "0,1" textline " " bitfld.long 0x0 24.--28. " WEOFFTIME ,nWE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" group.byte 0x18C++0x3 line.long 0x0 "GPMC_CONFIG4_i_6,nWE and nOE signals timing parameter configuration" bitfld.long 0x0 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " OEEXTRADELAY ,nOE add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " OEOFFTIME ,nOE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " OEAADMUX_OFFTIME ,nOE deassertion time for the first address phase in an AAD-multiplexed access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--22. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " WEEXTRADELAY ,nWE add extra half-GPMC_FCLK cycle" "0,1" textline " " bitfld.long 0x0 24.--28. " WEOFFTIME ,nWE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" group.byte 0x1BC++0x3 line.long 0x0 "GPMC_CONFIG4_i_7,nWE and nOE signals timing parameter configuration" bitfld.long 0x0 0.--3. " OEONTIME ,nOE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " OEAADMUX_ONTIME ,nOE assertion time for the first address phase in an AAD-mux access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " OEEXTRADELAY ,nOE add extra half-GPMC_FCLK cycle" "0,1" bitfld.long 0x0 8.--12. " OEOFFTIME ,nOE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--15. " OEAADMUX_OFFTIME ,nOE deassertion time for the first address phase in an AAD-multiplexed access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--19. " WEONTIME ,nWE assertion time from start cycle time 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--22. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " WEEXTRADELAY ,nWE add extra half-GPMC_FCLK cycle" "0,1" textline " " bitfld.long 0x0 24.--28. " WEOFFTIME ,nWE deassertion time from start cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" group.byte 0x70++0x3 line.long 0x0 "GPMC_CONFIG5_i_0,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x0 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xA0++0x3 line.long 0x0 "GPMC_CONFIG5_i_1,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x0 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x3 line.long 0x0 "GPMC_CONFIG5_i_2,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x0 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x100++0x3 line.long 0x0 "GPMC_CONFIG5_i_3,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x0 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x130++0x3 line.long 0x0 "GPMC_CONFIG5_i_4,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x0 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x160++0x3 line.long 0x0 "GPMC_CONFIG5_i_5,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x0 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x190++0x3 line.long 0x0 "GPMC_CONFIG5_i_6,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x0 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1C0++0x3 line.long 0x0 "GPMC_CONFIG5_i_7,RdAccessTime and CycleTime timing parameters configuration" bitfld.long 0x0 0.--4. " RDCYCLETIME ,Total read cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " WRCYCLETIME ,Total write cycle time 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Write 0s for future compatibility. Reads returns 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " RDACCESSTIME ,Delay between start cycle time and first data valid 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x74++0x3 line.long 0x0 "GPMC_CONFIG6_i_0,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x0 0.--3. " BUSTURNAROUND ,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "0,1" bitfld.long 0x0 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "0,1" textline " " bitfld.long 0x0 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--30. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 31. " RESERVED ,TI Internal use - Do not modify." "0,1" group.byte 0xA4++0x3 line.long 0x0 "GPMC_CONFIG6_i_1,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x0 0.--3. " BUSTURNAROUND ,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "0,1" bitfld.long 0x0 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "0,1" textline " " bitfld.long 0x0 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--30. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 31. " RESERVED ,TI Internal use - Do not modify." "0,1" group.byte 0xD4++0x3 line.long 0x0 "GPMC_CONFIG6_i_2,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x0 0.--3. " BUSTURNAROUND ,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "0,1" bitfld.long 0x0 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "0,1" textline " " bitfld.long 0x0 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--30. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 31. " RESERVED ,TI Internal use - Do not modify." "0,1" group.byte 0x104++0x3 line.long 0x0 "GPMC_CONFIG6_i_3,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x0 0.--3. " BUSTURNAROUND ,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "0,1" bitfld.long 0x0 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "0,1" textline " " bitfld.long 0x0 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--30. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 31. " RESERVED ,TI Internal use - Do not modify." "0,1" group.byte 0x134++0x3 line.long 0x0 "GPMC_CONFIG6_i_4,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x0 0.--3. " BUSTURNAROUND ,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "0,1" bitfld.long 0x0 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "0,1" textline " " bitfld.long 0x0 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--30. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 31. " RESERVED ,TI Internal use - Do not modify." "0,1" group.byte 0x164++0x3 line.long 0x0 "GPMC_CONFIG6_i_5,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x0 0.--3. " BUSTURNAROUND ,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "0,1" bitfld.long 0x0 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "0,1" textline " " bitfld.long 0x0 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--30. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 31. " RESERVED ,TI Internal use - Do not modify." "0,1" group.byte 0x194++0x3 line.long 0x0 "GPMC_CONFIG6_i_6,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x0 0.--3. " BUSTURNAROUND ,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "0,1" bitfld.long 0x0 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "0,1" textline " " bitfld.long 0x0 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--30. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 31. " RESERVED ,TI Internal use - Do not modify." "0,1" group.byte 0x1C4++0x3 line.long 0x0 "GPMC_CONFIG6_i_7,WrAccessTime, WrDataOnADmuxBus, Cycle2Cycle and BusTurnAround parameters configuration" bitfld.long 0x0 0.--3. " BUSTURNAROUND ,Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write) 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 6. " CYCLE2CYCLEDIFFCSEN ,Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)" "0,1" bitfld.long 0x0 7. " CYCLE2CYCLESAMECSEN ,Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)" "0,1" textline " " bitfld.long 0x0 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between successive accesses 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0xF: 15 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC_CLK rising edge used by the attached memory for the first data capture 0x00: 0 GPMC_FCLK cycle 0x01: 1 GPMC_FCLK cycle ... 0x1F: 31 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--30. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 31. " RESERVED ,TI Internal use - Do not modify." "0,1" group.byte 0x78++0x3 line.long 0x0 "GPMC_CONFIG7_i_0,CS address mapping configuration" bitfld.long 0x0 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CSVALID ,CS enable" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 8.--11. " MASKADDRESS ,CS mask address. 0x0000: Chip-select size of 256 MiB 0x1000: Chip-select size of 128 MiB 0x1100: Chip-select size of 64 MiB 0x1110: Chip-select size of 32 MiB 0x1111: Chip-select size of 16 MiB Other values must be avoided as they create holes in the chip-select address space." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0xA8++0x3 line.long 0x0 "GPMC_CONFIG7_i_1,CS address mapping configuration" bitfld.long 0x0 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CSVALID ,CS enable" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 8.--11. " MASKADDRESS ,CS mask address. 0x0000: Chip-select size of 256 MiB 0x1000: Chip-select size of 128 MiB 0x1100: Chip-select size of 64 MiB 0x1110: Chip-select size of 32 MiB 0x1111: Chip-select size of 16 MiB Other values must be avoided as they create holes in the chip-select address space." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0xD8++0x3 line.long 0x0 "GPMC_CONFIG7_i_2,CS address mapping configuration" bitfld.long 0x0 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CSVALID ,CS enable" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 8.--11. " MASKADDRESS ,CS mask address. 0x0000: Chip-select size of 256 MiB 0x1000: Chip-select size of 128 MiB 0x1100: Chip-select size of 64 MiB 0x1110: Chip-select size of 32 MiB 0x1111: Chip-select size of 16 MiB Other values must be avoided as they create holes in the chip-select address space." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x108++0x3 line.long 0x0 "GPMC_CONFIG7_i_3,CS address mapping configuration" bitfld.long 0x0 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CSVALID ,CS enable" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 8.--11. " MASKADDRESS ,CS mask address. 0x0000: Chip-select size of 256 MiB 0x1000: Chip-select size of 128 MiB 0x1100: Chip-select size of 64 MiB 0x1110: Chip-select size of 32 MiB 0x1111: Chip-select size of 16 MiB Other values must be avoided as they create holes in the chip-select address space." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x138++0x3 line.long 0x0 "GPMC_CONFIG7_i_4,CS address mapping configuration" bitfld.long 0x0 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CSVALID ,CS enable" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 8.--11. " MASKADDRESS ,CS mask address. 0x0000: Chip-select size of 256 MiB 0x1000: Chip-select size of 128 MiB 0x1100: Chip-select size of 64 MiB 0x1110: Chip-select size of 32 MiB 0x1111: Chip-select size of 16 MiB Other values must be avoided as they create holes in the chip-select address space." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x168++0x3 line.long 0x0 "GPMC_CONFIG7_i_5,CS address mapping configuration" bitfld.long 0x0 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CSVALID ,CS enable" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 8.--11. " MASKADDRESS ,CS mask address. 0x0000: Chip-select size of 256 MiB 0x1000: Chip-select size of 128 MiB 0x1100: Chip-select size of 64 MiB 0x1110: Chip-select size of 32 MiB 0x1111: Chip-select size of 16 MiB Other values must be avoided as they create holes in the chip-select address space." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x198++0x3 line.long 0x0 "GPMC_CONFIG7_i_6,CS address mapping configuration" bitfld.long 0x0 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CSVALID ,CS enable" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 8.--11. " MASKADDRESS ,CS mask address. 0x0000: Chip-select size of 256 MiB 0x1000: Chip-select size of 128 MiB 0x1100: Chip-select size of 64 MiB 0x1110: Chip-select size of 32 MiB 0x1111: Chip-select size of 16 MiB Other values must be avoided as they create holes in the chip-select address space." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x1C8++0x3 line.long 0x0 "GPMC_CONFIG7_i_7,CS address mapping configuration" bitfld.long 0x0 0.--5. " BASEADDRESS ,CSi base address where i = 0 to 7 (16-MiB minimum granularity) bits [5:0] corresponds to A29, A28, A27, A26, A25, and A24. See" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CSVALID ,CS enable" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 8.--11. " MASKADDRESS ,CS mask address. 0x0000: Chip-select size of 256 MiB 0x1000: Chip-select size of 128 MiB 0x1100: Chip-select size of 64 MiB 0x1110: Chip-select size of 32 MiB 0x1111: Chip-select size of 16 MiB Other values must be avoided as they create holes in the chip-select address space." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x7C++0x3 line.long 0x0 "GPMC_NAND_COMMAND_i_0,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." group.byte 0xAC++0x3 line.long 0x0 "GPMC_NAND_COMMAND_i_1,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." group.byte 0xDC++0x3 line.long 0x0 "GPMC_NAND_COMMAND_i_2,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." group.byte 0x10C++0x3 line.long 0x0 "GPMC_NAND_COMMAND_i_3,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." group.byte 0x13C++0x3 line.long 0x0 "GPMC_NAND_COMMAND_i_4,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." group.byte 0x16C++0x3 line.long 0x0 "GPMC_NAND_COMMAND_i_5,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." group.byte 0x19C++0x3 line.long 0x0 "GPMC_NAND_COMMAND_i_6,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." group.byte 0x1CC++0x3 line.long 0x0 "GPMC_NAND_COMMAND_i_7,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_COMMAND ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_COMMAND_i location places the data as the NAND command value on the bus, using a regular asynchronous write access." group.byte 0x80++0x3 line.long 0x0 "GPMC_NAND_ADDRESS_i_0,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." group.byte 0xB0++0x3 line.long 0x0 "GPMC_NAND_ADDRESS_i_1,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." group.byte 0xE0++0x3 line.long 0x0 "GPMC_NAND_ADDRESS_i_2,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." group.byte 0x110++0x3 line.long 0x0 "GPMC_NAND_ADDRESS_i_3,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." group.byte 0x140++0x3 line.long 0x0 "GPMC_NAND_ADDRESS_i_4,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." group.byte 0x170++0x3 line.long 0x0 "GPMC_NAND_ADDRESS_i_5,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." group.byte 0x1A0++0x3 line.long 0x0 "GPMC_NAND_ADDRESS_i_6,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." group.byte 0x1D0++0x3 line.long 0x0 "GPMC_NAND_ADDRESS_i_7,This register is not a true register, only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_ADDRESS ,This register is not a true register, only an address location. Writing data at theGPMC_NAND_ADDRESS_i location places the data as the NAND partial address value on the bus, using a regular asynchronous write access." group.byte 0x84++0x3 line.long 0x0 "GPMC_NAND_DATA_i_0,This register is not a true register,only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, only an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." group.byte 0xB4++0x3 line.long 0x0 "GPMC_NAND_DATA_i_1,This register is not a true register,only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, only an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." group.byte 0xE4++0x3 line.long 0x0 "GPMC_NAND_DATA_i_2,This register is not a true register,only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, only an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." group.byte 0x114++0x3 line.long 0x0 "GPMC_NAND_DATA_i_3,This register is not a true register,only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, only an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." group.byte 0x144++0x3 line.long 0x0 "GPMC_NAND_DATA_i_4,This register is not a true register,only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, only an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." group.byte 0x174++0x3 line.long 0x0 "GPMC_NAND_DATA_i_5,This register is not a true register,only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, only an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." group.byte 0x1A4++0x3 line.long 0x0 "GPMC_NAND_DATA_i_6,This register is not a true register,only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, only an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." group.byte 0x1D4++0x3 line.long 0x0 "GPMC_NAND_DATA_i_7,This register is not a true register,only an address location." hexmask.long 0x0 0.--31. 1. " GPMC_NAND_DATA ,This register is not a true register, only an address location. Reading data from theGPMC_NAND_DATA_i location or from any location in the associated chip-select memory region activates an asynchronous read access." group.byte 0x1E0++0x3 line.long 0x0 "GPMC_PREFETCH_CONFIG1,Prefetch engine configuration 1" bitfld.long 0x0 0. " ACCESSMODE ,Selects prefetch read or write-posting accesses" "0,1" bitfld.long 0x0 1. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 2. " DMAMODE ,Selects interrupt synchronization or DMA request synchronization" "0,1" bitfld.long 0x0 3. " SYNCHROMODE ,Selects when the engine starts the access to chip-select" "0,1" textline " " bitfld.long 0x0 4.--5. " WAITPINSELECTOR ,Select which wait pin edge detector should start the engine in synchronized mode0x2, 0x3: Reserved enum=W2 ." "0,1,2,3" bitfld.long 0x0 6. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 7. " ENABLEENGINE ,Enables the Prefetch Postwite engine" "0,1" hexmask.long.byte 0x0 8.--14. 1. " FIFOTHRESHOLD ,Selects the maximum number of bytes read from the FIFO or written to the FIFO by the host on a DMA or interrupt request 0x00: 0 byte 0x01: 1 byte ... 0x40: 64 bytes" textline " " bitfld.long 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 16.--19. " PFPWWEIGHTEDPRIO ,When an arbitration occurs between a DMA and a PFPW engine access, the DMA is always serviced. If the PFPWEnRoundRobin is enabled, 0x0: The next access is granted to the PFPW engine. 0x1: The next two accesses are granted to the PFPW engine. ..., 0xF: The next 16 accesses are granted to the PFPW engine." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--22. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " PFPWENROUNDROBIN ,Enables the PFPW RoundRobin arbitration" "0,1" textline " " bitfld.long 0x0 24.--26. " ENGINECSSELECTOR ,Selects the chip-select where Prefetch Postwrite engine is active 0x0: CS0 0x1: CS1 0x2: CS2 0x3: CS3 0x4: CS4 0x5: CS5 0x6: CS6 0x7: CS7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " ENABLEOPTIMIZEDACCESS ,Enables access cycle optimization" "0,1" textline " " bitfld.long 0x0 28.--30. " CYCLEOPTIMIZATION ,Define the number of GPMC_FCLK cycles to be subtracted from RDCYCLETIME, WRCYCLETIME, RDACCESSTIME, CSRDOFFTIME, CSWROFFTIME, ADVRDOFFTIME, ADVWROFFTIME, OEOFFTIME, WEOFFTIME 0x0: 0 GPMC_FCLK cycle 0x1: 1 GPMC_FCLK cycle ... 0x7: 7 GPMC_FCLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x1E4++0x3 line.long 0x0 "GPMC_PREFETCH_CONFIG2,Prefetch engine configuration 2" hexmask.long.word 0x0 0.--13. 1. " TRANSFERCOUNT ,Selects the number of bytes to be read or written by the engine to the selected chip-select 0x0000: 0 byte 0x0001: 1 byte ... 0x2000: 8 Kbytes" hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x1EC++0x3 line.long 0x0 "GPMC_PREFETCH_CONTROL,Prefetch engine control" bitfld.long 0x0 0. " STARTENGINE ,Resets the FIFO pointer and starts the engine" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x1F0++0x3 line.long 0x0 "GPMC_PREFETCH_STATUS,Prefetch engine status" hexmask.long.word 0x0 0.--13. 1. " COUNTVALUE ,Number of remaining bytes to be read or to be written by the engine according to the TransferCount value 0x0000: 0 byte remaining to be read or to be written 0x0001: 1 byte remaining to be read or to be written ... 0x2000: 8 KiB remaining to be read or to be written" bitfld.long 0x0 14.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" textline " " bitfld.long 0x0 16. " FIFOTHRESHOLDSTATUS ,Set when FIFOPointer exceeds FIFOThreshold value" "0,1" hexmask.long.byte 0x0 17.--23. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." textline " " hexmask.long.byte 0x0 24.--30. 1. " FIFOPOINTER ,Number of available bytes to be read or number of free empty byte places to be written 0x00: 0 byte available to be read or 0 free empty place to be written ... 0x40: 64 bytes available to be read or 64 empty places to be written" bitfld.long 0x0 31. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x1F4++0x3 line.long 0x0 "GPMC_ECC_CONFIG,ECC configuration" bitfld.long 0x0 0. " ECCENABLE ,Enables the ECC feature" "0,1" bitfld.long 0x0 1.--3. " ECCCS ,Selects the CS where ECC is computedOther: Reserved enum=CS3 ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " ECCTOPSECTOR ,Number of sectors to process with the BCH algorithm 0x0: 1 sector (512-kB page) 0x1: 2 sectors ... 0x3: 4 sectors (2-kB page) ... 0x7: 8 sectors (4-kB page)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " ECC16B ,Selects an ECC calculated on 16 columns" "0,1" textline " " bitfld.long 0x0 8.--11. " ECCWRAPMODE ,Spare area organization definition for the BCH algorithm. See the BCH syndrome/parity calculator module functional specification for more details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--13. " ECCBCHTSEL ,Error correction capability used for BCH" "0,1,2,3" textline " " bitfld.long 0x0 14.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3" bitfld.long 0x0 16. " ECCALGORITHM ,ECC algorithm used" "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x1F8++0x3 line.long 0x0 "GPMC_ECC_CONTROL,ECC control" bitfld.long 0x0 0.--3. " ECCPOINTER ,Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer - Writes to this field select the ECC result register where the first ECC computation will be stored.); Other enums: writing other values disables the ECC engine (ECCENABLE bit ofGPMC_ECC_CONFIG set to 0)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " ECCCLEAR ,Clear all ECC result registers Reads return 0. Write 0x1 to this field clears all ECC result registers. Write 0x0 is ignored." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x1FC++0x3 line.long 0x0 "GPMC_ECC_SIZE_CONFIG,ECC size" bitfld.long 0x0 0. " ECC1RESULTSIZE ,Selects ECC size for ECC 1 result register" "0,1" bitfld.long 0x0 1. " ECC2RESULTSIZE ,Selects ECC size for ECC 2 result register" "0,1" textline " " bitfld.long 0x0 2. " ECC3RESULTSIZE ,Selects ECC size for ECC 3 result register" "0,1" bitfld.long 0x0 3. " ECC4RESULTSIZE ,Selects ECC size for ECC 4 result register" "0,1" textline " " bitfld.long 0x0 4. " ECC5RESULTSIZE ,Selects ECC size for ECC 5 result register" "0,1" bitfld.long 0x0 5. " ECC6RESULTSIZE ,Selects ECC size for ECC 6 result register" "0,1" textline " " bitfld.long 0x0 6. " ECC7RESULTSIZE ,Selects ECC size for ECC 7 result register" "0,1" bitfld.long 0x0 7. " ECC8RESULTSIZE ,Selects ECC size for ECC 8 result register" "0,1" textline " " bitfld.long 0x0 8. " ECC9RESULTSIZE ,Selects ECC size for ECC 9 result register" "0,1" bitfld.long 0x0 9.--11. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x0 12.--19. 1. " ECCSIZE0 ,Defines Hamming code ECC size 0 in bytes 0x00: 2 bytes 0x01: 4 bytes 0x02: 6 bytes 0x03: 8 bytes ... 0xFF: 512 bytes For BCH code ECC, the size 0 is programmed directly with the number of nibbles. For details, see , Wrapping Modes." bitfld.long 0x0 20.--21. " RESERVED ,Write 0s for future compatibility. Read returns 3." "0,1,2,3" textline " " hexmask.long.byte 0x0 22.--29. 1. " ECCSIZE1 ,Defines Hamming code ECC size 1 in bytes 0x00: 2 bytes 0x01: 4 bytes 0x02: 6 bytes 0x03: 8 bytes ... 0xFF: 512 bytes For BCH code ECC, the size 1 is programmed directly with the number of nibbles. For details, see , Wrapping Modes." bitfld.long 0x0 30.--31. " RESERVED ,Write 0s for future compatibility. Read returns 3." "0,1,2,3" group.byte 0x200++0x3 line.long 0x0 "GPMC_ECCj_RESULT_0,ECC result register" bitfld.long 0x0 0. " P1E ,Even column parity bit 1" "0,1" bitfld.long 0x0 1. " P2E ,Even column parity bit 2" "0,1" textline " " bitfld.long 0x0 2. " P4E ,Even column parity bit 4" "0,1" bitfld.long 0x0 3. " P8E ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x0 4. " P16E ,Even row parity bit 16" "0,1" bitfld.long 0x0 5. " P32E ,Even row parity bit 32" "0,1" textline " " bitfld.long 0x0 6. " P64E ,Even row parity bit 64" "0,1" bitfld.long 0x0 7. " P128E ,Even row parity bit 128" "0,1" textline " " bitfld.long 0x0 8. " P256E ,Even row parity bit 256" "0,1" bitfld.long 0x0 9. " P512E ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x0 10. " P1024E ,Even row parity bit 1024" "0,1" bitfld.long 0x0 11. " P2048E ,Even row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" textline " " bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd row parity bit 8" "0,1" bitfld.long 0x0 20. " P16O ,Odd row parity bit 16" "0,1" textline " " bitfld.long 0x0 21. " P32O ,Odd row parity bit 32" "0,1" bitfld.long 0x0 22. " P64O ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd row parity bit 128" "0,1" bitfld.long 0x0 24. " P256O ,Odd row parity bit 256" "0,1" textline " " bitfld.long 0x0 25. " P512O ,Odd row parity bit 512" "0,1" bitfld.long 0x0 26. " P1024O ,Odd row parity bit 1024" "0,1" textline " " bitfld.long 0x0 27. " P2048O ,Odd row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x204++0x3 line.long 0x0 "GPMC_ECCj_RESULT_1,ECC result register" bitfld.long 0x0 0. " P1E ,Even column parity bit 1" "0,1" bitfld.long 0x0 1. " P2E ,Even column parity bit 2" "0,1" textline " " bitfld.long 0x0 2. " P4E ,Even column parity bit 4" "0,1" bitfld.long 0x0 3. " P8E ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x0 4. " P16E ,Even row parity bit 16" "0,1" bitfld.long 0x0 5. " P32E ,Even row parity bit 32" "0,1" textline " " bitfld.long 0x0 6. " P64E ,Even row parity bit 64" "0,1" bitfld.long 0x0 7. " P128E ,Even row parity bit 128" "0,1" textline " " bitfld.long 0x0 8. " P256E ,Even row parity bit 256" "0,1" bitfld.long 0x0 9. " P512E ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x0 10. " P1024E ,Even row parity bit 1024" "0,1" bitfld.long 0x0 11. " P2048E ,Even row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" textline " " bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd row parity bit 8" "0,1" bitfld.long 0x0 20. " P16O ,Odd row parity bit 16" "0,1" textline " " bitfld.long 0x0 21. " P32O ,Odd row parity bit 32" "0,1" bitfld.long 0x0 22. " P64O ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd row parity bit 128" "0,1" bitfld.long 0x0 24. " P256O ,Odd row parity bit 256" "0,1" textline " " bitfld.long 0x0 25. " P512O ,Odd row parity bit 512" "0,1" bitfld.long 0x0 26. " P1024O ,Odd row parity bit 1024" "0,1" textline " " bitfld.long 0x0 27. " P2048O ,Odd row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x208++0x3 line.long 0x0 "GPMC_ECCj_RESULT_2,ECC result register" bitfld.long 0x0 0. " P1E ,Even column parity bit 1" "0,1" bitfld.long 0x0 1. " P2E ,Even column parity bit 2" "0,1" textline " " bitfld.long 0x0 2. " P4E ,Even column parity bit 4" "0,1" bitfld.long 0x0 3. " P8E ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x0 4. " P16E ,Even row parity bit 16" "0,1" bitfld.long 0x0 5. " P32E ,Even row parity bit 32" "0,1" textline " " bitfld.long 0x0 6. " P64E ,Even row parity bit 64" "0,1" bitfld.long 0x0 7. " P128E ,Even row parity bit 128" "0,1" textline " " bitfld.long 0x0 8. " P256E ,Even row parity bit 256" "0,1" bitfld.long 0x0 9. " P512E ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x0 10. " P1024E ,Even row parity bit 1024" "0,1" bitfld.long 0x0 11. " P2048E ,Even row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" textline " " bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd row parity bit 8" "0,1" bitfld.long 0x0 20. " P16O ,Odd row parity bit 16" "0,1" textline " " bitfld.long 0x0 21. " P32O ,Odd row parity bit 32" "0,1" bitfld.long 0x0 22. " P64O ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd row parity bit 128" "0,1" bitfld.long 0x0 24. " P256O ,Odd row parity bit 256" "0,1" textline " " bitfld.long 0x0 25. " P512O ,Odd row parity bit 512" "0,1" bitfld.long 0x0 26. " P1024O ,Odd row parity bit 1024" "0,1" textline " " bitfld.long 0x0 27. " P2048O ,Odd row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x20C++0x3 line.long 0x0 "GPMC_ECCj_RESULT_3,ECC result register" bitfld.long 0x0 0. " P1E ,Even column parity bit 1" "0,1" bitfld.long 0x0 1. " P2E ,Even column parity bit 2" "0,1" textline " " bitfld.long 0x0 2. " P4E ,Even column parity bit 4" "0,1" bitfld.long 0x0 3. " P8E ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x0 4. " P16E ,Even row parity bit 16" "0,1" bitfld.long 0x0 5. " P32E ,Even row parity bit 32" "0,1" textline " " bitfld.long 0x0 6. " P64E ,Even row parity bit 64" "0,1" bitfld.long 0x0 7. " P128E ,Even row parity bit 128" "0,1" textline " " bitfld.long 0x0 8. " P256E ,Even row parity bit 256" "0,1" bitfld.long 0x0 9. " P512E ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x0 10. " P1024E ,Even row parity bit 1024" "0,1" bitfld.long 0x0 11. " P2048E ,Even row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" textline " " bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd row parity bit 8" "0,1" bitfld.long 0x0 20. " P16O ,Odd row parity bit 16" "0,1" textline " " bitfld.long 0x0 21. " P32O ,Odd row parity bit 32" "0,1" bitfld.long 0x0 22. " P64O ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd row parity bit 128" "0,1" bitfld.long 0x0 24. " P256O ,Odd row parity bit 256" "0,1" textline " " bitfld.long 0x0 25. " P512O ,Odd row parity bit 512" "0,1" bitfld.long 0x0 26. " P1024O ,Odd row parity bit 1024" "0,1" textline " " bitfld.long 0x0 27. " P2048O ,Odd row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x210++0x3 line.long 0x0 "GPMC_ECCj_RESULT_4,ECC result register" bitfld.long 0x0 0. " P1E ,Even column parity bit 1" "0,1" bitfld.long 0x0 1. " P2E ,Even column parity bit 2" "0,1" textline " " bitfld.long 0x0 2. " P4E ,Even column parity bit 4" "0,1" bitfld.long 0x0 3. " P8E ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x0 4. " P16E ,Even row parity bit 16" "0,1" bitfld.long 0x0 5. " P32E ,Even row parity bit 32" "0,1" textline " " bitfld.long 0x0 6. " P64E ,Even row parity bit 64" "0,1" bitfld.long 0x0 7. " P128E ,Even row parity bit 128" "0,1" textline " " bitfld.long 0x0 8. " P256E ,Even row parity bit 256" "0,1" bitfld.long 0x0 9. " P512E ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x0 10. " P1024E ,Even row parity bit 1024" "0,1" bitfld.long 0x0 11. " P2048E ,Even row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" textline " " bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd row parity bit 8" "0,1" bitfld.long 0x0 20. " P16O ,Odd row parity bit 16" "0,1" textline " " bitfld.long 0x0 21. " P32O ,Odd row parity bit 32" "0,1" bitfld.long 0x0 22. " P64O ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd row parity bit 128" "0,1" bitfld.long 0x0 24. " P256O ,Odd row parity bit 256" "0,1" textline " " bitfld.long 0x0 25. " P512O ,Odd row parity bit 512" "0,1" bitfld.long 0x0 26. " P1024O ,Odd row parity bit 1024" "0,1" textline " " bitfld.long 0x0 27. " P2048O ,Odd row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x214++0x3 line.long 0x0 "GPMC_ECCj_RESULT_5,ECC result register" bitfld.long 0x0 0. " P1E ,Even column parity bit 1" "0,1" bitfld.long 0x0 1. " P2E ,Even column parity bit 2" "0,1" textline " " bitfld.long 0x0 2. " P4E ,Even column parity bit 4" "0,1" bitfld.long 0x0 3. " P8E ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x0 4. " P16E ,Even row parity bit 16" "0,1" bitfld.long 0x0 5. " P32E ,Even row parity bit 32" "0,1" textline " " bitfld.long 0x0 6. " P64E ,Even row parity bit 64" "0,1" bitfld.long 0x0 7. " P128E ,Even row parity bit 128" "0,1" textline " " bitfld.long 0x0 8. " P256E ,Even row parity bit 256" "0,1" bitfld.long 0x0 9. " P512E ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x0 10. " P1024E ,Even row parity bit 1024" "0,1" bitfld.long 0x0 11. " P2048E ,Even row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" textline " " bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd row parity bit 8" "0,1" bitfld.long 0x0 20. " P16O ,Odd row parity bit 16" "0,1" textline " " bitfld.long 0x0 21. " P32O ,Odd row parity bit 32" "0,1" bitfld.long 0x0 22. " P64O ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd row parity bit 128" "0,1" bitfld.long 0x0 24. " P256O ,Odd row parity bit 256" "0,1" textline " " bitfld.long 0x0 25. " P512O ,Odd row parity bit 512" "0,1" bitfld.long 0x0 26. " P1024O ,Odd row parity bit 1024" "0,1" textline " " bitfld.long 0x0 27. " P2048O ,Odd row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x218++0x3 line.long 0x0 "GPMC_ECCj_RESULT_6,ECC result register" bitfld.long 0x0 0. " P1E ,Even column parity bit 1" "0,1" bitfld.long 0x0 1. " P2E ,Even column parity bit 2" "0,1" textline " " bitfld.long 0x0 2. " P4E ,Even column parity bit 4" "0,1" bitfld.long 0x0 3. " P8E ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x0 4. " P16E ,Even row parity bit 16" "0,1" bitfld.long 0x0 5. " P32E ,Even row parity bit 32" "0,1" textline " " bitfld.long 0x0 6. " P64E ,Even row parity bit 64" "0,1" bitfld.long 0x0 7. " P128E ,Even row parity bit 128" "0,1" textline " " bitfld.long 0x0 8. " P256E ,Even row parity bit 256" "0,1" bitfld.long 0x0 9. " P512E ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x0 10. " P1024E ,Even row parity bit 1024" "0,1" bitfld.long 0x0 11. " P2048E ,Even row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" textline " " bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd row parity bit 8" "0,1" bitfld.long 0x0 20. " P16O ,Odd row parity bit 16" "0,1" textline " " bitfld.long 0x0 21. " P32O ,Odd row parity bit 32" "0,1" bitfld.long 0x0 22. " P64O ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd row parity bit 128" "0,1" bitfld.long 0x0 24. " P256O ,Odd row parity bit 256" "0,1" textline " " bitfld.long 0x0 25. " P512O ,Odd row parity bit 512" "0,1" bitfld.long 0x0 26. " P1024O ,Odd row parity bit 1024" "0,1" textline " " bitfld.long 0x0 27. " P2048O ,Odd row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x21C++0x3 line.long 0x0 "GPMC_ECCj_RESULT_7,ECC result register" bitfld.long 0x0 0. " P1E ,Even column parity bit 1" "0,1" bitfld.long 0x0 1. " P2E ,Even column parity bit 2" "0,1" textline " " bitfld.long 0x0 2. " P4E ,Even column parity bit 4" "0,1" bitfld.long 0x0 3. " P8E ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x0 4. " P16E ,Even row parity bit 16" "0,1" bitfld.long 0x0 5. " P32E ,Even row parity bit 32" "0,1" textline " " bitfld.long 0x0 6. " P64E ,Even row parity bit 64" "0,1" bitfld.long 0x0 7. " P128E ,Even row parity bit 128" "0,1" textline " " bitfld.long 0x0 8. " P256E ,Even row parity bit 256" "0,1" bitfld.long 0x0 9. " P512E ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x0 10. " P1024E ,Even row parity bit 1024" "0,1" bitfld.long 0x0 11. " P2048E ,Even row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" textline " " bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd row parity bit 8" "0,1" bitfld.long 0x0 20. " P16O ,Odd row parity bit 16" "0,1" textline " " bitfld.long 0x0 21. " P32O ,Odd row parity bit 32" "0,1" bitfld.long 0x0 22. " P64O ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd row parity bit 128" "0,1" bitfld.long 0x0 24. " P256O ,Odd row parity bit 256" "0,1" textline " " bitfld.long 0x0 25. " P512O ,Odd row parity bit 512" "0,1" bitfld.long 0x0 26. " P1024O ,Odd row parity bit 1024" "0,1" textline " " bitfld.long 0x0 27. " P2048O ,Odd row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x220++0x3 line.long 0x0 "GPMC_ECCj_RESULT_8,ECC result register" bitfld.long 0x0 0. " P1E ,Even column parity bit 1" "0,1" bitfld.long 0x0 1. " P2E ,Even column parity bit 2" "0,1" textline " " bitfld.long 0x0 2. " P4E ,Even column parity bit 4" "0,1" bitfld.long 0x0 3. " P8E ,Even row parity bit 8" "0,1" textline " " bitfld.long 0x0 4. " P16E ,Even row parity bit 16" "0,1" bitfld.long 0x0 5. " P32E ,Even row parity bit 32" "0,1" textline " " bitfld.long 0x0 6. " P64E ,Even row parity bit 64" "0,1" bitfld.long 0x0 7. " P128E ,Even row parity bit 128" "0,1" textline " " bitfld.long 0x0 8. " P256E ,Even row parity bit 256" "0,1" bitfld.long 0x0 9. " P512E ,Even row parity bit 512" "0,1" textline " " bitfld.long 0x0 10. " P1024E ,Even row parity bit 1024" "0,1" bitfld.long 0x0 11. " P2048E ,Even row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" textline " " bitfld.long 0x0 12.--15. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1" textline " " bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1" bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1" textline " " bitfld.long 0x0 19. " P8O ,Odd row parity bit 8" "0,1" bitfld.long 0x0 20. " P16O ,Odd row parity bit 16" "0,1" textline " " bitfld.long 0x0 21. " P32O ,Odd row parity bit 32" "0,1" bitfld.long 0x0 22. " P64O ,Odd row parity bit 64" "0,1" textline " " bitfld.long 0x0 23. " P128O ,Odd row parity bit 128" "0,1" bitfld.long 0x0 24. " P256O ,Odd row parity bit 256" "0,1" textline " " bitfld.long 0x0 25. " P512O ,Odd row parity bit 512" "0,1" bitfld.long 0x0 26. " P1024O ,Odd row parity bit 1024" "0,1" textline " " bitfld.long 0x0 27. " P2048O ,Odd row parity bit 2048, only used for ECC computed on 512 bytes" "0,1" bitfld.long 0x0 28.--31. " RESERVED ,Write 0s for future compatibility. Read returns 0s." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x240++0x3 line.long 0x0 "GPMC_BCH_RESULT0_i_0,BCH ECC result (bits 0 to 31)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.byte 0x250++0x3 line.long 0x0 "GPMC_BCH_RESULT0_i_1,BCH ECC result (bits 0 to 31)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.byte 0x260++0x3 line.long 0x0 "GPMC_BCH_RESULT0_i_2,BCH ECC result (bits 0 to 31)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.byte 0x270++0x3 line.long 0x0 "GPMC_BCH_RESULT0_i_3,BCH ECC result (bits 0 to 31)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.byte 0x280++0x3 line.long 0x0 "GPMC_BCH_RESULT0_i_4,BCH ECC result (bits 0 to 31)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.byte 0x290++0x3 line.long 0x0 "GPMC_BCH_RESULT0_i_5,BCH ECC result (bits 0 to 31)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.byte 0x2A0++0x3 line.long 0x0 "GPMC_BCH_RESULT0_i_6,BCH ECC result (bits 0 to 31)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.byte 0x2B0++0x3 line.long 0x0 "GPMC_BCH_RESULT0_i_7,BCH ECC result (bits 0 to 31)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_0 ,BCH ECC result (bits 0 to 31)" group.byte 0x244++0x3 line.long 0x0 "GPMC_BCH_RESULT1_i_0,BCH ECC result (bits 32 to 63)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.byte 0x254++0x3 line.long 0x0 "GPMC_BCH_RESULT1_i_1,BCH ECC result (bits 32 to 63)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.byte 0x264++0x3 line.long 0x0 "GPMC_BCH_RESULT1_i_2,BCH ECC result (bits 32 to 63)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.byte 0x274++0x3 line.long 0x0 "GPMC_BCH_RESULT1_i_3,BCH ECC result (bits 32 to 63)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.byte 0x284++0x3 line.long 0x0 "GPMC_BCH_RESULT1_i_4,BCH ECC result (bits 32 to 63)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.byte 0x294++0x3 line.long 0x0 "GPMC_BCH_RESULT1_i_5,BCH ECC result (bits 32 to 63)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.byte 0x2A4++0x3 line.long 0x0 "GPMC_BCH_RESULT1_i_6,BCH ECC result (bits 32 to 63)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.byte 0x2B4++0x3 line.long 0x0 "GPMC_BCH_RESULT1_i_7,BCH ECC result (bits 32 to 63)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_1 ,BCH ECC result (bits 32 to 63)" group.byte 0x248++0x3 line.long 0x0 "GPMC_BCH_RESULT2_i_0,BCH ECC result (bits 64 to 95)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.byte 0x258++0x3 line.long 0x0 "GPMC_BCH_RESULT2_i_1,BCH ECC result (bits 64 to 95)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.byte 0x268++0x3 line.long 0x0 "GPMC_BCH_RESULT2_i_2,BCH ECC result (bits 64 to 95)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.byte 0x278++0x3 line.long 0x0 "GPMC_BCH_RESULT2_i_3,BCH ECC result (bits 64 to 95)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.byte 0x288++0x3 line.long 0x0 "GPMC_BCH_RESULT2_i_4,BCH ECC result (bits 64 to 95)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.byte 0x298++0x3 line.long 0x0 "GPMC_BCH_RESULT2_i_5,BCH ECC result (bits 64 to 95)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.byte 0x2A8++0x3 line.long 0x0 "GPMC_BCH_RESULT2_i_6,BCH ECC result (bits 64 to 95)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.byte 0x2B8++0x3 line.long 0x0 "GPMC_BCH_RESULT2_i_7,BCH ECC result (bits 64 to 95)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_2 ,BCH ECC result (bits 64 to 95)" group.byte 0x24C++0x3 line.long 0x0 "GPMC_BCH_RESULT3_i_0,BCH ECC result (bits 96 to 127)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.byte 0x25C++0x3 line.long 0x0 "GPMC_BCH_RESULT3_i_1,BCH ECC result (bits 96 to 127)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.byte 0x26C++0x3 line.long 0x0 "GPMC_BCH_RESULT3_i_2,BCH ECC result (bits 96 to 127)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.byte 0x27C++0x3 line.long 0x0 "GPMC_BCH_RESULT3_i_3,BCH ECC result (bits 96 to 127)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.byte 0x28C++0x3 line.long 0x0 "GPMC_BCH_RESULT3_i_4,BCH ECC result (bits 96 to 127)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.byte 0x29C++0x3 line.long 0x0 "GPMC_BCH_RESULT3_i_5,BCH ECC result (bits 96 to 127)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.byte 0x2AC++0x3 line.long 0x0 "GPMC_BCH_RESULT3_i_6,BCH ECC result (bits 96 to 127)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.byte 0x2BC++0x3 line.long 0x0 "GPMC_BCH_RESULT3_i_7,BCH ECC result (bits 96 to 127)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 127)" group.byte 0x2D0++0x3 line.long 0x0 "GPMC_BCH_SWDATA,This register is used to directly pass data to the BCH ECC calculator without accessing the actual NAND flash interface." hexmask.long.word 0x0 0.--15. 1. " BCH_DATA ,Data to be included in the BCH calculation Only bits 0 to 7 are considered if the calculator is configured to use 8-bit data (GPMC_ECC_CONFIG[7] ECC16B = 0)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x300++0x3 line.long 0x0 "GPMC_BCH_RESULT4_i_0,BCH ECC result (bits 128 to 159)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.byte 0x310++0x3 line.long 0x0 "GPMC_BCH_RESULT4_i_1,BCH ECC result (bits 128 to 159)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.byte 0x320++0x3 line.long 0x0 "GPMC_BCH_RESULT4_i_2,BCH ECC result (bits 128 to 159)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.byte 0x330++0x3 line.long 0x0 "GPMC_BCH_RESULT4_i_3,BCH ECC result (bits 128 to 159)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.byte 0x340++0x3 line.long 0x0 "GPMC_BCH_RESULT4_i_4,BCH ECC result (bits 128 to 159)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.byte 0x350++0x3 line.long 0x0 "GPMC_BCH_RESULT4_i_5,BCH ECC result (bits 128 to 159)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.byte 0x360++0x3 line.long 0x0 "GPMC_BCH_RESULT4_i_6,BCH ECC result (bits 128 to 159)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.byte 0x370++0x3 line.long 0x0 "GPMC_BCH_RESULT4_i_7,BCH ECC result (bits 128 to 159)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_4 ,BCH ECC result (bits 128 to 159)" group.byte 0x304++0x3 line.long 0x0 "GPMC_BCH_RESULT5_i_0,BCH ECC result (bits 160 to 191)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.byte 0x314++0x3 line.long 0x0 "GPMC_BCH_RESULT5_i_1,BCH ECC result (bits 160 to 191)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.byte 0x324++0x3 line.long 0x0 "GPMC_BCH_RESULT5_i_2,BCH ECC result (bits 160 to 191)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.byte 0x334++0x3 line.long 0x0 "GPMC_BCH_RESULT5_i_3,BCH ECC result (bits 160 to 191)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.byte 0x344++0x3 line.long 0x0 "GPMC_BCH_RESULT5_i_4,BCH ECC result (bits 160 to 191)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.byte 0x354++0x3 line.long 0x0 "GPMC_BCH_RESULT5_i_5,BCH ECC result (bits 160 to 191)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.byte 0x364++0x3 line.long 0x0 "GPMC_BCH_RESULT5_i_6,BCH ECC result (bits 160 to 191)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.byte 0x374++0x3 line.long 0x0 "GPMC_BCH_RESULT5_i_7,BCH ECC result (bits 160 to 191)" hexmask.long 0x0 0.--31. 1. " BCH_RESULT_5 ,BCH ECC result (bits 160 to 191)" group.byte 0x308++0x3 line.long 0x0 "GPMC_BCH_RESULT6_i_0,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x318++0x3 line.long 0x0 "GPMC_BCH_RESULT6_i_1,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x328++0x3 line.long 0x0 "GPMC_BCH_RESULT6_i_2,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x338++0x3 line.long 0x0 "GPMC_BCH_RESULT6_i_3,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x348++0x3 line.long 0x0 "GPMC_BCH_RESULT6_i_4,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x358++0x3 line.long 0x0 "GPMC_BCH_RESULT6_i_5,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x368++0x3 line.long 0x0 "GPMC_BCH_RESULT6_i_6,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." group.byte 0x378++0x3 line.long 0x0 "GPMC_BCH_RESULT6_i_7,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 0.--15. 1. " BCH_RESULT_6 ,BCH ECC result (bits 192 to 207)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0s for future compatibility. Read returns 0s." width 0x0B tree.end tree "ELM" base ad:0x48078000 width 29. group.byte 0x0++0x3 line.long 0x0 "ELM_REVISION,This register contains the IP revision code. (A write or reset of to this register has no effect.)" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision (TI internal data)" group.byte 0x10++0x3 line.long 0x0 "ELM_SYSCONFIG,This register allows controlling various parameters of the OCP interface." bitfld.long 0x0 0. " AUTOGATING ,Internal OCP clock gating strategy (no module visible effect other than saving power)" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Module software reset This bit is automatically reset by hardware (during reads, it always returns 0). It has same effect as the OCP hardware reset." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Slave interface power management (IDLE req/ack control)" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. " CLOCKACTIVITYOCP ,OCP clock activity when module is in IDLE mode (during wake-up mode period)" "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "ELM_SYSSTATUS,Internal reset monitoring (OCP domain) Undefined since: From hardware perspective, the reset state is 0. From software user perspective, when the accessible module is 1." bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring (OCP domain) Undefined since: From hardware perspective, the reset state is 0. From software user perspective, when the accessible module is 1." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "ELM_IRQSTATUS,Interrupt status. This register doubles as a status register for the error-location processes." bitfld.long 0x0 0. " LOC_VALID_0 ,Error-location status for syndrome polynomial 0" "0,1" bitfld.long 0x0 1. " LOC_VALID_1 ,Error-location status for syndrome polynomial 1" "0,1" textline " " bitfld.long 0x0 2. " LOC_VALID_2 ,Error-location status for syndrome polynomial 2" "0,1" bitfld.long 0x0 3. " LOC_VALID_3 ,Error-location status for syndrome polynomial 3" "0,1" textline " " bitfld.long 0x0 4. " LOC_VALID_4 ,Error-location status for syndrome polynomial 4" "0,1" bitfld.long 0x0 5. " LOC_VALID_5 ,Error-location status for syndrome polynomial 5" "0,1" textline " " bitfld.long 0x0 6. " LOC_VALID_6 ,Error-location status for syndrome polynomial 6" "0,1" bitfld.long 0x0 7. " LOC_VALID_7 ,Error-location status for syndrome polynomial 7 Read 0x0: No syndrome processed or process in progress Read 0x1: Error-location process completed Write 0x0: No effect Write 0x1: Clear interrupt" "0,1" textline " " bitfld.long 0x0 8. " PAGE_VALID ,Error-location status for a full page, based on the mask definition Read 0x0: Error locations invalid for all polynomials enabled in the ECC_INTERRUPT_MASK register Read 0x1: All error locations valid Write 0x0: No effect Write 0x1: Clear interrupt" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "ELM_IRQENABLE,Interrupt enable" bitfld.long 0x0 0. " LOCATION_MASK_0 ,Error-location interrupt mask bit for syndrome polynomial 0 0: Disable interrupt 1: Enable interrupt" "0,1" bitfld.long 0x0 1. " LOCATION_MASK_1 ,Error-location interrupt mask bit for syndrome polynomial 1" "0,1" textline " " bitfld.long 0x0 2. " LOCATION_MASK_2 ,Error-location interrupt mask bit for syndrome polynomial 2" "0,1" bitfld.long 0x0 3. " LOCATION_MASK_3 ,Error-location interrupt mask bit for syndrome polynomial 3" "0,1" textline " " bitfld.long 0x0 4. " LOCATION_MASK_4 ,Error-location interrupt mask bit for syndrome polynomial 4" "0,1" bitfld.long 0x0 5. " LOCATION_MASK_5 ,Error-location interrupt mask bit for syndrome polynomial 5" "0,1" textline " " bitfld.long 0x0 6. " LOCATION_MASK_6 ,Error-location interrupt mask bit for syndrome polynomial 6" "0,1" bitfld.long 0x0 7. " LOCATION_MASK_7 ,Error-location interrupt mask bit for syndrome polynomial 7" "0,1" textline " " bitfld.long 0x0 8. " PAGE_MASK ,Page interrupt mask bit 0: Disable interrupt 1: Enable interrupt" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "ELM_LOCATION_CONFIG,ECC algorithm parameters" bitfld.long 0x0 0.--1. " ECC_BCH_LEVEL ,Error correction level 0x0: 4 bits 0x1: 8 bits 0x2: 16 bits 0x3: Reserved" "0,1,2,3" hexmask.long.word 0x0 2.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--26. 1. " ECC_SIZE ,Maximum size of the buffers for which the error-location engine is used, in number of nibbles (4-bit entities)" bitfld.long 0x0 27.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x80++0x3 line.long 0x0 "ELM_PAGE_CTRL,Page definition" bitfld.long 0x0 0. " SECTOR_0 ,Set to 1 if syndrome polynomial 0 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x0 1. " SECTOR_1 ,Set to 1 if syndrome polynomial 1 is part of the page in page mode. Must be 0 in continuous mode." "0,1" textline " " bitfld.long 0x0 2. " SECTOR_2 ,Set to 1 if syndrome polynomial 2 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x0 3. " SECTOR_3 ,Set to 1 if syndrome polynomial 3 is part of the page in page mode. Must be 0 in continuous mode." "0,1" textline " " bitfld.long 0x0 4. " SECTOR_4 ,Set to 1 if syndrome polynomial 4 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x0 5. " SECTOR_5 ,Set to 1 if syndrome polynomial 5 is part of the page in page mode. Must be 0 in continuous mode." "0,1" textline " " bitfld.long 0x0 6. " SECTOR_6 ,Set to 1 if syndrome polynomial 6 is part of the page in page mode. Must be 0 in continuous mode." "0,1" bitfld.long 0x0 7. " SECTOR_7 ,Set to 1 if syndrome polynomial 7 is part of the page in page mode. Must be 0 in continuous mode." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x400++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_0_i_0,Input syndrome polynomial bits 0 to 31." hexmask.long 0x0 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.byte 0x440++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_0_i_1,Input syndrome polynomial bits 0 to 31." hexmask.long 0x0 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.byte 0x480++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_0_i_2,Input syndrome polynomial bits 0 to 31." hexmask.long 0x0 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.byte 0x4C0++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_0_i_3,Input syndrome polynomial bits 0 to 31." hexmask.long 0x0 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.byte 0x500++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_0_i_4,Input syndrome polynomial bits 0 to 31." hexmask.long 0x0 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.byte 0x540++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_0_i_5,Input syndrome polynomial bits 0 to 31." hexmask.long 0x0 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.byte 0x580++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_0_i_6,Input syndrome polynomial bits 0 to 31." hexmask.long 0x0 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.byte 0x5C0++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_0_i_7,Input syndrome polynomial bits 0 to 31." hexmask.long 0x0 0.--31. 1. " SYNDROME_0 ,Syndrome bits 0 to 31" group.byte 0x404++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_1_i_0,Input syndrome polynomial bits 32 to 63." hexmask.long 0x0 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.byte 0x444++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_1_i_1,Input syndrome polynomial bits 32 to 63." hexmask.long 0x0 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.byte 0x484++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_1_i_2,Input syndrome polynomial bits 32 to 63." hexmask.long 0x0 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.byte 0x4C4++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_1_i_3,Input syndrome polynomial bits 32 to 63." hexmask.long 0x0 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.byte 0x504++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_1_i_4,Input syndrome polynomial bits 32 to 63." hexmask.long 0x0 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.byte 0x544++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_1_i_5,Input syndrome polynomial bits 32 to 63." hexmask.long 0x0 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.byte 0x584++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_1_i_6,Input syndrome polynomial bits 32 to 63." hexmask.long 0x0 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.byte 0x5C4++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_1_i_7,Input syndrome polynomial bits 32 to 63." hexmask.long 0x0 0.--31. 1. " SYNDROME_1 ,Syndrome bits 32 to 63" group.byte 0x408++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_2_i_0,Input syndrome polynomial bits 64 to 95." hexmask.long 0x0 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.byte 0x448++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_2_i_1,Input syndrome polynomial bits 64 to 95." hexmask.long 0x0 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.byte 0x488++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_2_i_2,Input syndrome polynomial bits 64 to 95." hexmask.long 0x0 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.byte 0x4C8++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_2_i_3,Input syndrome polynomial bits 64 to 95." hexmask.long 0x0 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.byte 0x508++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_2_i_4,Input syndrome polynomial bits 64 to 95." hexmask.long 0x0 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.byte 0x548++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_2_i_5,Input syndrome polynomial bits 64 to 95." hexmask.long 0x0 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.byte 0x588++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_2_i_6,Input syndrome polynomial bits 64 to 95." hexmask.long 0x0 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.byte 0x5C8++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_2_i_7,Input syndrome polynomial bits 64 to 95." hexmask.long 0x0 0.--31. 1. " SYNDROME_2 ,Syndrome bits 64 to 95" group.byte 0x40C++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_3_i_0,Input syndrome polynomial bits 96 to 127" hexmask.long 0x0 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.byte 0x44C++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_3_i_1,Input syndrome polynomial bits 96 to 127" hexmask.long 0x0 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.byte 0x48C++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_3_i_2,Input syndrome polynomial bits 96 to 127" hexmask.long 0x0 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.byte 0x4CC++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_3_i_3,Input syndrome polynomial bits 96 to 127" hexmask.long 0x0 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.byte 0x50C++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_3_i_4,Input syndrome polynomial bits 96 to 127" hexmask.long 0x0 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.byte 0x54C++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_3_i_5,Input syndrome polynomial bits 96 to 127" hexmask.long 0x0 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.byte 0x58C++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_3_i_6,Input syndrome polynomial bits 96 to 127" hexmask.long 0x0 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.byte 0x5CC++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_3_i_7,Input syndrome polynomial bits 96 to 127" hexmask.long 0x0 0.--31. 1. " SYNDROME_3 ,Syndrome bits 96 to 127" group.byte 0x410++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_4_i_0,Input syndrome polynomial bits 128 to 159." hexmask.long 0x0 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.byte 0x450++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_4_i_1,Input syndrome polynomial bits 128 to 159." hexmask.long 0x0 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.byte 0x490++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_4_i_2,Input syndrome polynomial bits 128 to 159." hexmask.long 0x0 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.byte 0x4D0++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_4_i_3,Input syndrome polynomial bits 128 to 159." hexmask.long 0x0 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.byte 0x510++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_4_i_4,Input syndrome polynomial bits 128 to 159." hexmask.long 0x0 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.byte 0x550++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_4_i_5,Input syndrome polynomial bits 128 to 159." hexmask.long 0x0 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.byte 0x590++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_4_i_6,Input syndrome polynomial bits 128 to 159." hexmask.long 0x0 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.byte 0x5D0++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_4_i_7,Input syndrome polynomial bits 128 to 159." hexmask.long 0x0 0.--31. 1. " SYNDROME_4 ,Syndrome bits 128 to 159" group.byte 0x414++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_5_i_0,Input syndrome polynomial bits 160 to 191." hexmask.long 0x0 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.byte 0x454++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_5_i_1,Input syndrome polynomial bits 160 to 191." hexmask.long 0x0 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.byte 0x494++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_5_i_2,Input syndrome polynomial bits 160 to 191." hexmask.long 0x0 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.byte 0x4D4++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_5_i_3,Input syndrome polynomial bits 160 to 191." hexmask.long 0x0 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.byte 0x514++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_5_i_4,Input syndrome polynomial bits 160 to 191." hexmask.long 0x0 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.byte 0x554++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_5_i_5,Input syndrome polynomial bits 160 to 191." hexmask.long 0x0 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.byte 0x594++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_5_i_6,Input syndrome polynomial bits 160 to 191." hexmask.long 0x0 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.byte 0x5D4++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_5_i_7,Input syndrome polynomial bits 160 to 191." hexmask.long 0x0 0.--31. 1. " SYNDROME_5 ,Syndrome bits 160 to 191" group.byte 0x418++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_6_i_0,Input syndrome polynomial bits 192 to 207." hexmask.long.word 0x0 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" bitfld.long 0x0 16. " SYNDROME_VALID ,Syndrome valid bit 0x0: This syndrome polynomial must not be processed. 0x1: This syndrome polynomial must be processed." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x458++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_6_i_1,Input syndrome polynomial bits 192 to 207." hexmask.long.word 0x0 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" bitfld.long 0x0 16. " SYNDROME_VALID ,Syndrome valid bit 0x0: This syndrome polynomial must not be processed. 0x1: This syndrome polynomial must be processed." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x498++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_6_i_2,Input syndrome polynomial bits 192 to 207." hexmask.long.word 0x0 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" bitfld.long 0x0 16. " SYNDROME_VALID ,Syndrome valid bit 0x0: This syndrome polynomial must not be processed. 0x1: This syndrome polynomial must be processed." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4D8++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_6_i_3,Input syndrome polynomial bits 192 to 207." hexmask.long.word 0x0 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" bitfld.long 0x0 16. " SYNDROME_VALID ,Syndrome valid bit 0x0: This syndrome polynomial must not be processed. 0x1: This syndrome polynomial must be processed." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x518++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_6_i_4,Input syndrome polynomial bits 192 to 207." hexmask.long.word 0x0 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" bitfld.long 0x0 16. " SYNDROME_VALID ,Syndrome valid bit 0x0: This syndrome polynomial must not be processed. 0x1: This syndrome polynomial must be processed." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x558++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_6_i_5,Input syndrome polynomial bits 192 to 207." hexmask.long.word 0x0 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" bitfld.long 0x0 16. " SYNDROME_VALID ,Syndrome valid bit 0x0: This syndrome polynomial must not be processed. 0x1: This syndrome polynomial must be processed." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x598++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_6_i_6,Input syndrome polynomial bits 192 to 207." hexmask.long.word 0x0 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" bitfld.long 0x0 16. " SYNDROME_VALID ,Syndrome valid bit 0x0: This syndrome polynomial must not be processed. 0x1: This syndrome polynomial must be processed." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x5D8++0x3 line.long 0x0 "ELM_SYNDROME_FRAGMENT_6_i_7,Input syndrome polynomial bits 192 to 207." hexmask.long.word 0x0 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207" bitfld.long 0x0 16. " SYNDROME_VALID ,Syndrome valid bit 0x0: This syndrome polynomial must not be processed. 0x1: This syndrome polynomial must be processed." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "ELM_LOCATION_STATUS_i_0,Exit status for the syndrome polynomial processing" bitfld.long 0x0 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " ECC_CORRECTABLE ,Error-location process exit status 0x0: ECC error-location process failed. Number of errors and error locations are invalid. 0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x900++0x3 line.long 0x0 "ELM_LOCATION_STATUS_i_1,Exit status for the syndrome polynomial processing" bitfld.long 0x0 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " ECC_CORRECTABLE ,Error-location process exit status 0x0: ECC error-location process failed. Number of errors and error locations are invalid. 0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xA00++0x3 line.long 0x0 "ELM_LOCATION_STATUS_i_2,Exit status for the syndrome polynomial processing" bitfld.long 0x0 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " ECC_CORRECTABLE ,Error-location process exit status 0x0: ECC error-location process failed. Number of errors and error locations are invalid. 0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xB00++0x3 line.long 0x0 "ELM_LOCATION_STATUS_i_3,Exit status for the syndrome polynomial processing" bitfld.long 0x0 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " ECC_CORRECTABLE ,Error-location process exit status 0x0: ECC error-location process failed. Number of errors and error locations are invalid. 0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC00++0x3 line.long 0x0 "ELM_LOCATION_STATUS_i_4,Exit status for the syndrome polynomial processing" bitfld.long 0x0 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " ECC_CORRECTABLE ,Error-location process exit status 0x0: ECC error-location process failed. Number of errors and error locations are invalid. 0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xD00++0x3 line.long 0x0 "ELM_LOCATION_STATUS_i_5,Exit status for the syndrome polynomial processing" bitfld.long 0x0 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " ECC_CORRECTABLE ,Error-location process exit status 0x0: ECC error-location process failed. Number of errors and error locations are invalid. 0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xE00++0x3 line.long 0x0 "ELM_LOCATION_STATUS_i_6,Exit status for the syndrome polynomial processing" bitfld.long 0x0 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " ECC_CORRECTABLE ,Error-location process exit status 0x0: ECC error-location process failed. Number of errors and error locations are invalid. 0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xF00++0x3 line.long 0x0 "ELM_LOCATION_STATUS_i_7,Exit status for the syndrome polynomial processing" bitfld.long 0x0 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " ECC_CORRECTABLE ,Error-location process exit status 0x0: ECC error-location process failed. Number of errors and error locations are invalid. 0x1: All errors were successfully located. Number of errors and error locations are valid." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x880++0x3 line.long 0x0 "ELM_ERROR_LOCATION_0_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x980++0x3 line.long 0x0 "ELM_ERROR_LOCATION_0_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA80++0x3 line.long 0x0 "ELM_ERROR_LOCATION_0_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB80++0x3 line.long 0x0 "ELM_ERROR_LOCATION_0_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xC80++0x3 line.long 0x0 "ELM_ERROR_LOCATION_0_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xD80++0x3 line.long 0x0 "ELM_ERROR_LOCATION_0_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xE80++0x3 line.long 0x0 "ELM_ERROR_LOCATION_0_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xF80++0x3 line.long 0x0 "ELM_ERROR_LOCATION_0_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x884++0x3 line.long 0x0 "ELM_ERROR_LOCATION_1_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x984++0x3 line.long 0x0 "ELM_ERROR_LOCATION_1_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA84++0x3 line.long 0x0 "ELM_ERROR_LOCATION_1_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB84++0x3 line.long 0x0 "ELM_ERROR_LOCATION_1_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xC84++0x3 line.long 0x0 "ELM_ERROR_LOCATION_1_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xD84++0x3 line.long 0x0 "ELM_ERROR_LOCATION_1_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xE84++0x3 line.long 0x0 "ELM_ERROR_LOCATION_1_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xF84++0x3 line.long 0x0 "ELM_ERROR_LOCATION_1_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x888++0x3 line.long 0x0 "ELM_ERROR_LOCATION_2_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x988++0x3 line.long 0x0 "ELM_ERROR_LOCATION_2_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA88++0x3 line.long 0x0 "ELM_ERROR_LOCATION_2_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB88++0x3 line.long 0x0 "ELM_ERROR_LOCATION_2_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xC88++0x3 line.long 0x0 "ELM_ERROR_LOCATION_2_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xD88++0x3 line.long 0x0 "ELM_ERROR_LOCATION_2_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xE88++0x3 line.long 0x0 "ELM_ERROR_LOCATION_2_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xF88++0x3 line.long 0x0 "ELM_ERROR_LOCATION_2_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x88C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_3_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x98C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_3_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA8C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_3_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB8C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_3_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xC8C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_3_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xD8C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_3_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xE8C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_3_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xF8C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_3_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x890++0x3 line.long 0x0 "ELM_ERROR_LOCATION_4_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x990++0x3 line.long 0x0 "ELM_ERROR_LOCATION_4_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA90++0x3 line.long 0x0 "ELM_ERROR_LOCATION_4_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB90++0x3 line.long 0x0 "ELM_ERROR_LOCATION_4_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xC90++0x3 line.long 0x0 "ELM_ERROR_LOCATION_4_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xD90++0x3 line.long 0x0 "ELM_ERROR_LOCATION_4_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xE90++0x3 line.long 0x0 "ELM_ERROR_LOCATION_4_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xF90++0x3 line.long 0x0 "ELM_ERROR_LOCATION_4_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x894++0x3 line.long 0x0 "ELM_ERROR_LOCATION_5_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x994++0x3 line.long 0x0 "ELM_ERROR_LOCATION_5_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA94++0x3 line.long 0x0 "ELM_ERROR_LOCATION_5_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB94++0x3 line.long 0x0 "ELM_ERROR_LOCATION_5_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xC94++0x3 line.long 0x0 "ELM_ERROR_LOCATION_5_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xD94++0x3 line.long 0x0 "ELM_ERROR_LOCATION_5_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xE94++0x3 line.long 0x0 "ELM_ERROR_LOCATION_5_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xF94++0x3 line.long 0x0 "ELM_ERROR_LOCATION_5_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x898++0x3 line.long 0x0 "ELM_ERROR_LOCATION_6_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x998++0x3 line.long 0x0 "ELM_ERROR_LOCATION_6_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA98++0x3 line.long 0x0 "ELM_ERROR_LOCATION_6_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB98++0x3 line.long 0x0 "ELM_ERROR_LOCATION_6_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xC98++0x3 line.long 0x0 "ELM_ERROR_LOCATION_6_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xD98++0x3 line.long 0x0 "ELM_ERROR_LOCATION_6_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xE98++0x3 line.long 0x0 "ELM_ERROR_LOCATION_6_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xF98++0x3 line.long 0x0 "ELM_ERROR_LOCATION_6_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x89C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_7_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x99C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_7_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xA9C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_7_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xB9C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_7_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xC9C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_7_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xD9C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_7_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xE9C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_7_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xF9C++0x3 line.long 0x0 "ELM_ERROR_LOCATION_7_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8A0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_8_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x9A0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_8_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xAA0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_8_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xBA0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_8_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xCA0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_8_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xDA0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_8_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xEA0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_8_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xFA0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_8_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8A4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_9_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x9A4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_9_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xAA4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_9_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xBA4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_9_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xCA4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_9_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xDA4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_9_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xEA4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_9_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xFA4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_9_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8A8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_10_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x9A8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_10_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xAA8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_10_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xBA8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_10_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xCA8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_10_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xDA8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_10_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xEA8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_10_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xFA8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_10_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8AC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_11_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x9AC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_11_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xAAC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_11_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xBAC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_11_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xCAC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_11_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xDAC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_11_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xEAC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_11_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xFAC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_11_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8B0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_12_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x9B0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_12_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xAB0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_12_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xBB0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_12_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xCB0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_12_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xDB0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_12_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xEB0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_12_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xFB0++0x3 line.long 0x0 "ELM_ERROR_LOCATION_12_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8B4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_13_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x9B4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_13_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xAB4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_13_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xBB4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_13_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xCB4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_13_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xDB4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_13_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xEB4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_13_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xFB4++0x3 line.long 0x0 "ELM_ERROR_LOCATION_13_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8B8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_14_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x9B8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_14_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xAB8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_14_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xBB8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_14_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xCB8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_14_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xDB8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_14_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xEB8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_14_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xFB8++0x3 line.long 0x0 "ELM_ERROR_LOCATION_14_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x8BC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_15_i_0,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x9BC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_15_i_1,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xABC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_15_i_2,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xBBC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_15_i_3,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xCBC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_15_i_4,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xDBC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_15_i_5,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xEBC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_15_i_6,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0xFBC++0x3 line.long 0x0 "ELM_ERROR_LOCATION_15_i_7,Error-location register" hexmask.long.word 0x0 0.--12. 1. " ECC_ERROR_LOCATION ,Error-location bit address" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "OCMC_RAM1" base ad:0x48804000 width 37. group.byte 0x0++0x3 line.long 0x0 "OCMC_ECC_PID,OCMC_ECC_PID" hexmask.long 0x0 0.--31. 1. " REVISION ,TI internal data" group.byte 0x4++0x3 line.long 0x0 "OCMC_SYSCONFIG_PM,OCMC_SYSCONFIG_PM" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "OCMC_SYSCONFIG_RST,OCMC_SYSCONFIG_RST" bitfld.long 0x0 0. " SW_RST ,Software reset of the OCM controller configuration and history logic (does not reset L4 interface)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "OCMC_MEM_SIZE_READ,This register provides the status of the OCM Controller configuration." bitfld.long 0x0 0.--4. " MEM_SIZE_128K_CNT ,This bit field indicates how many 128KiB memory blocks are present in the SRAM. Access beyond the memory size reported in the MEM_SIZE_128K_CNT bit field results in an address error interrupt. 0x1: One 128KiB memory block 0x2: Two 128KiB memory blocks ... 0x14: 20 memory blocks of 128KiB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " MEM_ECC_ENABLE ,Indicates whether ECC is supported or not." "0,1" bitfld.long 0x0 9. " MEM_CBUF_ENABLE ,Indicates whether CBUF is supported or not." "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12.--16. " VBUF_ADDR_MSB ,This bit field returns the MSB bit of the valid VBUF address range. The default value of 23 means that the valid VBUF address range is from 0x8000 0000 to 0x80FF FFFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "INTR0_STATUS_RAW_SET,This register contains the raw interrupt status. Read indicates RAW interrupt status (0=inactive, 1=active). Writing 1 will SET the corresponding raw status bit (soft interrupt set). Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "INTR0_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive, 1=active). Writing 1 will CLEAR the corresponding enabled status bit. Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "INTR0_ENABLE_SET,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will set the corresponding interrupt enable bit. Writing 0 has no effect. Interrupt_enable_set" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "INTR0_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will clear interrupt enabled. Writing 0 has no effect. Interrupt_enable_clear" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "OCMC_INTR0_EOI,This register contains the EOI vector." bitfld.long 0x0 0. " EOI_VECTOR ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "INTR1_STATUS_RAW_SET,This register contains the raw interrupt status. Read indicates RAW interrupt status (0=inactive, 1=active). Writing 1 will SET the corresponding raw status bit (soft interrupt set). Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "INTR1_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive, 1=active). Writing 1 will CLEAR the corresponding enabled status bit. Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "INTR1_ENABLE_SET,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will set the corresponding interrupt enable bit. Writing 0 has no effect. Interrupt_enable_set" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "INTR1_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will clear interrupt enabled. Writing 0 has no effect. Interrupt_enable_clear" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "OCMC_INTR1_EOI,This register contains the EOI vector." bitfld.long 0x0 0. " EOI_VECTOR ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "CFG_OCMC_ECC,CFG_OCMC_ECC" bitfld.long 0x0 0.--2. " CFG_OCMC_MODE ,OCM Controller memory access modes. 0x0: Non-ECC mode (data access) 0x1: Non-ECC mode (code access) 0x2: Full ECC enabled mode 0x3: Block ECC enabled mode 0x4-0x7: Reserved (internally defaults to 0x0 mode)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " CFG_ECC_SEC_AUTO_CORRECT ,SEC error auto correction mode. Enables the OCM Controller to automatically update the wrong data word with the corrected word. 0x0: Disable 0x1: Enable (If the OCM Controller is performing a read-modify operation for a sub-128b write to an ECC enabled memory, the error found during the read phase will be corrected always regardless of the value of this bit)" "0,1" textline " " bitfld.long 0x0 4. " CFG_ECC_ERR_SRESP_EN ,ECC non-correctable error SRESP enable. Enables ERR return on L3 OCP SRESP when a non-correctable data (DED) or address error is detected. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 5. " CFG_ECC_OPT_NON_ECC_READ ,Optimize read latency for non-ECC read. Returns the data one cycle faster if the read access is from a non-ECC enabled space. 0x0: Disable 0x1: Enable" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "CFG_OCMC_ECC_MEM_BLK,CFG_OCMC_ECC_MEM_BLK" hexmask.long.tbyte 0x0 0.--19. 1. " CFG_ECC_ENABLED_128K_BLK ,ECC memory block enable bits. The active level of each bit is 0x1. Bit [0] -> Address offset range 0x0 to 0x1FFFF Bit [1] -> Address offset range 0x20000 to 0x3FFFF ... Bit [19] -> Address offset range 0x260000 to 0x27FFFF" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CFG_OCMC_ECC_ERROR,CFG_OCMC_ECC_ERROR" hexmask.long.word 0x0 0.--15. 1. " CFG_SEC_CNT_MAX ,Number of SEC error to trigger an interrupt (The value configured must be > 0 to generate an interrupt)." bitfld.long 0x0 16.--19. " CFG_DED_CNT_MAX ,Number of DED errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " CFG_ADDR_ERR_CNT_MAX ,Number of ADDR errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " CFG_DISCARD_DUP_ADDR ,Do not save duplicate error address. This bit applies to the SEC, DED and ADDRERR FIFOs. 0x0: Save the duplicated addresses 0x1: Save only the unique addresses" "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "CFG_OCMC_ECC_CLEAR_HIST,CFG_OCMC_ECC_CLEAR_HIST" bitfld.long 0x0 0. " CLEAR_SEC_ERR_CNT ,Clear stored single error correction history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the" "0,1" bitfld.long 0x0 1. " CLEAR_DED_ERR_CNT ,Clear stored double error detection (DED) history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the" "0,1" textline " " bitfld.long 0x0 2. " CLEAR_ADDR_ERR_CNT ,Clear stored address error history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the" "0,1" bitfld.long 0x0 3. " CLEAR_SEC_BIT_DISTR ,Clear stored single error correction (SEC) bit distribution history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Cleares the following registers:" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "STATUS_ERROR_CNT,OCM Controller error status" hexmask.long.word 0x0 0.--15. 1. " SEC_ERROR_CNT ,Counter for the single errors occured. This bit field is reset when 0x1 is written to the" bitfld.long 0x0 16.--19. " DED_ERROR_CNT ,Counter for the double error detections. This bit field is reset when 0x1 is written to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ADDR_ERROR_CNT ,Counter for the address errors found. This bit field is reset when 0x1 is written to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "STATUS_SEC_ERROR_TRACE,SEC error 128-bit memory address" hexmask.long.tbyte 0x0 0.--17. 1. " ADDRESS_128BIT ,SEC error 128-bit memory address (Read from the SEC error address trace fifo)" bitfld.long 0x0 18. " VALID ,SEC FIFO valid addres indication." "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "STATUS_DED_ERROR_TRACE,DED error 128-bit memory address" hexmask.long.tbyte 0x0 0.--17. 1. " ADDRESS_128BIT ,DED error 128-bit memory address (Read from the DED error address trace fifo)" bitfld.long 0x0 18. " VALID ,DED FIFO valid addres indication. 0x0: The DED FIFO is empty 0x1: There is a valid address in the DED FIFO" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "STATUS_ADDR_TRANSLATION_ERROR_TRACE,ADDR error 128-bit memory address" hexmask.long.tbyte 0x0 0.--17. 1. " ADDRESS_128BIT ,ADDR error 128-bit memory address (Read from the ADDR error address trace fifo)" bitfld.long 0x0 18. " VALID ,ADDRERR FIFO valid addres indication. 0x0: The ADDRERR FIFO is empty 0x1: There is a valid address in the ADDRERR FIFO" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_0,SEC data error bit distribution status [31:0]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xA4++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_1,SEC data error bit distribution status [63:32]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xA8++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_2,SEC data error bit distribution status [95:64]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xAC++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_3,SEC data error bit distribution status [127:96]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xB0++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_4,SEC ecc code error bit distribution status [7:0]" hexmask.long.byte 0x0 0.--7. 1. " SEC_ECC_CODE_ERROR_FOUND ,ECC Code (excluding the parity bit) error distribution [7:0]. For each bit: 0x0: SEC error not found 0x1: SEC error found In the corresponding bit location" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x200++0x3 line.long 0x0 "CFG_OCMC_CBUF_EN,CBUF mode enable register" bitfld.long 0x0 0. " CBUF_MODE_EN ,CBUF Mode Enable. 0x0: Disable all CBUF address translation 0x1: Enable CBUF address translation" "0,1" bitfld.long 0x0 1. " CBUF_DEBUG_EN ,CBUF Debug Enable Mode. 0x0: Default Normal mode. All CBUF accesses with MReqDebug=1 are rejected. 0x1: Debug mode. MReqDebug Interconnect qualifier is ignored." "0,1" textline " " bitfld.long 0x0 2. " NEW_FRAME_SEL ,CBUF New Frame Event Definition Select. 0x0: New frame event flag is set when a VBUF access is made to the base address of the VBUF 0x1: New frame event flag is set when a VBUF access is made to the base CBUF slice address range of the VBUF" "0,1" hexmask.long.word 0x0 3.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " CBUF_EN_0 ,CBUF 0 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 17. " CBUF_EN_1 ,CBUF 1 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 18. " CBUF_EN_2 ,CBUF 2 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 19. " CBUF_EN_3 ,CBUF 3 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 20. " CBUF_EN_4 ,CBUF 4 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 21. " CBUF_EN_5 ,CBUF 5 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 22. " CBUF_EN_6 ,CBUF 6 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 23. " CBUF_EN_7 ,CBUF 7 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 24. " CBUF_EN_8 ,CBUF 8 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 25. " CBUF_EN_9 ,CBUF 9 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 26. " CBUF_EN_10 ,CBUF 10 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 27. " CBUF_EN_11 ,CBUF 11 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x204++0x3 line.long 0x0 "CFG_OCMC_CBUF_RESET,Writing 1 to bit n will set a reset bit to clear the corresponding CBUF_n address translation logic. Sliding CBUF frame tracking will be cleared so that the CBUF now points to the base of the virtual frame buffer. Normally, a reset is not required since the CBUF logic will clear itself when a VBUF access is to the base of the virtual frame." bitfld.long 0x0 0. " CBUF_RESET_0 ,cbuf_reset_0" "0,1" bitfld.long 0x0 1. " CBUF_RESET_1 ,cbuf_reset_1" "0,1" textline " " bitfld.long 0x0 2. " CBUF_RESET_2 ,cbuf_reset_2" "0,1" bitfld.long 0x0 3. " CBUF_RESET_3 ,cbuf_reset_3" "0,1" textline " " bitfld.long 0x0 4. " CBUF_RESET_4 ,cbuf_reset_4" "0,1" bitfld.long 0x0 5. " CBUF_RESET_5 ,cbuf_reset_5" "0,1" textline " " bitfld.long 0x0 6. " CBUF_RESET_6 ,cbuf_reset_6" "0,1" bitfld.long 0x0 7. " CBUF_RESET_7 ,cbuf_reset_7" "0,1" textline " " bitfld.long 0x0 8. " CBUF_RESET_8 ,cbuf_reset_8" "0,1" bitfld.long 0x0 9. " CBUF_RESET_9 ,cbuf_reset_9" "0,1" textline " " bitfld.long 0x0 10. " CBUF_RESET_10 ,cbuf_reset_10" "0,1" bitfld.long 0x0 11. " CBUF_RESET_11 ,cbuf_reset_11" "0,1" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "CFG_OCMC_CBUF_ERR_HANDLER,CFG_OCMC_CBUF_ERR_HANDLER" bitfld.long 0x0 0. " SHORT_FRAME_DETECT_CHECK_EN ,Short frame detection enable." "0,1" bitfld.long 0x0 1. " SHORT_FRAME_PREV_EOF_SEL ,0x0: previous frame EOF history is set if the last write address is equal to the VBUF frame end address 0x1: previous frame EOF history is set if the last write address is in the Last CBUF slice" "0,1" textline " " bitfld.long 0x0 2. " OVERFLOW_ERR_CHECK_EN ,Overflow chek enable." "0,1" bitfld.long 0x0 3. " UNDERFLOW_ERR_CHECK_EN ,Underflow chek enable." "0,1" textline " " bitfld.long 0x0 4.--5. " OVERFLOW_WRITE_HANDLER_SEL ,Overflow write handler selection. 0x0: Writes disabled only on CBUF_overflow_wrap cases until next write to virtual frame start address is detected 0x1: Writes disabled on all overflow cases until next write to virtual frame start address is detected 0x2: Writes serviced with CBUF pointer updated even on overflow condition 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 6.--7. " OVERFLOW_CHECK_REENABLE_SEL ,Overflow check re-enable selection. 0x0: Overflow check is disabled until next wtire to or read from virtual frame start address is detected 0x1: Overflow check is disabled until next write to virtual frame start address is detected 0x2: Overflow check is disabled until next read from virtual frame start address is detected 0x3: Overflow check is re-enabled immediately" "0,1,2,3" textline " " bitfld.long 0x0 8. " UNDERFLOW_LAST_CBUF_SLICE_DISABLE ,0x0: Check underflow even when read is from the last CBUF slice 0x1: Disable underflow check when read is from the last CBUF slice" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "STATUS_CBUF_WR_OUT_OF_RANGE_ERR,STATUS_CBUF_WR_OUT_OF_RANGE_ERR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,Indicates that the CBUF write address is out of the CBUF range. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "STATUS_CBUF_WR_VBUF_START_ERR,STATUS_CBUF_WR_VBUF_START_ERR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF write is not to the base address at vbuf access start. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "STATUS_CBUF_WR_ADDR_SEQ_ERROR,STATUS_CBUF_WR_ADDR_SEQ_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF address is not incrementing in raster scan order. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x218++0x3 line.long 0x0 "STATUS_CBUF_RD_OUT_OF_RANGE_ERROR,STATUS_CBUF_RD_OUT_OF_RANGE_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,Indicates that the CBUF read address is out of the CBUF range. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x21C++0x3 line.long 0x0 "STATUS_CBUF_VBUF_RD_START_ERROR,STATUS_CBUF_VBUF_RD_START_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF read is not from the base address at VBUF access start. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x220++0x3 line.long 0x0 "STATUS_CBUF_RD_ADDR_SEQ_ERROR,STATUS_CBUF_RD_ADDR_SEQ_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF read address is not incrementing in raster scan order. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "STATUS_CBUF_OVERFLOW_MID,STATUS_CBUF_OVERFLOW_MID" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF overflow condition detected in the middle of a frame. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x228++0x3 line.long 0x0 "STATUS_CBUF_OVERFLOW_WRAP,STATUS_CBUF_OVERFLOW_WRAP" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF overflow condition detected during buffer switching. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x22C++0x3 line.long 0x0 "STATUS_CBUF_UNDERFLOW,STATUS_CBUF_UNDERFLOW" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF underflow condition detected. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "STATUS_CBUF_SHORT_FRAME_DETECT,STATUS_CBUF_SHORT_FRAME_DETECT" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF short frame detected. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x240++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_0,CBUF_i_VBUF_START_ADDR_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x256++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_1,CBUF_i_VBUF_START_ADDR_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x26C++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_2,CBUF_i_VBUF_START_ADDR_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x282++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_3,CBUF_i_VBUF_START_ADDR_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x298++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_4,CBUF_i_VBUF_START_ADDR_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2AE++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_5,CBUF_i_VBUF_START_ADDR_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2C4++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_6,CBUF_i_VBUF_START_ADDR_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2DA++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_7,CBUF_i_VBUF_START_ADDR_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2F0++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_8,CBUF_i_VBUF_START_ADDR_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x306++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_9,CBUF_i_VBUF_START_ADDR_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x31C++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_10,CBUF_i_VBUF_START_ADDR_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x332++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_11,CBUF_i_VBUF_START_ADDR_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x244++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_0,CBUF_i_VBUF_END_ADDR_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x25A++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_1,CBUF_i_VBUF_END_ADDR_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x270++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_2,CBUF_i_VBUF_END_ADDR_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x286++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_3,CBUF_i_VBUF_END_ADDR_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x29C++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_4,CBUF_i_VBUF_END_ADDR_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2B2++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_5,CBUF_i_VBUF_END_ADDR_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2C8++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_6,CBUF_i_VBUF_END_ADDR_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2DE++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_7,CBUF_i_VBUF_END_ADDR_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2F4++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_8,CBUF_i_VBUF_END_ADDR_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x30A++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_9,CBUF_i_VBUF_END_ADDR_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x320++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_10,CBUF_i_VBUF_END_ADDR_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x336++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_11,CBUF_i_VBUF_END_ADDR_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x248++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_0,CBUF_i_OCMC_START_ADDR_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x25E++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_1,CBUF_i_OCMC_START_ADDR_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x274++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_2,CBUF_i_OCMC_START_ADDR_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x28A++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_3,CBUF_i_OCMC_START_ADDR_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2A0++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_4,CBUF_i_OCMC_START_ADDR_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2B6++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_5,CBUF_i_OCMC_START_ADDR_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2CC++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_6,CBUF_i_OCMC_START_ADDR_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2E2++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_7,CBUF_i_OCMC_START_ADDR_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2F8++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_8,CBUF_i_OCMC_START_ADDR_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x30E++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_9,CBUF_i_OCMC_START_ADDR_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x324++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_10,CBUF_i_OCMC_START_ADDR_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x33A++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_11,CBUF_i_OCMC_START_ADDR_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x24C++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_0,CBUF_i_OCMC_BUF_SIZE_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x262++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_1,CBUF_i_OCMC_BUF_SIZE_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x278++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_2,CBUF_i_OCMC_BUF_SIZE_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x28E++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_3,CBUF_i_OCMC_BUF_SIZE_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2A4++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_4,CBUF_i_OCMC_BUF_SIZE_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2BA++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_5,CBUF_i_OCMC_BUF_SIZE_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2D0++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_6,CBUF_i_OCMC_BUF_SIZE_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2E6++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_7,CBUF_i_OCMC_BUF_SIZE_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2FC++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_8,CBUF_i_OCMC_BUF_SIZE_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x312++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_9,CBUF_i_OCMC_BUF_SIZE_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x328++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_10,CBUF_i_OCMC_BUF_SIZE_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x33E++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_11,CBUF_i_OCMC_BUF_SIZE_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x300++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_0,CBUF_k_LAST_WR_ADDR_0" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x308++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_1,CBUF_k_LAST_WR_ADDR_1" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x310++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_2,CBUF_k_LAST_WR_ADDR_2" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x318++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_3,CBUF_k_LAST_WR_ADDR_3" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x320++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_4,CBUF_k_LAST_WR_ADDR_4" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x328++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_5,CBUF_k_LAST_WR_ADDR_5" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x330++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_6,CBUF_k_LAST_WR_ADDR_6" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x338++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_7,CBUF_k_LAST_WR_ADDR_7" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x340++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_8,CBUF_k_LAST_WR_ADDR_8" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x348++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_9,CBUF_k_LAST_WR_ADDR_9" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x350++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_10,CBUF_k_LAST_WR_ADDR_10" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x358++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_11,CBUF_k_LAST_WR_ADDR_11" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x304++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_0,CBUF_k_LAST_RD_ADDR_0" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x30C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_1,CBUF_k_LAST_RD_ADDR_1" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x314++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_2,CBUF_k_LAST_RD_ADDR_2" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x31C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_3,CBUF_k_LAST_RD_ADDR_3" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x324++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_4,CBUF_k_LAST_RD_ADDR_4" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x32C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_5,CBUF_k_LAST_RD_ADDR_5" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x334++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_6,CBUF_k_LAST_RD_ADDR_6" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x33C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_7,CBUF_k_LAST_RD_ADDR_7" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x344++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_8,CBUF_k_LAST_RD_ADDR_8" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x34C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_9,CBUF_k_LAST_RD_ADDR_9" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x354++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_10,CBUF_k_LAST_RD_ADDR_10" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x35C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_11,CBUF_k_LAST_RD_ADDR_11" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x360++0x3 line.long 0x0 "LAST_ILLEGAL_OCMC_ADDR,LAST_ILLEGAL_OCMC_ADDR" hexmask.long 0x0 0.--31. 1. " ADDR ,Last Illegal OCMC Address. This register returns the OCMC L3_MAIN address of the last access that was invalidated due to an OUT_OF_RANGE_ERR_FOUND (non-VBUF address) error or any one of the CBUF related access errors (including any write access disabled during overflow error handling)." width 0x0B tree.end tree "OCMC_RAM2" base ad:0x4880A000 width 37. group.byte 0x0++0x3 line.long 0x0 "OCMC_ECC_PID,OCMC_ECC_PID" hexmask.long 0x0 0.--31. 1. " REVISION ,TI internal data" group.byte 0x4++0x3 line.long 0x0 "OCMC_SYSCONFIG_PM,OCMC_SYSCONFIG_PM" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "OCMC_SYSCONFIG_RST,OCMC_SYSCONFIG_RST" bitfld.long 0x0 0. " SW_RST ,Software reset of the OCM controller configuration and history logic (does not reset L4 interface)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "OCMC_MEM_SIZE_READ,This register provides the status of the OCM Controller configuration." bitfld.long 0x0 0.--4. " MEM_SIZE_128K_CNT ,This bit field indicates how many 128KiB memory blocks are present in the SRAM. Access beyond the memory size reported in the MEM_SIZE_128K_CNT bit field results in an address error interrupt. 0x1: One 128KiB memory block 0x2: Two 128KiB memory blocks ... 0x14: 20 memory blocks of 128KiB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " MEM_ECC_ENABLE ,Indicates whether ECC is supported or not." "0,1" bitfld.long 0x0 9. " MEM_CBUF_ENABLE ,Indicates whether CBUF is supported or not." "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12.--16. " VBUF_ADDR_MSB ,This bit field returns the MSB bit of the valid VBUF address range. The default value of 23 means that the valid VBUF address range is from 0x8000 0000 to 0x80FF FFFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "INTR0_STATUS_RAW_SET,This register contains the raw interrupt status. Read indicates RAW interrupt status (0=inactive, 1=active). Writing 1 will SET the corresponding raw status bit (soft interrupt set). Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "INTR0_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive, 1=active). Writing 1 will CLEAR the corresponding enabled status bit. Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "INTR0_ENABLE_SET,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will set the corresponding interrupt enable bit. Writing 0 has no effect. Interrupt_enable_set" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "INTR0_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will clear interrupt enabled. Writing 0 has no effect. Interrupt_enable_clear" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "OCMC_INTR0_EOI,This register contains the EOI vector." bitfld.long 0x0 0. " EOI_VECTOR ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "INTR1_STATUS_RAW_SET,This register contains the raw interrupt status. Read indicates RAW interrupt status (0=inactive, 1=active). Writing 1 will SET the corresponding raw status bit (soft interrupt set). Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "INTR1_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive, 1=active). Writing 1 will CLEAR the corresponding enabled status bit. Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "INTR1_ENABLE_SET,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will set the corresponding interrupt enable bit. Writing 0 has no effect. Interrupt_enable_set" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "INTR1_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will clear interrupt enabled. Writing 0 has no effect. Interrupt_enable_clear" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "OCMC_INTR1_EOI,This register contains the EOI vector." bitfld.long 0x0 0. " EOI_VECTOR ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "CFG_OCMC_ECC,CFG_OCMC_ECC" bitfld.long 0x0 0.--2. " CFG_OCMC_MODE ,OCM Controller memory access modes. 0x0: Non-ECC mode (data access) 0x1: Non-ECC mode (code access) 0x2: Full ECC enabled mode 0x3: Block ECC enabled mode 0x4-0x7: Reserved (internally defaults to 0x0 mode)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " CFG_ECC_SEC_AUTO_CORRECT ,SEC error auto correction mode. Enables the OCM Controller to automatically update the wrong data word with the corrected word. 0x0: Disable 0x1: Enable (If the OCM Controller is performing a read-modify operation for a sub-128b write to an ECC enabled memory, the error found during the read phase will be corrected always regardless of the value of this bit)" "0,1" textline " " bitfld.long 0x0 4. " CFG_ECC_ERR_SRESP_EN ,ECC non-correctable error SRESP enable. Enables ERR return on L3 OCP SRESP when a non-correctable data (DED) or address error is detected. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 5. " CFG_ECC_OPT_NON_ECC_READ ,Optimize read latency for non-ECC read. Returns the data one cycle faster if the read access is from a non-ECC enabled space. 0x0: Disable 0x1: Enable" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "CFG_OCMC_ECC_MEM_BLK,CFG_OCMC_ECC_MEM_BLK" hexmask.long.tbyte 0x0 0.--19. 1. " CFG_ECC_ENABLED_128K_BLK ,ECC memory block enable bits. The active level of each bit is 0x1. Bit [0] -> Address offset range 0x0 to 0x1FFFF Bit [1] -> Address offset range 0x20000 to 0x3FFFF ... Bit [19] -> Address offset range 0x260000 to 0x27FFFF" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CFG_OCMC_ECC_ERROR,CFG_OCMC_ECC_ERROR" hexmask.long.word 0x0 0.--15. 1. " CFG_SEC_CNT_MAX ,Number of SEC error to trigger an interrupt (The value configured must be > 0 to generate an interrupt)." bitfld.long 0x0 16.--19. " CFG_DED_CNT_MAX ,Number of DED errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " CFG_ADDR_ERR_CNT_MAX ,Number of ADDR errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " CFG_DISCARD_DUP_ADDR ,Do not save duplicate error address. This bit applies to the SEC, DED and ADDRERR FIFOs. 0x0: Save the duplicated addresses 0x1: Save only the unique addresses" "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "CFG_OCMC_ECC_CLEAR_HIST,CFG_OCMC_ECC_CLEAR_HIST" bitfld.long 0x0 0. " CLEAR_SEC_ERR_CNT ,Clear stored single error correction history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the" "0,1" bitfld.long 0x0 1. " CLEAR_DED_ERR_CNT ,Clear stored double error detection (DED) history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the" "0,1" textline " " bitfld.long 0x0 2. " CLEAR_ADDR_ERR_CNT ,Clear stored address error history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the" "0,1" bitfld.long 0x0 3. " CLEAR_SEC_BIT_DISTR ,Clear stored single error correction (SEC) bit distribution history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Cleares the following registers:" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "STATUS_ERROR_CNT,OCM Controller error status" hexmask.long.word 0x0 0.--15. 1. " SEC_ERROR_CNT ,Counter for the single errors occured. This bit field is reset when 0x1 is written to the" bitfld.long 0x0 16.--19. " DED_ERROR_CNT ,Counter for the double error detections. This bit field is reset when 0x1 is written to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ADDR_ERROR_CNT ,Counter for the address errors found. This bit field is reset when 0x1 is written to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "STATUS_SEC_ERROR_TRACE,SEC error 128-bit memory address" hexmask.long.tbyte 0x0 0.--17. 1. " ADDRESS_128BIT ,SEC error 128-bit memory address (Read from the SEC error address trace fifo)" bitfld.long 0x0 18. " VALID ,SEC FIFO valid addres indication." "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "STATUS_DED_ERROR_TRACE,DED error 128-bit memory address" hexmask.long.tbyte 0x0 0.--17. 1. " ADDRESS_128BIT ,DED error 128-bit memory address (Read from the DED error address trace fifo)" bitfld.long 0x0 18. " VALID ,DED FIFO valid addres indication. 0x0: The DED FIFO is empty 0x1: There is a valid address in the DED FIFO" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "STATUS_ADDR_TRANSLATION_ERROR_TRACE,ADDR error 128-bit memory address" hexmask.long.tbyte 0x0 0.--17. 1. " ADDRESS_128BIT ,ADDR error 128-bit memory address (Read from the ADDR error address trace fifo)" bitfld.long 0x0 18. " VALID ,ADDRERR FIFO valid addres indication. 0x0: The ADDRERR FIFO is empty 0x1: There is a valid address in the ADDRERR FIFO" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_0,SEC data error bit distribution status [31:0]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xA4++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_1,SEC data error bit distribution status [63:32]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xA8++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_2,SEC data error bit distribution status [95:64]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xAC++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_3,SEC data error bit distribution status [127:96]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xB0++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_4,SEC ecc code error bit distribution status [7:0]" hexmask.long.byte 0x0 0.--7. 1. " SEC_ECC_CODE_ERROR_FOUND ,ECC Code (excluding the parity bit) error distribution [7:0]. For each bit: 0x0: SEC error not found 0x1: SEC error found In the corresponding bit location" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x200++0x3 line.long 0x0 "CFG_OCMC_CBUF_EN,CBUF mode enable register" bitfld.long 0x0 0. " CBUF_MODE_EN ,CBUF Mode Enable. 0x0: Disable all CBUF address translation 0x1: Enable CBUF address translation" "0,1" bitfld.long 0x0 1. " CBUF_DEBUG_EN ,CBUF Debug Enable Mode. 0x0: Default Normal mode. All CBUF accesses with MReqDebug=1 are rejected. 0x1: Debug mode. MReqDebug Interconnect qualifier is ignored." "0,1" textline " " bitfld.long 0x0 2. " NEW_FRAME_SEL ,CBUF New Frame Event Definition Select. 0x0: New frame event flag is set when a VBUF access is made to the base address of the VBUF 0x1: New frame event flag is set when a VBUF access is made to the base CBUF slice address range of the VBUF" "0,1" hexmask.long.word 0x0 3.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " CBUF_EN_0 ,CBUF 0 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 17. " CBUF_EN_1 ,CBUF 1 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 18. " CBUF_EN_2 ,CBUF 2 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 19. " CBUF_EN_3 ,CBUF 3 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 20. " CBUF_EN_4 ,CBUF 4 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 21. " CBUF_EN_5 ,CBUF 5 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 22. " CBUF_EN_6 ,CBUF 6 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 23. " CBUF_EN_7 ,CBUF 7 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 24. " CBUF_EN_8 ,CBUF 8 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 25. " CBUF_EN_9 ,CBUF 9 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 26. " CBUF_EN_10 ,CBUF 10 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 27. " CBUF_EN_11 ,CBUF 11 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x204++0x3 line.long 0x0 "CFG_OCMC_CBUF_RESET,Writing 1 to bit n will set a reset bit to clear the corresponding CBUF_n address translation logic. Sliding CBUF frame tracking will be cleared so that the CBUF now points to the base of the virtual frame buffer. Normally, a reset is not required since the CBUF logic will clear itself when a VBUF access is to the base of the virtual frame." bitfld.long 0x0 0. " CBUF_RESET_0 ,cbuf_reset_0" "0,1" bitfld.long 0x0 1. " CBUF_RESET_1 ,cbuf_reset_1" "0,1" textline " " bitfld.long 0x0 2. " CBUF_RESET_2 ,cbuf_reset_2" "0,1" bitfld.long 0x0 3. " CBUF_RESET_3 ,cbuf_reset_3" "0,1" textline " " bitfld.long 0x0 4. " CBUF_RESET_4 ,cbuf_reset_4" "0,1" bitfld.long 0x0 5. " CBUF_RESET_5 ,cbuf_reset_5" "0,1" textline " " bitfld.long 0x0 6. " CBUF_RESET_6 ,cbuf_reset_6" "0,1" bitfld.long 0x0 7. " CBUF_RESET_7 ,cbuf_reset_7" "0,1" textline " " bitfld.long 0x0 8. " CBUF_RESET_8 ,cbuf_reset_8" "0,1" bitfld.long 0x0 9. " CBUF_RESET_9 ,cbuf_reset_9" "0,1" textline " " bitfld.long 0x0 10. " CBUF_RESET_10 ,cbuf_reset_10" "0,1" bitfld.long 0x0 11. " CBUF_RESET_11 ,cbuf_reset_11" "0,1" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "CFG_OCMC_CBUF_ERR_HANDLER,CFG_OCMC_CBUF_ERR_HANDLER" bitfld.long 0x0 0. " SHORT_FRAME_DETECT_CHECK_EN ,Short frame detection enable." "0,1" bitfld.long 0x0 1. " SHORT_FRAME_PREV_EOF_SEL ,0x0: previous frame EOF history is set if the last write address is equal to the VBUF frame end address 0x1: previous frame EOF history is set if the last write address is in the Last CBUF slice" "0,1" textline " " bitfld.long 0x0 2. " OVERFLOW_ERR_CHECK_EN ,Overflow chek enable." "0,1" bitfld.long 0x0 3. " UNDERFLOW_ERR_CHECK_EN ,Underflow chek enable." "0,1" textline " " bitfld.long 0x0 4.--5. " OVERFLOW_WRITE_HANDLER_SEL ,Overflow write handler selection. 0x0: Writes disabled only on CBUF_overflow_wrap cases until next write to virtual frame start address is detected 0x1: Writes disabled on all overflow cases until next write to virtual frame start address is detected 0x2: Writes serviced with CBUF pointer updated even on overflow condition 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 6.--7. " OVERFLOW_CHECK_REENABLE_SEL ,Overflow check re-enable selection. 0x0: Overflow check is disabled until next wtire to or read from virtual frame start address is detected 0x1: Overflow check is disabled until next write to virtual frame start address is detected 0x2: Overflow check is disabled until next read from virtual frame start address is detected 0x3: Overflow check is re-enabled immediately" "0,1,2,3" textline " " bitfld.long 0x0 8. " UNDERFLOW_LAST_CBUF_SLICE_DISABLE ,0x0: Check underflow even when read is from the last CBUF slice 0x1: Disable underflow check when read is from the last CBUF slice" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "STATUS_CBUF_WR_OUT_OF_RANGE_ERR,STATUS_CBUF_WR_OUT_OF_RANGE_ERR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,Indicates that the CBUF write address is out of the CBUF range. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "STATUS_CBUF_WR_VBUF_START_ERR,STATUS_CBUF_WR_VBUF_START_ERR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF write is not to the base address at vbuf access start. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "STATUS_CBUF_WR_ADDR_SEQ_ERROR,STATUS_CBUF_WR_ADDR_SEQ_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF address is not incrementing in raster scan order. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x218++0x3 line.long 0x0 "STATUS_CBUF_RD_OUT_OF_RANGE_ERROR,STATUS_CBUF_RD_OUT_OF_RANGE_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,Indicates that the CBUF read address is out of the CBUF range. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x21C++0x3 line.long 0x0 "STATUS_CBUF_VBUF_RD_START_ERROR,STATUS_CBUF_VBUF_RD_START_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF read is not from the base address at VBUF access start. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x220++0x3 line.long 0x0 "STATUS_CBUF_RD_ADDR_SEQ_ERROR,STATUS_CBUF_RD_ADDR_SEQ_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF read address is not incrementing in raster scan order. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "STATUS_CBUF_OVERFLOW_MID,STATUS_CBUF_OVERFLOW_MID" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF overflow condition detected in the middle of a frame. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x228++0x3 line.long 0x0 "STATUS_CBUF_OVERFLOW_WRAP,STATUS_CBUF_OVERFLOW_WRAP" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF overflow condition detected during buffer switching. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x22C++0x3 line.long 0x0 "STATUS_CBUF_UNDERFLOW,STATUS_CBUF_UNDERFLOW" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF underflow condition detected. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "STATUS_CBUF_SHORT_FRAME_DETECT,STATUS_CBUF_SHORT_FRAME_DETECT" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF short frame detected. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x240++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_0,CBUF_i_VBUF_START_ADDR_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x256++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_1,CBUF_i_VBUF_START_ADDR_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x26C++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_2,CBUF_i_VBUF_START_ADDR_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x282++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_3,CBUF_i_VBUF_START_ADDR_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x298++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_4,CBUF_i_VBUF_START_ADDR_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2AE++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_5,CBUF_i_VBUF_START_ADDR_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2C4++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_6,CBUF_i_VBUF_START_ADDR_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2DA++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_7,CBUF_i_VBUF_START_ADDR_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2F0++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_8,CBUF_i_VBUF_START_ADDR_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x306++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_9,CBUF_i_VBUF_START_ADDR_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x31C++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_10,CBUF_i_VBUF_START_ADDR_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x332++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_11,CBUF_i_VBUF_START_ADDR_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x244++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_0,CBUF_i_VBUF_END_ADDR_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x25A++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_1,CBUF_i_VBUF_END_ADDR_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x270++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_2,CBUF_i_VBUF_END_ADDR_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x286++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_3,CBUF_i_VBUF_END_ADDR_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x29C++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_4,CBUF_i_VBUF_END_ADDR_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2B2++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_5,CBUF_i_VBUF_END_ADDR_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2C8++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_6,CBUF_i_VBUF_END_ADDR_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2DE++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_7,CBUF_i_VBUF_END_ADDR_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2F4++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_8,CBUF_i_VBUF_END_ADDR_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x30A++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_9,CBUF_i_VBUF_END_ADDR_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x320++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_10,CBUF_i_VBUF_END_ADDR_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x336++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_11,CBUF_i_VBUF_END_ADDR_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x248++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_0,CBUF_i_OCMC_START_ADDR_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x25E++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_1,CBUF_i_OCMC_START_ADDR_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x274++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_2,CBUF_i_OCMC_START_ADDR_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x28A++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_3,CBUF_i_OCMC_START_ADDR_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2A0++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_4,CBUF_i_OCMC_START_ADDR_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2B6++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_5,CBUF_i_OCMC_START_ADDR_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2CC++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_6,CBUF_i_OCMC_START_ADDR_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2E2++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_7,CBUF_i_OCMC_START_ADDR_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2F8++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_8,CBUF_i_OCMC_START_ADDR_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x30E++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_9,CBUF_i_OCMC_START_ADDR_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x324++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_10,CBUF_i_OCMC_START_ADDR_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x33A++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_11,CBUF_i_OCMC_START_ADDR_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x24C++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_0,CBUF_i_OCMC_BUF_SIZE_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x262++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_1,CBUF_i_OCMC_BUF_SIZE_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x278++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_2,CBUF_i_OCMC_BUF_SIZE_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x28E++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_3,CBUF_i_OCMC_BUF_SIZE_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2A4++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_4,CBUF_i_OCMC_BUF_SIZE_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2BA++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_5,CBUF_i_OCMC_BUF_SIZE_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2D0++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_6,CBUF_i_OCMC_BUF_SIZE_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2E6++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_7,CBUF_i_OCMC_BUF_SIZE_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2FC++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_8,CBUF_i_OCMC_BUF_SIZE_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x312++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_9,CBUF_i_OCMC_BUF_SIZE_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x328++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_10,CBUF_i_OCMC_BUF_SIZE_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x33E++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_11,CBUF_i_OCMC_BUF_SIZE_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x300++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_0,CBUF_k_LAST_WR_ADDR_0" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x308++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_1,CBUF_k_LAST_WR_ADDR_1" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x310++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_2,CBUF_k_LAST_WR_ADDR_2" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x318++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_3,CBUF_k_LAST_WR_ADDR_3" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x320++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_4,CBUF_k_LAST_WR_ADDR_4" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x328++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_5,CBUF_k_LAST_WR_ADDR_5" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x330++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_6,CBUF_k_LAST_WR_ADDR_6" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x338++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_7,CBUF_k_LAST_WR_ADDR_7" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x340++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_8,CBUF_k_LAST_WR_ADDR_8" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x348++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_9,CBUF_k_LAST_WR_ADDR_9" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x350++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_10,CBUF_k_LAST_WR_ADDR_10" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x358++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_11,CBUF_k_LAST_WR_ADDR_11" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x304++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_0,CBUF_k_LAST_RD_ADDR_0" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x30C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_1,CBUF_k_LAST_RD_ADDR_1" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x314++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_2,CBUF_k_LAST_RD_ADDR_2" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x31C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_3,CBUF_k_LAST_RD_ADDR_3" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x324++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_4,CBUF_k_LAST_RD_ADDR_4" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x32C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_5,CBUF_k_LAST_RD_ADDR_5" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x334++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_6,CBUF_k_LAST_RD_ADDR_6" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x33C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_7,CBUF_k_LAST_RD_ADDR_7" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x344++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_8,CBUF_k_LAST_RD_ADDR_8" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x34C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_9,CBUF_k_LAST_RD_ADDR_9" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x354++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_10,CBUF_k_LAST_RD_ADDR_10" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x35C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_11,CBUF_k_LAST_RD_ADDR_11" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x360++0x3 line.long 0x0 "LAST_ILLEGAL_OCMC_ADDR,LAST_ILLEGAL_OCMC_ADDR" hexmask.long 0x0 0.--31. 1. " ADDR ,Last Illegal OCMC Address. This register returns the OCMC L3_MAIN address of the last access that was invalidated due to an OUT_OF_RANGE_ERR_FOUND (non-VBUF address) error or any one of the CBUF related access errors (including any write access disabled during overflow error handling)." width 0x0B tree.end tree "OCMC_RAM3" base ad:0x48810000 width 37. group.byte 0x0++0x3 line.long 0x0 "OCMC_ECC_PID,OCMC_ECC_PID" hexmask.long 0x0 0.--31. 1. " REVISION ,TI internal data" group.byte 0x4++0x3 line.long 0x0 "OCMC_SYSCONFIG_PM,OCMC_SYSCONFIG_PM" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "OCMC_SYSCONFIG_RST,OCMC_SYSCONFIG_RST" bitfld.long 0x0 0. " SW_RST ,Software reset of the OCM controller configuration and history logic (does not reset L4 interface)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "OCMC_MEM_SIZE_READ,This register provides the status of the OCM Controller configuration." bitfld.long 0x0 0.--4. " MEM_SIZE_128K_CNT ,This bit field indicates how many 128KiB memory blocks are present in the SRAM. Access beyond the memory size reported in the MEM_SIZE_128K_CNT bit field results in an address error interrupt. 0x1: One 128KiB memory block 0x2: Two 128KiB memory blocks ... 0x14: 20 memory blocks of 128KiB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " MEM_ECC_ENABLE ,Indicates whether ECC is supported or not." "0,1" bitfld.long 0x0 9. " MEM_CBUF_ENABLE ,Indicates whether CBUF is supported or not." "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12.--16. " VBUF_ADDR_MSB ,This bit field returns the MSB bit of the valid VBUF address range. The default value of 23 means that the valid VBUF address range is from 0x8000 0000 to 0x80FF FFFF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "INTR0_STATUS_RAW_SET,This register contains the raw interrupt status. Read indicates RAW interrupt status (0=inactive, 1=active). Writing 1 will SET the corresponding raw status bit (soft interrupt set). Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "INTR0_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive, 1=active). Writing 1 will CLEAR the corresponding enabled status bit. Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "INTR0_ENABLE_SET,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will set the corresponding interrupt enable bit. Writing 0 has no effect. Interrupt_enable_set" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "INTR0_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will clear interrupt enabled. Writing 0 has no effect. Interrupt_enable_clear" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "OCMC_INTR0_EOI,This register contains the EOI vector." bitfld.long 0x0 0. " EOI_VECTOR ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "INTR1_STATUS_RAW_SET,This register contains the raw interrupt status. Read indicates RAW interrupt status (0=inactive, 1=active). Writing 1 will SET the corresponding raw status bit (soft interrupt set). Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "INTR1_STATUS_ENABLED_CLEAR,Read indicates ENABLED interrupt status (0=inactive, 1=active). Writing 1 will CLEAR the corresponding enabled status bit. Writing 0 has no effect." bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "INTR1_ENABLE_SET,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will set the corresponding interrupt enable bit. Writing 0 has no effect. Interrupt_enable_set" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "INTR1_ENABLE_CLEAR,Read indicates interrupt enable (0=disabled, 1=enabled) Writing 1 will clear interrupt enabled. Writing 0 has no effect. Interrupt_enable_clear" bitfld.long 0x0 0. " SEC_ERR_FOUND ," "0,1" bitfld.long 0x0 1. " DED_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 2. " ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 3. " OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 4. " CBUF_VIRTUAL_ADDR_ERR_FOUND ," "0,1" bitfld.long 0x0 5. " CBUF_WR_OUT_OF_RANGE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 6. " CBUF_VBUF_WRITE_START_ERR_FOUND ," "0,1" bitfld.long 0x0 7. " CBUF_WRITE_SEQUENCE_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 8. " CBUF_READ_OUT_OF_RANGE_ERR_FOUND ," "0,1" bitfld.long 0x0 9. " CBUF_VBUF_READ_START_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 10. " CBUF_READ_SEQUENCE_ERR_FOUND ," "0,1" bitfld.long 0x0 11. " CBUF_OVERFLOW_MID_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 12. " CBUF_OVERFLOW_WRAP_ERR_FOUND ," "0,1" bitfld.long 0x0 13. " CBUF_UNDERFLOW_ERR_FOUND ," "0,1" textline " " bitfld.long 0x0 14. " CBUF_SHORT_FRAME_DETECT_FOUND ,CBUF detected short frame" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "OCMC_INTR1_EOI,This register contains the EOI vector." bitfld.long 0x0 0. " EOI_VECTOR ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "CFG_OCMC_ECC,CFG_OCMC_ECC" bitfld.long 0x0 0.--2. " CFG_OCMC_MODE ,OCM Controller memory access modes. 0x0: Non-ECC mode (data access) 0x1: Non-ECC mode (code access) 0x2: Full ECC enabled mode 0x3: Block ECC enabled mode 0x4-0x7: Reserved (internally defaults to 0x0 mode)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " CFG_ECC_SEC_AUTO_CORRECT ,SEC error auto correction mode. Enables the OCM Controller to automatically update the wrong data word with the corrected word. 0x0: Disable 0x1: Enable (If the OCM Controller is performing a read-modify operation for a sub-128b write to an ECC enabled memory, the error found during the read phase will be corrected always regardless of the value of this bit)" "0,1" textline " " bitfld.long 0x0 4. " CFG_ECC_ERR_SRESP_EN ,ECC non-correctable error SRESP enable. Enables ERR return on L3 OCP SRESP when a non-correctable data (DED) or address error is detected. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 5. " CFG_ECC_OPT_NON_ECC_READ ,Optimize read latency for non-ECC read. Returns the data one cycle faster if the read access is from a non-ECC enabled space. 0x0: Disable 0x1: Enable" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "CFG_OCMC_ECC_MEM_BLK,CFG_OCMC_ECC_MEM_BLK" hexmask.long.tbyte 0x0 0.--19. 1. " CFG_ECC_ENABLED_128K_BLK ,ECC memory block enable bits. The active level of each bit is 0x1. Bit [0] -> Address offset range 0x0 to 0x1FFFF Bit [1] -> Address offset range 0x20000 to 0x3FFFF ... Bit [19] -> Address offset range 0x260000 to 0x27FFFF" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CFG_OCMC_ECC_ERROR,CFG_OCMC_ECC_ERROR" hexmask.long.word 0x0 0.--15. 1. " CFG_SEC_CNT_MAX ,Number of SEC error to trigger an interrupt (The value configured must be > 0 to generate an interrupt)." bitfld.long 0x0 16.--19. " CFG_DED_CNT_MAX ,Number of DED errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " CFG_ADDR_ERR_CNT_MAX ,Number of ADDR errors to trigger an interrupt (The value configured must be > 0 to generate an interrupt)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " CFG_DISCARD_DUP_ADDR ,Do not save duplicate error address. This bit applies to the SEC, DED and ADDRERR FIFOs. 0x0: Save the duplicated addresses 0x1: Save only the unique addresses" "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "CFG_OCMC_ECC_CLEAR_HIST,CFG_OCMC_ECC_CLEAR_HIST" bitfld.long 0x0 0. " CLEAR_SEC_ERR_CNT ,Clear stored single error correction history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the" "0,1" bitfld.long 0x0 1. " CLEAR_DED_ERR_CNT ,Clear stored double error detection (DED) history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the" "0,1" textline " " bitfld.long 0x0 2. " CLEAR_ADDR_ERR_CNT ,Clear stored address error history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Clears the" "0,1" bitfld.long 0x0 3. " CLEAR_SEC_BIT_DISTR ,Clear stored single error correction (SEC) bit distribution history. Returns 0 on read. 0x0: Reserved (not used) 0x1: Cleares the following registers:" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "STATUS_ERROR_CNT,OCM Controller error status" hexmask.long.word 0x0 0.--15. 1. " SEC_ERROR_CNT ,Counter for the single errors occured. This bit field is reset when 0x1 is written to the" bitfld.long 0x0 16.--19. " DED_ERROR_CNT ,Counter for the double error detections. This bit field is reset when 0x1 is written to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " ADDR_ERROR_CNT ,Counter for the address errors found. This bit field is reset when 0x1 is written to the" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "STATUS_SEC_ERROR_TRACE,SEC error 128-bit memory address" hexmask.long.tbyte 0x0 0.--17. 1. " ADDRESS_128BIT ,SEC error 128-bit memory address (Read from the SEC error address trace fifo)" bitfld.long 0x0 18. " VALID ,SEC FIFO valid addres indication." "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "STATUS_DED_ERROR_TRACE,DED error 128-bit memory address" hexmask.long.tbyte 0x0 0.--17. 1. " ADDRESS_128BIT ,DED error 128-bit memory address (Read from the DED error address trace fifo)" bitfld.long 0x0 18. " VALID ,DED FIFO valid addres indication. 0x0: The DED FIFO is empty 0x1: There is a valid address in the DED FIFO" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "STATUS_ADDR_TRANSLATION_ERROR_TRACE,ADDR error 128-bit memory address" hexmask.long.tbyte 0x0 0.--17. 1. " ADDRESS_128BIT ,ADDR error 128-bit memory address (Read from the ADDR error address trace fifo)" bitfld.long 0x0 18. " VALID ,ADDRERR FIFO valid addres indication. 0x0: The ADDRERR FIFO is empty 0x1: There is a valid address in the ADDRERR FIFO" "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_0,SEC data error bit distribution status [31:0]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xA4++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_1,SEC data error bit distribution status [63:32]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xA8++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_2,SEC data error bit distribution status [95:64]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xAC++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_3,SEC data error bit distribution status [127:96]" hexmask.long 0x0 0.--31. 1. " SEC_BIT_ERROR_FOUND ,1 in a bit position means that an SEC error was found at that bit position and corrected" group.byte 0xB0++0x3 line.long 0x0 "STATUS_SEC_ERROR_DISTR_4,SEC ecc code error bit distribution status [7:0]" hexmask.long.byte 0x0 0.--7. 1. " SEC_ECC_CODE_ERROR_FOUND ,ECC Code (excluding the parity bit) error distribution [7:0]. For each bit: 0x0: SEC error not found 0x1: SEC error found In the corresponding bit location" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x200++0x3 line.long 0x0 "CFG_OCMC_CBUF_EN,CBUF mode enable register" bitfld.long 0x0 0. " CBUF_MODE_EN ,CBUF Mode Enable. 0x0: Disable all CBUF address translation 0x1: Enable CBUF address translation" "0,1" bitfld.long 0x0 1. " CBUF_DEBUG_EN ,CBUF Debug Enable Mode. 0x0: Default Normal mode. All CBUF accesses with MReqDebug=1 are rejected. 0x1: Debug mode. MReqDebug Interconnect qualifier is ignored." "0,1" textline " " bitfld.long 0x0 2. " NEW_FRAME_SEL ,CBUF New Frame Event Definition Select. 0x0: New frame event flag is set when a VBUF access is made to the base address of the VBUF 0x1: New frame event flag is set when a VBUF access is made to the base CBUF slice address range of the VBUF" "0,1" hexmask.long.word 0x0 3.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " CBUF_EN_0 ,CBUF 0 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 17. " CBUF_EN_1 ,CBUF 1 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 18. " CBUF_EN_2 ,CBUF 2 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 19. " CBUF_EN_3 ,CBUF 3 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 20. " CBUF_EN_4 ,CBUF 4 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 21. " CBUF_EN_5 ,CBUF 5 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 22. " CBUF_EN_6 ,CBUF 6 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 23. " CBUF_EN_7 ,CBUF 7 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 24. " CBUF_EN_8 ,CBUF 8 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 25. " CBUF_EN_9 ,CBUF 9 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 26. " CBUF_EN_10 ,CBUF 10 enable. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 27. " CBUF_EN_11 ,CBUF 11 enable. 0x0: Disable 0x1: Enable" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x204++0x3 line.long 0x0 "CFG_OCMC_CBUF_RESET,Writing 1 to bit n will set a reset bit to clear the corresponding CBUF_n address translation logic. Sliding CBUF frame tracking will be cleared so that the CBUF now points to the base of the virtual frame buffer. Normally, a reset is not required since the CBUF logic will clear itself when a VBUF access is to the base of the virtual frame." bitfld.long 0x0 0. " CBUF_RESET_0 ,cbuf_reset_0" "0,1" bitfld.long 0x0 1. " CBUF_RESET_1 ,cbuf_reset_1" "0,1" textline " " bitfld.long 0x0 2. " CBUF_RESET_2 ,cbuf_reset_2" "0,1" bitfld.long 0x0 3. " CBUF_RESET_3 ,cbuf_reset_3" "0,1" textline " " bitfld.long 0x0 4. " CBUF_RESET_4 ,cbuf_reset_4" "0,1" bitfld.long 0x0 5. " CBUF_RESET_5 ,cbuf_reset_5" "0,1" textline " " bitfld.long 0x0 6. " CBUF_RESET_6 ,cbuf_reset_6" "0,1" bitfld.long 0x0 7. " CBUF_RESET_7 ,cbuf_reset_7" "0,1" textline " " bitfld.long 0x0 8. " CBUF_RESET_8 ,cbuf_reset_8" "0,1" bitfld.long 0x0 9. " CBUF_RESET_9 ,cbuf_reset_9" "0,1" textline " " bitfld.long 0x0 10. " CBUF_RESET_10 ,cbuf_reset_10" "0,1" bitfld.long 0x0 11. " CBUF_RESET_11 ,cbuf_reset_11" "0,1" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "CFG_OCMC_CBUF_ERR_HANDLER,CFG_OCMC_CBUF_ERR_HANDLER" bitfld.long 0x0 0. " SHORT_FRAME_DETECT_CHECK_EN ,Short frame detection enable." "0,1" bitfld.long 0x0 1. " SHORT_FRAME_PREV_EOF_SEL ,0x0: previous frame EOF history is set if the last write address is equal to the VBUF frame end address 0x1: previous frame EOF history is set if the last write address is in the Last CBUF slice" "0,1" textline " " bitfld.long 0x0 2. " OVERFLOW_ERR_CHECK_EN ,Overflow chek enable." "0,1" bitfld.long 0x0 3. " UNDERFLOW_ERR_CHECK_EN ,Underflow chek enable." "0,1" textline " " bitfld.long 0x0 4.--5. " OVERFLOW_WRITE_HANDLER_SEL ,Overflow write handler selection. 0x0: Writes disabled only on CBUF_overflow_wrap cases until next write to virtual frame start address is detected 0x1: Writes disabled on all overflow cases until next write to virtual frame start address is detected 0x2: Writes serviced with CBUF pointer updated even on overflow condition 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 6.--7. " OVERFLOW_CHECK_REENABLE_SEL ,Overflow check re-enable selection. 0x0: Overflow check is disabled until next wtire to or read from virtual frame start address is detected 0x1: Overflow check is disabled until next write to virtual frame start address is detected 0x2: Overflow check is disabled until next read from virtual frame start address is detected 0x3: Overflow check is re-enabled immediately" "0,1,2,3" textline " " bitfld.long 0x0 8. " UNDERFLOW_LAST_CBUF_SLICE_DISABLE ,0x0: Check underflow even when read is from the last CBUF slice 0x1: Disable underflow check when read is from the last CBUF slice" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "STATUS_CBUF_WR_OUT_OF_RANGE_ERR,STATUS_CBUF_WR_OUT_OF_RANGE_ERR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,Indicates that the CBUF write address is out of the CBUF range. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "STATUS_CBUF_WR_VBUF_START_ERR,STATUS_CBUF_WR_VBUF_START_ERR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF write is not to the base address at vbuf access start. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "STATUS_CBUF_WR_ADDR_SEQ_ERROR,STATUS_CBUF_WR_ADDR_SEQ_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF address is not incrementing in raster scan order. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x218++0x3 line.long 0x0 "STATUS_CBUF_RD_OUT_OF_RANGE_ERROR,STATUS_CBUF_RD_OUT_OF_RANGE_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,Indicates that the CBUF read address is out of the CBUF range. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x21C++0x3 line.long 0x0 "STATUS_CBUF_VBUF_RD_START_ERROR,STATUS_CBUF_VBUF_RD_START_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF read is not from the base address at VBUF access start. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x220++0x3 line.long 0x0 "STATUS_CBUF_RD_ADDR_SEQ_ERROR,STATUS_CBUF_RD_ADDR_SEQ_ERROR" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF read address is not incrementing in raster scan order. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "STATUS_CBUF_OVERFLOW_MID,STATUS_CBUF_OVERFLOW_MID" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF overflow condition detected in the middle of a frame. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x228++0x3 line.long 0x0 "STATUS_CBUF_OVERFLOW_WRAP,STATUS_CBUF_OVERFLOW_WRAP" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF overflow condition detected during buffer switching. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x22C++0x3 line.long 0x0 "STATUS_CBUF_UNDERFLOW,STATUS_CBUF_UNDERFLOW" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF underflow condition detected. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "STATUS_CBUF_SHORT_FRAME_DETECT,STATUS_CBUF_SHORT_FRAME_DETECT" hexmask.long.word 0x0 0.--11. 1. " CBUF_ERR ,CBUF short frame detected. Each bit indicates the error of this type for CBUF[n], where n = 0 to 11. Writing 0x1 to bit [n] clears the status of CBUF[n]. Reading 0x1 from bit [n] means that the status is set." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x240++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_0,CBUF_i_VBUF_START_ADDR_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x256++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_1,CBUF_i_VBUF_START_ADDR_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x26C++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_2,CBUF_i_VBUF_START_ADDR_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x282++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_3,CBUF_i_VBUF_START_ADDR_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x298++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_4,CBUF_i_VBUF_START_ADDR_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2AE++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_5,CBUF_i_VBUF_START_ADDR_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2C4++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_6,CBUF_i_VBUF_START_ADDR_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2DA++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_7,CBUF_i_VBUF_START_ADDR_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2F0++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_8,CBUF_i_VBUF_START_ADDR_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x306++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_9,CBUF_i_VBUF_START_ADDR_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x31C++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_10,CBUF_i_VBUF_START_ADDR_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x332++0x3 line.long 0x0 "CBUF_i_VBUF_START_ADDR_11,CBUF_i_VBUF_START_ADDR_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame start address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x244++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_0,CBUF_i_VBUF_END_ADDR_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x25A++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_1,CBUF_i_VBUF_END_ADDR_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x270++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_2,CBUF_i_VBUF_END_ADDR_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x286++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_3,CBUF_i_VBUF_END_ADDR_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x29C++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_4,CBUF_i_VBUF_END_ADDR_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2B2++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_5,CBUF_i_VBUF_END_ADDR_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2C8++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_6,CBUF_i_VBUF_END_ADDR_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2DE++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_7,CBUF_i_VBUF_END_ADDR_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x2F4++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_8,CBUF_i_VBUF_END_ADDR_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x30A++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_9,CBUF_i_VBUF_END_ADDR_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x320++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_10,CBUF_i_VBUF_END_ADDR_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x336++0x3 line.long 0x0 "CBUF_i_VBUF_END_ADDR_11,CBUF_i_VBUF_END_ADDR_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--23. 1. " ADDR ,Virtual frame end address for this CBUF - bits [23:4]" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,The virtual address range is determined by theOCMC_MEM_SIZE_READ[16:12] VBUF_ADDR_MSB bit field. For default value of 23, the valid VBUF address is 0x80xx_xxxx. Writing to this field above the MSB bit returned by VBUF_ADDR_MSB will be ignored and reading will return all zeroes except for bit[31] = 1." group.byte 0x248++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_0,CBUF_i_OCMC_START_ADDR_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x25E++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_1,CBUF_i_OCMC_START_ADDR_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x274++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_2,CBUF_i_OCMC_START_ADDR_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x28A++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_3,CBUF_i_OCMC_START_ADDR_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2A0++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_4,CBUF_i_OCMC_START_ADDR_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2B6++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_5,CBUF_i_OCMC_START_ADDR_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2CC++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_6,CBUF_i_OCMC_START_ADDR_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2E2++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_7,CBUF_i_OCMC_START_ADDR_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x2F8++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_8,CBUF_i_OCMC_START_ADDR_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x30E++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_9,CBUF_i_OCMC_START_ADDR_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x324++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_10,CBUF_i_OCMC_START_ADDR_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x33A++0x3 line.long 0x0 "CBUF_i_OCMC_START_ADDR_11,CBUF_i_OCMC_START_ADDR_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 4.--21. 1. " ADDR ,SRAM start address for this CBUF - bits [21:4]" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x24C++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_0,CBUF_i_OCMC_BUF_SIZE_0" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x262++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_1,CBUF_i_OCMC_BUF_SIZE_1" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x278++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_2,CBUF_i_OCMC_BUF_SIZE_2" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x28E++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_3,CBUF_i_OCMC_BUF_SIZE_3" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2A4++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_4,CBUF_i_OCMC_BUF_SIZE_4" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2BA++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_5,CBUF_i_OCMC_BUF_SIZE_5" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2D0++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_6,CBUF_i_OCMC_BUF_SIZE_6" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2E6++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_7,CBUF_i_OCMC_BUF_SIZE_7" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x2FC++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_8,CBUF_i_OCMC_BUF_SIZE_8" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x312++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_9,CBUF_i_OCMC_BUF_SIZE_9" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x328++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_10,CBUF_i_OCMC_BUF_SIZE_10" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x33E++0x3 line.long 0x0 "CBUF_i_OCMC_BUF_SIZE_11,CBUF_i_OCMC_BUF_SIZE_11" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--19. 1. " BUF_SIZE ,SRAM size allocated for this CBUF - bits [19:4]" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x300++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_0,CBUF_k_LAST_WR_ADDR_0" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x308++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_1,CBUF_k_LAST_WR_ADDR_1" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x310++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_2,CBUF_k_LAST_WR_ADDR_2" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x318++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_3,CBUF_k_LAST_WR_ADDR_3" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x320++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_4,CBUF_k_LAST_WR_ADDR_4" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x328++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_5,CBUF_k_LAST_WR_ADDR_5" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x330++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_6,CBUF_k_LAST_WR_ADDR_6" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x338++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_7,CBUF_k_LAST_WR_ADDR_7" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x340++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_8,CBUF_k_LAST_WR_ADDR_8" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x348++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_9,CBUF_k_LAST_WR_ADDR_9" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x350++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_10,CBUF_k_LAST_WR_ADDR_10" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x358++0x3 line.long 0x0 "CBUF_k_LAST_WR_ADDR_11,CBUF_k_LAST_WR_ADDR_11" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual write address accessing CBUF" group.byte 0x304++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_0,CBUF_k_LAST_RD_ADDR_0" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x30C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_1,CBUF_k_LAST_RD_ADDR_1" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x314++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_2,CBUF_k_LAST_RD_ADDR_2" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x31C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_3,CBUF_k_LAST_RD_ADDR_3" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x324++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_4,CBUF_k_LAST_RD_ADDR_4" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x32C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_5,CBUF_k_LAST_RD_ADDR_5" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x334++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_6,CBUF_k_LAST_RD_ADDR_6" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x33C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_7,CBUF_k_LAST_RD_ADDR_7" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x344++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_8,CBUF_k_LAST_RD_ADDR_8" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x34C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_9,CBUF_k_LAST_RD_ADDR_9" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x354++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_10,CBUF_k_LAST_RD_ADDR_10" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x35C++0x3 line.long 0x0 "CBUF_k_LAST_RD_ADDR_11,CBUF_k_LAST_RD_ADDR_11" hexmask.long 0x0 0.--31. 1. " ADDR ,Last virtual read address accessing CBUF" group.byte 0x360++0x3 line.long 0x0 "LAST_ILLEGAL_OCMC_ADDR,LAST_ILLEGAL_OCMC_ADDR" hexmask.long 0x0 0.--31. 1. " ADDR ,Last Illegal OCMC Address. This register returns the OCMC L3_MAIN address of the last access that was invalidated due to an OUT_OF_RANGE_ERR_FOUND (non-VBUF address) error or any one of the CBUF related access errors (including any write access disabled during overflow error handling)." width 0x0B tree.end tree "DMA_SYSTEM" base ad:0x4A056000 width 21. group.byte 0x0++0x3 line.long 0x0 "DMA4_REVISION,This register contains the DMA revision code" hexmask.long 0x0 0.--31. 1. " REVISION,Reserved ,Reserved, Write 0's for future compatibility. Read returns 0" group.byte 0x8++0x3 line.long 0x0 "DMA4_IRQSTATUS_Lj_0,The interrupt status register regroups all the status of the DMA_SYSTEM channels that can generate an interrupt over line Lj." hexmask.long 0x0 0.--31. 1. " CH_31_0_Lj ,Channel 31 Interrupt on Lj: When an interrupt is seen on the line Lj the status of a interrupting channel i is read in the bit field i." group.byte 0xC++0x3 line.long 0x0 "DMA4_IRQSTATUS_Lj_1,The interrupt status register regroups all the status of the DMA_SYSTEM channels that can generate an interrupt over line Lj." hexmask.long 0x0 0.--31. 1. " CH_31_0_Lj ,Channel 31 Interrupt on Lj: When an interrupt is seen on the line Lj the status of a interrupting channel i is read in the bit field i." group.byte 0x10++0x3 line.long 0x0 "DMA4_IRQSTATUS_Lj_2,The interrupt status register regroups all the status of the DMA_SYSTEM channels that can generate an interrupt over line Lj." hexmask.long 0x0 0.--31. 1. " CH_31_0_Lj ,Channel 31 Interrupt on Lj: When an interrupt is seen on the line Lj the status of a interrupting channel i is read in the bit field i." group.byte 0x14++0x3 line.long 0x0 "DMA4_IRQSTATUS_Lj_3,The interrupt status register regroups all the status of the DMA_SYSTEM channels that can generate an interrupt over line Lj." hexmask.long 0x0 0.--31. 1. " CH_31_0_Lj ,Channel 31 Interrupt on Lj: When an interrupt is seen on the line Lj the status of a interrupting channel i is read in the bit field i." group.byte 0x18++0x3 line.long 0x0 "DMA4_IRQENABLE_Lj_0,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line Lj" hexmask.long 0x0 0.--31. 1. " CH_31_0_Lj_EN ,Channel Interrupt on Lj mask/unmask : to Mask/Unmask a channel i interrupt on Lj the user writes 0/1 on the bit field i." group.byte 0x1C++0x3 line.long 0x0 "DMA4_IRQENABLE_Lj_1,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line Lj" hexmask.long 0x0 0.--31. 1. " CH_31_0_Lj_EN ,Channel Interrupt on Lj mask/unmask : to Mask/Unmask a channel i interrupt on Lj the user writes 0/1 on the bit field i." group.byte 0x20++0x3 line.long 0x0 "DMA4_IRQENABLE_Lj_2,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line Lj" hexmask.long 0x0 0.--31. 1. " CH_31_0_Lj_EN ,Channel Interrupt on Lj mask/unmask : to Mask/Unmask a channel i interrupt on Lj the user writes 0/1 on the bit field i." group.byte 0x24++0x3 line.long 0x0 "DMA4_IRQENABLE_Lj_3,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on line Lj" hexmask.long 0x0 0.--31. 1. " CH_31_0_Lj_EN ,Channel Interrupt on Lj mask/unmask : to Mask/Unmask a channel i interrupt on Lj the user writes 0/1 on the bit field i." group.byte 0x28++0x3 line.long 0x0 "DMA4_SYSSTATUS,The register provides status information about the module excluding the interrupt status information (see interrupt status register)" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved for module-specific status information" group.byte 0x2C++0x3 line.long 0x0 "DMA4_OCP_SYSCONFIG,DMA system configuration register" bitfld.long 0x0 0. " AUTOIDLE ,Internal interface clock gating strategy" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved for non-GP devices . ." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Configuration port power management, Idle req/ack control" "0,1,2,3" textline " " bitfld.long 0x0 5. " EMUFREE ,Enable sensitivity to MSuspend" "0,1" bitfld.long 0x0 6.--7. " RESERVED ,Write 0's for future compatibility. Read returns 0" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clocks activities during wake-up Bit 8: Interface clock 0x0: Interface clock can be switched-off Bit 9: Functional clock 0x0: Functional clock can be switched-off" "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ,Reserved for clocks activities extension" "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " MIDLEMODE ,Read write power management, standby/wait control" "0,1,2,3" hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x64++0x3 line.long 0x0 "DMA4_CAPS_0,DMA Capabilities Register 0 LSW" hexmask.long.tbyte 0x0 0.--17. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" bitfld.long 0x0 18. " TRANSPARENT_BLT_CPBLTY ,Transparent_BLT_Capability" "0,1" textline " " bitfld.long 0x0 19. " CONST_FILL_CPBLTY ,Constant_Fill_Capability" "0,1" bitfld.long 0x0 20. " LINK_LIST_CPBLTY_TYPE123 ,Link List capability for type123 descriptor capability" "0,1" textline " " bitfld.long 0x0 21. " LINK_LIST_CPBLTY_TYPE4 ,Link List capability for type4 descriptor capability" "0,1" hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x6C++0x3 line.long 0x0 "DMA4_CAPS_2,DMA Capabilities Register 2" bitfld.long 0x0 0. " SRC_CONST_ADRS_CPBLTY ,Source_constant_address_capability" "0,1" bitfld.long 0x0 1. " SRC_POST_INCREMENT_ADRS_CPBLTY ,Source_post_increment_address_capability" "0,1" textline " " bitfld.long 0x0 2. " SRC_SINGLE_INDEX_ADRS_CPBLTY ,Source_single_index_address_capability" "0,1" bitfld.long 0x0 3. " SRC_DOUBLE_INDEX_ADRS_CPBLTY ,Source_double_index_address_capability" "0,1" textline " " bitfld.long 0x0 4. " DST_CONST_ADRS_CPBLTY ,Destination_constant_address_capability" "0,1" bitfld.long 0x0 5. " DST_POST_INCRMNT_ADRS_CPBLTY ,Destination_post_increment_address_capability" "0,1" textline " " bitfld.long 0x0 6. " DST_SINGLE_INDEX_ADRS_CPBLTY ,Destination_single_index_address_capability" "0,1" bitfld.long 0x0 7. " DST_DOUBLE_INDEX_ADRS_CPBLTY ,Destination_double_index_address_capability" "0,1" textline " " bitfld.long 0x0 8. " SEPARATE_SRC_AND_DST_INDEX_CPBLTY ,Separate_source/destination_index_capability" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x70++0x3 line.long 0x0 "DMA4_CAPS_3,DMA Capabilities Register 3" bitfld.long 0x0 0. " ELMNT_SYNCHR_CPBLTY ,Element_synchronization_capability" "0,1" bitfld.long 0x0 1. " FRAME_SYNCHR_CPBLTY ,Frame_synchronization_capability" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " CHANNEL_INTERLEAVE_CPBLTY ,Channel_interleave_capability" "0,1" textline " " bitfld.long 0x0 5. " CHANNEL_CHANINIG_CPBLTY ,Channel_Chaninig_capability" "0,1" bitfld.long 0x0 6. " PKT_SYNCHR_CPBLTY ,Packet_synchronization_capability" "0,1" textline " " bitfld.long 0x0 7. " BLOCK_SYNCHR_CPBLTY ,Block_synchronization_capability" "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x74++0x3 line.long 0x0 "DMA4_CAPS_4,DMA Capabilities Register 4" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " EVENT_DROP_INTERRUPT_CPBLTY ,Request collision detection capability." "0,1" textline " " bitfld.long 0x0 2. " HALF_FRAME_INTERRUPT_CPBLTY ,Detection capability of the half of frame end." "0,1" bitfld.long 0x0 3. " FRAME_INTERRUPT_CPBLTY ,End of frame detection capability." "0,1" textline " " bitfld.long 0x0 4. " LAST_FRAME_INTERRUPT_CPBLTY ,Start of last frame detection capability." "0,1" bitfld.long 0x0 5. " BLOCK_INTERRUPT_CPBLTY ,End of block detection capability." "0,1" textline " " bitfld.long 0x0 6. " SYNC_STATUS_CPBLTY ,Sync_status_capability" "0,1" bitfld.long 0x0 7. " PKT_INTERRUPT_CPBLTY ,End of Packet detection capability." "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_INTERRUPT_CPBLTY ,Transaction error detection capability." "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_INTERRUPT_CPBLTY ,Supervisor error detection capability." "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR_INTERRUPT_CPBLTY ,Misaligned error detection capability." "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END_INTERRUPT_CPBLTY ,Drain End detection capability." "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " EOSB_INTERRUPT_CPBLTY ,End of Super Block detection capability." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x78++0x3 line.long 0x0 "DMA4_GCR,FIFO sharing between high and low priority channel. The Maximum per channel FIFO depth is bounded by the low and high channel FIFO budget. The high respectively low priority channels maximum burst size must be less than the min (high respectively low priority channel FIFO budget, per channel maximum FIFO depth)" hexmask.long.byte 0x0 0.--7. 1. " MAX_CHANNEL_FIFO_DEPTH ,Maximum FIFO depth allocated to one logical channel. Maximum FIFO depth can not be 0x0. It should be at least 0x1 or greater. Note that If channel limit is less than destination burst size enough data will not be accumulated in the data FIFO and it will never be sent out on the WR port. The burst size should be less than the FIFO limit specified in this bit field." bitfld.long 0x0 8.--11. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12.--13. " HI_THREAD_RESERVED ,Allow thread reservation for high priority channel on both read and write ports." "0,1,2,3" bitfld.long 0x0 14.--15. " HI_LO_FIFO_BUDGET ,Allow to have a separate Global FIFO budget for high and low priority channels. For Hi priority Channel: (Per_channel_Maximum FIFO depth + 1) x Number of active High priority Channel =< High Budget FIFO For Low priority channel: (Per_channel_Maximum FIFO depth + 1) x Number of active Low priority Channel =< Low Budget FIFO" "0,1,2,3" textline " " hexmask.long.byte 0x0 16.--23. 1. " ARBITRATION_RATE ,Arbitration switching rate between prioritized and regular channel queues" bitfld.long 0x0 24. " CHANNEL_ID_GATE ,Gates the Channel ID bus monitoring on both Read and Write ports 0x0: Gates the Channel ID qualifiers on both Read and Write Ports 0x1: Does not gate the Channel ID qualifiers on both Read and Write Ports" "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x80++0x3 line.long 0x0 "DMA4_CCRi_0,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0xE0++0x3 line.long 0x0 "DMA4_CCRi_1,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x140++0x3 line.long 0x0 "DMA4_CCRi_2,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x1A0++0x3 line.long 0x0 "DMA4_CCRi_3,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x200++0x3 line.long 0x0 "DMA4_CCRi_4,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x260++0x3 line.long 0x0 "DMA4_CCRi_5,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x2C0++0x3 line.long 0x0 "DMA4_CCRi_6,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x320++0x3 line.long 0x0 "DMA4_CCRi_7,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x380++0x3 line.long 0x0 "DMA4_CCRi_8,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x3E0++0x3 line.long 0x0 "DMA4_CCRi_9,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x440++0x3 line.long 0x0 "DMA4_CCRi_10,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x4A0++0x3 line.long 0x0 "DMA4_CCRi_11,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x500++0x3 line.long 0x0 "DMA4_CCRi_12,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x560++0x3 line.long 0x0 "DMA4_CCRi_13,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x5C0++0x3 line.long 0x0 "DMA4_CCRi_14,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x620++0x3 line.long 0x0 "DMA4_CCRi_15,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x680++0x3 line.long 0x0 "DMA4_CCRi_16,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x6E0++0x3 line.long 0x0 "DMA4_CCRi_17,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x740++0x3 line.long 0x0 "DMA4_CCRi_18,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x7A0++0x3 line.long 0x0 "DMA4_CCRi_19,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x800++0x3 line.long 0x0 "DMA4_CCRi_20,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x860++0x3 line.long 0x0 "DMA4_CCRi_21,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x8C0++0x3 line.long 0x0 "DMA4_CCRi_22,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x920++0x3 line.long 0x0 "DMA4_CCRi_23,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x980++0x3 line.long 0x0 "DMA4_CCRi_24,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x9E0++0x3 line.long 0x0 "DMA4_CCRi_25,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0xA40++0x3 line.long 0x0 "DMA4_CCRi_26,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0xAA0++0x3 line.long 0x0 "DMA4_CCRi_27,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0xB00++0x3 line.long 0x0 "DMA4_CCRi_28,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0xB60++0x3 line.long 0x0 "DMA4_CCRi_29,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0xBC0++0x3 line.long 0x0 "DMA4_CCRi_30,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0xC20++0x3 line.long 0x0 "DMA4_CCRi_31,Channel Control Register" bitfld.long 0x0 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control This bit field used in conjunction with the second_level_ synchro_control_upper (as 2 MSB) 0000000 : Is reserved for non synchronized LCH transfer xxxxxxx (from 1 to 127)There are 127 possible DMA request to assign to any LCH. Note: The channel synchronization control registers are 1-based. For example, to enable the S_DMA_1 request, DMA4_CCR[4:0] SYNCHRO_CONTROL must be set to 0x2 (DMA request number + 1)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " FS ,Frame synchronization This bit used in conjunction with the BS to see how the DMA request is serviced in a synchronized transfer FS = 0 and BS = 0: An element is transferred once a DMA request is made. FS = 0 and BS = 1: An entire block is transferred once a DMA request is made. FS = 1 and BS = 0: An entire frame is transferred once a DMA request is made. FS = 1 and BS = 1: A packet is transferred once a DMA request is made. All these different transfers can be interleaved on the port with other DMA requests." "0,1" textline " " bitfld.long 0x0 6. " READ_PRIORITY ,Channel priority on the read side" "0,1" bitfld.long 0x0 7. " ENABLE ,Logical channel enable. It is SW responsibility to clear the CSR register and the IRQSTATUS bit for the different interrupt lines before enabling the channel." "0,1" textline " " bitfld.long 0x0 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable bit" "0,1" bitfld.long 0x0 9. " RD_ACTIVE ,Indicates if the channel read context is active or not" "0,1" textline " " bitfld.long 0x0 10. " WR_ACTIVE ,Indicates if the channel write context is active or not" "0,1" bitfld.long 0x0 11. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" textline " " bitfld.long 0x0 12.--13. " SRC_AMODE ,Selects the addressing mode on the Read Port of a channel." "0,1,2,3" bitfld.long 0x0 14.--15. " DST_AMODE ,Selects the addressing mode on the Write Port of a channel." "0,1,2,3" textline " " bitfld.long 0x0 16. " CONST_FILL_ENABLE ,Constant fill enable" "0,1" bitfld.long 0x0 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "0,1" textline " " bitfld.long 0x0 18. " BS ,Block synchronization This bit used in conjunction with the fs to see how the DMA request is serviced in a synchronized transfer." "0,1" bitfld.long 0x0 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper (used in conjunction with the 5 bits of synchro channelDMA4_CCRi[4:0]) Used in conjunction, as 2 MSB, with the 5 bits of the synchro channel bit field." "0,1,2,3" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved for non-GP devices" "0,1" bitfld.long 0x0 22. " SUPERVISOR ,Enables the supervisor mode" "0,1" textline " " bitfld.long 0x0 23. " PREFETCH ,Enables the prefetch mode" "0,1" bitfld.long 0x0 24. " SEL_SRC_DST_SYNC ,Specifies that element, packet, frame or block transfer (depending on CCR.bs and CCR.fs) is triggered by the source or the destination on the DMA request" "0,1" textline " " bitfld.long 0x0 25. " BUFFERING_DISABLE ,This bit allows to disable the default buffering functionality when transfer is source synchronized." "0,1" bitfld.long 0x0 26. " WRITE_PRIORITY ,Channel priority on the Write side" "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ,Reserved for non-GP devices" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1,2,3" group.byte 0x84++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_0,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xE4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_1,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x144++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_2,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1A4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_3,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x204++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_4,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x264++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_5,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2C4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_6,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x324++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_7,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x384++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_8,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3E4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_9,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x444++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_10,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4A4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_11,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x504++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_12,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x564++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_13,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5C4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_14,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x624++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_15,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x684++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_16,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6E4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_17,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x744++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_18,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7A4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_19,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x804++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_20,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x864++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_21,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8C4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_22,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x924++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_23,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x984++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_24,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9E4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_25,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA44++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_26,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xAA4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_27,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB04++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_28,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB64++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_29,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBC4++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_30,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC24++0x3 line.long 0x0 "DMA4_CLNK_CTRLi_31,Channel Link Control Register" bitfld.long 0x0 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID, which is used to build logical channel chaining queue." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--14. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." textline " " bitfld.long 0x0 15. " ENABLE_LNK ,Enables or disable the channel linking." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x88++0x3 line.long 0x0 "DMA4_CICRi_0,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xE8++0x3 line.long 0x0 "DMA4_CICRi_1,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x148++0x3 line.long 0x0 "DMA4_CICRi_2,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1A8++0x3 line.long 0x0 "DMA4_CICRi_3,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x208++0x3 line.long 0x0 "DMA4_CICRi_4,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x268++0x3 line.long 0x0 "DMA4_CICRi_5,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2C8++0x3 line.long 0x0 "DMA4_CICRi_6,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x328++0x3 line.long 0x0 "DMA4_CICRi_7,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x388++0x3 line.long 0x0 "DMA4_CICRi_8,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3E8++0x3 line.long 0x0 "DMA4_CICRi_9,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x448++0x3 line.long 0x0 "DMA4_CICRi_10,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4A8++0x3 line.long 0x0 "DMA4_CICRi_11,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x508++0x3 line.long 0x0 "DMA4_CICRi_12,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x568++0x3 line.long 0x0 "DMA4_CICRi_13,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5C8++0x3 line.long 0x0 "DMA4_CICRi_14,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x628++0x3 line.long 0x0 "DMA4_CICRi_15,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x688++0x3 line.long 0x0 "DMA4_CICRi_16,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6E8++0x3 line.long 0x0 "DMA4_CICRi_17,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x748++0x3 line.long 0x0 "DMA4_CICRi_18,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7A8++0x3 line.long 0x0 "DMA4_CICRi_19,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x808++0x3 line.long 0x0 "DMA4_CICRi_20,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x868++0x3 line.long 0x0 "DMA4_CICRi_21,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8C8++0x3 line.long 0x0 "DMA4_CICRi_22,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x928++0x3 line.long 0x0 "DMA4_CICRi_23,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x988++0x3 line.long 0x0 "DMA4_CICRi_24,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9E8++0x3 line.long 0x0 "DMA4_CICRi_25,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA48++0x3 line.long 0x0 "DMA4_CICRi_26,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xAA8++0x3 line.long 0x0 "DMA4_CICRi_27,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB08++0x3 line.long 0x0 "DMA4_CICRi_28,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB68++0x3 line.long 0x0 "DMA4_CICRi_29,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBC8++0x3 line.long 0x0 "DMA4_CICRi_30,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC28++0x3 line.long 0x0 "DMA4_CICRi_31,Channel Interrupt Control Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "0,1" textline " " bitfld.long 0x0 2. " HALF_IE ,Enables or disables the half frame interrupt." "0,1" bitfld.long 0x0 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "0,1" textline " " bitfld.long 0x0 4. " LAST_IE ,Last frame interrupt enable (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK_IE ,Enables the end of block interrupt" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 7. " PKT_IE ,Enables the end of Packet interrupt" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "0,1" bitfld.long 0x0 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_IE ,Enables the end of draining interrupt" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK_IE ,Enables the end of super block interrupt" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8C++0x3 line.long 0x0 "DMA4_CSRi_0,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xEC++0x3 line.long 0x0 "DMA4_CSRi_1,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x14C++0x3 line.long 0x0 "DMA4_CSRi_2,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1AC++0x3 line.long 0x0 "DMA4_CSRi_3,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x20C++0x3 line.long 0x0 "DMA4_CSRi_4,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x26C++0x3 line.long 0x0 "DMA4_CSRi_5,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2CC++0x3 line.long 0x0 "DMA4_CSRi_6,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x32C++0x3 line.long 0x0 "DMA4_CSRi_7,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x38C++0x3 line.long 0x0 "DMA4_CSRi_8,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3EC++0x3 line.long 0x0 "DMA4_CSRi_9,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x44C++0x3 line.long 0x0 "DMA4_CSRi_10,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4AC++0x3 line.long 0x0 "DMA4_CSRi_11,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x50C++0x3 line.long 0x0 "DMA4_CSRi_12,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x56C++0x3 line.long 0x0 "DMA4_CSRi_13,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5CC++0x3 line.long 0x0 "DMA4_CSRi_14,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x62C++0x3 line.long 0x0 "DMA4_CSRi_15,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x68C++0x3 line.long 0x0 "DMA4_CSRi_16,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6EC++0x3 line.long 0x0 "DMA4_CSRi_17,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x74C++0x3 line.long 0x0 "DMA4_CSRi_18,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7AC++0x3 line.long 0x0 "DMA4_CSRi_19,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x80C++0x3 line.long 0x0 "DMA4_CSRi_20,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x86C++0x3 line.long 0x0 "DMA4_CSRi_21,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8CC++0x3 line.long 0x0 "DMA4_CSRi_22,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x92C++0x3 line.long 0x0 "DMA4_CSRi_23,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x98C++0x3 line.long 0x0 "DMA4_CSRi_24,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9EC++0x3 line.long 0x0 "DMA4_CSRi_25,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA4C++0x3 line.long 0x0 "DMA4_CSRi_26,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xAAC++0x3 line.long 0x0 "DMA4_CSRi_27,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB0C++0x3 line.long 0x0 "DMA4_CSRi_28,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB6C++0x3 line.long 0x0 "DMA4_CSRi_29,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBCC++0x3 line.long 0x0 "DMA4_CSRi_30,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC2C++0x3 line.long 0x0 "DMA4_CSRi_31,Channel Status Register" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Read returns 0." "0,1" bitfld.long 0x0 1. " DROP ,Synchronization event drop occured during the transfer" "0,1" textline " " bitfld.long 0x0 2. " HALF ,Half of frame event." "0,1" bitfld.long 0x0 3. " FRAME ,End of frame event" "0,1" textline " " bitfld.long 0x0 4. " LAST ,Last frame (start of last frame)" "0,1" bitfld.long 0x0 5. " BLOCK ,End of block event" "0,1" textline " " bitfld.long 0x0 6. " SYNC ,Synchronization status of a channel." "0,1" bitfld.long 0x0 7. " PKT ,End of Packet transfer" "0,1" textline " " bitfld.long 0x0 8. " TRANS_ERR ,Transaction error event" "0,1" bitfld.long 0x0 9. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "0,1" bitfld.long 0x0 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "0,1" textline " " bitfld.long 0x0 12. " DRAIN_END ,End of channel draining Read 0x0: No drain end in the current transfer Write 0x0: Status bit unchanged Read 0x1: The current channel draining is completed Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 13. " RESERVED ,Reserved for non-GP devices" "0,1" textline " " bitfld.long 0x0 14. " SUPER_BLOCK ,End of Super block event Read 0x0: The current Super block transfer has not been finished Write 0x0: Status bit unchanged Read 0x1: The current Super block has been transferred Write 0x1: Status bit is reset" "0,1" bitfld.long 0x0 15.--16. " RESERVED ,Reserved for debug (Monitor descriptor/data load phase), Write 0's for future compatibility, Read returns 0" "0,1,2,3" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x90++0x3 line.long 0x0 "DMA4_CSDPi_0,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xF0++0x3 line.long 0x0 "DMA4_CSDPi_1,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x150++0x3 line.long 0x0 "DMA4_CSDPi_2,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1B0++0x3 line.long 0x0 "DMA4_CSDPi_3,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x210++0x3 line.long 0x0 "DMA4_CSDPi_4,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x270++0x3 line.long 0x0 "DMA4_CSDPi_5,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2D0++0x3 line.long 0x0 "DMA4_CSDPi_6,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x330++0x3 line.long 0x0 "DMA4_CSDPi_7,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x390++0x3 line.long 0x0 "DMA4_CSDPi_8,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3F0++0x3 line.long 0x0 "DMA4_CSDPi_9,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x450++0x3 line.long 0x0 "DMA4_CSDPi_10,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4B0++0x3 line.long 0x0 "DMA4_CSDPi_11,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x510++0x3 line.long 0x0 "DMA4_CSDPi_12,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x570++0x3 line.long 0x0 "DMA4_CSDPi_13,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5D0++0x3 line.long 0x0 "DMA4_CSDPi_14,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x630++0x3 line.long 0x0 "DMA4_CSDPi_15,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x690++0x3 line.long 0x0 "DMA4_CSDPi_16,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6F0++0x3 line.long 0x0 "DMA4_CSDPi_17,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x750++0x3 line.long 0x0 "DMA4_CSDPi_18,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7B0++0x3 line.long 0x0 "DMA4_CSDPi_19,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x810++0x3 line.long 0x0 "DMA4_CSDPi_20,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x870++0x3 line.long 0x0 "DMA4_CSDPi_21,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8D0++0x3 line.long 0x0 "DMA4_CSDPi_22,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x930++0x3 line.long 0x0 "DMA4_CSDPi_23,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x990++0x3 line.long 0x0 "DMA4_CSDPi_24,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9F0++0x3 line.long 0x0 "DMA4_CSDPi_25,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA50++0x3 line.long 0x0 "DMA4_CSDPi_26,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xAB0++0x3 line.long 0x0 "DMA4_CSDPi_27,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB10++0x3 line.long 0x0 "DMA4_CSDPi_28,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB70++0x3 line.long 0x0 "DMA4_CSDPi_29,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBD0++0x3 line.long 0x0 "DMA4_CSDPi_30,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC30++0x3 line.long 0x0 "DMA4_CSDPi_31,Channel Source Destination Parameters" bitfld.long 0x0 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel." "0,1,2,3" bitfld.long 0x0 2.--5. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 6. " SRC_PACKED ,Source provides packed data." "0,1" bitfld.long 0x0 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" textline " " bitfld.long 0x0 9.--12. " RESERVED ,Write the reset value. Read returns reset value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 13. " DST_PACKED ,Destination receives packed data." "0,1" textline " " bitfld.long 0x0 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port. Smaller burst size than the programmed burst size is also allowed" "0,1,2,3" bitfld.long 0x0 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "0,1,2,3" textline " " bitfld.long 0x0 18. " DST_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 19. " DST_ENDIAN ,Channel Destination endianness control" "0,1" textline " " bitfld.long 0x0 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "0,1" bitfld.long 0x0 21. " SRC_ENDIAN ,Channel source endianness control" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x94++0x3 line.long 0x0 "DMA4_CENi_0,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xF4++0x3 line.long 0x0 "DMA4_CENi_1,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x154++0x3 line.long 0x0 "DMA4_CENi_2,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1B4++0x3 line.long 0x0 "DMA4_CENi_3,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x214++0x3 line.long 0x0 "DMA4_CENi_4,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x274++0x3 line.long 0x0 "DMA4_CENi_5,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2D4++0x3 line.long 0x0 "DMA4_CENi_6,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x334++0x3 line.long 0x0 "DMA4_CENi_7,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x394++0x3 line.long 0x0 "DMA4_CENi_8,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3F4++0x3 line.long 0x0 "DMA4_CENi_9,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x454++0x3 line.long 0x0 "DMA4_CENi_10,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4B4++0x3 line.long 0x0 "DMA4_CENi_11,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x514++0x3 line.long 0x0 "DMA4_CENi_12,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x574++0x3 line.long 0x0 "DMA4_CENi_13,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5D4++0x3 line.long 0x0 "DMA4_CENi_14,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x634++0x3 line.long 0x0 "DMA4_CENi_15,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x694++0x3 line.long 0x0 "DMA4_CENi_16,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6F4++0x3 line.long 0x0 "DMA4_CENi_17,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x754++0x3 line.long 0x0 "DMA4_CENi_18,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7B4++0x3 line.long 0x0 "DMA4_CENi_19,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x814++0x3 line.long 0x0 "DMA4_CENi_20,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x874++0x3 line.long 0x0 "DMA4_CENi_21,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8D4++0x3 line.long 0x0 "DMA4_CENi_22,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x934++0x3 line.long 0x0 "DMA4_CENi_23,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x994++0x3 line.long 0x0 "DMA4_CENi_24,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9F4++0x3 line.long 0x0 "DMA4_CENi_25,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA54++0x3 line.long 0x0 "DMA4_CENi_26,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xAB4++0x3 line.long 0x0 "DMA4_CENi_27,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB14++0x3 line.long 0x0 "DMA4_CENi_28,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB74++0x3 line.long 0x0 "DMA4_CENi_29,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBD4++0x3 line.long 0x0 "DMA4_CENi_30,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC34++0x3 line.long 0x0 "DMA4_CENi_31,Channel Element Number" hexmask.long.tbyte 0x0 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x98++0x3 line.long 0x0 "DMA4_CFNi_0,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xF8++0x3 line.long 0x0 "DMA4_CFNi_1,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x158++0x3 line.long 0x0 "DMA4_CFNi_2,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1B8++0x3 line.long 0x0 "DMA4_CFNi_3,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x218++0x3 line.long 0x0 "DMA4_CFNi_4,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x278++0x3 line.long 0x0 "DMA4_CFNi_5,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2D8++0x3 line.long 0x0 "DMA4_CFNi_6,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x338++0x3 line.long 0x0 "DMA4_CFNi_7,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x398++0x3 line.long 0x0 "DMA4_CFNi_8,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3F8++0x3 line.long 0x0 "DMA4_CFNi_9,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x458++0x3 line.long 0x0 "DMA4_CFNi_10,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4B8++0x3 line.long 0x0 "DMA4_CFNi_11,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x518++0x3 line.long 0x0 "DMA4_CFNi_12,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x578++0x3 line.long 0x0 "DMA4_CFNi_13,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5D8++0x3 line.long 0x0 "DMA4_CFNi_14,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x638++0x3 line.long 0x0 "DMA4_CFNi_15,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x698++0x3 line.long 0x0 "DMA4_CFNi_16,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6F8++0x3 line.long 0x0 "DMA4_CFNi_17,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x758++0x3 line.long 0x0 "DMA4_CFNi_18,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7B8++0x3 line.long 0x0 "DMA4_CFNi_19,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x818++0x3 line.long 0x0 "DMA4_CFNi_20,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x878++0x3 line.long 0x0 "DMA4_CFNi_21,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8D8++0x3 line.long 0x0 "DMA4_CFNi_22,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x938++0x3 line.long 0x0 "DMA4_CFNi_23,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x998++0x3 line.long 0x0 "DMA4_CFNi_24,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9F8++0x3 line.long 0x0 "DMA4_CFNi_25,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA58++0x3 line.long 0x0 "DMA4_CFNi_26,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xAB8++0x3 line.long 0x0 "DMA4_CFNi_27,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB18++0x3 line.long 0x0 "DMA4_CFNi_28,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB78++0x3 line.long 0x0 "DMA4_CFNi_29,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBD8++0x3 line.long 0x0 "DMA4_CFNi_30,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC38++0x3 line.long 0x0 "DMA4_CFNi_31,Channel Frame Number" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred (unsigned)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9C++0x3 line.long 0x0 "DMA4_CSSAi_0,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0xFC++0x3 line.long 0x0 "DMA4_CSSAi_1,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x15C++0x3 line.long 0x0 "DMA4_CSSAi_2,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x1BC++0x3 line.long 0x0 "DMA4_CSSAi_3,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x21C++0x3 line.long 0x0 "DMA4_CSSAi_4,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x27C++0x3 line.long 0x0 "DMA4_CSSAi_5,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x2DC++0x3 line.long 0x0 "DMA4_CSSAi_6,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x33C++0x3 line.long 0x0 "DMA4_CSSAi_7,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x39C++0x3 line.long 0x0 "DMA4_CSSAi_8,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x3FC++0x3 line.long 0x0 "DMA4_CSSAi_9,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x45C++0x3 line.long 0x0 "DMA4_CSSAi_10,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x4BC++0x3 line.long 0x0 "DMA4_CSSAi_11,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x51C++0x3 line.long 0x0 "DMA4_CSSAi_12,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x57C++0x3 line.long 0x0 "DMA4_CSSAi_13,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x5DC++0x3 line.long 0x0 "DMA4_CSSAi_14,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x63C++0x3 line.long 0x0 "DMA4_CSSAi_15,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x69C++0x3 line.long 0x0 "DMA4_CSSAi_16,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x6FC++0x3 line.long 0x0 "DMA4_CSSAi_17,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x75C++0x3 line.long 0x0 "DMA4_CSSAi_18,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x7BC++0x3 line.long 0x0 "DMA4_CSSAi_19,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x81C++0x3 line.long 0x0 "DMA4_CSSAi_20,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x87C++0x3 line.long 0x0 "DMA4_CSSAi_21,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x8DC++0x3 line.long 0x0 "DMA4_CSSAi_22,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x93C++0x3 line.long 0x0 "DMA4_CSSAi_23,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x99C++0x3 line.long 0x0 "DMA4_CSSAi_24,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0x9FC++0x3 line.long 0x0 "DMA4_CSSAi_25,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0xA5C++0x3 line.long 0x0 "DMA4_CSSAi_26,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0xABC++0x3 line.long 0x0 "DMA4_CSSAi_27,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0xB1C++0x3 line.long 0x0 "DMA4_CSSAi_28,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0xB7C++0x3 line.long 0x0 "DMA4_CSSAi_29,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0xBDC++0x3 line.long 0x0 "DMA4_CSSAi_30,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0xC3C++0x3 line.long 0x0 "DMA4_CSSAi_31,Channel Source Start Address" hexmask.long 0x0 0.--31. 1. " SRC_START_ADRS ,32 bits of the source start address" group.byte 0xA0++0x3 line.long 0x0 "DMA4_CDSAi_0,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x100++0x3 line.long 0x0 "DMA4_CDSAi_1,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x160++0x3 line.long 0x0 "DMA4_CDSAi_2,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x1C0++0x3 line.long 0x0 "DMA4_CDSAi_3,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x220++0x3 line.long 0x0 "DMA4_CDSAi_4,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x280++0x3 line.long 0x0 "DMA4_CDSAi_5,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x2E0++0x3 line.long 0x0 "DMA4_CDSAi_6,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x340++0x3 line.long 0x0 "DMA4_CDSAi_7,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x3A0++0x3 line.long 0x0 "DMA4_CDSAi_8,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x400++0x3 line.long 0x0 "DMA4_CDSAi_9,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x460++0x3 line.long 0x0 "DMA4_CDSAi_10,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x4C0++0x3 line.long 0x0 "DMA4_CDSAi_11,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x520++0x3 line.long 0x0 "DMA4_CDSAi_12,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x580++0x3 line.long 0x0 "DMA4_CDSAi_13,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x5E0++0x3 line.long 0x0 "DMA4_CDSAi_14,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x640++0x3 line.long 0x0 "DMA4_CDSAi_15,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x6A0++0x3 line.long 0x0 "DMA4_CDSAi_16,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x700++0x3 line.long 0x0 "DMA4_CDSAi_17,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x760++0x3 line.long 0x0 "DMA4_CDSAi_18,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x7C0++0x3 line.long 0x0 "DMA4_CDSAi_19,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x820++0x3 line.long 0x0 "DMA4_CDSAi_20,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x880++0x3 line.long 0x0 "DMA4_CDSAi_21,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x8E0++0x3 line.long 0x0 "DMA4_CDSAi_22,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x940++0x3 line.long 0x0 "DMA4_CDSAi_23,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0x9A0++0x3 line.long 0x0 "DMA4_CDSAi_24,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0xA00++0x3 line.long 0x0 "DMA4_CDSAi_25,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0xA60++0x3 line.long 0x0 "DMA4_CDSAi_26,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0xAC0++0x3 line.long 0x0 "DMA4_CDSAi_27,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0xB20++0x3 line.long 0x0 "DMA4_CDSAi_28,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0xB80++0x3 line.long 0x0 "DMA4_CDSAi_29,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0xBE0++0x3 line.long 0x0 "DMA4_CDSAi_30,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0xC40++0x3 line.long 0x0 "DMA4_CDSAi_31,Channel Destination Start Address" hexmask.long 0x0 0.--31. 1. " DST_START_ADRS ,32 bits of the destination start address" group.byte 0xA4++0x3 line.long 0x0 "DMA4_CSEIi_0,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x104++0x3 line.long 0x0 "DMA4_CSEIi_1,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x164++0x3 line.long 0x0 "DMA4_CSEIi_2,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1C4++0x3 line.long 0x0 "DMA4_CSEIi_3,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x224++0x3 line.long 0x0 "DMA4_CSEIi_4,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x284++0x3 line.long 0x0 "DMA4_CSEIi_5,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2E4++0x3 line.long 0x0 "DMA4_CSEIi_6,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x344++0x3 line.long 0x0 "DMA4_CSEIi_7,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3A4++0x3 line.long 0x0 "DMA4_CSEIi_8,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x404++0x3 line.long 0x0 "DMA4_CSEIi_9,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x464++0x3 line.long 0x0 "DMA4_CSEIi_10,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4C4++0x3 line.long 0x0 "DMA4_CSEIi_11,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x524++0x3 line.long 0x0 "DMA4_CSEIi_12,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x584++0x3 line.long 0x0 "DMA4_CSEIi_13,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5E4++0x3 line.long 0x0 "DMA4_CSEIi_14,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x644++0x3 line.long 0x0 "DMA4_CSEIi_15,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6A4++0x3 line.long 0x0 "DMA4_CSEIi_16,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x704++0x3 line.long 0x0 "DMA4_CSEIi_17,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x764++0x3 line.long 0x0 "DMA4_CSEIi_18,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7C4++0x3 line.long 0x0 "DMA4_CSEIi_19,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x824++0x3 line.long 0x0 "DMA4_CSEIi_20,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x884++0x3 line.long 0x0 "DMA4_CSEIi_21,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8E4++0x3 line.long 0x0 "DMA4_CSEIi_22,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x944++0x3 line.long 0x0 "DMA4_CSEIi_23,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9A4++0x3 line.long 0x0 "DMA4_CSEIi_24,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA04++0x3 line.long 0x0 "DMA4_CSEIi_25,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA64++0x3 line.long 0x0 "DMA4_CSEIi_26,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xAC4++0x3 line.long 0x0 "DMA4_CSEIi_27,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB24++0x3 line.long 0x0 "DMA4_CSEIi_28,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB84++0x3 line.long 0x0 "DMA4_CSEIi_29,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBE4++0x3 line.long 0x0 "DMA4_CSEIi_30,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC44++0x3 line.long 0x0 "DMA4_CSEIi_31,Channel Source Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA8++0x3 line.long 0x0 "DMA4_CSFIi_0,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x108++0x3 line.long 0x0 "DMA4_CSFIi_1,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x168++0x3 line.long 0x0 "DMA4_CSFIi_2,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x1C8++0x3 line.long 0x0 "DMA4_CSFIi_3,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x228++0x3 line.long 0x0 "DMA4_CSFIi_4,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x288++0x3 line.long 0x0 "DMA4_CSFIi_5,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x2E8++0x3 line.long 0x0 "DMA4_CSFIi_6,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x348++0x3 line.long 0x0 "DMA4_CSFIi_7,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x3A8++0x3 line.long 0x0 "DMA4_CSFIi_8,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x408++0x3 line.long 0x0 "DMA4_CSFIi_9,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x468++0x3 line.long 0x0 "DMA4_CSFIi_10,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x4C8++0x3 line.long 0x0 "DMA4_CSFIi_11,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x528++0x3 line.long 0x0 "DMA4_CSFIi_12,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x588++0x3 line.long 0x0 "DMA4_CSFIi_13,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x5E8++0x3 line.long 0x0 "DMA4_CSFIi_14,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x648++0x3 line.long 0x0 "DMA4_CSFIi_15,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x6A8++0x3 line.long 0x0 "DMA4_CSFIi_16,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x708++0x3 line.long 0x0 "DMA4_CSFIi_17,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x768++0x3 line.long 0x0 "DMA4_CSFIi_18,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x7C8++0x3 line.long 0x0 "DMA4_CSFIi_19,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x828++0x3 line.long 0x0 "DMA4_CSFIi_20,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x888++0x3 line.long 0x0 "DMA4_CSFIi_21,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x8E8++0x3 line.long 0x0 "DMA4_CSFIi_22,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x948++0x3 line.long 0x0 "DMA4_CSFIi_23,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0x9A8++0x3 line.long 0x0 "DMA4_CSFIi_24,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0xA08++0x3 line.long 0x0 "DMA4_CSFIi_25,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0xA68++0x3 line.long 0x0 "DMA4_CSFIi_26,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0xAC8++0x3 line.long 0x0 "DMA4_CSFIi_27,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0xB28++0x3 line.long 0x0 "DMA4_CSFIi_28,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0xB88++0x3 line.long 0x0 "DMA4_CSFIi_29,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0xBE8++0x3 line.long 0x0 "DMA4_CSFIi_30,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0xC48++0x3 line.long 0x0 "DMA4_CSFIi_31,Channel Source Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_SRC_FRM_INDEX_OR_16BIT_PKT_ELNT_NBR ,Channel source frame index value if source address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC] = 1; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size." group.byte 0xAC++0x3 line.long 0x0 "DMA4_CDEIi_0,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x10C++0x3 line.long 0x0 "DMA4_CDEIi_1,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x16C++0x3 line.long 0x0 "DMA4_CDEIi_2,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1CC++0x3 line.long 0x0 "DMA4_CDEIi_3,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x22C++0x3 line.long 0x0 "DMA4_CDEIi_4,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x28C++0x3 line.long 0x0 "DMA4_CDEIi_5,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2EC++0x3 line.long 0x0 "DMA4_CDEIi_6,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x34C++0x3 line.long 0x0 "DMA4_CDEIi_7,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3AC++0x3 line.long 0x0 "DMA4_CDEIi_8,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x40C++0x3 line.long 0x0 "DMA4_CDEIi_9,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x46C++0x3 line.long 0x0 "DMA4_CDEIi_10,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4CC++0x3 line.long 0x0 "DMA4_CDEIi_11,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x52C++0x3 line.long 0x0 "DMA4_CDEIi_12,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x58C++0x3 line.long 0x0 "DMA4_CDEIi_13,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5EC++0x3 line.long 0x0 "DMA4_CDEIi_14,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x64C++0x3 line.long 0x0 "DMA4_CDEIi_15,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6AC++0x3 line.long 0x0 "DMA4_CDEIi_16,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x70C++0x3 line.long 0x0 "DMA4_CDEIi_17,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x76C++0x3 line.long 0x0 "DMA4_CDEIi_18,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7CC++0x3 line.long 0x0 "DMA4_CDEIi_19,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x82C++0x3 line.long 0x0 "DMA4_CDEIi_20,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x88C++0x3 line.long 0x0 "DMA4_CDEIi_21,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8EC++0x3 line.long 0x0 "DMA4_CDEIi_22,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x94C++0x3 line.long 0x0 "DMA4_CDEIi_23,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9AC++0x3 line.long 0x0 "DMA4_CDEIi_24,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA0C++0x3 line.long 0x0 "DMA4_CDEIi_25,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA6C++0x3 line.long 0x0 "DMA4_CDEIi_26,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xACC++0x3 line.long 0x0 "DMA4_CDEIi_27,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB2C++0x3 line.long 0x0 "DMA4_CDEIi_28,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB8C++0x3 line.long 0x0 "DMA4_CDEIi_29,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBEC++0x3 line.long 0x0 "DMA4_CDEIi_30,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC4C++0x3 line.long 0x0 "DMA4_CDEIi_31,Channel Destination Element Index (Signed)" hexmask.long.word 0x0 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB0++0x3 line.long 0x0 "DMA4_CDFIi_0,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x110++0x3 line.long 0x0 "DMA4_CDFIi_1,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x170++0x3 line.long 0x0 "DMA4_CDFIi_2,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x1D0++0x3 line.long 0x0 "DMA4_CDFIi_3,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x230++0x3 line.long 0x0 "DMA4_CDFIi_4,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x290++0x3 line.long 0x0 "DMA4_CDFIi_5,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x2F0++0x3 line.long 0x0 "DMA4_CDFIi_6,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x350++0x3 line.long 0x0 "DMA4_CDFIi_7,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x3B0++0x3 line.long 0x0 "DMA4_CDFIi_8,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x410++0x3 line.long 0x0 "DMA4_CDFIi_9,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x470++0x3 line.long 0x0 "DMA4_CDFIi_10,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x4D0++0x3 line.long 0x0 "DMA4_CDFIi_11,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x530++0x3 line.long 0x0 "DMA4_CDFIi_12,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x590++0x3 line.long 0x0 "DMA4_CDFIi_13,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x5F0++0x3 line.long 0x0 "DMA4_CDFIi_14,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x650++0x3 line.long 0x0 "DMA4_CDFIi_15,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x6B0++0x3 line.long 0x0 "DMA4_CDFIi_16,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x710++0x3 line.long 0x0 "DMA4_CDFIi_17,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x770++0x3 line.long 0x0 "DMA4_CDFIi_18,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x7D0++0x3 line.long 0x0 "DMA4_CDFIi_19,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x830++0x3 line.long 0x0 "DMA4_CDFIi_20,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x890++0x3 line.long 0x0 "DMA4_CDFIi_21,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x8F0++0x3 line.long 0x0 "DMA4_CDFIi_22,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x950++0x3 line.long 0x0 "DMA4_CDFIi_23,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0x9B0++0x3 line.long 0x0 "DMA4_CDFIi_24,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0xA10++0x3 line.long 0x0 "DMA4_CDFIi_25,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0xA70++0x3 line.long 0x0 "DMA4_CDFIi_26,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0xAD0++0x3 line.long 0x0 "DMA4_CDFIi_27,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0xB30++0x3 line.long 0x0 "DMA4_CDFIi_28,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0xB90++0x3 line.long 0x0 "DMA4_CDFIi_29,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0xBF0++0x3 line.long 0x0 "DMA4_CDFIi_30,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0xC50++0x3 line.long 0x0 "DMA4_CDFIi_31,Channel Destination Frame Index (Signed) or 16-bit Packet size" hexmask.long 0x0 0.--31. 1. " CH_DST_FRM_IDX_OR_16BIT_PKT_ELNT_NBR ,Channel destination frame index value if destination address is in double index mode. Or if fs=bs=1 and DMA_CCR[SEL_SRC_DST_SYNC]=0; the bit field [15:0] gives the number of element in packet. The field [31:16] is unused for the packet size.." group.byte 0xB4++0x3 line.long 0x0 "DMA4_CSACi_0,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x114++0x3 line.long 0x0 "DMA4_CSACi_1,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x174++0x3 line.long 0x0 "DMA4_CSACi_2,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x1D4++0x3 line.long 0x0 "DMA4_CSACi_3,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x234++0x3 line.long 0x0 "DMA4_CSACi_4,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x294++0x3 line.long 0x0 "DMA4_CSACi_5,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x2F4++0x3 line.long 0x0 "DMA4_CSACi_6,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x354++0x3 line.long 0x0 "DMA4_CSACi_7,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x3B4++0x3 line.long 0x0 "DMA4_CSACi_8,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x414++0x3 line.long 0x0 "DMA4_CSACi_9,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x474++0x3 line.long 0x0 "DMA4_CSACi_10,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x4D4++0x3 line.long 0x0 "DMA4_CSACi_11,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x534++0x3 line.long 0x0 "DMA4_CSACi_12,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x594++0x3 line.long 0x0 "DMA4_CSACi_13,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x5F4++0x3 line.long 0x0 "DMA4_CSACi_14,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x654++0x3 line.long 0x0 "DMA4_CSACi_15,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x6B4++0x3 line.long 0x0 "DMA4_CSACi_16,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x714++0x3 line.long 0x0 "DMA4_CSACi_17,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x774++0x3 line.long 0x0 "DMA4_CSACi_18,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x7D4++0x3 line.long 0x0 "DMA4_CSACi_19,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x834++0x3 line.long 0x0 "DMA4_CSACi_20,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x894++0x3 line.long 0x0 "DMA4_CSACi_21,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x8F4++0x3 line.long 0x0 "DMA4_CSACi_22,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x954++0x3 line.long 0x0 "DMA4_CSACi_23,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0x9B4++0x3 line.long 0x0 "DMA4_CSACi_24,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0xA14++0x3 line.long 0x0 "DMA4_CSACi_25,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0xA74++0x3 line.long 0x0 "DMA4_CSACi_26,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0xAD4++0x3 line.long 0x0 "DMA4_CSACi_27,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0xB34++0x3 line.long 0x0 "DMA4_CSACi_28,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0xB94++0x3 line.long 0x0 "DMA4_CSACi_29,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0xBF4++0x3 line.long 0x0 "DMA4_CSACi_30,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0xC54++0x3 line.long 0x0 "DMA4_CSACi_31,Channel Source Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " SRC_ELMNT_ADRS ,Current source address counter value" group.byte 0xB8++0x3 line.long 0x0 "DMA4_CDACi_0,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x118++0x3 line.long 0x0 "DMA4_CDACi_1,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x178++0x3 line.long 0x0 "DMA4_CDACi_2,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x1D8++0x3 line.long 0x0 "DMA4_CDACi_3,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x238++0x3 line.long 0x0 "DMA4_CDACi_4,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x298++0x3 line.long 0x0 "DMA4_CDACi_5,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x2F8++0x3 line.long 0x0 "DMA4_CDACi_6,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x358++0x3 line.long 0x0 "DMA4_CDACi_7,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x3B8++0x3 line.long 0x0 "DMA4_CDACi_8,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x418++0x3 line.long 0x0 "DMA4_CDACi_9,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x478++0x3 line.long 0x0 "DMA4_CDACi_10,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x4D8++0x3 line.long 0x0 "DMA4_CDACi_11,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x538++0x3 line.long 0x0 "DMA4_CDACi_12,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x598++0x3 line.long 0x0 "DMA4_CDACi_13,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x5F8++0x3 line.long 0x0 "DMA4_CDACi_14,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x658++0x3 line.long 0x0 "DMA4_CDACi_15,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x6B8++0x3 line.long 0x0 "DMA4_CDACi_16,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x718++0x3 line.long 0x0 "DMA4_CDACi_17,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x778++0x3 line.long 0x0 "DMA4_CDACi_18,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x7D8++0x3 line.long 0x0 "DMA4_CDACi_19,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x838++0x3 line.long 0x0 "DMA4_CDACi_20,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x898++0x3 line.long 0x0 "DMA4_CDACi_21,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x8F8++0x3 line.long 0x0 "DMA4_CDACi_22,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x958++0x3 line.long 0x0 "DMA4_CDACi_23,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0x9B8++0x3 line.long 0x0 "DMA4_CDACi_24,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0xA18++0x3 line.long 0x0 "DMA4_CDACi_25,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0xA78++0x3 line.long 0x0 "DMA4_CDACi_26,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0xAD8++0x3 line.long 0x0 "DMA4_CDACi_27,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0xB38++0x3 line.long 0x0 "DMA4_CDACi_28,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0xB98++0x3 line.long 0x0 "DMA4_CDACi_29,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0xBF8++0x3 line.long 0x0 "DMA4_CDACi_30,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0xC58++0x3 line.long 0x0 "DMA4_CDACi_31,Channel Destination Address Value. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long 0x0 0.--31. 1. " DST_ELMNT_ADRS ,Current destination address counter value" group.byte 0xBC++0x3 line.long 0x0 "DMA4_CCENi_0,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x11C++0x3 line.long 0x0 "DMA4_CCENi_1,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x17C++0x3 line.long 0x0 "DMA4_CCENi_2,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1DC++0x3 line.long 0x0 "DMA4_CCENi_3,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x23C++0x3 line.long 0x0 "DMA4_CCENi_4,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x29C++0x3 line.long 0x0 "DMA4_CCENi_5,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2FC++0x3 line.long 0x0 "DMA4_CCENi_6,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x35C++0x3 line.long 0x0 "DMA4_CCENi_7,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3BC++0x3 line.long 0x0 "DMA4_CCENi_8,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x41C++0x3 line.long 0x0 "DMA4_CCENi_9,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x47C++0x3 line.long 0x0 "DMA4_CCENi_10,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4DC++0x3 line.long 0x0 "DMA4_CCENi_11,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x53C++0x3 line.long 0x0 "DMA4_CCENi_12,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x59C++0x3 line.long 0x0 "DMA4_CCENi_13,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5FC++0x3 line.long 0x0 "DMA4_CCENi_14,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x65C++0x3 line.long 0x0 "DMA4_CCENi_15,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6BC++0x3 line.long 0x0 "DMA4_CCENi_16,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x71C++0x3 line.long 0x0 "DMA4_CCENi_17,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x77C++0x3 line.long 0x0 "DMA4_CCENi_18,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7DC++0x3 line.long 0x0 "DMA4_CCENi_19,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x83C++0x3 line.long 0x0 "DMA4_CCENi_20,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x89C++0x3 line.long 0x0 "DMA4_CCENi_21,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8FC++0x3 line.long 0x0 "DMA4_CCENi_22,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x95C++0x3 line.long 0x0 "DMA4_CCENi_23,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9BC++0x3 line.long 0x0 "DMA4_CCENi_24,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA1C++0x3 line.long 0x0 "DMA4_CCENi_25,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA7C++0x3 line.long 0x0 "DMA4_CCENi_26,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xADC++0x3 line.long 0x0 "DMA4_CCENi_27,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB3C++0x3 line.long 0x0 "DMA4_CCENi_28,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB9C++0x3 line.long 0x0 "DMA4_CCENi_29,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBFC++0x3 line.long 0x0 "DMA4_CCENi_30,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC5C++0x3 line.long 0x0 "DMA4_CCENi_31,Channel Current Transferred Element Number in the current frame. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.tbyte 0x0 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC0++0x3 line.long 0x0 "DMA4_CCFNi_0,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x120++0x3 line.long 0x0 "DMA4_CCFNi_1,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x180++0x3 line.long 0x0 "DMA4_CCFNi_2,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1E0++0x3 line.long 0x0 "DMA4_CCFNi_3,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x240++0x3 line.long 0x0 "DMA4_CCFNi_4,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2A0++0x3 line.long 0x0 "DMA4_CCFNi_5,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x300++0x3 line.long 0x0 "DMA4_CCFNi_6,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x360++0x3 line.long 0x0 "DMA4_CCFNi_7,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3C0++0x3 line.long 0x0 "DMA4_CCFNi_8,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x420++0x3 line.long 0x0 "DMA4_CCFNi_9,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x480++0x3 line.long 0x0 "DMA4_CCFNi_10,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4E0++0x3 line.long 0x0 "DMA4_CCFNi_11,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x540++0x3 line.long 0x0 "DMA4_CCFNi_12,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5A0++0x3 line.long 0x0 "DMA4_CCFNi_13,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x600++0x3 line.long 0x0 "DMA4_CCFNi_14,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x660++0x3 line.long 0x0 "DMA4_CCFNi_15,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6C0++0x3 line.long 0x0 "DMA4_CCFNi_16,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x720++0x3 line.long 0x0 "DMA4_CCFNi_17,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x780++0x3 line.long 0x0 "DMA4_CCFNi_18,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7E0++0x3 line.long 0x0 "DMA4_CCFNi_19,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x840++0x3 line.long 0x0 "DMA4_CCFNi_20,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8A0++0x3 line.long 0x0 "DMA4_CCFNi_21,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x900++0x3 line.long 0x0 "DMA4_CCFNi_22,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x960++0x3 line.long 0x0 "DMA4_CCFNi_23,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9C0++0x3 line.long 0x0 "DMA4_CCFNi_24,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA20++0x3 line.long 0x0 "DMA4_CCFNi_25,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA80++0x3 line.long 0x0 "DMA4_CCFNi_26,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xAE0++0x3 line.long 0x0 "DMA4_CCFNi_27,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB40++0x3 line.long 0x0 "DMA4_CCFNi_28,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBA0++0x3 line.long 0x0 "DMA4_CCFNi_29,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC00++0x3 line.long 0x0 "DMA4_CCFNi_30,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC60++0x3 line.long 0x0 "DMA4_CCFNi_31,Channel Current Transferred Frame Number in the current transfer. User has to access this register only in 32-bit access. If accessed in 8-bit or 16bit data may be corrupted." hexmask.long.word 0x0 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC4++0x3 line.long 0x0 "DMA4_COLORi_0,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x124++0x3 line.long 0x0 "DMA4_COLORi_1,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x184++0x3 line.long 0x0 "DMA4_COLORi_2,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x1E4++0x3 line.long 0x0 "DMA4_COLORi_3,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x244++0x3 line.long 0x0 "DMA4_COLORi_4,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x2A4++0x3 line.long 0x0 "DMA4_COLORi_5,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x304++0x3 line.long 0x0 "DMA4_COLORi_6,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x364++0x3 line.long 0x0 "DMA4_COLORi_7,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x3C4++0x3 line.long 0x0 "DMA4_COLORi_8,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x424++0x3 line.long 0x0 "DMA4_COLORi_9,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x484++0x3 line.long 0x0 "DMA4_COLORi_10,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x4E4++0x3 line.long 0x0 "DMA4_COLORi_11,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x544++0x3 line.long 0x0 "DMA4_COLORi_12,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x5A4++0x3 line.long 0x0 "DMA4_COLORi_13,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x604++0x3 line.long 0x0 "DMA4_COLORi_14,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x664++0x3 line.long 0x0 "DMA4_COLORi_15,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x6C4++0x3 line.long 0x0 "DMA4_COLORi_16,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x724++0x3 line.long 0x0 "DMA4_COLORi_17,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x784++0x3 line.long 0x0 "DMA4_COLORi_18,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x7E4++0x3 line.long 0x0 "DMA4_COLORi_19,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x844++0x3 line.long 0x0 "DMA4_COLORi_20,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x8A4++0x3 line.long 0x0 "DMA4_COLORi_21,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x904++0x3 line.long 0x0 "DMA4_COLORi_22,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x964++0x3 line.long 0x0 "DMA4_COLORi_23,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0x9C4++0x3 line.long 0x0 "DMA4_COLORi_24,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA24++0x3 line.long 0x0 "DMA4_COLORi_25,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xA84++0x3 line.long 0x0 "DMA4_COLORi_26,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xAE4++0x3 line.long 0x0 "DMA4_COLORi_27,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xB44++0x3 line.long 0x0 "DMA4_COLORi_28,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xBA4++0x3 line.long 0x0 "DMA4_COLORi_29,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC04++0x3 line.long 0x0 "DMA4_COLORi_30,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xC64++0x3 line.long 0x0 "DMA4_COLORi_31,Channel DMA COLOR KEY /SOLID COLOR" hexmask.long.tbyte 0x0 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLID_COLOR_PTRN ,Color key or solid color pattern: The pattern is replicated according to the data type. If the data-type is 8-bit the pattern is replicated 4 times to fill the register in order to enhance processing when data is packed at the graphic module input. The same reasoning for 16-bit data-type." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0." group.byte 0xD0++0x3 line.long 0x0 "DMA4_CDPi_0,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x130++0x3 line.long 0x0 "DMA4_CDPi_1,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x190++0x3 line.long 0x0 "DMA4_CDPi_2,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x1F0++0x3 line.long 0x0 "DMA4_CDPi_3,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x250++0x3 line.long 0x0 "DMA4_CDPi_4,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x2B0++0x3 line.long 0x0 "DMA4_CDPi_5,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x310++0x3 line.long 0x0 "DMA4_CDPi_6,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x370++0x3 line.long 0x0 "DMA4_CDPi_7,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x3D0++0x3 line.long 0x0 "DMA4_CDPi_8,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x430++0x3 line.long 0x0 "DMA4_CDPi_9,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x490++0x3 line.long 0x0 "DMA4_CDPi_10,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x4F0++0x3 line.long 0x0 "DMA4_CDPi_11,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x550++0x3 line.long 0x0 "DMA4_CDPi_12,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x5B0++0x3 line.long 0x0 "DMA4_CDPi_13,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x610++0x3 line.long 0x0 "DMA4_CDPi_14,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x670++0x3 line.long 0x0 "DMA4_CDPi_15,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x6D0++0x3 line.long 0x0 "DMA4_CDPi_16,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x730++0x3 line.long 0x0 "DMA4_CDPi_17,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x790++0x3 line.long 0x0 "DMA4_CDPi_18,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x7F0++0x3 line.long 0x0 "DMA4_CDPi_19,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x850++0x3 line.long 0x0 "DMA4_CDPi_20,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x8B0++0x3 line.long 0x0 "DMA4_CDPi_21,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x910++0x3 line.long 0x0 "DMA4_CDPi_22,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x970++0x3 line.long 0x0 "DMA4_CDPi_23,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x9D0++0x3 line.long 0x0 "DMA4_CDPi_24,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xA30++0x3 line.long 0x0 "DMA4_CDPi_25,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xA90++0x3 line.long 0x0 "DMA4_CDPi_26,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xAF0++0x3 line.long 0x0 "DMA4_CDPi_27,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xB50++0x3 line.long 0x0 "DMA4_CDPi_28,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xBB0++0x3 line.long 0x0 "DMA4_CDPi_29,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xC10++0x3 line.long 0x0 "DMA4_CDPi_30,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xC70++0x3 line.long 0x0 "DMA4_CDPi_31,This register controls the various parameters of the link list mechanism" bitfld.long 0x0 0.--1. " DEST_VALID ,Destination address valid" "0,1,2,3" bitfld.long 0x0 2.--3. " SRC_VALID ,Source address valid" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " NEXT_DESCRIPTOR_TYPE ,Next Descriptor Type" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " PAUSE_LINK_LIST ,Suspend the linked-list transfer at completion of the current block transfer." "0,1" textline " " bitfld.long 0x0 8.--9. " TRANSFER_MODE ,Enable linked-list transfer mode" "0,1,2,3" bitfld.long 0x0 10. " FAST ,Sets the fast-start mode for linked list descriptor types 1, 2 and 3" "0,1" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xD4++0x3 line.long 0x0 "DMA4_CNDPi_0,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x134++0x3 line.long 0x0 "DMA4_CNDPi_1,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x194++0x3 line.long 0x0 "DMA4_CNDPi_2,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x1F4++0x3 line.long 0x0 "DMA4_CNDPi_3,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x254++0x3 line.long 0x0 "DMA4_CNDPi_4,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x2B4++0x3 line.long 0x0 "DMA4_CNDPi_5,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x314++0x3 line.long 0x0 "DMA4_CNDPi_6,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x374++0x3 line.long 0x0 "DMA4_CNDPi_7,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x3D4++0x3 line.long 0x0 "DMA4_CNDPi_8,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x434++0x3 line.long 0x0 "DMA4_CNDPi_9,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x494++0x3 line.long 0x0 "DMA4_CNDPi_10,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x4F4++0x3 line.long 0x0 "DMA4_CNDPi_11,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x554++0x3 line.long 0x0 "DMA4_CNDPi_12,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x5B4++0x3 line.long 0x0 "DMA4_CNDPi_13,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x614++0x3 line.long 0x0 "DMA4_CNDPi_14,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x674++0x3 line.long 0x0 "DMA4_CNDPi_15,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x6D4++0x3 line.long 0x0 "DMA4_CNDPi_16,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x734++0x3 line.long 0x0 "DMA4_CNDPi_17,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x794++0x3 line.long 0x0 "DMA4_CNDPi_18,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x7F4++0x3 line.long 0x0 "DMA4_CNDPi_19,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x854++0x3 line.long 0x0 "DMA4_CNDPi_20,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x8B4++0x3 line.long 0x0 "DMA4_CNDPi_21,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x914++0x3 line.long 0x0 "DMA4_CNDPi_22,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x974++0x3 line.long 0x0 "DMA4_CNDPi_23,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0x9D4++0x3 line.long 0x0 "DMA4_CNDPi_24,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0xA34++0x3 line.long 0x0 "DMA4_CNDPi_25,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0xA94++0x3 line.long 0x0 "DMA4_CNDPi_26,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0xAF4++0x3 line.long 0x0 "DMA4_CNDPi_27,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0xB54++0x3 line.long 0x0 "DMA4_CNDPi_28,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0xBB4++0x3 line.long 0x0 "DMA4_CNDPi_29,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0xC14++0x3 line.long 0x0 "DMA4_CNDPi_30,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0xC74++0x3 line.long 0x0 "DMA4_CNDPi_31,This register contains the Next descriptor Address Pointer for the link list Mechanism" bitfld.long 0x0 0.--1. " RESERVED ,Write 0's for future compatibility, Reads return 0" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " NEXT_DESCRIPTOR_POINTER ,This register contains the Next descriptor Address Pointer for the link list Mechanism" group.byte 0xD8++0x3 line.long 0x0 "DMA4_CCDNi_0,DMA4_CCDNi_0" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x138++0x3 line.long 0x0 "DMA4_CCDNi_1,DMA4_CCDNi_1" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x198++0x3 line.long 0x0 "DMA4_CCDNi_2,DMA4_CCDNi_2" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x1F8++0x3 line.long 0x0 "DMA4_CCDNi_3,DMA4_CCDNi_3" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x258++0x3 line.long 0x0 "DMA4_CCDNi_4,DMA4_CCDNi_4" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x2B8++0x3 line.long 0x0 "DMA4_CCDNi_5,DMA4_CCDNi_5" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x318++0x3 line.long 0x0 "DMA4_CCDNi_6,DMA4_CCDNi_6" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x378++0x3 line.long 0x0 "DMA4_CCDNi_7,DMA4_CCDNi_7" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x3D8++0x3 line.long 0x0 "DMA4_CCDNi_8,DMA4_CCDNi_8" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x438++0x3 line.long 0x0 "DMA4_CCDNi_9,DMA4_CCDNi_9" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x498++0x3 line.long 0x0 "DMA4_CCDNi_10,DMA4_CCDNi_10" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x4F8++0x3 line.long 0x0 "DMA4_CCDNi_11,DMA4_CCDNi_11" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x558++0x3 line.long 0x0 "DMA4_CCDNi_12,DMA4_CCDNi_12" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x5B8++0x3 line.long 0x0 "DMA4_CCDNi_13,DMA4_CCDNi_13" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x618++0x3 line.long 0x0 "DMA4_CCDNi_14,DMA4_CCDNi_14" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x678++0x3 line.long 0x0 "DMA4_CCDNi_15,DMA4_CCDNi_15" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x6D8++0x3 line.long 0x0 "DMA4_CCDNi_16,DMA4_CCDNi_16" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x738++0x3 line.long 0x0 "DMA4_CCDNi_17,DMA4_CCDNi_17" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x798++0x3 line.long 0x0 "DMA4_CCDNi_18,DMA4_CCDNi_18" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x7F8++0x3 line.long 0x0 "DMA4_CCDNi_19,DMA4_CCDNi_19" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x858++0x3 line.long 0x0 "DMA4_CCDNi_20,DMA4_CCDNi_20" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x8B8++0x3 line.long 0x0 "DMA4_CCDNi_21,DMA4_CCDNi_21" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x918++0x3 line.long 0x0 "DMA4_CCDNi_22,DMA4_CCDNi_22" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x978++0x3 line.long 0x0 "DMA4_CCDNi_23,DMA4_CCDNi_23" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0x9D8++0x3 line.long 0x0 "DMA4_CCDNi_24,DMA4_CCDNi_24" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xA38++0x3 line.long 0x0 "DMA4_CCDNi_25,DMA4_CCDNi_25" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xA98++0x3 line.long 0x0 "DMA4_CCDNi_26,DMA4_CCDNi_26" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xAF8++0x3 line.long 0x0 "DMA4_CCDNi_27,DMA4_CCDNi_27" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xB58++0x3 line.long 0x0 "DMA4_CCDNi_28,DMA4_CCDNi_28" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xBB8++0x3 line.long 0x0 "DMA4_CCDNi_29,DMA4_CCDNi_29" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xC18++0x3 line.long 0x0 "DMA4_CCDNi_30,DMA4_CCDNi_30" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" group.byte 0xC78++0x3 line.long 0x0 "DMA4_CCDNi_31,DMA4_CCDNi_31" hexmask.long.word 0x0 0.--15. 1. " CURRENT_DESCRIPTOR_NBR ,This register when read contains the current active descriptor number in the link list. This register is Read/write to allow user initialization." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Write 0's for future compatibility, Reads return 0" width 0x0B tree.end tree "EVE1_EDMA_TPTC0" base ad:0x42086000 width 24. group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE1_EDMA_TPTC1" base ad:0x42087000 width 24. group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE2_EDMA_TPTC0" base ad:0x42186000 width 24. group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE2_EDMA_TPTC1" base ad:0x42187000 width 24. group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE3_EDMA_TPTC0" base ad:0x42286000 width 24. group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE3_EDMA_TPTC1" base ad:0x42287000 width 24. group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE4_EDMA_TPTC0" base ad:0x42386000 width 24. group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE4_EDMA_TPTC1" base ad:0x42387000 width 24. group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE1_EDMA_TPCC" base ad:0x420A0000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPCC_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x0 0.--2. " NUMDMACH ,Number of DMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--6. " NUMQDMACH ,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 8.--10. " NUMINTCH ,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 12.--14. " NUMPAENTRY ,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 16.--18. " NUMTC ,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 20.--21. " NUMREGN ,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 24. " CHMAPEXIST ,Channel Mapping Existence" "0,1" bitfld.long 0x0 25. " MPEXIST ,Memory Protection Existence" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reads return 0's" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xFC++0x3 line.long 0x0 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x0 0. " CLKGDIS ,Auto Clock Gate Disable" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x114++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x118++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x11C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x138++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x13C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x248++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x254++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x260++0x3 line.long 0x0 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." bitfld.long 0x0 0.--2. " E0 ,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x280++0x3 line.long 0x0 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x0 0.--2. " TCNUMQ0 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " TCNUMQ1 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x0 0.--2. " PRIQ0 ,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " PRIQ1 ,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x300++0x3 line.long 0x0 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed #31" "0,1" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E32 ,Event Missed #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed #63" "0,1" group.byte 0x308++0x3 line.long 0x0 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed Clear #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed Clear #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed Clear #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed Clear #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed Clear #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed Clear #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed Clear #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed Clear #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed Clear #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed Clear #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed Clear #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed Clear #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed Clear #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed Clear #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed Clear #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed Clear #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed Clear #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed Clear #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed Clear #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed Clear #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed Clear #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed Clear #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed Clear #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed Clear #31" "0,1" group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E32 ,Event Missed Clear #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed Clear #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed Clear #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed Clear #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed Clear #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed Clear #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed Clear #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed Clear #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed Clear #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed Clear #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed Clear #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed Clear #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed Clear #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed Clear #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed Clear #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed Clear #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed Clear #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed Clear #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed Clear #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed Clear #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed Clear #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed Clear #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed Clear #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed Clear #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed Clear #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed Clear #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed Clear #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed Clear #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed Clear #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed Clear #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed Clear #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed Clear #63" "0,1" group.byte 0x310++0x3 line.long 0x0 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced. If any bit in the register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x314++0x3 line.long 0x0 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x318++0x3 line.long 0x0 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x0 0. " QTHRXCD0 ,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors were previously clear), then an error will be signaled with TPCC error interrupt. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x31C++0x3 line.long 0x0 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x0 0. " QTHRXCD0 ,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT0.WM, QSTAT0.THRXCD,[0] QTHRXCD0 ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM, QSTAT1.THRXCD,[1] QTHRXCD1 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT2.WM, QSTAT2.THRXCD,[2] QTHRXCD2 ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM, QSTAT3.THRXCD,[3] QTHRXCD3 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT4.WM, QSTAT4.THRXCD,[4] QTHRXCD4 ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT5.WM, QSTAT5.THRXCD,[5]QTHRXCD5 ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT6.WM, QSTAT6.THRXCD,[6]QTHRXCD6 ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT7.WM, QSTAT7.THRXCD,[7] QTHRXCD7 ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR. . Write 0x0 have no affect. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x320++0x3 line.long 0x0 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x0 0. " EVAL ,Error Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the/, , or registers. The CPU must also write 0x1 after any error interrupts are serviced in order for subsequent interrupts to be asserted. ." "0,1" bitfld.long 0x0 1. " SET ,Error Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of/, , or . ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x388++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x38C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x39C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRA,Queue Threshold A, for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q0 ,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q1 ,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q2 ,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q3 ,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x624++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRB,Queue Threshold B, for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q4 ,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q5 ,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q6 ,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q7 ,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x0 0. " EVTACTV ,DMA Event Active" "0,1" bitfld.long 0x0 1. " QEVTACTV ,QDMA Event Active" "0,1" textline " " bitfld.long 0x0 2. " TRACTV ,Transfer Request Active TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0,1" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4. " ACTV ,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals. The ACTV bit must remain high through the life of a:" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,reads return 0's" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " COMPACTV ,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " QUEACTV0 ,Queue 0 Active" "0,1" bitfld.long 0x0 17. " QUEACTV1 ,Queue 1 Active" "0,1" textline " " bitfld.long 0x0 18. " QUEACTV2 ,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0,1" bitfld.long 0x0 19. " QUEACTV3 ,Queue 3 Active" "0,1" textline " " bitfld.long 0x0 20. " QUEACTV4 ,Queue 4 Active" "0,1" bitfld.long 0x0 21. " QUEACTV5 ,Queue 5 Active" "0,1" textline " " bitfld.long 0x0 22. " QUEACTV6 ,Queue 6 Active" "0,1" bitfld.long 0x0 23. " QUEACTV7 ,Queue 7 Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,reads return 0's" group.byte 0x700++0x3 line.long 0x0 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 0.--5. " STRTEVT ,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " TYPE ,AET Event Type" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--13. " ENDINT ,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.tbyte 0x0 14.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " EN ,AET Enable" "0,1" group.byte 0x704++0x3 line.long 0x0 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x0 0. " STAT ,AET Status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x708++0x3 line.long 0x0 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x0 0. " CLR ,AET Clear commandCPU writes 0x0 has no effect. . CPU writes 0x1 to the CLR bit causes the tpcc_aet output signal and[0]STAT register to be cleared. ." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" hexmask.long 0x0 0.--31. 1. " FADDR ,Fault Address: 32-bit read-only status register containing the faulting address when a mMemory protection violation is detected. This register can only be cleared via theEDMA_TPCC_MPFCR." group.byte 0x804++0x3 line.long 0x0 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x0 0. " UXE ,User Execute Error" "0,1" bitfld.long 0x0 1. " UWE ,User Write Error" "0,1" textline " " bitfld.long 0x0 2. " URE ,User Read Error" "0,1" bitfld.long 0x0 3. " SXE ,Supervisor Execute Error" "0,1" textline " " bitfld.long 0x0 4. " SWE ,Supervisor Write Error" "0,1" bitfld.long 0x0 5. " SRE ,Supervisor Read Error" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--12. " FID ,Faulted ID: FID register contains valid info if any of the MP error bits (UXE, UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x808++0x3 line.long 0x0 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x0 0. " MPFCLR ,Fault Clear register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x80C++0x3 line.long 0x0 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0" "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x810++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x814++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x818++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x81C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x820++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x824++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x828++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x82C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x1000++0x3 line.long 0x0 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1004++0x3 line.long 0x0 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1008++0x3 line.long 0x0 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x100C++0x3 line.long 0x0 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1010++0x3 line.long 0x0 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1014++0x3 line.long 0x0 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1018++0x3 line.long 0x0 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x101C++0x3 line.long 0x0 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1020++0x3 line.long 0x0 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1024++0x3 line.long 0x0 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1028++0x3 line.long 0x0 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x102C++0x3 line.long 0x0 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1030++0x3 line.long 0x0 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1034++0x3 line.long 0x0 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1038++0x3 line.long 0x0 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x103C++0x3 line.long 0x0 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1040++0x3 line.long 0x0 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1044++0x3 line.long 0x0 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1050++0x3 line.long 0x0 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1054++0x3 line.long 0x0 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1058++0x3 line.long 0x0 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x105C++0x3 line.long 0x0 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1060++0x3 line.long 0x0 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1064++0x3 line.long 0x0 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1068++0x3 line.long 0x0 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x106C++0x3 line.long 0x0 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. . In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1070++0x3 line.long 0x0 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1074++0x3 line.long 0x0 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" bitfld.long 0x0 1. " SET ,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1080++0x3 line.long 0x0 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1084++0x3 line.long 0x0 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1088++0x3 line.long 0x0 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x108C++0x3 line.long 0x0 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1090++0x3 line.long 0x0 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1094++0x3 line.long 0x0 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2000++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2200++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2400++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2600++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2800++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2004++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2204++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2404++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2604++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2804++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2008++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2208++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2408++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2608++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2808++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x200C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x220C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x240C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x260C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x280C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2010++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2210++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2410++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2610++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2810++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2014++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2214++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2414++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2614++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2814++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2018++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2218++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2418++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2618++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2818++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x201C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x221C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x241C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x261C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x281C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2020++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2220++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2420++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2620++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2820++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2024++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2224++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2424++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2624++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2824++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2028++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2228++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2428++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2628++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2828++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x202C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x222C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x242C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x262C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x282C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2030++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2230++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2430++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2630++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2830++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2034++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2234++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2434++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2634++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2834++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2038++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2238++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2438++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2638++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2838++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x203C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x223C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x243C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x263C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x283C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2040++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2240++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2440++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2640++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2840++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2044++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2244++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2444++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2644++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2844++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2050++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2250++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2450++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2650++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2850++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2054++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2254++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2454++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2654++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2854++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2058++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2258++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2458++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2658++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2858++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x205C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x225C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x245C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x265C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x285C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2060++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2260++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2460++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2660++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2860++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2064++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2264++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2464++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2664++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2864++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2068++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2268++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2468++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2668++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2868++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x206C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x226C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x246C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x266C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x286C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2070++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2270++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2470++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2670++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2870++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2074++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2274++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2474++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2674++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2874++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2278++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2478++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2678++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2878++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2A78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2C78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2E78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2080++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2280++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2480++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2680++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2880++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2084++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2284++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2484++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2684++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2884++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2088++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2288++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2488++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2688++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2888++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x208C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x228C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x248C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x268C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x288C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2090++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2290++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2490++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2690++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2890++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2094++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2294++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2494++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2694++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2894++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2A94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2C94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2E94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x4000++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_0,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4020++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_1,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4040++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_2,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4060++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_3,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4080++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_4,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_5,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_6,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_7,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4100++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_8,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4120++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_9,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4140++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_10,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4160++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_11,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4180++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_12,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_13,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_14,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_15,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4200++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_16,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4220++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_17,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4240++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_18,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4260++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_19,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4280++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_20,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_21,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_22,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_23,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4300++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_24,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4320++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_25,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4340++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_26,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4360++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_27,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4380++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_28,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_29,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_30,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_31,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4400++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_32,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4420++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_33,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4440++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_34,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4460++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_35,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4480++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_36,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_37,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_38,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_39,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4500++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_40,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4520++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_41,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4540++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_42,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4560++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_43,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4580++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_44,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_45,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_46,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_47,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4600++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_48,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4620++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_49,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4640++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_50,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4660++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_51,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4680++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_52,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_53,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_54,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_55,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4700++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_56,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4720++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_57,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4740++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_58,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4760++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_59,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4780++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_60,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_61,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_62,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_63,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4800++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_64,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4820++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_65,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4840++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_66,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4860++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_67,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4880++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_68,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_69,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_70,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_71,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4900++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_72,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4920++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_73,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4940++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_74,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4960++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_75,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4980++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_76,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_77,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_78,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_79,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_80,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_81,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_82,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_83,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_84,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_85,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_86,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_87,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_88,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_89,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_90,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_91,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_92,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_93,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_94,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_95,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_96,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_97,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_98,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_99,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_100,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_101,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_102,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_103,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_104,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_105,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_106,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_107,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_108,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_109,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_110,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_111,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_112,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_113,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_114,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_115,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_116,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_117,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_118,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_119,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_120,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_121,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_122,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_123,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_124,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_125,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_126,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_127,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4004++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_0,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4024++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_1,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4044++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_2,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4064++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_3,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4084++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_4,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_5,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_6,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_7,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4104++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_8,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4124++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_9,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4144++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_10,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4164++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_11,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4184++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_12,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_13,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_14,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_15,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4204++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_16,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4224++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_17,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4244++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_18,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4264++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_19,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4284++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_20,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_21,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_22,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_23,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4304++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_24,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4324++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_25,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4344++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_26,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4364++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_27,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4384++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_28,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_29,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_30,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_31,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4404++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_32,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4424++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_33,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4444++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_34,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4464++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_35,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4484++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_36,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_37,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_38,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_39,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4504++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_40,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4524++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_41,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4544++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_42,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4564++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_43,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4584++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_44,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_45,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_46,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_47,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4604++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_48,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4624++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_49,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4644++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_50,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4664++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_51,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4684++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_52,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_53,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_54,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_55,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4704++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_56,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4724++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_57,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4744++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_58,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4764++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_59,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4784++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_60,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_61,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_62,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_63,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4804++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_64,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4824++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_65,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4844++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_66,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4864++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_67,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4884++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_68,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_69,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_70,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_71,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4904++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_72,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4924++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_73,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4944++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_74,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4964++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_75,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4984++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_76,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_77,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_78,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_79,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_80,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_81,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_82,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_83,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_84,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_85,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_86,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_87,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_88,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_89,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_90,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_91,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_92,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_93,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_94,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_95,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_96,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_97,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_98,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_99,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_100,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_101,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_102,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_103,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_104,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_105,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_106,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_107,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_108,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_109,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_110,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_111,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_112,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_113,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_114,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_115,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_116,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_117,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_118,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_119,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_120,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_121,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_122,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_123,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_124,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_125,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_126,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_127,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4008++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4028++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4048++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4068++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4088++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4108++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4128++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4148++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4168++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4188++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4208++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4228++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4248++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4268++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4288++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4308++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4328++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4348++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4368++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4388++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4408++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4428++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4448++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4468++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4488++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4508++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4528++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4548++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4568++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4588++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4608++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4628++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4648++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4668++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4688++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4708++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4728++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4748++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4768++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4788++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4808++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4828++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4848++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4868++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4888++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4908++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4928++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4948++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4968++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4988++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x400C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_0,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x402C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_1,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x404C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_2,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x406C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_3,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x408C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_4,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_5,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_6,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_7,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x410C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_8,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x412C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_9,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x414C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_10,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x416C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_11,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x418C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_12,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_13,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_14,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_15,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x420C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_16,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x422C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_17,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x424C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_18,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x426C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_19,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x428C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_20,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_21,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_22,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_23,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x430C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_24,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x432C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_25,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x434C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_26,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x436C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_27,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x438C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_28,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_29,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_30,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_31,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x440C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_32,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x442C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_33,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x444C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_34,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x446C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_35,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x448C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_36,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_37,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_38,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_39,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x450C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_40,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x452C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_41,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x454C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_42,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x456C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_43,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x458C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_44,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_45,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_46,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_47,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x460C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_48,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x462C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_49,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x464C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_50,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x466C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_51,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x468C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_52,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_53,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_54,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_55,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x470C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_56,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x472C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_57,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x474C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_58,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x476C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_59,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x478C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_60,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_61,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_62,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_63,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x480C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_64,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x482C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_65,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x484C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_66,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x486C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_67,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x488C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_68,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_69,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_70,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_71,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x490C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_72,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x492C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_73,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x494C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_74,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x496C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_75,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x498C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_76,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_77,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_78,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_79,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_80,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_81,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_82,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_83,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_84,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_85,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ACC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_86,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_87,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_88,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_89,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_90,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_91,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_92,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_93,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_94,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_95,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_96,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_97,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_98,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_99,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_100,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_101,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_102,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_103,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_104,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_105,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_106,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_107,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_108,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_109,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_110,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_111,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_112,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_113,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_114,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_115,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_116,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_117,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ECC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_118,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_119,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_120,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_121,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_122,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_123,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_124,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_125,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_126,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_127,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4010++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_0,EDMA_TPCC_BIDX_n_0" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4030++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_1,EDMA_TPCC_BIDX_n_1" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4050++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_2,EDMA_TPCC_BIDX_n_2" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4070++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_3,EDMA_TPCC_BIDX_n_3" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4090++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_4,EDMA_TPCC_BIDX_n_4" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_5,EDMA_TPCC_BIDX_n_5" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_6,EDMA_TPCC_BIDX_n_6" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_7,EDMA_TPCC_BIDX_n_7" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4110++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_8,EDMA_TPCC_BIDX_n_8" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4130++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_9,EDMA_TPCC_BIDX_n_9" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4150++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_10,EDMA_TPCC_BIDX_n_10" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4170++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_11,EDMA_TPCC_BIDX_n_11" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4190++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_12,EDMA_TPCC_BIDX_n_12" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_13,EDMA_TPCC_BIDX_n_13" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_14,EDMA_TPCC_BIDX_n_14" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_15,EDMA_TPCC_BIDX_n_15" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4210++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_16,EDMA_TPCC_BIDX_n_16" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4230++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_17,EDMA_TPCC_BIDX_n_17" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4250++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_18,EDMA_TPCC_BIDX_n_18" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4270++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_19,EDMA_TPCC_BIDX_n_19" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4290++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_20,EDMA_TPCC_BIDX_n_20" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_21,EDMA_TPCC_BIDX_n_21" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_22,EDMA_TPCC_BIDX_n_22" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_23,EDMA_TPCC_BIDX_n_23" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4310++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_24,EDMA_TPCC_BIDX_n_24" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4330++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_25,EDMA_TPCC_BIDX_n_25" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4350++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_26,EDMA_TPCC_BIDX_n_26" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4370++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_27,EDMA_TPCC_BIDX_n_27" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4390++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_28,EDMA_TPCC_BIDX_n_28" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_29,EDMA_TPCC_BIDX_n_29" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_30,EDMA_TPCC_BIDX_n_30" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_31,EDMA_TPCC_BIDX_n_31" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4410++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_32,EDMA_TPCC_BIDX_n_32" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4430++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_33,EDMA_TPCC_BIDX_n_33" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4450++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_34,EDMA_TPCC_BIDX_n_34" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4470++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_35,EDMA_TPCC_BIDX_n_35" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4490++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_36,EDMA_TPCC_BIDX_n_36" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_37,EDMA_TPCC_BIDX_n_37" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_38,EDMA_TPCC_BIDX_n_38" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_39,EDMA_TPCC_BIDX_n_39" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4510++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_40,EDMA_TPCC_BIDX_n_40" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4530++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_41,EDMA_TPCC_BIDX_n_41" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4550++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_42,EDMA_TPCC_BIDX_n_42" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4570++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_43,EDMA_TPCC_BIDX_n_43" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4590++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_44,EDMA_TPCC_BIDX_n_44" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_45,EDMA_TPCC_BIDX_n_45" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_46,EDMA_TPCC_BIDX_n_46" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_47,EDMA_TPCC_BIDX_n_47" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4610++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_48,EDMA_TPCC_BIDX_n_48" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4630++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_49,EDMA_TPCC_BIDX_n_49" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4650++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_50,EDMA_TPCC_BIDX_n_50" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4670++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_51,EDMA_TPCC_BIDX_n_51" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4690++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_52,EDMA_TPCC_BIDX_n_52" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_53,EDMA_TPCC_BIDX_n_53" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_54,EDMA_TPCC_BIDX_n_54" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_55,EDMA_TPCC_BIDX_n_55" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4710++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_56,EDMA_TPCC_BIDX_n_56" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4730++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_57,EDMA_TPCC_BIDX_n_57" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4750++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_58,EDMA_TPCC_BIDX_n_58" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4770++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_59,EDMA_TPCC_BIDX_n_59" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4790++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_60,EDMA_TPCC_BIDX_n_60" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_61,EDMA_TPCC_BIDX_n_61" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_62,EDMA_TPCC_BIDX_n_62" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_63,EDMA_TPCC_BIDX_n_63" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4810++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_64,EDMA_TPCC_BIDX_n_64" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4830++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_65,EDMA_TPCC_BIDX_n_65" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4850++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_66,EDMA_TPCC_BIDX_n_66" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4870++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_67,EDMA_TPCC_BIDX_n_67" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4890++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_68,EDMA_TPCC_BIDX_n_68" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_69,EDMA_TPCC_BIDX_n_69" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_70,EDMA_TPCC_BIDX_n_70" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_71,EDMA_TPCC_BIDX_n_71" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4910++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_72,EDMA_TPCC_BIDX_n_72" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4930++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_73,EDMA_TPCC_BIDX_n_73" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4950++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_74,EDMA_TPCC_BIDX_n_74" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4970++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_75,EDMA_TPCC_BIDX_n_75" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4990++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_76,EDMA_TPCC_BIDX_n_76" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_77,EDMA_TPCC_BIDX_n_77" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_78,EDMA_TPCC_BIDX_n_78" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_79,EDMA_TPCC_BIDX_n_79" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_80,EDMA_TPCC_BIDX_n_80" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_81,EDMA_TPCC_BIDX_n_81" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_82,EDMA_TPCC_BIDX_n_82" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_83,EDMA_TPCC_BIDX_n_83" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_84,EDMA_TPCC_BIDX_n_84" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_85,EDMA_TPCC_BIDX_n_85" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_86,EDMA_TPCC_BIDX_n_86" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_87,EDMA_TPCC_BIDX_n_87" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_88,EDMA_TPCC_BIDX_n_88" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_89,EDMA_TPCC_BIDX_n_89" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_90,EDMA_TPCC_BIDX_n_90" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_91,EDMA_TPCC_BIDX_n_91" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_92,EDMA_TPCC_BIDX_n_92" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_93,EDMA_TPCC_BIDX_n_93" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_94,EDMA_TPCC_BIDX_n_94" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_95,EDMA_TPCC_BIDX_n_95" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_96,EDMA_TPCC_BIDX_n_96" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_97,EDMA_TPCC_BIDX_n_97" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_98,EDMA_TPCC_BIDX_n_98" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_99,EDMA_TPCC_BIDX_n_99" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_100,EDMA_TPCC_BIDX_n_100" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_101,EDMA_TPCC_BIDX_n_101" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_102,EDMA_TPCC_BIDX_n_102" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_103,EDMA_TPCC_BIDX_n_103" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_104,EDMA_TPCC_BIDX_n_104" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_105,EDMA_TPCC_BIDX_n_105" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_106,EDMA_TPCC_BIDX_n_106" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_107,EDMA_TPCC_BIDX_n_107" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_108,EDMA_TPCC_BIDX_n_108" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_109,EDMA_TPCC_BIDX_n_109" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_110,EDMA_TPCC_BIDX_n_110" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_111,EDMA_TPCC_BIDX_n_111" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_112,EDMA_TPCC_BIDX_n_112" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_113,EDMA_TPCC_BIDX_n_113" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_114,EDMA_TPCC_BIDX_n_114" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_115,EDMA_TPCC_BIDX_n_115" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_116,EDMA_TPCC_BIDX_n_116" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_117,EDMA_TPCC_BIDX_n_117" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4ED0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_118,EDMA_TPCC_BIDX_n_118" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_119,EDMA_TPCC_BIDX_n_119" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_120,EDMA_TPCC_BIDX_n_120" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_121,EDMA_TPCC_BIDX_n_121" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_122,EDMA_TPCC_BIDX_n_122" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_123,EDMA_TPCC_BIDX_n_123" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_124,EDMA_TPCC_BIDX_n_124" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_125,EDMA_TPCC_BIDX_n_125" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_126,EDMA_TPCC_BIDX_n_126" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_127,EDMA_TPCC_BIDX_n_127" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4014++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4034++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4054++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4074++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4094++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4114++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4134++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4154++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4174++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4194++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4214++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4234++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4254++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4274++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4294++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4314++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4334++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4354++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4374++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4394++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4414++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4434++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4454++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4474++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4494++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4514++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4534++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4554++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4574++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4594++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4614++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4634++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4654++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4674++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4694++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4714++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4734++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4754++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4774++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4794++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4814++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4834++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4854++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4874++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4894++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4914++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4934++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4954++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4974++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4994++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4ED4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4018++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4038++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4058++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4078++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4098++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4118++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4138++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4158++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4178++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4198++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4218++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4238++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4258++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4278++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4298++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4318++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4338++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4358++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4378++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4398++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4418++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4438++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4458++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4478++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4498++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4518++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4538++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4558++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4578++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4598++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4618++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4638++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4658++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4678++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4698++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4718++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4738++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4758++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4778++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4798++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4818++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4838++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4858++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4878++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4898++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4918++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4938++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4958++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4978++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4998++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4ED8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x401C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x403C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x405C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x407C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x409C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x411C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x413C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x415C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x417C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x419C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x421C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x423C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x425C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x427C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x429C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x431C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x433C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x435C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x437C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x439C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x441C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x443C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x445C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x447C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x449C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x451C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x453C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x455C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x457C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x459C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x461C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x463C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x465C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x467C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x469C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x471C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x473C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x475C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x477C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x479C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x481C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x483C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x485C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x487C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x489C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x491C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x493C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x495C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x497C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x499C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ABC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ADC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4AFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE2_EDMA_TPCC" base ad:0x421A0000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPCC_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x0 0.--2. " NUMDMACH ,Number of DMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--6. " NUMQDMACH ,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 8.--10. " NUMINTCH ,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 12.--14. " NUMPAENTRY ,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 16.--18. " NUMTC ,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 20.--21. " NUMREGN ,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 24. " CHMAPEXIST ,Channel Mapping Existence" "0,1" bitfld.long 0x0 25. " MPEXIST ,Memory Protection Existence" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reads return 0's" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xFC++0x3 line.long 0x0 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x0 0. " CLKGDIS ,Auto Clock Gate Disable" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x114++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x118++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x11C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x138++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x13C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x248++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x254++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x260++0x3 line.long 0x0 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." bitfld.long 0x0 0.--2. " E0 ,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x280++0x3 line.long 0x0 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x0 0.--2. " TCNUMQ0 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " TCNUMQ1 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x0 0.--2. " PRIQ0 ,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " PRIQ1 ,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x300++0x3 line.long 0x0 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed #31" "0,1" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E32 ,Event Missed #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed #63" "0,1" group.byte 0x308++0x3 line.long 0x0 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed Clear #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed Clear #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed Clear #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed Clear #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed Clear #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed Clear #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed Clear #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed Clear #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed Clear #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed Clear #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed Clear #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed Clear #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed Clear #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed Clear #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed Clear #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed Clear #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed Clear #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed Clear #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed Clear #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed Clear #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed Clear #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed Clear #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed Clear #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed Clear #31" "0,1" group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E32 ,Event Missed Clear #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed Clear #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed Clear #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed Clear #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed Clear #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed Clear #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed Clear #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed Clear #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed Clear #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed Clear #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed Clear #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed Clear #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed Clear #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed Clear #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed Clear #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed Clear #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed Clear #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed Clear #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed Clear #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed Clear #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed Clear #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed Clear #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed Clear #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed Clear #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed Clear #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed Clear #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed Clear #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed Clear #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed Clear #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed Clear #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed Clear #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed Clear #63" "0,1" group.byte 0x310++0x3 line.long 0x0 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced. If any bit in the register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x314++0x3 line.long 0x0 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x318++0x3 line.long 0x0 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x0 0. " QTHRXCD0 ,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors were previously clear), then an error will be signaled with TPCC error interrupt. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x31C++0x3 line.long 0x0 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x0 0. " QTHRXCD0 ,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT0.WM, QSTAT0.THRXCD,[0] QTHRXCD0 ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM, QSTAT1.THRXCD,[1] QTHRXCD1 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT2.WM, QSTAT2.THRXCD,[2] QTHRXCD2 ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM, QSTAT3.THRXCD,[3] QTHRXCD3 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT4.WM, QSTAT4.THRXCD,[4] QTHRXCD4 ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT5.WM, QSTAT5.THRXCD,[5]QTHRXCD5 ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT6.WM, QSTAT6.THRXCD,[6]QTHRXCD6 ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT7.WM, QSTAT7.THRXCD,[7] QTHRXCD7 ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR. . Write 0x0 have no affect. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x320++0x3 line.long 0x0 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x0 0. " EVAL ,Error Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the/, , or registers. The CPU must also write 0x1 after any error interrupts are serviced in order for subsequent interrupts to be asserted. ." "0,1" bitfld.long 0x0 1. " SET ,Error Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of/, , or . ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x388++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x38C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x39C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRA,Queue Threshold A, for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q0 ,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q1 ,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q2 ,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q3 ,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x624++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRB,Queue Threshold B, for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q4 ,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q5 ,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q6 ,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q7 ,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x0 0. " EVTACTV ,DMA Event Active" "0,1" bitfld.long 0x0 1. " QEVTACTV ,QDMA Event Active" "0,1" textline " " bitfld.long 0x0 2. " TRACTV ,Transfer Request Active TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0,1" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4. " ACTV ,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals. The ACTV bit must remain high through the life of a:" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,reads return 0's" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " COMPACTV ,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " QUEACTV0 ,Queue 0 Active" "0,1" bitfld.long 0x0 17. " QUEACTV1 ,Queue 1 Active" "0,1" textline " " bitfld.long 0x0 18. " QUEACTV2 ,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0,1" bitfld.long 0x0 19. " QUEACTV3 ,Queue 3 Active" "0,1" textline " " bitfld.long 0x0 20. " QUEACTV4 ,Queue 4 Active" "0,1" bitfld.long 0x0 21. " QUEACTV5 ,Queue 5 Active" "0,1" textline " " bitfld.long 0x0 22. " QUEACTV6 ,Queue 6 Active" "0,1" bitfld.long 0x0 23. " QUEACTV7 ,Queue 7 Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,reads return 0's" group.byte 0x700++0x3 line.long 0x0 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 0.--5. " STRTEVT ,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " TYPE ,AET Event Type" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--13. " ENDINT ,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.tbyte 0x0 14.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " EN ,AET Enable" "0,1" group.byte 0x704++0x3 line.long 0x0 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x0 0. " STAT ,AET Status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x708++0x3 line.long 0x0 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x0 0. " CLR ,AET Clear commandCPU writes 0x0 has no effect. . CPU writes 0x1 to the CLR bit causes the tpcc_aet output signal and[0]STAT register to be cleared. ." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" hexmask.long 0x0 0.--31. 1. " FADDR ,Fault Address: 32-bit read-only status register containing the faulting address when a mMemory protection violation is detected. This register can only be cleared via theEDMA_TPCC_MPFCR." group.byte 0x804++0x3 line.long 0x0 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x0 0. " UXE ,User Execute Error" "0,1" bitfld.long 0x0 1. " UWE ,User Write Error" "0,1" textline " " bitfld.long 0x0 2. " URE ,User Read Error" "0,1" bitfld.long 0x0 3. " SXE ,Supervisor Execute Error" "0,1" textline " " bitfld.long 0x0 4. " SWE ,Supervisor Write Error" "0,1" bitfld.long 0x0 5. " SRE ,Supervisor Read Error" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--12. " FID ,Faulted ID: FID register contains valid info if any of the MP error bits (UXE, UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x808++0x3 line.long 0x0 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x0 0. " MPFCLR ,Fault Clear register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x80C++0x3 line.long 0x0 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0" "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x810++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x814++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x818++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x81C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x820++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x824++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x828++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x82C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x1000++0x3 line.long 0x0 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1004++0x3 line.long 0x0 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1008++0x3 line.long 0x0 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x100C++0x3 line.long 0x0 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1010++0x3 line.long 0x0 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1014++0x3 line.long 0x0 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1018++0x3 line.long 0x0 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x101C++0x3 line.long 0x0 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1020++0x3 line.long 0x0 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1024++0x3 line.long 0x0 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1028++0x3 line.long 0x0 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x102C++0x3 line.long 0x0 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1030++0x3 line.long 0x0 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1034++0x3 line.long 0x0 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1038++0x3 line.long 0x0 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x103C++0x3 line.long 0x0 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1040++0x3 line.long 0x0 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1044++0x3 line.long 0x0 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1050++0x3 line.long 0x0 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1054++0x3 line.long 0x0 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1058++0x3 line.long 0x0 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x105C++0x3 line.long 0x0 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1060++0x3 line.long 0x0 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1064++0x3 line.long 0x0 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1068++0x3 line.long 0x0 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x106C++0x3 line.long 0x0 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. . In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1070++0x3 line.long 0x0 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1074++0x3 line.long 0x0 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" bitfld.long 0x0 1. " SET ,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1080++0x3 line.long 0x0 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1084++0x3 line.long 0x0 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1088++0x3 line.long 0x0 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x108C++0x3 line.long 0x0 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1090++0x3 line.long 0x0 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1094++0x3 line.long 0x0 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2000++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2200++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2400++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2600++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2800++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2004++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2204++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2404++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2604++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2804++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2008++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2208++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2408++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2608++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2808++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x200C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x220C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x240C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x260C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x280C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2010++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2210++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2410++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2610++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2810++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2014++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2214++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2414++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2614++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2814++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2018++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2218++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2418++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2618++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2818++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x201C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x221C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x241C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x261C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x281C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2020++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2220++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2420++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2620++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2820++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2024++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2224++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2424++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2624++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2824++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2028++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2228++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2428++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2628++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2828++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x202C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x222C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x242C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x262C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x282C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2030++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2230++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2430++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2630++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2830++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2034++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2234++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2434++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2634++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2834++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2038++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2238++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2438++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2638++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2838++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x203C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x223C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x243C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x263C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x283C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2040++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2240++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2440++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2640++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2840++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2044++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2244++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2444++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2644++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2844++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2050++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2250++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2450++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2650++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2850++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2054++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2254++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2454++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2654++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2854++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2058++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2258++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2458++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2658++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2858++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x205C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x225C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x245C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x265C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x285C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2060++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2260++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2460++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2660++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2860++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2064++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2264++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2464++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2664++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2864++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2068++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2268++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2468++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2668++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2868++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x206C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x226C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x246C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x266C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x286C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2070++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2270++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2470++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2670++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2870++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2074++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2274++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2474++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2674++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2874++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2278++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2478++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2678++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2878++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2A78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2C78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2E78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2080++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2280++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2480++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2680++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2880++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2084++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2284++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2484++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2684++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2884++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2088++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2288++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2488++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2688++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2888++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x208C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x228C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x248C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x268C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x288C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2090++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2290++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2490++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2690++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2890++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2094++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2294++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2494++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2694++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2894++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2A94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2C94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2E94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x4000++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_0,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4020++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_1,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4040++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_2,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4060++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_3,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4080++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_4,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_5,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_6,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_7,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4100++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_8,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4120++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_9,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4140++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_10,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4160++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_11,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4180++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_12,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_13,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_14,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_15,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4200++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_16,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4220++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_17,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4240++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_18,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4260++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_19,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4280++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_20,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_21,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_22,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_23,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4300++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_24,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4320++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_25,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4340++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_26,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4360++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_27,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4380++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_28,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_29,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_30,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_31,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4400++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_32,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4420++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_33,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4440++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_34,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4460++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_35,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4480++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_36,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_37,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_38,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_39,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4500++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_40,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4520++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_41,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4540++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_42,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4560++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_43,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4580++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_44,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_45,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_46,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_47,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4600++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_48,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4620++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_49,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4640++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_50,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4660++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_51,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4680++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_52,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_53,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_54,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_55,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4700++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_56,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4720++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_57,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4740++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_58,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4760++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_59,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4780++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_60,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_61,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_62,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_63,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4800++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_64,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4820++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_65,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4840++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_66,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4860++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_67,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4880++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_68,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_69,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_70,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_71,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4900++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_72,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4920++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_73,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4940++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_74,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4960++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_75,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4980++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_76,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_77,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_78,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_79,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_80,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_81,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_82,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_83,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_84,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_85,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_86,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_87,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_88,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_89,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_90,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_91,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_92,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_93,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_94,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_95,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_96,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_97,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_98,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_99,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_100,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_101,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_102,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_103,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_104,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_105,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_106,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_107,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_108,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_109,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_110,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_111,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_112,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_113,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_114,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_115,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_116,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_117,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_118,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_119,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_120,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_121,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_122,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_123,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_124,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_125,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_126,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_127,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4004++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_0,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4024++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_1,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4044++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_2,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4064++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_3,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4084++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_4,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_5,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_6,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_7,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4104++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_8,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4124++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_9,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4144++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_10,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4164++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_11,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4184++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_12,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_13,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_14,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_15,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4204++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_16,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4224++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_17,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4244++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_18,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4264++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_19,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4284++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_20,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_21,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_22,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_23,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4304++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_24,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4324++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_25,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4344++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_26,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4364++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_27,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4384++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_28,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_29,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_30,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_31,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4404++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_32,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4424++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_33,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4444++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_34,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4464++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_35,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4484++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_36,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_37,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_38,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_39,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4504++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_40,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4524++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_41,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4544++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_42,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4564++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_43,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4584++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_44,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_45,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_46,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_47,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4604++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_48,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4624++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_49,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4644++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_50,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4664++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_51,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4684++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_52,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_53,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_54,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_55,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4704++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_56,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4724++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_57,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4744++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_58,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4764++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_59,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4784++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_60,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_61,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_62,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_63,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4804++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_64,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4824++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_65,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4844++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_66,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4864++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_67,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4884++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_68,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_69,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_70,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_71,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4904++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_72,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4924++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_73,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4944++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_74,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4964++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_75,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4984++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_76,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_77,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_78,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_79,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_80,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_81,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_82,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_83,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_84,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_85,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_86,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_87,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_88,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_89,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_90,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_91,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_92,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_93,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_94,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_95,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_96,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_97,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_98,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_99,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_100,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_101,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_102,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_103,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_104,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_105,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_106,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_107,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_108,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_109,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_110,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_111,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_112,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_113,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_114,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_115,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_116,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_117,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_118,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_119,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_120,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_121,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_122,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_123,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_124,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_125,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_126,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_127,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4008++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4028++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4048++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4068++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4088++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4108++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4128++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4148++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4168++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4188++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4208++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4228++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4248++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4268++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4288++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4308++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4328++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4348++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4368++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4388++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4408++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4428++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4448++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4468++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4488++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4508++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4528++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4548++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4568++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4588++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4608++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4628++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4648++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4668++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4688++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4708++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4728++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4748++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4768++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4788++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4808++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4828++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4848++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4868++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4888++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4908++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4928++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4948++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4968++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4988++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x400C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_0,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x402C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_1,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x404C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_2,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x406C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_3,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x408C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_4,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_5,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_6,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_7,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x410C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_8,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x412C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_9,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x414C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_10,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x416C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_11,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x418C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_12,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_13,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_14,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_15,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x420C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_16,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x422C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_17,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x424C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_18,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x426C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_19,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x428C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_20,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_21,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_22,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_23,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x430C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_24,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x432C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_25,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x434C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_26,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x436C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_27,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x438C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_28,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_29,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_30,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_31,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x440C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_32,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x442C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_33,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x444C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_34,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x446C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_35,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x448C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_36,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_37,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_38,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_39,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x450C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_40,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x452C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_41,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x454C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_42,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x456C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_43,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x458C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_44,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_45,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_46,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_47,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x460C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_48,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x462C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_49,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x464C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_50,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x466C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_51,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x468C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_52,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_53,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_54,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_55,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x470C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_56,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x472C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_57,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x474C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_58,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x476C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_59,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x478C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_60,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_61,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_62,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_63,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x480C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_64,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x482C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_65,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x484C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_66,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x486C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_67,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x488C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_68,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_69,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_70,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_71,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x490C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_72,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x492C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_73,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x494C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_74,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x496C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_75,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x498C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_76,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_77,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_78,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_79,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_80,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_81,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_82,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_83,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_84,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_85,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ACC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_86,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_87,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_88,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_89,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_90,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_91,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_92,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_93,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_94,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_95,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_96,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_97,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_98,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_99,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_100,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_101,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_102,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_103,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_104,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_105,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_106,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_107,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_108,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_109,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_110,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_111,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_112,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_113,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_114,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_115,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_116,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_117,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ECC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_118,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_119,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_120,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_121,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_122,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_123,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_124,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_125,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_126,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_127,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4010++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_0,EDMA_TPCC_BIDX_n_0" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4030++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_1,EDMA_TPCC_BIDX_n_1" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4050++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_2,EDMA_TPCC_BIDX_n_2" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4070++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_3,EDMA_TPCC_BIDX_n_3" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4090++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_4,EDMA_TPCC_BIDX_n_4" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_5,EDMA_TPCC_BIDX_n_5" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_6,EDMA_TPCC_BIDX_n_6" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_7,EDMA_TPCC_BIDX_n_7" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4110++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_8,EDMA_TPCC_BIDX_n_8" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4130++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_9,EDMA_TPCC_BIDX_n_9" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4150++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_10,EDMA_TPCC_BIDX_n_10" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4170++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_11,EDMA_TPCC_BIDX_n_11" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4190++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_12,EDMA_TPCC_BIDX_n_12" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_13,EDMA_TPCC_BIDX_n_13" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_14,EDMA_TPCC_BIDX_n_14" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_15,EDMA_TPCC_BIDX_n_15" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4210++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_16,EDMA_TPCC_BIDX_n_16" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4230++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_17,EDMA_TPCC_BIDX_n_17" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4250++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_18,EDMA_TPCC_BIDX_n_18" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4270++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_19,EDMA_TPCC_BIDX_n_19" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4290++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_20,EDMA_TPCC_BIDX_n_20" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_21,EDMA_TPCC_BIDX_n_21" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_22,EDMA_TPCC_BIDX_n_22" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_23,EDMA_TPCC_BIDX_n_23" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4310++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_24,EDMA_TPCC_BIDX_n_24" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4330++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_25,EDMA_TPCC_BIDX_n_25" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4350++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_26,EDMA_TPCC_BIDX_n_26" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4370++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_27,EDMA_TPCC_BIDX_n_27" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4390++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_28,EDMA_TPCC_BIDX_n_28" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_29,EDMA_TPCC_BIDX_n_29" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_30,EDMA_TPCC_BIDX_n_30" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_31,EDMA_TPCC_BIDX_n_31" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4410++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_32,EDMA_TPCC_BIDX_n_32" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4430++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_33,EDMA_TPCC_BIDX_n_33" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4450++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_34,EDMA_TPCC_BIDX_n_34" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4470++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_35,EDMA_TPCC_BIDX_n_35" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4490++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_36,EDMA_TPCC_BIDX_n_36" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_37,EDMA_TPCC_BIDX_n_37" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_38,EDMA_TPCC_BIDX_n_38" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_39,EDMA_TPCC_BIDX_n_39" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4510++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_40,EDMA_TPCC_BIDX_n_40" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4530++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_41,EDMA_TPCC_BIDX_n_41" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4550++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_42,EDMA_TPCC_BIDX_n_42" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4570++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_43,EDMA_TPCC_BIDX_n_43" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4590++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_44,EDMA_TPCC_BIDX_n_44" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_45,EDMA_TPCC_BIDX_n_45" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_46,EDMA_TPCC_BIDX_n_46" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_47,EDMA_TPCC_BIDX_n_47" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4610++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_48,EDMA_TPCC_BIDX_n_48" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4630++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_49,EDMA_TPCC_BIDX_n_49" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4650++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_50,EDMA_TPCC_BIDX_n_50" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4670++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_51,EDMA_TPCC_BIDX_n_51" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4690++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_52,EDMA_TPCC_BIDX_n_52" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_53,EDMA_TPCC_BIDX_n_53" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_54,EDMA_TPCC_BIDX_n_54" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_55,EDMA_TPCC_BIDX_n_55" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4710++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_56,EDMA_TPCC_BIDX_n_56" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4730++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_57,EDMA_TPCC_BIDX_n_57" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4750++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_58,EDMA_TPCC_BIDX_n_58" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4770++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_59,EDMA_TPCC_BIDX_n_59" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4790++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_60,EDMA_TPCC_BIDX_n_60" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_61,EDMA_TPCC_BIDX_n_61" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_62,EDMA_TPCC_BIDX_n_62" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_63,EDMA_TPCC_BIDX_n_63" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4810++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_64,EDMA_TPCC_BIDX_n_64" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4830++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_65,EDMA_TPCC_BIDX_n_65" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4850++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_66,EDMA_TPCC_BIDX_n_66" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4870++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_67,EDMA_TPCC_BIDX_n_67" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4890++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_68,EDMA_TPCC_BIDX_n_68" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_69,EDMA_TPCC_BIDX_n_69" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_70,EDMA_TPCC_BIDX_n_70" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_71,EDMA_TPCC_BIDX_n_71" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4910++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_72,EDMA_TPCC_BIDX_n_72" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4930++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_73,EDMA_TPCC_BIDX_n_73" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4950++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_74,EDMA_TPCC_BIDX_n_74" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4970++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_75,EDMA_TPCC_BIDX_n_75" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4990++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_76,EDMA_TPCC_BIDX_n_76" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_77,EDMA_TPCC_BIDX_n_77" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_78,EDMA_TPCC_BIDX_n_78" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_79,EDMA_TPCC_BIDX_n_79" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_80,EDMA_TPCC_BIDX_n_80" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_81,EDMA_TPCC_BIDX_n_81" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_82,EDMA_TPCC_BIDX_n_82" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_83,EDMA_TPCC_BIDX_n_83" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_84,EDMA_TPCC_BIDX_n_84" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_85,EDMA_TPCC_BIDX_n_85" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_86,EDMA_TPCC_BIDX_n_86" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_87,EDMA_TPCC_BIDX_n_87" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_88,EDMA_TPCC_BIDX_n_88" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_89,EDMA_TPCC_BIDX_n_89" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_90,EDMA_TPCC_BIDX_n_90" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_91,EDMA_TPCC_BIDX_n_91" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_92,EDMA_TPCC_BIDX_n_92" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_93,EDMA_TPCC_BIDX_n_93" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_94,EDMA_TPCC_BIDX_n_94" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_95,EDMA_TPCC_BIDX_n_95" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_96,EDMA_TPCC_BIDX_n_96" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_97,EDMA_TPCC_BIDX_n_97" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_98,EDMA_TPCC_BIDX_n_98" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_99,EDMA_TPCC_BIDX_n_99" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_100,EDMA_TPCC_BIDX_n_100" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_101,EDMA_TPCC_BIDX_n_101" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_102,EDMA_TPCC_BIDX_n_102" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_103,EDMA_TPCC_BIDX_n_103" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_104,EDMA_TPCC_BIDX_n_104" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_105,EDMA_TPCC_BIDX_n_105" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_106,EDMA_TPCC_BIDX_n_106" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_107,EDMA_TPCC_BIDX_n_107" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_108,EDMA_TPCC_BIDX_n_108" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_109,EDMA_TPCC_BIDX_n_109" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_110,EDMA_TPCC_BIDX_n_110" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_111,EDMA_TPCC_BIDX_n_111" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_112,EDMA_TPCC_BIDX_n_112" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_113,EDMA_TPCC_BIDX_n_113" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_114,EDMA_TPCC_BIDX_n_114" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_115,EDMA_TPCC_BIDX_n_115" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_116,EDMA_TPCC_BIDX_n_116" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_117,EDMA_TPCC_BIDX_n_117" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4ED0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_118,EDMA_TPCC_BIDX_n_118" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_119,EDMA_TPCC_BIDX_n_119" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_120,EDMA_TPCC_BIDX_n_120" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_121,EDMA_TPCC_BIDX_n_121" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_122,EDMA_TPCC_BIDX_n_122" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_123,EDMA_TPCC_BIDX_n_123" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_124,EDMA_TPCC_BIDX_n_124" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_125,EDMA_TPCC_BIDX_n_125" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_126,EDMA_TPCC_BIDX_n_126" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_127,EDMA_TPCC_BIDX_n_127" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4014++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4034++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4054++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4074++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4094++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4114++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4134++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4154++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4174++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4194++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4214++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4234++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4254++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4274++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4294++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4314++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4334++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4354++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4374++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4394++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4414++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4434++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4454++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4474++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4494++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4514++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4534++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4554++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4574++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4594++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4614++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4634++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4654++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4674++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4694++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4714++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4734++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4754++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4774++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4794++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4814++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4834++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4854++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4874++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4894++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4914++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4934++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4954++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4974++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4994++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4ED4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4018++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4038++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4058++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4078++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4098++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4118++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4138++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4158++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4178++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4198++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4218++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4238++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4258++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4278++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4298++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4318++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4338++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4358++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4378++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4398++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4418++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4438++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4458++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4478++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4498++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4518++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4538++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4558++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4578++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4598++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4618++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4638++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4658++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4678++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4698++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4718++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4738++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4758++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4778++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4798++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4818++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4838++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4858++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4878++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4898++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4918++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4938++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4958++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4978++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4998++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4ED8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x401C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x403C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x405C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x407C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x409C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x411C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x413C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x415C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x417C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x419C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x421C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x423C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x425C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x427C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x429C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x431C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x433C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x435C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x437C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x439C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x441C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x443C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x445C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x447C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x449C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x451C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x453C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x455C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x457C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x459C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x461C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x463C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x465C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x467C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x469C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x471C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x473C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x475C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x477C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x479C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x481C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x483C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x485C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x487C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x489C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x491C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x493C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x495C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x497C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x499C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ABC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ADC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4AFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP_EDMA_TPCC" base ad:0x1D10000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPCC_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x0 0.--2. " NUMDMACH ,Number of DMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--6. " NUMQDMACH ,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 8.--10. " NUMINTCH ,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 12.--14. " NUMPAENTRY ,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 16.--18. " NUMTC ,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 20.--21. " NUMREGN ,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 24. " CHMAPEXIST ,Channel Mapping Existence" "0,1" bitfld.long 0x0 25. " MPEXIST ,Memory Protection Existence" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reads return 0's" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xFC++0x3 line.long 0x0 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x0 0. " CLKGDIS ,Auto Clock Gate Disable" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x114++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x118++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x11C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x138++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x13C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x144++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x148++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x14C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x150++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x154++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x158++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x15C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x160++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x164++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x168++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x16C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x170++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x174++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x178++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x17C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x180++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x194++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x198++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x19C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1AC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1BC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1CC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1DC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1EC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x248++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x254++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x260++0x3 line.long 0x0 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." bitfld.long 0x0 0.--2. " E0 ,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x280++0x3 line.long 0x0 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x0 0.--2. " TCNUMQ0 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " TCNUMQ1 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x0 0.--2. " PRIQ0 ,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " PRIQ1 ,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x300++0x3 line.long 0x0 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed #31" "0,1" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E32 ,Event Missed #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed #63" "0,1" group.byte 0x308++0x3 line.long 0x0 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed Clear #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed Clear #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed Clear #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed Clear #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed Clear #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed Clear #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed Clear #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed Clear #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed Clear #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed Clear #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed Clear #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed Clear #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed Clear #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed Clear #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed Clear #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed Clear #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed Clear #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed Clear #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed Clear #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed Clear #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed Clear #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed Clear #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed Clear #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed Clear #31" "0,1" group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E32 ,Event Missed Clear #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed Clear #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed Clear #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed Clear #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed Clear #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed Clear #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed Clear #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed Clear #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed Clear #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed Clear #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed Clear #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed Clear #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed Clear #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed Clear #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed Clear #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed Clear #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed Clear #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed Clear #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed Clear #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed Clear #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed Clear #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed Clear #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed Clear #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed Clear #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed Clear #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed Clear #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed Clear #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed Clear #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed Clear #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed Clear #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed Clear #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed Clear #63" "0,1" group.byte 0x310++0x3 line.long 0x0 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced. If any bit in the register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x314++0x3 line.long 0x0 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x318++0x3 line.long 0x0 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x0 0. " QTHRXCD0 ,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors were previously clear), then an error will be signaled with TPCC error interrupt. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x31C++0x3 line.long 0x0 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x0 0. " QTHRXCD0 ,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT0.WM, QSTAT0.THRXCD,[0] QTHRXCD0 ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM, QSTAT1.THRXCD,[1] QTHRXCD1 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT2.WM, QSTAT2.THRXCD,[2] QTHRXCD2 ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM, QSTAT3.THRXCD,[3] QTHRXCD3 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT4.WM, QSTAT4.THRXCD,[4] QTHRXCD4 ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT5.WM, QSTAT5.THRXCD,[5]QTHRXCD5 ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT6.WM, QSTAT6.THRXCD,[6]QTHRXCD6 ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT7.WM, QSTAT7.THRXCD,[7] QTHRXCD7 ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR. . Write 0x0 have no affect. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x320++0x3 line.long 0x0 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x0 0. " EVAL ,Error Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the/, , or registers. The CPU must also write 0x1 after any error interrupts are serviced in order for subsequent interrupts to be asserted. ." "0,1" bitfld.long 0x0 1. " SET ,Error Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of/, , or . ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x348++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x350++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x358++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x360++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x368++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x370++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x378++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x344++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x35C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x364++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x36C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x374++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x37C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x380++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x388++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x38C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x39C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x400++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x404++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x408++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x40C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x410++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x414++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x418++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x41C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x420++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x424++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x428++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x42C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x430++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x434++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x438++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x43C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x440++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x444++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x448++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x44C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x450++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x454++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x458++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x45C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x460++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x464++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x468++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x46C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x470++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x474++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x478++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x47C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRA,Queue Threshold A, for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q0 ,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q1 ,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q2 ,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q3 ,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x624++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRB,Queue Threshold B, for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q4 ,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q5 ,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q6 ,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q7 ,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x0 0. " EVTACTV ,DMA Event Active" "0,1" bitfld.long 0x0 1. " QEVTACTV ,QDMA Event Active" "0,1" textline " " bitfld.long 0x0 2. " TRACTV ,Transfer Request Active TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0,1" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4. " ACTV ,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals. The ACTV bit must remain high through the life of a:" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,reads return 0's" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " COMPACTV ,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " QUEACTV0 ,Queue 0 Active" "0,1" bitfld.long 0x0 17. " QUEACTV1 ,Queue 1 Active" "0,1" textline " " bitfld.long 0x0 18. " QUEACTV2 ,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0,1" bitfld.long 0x0 19. " QUEACTV3 ,Queue 3 Active" "0,1" textline " " bitfld.long 0x0 20. " QUEACTV4 ,Queue 4 Active" "0,1" bitfld.long 0x0 21. " QUEACTV5 ,Queue 5 Active" "0,1" textline " " bitfld.long 0x0 22. " QUEACTV6 ,Queue 6 Active" "0,1" bitfld.long 0x0 23. " QUEACTV7 ,Queue 7 Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,reads return 0's" group.byte 0x700++0x3 line.long 0x0 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 0.--5. " STRTEVT ,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " TYPE ,AET Event Type" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--13. " ENDINT ,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.tbyte 0x0 14.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " EN ,AET Enable" "0,1" group.byte 0x704++0x3 line.long 0x0 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x0 0. " STAT ,AET Status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x708++0x3 line.long 0x0 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x0 0. " CLR ,AET Clear commandCPU writes 0x0 has no effect. . CPU writes 0x1 to the CLR bit causes the tpcc_aet output signal and[0]STAT register to be cleared. ." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" hexmask.long 0x0 0.--31. 1. " FADDR ,Fault Address: 32-bit read-only status register containing the faulting address when a mMemory protection violation is detected. This register can only be cleared via theEDMA_TPCC_MPFCR." group.byte 0x804++0x3 line.long 0x0 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x0 0. " UXE ,User Execute Error" "0,1" bitfld.long 0x0 1. " UWE ,User Write Error" "0,1" textline " " bitfld.long 0x0 2. " URE ,User Read Error" "0,1" bitfld.long 0x0 3. " SXE ,Supervisor Execute Error" "0,1" textline " " bitfld.long 0x0 4. " SWE ,Supervisor Write Error" "0,1" bitfld.long 0x0 5. " SRE ,Supervisor Read Error" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--12. " FID ,Faulted ID: FID register contains valid info if any of the MP error bits (UXE, UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x808++0x3 line.long 0x0 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x0 0. " MPFCLR ,Fault Clear register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x80C++0x3 line.long 0x0 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0" "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x810++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x814++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x818++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x81C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x820++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x824++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x828++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x82C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x1000++0x3 line.long 0x0 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1004++0x3 line.long 0x0 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1008++0x3 line.long 0x0 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x100C++0x3 line.long 0x0 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1010++0x3 line.long 0x0 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1014++0x3 line.long 0x0 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1018++0x3 line.long 0x0 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x101C++0x3 line.long 0x0 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1020++0x3 line.long 0x0 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1024++0x3 line.long 0x0 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1028++0x3 line.long 0x0 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x102C++0x3 line.long 0x0 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1030++0x3 line.long 0x0 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1034++0x3 line.long 0x0 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1038++0x3 line.long 0x0 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x103C++0x3 line.long 0x0 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1040++0x3 line.long 0x0 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1044++0x3 line.long 0x0 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1050++0x3 line.long 0x0 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1054++0x3 line.long 0x0 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1058++0x3 line.long 0x0 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x105C++0x3 line.long 0x0 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1060++0x3 line.long 0x0 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1064++0x3 line.long 0x0 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1068++0x3 line.long 0x0 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x106C++0x3 line.long 0x0 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. . In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1070++0x3 line.long 0x0 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1074++0x3 line.long 0x0 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" bitfld.long 0x0 1. " SET ,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1080++0x3 line.long 0x0 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1084++0x3 line.long 0x0 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1088++0x3 line.long 0x0 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x108C++0x3 line.long 0x0 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1090++0x3 line.long 0x0 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1094++0x3 line.long 0x0 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2000++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2200++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2400++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2600++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2800++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2004++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2204++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2404++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2604++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2804++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2008++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2208++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2408++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2608++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2808++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x200C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x220C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x240C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x260C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x280C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2010++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2210++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2410++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2610++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2810++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2014++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2214++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2414++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2614++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2814++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2018++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2218++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2418++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2618++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2818++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x201C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x221C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x241C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x261C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x281C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2020++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2220++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2420++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2620++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2820++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2024++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2224++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2424++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2624++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2824++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2028++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2228++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2428++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2628++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2828++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x202C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x222C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x242C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x262C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x282C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2030++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2230++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2430++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2630++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2830++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2034++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2234++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2434++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2634++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2834++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2038++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2238++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2438++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2638++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2838++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x203C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x223C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x243C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x263C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x283C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2040++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2240++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2440++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2640++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2840++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2044++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2244++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2444++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2644++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2844++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2050++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2250++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2450++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2650++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2850++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2054++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2254++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2454++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2654++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2854++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2058++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2258++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2458++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2658++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2858++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x205C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x225C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x245C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x265C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x285C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2060++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2260++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2460++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2660++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2860++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2064++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2264++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2464++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2664++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2864++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2068++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2268++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2468++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2668++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2868++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x206C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x226C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x246C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x266C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x286C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2070++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2270++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2470++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2670++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2870++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2074++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2274++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2474++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2674++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2874++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2278++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2478++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2678++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2878++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2A78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2C78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2E78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2080++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2280++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2480++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2680++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2880++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2084++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2284++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2484++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2684++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2884++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2088++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2288++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2488++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2688++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2888++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x208C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x228C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x248C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x268C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x288C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2090++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2290++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2490++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2690++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2890++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2094++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2294++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2494++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2694++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2894++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2A94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2C94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2E94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x4000++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_0,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4020++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_1,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4040++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_2,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4060++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_3,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4080++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_4,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_5,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_6,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_7,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4100++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_8,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4120++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_9,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4140++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_10,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4160++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_11,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4180++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_12,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_13,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_14,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_15,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4200++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_16,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4220++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_17,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4240++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_18,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4260++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_19,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4280++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_20,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_21,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_22,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_23,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4300++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_24,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4320++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_25,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4340++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_26,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4360++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_27,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4380++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_28,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_29,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_30,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_31,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4400++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_32,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4420++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_33,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4440++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_34,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4460++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_35,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4480++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_36,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_37,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_38,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_39,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4500++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_40,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4520++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_41,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4540++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_42,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4560++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_43,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4580++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_44,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_45,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_46,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_47,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4600++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_48,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4620++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_49,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4640++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_50,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4660++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_51,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4680++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_52,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_53,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_54,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_55,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4700++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_56,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4720++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_57,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4740++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_58,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4760++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_59,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4780++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_60,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_61,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_62,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_63,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4800++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_64,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4820++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_65,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4840++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_66,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4860++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_67,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4880++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_68,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_69,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_70,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_71,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4900++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_72,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4920++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_73,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4940++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_74,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4960++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_75,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4980++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_76,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_77,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_78,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_79,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_80,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_81,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_82,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_83,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_84,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_85,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_86,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_87,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_88,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_89,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_90,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_91,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_92,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_93,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_94,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_95,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_96,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_97,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_98,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_99,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_100,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_101,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_102,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_103,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_104,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_105,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_106,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_107,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_108,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_109,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_110,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_111,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_112,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_113,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_114,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_115,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_116,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_117,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_118,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_119,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_120,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_121,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_122,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_123,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_124,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_125,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_126,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_127,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4004++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_0,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4024++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_1,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4044++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_2,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4064++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_3,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4084++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_4,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_5,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_6,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_7,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4104++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_8,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4124++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_9,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4144++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_10,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4164++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_11,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4184++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_12,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_13,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_14,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_15,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4204++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_16,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4224++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_17,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4244++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_18,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4264++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_19,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4284++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_20,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_21,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_22,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_23,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4304++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_24,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4324++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_25,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4344++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_26,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4364++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_27,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4384++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_28,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_29,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_30,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_31,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4404++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_32,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4424++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_33,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4444++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_34,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4464++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_35,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4484++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_36,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_37,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_38,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_39,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4504++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_40,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4524++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_41,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4544++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_42,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4564++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_43,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4584++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_44,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_45,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_46,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_47,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4604++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_48,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4624++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_49,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4644++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_50,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4664++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_51,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4684++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_52,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_53,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_54,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_55,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4704++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_56,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4724++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_57,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4744++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_58,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4764++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_59,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4784++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_60,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_61,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_62,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_63,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4804++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_64,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4824++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_65,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4844++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_66,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4864++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_67,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4884++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_68,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_69,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_70,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_71,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4904++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_72,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4924++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_73,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4944++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_74,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4964++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_75,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4984++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_76,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_77,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_78,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_79,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_80,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_81,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_82,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_83,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_84,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_85,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_86,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_87,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_88,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_89,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_90,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_91,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_92,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_93,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_94,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_95,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_96,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_97,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_98,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_99,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_100,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_101,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_102,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_103,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_104,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_105,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_106,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_107,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_108,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_109,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_110,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_111,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_112,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_113,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_114,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_115,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_116,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_117,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_118,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_119,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_120,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_121,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_122,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_123,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_124,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_125,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_126,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_127,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4008++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4028++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4048++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4068++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4088++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4108++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4128++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4148++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4168++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4188++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4208++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4228++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4248++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4268++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4288++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4308++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4328++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4348++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4368++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4388++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4408++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4428++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4448++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4468++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4488++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4508++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4528++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4548++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4568++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4588++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4608++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4628++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4648++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4668++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4688++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4708++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4728++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4748++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4768++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4788++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4808++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4828++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4848++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4868++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4888++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4908++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4928++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4948++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4968++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4988++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x400C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_0,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x402C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_1,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x404C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_2,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x406C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_3,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x408C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_4,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_5,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_6,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_7,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x410C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_8,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x412C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_9,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x414C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_10,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x416C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_11,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x418C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_12,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_13,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_14,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_15,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x420C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_16,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x422C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_17,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x424C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_18,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x426C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_19,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x428C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_20,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_21,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_22,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_23,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x430C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_24,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x432C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_25,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x434C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_26,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x436C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_27,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x438C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_28,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_29,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_30,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_31,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x440C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_32,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x442C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_33,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x444C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_34,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x446C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_35,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x448C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_36,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_37,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_38,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_39,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x450C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_40,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x452C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_41,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x454C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_42,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x456C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_43,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x458C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_44,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_45,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_46,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_47,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x460C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_48,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x462C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_49,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x464C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_50,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x466C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_51,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x468C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_52,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_53,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_54,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_55,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x470C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_56,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x472C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_57,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x474C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_58,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x476C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_59,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x478C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_60,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_61,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_62,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_63,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x480C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_64,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x482C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_65,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x484C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_66,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x486C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_67,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x488C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_68,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_69,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_70,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_71,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x490C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_72,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x492C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_73,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x494C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_74,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x496C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_75,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x498C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_76,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_77,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_78,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_79,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_80,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_81,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_82,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_83,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_84,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_85,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ACC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_86,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_87,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_88,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_89,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_90,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_91,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_92,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_93,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_94,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_95,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_96,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_97,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_98,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_99,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_100,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_101,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_102,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_103,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_104,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_105,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_106,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_107,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_108,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_109,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_110,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_111,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_112,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_113,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_114,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_115,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_116,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_117,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ECC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_118,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_119,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_120,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_121,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_122,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_123,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_124,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_125,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_126,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_127,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4010++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_0,EDMA_TPCC_BIDX_n_0" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4030++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_1,EDMA_TPCC_BIDX_n_1" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4050++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_2,EDMA_TPCC_BIDX_n_2" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4070++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_3,EDMA_TPCC_BIDX_n_3" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4090++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_4,EDMA_TPCC_BIDX_n_4" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_5,EDMA_TPCC_BIDX_n_5" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_6,EDMA_TPCC_BIDX_n_6" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_7,EDMA_TPCC_BIDX_n_7" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4110++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_8,EDMA_TPCC_BIDX_n_8" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4130++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_9,EDMA_TPCC_BIDX_n_9" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4150++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_10,EDMA_TPCC_BIDX_n_10" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4170++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_11,EDMA_TPCC_BIDX_n_11" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4190++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_12,EDMA_TPCC_BIDX_n_12" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_13,EDMA_TPCC_BIDX_n_13" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_14,EDMA_TPCC_BIDX_n_14" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_15,EDMA_TPCC_BIDX_n_15" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4210++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_16,EDMA_TPCC_BIDX_n_16" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4230++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_17,EDMA_TPCC_BIDX_n_17" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4250++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_18,EDMA_TPCC_BIDX_n_18" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4270++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_19,EDMA_TPCC_BIDX_n_19" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4290++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_20,EDMA_TPCC_BIDX_n_20" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_21,EDMA_TPCC_BIDX_n_21" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_22,EDMA_TPCC_BIDX_n_22" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_23,EDMA_TPCC_BIDX_n_23" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4310++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_24,EDMA_TPCC_BIDX_n_24" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4330++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_25,EDMA_TPCC_BIDX_n_25" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4350++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_26,EDMA_TPCC_BIDX_n_26" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4370++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_27,EDMA_TPCC_BIDX_n_27" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4390++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_28,EDMA_TPCC_BIDX_n_28" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_29,EDMA_TPCC_BIDX_n_29" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_30,EDMA_TPCC_BIDX_n_30" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_31,EDMA_TPCC_BIDX_n_31" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4410++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_32,EDMA_TPCC_BIDX_n_32" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4430++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_33,EDMA_TPCC_BIDX_n_33" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4450++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_34,EDMA_TPCC_BIDX_n_34" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4470++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_35,EDMA_TPCC_BIDX_n_35" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4490++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_36,EDMA_TPCC_BIDX_n_36" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_37,EDMA_TPCC_BIDX_n_37" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_38,EDMA_TPCC_BIDX_n_38" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_39,EDMA_TPCC_BIDX_n_39" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4510++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_40,EDMA_TPCC_BIDX_n_40" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4530++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_41,EDMA_TPCC_BIDX_n_41" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4550++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_42,EDMA_TPCC_BIDX_n_42" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4570++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_43,EDMA_TPCC_BIDX_n_43" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4590++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_44,EDMA_TPCC_BIDX_n_44" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_45,EDMA_TPCC_BIDX_n_45" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_46,EDMA_TPCC_BIDX_n_46" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_47,EDMA_TPCC_BIDX_n_47" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4610++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_48,EDMA_TPCC_BIDX_n_48" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4630++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_49,EDMA_TPCC_BIDX_n_49" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4650++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_50,EDMA_TPCC_BIDX_n_50" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4670++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_51,EDMA_TPCC_BIDX_n_51" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4690++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_52,EDMA_TPCC_BIDX_n_52" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_53,EDMA_TPCC_BIDX_n_53" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_54,EDMA_TPCC_BIDX_n_54" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_55,EDMA_TPCC_BIDX_n_55" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4710++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_56,EDMA_TPCC_BIDX_n_56" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4730++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_57,EDMA_TPCC_BIDX_n_57" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4750++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_58,EDMA_TPCC_BIDX_n_58" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4770++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_59,EDMA_TPCC_BIDX_n_59" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4790++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_60,EDMA_TPCC_BIDX_n_60" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_61,EDMA_TPCC_BIDX_n_61" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_62,EDMA_TPCC_BIDX_n_62" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_63,EDMA_TPCC_BIDX_n_63" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4810++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_64,EDMA_TPCC_BIDX_n_64" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4830++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_65,EDMA_TPCC_BIDX_n_65" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4850++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_66,EDMA_TPCC_BIDX_n_66" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4870++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_67,EDMA_TPCC_BIDX_n_67" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4890++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_68,EDMA_TPCC_BIDX_n_68" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_69,EDMA_TPCC_BIDX_n_69" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_70,EDMA_TPCC_BIDX_n_70" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_71,EDMA_TPCC_BIDX_n_71" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4910++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_72,EDMA_TPCC_BIDX_n_72" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4930++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_73,EDMA_TPCC_BIDX_n_73" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4950++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_74,EDMA_TPCC_BIDX_n_74" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4970++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_75,EDMA_TPCC_BIDX_n_75" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4990++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_76,EDMA_TPCC_BIDX_n_76" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_77,EDMA_TPCC_BIDX_n_77" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_78,EDMA_TPCC_BIDX_n_78" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_79,EDMA_TPCC_BIDX_n_79" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_80,EDMA_TPCC_BIDX_n_80" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_81,EDMA_TPCC_BIDX_n_81" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_82,EDMA_TPCC_BIDX_n_82" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_83,EDMA_TPCC_BIDX_n_83" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_84,EDMA_TPCC_BIDX_n_84" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_85,EDMA_TPCC_BIDX_n_85" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_86,EDMA_TPCC_BIDX_n_86" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_87,EDMA_TPCC_BIDX_n_87" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_88,EDMA_TPCC_BIDX_n_88" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_89,EDMA_TPCC_BIDX_n_89" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_90,EDMA_TPCC_BIDX_n_90" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_91,EDMA_TPCC_BIDX_n_91" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_92,EDMA_TPCC_BIDX_n_92" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_93,EDMA_TPCC_BIDX_n_93" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_94,EDMA_TPCC_BIDX_n_94" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_95,EDMA_TPCC_BIDX_n_95" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_96,EDMA_TPCC_BIDX_n_96" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_97,EDMA_TPCC_BIDX_n_97" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_98,EDMA_TPCC_BIDX_n_98" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_99,EDMA_TPCC_BIDX_n_99" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_100,EDMA_TPCC_BIDX_n_100" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_101,EDMA_TPCC_BIDX_n_101" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_102,EDMA_TPCC_BIDX_n_102" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_103,EDMA_TPCC_BIDX_n_103" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_104,EDMA_TPCC_BIDX_n_104" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_105,EDMA_TPCC_BIDX_n_105" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_106,EDMA_TPCC_BIDX_n_106" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_107,EDMA_TPCC_BIDX_n_107" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_108,EDMA_TPCC_BIDX_n_108" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_109,EDMA_TPCC_BIDX_n_109" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_110,EDMA_TPCC_BIDX_n_110" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_111,EDMA_TPCC_BIDX_n_111" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_112,EDMA_TPCC_BIDX_n_112" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_113,EDMA_TPCC_BIDX_n_113" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_114,EDMA_TPCC_BIDX_n_114" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_115,EDMA_TPCC_BIDX_n_115" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_116,EDMA_TPCC_BIDX_n_116" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_117,EDMA_TPCC_BIDX_n_117" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4ED0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_118,EDMA_TPCC_BIDX_n_118" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_119,EDMA_TPCC_BIDX_n_119" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_120,EDMA_TPCC_BIDX_n_120" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_121,EDMA_TPCC_BIDX_n_121" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_122,EDMA_TPCC_BIDX_n_122" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_123,EDMA_TPCC_BIDX_n_123" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_124,EDMA_TPCC_BIDX_n_124" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_125,EDMA_TPCC_BIDX_n_125" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_126,EDMA_TPCC_BIDX_n_126" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_127,EDMA_TPCC_BIDX_n_127" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4014++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4034++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4054++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4074++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4094++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4114++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4134++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4154++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4174++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4194++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4214++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4234++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4254++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4274++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4294++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4314++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4334++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4354++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4374++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4394++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4414++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4434++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4454++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4474++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4494++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4514++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4534++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4554++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4574++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4594++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4614++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4634++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4654++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4674++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4694++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4714++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4734++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4754++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4774++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4794++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4814++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4834++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4854++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4874++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4894++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4914++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4934++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4954++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4974++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4994++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4ED4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4018++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4038++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4058++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4078++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4098++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4118++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4138++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4158++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4178++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4198++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4218++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4238++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4258++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4278++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4298++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4318++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4338++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4358++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4378++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4398++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4418++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4438++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4458++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4478++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4498++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4518++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4538++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4558++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4578++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4598++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4618++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4638++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4658++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4678++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4698++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4718++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4738++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4758++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4778++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4798++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4818++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4838++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4858++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4878++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4898++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4918++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4938++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4958++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4978++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4998++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4ED8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x401C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x403C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x405C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x407C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x409C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x411C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x413C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x415C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x417C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x419C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x421C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x423C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x425C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x427C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x429C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x431C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x433C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x435C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x437C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x439C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x441C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x443C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x445C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x447C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x449C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x451C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x453C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x455C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x457C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x459C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x461C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x463C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x465C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x467C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x469C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x471C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x473C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x475C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x477C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x479C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x481C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x483C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x485C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x487C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x489C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x491C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x493C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x495C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x497C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x499C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ABC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ADC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4AFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_EDMA_TPCC" base ad:0x41510000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPCC_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x0 0.--2. " NUMDMACH ,Number of DMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--6. " NUMQDMACH ,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 8.--10. " NUMINTCH ,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 12.--14. " NUMPAENTRY ,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 16.--18. " NUMTC ,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 20.--21. " NUMREGN ,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 24. " CHMAPEXIST ,Channel Mapping Existence" "0,1" bitfld.long 0x0 25. " MPEXIST ,Memory Protection Existence" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reads return 0's" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xFC++0x3 line.long 0x0 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x0 0. " CLKGDIS ,Auto Clock Gate Disable" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x114++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x118++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x11C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x138++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x13C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x144++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x148++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x14C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x150++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x154++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x158++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x15C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x160++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x164++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x168++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x16C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x170++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x174++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x178++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x17C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x180++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x194++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x198++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x19C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1AC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1BC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1CC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1DC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1EC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x248++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x254++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x260++0x3 line.long 0x0 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." bitfld.long 0x0 0.--2. " E0 ,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x280++0x3 line.long 0x0 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x0 0.--2. " TCNUMQ0 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " TCNUMQ1 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x0 0.--2. " PRIQ0 ,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " PRIQ1 ,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x300++0x3 line.long 0x0 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed #31" "0,1" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E32 ,Event Missed #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed #63" "0,1" group.byte 0x308++0x3 line.long 0x0 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed Clear #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed Clear #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed Clear #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed Clear #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed Clear #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed Clear #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed Clear #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed Clear #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed Clear #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed Clear #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed Clear #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed Clear #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed Clear #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed Clear #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed Clear #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed Clear #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed Clear #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed Clear #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed Clear #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed Clear #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed Clear #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed Clear #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed Clear #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed Clear #31" "0,1" group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E32 ,Event Missed Clear #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed Clear #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed Clear #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed Clear #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed Clear #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed Clear #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed Clear #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed Clear #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed Clear #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed Clear #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed Clear #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed Clear #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed Clear #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed Clear #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed Clear #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed Clear #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed Clear #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed Clear #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed Clear #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed Clear #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed Clear #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed Clear #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed Clear #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed Clear #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed Clear #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed Clear #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed Clear #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed Clear #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed Clear #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed Clear #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed Clear #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed Clear #63" "0,1" group.byte 0x310++0x3 line.long 0x0 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced. If any bit in the register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x314++0x3 line.long 0x0 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x318++0x3 line.long 0x0 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x0 0. " QTHRXCD0 ,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors were previously clear), then an error will be signaled with TPCC error interrupt. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x31C++0x3 line.long 0x0 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x0 0. " QTHRXCD0 ,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT0.WM, QSTAT0.THRXCD,[0] QTHRXCD0 ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM, QSTAT1.THRXCD,[1] QTHRXCD1 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT2.WM, QSTAT2.THRXCD,[2] QTHRXCD2 ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM, QSTAT3.THRXCD,[3] QTHRXCD3 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT4.WM, QSTAT4.THRXCD,[4] QTHRXCD4 ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT5.WM, QSTAT5.THRXCD,[5]QTHRXCD5 ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT6.WM, QSTAT6.THRXCD,[6]QTHRXCD6 ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT7.WM, QSTAT7.THRXCD,[7] QTHRXCD7 ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR. . Write 0x0 have no affect. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x320++0x3 line.long 0x0 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x0 0. " EVAL ,Error Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the/, , or registers. The CPU must also write 0x1 after any error interrupts are serviced in order for subsequent interrupts to be asserted. ." "0,1" bitfld.long 0x0 1. " SET ,Error Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of/, , or . ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x348++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x350++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x358++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x360++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x368++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x370++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x378++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x344++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x35C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x364++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x36C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x374++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x37C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x380++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x388++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x38C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x39C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x400++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x404++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x408++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x40C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x410++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x414++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x418++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x41C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x420++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x424++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x428++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x42C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x430++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x434++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x438++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x43C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x440++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x444++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x448++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x44C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x450++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x454++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x458++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x45C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x460++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x464++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x468++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x46C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x470++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x474++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x478++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x47C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRA,Queue Threshold A, for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q0 ,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q1 ,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q2 ,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q3 ,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x624++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRB,Queue Threshold B, for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q4 ,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q5 ,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q6 ,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q7 ,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x0 0. " EVTACTV ,DMA Event Active" "0,1" bitfld.long 0x0 1. " QEVTACTV ,QDMA Event Active" "0,1" textline " " bitfld.long 0x0 2. " TRACTV ,Transfer Request Active TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0,1" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4. " ACTV ,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals. The ACTV bit must remain high through the life of a:" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,reads return 0's" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " COMPACTV ,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " QUEACTV0 ,Queue 0 Active" "0,1" bitfld.long 0x0 17. " QUEACTV1 ,Queue 1 Active" "0,1" textline " " bitfld.long 0x0 18. " QUEACTV2 ,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0,1" bitfld.long 0x0 19. " QUEACTV3 ,Queue 3 Active" "0,1" textline " " bitfld.long 0x0 20. " QUEACTV4 ,Queue 4 Active" "0,1" bitfld.long 0x0 21. " QUEACTV5 ,Queue 5 Active" "0,1" textline " " bitfld.long 0x0 22. " QUEACTV6 ,Queue 6 Active" "0,1" bitfld.long 0x0 23. " QUEACTV7 ,Queue 7 Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,reads return 0's" group.byte 0x700++0x3 line.long 0x0 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 0.--5. " STRTEVT ,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " TYPE ,AET Event Type" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--13. " ENDINT ,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.tbyte 0x0 14.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " EN ,AET Enable" "0,1" group.byte 0x704++0x3 line.long 0x0 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x0 0. " STAT ,AET Status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x708++0x3 line.long 0x0 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x0 0. " CLR ,AET Clear commandCPU writes 0x0 has no effect. . CPU writes 0x1 to the CLR bit causes the tpcc_aet output signal and[0]STAT register to be cleared. ." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" hexmask.long 0x0 0.--31. 1. " FADDR ,Fault Address: 32-bit read-only status register containing the faulting address when a mMemory protection violation is detected. This register can only be cleared via theEDMA_TPCC_MPFCR." group.byte 0x804++0x3 line.long 0x0 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x0 0. " UXE ,User Execute Error" "0,1" bitfld.long 0x0 1. " UWE ,User Write Error" "0,1" textline " " bitfld.long 0x0 2. " URE ,User Read Error" "0,1" bitfld.long 0x0 3. " SXE ,Supervisor Execute Error" "0,1" textline " " bitfld.long 0x0 4. " SWE ,Supervisor Write Error" "0,1" bitfld.long 0x0 5. " SRE ,Supervisor Read Error" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--12. " FID ,Faulted ID: FID register contains valid info if any of the MP error bits (UXE, UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x808++0x3 line.long 0x0 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x0 0. " MPFCLR ,Fault Clear register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x80C++0x3 line.long 0x0 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0" "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x810++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x814++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x818++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x81C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x820++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x824++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x828++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x82C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x1000++0x3 line.long 0x0 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1004++0x3 line.long 0x0 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1008++0x3 line.long 0x0 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x100C++0x3 line.long 0x0 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1010++0x3 line.long 0x0 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1014++0x3 line.long 0x0 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1018++0x3 line.long 0x0 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x101C++0x3 line.long 0x0 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1020++0x3 line.long 0x0 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1024++0x3 line.long 0x0 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1028++0x3 line.long 0x0 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x102C++0x3 line.long 0x0 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1030++0x3 line.long 0x0 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1034++0x3 line.long 0x0 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1038++0x3 line.long 0x0 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x103C++0x3 line.long 0x0 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1040++0x3 line.long 0x0 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1044++0x3 line.long 0x0 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1050++0x3 line.long 0x0 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1054++0x3 line.long 0x0 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1058++0x3 line.long 0x0 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x105C++0x3 line.long 0x0 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1060++0x3 line.long 0x0 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1064++0x3 line.long 0x0 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1068++0x3 line.long 0x0 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x106C++0x3 line.long 0x0 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. . In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1070++0x3 line.long 0x0 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1074++0x3 line.long 0x0 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" bitfld.long 0x0 1. " SET ,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1080++0x3 line.long 0x0 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1084++0x3 line.long 0x0 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1088++0x3 line.long 0x0 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x108C++0x3 line.long 0x0 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1090++0x3 line.long 0x0 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1094++0x3 line.long 0x0 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2000++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2200++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2400++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2600++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2800++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2004++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2204++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2404++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2604++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2804++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2008++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2208++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2408++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2608++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2808++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x200C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x220C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x240C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x260C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x280C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2010++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2210++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2410++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2610++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2810++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2014++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2214++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2414++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2614++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2814++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2018++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2218++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2418++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2618++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2818++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x201C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x221C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x241C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x261C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x281C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2020++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2220++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2420++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2620++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2820++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2024++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2224++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2424++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2624++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2824++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2028++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2228++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2428++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2628++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2828++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x202C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x222C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x242C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x262C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x282C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2030++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2230++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2430++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2630++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2830++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2034++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2234++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2434++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2634++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2834++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2038++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2238++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2438++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2638++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2838++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x203C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x223C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x243C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x263C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x283C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2040++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2240++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2440++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2640++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2840++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2044++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2244++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2444++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2644++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2844++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2050++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2250++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2450++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2650++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2850++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2054++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2254++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2454++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2654++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2854++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2058++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2258++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2458++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2658++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2858++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x205C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x225C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x245C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x265C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x285C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2060++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2260++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2460++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2660++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2860++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2064++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2264++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2464++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2664++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2864++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2068++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2268++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2468++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2668++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2868++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x206C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x226C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x246C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x266C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x286C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2070++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2270++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2470++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2670++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2870++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2074++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2274++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2474++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2674++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2874++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2278++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2478++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2678++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2878++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2A78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2C78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2E78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2080++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2280++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2480++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2680++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2880++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2084++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2284++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2484++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2684++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2884++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2088++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2288++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2488++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2688++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2888++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x208C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x228C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x248C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x268C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x288C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2090++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2290++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2490++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2690++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2890++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2094++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2294++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2494++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2694++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2894++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2A94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2C94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2E94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x4000++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_0,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4020++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_1,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4040++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_2,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4060++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_3,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4080++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_4,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_5,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_6,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_7,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4100++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_8,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4120++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_9,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4140++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_10,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4160++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_11,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4180++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_12,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_13,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_14,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_15,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4200++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_16,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4220++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_17,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4240++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_18,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4260++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_19,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4280++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_20,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_21,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_22,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_23,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4300++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_24,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4320++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_25,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4340++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_26,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4360++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_27,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4380++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_28,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_29,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_30,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_31,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4400++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_32,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4420++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_33,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4440++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_34,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4460++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_35,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4480++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_36,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_37,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_38,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_39,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4500++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_40,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4520++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_41,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4540++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_42,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4560++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_43,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4580++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_44,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_45,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_46,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_47,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4600++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_48,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4620++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_49,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4640++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_50,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4660++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_51,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4680++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_52,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_53,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_54,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_55,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4700++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_56,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4720++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_57,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4740++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_58,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4760++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_59,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4780++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_60,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_61,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_62,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_63,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4800++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_64,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4820++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_65,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4840++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_66,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4860++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_67,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4880++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_68,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_69,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_70,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_71,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4900++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_72,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4920++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_73,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4940++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_74,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4960++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_75,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4980++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_76,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_77,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_78,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_79,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_80,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_81,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_82,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_83,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_84,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_85,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_86,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_87,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_88,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_89,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_90,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_91,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_92,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_93,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_94,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_95,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_96,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_97,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_98,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_99,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_100,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_101,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_102,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_103,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_104,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_105,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_106,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_107,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_108,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_109,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_110,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_111,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_112,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_113,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_114,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_115,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_116,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_117,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_118,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_119,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_120,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_121,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_122,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_123,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_124,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_125,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_126,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_127,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4004++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_0,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4024++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_1,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4044++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_2,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4064++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_3,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4084++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_4,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_5,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_6,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_7,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4104++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_8,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4124++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_9,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4144++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_10,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4164++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_11,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4184++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_12,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_13,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_14,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_15,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4204++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_16,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4224++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_17,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4244++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_18,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4264++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_19,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4284++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_20,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_21,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_22,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_23,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4304++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_24,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4324++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_25,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4344++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_26,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4364++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_27,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4384++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_28,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_29,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_30,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_31,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4404++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_32,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4424++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_33,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4444++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_34,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4464++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_35,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4484++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_36,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_37,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_38,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_39,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4504++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_40,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4524++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_41,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4544++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_42,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4564++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_43,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4584++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_44,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_45,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_46,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_47,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4604++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_48,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4624++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_49,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4644++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_50,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4664++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_51,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4684++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_52,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_53,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_54,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_55,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4704++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_56,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4724++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_57,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4744++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_58,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4764++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_59,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4784++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_60,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_61,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_62,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_63,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4804++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_64,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4824++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_65,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4844++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_66,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4864++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_67,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4884++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_68,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_69,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_70,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_71,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4904++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_72,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4924++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_73,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4944++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_74,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4964++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_75,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4984++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_76,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_77,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_78,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_79,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_80,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_81,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_82,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_83,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_84,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_85,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_86,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_87,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_88,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_89,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_90,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_91,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_92,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_93,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_94,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_95,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_96,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_97,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_98,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_99,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_100,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_101,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_102,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_103,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_104,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_105,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_106,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_107,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_108,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_109,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_110,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_111,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_112,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_113,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_114,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_115,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_116,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_117,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_118,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_119,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_120,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_121,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_122,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_123,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_124,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_125,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_126,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_127,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4008++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4028++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4048++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4068++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4088++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4108++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4128++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4148++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4168++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4188++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4208++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4228++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4248++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4268++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4288++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4308++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4328++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4348++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4368++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4388++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4408++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4428++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4448++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4468++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4488++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4508++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4528++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4548++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4568++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4588++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4608++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4628++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4648++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4668++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4688++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4708++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4728++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4748++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4768++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4788++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4808++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4828++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4848++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4868++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4888++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4908++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4928++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4948++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4968++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4988++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x400C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_0,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x402C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_1,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x404C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_2,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x406C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_3,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x408C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_4,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_5,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_6,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_7,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x410C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_8,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x412C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_9,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x414C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_10,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x416C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_11,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x418C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_12,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_13,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_14,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_15,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x420C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_16,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x422C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_17,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x424C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_18,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x426C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_19,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x428C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_20,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_21,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_22,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_23,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x430C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_24,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x432C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_25,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x434C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_26,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x436C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_27,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x438C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_28,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_29,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_30,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_31,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x440C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_32,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x442C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_33,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x444C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_34,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x446C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_35,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x448C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_36,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_37,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_38,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_39,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x450C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_40,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x452C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_41,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x454C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_42,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x456C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_43,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x458C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_44,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_45,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_46,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_47,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x460C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_48,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x462C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_49,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x464C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_50,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x466C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_51,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x468C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_52,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_53,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_54,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_55,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x470C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_56,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x472C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_57,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x474C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_58,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x476C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_59,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x478C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_60,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_61,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_62,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_63,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x480C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_64,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x482C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_65,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x484C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_66,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x486C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_67,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x488C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_68,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_69,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_70,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_71,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x490C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_72,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x492C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_73,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x494C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_74,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x496C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_75,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x498C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_76,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_77,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_78,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_79,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_80,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_81,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_82,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_83,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_84,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_85,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ACC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_86,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_87,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_88,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_89,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_90,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_91,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_92,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_93,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_94,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_95,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_96,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_97,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_98,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_99,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_100,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_101,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_102,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_103,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_104,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_105,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_106,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_107,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_108,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_109,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_110,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_111,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_112,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_113,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_114,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_115,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_116,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_117,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ECC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_118,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_119,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_120,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_121,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_122,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_123,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_124,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_125,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_126,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_127,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4010++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_0,EDMA_TPCC_BIDX_n_0" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4030++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_1,EDMA_TPCC_BIDX_n_1" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4050++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_2,EDMA_TPCC_BIDX_n_2" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4070++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_3,EDMA_TPCC_BIDX_n_3" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4090++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_4,EDMA_TPCC_BIDX_n_4" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_5,EDMA_TPCC_BIDX_n_5" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_6,EDMA_TPCC_BIDX_n_6" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_7,EDMA_TPCC_BIDX_n_7" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4110++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_8,EDMA_TPCC_BIDX_n_8" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4130++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_9,EDMA_TPCC_BIDX_n_9" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4150++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_10,EDMA_TPCC_BIDX_n_10" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4170++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_11,EDMA_TPCC_BIDX_n_11" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4190++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_12,EDMA_TPCC_BIDX_n_12" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_13,EDMA_TPCC_BIDX_n_13" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_14,EDMA_TPCC_BIDX_n_14" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_15,EDMA_TPCC_BIDX_n_15" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4210++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_16,EDMA_TPCC_BIDX_n_16" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4230++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_17,EDMA_TPCC_BIDX_n_17" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4250++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_18,EDMA_TPCC_BIDX_n_18" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4270++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_19,EDMA_TPCC_BIDX_n_19" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4290++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_20,EDMA_TPCC_BIDX_n_20" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_21,EDMA_TPCC_BIDX_n_21" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_22,EDMA_TPCC_BIDX_n_22" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_23,EDMA_TPCC_BIDX_n_23" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4310++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_24,EDMA_TPCC_BIDX_n_24" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4330++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_25,EDMA_TPCC_BIDX_n_25" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4350++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_26,EDMA_TPCC_BIDX_n_26" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4370++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_27,EDMA_TPCC_BIDX_n_27" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4390++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_28,EDMA_TPCC_BIDX_n_28" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_29,EDMA_TPCC_BIDX_n_29" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_30,EDMA_TPCC_BIDX_n_30" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_31,EDMA_TPCC_BIDX_n_31" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4410++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_32,EDMA_TPCC_BIDX_n_32" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4430++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_33,EDMA_TPCC_BIDX_n_33" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4450++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_34,EDMA_TPCC_BIDX_n_34" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4470++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_35,EDMA_TPCC_BIDX_n_35" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4490++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_36,EDMA_TPCC_BIDX_n_36" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_37,EDMA_TPCC_BIDX_n_37" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_38,EDMA_TPCC_BIDX_n_38" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_39,EDMA_TPCC_BIDX_n_39" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4510++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_40,EDMA_TPCC_BIDX_n_40" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4530++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_41,EDMA_TPCC_BIDX_n_41" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4550++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_42,EDMA_TPCC_BIDX_n_42" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4570++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_43,EDMA_TPCC_BIDX_n_43" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4590++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_44,EDMA_TPCC_BIDX_n_44" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_45,EDMA_TPCC_BIDX_n_45" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_46,EDMA_TPCC_BIDX_n_46" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_47,EDMA_TPCC_BIDX_n_47" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4610++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_48,EDMA_TPCC_BIDX_n_48" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4630++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_49,EDMA_TPCC_BIDX_n_49" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4650++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_50,EDMA_TPCC_BIDX_n_50" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4670++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_51,EDMA_TPCC_BIDX_n_51" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4690++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_52,EDMA_TPCC_BIDX_n_52" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_53,EDMA_TPCC_BIDX_n_53" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_54,EDMA_TPCC_BIDX_n_54" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_55,EDMA_TPCC_BIDX_n_55" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4710++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_56,EDMA_TPCC_BIDX_n_56" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4730++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_57,EDMA_TPCC_BIDX_n_57" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4750++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_58,EDMA_TPCC_BIDX_n_58" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4770++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_59,EDMA_TPCC_BIDX_n_59" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4790++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_60,EDMA_TPCC_BIDX_n_60" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_61,EDMA_TPCC_BIDX_n_61" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_62,EDMA_TPCC_BIDX_n_62" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_63,EDMA_TPCC_BIDX_n_63" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4810++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_64,EDMA_TPCC_BIDX_n_64" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4830++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_65,EDMA_TPCC_BIDX_n_65" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4850++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_66,EDMA_TPCC_BIDX_n_66" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4870++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_67,EDMA_TPCC_BIDX_n_67" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4890++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_68,EDMA_TPCC_BIDX_n_68" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_69,EDMA_TPCC_BIDX_n_69" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_70,EDMA_TPCC_BIDX_n_70" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_71,EDMA_TPCC_BIDX_n_71" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4910++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_72,EDMA_TPCC_BIDX_n_72" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4930++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_73,EDMA_TPCC_BIDX_n_73" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4950++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_74,EDMA_TPCC_BIDX_n_74" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4970++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_75,EDMA_TPCC_BIDX_n_75" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4990++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_76,EDMA_TPCC_BIDX_n_76" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_77,EDMA_TPCC_BIDX_n_77" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_78,EDMA_TPCC_BIDX_n_78" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_79,EDMA_TPCC_BIDX_n_79" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_80,EDMA_TPCC_BIDX_n_80" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_81,EDMA_TPCC_BIDX_n_81" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_82,EDMA_TPCC_BIDX_n_82" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_83,EDMA_TPCC_BIDX_n_83" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_84,EDMA_TPCC_BIDX_n_84" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_85,EDMA_TPCC_BIDX_n_85" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_86,EDMA_TPCC_BIDX_n_86" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_87,EDMA_TPCC_BIDX_n_87" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_88,EDMA_TPCC_BIDX_n_88" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_89,EDMA_TPCC_BIDX_n_89" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_90,EDMA_TPCC_BIDX_n_90" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_91,EDMA_TPCC_BIDX_n_91" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_92,EDMA_TPCC_BIDX_n_92" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_93,EDMA_TPCC_BIDX_n_93" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_94,EDMA_TPCC_BIDX_n_94" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_95,EDMA_TPCC_BIDX_n_95" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_96,EDMA_TPCC_BIDX_n_96" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_97,EDMA_TPCC_BIDX_n_97" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_98,EDMA_TPCC_BIDX_n_98" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_99,EDMA_TPCC_BIDX_n_99" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_100,EDMA_TPCC_BIDX_n_100" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_101,EDMA_TPCC_BIDX_n_101" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_102,EDMA_TPCC_BIDX_n_102" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_103,EDMA_TPCC_BIDX_n_103" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_104,EDMA_TPCC_BIDX_n_104" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_105,EDMA_TPCC_BIDX_n_105" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_106,EDMA_TPCC_BIDX_n_106" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_107,EDMA_TPCC_BIDX_n_107" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_108,EDMA_TPCC_BIDX_n_108" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_109,EDMA_TPCC_BIDX_n_109" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_110,EDMA_TPCC_BIDX_n_110" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_111,EDMA_TPCC_BIDX_n_111" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_112,EDMA_TPCC_BIDX_n_112" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_113,EDMA_TPCC_BIDX_n_113" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_114,EDMA_TPCC_BIDX_n_114" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_115,EDMA_TPCC_BIDX_n_115" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_116,EDMA_TPCC_BIDX_n_116" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_117,EDMA_TPCC_BIDX_n_117" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4ED0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_118,EDMA_TPCC_BIDX_n_118" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_119,EDMA_TPCC_BIDX_n_119" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_120,EDMA_TPCC_BIDX_n_120" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_121,EDMA_TPCC_BIDX_n_121" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_122,EDMA_TPCC_BIDX_n_122" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_123,EDMA_TPCC_BIDX_n_123" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_124,EDMA_TPCC_BIDX_n_124" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_125,EDMA_TPCC_BIDX_n_125" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_126,EDMA_TPCC_BIDX_n_126" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_127,EDMA_TPCC_BIDX_n_127" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4014++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4034++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4054++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4074++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4094++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4114++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4134++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4154++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4174++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4194++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4214++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4234++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4254++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4274++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4294++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4314++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4334++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4354++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4374++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4394++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4414++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4434++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4454++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4474++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4494++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4514++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4534++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4554++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4574++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4594++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4614++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4634++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4654++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4674++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4694++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4714++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4734++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4754++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4774++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4794++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4814++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4834++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4854++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4874++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4894++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4914++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4934++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4954++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4974++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4994++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4ED4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4018++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4038++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4058++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4078++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4098++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4118++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4138++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4158++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4178++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4198++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4218++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4238++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4258++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4278++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4298++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4318++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4338++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4358++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4378++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4398++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4418++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4438++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4458++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4478++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4498++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4518++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4538++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4558++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4578++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4598++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4618++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4638++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4658++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4678++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4698++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4718++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4738++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4758++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4778++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4798++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4818++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4838++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4858++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4878++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4898++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4918++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4938++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4958++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4978++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4998++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4ED8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x401C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x403C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x405C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x407C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x409C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x411C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x413C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x415C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x417C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x419C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x421C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x423C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x425C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x427C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x429C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x431C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x433C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x435C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x437C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x439C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x441C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x443C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x445C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x447C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x449C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x451C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x453C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x455C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x457C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x459C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x461C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x463C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x465C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x467C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x469C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x471C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x473C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x475C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x477C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x479C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x481C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x483C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x485C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x487C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x489C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x491C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x493C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x495C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x497C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x499C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ABC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ADC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4AFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "SYS_EDMA_TPCC" base ad:0x43300000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPCC_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x0 0.--2. " NUMDMACH ,Number of DMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--6. " NUMQDMACH ,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 8.--10. " NUMINTCH ,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 12.--14. " NUMPAENTRY ,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 16.--18. " NUMTC ,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 20.--21. " NUMREGN ,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 24. " CHMAPEXIST ,Channel Mapping Existence" "0,1" bitfld.long 0x0 25. " MPEXIST ,Memory Protection Existence" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reads return 0's" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xFC++0x3 line.long 0x0 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x0 0. " CLKGDIS ,Auto Clock Gate Disable" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x114++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x118++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x11C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x138++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x13C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x144++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x148++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x14C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x150++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x154++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x158++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x15C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x160++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x164++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x168++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x16C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x170++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x174++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x178++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x17C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x180++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x194++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x198++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x19C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1AC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1BC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1CC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1DC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1EC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x248++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x254++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x260++0x3 line.long 0x0 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." bitfld.long 0x0 0.--2. " E0 ,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x280++0x3 line.long 0x0 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x0 0.--2. " TCNUMQ0 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " TCNUMQ1 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x0 0.--2. " PRIQ0 ,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " PRIQ1 ,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x300++0x3 line.long 0x0 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed #31" "0,1" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E32 ,Event Missed #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed #63" "0,1" group.byte 0x308++0x3 line.long 0x0 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed Clear #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed Clear #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed Clear #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed Clear #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed Clear #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed Clear #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed Clear #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed Clear #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed Clear #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed Clear #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed Clear #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed Clear #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed Clear #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed Clear #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed Clear #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed Clear #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed Clear #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed Clear #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed Clear #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed Clear #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed Clear #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed Clear #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed Clear #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed Clear #31" "0,1" group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E32 ,Event Missed Clear #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed Clear #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed Clear #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed Clear #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed Clear #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed Clear #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed Clear #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed Clear #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed Clear #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed Clear #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed Clear #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed Clear #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed Clear #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed Clear #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed Clear #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed Clear #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed Clear #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed Clear #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed Clear #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed Clear #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed Clear #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed Clear #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed Clear #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed Clear #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed Clear #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed Clear #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed Clear #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed Clear #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed Clear #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed Clear #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed Clear #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed Clear #63" "0,1" group.byte 0x310++0x3 line.long 0x0 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced. If any bit in the register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x314++0x3 line.long 0x0 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x318++0x3 line.long 0x0 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x0 0. " QTHRXCD0 ,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors were previously clear), then an error will be signaled with TPCC error interrupt. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x31C++0x3 line.long 0x0 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x0 0. " QTHRXCD0 ,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT0.WM, QSTAT0.THRXCD,[0] QTHRXCD0 ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM, QSTAT1.THRXCD,[1] QTHRXCD1 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT2.WM, QSTAT2.THRXCD,[2] QTHRXCD2 ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM, QSTAT3.THRXCD,[3] QTHRXCD3 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT4.WM, QSTAT4.THRXCD,[4] QTHRXCD4 ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT5.WM, QSTAT5.THRXCD,[5]QTHRXCD5 ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT6.WM, QSTAT6.THRXCD,[6]QTHRXCD6 ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT7.WM, QSTAT7.THRXCD,[7] QTHRXCD7 ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR. . Write 0x0 have no affect. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x320++0x3 line.long 0x0 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x0 0. " EVAL ,Error Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the/, , or registers. The CPU must also write 0x1 after any error interrupts are serviced in order for subsequent interrupts to be asserted. ." "0,1" bitfld.long 0x0 1. " SET ,Error Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of/, , or . ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x348++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x350++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x358++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x360++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x368++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x370++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x378++0x3 line.long 0x0 "EDMA_TPCC_DRAEM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E0 ,DMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,DMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,DMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,DMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,DMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,DMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,DMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,DMA Region Access enable for Region M, bit #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,DMA Region Access enable for Region M, bit #8" "0,1" bitfld.long 0x0 9. " E9 ,DMA Region Access enable for Region M, bit #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,DMA Region Access enable for Region M, bit #10" "0,1" bitfld.long 0x0 11. " E11 ,DMA Region Access enable for Region M, bit #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,DMA Region Access enable for Region M, bit #12" "0,1" bitfld.long 0x0 13. " E13 ,DMA Region Access enable for Region M, bit #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,DMA Region Access enable for Region M, bit #14" "0,1" bitfld.long 0x0 15. " E15 ,DMA Region Access enable for Region M, bit #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,DMA Region Access enable for Region M, bit #16" "0,1" bitfld.long 0x0 17. " E17 ,DMA Region Access enable for Region M, bit #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,DMA Region Access enable for Region M, bit #18" "0,1" bitfld.long 0x0 19. " E19 ,DMA Region Access enable for Region M, bit #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,DMA Region Access enable for Region M, bit #20" "0,1" bitfld.long 0x0 21. " E21 ,DMA Region Access enable for Region M, bit #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,DMA Region Access enable for Region M, bit #22" "0,1" bitfld.long 0x0 23. " E23 ,DMA Region Access enable for Region M, bit #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,DMA Region Access enable for Region M, bit #24" "0,1" bitfld.long 0x0 25. " E25 ,DMA Region Access enable for Region M, bit #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,DMA Region Access enable for Region M, bit #26" "0,1" bitfld.long 0x0 27. " E27 ,DMA Region Access enable for Region M, bit #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,DMA Region Access enable for Region M, bit #28" "0,1" bitfld.long 0x0 29. " E29 ,DMA Region Access enable for Region M, bit #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,DMA Region Access enable for Region M, bit #30" "0,1" bitfld.long 0x0 31. " E31 ,DMA Region Access enable for Region M, bit #31" "0,1" group.byte 0x344++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_0,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_1,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_2,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x35C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_3,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x364++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_4,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x36C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_5,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x374++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_6,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x37C++0x3 line.long 0x0 "EDMA_TPCC_DRAEHM_k_7,DMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt. En = 0 : Accesses via Region M address space to Bit N in any DMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any DMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region M interrupt." bitfld.long 0x0 0. " E32 ,DMA Region Access enable for Region M, bit #32" "0,1" bitfld.long 0x0 1. " E33 ,DMA Region Access enable for Region M, bit #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,DMA Region Access enable for Region M, bit #34" "0,1" bitfld.long 0x0 3. " E35 ,DMA Region Access enable for Region M, bit #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,DMA Region Access enable for Region M, bit #36" "0,1" bitfld.long 0x0 5. " E37 ,DMA Region Access enable for Region M, bit #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,DMA Region Access enable for Region M, bit #38" "0,1" bitfld.long 0x0 7. " E39 ,DMA Region Access enable for Region M, bit #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,DMA Region Access enable for Region M, bit #40" "0,1" bitfld.long 0x0 9. " E41 ,DMA Region Access enable for Region M, bit #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,DMA Region Access enable for Region M, bit #42" "0,1" bitfld.long 0x0 11. " E43 ,DMA Region Access enable for Region M, bit #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,DMA Region Access enable for Region M, bit #44" "0,1" bitfld.long 0x0 13. " E45 ,DMA Region Access enable for Region M, bit #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,DMA Region Access enable for Region M, bit #46" "0,1" bitfld.long 0x0 15. " E47 ,DMA Region Access enable for Region M, bit #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,DMA Region Access enable for Region M, bit #48" "0,1" bitfld.long 0x0 17. " E49 ,DMA Region Access enable for Region M, bit #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,DMA Region Access enable for Region M, bit #50" "0,1" bitfld.long 0x0 19. " E51 ,DMA Region Access enable for Region M, bit #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,DMA Region Access enable for Region M, bit #52" "0,1" bitfld.long 0x0 21. " E53 ,DMA Region Access enable for Region M, bit #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,DMA Region Access enable for Region M, bit #54" "0,1" bitfld.long 0x0 23. " E55 ,DMA Region Access enable for Region M, bit #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,DMA Region Access enable for Region M, bit #56" "0,1" bitfld.long 0x0 25. " E57 ,DMA Region Access enable for Region M, bit #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,DMA Region Access enable for Region M, bit #58" "0,1" bitfld.long 0x0 27. " E59 ,DMA Region Access enable for Region M, bit #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,DMA Region Access enable for Region M, bit #60" "0,1" bitfld.long 0x0 29. " E61 ,DMA Region Access enable for Region M, bit #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,DMA Region Access enable for Region M, bit #62" "0,1" bitfld.long 0x0 31. " E63 ,DMA Region Access enable for Region M, bit #63" "0,1" group.byte 0x380++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x388++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x38C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x39C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x400++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_0,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x404++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_1,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x408++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_2,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x40C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_3,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x410++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_4,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x414++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_5,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x418++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_6,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x41C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_7,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x420++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_8,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x424++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_9,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x428++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_10,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x42C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_11,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x430++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_12,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x434++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_13,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x438++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_14,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x43C++0x3 line.long 0x0 "EDMA_TPCC_Q0E_p_15,Event Queue Entries Diagram for Queue 0 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER/EDMA_TPCC_ESR/EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x440++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_0,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x444++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_1,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x448++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_2,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x44C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_3,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x450++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_4,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x454++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_5,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x458++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_6,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x45C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_7,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x460++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_8,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x464++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_9,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x468++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_10,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x46C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_11,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x470++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_12,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x474++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_13,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x478++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_14,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x47C++0x3 line.long 0x0 "EDMA_TPCC_Q1E_p_15,Event Queue Entries Diagram for Queue 1 - Entry 0 through Entry 15" bitfld.long 0x0 0.--5. " ENUM ,Event Number: Specifies the specific Event Number for the given entry in the Event Queue. For DMA Channel events (EDMA_TPCC_ER / EDMA_TPCC_ESR / EDMA_TPCC_CER), ENUM will range between 0 and NUM_DMACH (up to 63). For QDMA Channel events (EDMA_TPCC_QER), ENUM will range between 0 and NUM_QDMACH (up to 7)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " ETYPE ,Event Type: Specifies the specific Event Type for the given entry in the Event Queue." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRA,Queue Threshold A, for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q0 ,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q1 ,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q2 ,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q3 ,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x624++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRB,Queue Threshold B, for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q4 ,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q5 ,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q6 ,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q7 ,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x0 0. " EVTACTV ,DMA Event Active" "0,1" bitfld.long 0x0 1. " QEVTACTV ,QDMA Event Active" "0,1" textline " " bitfld.long 0x0 2. " TRACTV ,Transfer Request Active TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0,1" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4. " ACTV ,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals. The ACTV bit must remain high through the life of a:" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,reads return 0's" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " COMPACTV ,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " QUEACTV0 ,Queue 0 Active" "0,1" bitfld.long 0x0 17. " QUEACTV1 ,Queue 1 Active" "0,1" textline " " bitfld.long 0x0 18. " QUEACTV2 ,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0,1" bitfld.long 0x0 19. " QUEACTV3 ,Queue 3 Active" "0,1" textline " " bitfld.long 0x0 20. " QUEACTV4 ,Queue 4 Active" "0,1" bitfld.long 0x0 21. " QUEACTV5 ,Queue 5 Active" "0,1" textline " " bitfld.long 0x0 22. " QUEACTV6 ,Queue 6 Active" "0,1" bitfld.long 0x0 23. " QUEACTV7 ,Queue 7 Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,reads return 0's" group.byte 0x700++0x3 line.long 0x0 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 0.--5. " STRTEVT ,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " TYPE ,AET Event Type" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--13. " ENDINT ,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.tbyte 0x0 14.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " EN ,AET Enable" "0,1" group.byte 0x704++0x3 line.long 0x0 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x0 0. " STAT ,AET Status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x708++0x3 line.long 0x0 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x0 0. " CLR ,AET Clear commandCPU writes 0x0 has no effect. . CPU writes 0x1 to the CLR bit causes the tpcc_aet output signal and[0]STAT register to be cleared. ." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" hexmask.long 0x0 0.--31. 1. " FADDR ,Fault Address: 32-bit read-only status register containing the faulting address when a mMemory protection violation is detected. This register can only be cleared via theEDMA_TPCC_MPFCR." group.byte 0x804++0x3 line.long 0x0 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x0 0. " UXE ,User Execute Error" "0,1" bitfld.long 0x0 1. " UWE ,User Write Error" "0,1" textline " " bitfld.long 0x0 2. " URE ,User Read Error" "0,1" bitfld.long 0x0 3. " SXE ,Supervisor Execute Error" "0,1" textline " " bitfld.long 0x0 4. " SWE ,Supervisor Write Error" "0,1" bitfld.long 0x0 5. " SRE ,Supervisor Read Error" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--12. " FID ,Faulted ID: FID register contains valid info if any of the MP error bits (UXE, UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x808++0x3 line.long 0x0 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x0 0. " MPFCLR ,Fault Clear register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x80C++0x3 line.long 0x0 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0" "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x810++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x814++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x818++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x81C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x820++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x824++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x828++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x82C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x1000++0x3 line.long 0x0 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1004++0x3 line.long 0x0 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1008++0x3 line.long 0x0 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x100C++0x3 line.long 0x0 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1010++0x3 line.long 0x0 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1014++0x3 line.long 0x0 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1018++0x3 line.long 0x0 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x101C++0x3 line.long 0x0 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1020++0x3 line.long 0x0 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1024++0x3 line.long 0x0 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1028++0x3 line.long 0x0 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x102C++0x3 line.long 0x0 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1030++0x3 line.long 0x0 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1034++0x3 line.long 0x0 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1038++0x3 line.long 0x0 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x103C++0x3 line.long 0x0 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1040++0x3 line.long 0x0 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1044++0x3 line.long 0x0 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1050++0x3 line.long 0x0 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1054++0x3 line.long 0x0 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1058++0x3 line.long 0x0 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x105C++0x3 line.long 0x0 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1060++0x3 line.long 0x0 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1064++0x3 line.long 0x0 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1068++0x3 line.long 0x0 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x106C++0x3 line.long 0x0 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. . In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1070++0x3 line.long 0x0 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1074++0x3 line.long 0x0 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" bitfld.long 0x0 1. " SET ,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1080++0x3 line.long 0x0 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1084++0x3 line.long 0x0 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1088++0x3 line.long 0x0 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x108C++0x3 line.long 0x0 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1090++0x3 line.long 0x0 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1094++0x3 line.long 0x0 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2000++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2200++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2400++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2600++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2800++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2004++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2204++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2404++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2604++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2804++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2008++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2208++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2408++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2608++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2808++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x200C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x220C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x240C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x260C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x280C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2010++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2210++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2410++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2610++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2810++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2014++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2214++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2414++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2614++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2814++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2018++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2218++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2418++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2618++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2818++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x201C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x221C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x241C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x261C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x281C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2020++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2220++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2420++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2620++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2820++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2024++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2224++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2424++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2624++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2824++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2028++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2228++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2428++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2628++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2828++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x202C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x222C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x242C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x262C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x282C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2030++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2230++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2430++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2630++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2830++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2034++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2234++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2434++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2634++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2834++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2038++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2238++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2438++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2638++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2838++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x203C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x223C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x243C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x263C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x283C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2040++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2240++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2440++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2640++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2840++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2044++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2244++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2444++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2644++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2844++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2050++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2250++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2450++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2650++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2850++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2054++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2254++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2454++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2654++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2854++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2058++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2258++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2458++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2658++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2858++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x205C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x225C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x245C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x265C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x285C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2060++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2260++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2460++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2660++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2860++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2064++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2264++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2464++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2664++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2864++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2068++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2268++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2468++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2668++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2868++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x206C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x226C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x246C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x266C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x286C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2070++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2270++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2470++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2670++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2870++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2074++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2274++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2474++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2674++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2874++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2278++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2478++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2678++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2878++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2A78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2C78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2E78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2080++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2280++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2480++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2680++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2880++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2084++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2284++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2484++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2684++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2884++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2088++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2288++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2488++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2688++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2888++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x208C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x228C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x248C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x268C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x288C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2090++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2290++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2490++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2690++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2890++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2094++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2294++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2494++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2694++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2894++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2A94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2C94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2E94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x4000++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_0,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4020++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_1,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4040++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_2,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4060++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_3,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4080++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_4,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_5,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_6,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_7,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4100++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_8,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4120++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_9,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4140++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_10,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4160++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_11,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4180++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_12,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_13,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_14,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_15,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4200++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_16,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4220++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_17,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4240++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_18,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4260++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_19,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4280++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_20,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_21,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_22,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_23,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4300++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_24,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4320++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_25,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4340++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_26,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4360++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_27,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4380++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_28,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_29,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_30,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_31,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4400++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_32,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4420++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_33,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4440++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_34,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4460++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_35,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4480++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_36,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_37,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_38,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_39,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4500++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_40,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4520++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_41,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4540++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_42,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4560++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_43,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4580++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_44,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_45,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_46,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_47,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4600++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_48,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4620++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_49,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4640++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_50,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4660++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_51,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4680++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_52,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_53,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_54,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_55,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4700++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_56,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4720++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_57,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4740++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_58,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4760++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_59,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4780++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_60,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_61,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_62,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_63,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4800++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_64,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4820++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_65,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4840++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_66,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4860++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_67,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4880++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_68,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_69,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_70,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_71,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4900++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_72,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4920++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_73,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4940++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_74,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4960++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_75,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4980++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_76,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_77,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_78,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_79,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_80,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_81,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_82,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_83,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_84,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_85,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_86,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_87,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_88,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_89,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_90,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_91,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_92,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_93,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_94,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_95,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_96,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_97,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_98,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_99,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_100,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_101,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_102,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_103,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_104,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_105,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_106,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_107,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_108,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_109,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_110,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_111,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_112,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_113,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_114,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_115,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_116,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_117,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_118,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_119,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_120,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_121,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_122,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_123,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_124,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_125,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_126,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_127,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4004++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_0,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4024++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_1,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4044++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_2,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4064++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_3,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4084++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_4,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_5,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_6,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_7,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4104++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_8,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4124++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_9,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4144++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_10,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4164++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_11,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4184++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_12,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_13,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_14,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_15,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4204++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_16,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4224++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_17,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4244++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_18,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4264++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_19,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4284++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_20,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_21,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_22,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_23,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4304++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_24,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4324++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_25,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4344++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_26,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4364++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_27,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4384++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_28,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_29,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_30,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_31,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4404++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_32,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4424++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_33,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4444++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_34,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4464++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_35,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4484++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_36,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_37,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_38,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_39,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4504++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_40,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4524++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_41,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4544++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_42,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4564++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_43,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4584++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_44,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_45,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_46,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_47,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4604++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_48,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4624++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_49,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4644++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_50,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4664++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_51,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4684++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_52,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_53,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_54,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_55,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4704++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_56,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4724++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_57,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4744++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_58,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4764++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_59,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4784++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_60,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_61,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_62,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_63,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4804++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_64,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4824++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_65,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4844++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_66,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4864++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_67,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4884++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_68,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_69,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_70,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_71,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4904++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_72,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4924++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_73,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4944++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_74,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4964++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_75,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4984++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_76,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_77,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_78,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_79,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_80,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_81,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_82,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_83,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_84,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_85,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_86,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_87,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_88,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_89,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_90,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_91,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_92,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_93,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_94,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_95,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_96,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_97,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_98,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_99,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_100,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_101,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_102,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_103,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_104,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_105,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_106,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_107,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_108,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_109,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_110,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_111,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_112,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_113,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_114,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_115,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_116,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_117,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_118,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_119,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_120,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_121,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_122,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_123,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_124,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_125,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_126,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_127,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4008++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4028++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4048++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4068++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4088++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4108++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4128++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4148++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4168++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4188++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4208++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4228++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4248++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4268++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4288++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4308++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4328++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4348++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4368++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4388++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4408++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4428++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4448++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4468++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4488++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4508++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4528++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4548++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4568++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4588++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4608++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4628++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4648++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4668++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4688++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4708++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4728++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4748++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4768++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4788++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4808++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4828++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4848++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4868++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4888++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4908++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4928++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4948++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4968++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4988++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x400C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_0,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x402C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_1,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x404C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_2,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x406C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_3,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x408C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_4,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_5,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_6,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_7,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x410C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_8,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x412C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_9,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x414C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_10,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x416C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_11,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x418C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_12,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_13,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_14,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_15,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x420C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_16,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x422C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_17,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x424C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_18,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x426C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_19,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x428C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_20,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_21,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_22,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_23,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x430C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_24,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x432C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_25,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x434C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_26,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x436C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_27,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x438C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_28,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_29,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_30,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_31,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x440C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_32,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x442C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_33,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x444C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_34,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x446C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_35,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x448C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_36,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_37,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_38,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_39,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x450C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_40,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x452C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_41,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x454C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_42,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x456C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_43,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x458C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_44,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_45,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_46,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_47,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x460C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_48,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x462C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_49,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x464C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_50,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x466C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_51,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x468C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_52,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_53,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_54,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_55,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x470C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_56,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x472C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_57,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x474C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_58,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x476C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_59,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x478C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_60,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_61,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_62,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_63,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x480C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_64,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x482C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_65,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x484C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_66,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x486C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_67,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x488C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_68,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_69,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_70,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_71,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x490C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_72,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x492C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_73,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x494C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_74,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x496C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_75,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x498C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_76,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_77,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_78,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_79,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_80,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_81,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_82,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_83,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_84,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_85,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ACC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_86,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_87,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_88,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_89,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_90,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_91,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_92,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_93,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_94,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_95,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_96,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_97,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_98,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_99,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_100,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_101,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_102,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_103,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_104,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_105,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_106,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_107,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_108,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_109,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_110,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_111,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_112,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_113,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_114,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_115,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_116,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_117,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ECC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_118,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_119,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_120,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_121,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_122,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_123,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_124,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_125,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_126,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_127,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4010++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_0,EDMA_TPCC_BIDX_n_0" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4030++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_1,EDMA_TPCC_BIDX_n_1" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4050++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_2,EDMA_TPCC_BIDX_n_2" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4070++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_3,EDMA_TPCC_BIDX_n_3" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4090++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_4,EDMA_TPCC_BIDX_n_4" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_5,EDMA_TPCC_BIDX_n_5" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_6,EDMA_TPCC_BIDX_n_6" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_7,EDMA_TPCC_BIDX_n_7" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4110++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_8,EDMA_TPCC_BIDX_n_8" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4130++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_9,EDMA_TPCC_BIDX_n_9" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4150++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_10,EDMA_TPCC_BIDX_n_10" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4170++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_11,EDMA_TPCC_BIDX_n_11" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4190++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_12,EDMA_TPCC_BIDX_n_12" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_13,EDMA_TPCC_BIDX_n_13" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_14,EDMA_TPCC_BIDX_n_14" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_15,EDMA_TPCC_BIDX_n_15" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4210++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_16,EDMA_TPCC_BIDX_n_16" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4230++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_17,EDMA_TPCC_BIDX_n_17" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4250++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_18,EDMA_TPCC_BIDX_n_18" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4270++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_19,EDMA_TPCC_BIDX_n_19" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4290++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_20,EDMA_TPCC_BIDX_n_20" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_21,EDMA_TPCC_BIDX_n_21" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_22,EDMA_TPCC_BIDX_n_22" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_23,EDMA_TPCC_BIDX_n_23" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4310++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_24,EDMA_TPCC_BIDX_n_24" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4330++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_25,EDMA_TPCC_BIDX_n_25" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4350++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_26,EDMA_TPCC_BIDX_n_26" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4370++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_27,EDMA_TPCC_BIDX_n_27" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4390++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_28,EDMA_TPCC_BIDX_n_28" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_29,EDMA_TPCC_BIDX_n_29" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_30,EDMA_TPCC_BIDX_n_30" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_31,EDMA_TPCC_BIDX_n_31" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4410++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_32,EDMA_TPCC_BIDX_n_32" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4430++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_33,EDMA_TPCC_BIDX_n_33" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4450++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_34,EDMA_TPCC_BIDX_n_34" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4470++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_35,EDMA_TPCC_BIDX_n_35" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4490++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_36,EDMA_TPCC_BIDX_n_36" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_37,EDMA_TPCC_BIDX_n_37" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_38,EDMA_TPCC_BIDX_n_38" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_39,EDMA_TPCC_BIDX_n_39" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4510++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_40,EDMA_TPCC_BIDX_n_40" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4530++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_41,EDMA_TPCC_BIDX_n_41" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4550++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_42,EDMA_TPCC_BIDX_n_42" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4570++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_43,EDMA_TPCC_BIDX_n_43" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4590++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_44,EDMA_TPCC_BIDX_n_44" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_45,EDMA_TPCC_BIDX_n_45" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_46,EDMA_TPCC_BIDX_n_46" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_47,EDMA_TPCC_BIDX_n_47" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4610++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_48,EDMA_TPCC_BIDX_n_48" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4630++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_49,EDMA_TPCC_BIDX_n_49" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4650++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_50,EDMA_TPCC_BIDX_n_50" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4670++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_51,EDMA_TPCC_BIDX_n_51" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4690++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_52,EDMA_TPCC_BIDX_n_52" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_53,EDMA_TPCC_BIDX_n_53" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_54,EDMA_TPCC_BIDX_n_54" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_55,EDMA_TPCC_BIDX_n_55" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4710++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_56,EDMA_TPCC_BIDX_n_56" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4730++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_57,EDMA_TPCC_BIDX_n_57" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4750++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_58,EDMA_TPCC_BIDX_n_58" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4770++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_59,EDMA_TPCC_BIDX_n_59" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4790++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_60,EDMA_TPCC_BIDX_n_60" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_61,EDMA_TPCC_BIDX_n_61" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_62,EDMA_TPCC_BIDX_n_62" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_63,EDMA_TPCC_BIDX_n_63" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4810++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_64,EDMA_TPCC_BIDX_n_64" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4830++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_65,EDMA_TPCC_BIDX_n_65" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4850++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_66,EDMA_TPCC_BIDX_n_66" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4870++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_67,EDMA_TPCC_BIDX_n_67" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4890++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_68,EDMA_TPCC_BIDX_n_68" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_69,EDMA_TPCC_BIDX_n_69" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_70,EDMA_TPCC_BIDX_n_70" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_71,EDMA_TPCC_BIDX_n_71" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4910++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_72,EDMA_TPCC_BIDX_n_72" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4930++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_73,EDMA_TPCC_BIDX_n_73" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4950++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_74,EDMA_TPCC_BIDX_n_74" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4970++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_75,EDMA_TPCC_BIDX_n_75" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4990++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_76,EDMA_TPCC_BIDX_n_76" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_77,EDMA_TPCC_BIDX_n_77" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_78,EDMA_TPCC_BIDX_n_78" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_79,EDMA_TPCC_BIDX_n_79" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_80,EDMA_TPCC_BIDX_n_80" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_81,EDMA_TPCC_BIDX_n_81" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_82,EDMA_TPCC_BIDX_n_82" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_83,EDMA_TPCC_BIDX_n_83" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_84,EDMA_TPCC_BIDX_n_84" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_85,EDMA_TPCC_BIDX_n_85" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_86,EDMA_TPCC_BIDX_n_86" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_87,EDMA_TPCC_BIDX_n_87" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_88,EDMA_TPCC_BIDX_n_88" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_89,EDMA_TPCC_BIDX_n_89" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_90,EDMA_TPCC_BIDX_n_90" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_91,EDMA_TPCC_BIDX_n_91" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_92,EDMA_TPCC_BIDX_n_92" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_93,EDMA_TPCC_BIDX_n_93" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_94,EDMA_TPCC_BIDX_n_94" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_95,EDMA_TPCC_BIDX_n_95" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_96,EDMA_TPCC_BIDX_n_96" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_97,EDMA_TPCC_BIDX_n_97" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_98,EDMA_TPCC_BIDX_n_98" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_99,EDMA_TPCC_BIDX_n_99" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_100,EDMA_TPCC_BIDX_n_100" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_101,EDMA_TPCC_BIDX_n_101" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_102,EDMA_TPCC_BIDX_n_102" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_103,EDMA_TPCC_BIDX_n_103" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_104,EDMA_TPCC_BIDX_n_104" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_105,EDMA_TPCC_BIDX_n_105" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_106,EDMA_TPCC_BIDX_n_106" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_107,EDMA_TPCC_BIDX_n_107" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_108,EDMA_TPCC_BIDX_n_108" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_109,EDMA_TPCC_BIDX_n_109" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_110,EDMA_TPCC_BIDX_n_110" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_111,EDMA_TPCC_BIDX_n_111" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_112,EDMA_TPCC_BIDX_n_112" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_113,EDMA_TPCC_BIDX_n_113" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_114,EDMA_TPCC_BIDX_n_114" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_115,EDMA_TPCC_BIDX_n_115" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_116,EDMA_TPCC_BIDX_n_116" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_117,EDMA_TPCC_BIDX_n_117" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4ED0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_118,EDMA_TPCC_BIDX_n_118" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_119,EDMA_TPCC_BIDX_n_119" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_120,EDMA_TPCC_BIDX_n_120" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_121,EDMA_TPCC_BIDX_n_121" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_122,EDMA_TPCC_BIDX_n_122" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_123,EDMA_TPCC_BIDX_n_123" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_124,EDMA_TPCC_BIDX_n_124" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_125,EDMA_TPCC_BIDX_n_125" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_126,EDMA_TPCC_BIDX_n_126" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_127,EDMA_TPCC_BIDX_n_127" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4014++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4034++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4054++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4074++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4094++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4114++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4134++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4154++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4174++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4194++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4214++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4234++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4254++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4274++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4294++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4314++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4334++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4354++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4374++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4394++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4414++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4434++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4454++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4474++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4494++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4514++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4534++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4554++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4574++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4594++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4614++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4634++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4654++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4674++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4694++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4714++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4734++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4754++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4774++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4794++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4814++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4834++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4854++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4874++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4894++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4914++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4934++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4954++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4974++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4994++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4ED4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4018++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4038++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4058++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4078++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4098++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4118++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4138++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4158++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4178++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4198++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4218++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4238++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4258++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4278++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4298++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4318++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4338++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4358++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4378++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4398++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4418++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4438++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4458++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4478++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4498++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4518++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4538++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4558++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4578++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4598++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4618++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4638++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4658++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4678++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4698++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4718++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4738++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4758++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4778++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4798++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4818++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4838++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4858++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4878++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4898++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4918++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4938++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4958++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4978++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4998++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4ED8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x401C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x403C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x405C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x407C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x409C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x411C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x413C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x415C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x417C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x419C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x421C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x423C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x425C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x427C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x429C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x431C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x433C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x435C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x437C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x439C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x441C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x443C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x445C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x447C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x449C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x451C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x453C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x455C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x457C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x459C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x461C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x463C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x465C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x467C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x469C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x471C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x473C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x475C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x477C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x479C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x481C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x483C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x485C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x487C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x489C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x491C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x493C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x495C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x497C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x499C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ABC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ADC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4AFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE3_EDMA_TPCC" base ad:0x422A0000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPCC_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x0 0.--2. " NUMDMACH ,Number of DMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " NUMQDMACH ,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " NUMINTCH ,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " NUMPAENTRY ,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " NUMTC ,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--21. " NUMREGN ,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 24. " CHMAPEXIST ,Channel Mapping Existence" "0,1" bitfld.long 0x0 25. " MPEXIST ,Memory Protection Existence" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xFC++0x3 line.long 0x0 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x0 0. " CLKGDIS ,Auto Clock Gate Disable" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x114++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x118++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x11C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x138++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x13C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x144++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x148++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x14C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x150++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x154++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x158++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x15C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x160++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x164++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x168++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x16C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x170++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x174++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x178++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x17C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x180++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x194++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x198++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x19C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1AC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1BC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1CC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1DC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1EC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x248++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x254++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x260++0x3 line.long 0x0 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." bitfld.long 0x0 0.--2. " E0 ,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x280++0x3 line.long 0x0 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x0 0.--2. " TCNUMQ0 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " TCNUMQ1 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x0 0.--2. " PRIQ0 ,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " PRIQ1 ,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x300++0x3 line.long 0x0 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed #31" "0,1" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E32 ,Event Missed #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed #63" "0,1" group.byte 0x308++0x3 line.long 0x0 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed Clear #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed Clear #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed Clear #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed Clear #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed Clear #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed Clear #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed Clear #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed Clear #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed Clear #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed Clear #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed Clear #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed Clear #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed Clear #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed Clear #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed Clear #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed Clear #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed Clear #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed Clear #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed Clear #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed Clear #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed Clear #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed Clear #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed Clear #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed Clear #31" "0,1" group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E32 ,Event Missed Clear #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed Clear #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed Clear #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed Clear #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed Clear #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed Clear #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed Clear #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed Clear #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed Clear #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed Clear #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed Clear #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed Clear #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed Clear #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed Clear #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed Clear #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed Clear #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed Clear #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed Clear #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed Clear #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed Clear #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed Clear #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed Clear #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed Clear #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed Clear #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed Clear #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed Clear #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed Clear #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed Clear #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed Clear #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed Clear #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed Clear #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed Clear #63" "0,1" group.byte 0x310++0x3 line.long 0x0 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced. If any bit in the register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x314++0x3 line.long 0x0 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x318++0x3 line.long 0x0 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x0 0. " QTHRXCD0 ,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors were previously clear), then an error will be signaled with TPCC error interrupt. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x31C++0x3 line.long 0x0 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x0 0. " QTHRXCD0 ,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT0.WM, QSTAT0.THRXCD,[0] QTHRXCD0 ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM, QSTAT1.THRXCD,[1] QTHRXCD1 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT2.WM, QSTAT2.THRXCD,[2] QTHRXCD2 ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM, QSTAT3.THRXCD,[3] QTHRXCD3 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT4.WM, QSTAT4.THRXCD,[4] QTHRXCD4 ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT5.WM, QSTAT5.THRXCD,[5]QTHRXCD5 ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT6.WM, QSTAT6.THRXCD,[6]QTHRXCD6 ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT7.WM, QSTAT7.THRXCD,[7] QTHRXCD7 ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR. . Write 0x0 have no affect. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x320++0x3 line.long 0x0 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x0 0. " EVAL ,Error Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the/, , or registers. ." "0,1" bitfld.long 0x0 1. " SET ,Error Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of/, , or . ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x388++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x38C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x39C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRA,Queue Threshold A, for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q0 ,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q1 ,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q2 ,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q3 ,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x624++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRB,Queue Threshold B, for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q4 ,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q5 ,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q6 ,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q7 ,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x0 0. " EVTACTV ,DMA Event Active" "0,1" bitfld.long 0x0 1. " QEVTACTV ,QDMA Event Active" "0,1" textline " " bitfld.long 0x0 2. " TRACTV ,Transfer Request Active TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0,1" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4. " ACTV ,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals. The ACTV bit must remain high through the life of a:" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,reads return 0's" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " COMPACTV ,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " QUEACTV0 ,Queue 0 Active" "0,1" bitfld.long 0x0 17. " QUEACTV1 ,Queue 1 Active" "0,1" textline " " bitfld.long 0x0 18. " QUEACTV2 ,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0,1" bitfld.long 0x0 19. " QUEACTV3 ,Queue 3 Active" "0,1" textline " " bitfld.long 0x0 20. " QUEACTV4 ,Queue 4 Active" "0,1" bitfld.long 0x0 21. " QUEACTV5 ,Queue 5 Active" "0,1" textline " " bitfld.long 0x0 22. " QUEACTV6 ,Queue 6 Active" "0,1" bitfld.long 0x0 23. " QUEACTV7 ,Queue 7 Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,reads return 0's" group.byte 0x700++0x3 line.long 0x0 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 0.--5. " STRTEVT ,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " TYPE ,AET Event Type" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--13. " ENDINT ,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.tbyte 0x0 14.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " EN ,AET Enable" "0,1" group.byte 0x704++0x3 line.long 0x0 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x0 0. " STAT ,AET Status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x708++0x3 line.long 0x0 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x0 0. " CLR ,AET Clear commandCPU writes 0x0 has no effect. . CPU writes 0x1 to the CLR bit causes the tpcc_aet output signal and[0]STAT register to be cleared. ." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" hexmask.long 0x0 0.--31. 1. " FADDR ,Fault Address: 32-bit read-only status register containing the faulting address when a mMemory protection violation is detected. This register can only be cleared via theEDMA_TPCC_MPFCR." group.byte 0x804++0x3 line.long 0x0 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x0 0. " UXE ,User Execute Error" "0,1" bitfld.long 0x0 1. " UWE ,User Write Error" "0,1" textline " " bitfld.long 0x0 2. " URE ,User Read Error" "0,1" bitfld.long 0x0 3. " SXE ,Supervisor Execute Error" "0,1" textline " " bitfld.long 0x0 4. " SWE ,Supervisor Write Error" "0,1" bitfld.long 0x0 5. " SRE ,Supervisor Read Error" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--12. " FID ,Faulted ID: FID register contains valid info if any of the MP error bits (UXE, UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x808++0x3 line.long 0x0 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x0 0. " MPFCLR ,Fault Clear register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x80C++0x3 line.long 0x0 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0" "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x810++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x814++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x818++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x81C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x820++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x824++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x828++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x82C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x1000++0x3 line.long 0x0 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1004++0x3 line.long 0x0 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1008++0x3 line.long 0x0 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x100C++0x3 line.long 0x0 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1010++0x3 line.long 0x0 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1014++0x3 line.long 0x0 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1018++0x3 line.long 0x0 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x101C++0x3 line.long 0x0 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1020++0x3 line.long 0x0 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1024++0x3 line.long 0x0 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1028++0x3 line.long 0x0 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x102C++0x3 line.long 0x0 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1030++0x3 line.long 0x0 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1034++0x3 line.long 0x0 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1038++0x3 line.long 0x0 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x103C++0x3 line.long 0x0 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1040++0x3 line.long 0x0 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1044++0x3 line.long 0x0 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1050++0x3 line.long 0x0 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1054++0x3 line.long 0x0 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1058++0x3 line.long 0x0 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x105C++0x3 line.long 0x0 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1060++0x3 line.long 0x0 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1064++0x3 line.long 0x0 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1068++0x3 line.long 0x0 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x106C++0x3 line.long 0x0 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. . In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1070++0x3 line.long 0x0 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1074++0x3 line.long 0x0 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" bitfld.long 0x0 1. " SET ,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1080++0x3 line.long 0x0 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1084++0x3 line.long 0x0 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1088++0x3 line.long 0x0 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x108C++0x3 line.long 0x0 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1090++0x3 line.long 0x0 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1094++0x3 line.long 0x0 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2000++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2200++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2400++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2600++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2800++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2004++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2204++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2404++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2604++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2804++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2008++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2208++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2408++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2608++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2808++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x200C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x220C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x240C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x260C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x280C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2010++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2210++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2410++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2610++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2810++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2014++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2214++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2414++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2614++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2814++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2018++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2218++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2418++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2618++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2818++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x201C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x221C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x241C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x261C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x281C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2020++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2220++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2420++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2620++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2820++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2024++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2224++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2424++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2624++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2824++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2028++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2228++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2428++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2628++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2828++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x202C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x222C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x242C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x262C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x282C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2030++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2230++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2430++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2630++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2830++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2034++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2234++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2434++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2634++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2834++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2038++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2238++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2438++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2638++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2838++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x203C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x223C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x243C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x263C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x283C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2040++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2240++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2440++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2640++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2840++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2044++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2244++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2444++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2644++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2844++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2050++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2250++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2450++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2650++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2850++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2054++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2254++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2454++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2654++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2854++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2058++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2258++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2458++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2658++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2858++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x205C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x225C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x245C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x265C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x285C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2060++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2260++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2460++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2660++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2860++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2064++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2264++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2464++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2664++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2864++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2068++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2268++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2468++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2668++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2868++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x206C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x226C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x246C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x266C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x286C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2070++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2270++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2470++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2670++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2870++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2074++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2274++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2474++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2674++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2874++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2278++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2478++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2678++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2878++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2A78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2C78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2E78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2080++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2280++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2480++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2680++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2880++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2084++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2284++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2484++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2684++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2884++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2088++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2288++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2488++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2688++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2888++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x208C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x228C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x248C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x268C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x288C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2090++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2290++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2490++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2690++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2890++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2094++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2294++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2494++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2694++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2894++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2A94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2C94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2E94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x4000++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_0,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4020++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_1,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4040++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_2,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4060++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_3,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4080++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_4,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_5,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_6,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_7,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4100++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_8,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4120++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_9,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4140++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_10,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4160++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_11,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4180++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_12,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_13,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_14,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_15,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4200++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_16,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4220++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_17,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4240++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_18,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4260++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_19,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4280++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_20,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_21,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_22,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_23,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4300++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_24,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4320++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_25,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4340++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_26,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4360++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_27,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4380++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_28,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_29,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_30,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_31,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4400++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_32,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4420++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_33,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4440++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_34,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4460++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_35,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4480++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_36,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_37,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_38,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_39,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4500++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_40,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4520++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_41,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4540++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_42,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4560++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_43,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4580++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_44,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_45,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_46,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_47,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4600++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_48,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4620++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_49,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4640++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_50,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4660++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_51,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4680++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_52,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_53,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_54,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_55,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4700++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_56,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4720++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_57,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4740++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_58,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4760++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_59,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4780++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_60,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_61,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_62,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_63,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4800++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_64,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4820++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_65,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4840++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_66,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4860++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_67,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4880++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_68,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_69,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_70,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_71,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4900++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_72,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4920++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_73,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4940++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_74,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4960++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_75,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4980++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_76,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_77,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_78,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_79,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_80,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_81,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_82,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_83,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_84,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_85,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_86,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_87,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_88,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_89,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_90,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_91,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_92,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_93,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_94,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_95,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_96,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_97,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_98,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_99,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_100,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_101,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_102,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_103,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_104,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_105,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_106,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_107,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_108,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_109,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_110,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_111,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_112,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_113,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_114,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_115,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_116,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_117,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_118,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_119,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_120,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_121,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_122,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_123,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_124,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_125,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_126,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_127,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4004++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_0,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4024++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_1,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4044++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_2,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4064++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_3,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4084++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_4,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_5,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_6,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_7,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4104++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_8,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4124++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_9,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4144++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_10,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4164++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_11,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4184++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_12,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_13,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_14,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_15,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4204++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_16,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4224++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_17,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4244++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_18,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4264++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_19,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4284++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_20,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_21,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_22,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_23,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4304++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_24,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4324++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_25,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4344++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_26,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4364++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_27,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4384++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_28,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_29,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_30,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_31,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4404++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_32,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4424++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_33,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4444++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_34,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4464++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_35,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4484++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_36,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_37,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_38,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_39,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4504++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_40,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4524++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_41,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4544++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_42,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4564++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_43,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4584++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_44,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_45,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_46,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_47,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4604++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_48,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4624++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_49,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4644++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_50,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4664++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_51,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4684++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_52,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_53,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_54,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_55,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4704++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_56,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4724++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_57,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4744++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_58,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4764++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_59,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4784++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_60,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_61,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_62,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_63,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4804++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_64,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4824++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_65,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4844++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_66,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4864++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_67,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4884++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_68,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_69,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_70,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_71,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4904++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_72,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4924++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_73,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4944++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_74,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4964++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_75,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4984++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_76,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_77,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_78,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_79,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_80,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_81,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_82,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_83,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_84,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_85,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_86,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_87,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_88,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_89,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_90,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_91,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_92,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_93,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_94,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_95,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_96,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_97,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_98,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_99,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_100,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_101,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_102,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_103,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_104,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_105,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_106,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_107,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_108,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_109,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_110,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_111,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_112,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_113,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_114,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_115,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_116,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_117,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_118,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_119,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_120,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_121,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_122,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_123,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_124,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_125,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_126,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_127,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4008++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4028++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4048++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4068++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4088++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4108++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4128++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4148++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4168++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4188++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4208++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4228++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4248++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4268++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4288++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4308++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4328++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4348++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4368++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4388++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4408++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4428++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4448++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4468++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4488++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4508++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4528++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4548++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4568++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4588++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4608++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4628++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4648++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4668++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4688++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4708++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4728++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4748++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4768++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4788++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4808++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4828++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4848++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4868++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4888++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4908++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4928++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4948++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4968++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4988++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x400C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_0,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x402C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_1,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x404C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_2,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x406C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_3,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x408C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_4,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_5,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_6,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_7,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x410C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_8,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x412C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_9,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x414C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_10,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x416C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_11,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x418C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_12,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_13,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_14,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_15,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x420C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_16,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x422C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_17,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x424C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_18,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x426C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_19,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x428C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_20,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_21,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_22,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_23,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x430C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_24,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x432C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_25,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x434C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_26,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x436C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_27,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x438C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_28,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_29,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_30,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_31,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x440C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_32,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x442C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_33,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x444C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_34,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x446C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_35,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x448C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_36,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_37,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_38,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_39,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x450C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_40,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x452C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_41,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x454C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_42,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x456C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_43,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x458C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_44,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_45,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_46,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_47,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x460C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_48,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x462C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_49,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x464C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_50,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x466C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_51,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x468C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_52,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_53,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_54,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_55,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x470C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_56,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x472C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_57,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x474C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_58,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x476C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_59,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x478C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_60,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_61,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_62,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_63,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x480C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_64,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x482C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_65,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x484C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_66,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x486C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_67,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x488C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_68,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_69,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_70,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_71,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x490C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_72,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x492C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_73,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x494C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_74,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x496C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_75,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x498C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_76,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_77,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_78,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_79,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_80,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_81,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_82,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_83,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_84,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_85,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ACC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_86,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_87,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_88,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_89,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_90,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_91,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_92,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_93,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_94,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_95,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_96,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_97,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_98,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_99,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_100,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_101,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_102,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_103,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_104,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_105,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_106,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_107,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_108,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_109,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_110,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_111,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_112,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_113,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_114,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_115,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_116,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_117,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ECC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_118,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_119,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_120,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_121,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_122,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_123,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_124,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_125,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_126,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_127,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4010++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_0,EDMA_TPCC_BIDX_n_0" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4030++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_1,EDMA_TPCC_BIDX_n_1" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4050++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_2,EDMA_TPCC_BIDX_n_2" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4070++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_3,EDMA_TPCC_BIDX_n_3" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4090++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_4,EDMA_TPCC_BIDX_n_4" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_5,EDMA_TPCC_BIDX_n_5" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_6,EDMA_TPCC_BIDX_n_6" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_7,EDMA_TPCC_BIDX_n_7" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4110++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_8,EDMA_TPCC_BIDX_n_8" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4130++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_9,EDMA_TPCC_BIDX_n_9" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4150++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_10,EDMA_TPCC_BIDX_n_10" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4170++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_11,EDMA_TPCC_BIDX_n_11" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4190++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_12,EDMA_TPCC_BIDX_n_12" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_13,EDMA_TPCC_BIDX_n_13" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_14,EDMA_TPCC_BIDX_n_14" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_15,EDMA_TPCC_BIDX_n_15" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4210++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_16,EDMA_TPCC_BIDX_n_16" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4230++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_17,EDMA_TPCC_BIDX_n_17" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4250++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_18,EDMA_TPCC_BIDX_n_18" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4270++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_19,EDMA_TPCC_BIDX_n_19" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4290++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_20,EDMA_TPCC_BIDX_n_20" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_21,EDMA_TPCC_BIDX_n_21" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_22,EDMA_TPCC_BIDX_n_22" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_23,EDMA_TPCC_BIDX_n_23" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4310++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_24,EDMA_TPCC_BIDX_n_24" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4330++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_25,EDMA_TPCC_BIDX_n_25" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4350++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_26,EDMA_TPCC_BIDX_n_26" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4370++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_27,EDMA_TPCC_BIDX_n_27" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4390++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_28,EDMA_TPCC_BIDX_n_28" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_29,EDMA_TPCC_BIDX_n_29" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_30,EDMA_TPCC_BIDX_n_30" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_31,EDMA_TPCC_BIDX_n_31" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4410++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_32,EDMA_TPCC_BIDX_n_32" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4430++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_33,EDMA_TPCC_BIDX_n_33" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4450++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_34,EDMA_TPCC_BIDX_n_34" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4470++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_35,EDMA_TPCC_BIDX_n_35" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4490++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_36,EDMA_TPCC_BIDX_n_36" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_37,EDMA_TPCC_BIDX_n_37" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_38,EDMA_TPCC_BIDX_n_38" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_39,EDMA_TPCC_BIDX_n_39" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4510++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_40,EDMA_TPCC_BIDX_n_40" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4530++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_41,EDMA_TPCC_BIDX_n_41" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4550++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_42,EDMA_TPCC_BIDX_n_42" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4570++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_43,EDMA_TPCC_BIDX_n_43" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4590++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_44,EDMA_TPCC_BIDX_n_44" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_45,EDMA_TPCC_BIDX_n_45" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_46,EDMA_TPCC_BIDX_n_46" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_47,EDMA_TPCC_BIDX_n_47" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4610++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_48,EDMA_TPCC_BIDX_n_48" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4630++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_49,EDMA_TPCC_BIDX_n_49" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4650++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_50,EDMA_TPCC_BIDX_n_50" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4670++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_51,EDMA_TPCC_BIDX_n_51" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4690++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_52,EDMA_TPCC_BIDX_n_52" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_53,EDMA_TPCC_BIDX_n_53" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_54,EDMA_TPCC_BIDX_n_54" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_55,EDMA_TPCC_BIDX_n_55" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4710++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_56,EDMA_TPCC_BIDX_n_56" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4730++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_57,EDMA_TPCC_BIDX_n_57" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4750++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_58,EDMA_TPCC_BIDX_n_58" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4770++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_59,EDMA_TPCC_BIDX_n_59" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4790++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_60,EDMA_TPCC_BIDX_n_60" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_61,EDMA_TPCC_BIDX_n_61" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_62,EDMA_TPCC_BIDX_n_62" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_63,EDMA_TPCC_BIDX_n_63" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4810++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_64,EDMA_TPCC_BIDX_n_64" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4830++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_65,EDMA_TPCC_BIDX_n_65" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4850++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_66,EDMA_TPCC_BIDX_n_66" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4870++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_67,EDMA_TPCC_BIDX_n_67" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4890++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_68,EDMA_TPCC_BIDX_n_68" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_69,EDMA_TPCC_BIDX_n_69" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_70,EDMA_TPCC_BIDX_n_70" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_71,EDMA_TPCC_BIDX_n_71" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4910++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_72,EDMA_TPCC_BIDX_n_72" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4930++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_73,EDMA_TPCC_BIDX_n_73" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4950++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_74,EDMA_TPCC_BIDX_n_74" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4970++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_75,EDMA_TPCC_BIDX_n_75" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4990++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_76,EDMA_TPCC_BIDX_n_76" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_77,EDMA_TPCC_BIDX_n_77" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_78,EDMA_TPCC_BIDX_n_78" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_79,EDMA_TPCC_BIDX_n_79" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_80,EDMA_TPCC_BIDX_n_80" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_81,EDMA_TPCC_BIDX_n_81" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_82,EDMA_TPCC_BIDX_n_82" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_83,EDMA_TPCC_BIDX_n_83" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_84,EDMA_TPCC_BIDX_n_84" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_85,EDMA_TPCC_BIDX_n_85" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_86,EDMA_TPCC_BIDX_n_86" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_87,EDMA_TPCC_BIDX_n_87" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_88,EDMA_TPCC_BIDX_n_88" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_89,EDMA_TPCC_BIDX_n_89" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_90,EDMA_TPCC_BIDX_n_90" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_91,EDMA_TPCC_BIDX_n_91" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_92,EDMA_TPCC_BIDX_n_92" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_93,EDMA_TPCC_BIDX_n_93" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_94,EDMA_TPCC_BIDX_n_94" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_95,EDMA_TPCC_BIDX_n_95" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_96,EDMA_TPCC_BIDX_n_96" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_97,EDMA_TPCC_BIDX_n_97" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_98,EDMA_TPCC_BIDX_n_98" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_99,EDMA_TPCC_BIDX_n_99" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_100,EDMA_TPCC_BIDX_n_100" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_101,EDMA_TPCC_BIDX_n_101" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_102,EDMA_TPCC_BIDX_n_102" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_103,EDMA_TPCC_BIDX_n_103" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_104,EDMA_TPCC_BIDX_n_104" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_105,EDMA_TPCC_BIDX_n_105" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_106,EDMA_TPCC_BIDX_n_106" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_107,EDMA_TPCC_BIDX_n_107" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_108,EDMA_TPCC_BIDX_n_108" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_109,EDMA_TPCC_BIDX_n_109" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_110,EDMA_TPCC_BIDX_n_110" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_111,EDMA_TPCC_BIDX_n_111" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_112,EDMA_TPCC_BIDX_n_112" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_113,EDMA_TPCC_BIDX_n_113" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_114,EDMA_TPCC_BIDX_n_114" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_115,EDMA_TPCC_BIDX_n_115" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_116,EDMA_TPCC_BIDX_n_116" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_117,EDMA_TPCC_BIDX_n_117" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4ED0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_118,EDMA_TPCC_BIDX_n_118" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_119,EDMA_TPCC_BIDX_n_119" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_120,EDMA_TPCC_BIDX_n_120" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_121,EDMA_TPCC_BIDX_n_121" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_122,EDMA_TPCC_BIDX_n_122" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_123,EDMA_TPCC_BIDX_n_123" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_124,EDMA_TPCC_BIDX_n_124" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_125,EDMA_TPCC_BIDX_n_125" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_126,EDMA_TPCC_BIDX_n_126" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_127,EDMA_TPCC_BIDX_n_127" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4014++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4034++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4054++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4074++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4094++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4114++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4134++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4154++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4174++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4194++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4214++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4234++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4254++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4274++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4294++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4314++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4334++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4354++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4374++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4394++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4414++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4434++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4454++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4474++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4494++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4514++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4534++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4554++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4574++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4594++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4614++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4634++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4654++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4674++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4694++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4714++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4734++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4754++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4774++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4794++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4814++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4834++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4854++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4874++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4894++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4914++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4934++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4954++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4974++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4994++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4ED4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4018++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4038++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4058++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4078++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4098++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4118++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4138++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4158++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4178++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4198++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4218++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4238++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4258++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4278++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4298++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4318++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4338++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4358++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4378++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4398++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4418++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4438++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4458++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4478++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4498++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4518++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4538++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4558++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4578++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4598++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4618++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4638++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4658++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4678++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4698++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4718++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4738++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4758++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4778++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4798++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4818++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4838++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4858++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4878++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4898++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4918++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4938++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4958++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4978++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4998++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4ED8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x401C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x403C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x405C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x407C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x409C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x411C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x413C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x415C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x417C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x419C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x421C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x423C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x425C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x427C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x429C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x431C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x433C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x435C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x437C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x439C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x441C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x443C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x445C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x447C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x449C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x451C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x453C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x455C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x457C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x459C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x461C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x463C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x465C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x467C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x469C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x471C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x473C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x475C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x477C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x479C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x481C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x483C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x485C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x487C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x489C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x491C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x493C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x495C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x497C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x499C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ABC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ADC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4AFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE4_EDMA_TPCC" base ad:0x423A0000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPCC_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPCC_CCCFG,CC Configuration Register" bitfld.long 0x0 0.--2. " NUMDMACH ,Number of DMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--6. " NUMQDMACH ,Number of QDMA Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 8.--10. " NUMINTCH ,Number of Interrupt Channels" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 12.--14. " NUMPAENTRY ,Number of PaRAM entries" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 16.--18. " NUMTC ,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 20.--21. " NUMREGN ,Number of MP and Shadow regions" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 24. " CHMAPEXIST ,Channel Mapping Existence" "0,1" bitfld.long 0x0 25. " MPEXIST ,Memory Protection Existence" "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reads return 0's" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xFC++0x3 line.long 0x0 "EDMA_TPCC_CLKGDIS,Auto Clock Gate Disable" bitfld.long 0x0 0. " CLKGDIS ,Auto Clock Gate Disable" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_0,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_1,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_2,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_3,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_4,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x114++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_5,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x118++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_6,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x11C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_7,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_8,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_9,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_10,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_11,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_12,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_13,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x138++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_14,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x13C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_15,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_16,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x144++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_17,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x148++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_18,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x14C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_19,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x150++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_20,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x154++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_21,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x158++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_22,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x15C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_23,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x160++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_24,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x164++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_25,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x168++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_26,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x16C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_27,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x170++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_28,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x174++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_29,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x178++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_30,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x17C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_31,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x180++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_32,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_33,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_34,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_35,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_36,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x194++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_37,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x198++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_38,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x19C++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_39,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_40,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_41,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1A8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_42,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1AC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_43,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_44,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_45,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1B8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_46,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1BC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_47,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_48,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_49,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1C8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_50,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1CC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_51,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_52,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_53,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1D8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_54,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1DC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_55,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_56,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_57,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1E8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_58,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1EC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_59,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F0++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_60,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F4++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_61,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1F8++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_62,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x1FC++0x3 line.long 0x0 "EDMA_TPCC_DCHMAPN_m_63,DMA Channel N Mapping Register" bitfld.long 0x0 0.--4. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for DMA Channel N." textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_0,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_1,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_2,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_3,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_4,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_5,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_6,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "EDMA_TPCC_QCHMAPN_j_7,QDMA Channel N Mapping Register" bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 2.--4. " TRWORD ,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY. A write to the trigger word results in a QDMA Event being recognized." "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PaRAM Entry number for QDMA Channel N." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_0,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_1,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x248++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_2,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_3,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_4,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x254++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_5,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_6,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPCC_DMAQNUMN_k_7,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel." bitfld.long 0x0 0.--2. " E0 ,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x260++0x3 line.long 0x0 "EDMA_TPCC_QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel." bitfld.long 0x0 0.--2. " E0 ,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " E1 ,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " E2 ,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " E3 ,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " E4 ,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " E5 ,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " E6 ,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " E7 ,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x280++0x3 line.long 0x0 "EDMA_TPCC_QUETCMAP,Queue to TC Mapping" bitfld.long 0x0 0.--2. " TCNUMQ0 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " TCNUMQ1 ,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPCC_QUEPRI,Queue Priority" bitfld.long 0x0 0.--2. " PRIQ0 ,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " PRIQ1 ,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs. Sets the priority used for TC read and write commands." "0,1,2,3,4,5,6,7" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x300++0x3 line.long 0x0 "EDMA_TPCC_EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed #31" "0,1" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPCC_EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced. Chained events (CER), Set Events (ESR), and normal events (ER) are treated individually. If any bit in the EMR register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E32 ,Event Missed #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed #63" "0,1" group.byte 0x308++0x3 line.long 0x0 "EDMA_TPCC_EMCR,Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect.. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event Missed Clear #8" "0,1" bitfld.long 0x0 9. " E9 ,Event Missed Clear #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event Missed Clear #10" "0,1" bitfld.long 0x0 11. " E11 ,Event Missed Clear #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event Missed Clear #12" "0,1" bitfld.long 0x0 13. " E13 ,Event Missed Clear #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event Missed Clear #14" "0,1" bitfld.long 0x0 15. " E15 ,Event Missed Clear #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event Missed Clear #16" "0,1" bitfld.long 0x0 17. " E17 ,Event Missed Clear #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event Missed Clear #18" "0,1" bitfld.long 0x0 19. " E19 ,Event Missed Clear #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event Missed Clear #20" "0,1" bitfld.long 0x0 21. " E21 ,Event Missed Clear #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event Missed Clear #22" "0,1" bitfld.long 0x0 23. " E23 ,Event Missed Clear #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event Missed Clear #24" "0,1" bitfld.long 0x0 25. " E25 ,Event Missed Clear #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event Missed Clear #26" "0,1" bitfld.long 0x0 27. " E27 ,Event Missed Clear #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event Missed Clear #28" "0,1" bitfld.long 0x0 29. " E29 ,Event Missed Clear #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event Missed Clear #30" "0,1" bitfld.long 0x0 31. " E31 ,Event Missed Clear #31" "0,1" group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPCC_EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E32 ,Event Missed Clear #32" "0,1" bitfld.long 0x0 1. " E33 ,Event Missed Clear #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event Missed Clear #34" "0,1" bitfld.long 0x0 3. " E35 ,Event Missed Clear #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event Missed Clear #36" "0,1" bitfld.long 0x0 5. " E37 ,Event Missed Clear #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event Missed Clear #38" "0,1" bitfld.long 0x0 7. " E39 ,Event Missed Clear #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event Missed Clear #40" "0,1" bitfld.long 0x0 9. " E41 ,Event Missed Clear #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event Missed Clear #42" "0,1" bitfld.long 0x0 11. " E43 ,Event Missed Clear #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event Missed Clear #44" "0,1" bitfld.long 0x0 13. " E45 ,Event Missed Clear #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event Missed Clear #46" "0,1" bitfld.long 0x0 15. " E47 ,Event Missed Clear #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event Missed Clear #48" "0,1" bitfld.long 0x0 17. " E49 ,Event Missed Clear #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event Missed Clear #50" "0,1" bitfld.long 0x0 19. " E51 ,Event Missed Clear #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event Missed Clear #52" "0,1" bitfld.long 0x0 21. " E53 ,Event Missed Clear #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event Missed Clear #54" "0,1" bitfld.long 0x0 23. " E55 ,Event Missed Clear #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event Missed Clear #56" "0,1" bitfld.long 0x0 25. " E57 ,Event Missed Clear #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event Missed Clear #58" "0,1" bitfld.long 0x0 27. " E59 ,Event Missed Clear #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event Missed Clear #60" "0,1" bitfld.long 0x0 29. " E61 ,Event Missed Clear #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event Missed Clear #62" "0,1" bitfld.long 0x0 31. " E63 ,Event Missed Clear #63" "0,1" group.byte 0x310++0x3 line.long 0x0 "EDMA_TPCC_QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced. If any bit in the register is set (and all errors (including / ) were previously clear), then an error will be signaled with TPCC error interrupt." bitfld.long 0x0 0. " E0 ,Event Missed #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x314++0x3 line.long 0x0 "EDMA_TPCC_QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the.En bit causes the .En bit to be cleared. CPU write of '0' has no effect. All error bits must be cleared before additional error interrupts will be asserted by CC." bitfld.long 0x0 0. " E0 ,Event Missed Clear #0" "0,1" bitfld.long 0x0 1. " E1 ,Event Missed Clear #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event Missed Clear #2" "0,1" bitfld.long 0x0 3. " E3 ,Event Missed Clear #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event Missed Clear #4" "0,1" bitfld.long 0x0 5. " E5 ,Event Missed Clear #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event Missed Clear #6" "0,1" bitfld.long 0x0 7. " E7 ,Event Missed Clear #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x318++0x3 line.long 0x0 "EDMA_TPCC_CCERR,CC Error Register" bitfld.long 0x0 0. " QTHRXCD0 ,Queue Threshold Error for Q0:QTHRXCD0 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Queue Threshold Error for Q1QTHRXCD1 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Queue Threshold Error for Q2QTHRXCD2 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Queue Threshold Error for Q3QTHRXCD3 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Queue Threshold Error for Q4QTHRXCD4 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Queue Threshold Error for Q5QTHRXCD5 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Queue Threshold Error for Q6QTHRXCD6 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Queue Threshold Error for Q7QTHRXCD7 can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors (including /) were previously clear), then an error will be signaled with the TPCC error interrupt. ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Transfer Completion Code ErrorTCERR can be cleared by writing a '1' to corresponding bit in register. If any bit in the register is set (and all errors were previously clear), then an error will be signaled with TPCC error interrupt. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x31C++0x3 line.long 0x0 "EDMA_TPCC_CCERRCLR,CC Error Clear Register" bitfld.long 0x0 0. " QTHRXCD0 ,Clear error forEDMA_TPCC_CCERR[0] QTHRXCD0Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT0.WM, QSTAT0.THRXCD,[0] QTHRXCD0 ." "0,1" bitfld.long 0x0 1. " QTHRXCD1 ,Clear error forEDMA_TPCC_CCERR[1] QTHRXCD1Write 0x1 to clear the values of QSTAT1.WM, QSTAT1.THRXCD,[1] QTHRXCD1 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 2. " QTHRXCD2 ,Clear error forEDMA_TPCC_CCERR[2] QTHRXCD2Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT2.WM, QSTAT2.THRXCD,[2] QTHRXCD2 ." "0,1" bitfld.long 0x0 3. " QTHRXCD3 ,Clear error forEDMA_TPCC_CCERR[3] QTHRXCD3Write 0x1 to clear the values of QSTAT3.WM, QSTAT3.THRXCD,[3] QTHRXCD3 . Write 0x0 have no affect. ." "0,1" textline " " bitfld.long 0x0 4. " QTHRXCD4 ,Clear error forEDMA_TPCC_CCERR[4] QTHRXCD4:Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT4.WM, QSTAT4.THRXCD,[4] QTHRXCD4 ." "0,1" bitfld.long 0x0 5. " QTHRXCD5 ,Clear error forEDMA_TPCC_CCERR[5] QTHRXCD5Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT5.WM, QSTAT5.THRXCD,[5]QTHRXCD5 ." "0,1" textline " " bitfld.long 0x0 6. " QTHRXCD6 ,Clear error forEDMA_TPCC_CCERR[6] QTHRXCD6Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT6.WM, QSTAT6.THRXCD,[6]QTHRXCD6 ." "0,1" bitfld.long 0x0 7. " QTHRXCD7 ,Clear error forEDMA_TPCC_CCERR[7]QTHRXCD7Write 0x0 have no affect. . Write 0x1 to clear the values of QSTAT7.WM, QSTAT7.THRXCD,[7] QTHRXCD7 ." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ,Reserved" bitfld.long 0x0 16. " TCERR ,Clear Error forEDMA_TPCC_CCERR[16] TR.Write 0x1 to clear the value of[16] TCERR. . Write 0x0 have no affect. ." "0,1" textline " " hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x320++0x3 line.long 0x0 "EDMA_TPCC_EEVAL,Error Eval Register" bitfld.long 0x0 0. " EVAL ,Error Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the/, , or registers. The CPU must also write 0x1 after any error interrupts are serviced in order for subsequent interrupts to be asserted. ." "0,1" bitfld.long 0x0 1. " SET ,Error Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of/, , or . ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x380++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_0,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x384++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_1,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x388++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_2,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x38C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_3,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x390++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_4,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x394++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_5,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x398++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_6,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x39C++0x3 line.long 0x0 "EDMA_TPCC_QRAEN_k_7,QDMA Region Access enable for bit N in Region M: En = 0 : Accesses via Region M address space to Bit N in any QDMA Channel Register are not allowed. Reads will return 'b0 on Bit N and writes will not modify the state of bit N. Enabled interrupt bits for bit N do not contribute to the generation of the TPCC region M interrupt. En = 1 : Accesses via Region M address space to Bit N in any QDMA Channel Register are allowed. Reads will return the value from Bit N and writes will modify the state of bit N. Enabled interrupt bits for bit N do contribute to the generation of the TPCC region n interrupt." bitfld.long 0x0 0. " E0 ,QDMA Region Access enable for Region M, bit #0" "0,1" bitfld.long 0x0 1. " E1 ,QDMA Region Access enable for Region M, bit #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,QDMA Region Access enable for Region M, bit #2" "0,1" bitfld.long 0x0 3. " E3 ,QDMA Region Access enable for Region M, bit #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,QDMA Region Access enable for Region M, bit #4" "0,1" bitfld.long 0x0 5. " E5 ,QDMA Region Access enable for Region M, bit #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,QDMA Region Access enable for Region M, bit #6" "0,1" bitfld.long 0x0 7. " E7 ,QDMA Region Access enable for Region M, bit #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x600++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_0,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x604++0x3 line.long 0x0 "EDMA_TPCC_QSTATN_i_1,QSTATn Register Set" bitfld.long 0x0 0.--3. " STRTPTR ,Start Pointer: Represents the offset to the head entry of QueueN, in units of *entries*. Always enabled. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--12. " NUMVAL ,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant. Always enabled. Legal values: = 0x0 (empty) to 0x10 (full)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " WM ,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared. QSTATn. WM is cleared via EDMA_TPCC_CCERR.WMCLRn bit. Legal values:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " THRXCD ,Threshold ExceededTHRXCD is cleared via. WMCLRn bit. ." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x620++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRA,Queue Threshold A, for Q[3:0]:.QTHRXCDn and QSTATn[24] THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by .Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q0 ,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q1 ,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q2 ,Queue Threshold for Q2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q3 ,Queue Threshold for Q3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x624++0x3 line.long 0x0 "EDMA_TPCC_QWMTHRB,Queue Threshold B, for Q[7:4]:.QTHRXCDn and QSTATn[24]THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn[12:8] NUMVAL) equals or exceeds the value specified by QWMTHRB.Qn. Legal values = 0x0 (ever used?) to 0x10 (ever full?) A value of 0x11 disables threshold errors." bitfld.long 0x0 0.--4. " Q4 ,Queue Threshold for Q4 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " Q5 ,Queue Threshold for Q5 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--20. " Q6 ,Queue Threshold for Q6 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--23. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--28. " Q7 ,Queue Threshold for Q7 value (unused in the context of IVAHD)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x640++0x3 line.long 0x0 "EDMA_TPCC_CCSTAT,CC Status Register" bitfld.long 0x0 0. " EVTACTV ,DMA Event Active" "0,1" bitfld.long 0x0 1. " QEVTACTV ,QDMA Event Active" "0,1" textline " " bitfld.long 0x0 2. " TRACTV ,Transfer Request Active TRACTV = 0 : Transfer Request processing/submission logic is inactive. TRACTV = 1 : Transfer Request processing/submission logic is active." "0,1" bitfld.long 0x0 3. " RESERVED ,reads return 0's" "0,1" textline " " bitfld.long 0x0 4. " ACTV ,Channel Controller Active Channel Controller Active is a logical-OR of each of the *ACTV signals. The ACTV bit must remain high through the life of a:" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,reads return 0's" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--13. " COMPACTV ,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC. The counter increments when a TR is submitted with TCINTEN or TCCHEN set to '1'. The counter decrements for every valid completion code received from any of the external TCs. The CC will not service new TRs if COMPACTV count is already at the limit.... ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " QUEACTV0 ,Queue 0 Active" "0,1" bitfld.long 0x0 17. " QUEACTV1 ,Queue 1 Active" "0,1" textline " " bitfld.long 0x0 18. " QUEACTV2 ,Queue 2 Active QUEACTV2 = 0 : No Evts are queued in Q2. QUEACTV2 = 1 : At least one TR is queued in Q2." "0,1" bitfld.long 0x0 19. " QUEACTV3 ,Queue 3 Active" "0,1" textline " " bitfld.long 0x0 20. " QUEACTV4 ,Queue 4 Active" "0,1" bitfld.long 0x0 21. " QUEACTV5 ,Queue 5 Active" "0,1" textline " " bitfld.long 0x0 22. " QUEACTV6 ,Queue 6 Active" "0,1" bitfld.long 0x0 23. " QUEACTV7 ,Queue 7 Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,reads return 0's" group.byte 0x700++0x3 line.long 0x0 "EDMA_TPCC_AETCTL,Advanced Event Trigger Control" bitfld.long 0x0 0.--5. " STRTEVT ,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " TYPE ,AET Event Type" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--13. " ENDINT ,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.tbyte 0x0 14.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " EN ,AET Enable" "0,1" group.byte 0x704++0x3 line.long 0x0 "EDMA_TPCC_AETSTAT,Advanced Event Trigger Stat" bitfld.long 0x0 0. " STAT ,AET Status" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x708++0x3 line.long 0x0 "EDMA_TPCC_AETCMD,AET Command" bitfld.long 0x0 0. " CLR ,AET Clear commandCPU writes 0x0 has no effect. . CPU writes 0x1 to the CLR bit causes the tpcc_aet output signal and[0]STAT register to be cleared. ." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x800++0x3 line.long 0x0 "EDMA_TPCC_MPFAR,MMemory Protection Fault Address" hexmask.long 0x0 0.--31. 1. " FADDR ,Fault Address: 32-bit read-only status register containing the faulting address when a mMemory protection violation is detected. This register can only be cleared via theEDMA_TPCC_MPFCR." group.byte 0x804++0x3 line.long 0x0 "EDMA_TPCC_MPFSR,Memory Protection Fault Status Register" bitfld.long 0x0 0. " UXE ,User Execute Error" "0,1" bitfld.long 0x0 1. " UWE ,User Write Error" "0,1" textline " " bitfld.long 0x0 2. " URE ,User Read Error" "0,1" bitfld.long 0x0 3. " SXE ,Supervisor Execute Error" "0,1" textline " " bitfld.long 0x0 4. " SWE ,Supervisor Write Error" "0,1" bitfld.long 0x0 5. " SRE ,Supervisor Read Error" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9.--12. " FID ,Faulted ID: FID register contains valid info if any of the MP error bits (UXE, UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been detected.) The FID field contains the VBus PrivID for the specific request/requestor that resulted in a MP Error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x808++0x3 line.long 0x0 "EDMA_TPCC_MPFCR,Memory Protection Fault Command Register" bitfld.long 0x0 0. " MPFCLR ,Fault Clear register" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x80C++0x3 line.long 0x0 "EDMA_TPCC_MPPAG,Memory Protection Page Attribute for Global registers" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0" "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x810++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_0,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x814++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_1,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x818++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_2,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x81C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_3,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x820++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_4,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x824++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_5,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x828++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_6,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x82C++0x3 line.long 0x0 "EDMA_TPCC_MPPAN_k_7,P Permission Attribute for DMA Region n" bitfld.long 0x0 0. " UX ,User Execute permission" "0,1" bitfld.long 0x0 1. " UW ,User Write permission" "0,1" textline " " bitfld.long 0x0 2. " UR ,User Read permission" "0,1" bitfld.long 0x0 3. " SX ,Supervisor Execute permission" "0,1" textline " " bitfld.long 0x0 4. " SW ,Supervisor Write permission" "0,1" bitfld.long 0x0 5. " SR ,Supervisor Read permission" "0,1" textline " " bitfld.long 0x0 6.--8. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 9. " EXT ,External Allowed ID" "0,1" textline " " bitfld.long 0x0 10. " AID0 ,Allowed ID 0: AID0 = 0 : VBus requests with PrivID == '0' are not allowed regardless of permission settings (UW, UR, SW, SR). AID0 = 1 : VBus requests with PrivID == '0' are permitted if access type is allowed as defined by permission settings (UW, UR, SW, SR)." "0,1" bitfld.long 0x0 11. " AID1 ,Allowed ID 1" "0,1" textline " " bitfld.long 0x0 12. " AID2 ,Allowed ID 2" "0,1" bitfld.long 0x0 13. " AID3 ,Allowed ID 3" "0,1" textline " " bitfld.long 0x0 14. " AID4 ,Allowed ID 4" "0,1" bitfld.long 0x0 15. " AID5 ,Allowed ID 5" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x1000++0x3 line.long 0x0 "EDMA_TPCC_ER,Event Register: If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1004++0x3 line.long 0x0 "EDMA_TPCC_ERH,Event Register (High Part): If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1008++0x3 line.long 0x0 "EDMA_TPCC_ECR,Event Clear Register: CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x100C++0x3 line.long 0x0 "EDMA_TPCC_ECRH,Event Clear Register (High Part): CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1010++0x3 line.long 0x0 "EDMA_TPCC_ESR,Event Set Register: CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1014++0x3 line.long 0x0 "EDMA_TPCC_ESRH,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1018++0x3 line.long 0x0 "EDMA_TPCC_CER,Chained Event Register: If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x101C++0x3 line.long 0x0 "EDMA_TPCC_CERH,Chained Event Register (High Part): If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1020++0x3 line.long 0x0 "EDMA_TPCC_EER,Event Enable Register: Enables DMA transfers for.En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1024++0x3 line.long 0x0 "EDMA_TPCC_EERH,Event Enable Register (High Part): Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). Note that if a bit is set in .En while .En is disabled, no action is taken. If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1028++0x3 line.long 0x0 "EDMA_TPCC_EECR,Event Enable Clear Register CPU writes of '1' to the .En bit causes the .En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x102C++0x3 line.long 0x0 "EDMA_TPCC_EECRH,Event Enable Clear Register (High Part) CPU writes of '1' to the .En bit causes the EERH.En bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1030++0x3 line.long 0x0 "EDMA_TPCC_EESR,Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1034++0x3 line.long 0x0 "EDMA_TPCC_EESRH,Event Enable Set Register (High Part) CPU writes of '1' to the .En bit causes the .En bit to be set. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1038++0x3 line.long 0x0 "EDMA_TPCC_SER,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x103C++0x3 line.long 0x0 "EDMA_TPCC_SERH,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1040++0x3 line.long 0x0 "EDMA_TPCC_SECR,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x1044++0x3 line.long 0x0 "EDMA_TPCC_SECRH,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '1' to the .En bit clears the register. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x1050++0x3 line.long 0x0 "EDMA_TPCC_IER,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1054++0x3 line.long 0x0 "EDMA_TPCC_IERH,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. . In = 0: .In is NOT enabled for interrupts. . In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1058++0x3 line.long 0x0 "EDMA_TPCC_IECR,Int Enable Clear Register CPU writes of '1' to the .In bit causes the .In bit to be cleared. CPU writes of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x105C++0x3 line.long 0x0 "EDMA_TPCC_IECRH,Int Enable Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1060++0x3 line.long 0x0 "EDMA_TPCC_IESR,Int Enable Set Register CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1064++0x3 line.long 0x0 "EDMA_TPCC_IESRH,Int Enable Set Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1068++0x3 line.long 0x0 "EDMA_TPCC_IPR,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x106C++0x3 line.long 0x0 "EDMA_TPCC_IPRH,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. . In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1070++0x3 line.long 0x0 "EDMA_TPCC_ICR,Interrupt Clear Register CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x1074++0x3 line.long 0x0 "EDMA_TPCC_ICRH,Interrupt Clear Register (High Part) CPU write of '1' to the .In bit causes the .In bit to be cleared. CPU write of '0' has no effect. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x1078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" bitfld.long 0x0 1. " SET ,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). CPU write of '0' has no effect." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x1080++0x3 line.long 0x0 "EDMA_TPCC_QER,QDMA Event Register: If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1084++0x3 line.long 0x0 "EDMA_TPCC_QEER,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1, The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1088++0x3 line.long 0x0 "EDMA_TPCC_QEECR,QDMA Event Enable Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x108C++0x3 line.long 0x0 "EDMA_TPCC_QEESR,QDMA Event Enable Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1090++0x3 line.long 0x0 "EDMA_TPCC_QSER,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1094++0x3 line.long 0x0 "EDMA_TPCC_QSECR,QDMA Secondary Event Clear Register The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields. CPU write of '0' has no effect.." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2000++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_0,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2200++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_1,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2400++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_2,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2600++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_3,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2800++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_4,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_5,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_6,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E00++0x3 line.long 0x0 "EDMA_TPCC_ER_RN_k_7,Event Register If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of .En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2004++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_0,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2204++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_1,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2404++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_2,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2604++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_3,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2804++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_4,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_5,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_6,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E04++0x3 line.long 0x0 "EDMA_TPCC_ERH_RN_k_7,Event Register (High Part) If .En bit is set and the .En bit is also set, then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when the input event #n transitions from inactive (low) to active (high), regardless of the state of EERH.En bit. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and a new inactive to active transition is detected on the input event #n input AND the corresponding bit in the register is set, then the corresponding bit in the Event Missed Register is set. Event N can be cleared via sw by writing a '1' to the pseudo-register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2008++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_0,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2208++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_1,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2408++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_2,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2608++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_3,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2808++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_4,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_5,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_6,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E08++0x3 line.long 0x0 "EDMA_TPCC_ECR_RN_k_7,Event Clear Register CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x200C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_0,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x220C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_1,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x240C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_2,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x260C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_3,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x280C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_4,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_5,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_6,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E0C++0x3 line.long 0x0 "EDMA_TPCC_ECRH_RN_k_7,Event Clear Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be cleared. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2010++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_0,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2210++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_1,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2410++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_2,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2610++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_3,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2810++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_4,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_5,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_6,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E10++0x3 line.long 0x0 "EDMA_TPCC_ESR_RN_k_7,Event Set Register CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2014++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_0,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2214++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_1,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2414++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_2,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2614++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_3,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2814++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_4,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_5,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_6,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E14++0x3 line.long 0x0 "EDMA_TPCC_ESRH_RN_k_7,Event Set Register (High Part) CPU write of '1' to the .En bit causes the .En bit to be set. CPU write of '0' has no effect." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2018++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_0,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2218++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_1,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2418++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_2,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2618++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_3,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2818++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_4,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_5,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_6,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E18++0x3 line.long 0x0 "EDMA_TPCC_CER_RN_k_7,Chained Event Register If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x201C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_0,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x221C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_1,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x241C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_2,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x261C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_3,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x281C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_4,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_5,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_6,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E1C++0x3 line.long 0x0 "EDMA_TPCC_CERH_RN_k_7,Chained Event Register (High Part) If .En bit is set (regardless of state of .En), then the corresponding DMA channel is prioritized vs. other pending DMA events for submission to the TC. .En bit is set when a chaining completion code is returned from one of the 3PTCs via the completion interface, or is generated internally via Early Completion path. .En bit is cleared when the corresponding event is prioritized and serviced. If the .En bit is already set and the corresponding chaining completion code is returned from the TC, then the corresponding bit in the Event Missed Register is set. .En cannot be set or cleared via software." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2020++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_0,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2220++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_1,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2420++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_2,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2620++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_3,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2820++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_4,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_5,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_6,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E20++0x3 line.long 0x0 "EDMA_TPCC_EER_RN_k_7,Event Enable Register Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2024++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_0,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2224++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_1,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2424++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_2,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2624++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_3,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2824++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_4,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_5,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_6,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E24++0x3 line.long 0x0 "EDMA_TPCC_EERH_RN_k_7,Event Enable Register (High Part) Enables DMA transfers for .En pending events. .En is set based on externally asserted events (via tpcc_eventN_pi). This register has no effect on Chained Event Register () or Event Set Register (). NOTE: If a bit is set in If .En is enabled at a later point (and .En has not been cleared via SW) then the event will be recognized as a valid 'TR Sync' .En is not directly writeable. Events can be enabled via writes to and can be disabled via writes to register. .En = 0: .En is not enabled to trigger DMA transfers. .En = 1: .En is enabled to trigger DMA transfers." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2028++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_0,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2228++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_1,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2428++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_2,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2628++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_3,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2828++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_4,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_5,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_6,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E28++0x3 line.long 0x0 "EDMA_TPCC_EECR_RN_k_7,Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x202C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_0,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x222C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_1,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x242C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_2,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x262C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_3,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x282C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_4,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_5,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_6,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E2C++0x3 line.long 0x0 "EDMA_TPCC_EECRH_RN_k_7,Event Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2030++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_0,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2230++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_1,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2430++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_2,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2630++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_3,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2830++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_4,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_5,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_6,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E30++0x3 line.long 0x0 "EDMA_TPCC_EESR_RN_k_7,Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2034++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_0,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2234++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_1,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2434++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_2,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2634++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_3,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2834++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_4,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_5,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_6,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E34++0x3 line.long 0x0 "EDMA_TPCC_EESRH_RN_k_7,Event Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2038++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_0,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2238++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_1,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2438++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_2,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2638++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_3,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2838++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_4,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_5,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_6,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E38++0x3 line.long 0x0 "EDMA_TPCC_SER_RN_k_7,Secondary Event Register The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x203C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_0,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x223C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_1,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x243C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_2,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x263C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_3,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x283C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_4,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_5,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_6,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E3C++0x3 line.long 0x0 "EDMA_TPCC_SERH_RN_k_7,Secondary Event Register (High Part) The secondary event register is used along with the Event Register () to provide information on the state of an Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2040++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_0,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2240++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_1,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2440++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_2,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2640++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_3,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2840++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_4,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2A40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_5,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2C40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_6,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2E40++0x3 line.long 0x0 "EDMA_TPCC_SECR_RN_k_7,Secondary Event Clear Register The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " bitfld.long 0x0 8. " E8 ,Event #8" "0,1" bitfld.long 0x0 9. " E9 ,Event #9" "0,1" textline " " bitfld.long 0x0 10. " E10 ,Event #10" "0,1" bitfld.long 0x0 11. " E11 ,Event #11" "0,1" textline " " bitfld.long 0x0 12. " E12 ,Event #12" "0,1" bitfld.long 0x0 13. " E13 ,Event #13" "0,1" textline " " bitfld.long 0x0 14. " E14 ,Event #14" "0,1" bitfld.long 0x0 15. " E15 ,Event #15" "0,1" textline " " bitfld.long 0x0 16. " E16 ,Event #16" "0,1" bitfld.long 0x0 17. " E17 ,Event #17" "0,1" textline " " bitfld.long 0x0 18. " E18 ,Event #18" "0,1" bitfld.long 0x0 19. " E19 ,Event #19" "0,1" textline " " bitfld.long 0x0 20. " E20 ,Event #20" "0,1" bitfld.long 0x0 21. " E21 ,Event #21" "0,1" textline " " bitfld.long 0x0 22. " E22 ,Event #22" "0,1" bitfld.long 0x0 23. " E23 ,Event #23" "0,1" textline " " bitfld.long 0x0 24. " E24 ,Event #24" "0,1" bitfld.long 0x0 25. " E25 ,Event #25" "0,1" textline " " bitfld.long 0x0 26. " E26 ,Event #26" "0,1" bitfld.long 0x0 27. " E27 ,Event #27" "0,1" textline " " bitfld.long 0x0 28. " E28 ,Event #28" "0,1" bitfld.long 0x0 29. " E29 ,Event #29" "0,1" textline " " bitfld.long 0x0 30. " E30 ,Event #30" "0,1" bitfld.long 0x0 31. " E31 ,Event #31" "0,1" group.byte 0x2044++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_0,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2244++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_1,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2444++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_2,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2644++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_3,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2844++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_4,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2A44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_5,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2C44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_6,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2E44++0x3 line.long 0x0 "EDMA_TPCC_SECRH_RN_k_7,Secondary Event Clear Register (High Part) The secondary event clear register is used to clear the status of the registers. CPU write of '0' has no effect. CPU write of '1' to the .En bit clears the register." bitfld.long 0x0 0. " E32 ,Event #32" "0,1" bitfld.long 0x0 1. " E33 ,Event #33" "0,1" textline " " bitfld.long 0x0 2. " E34 ,Event #34" "0,1" bitfld.long 0x0 3. " E35 ,Event #35" "0,1" textline " " bitfld.long 0x0 4. " E36 ,Event #36" "0,1" bitfld.long 0x0 5. " E37 ,Event #37" "0,1" textline " " bitfld.long 0x0 6. " E38 ,Event #38" "0,1" bitfld.long 0x0 7. " E39 ,Event #39" "0,1" textline " " bitfld.long 0x0 8. " E40 ,Event #40" "0,1" bitfld.long 0x0 9. " E41 ,Event #41" "0,1" textline " " bitfld.long 0x0 10. " E42 ,Event #42" "0,1" bitfld.long 0x0 11. " E43 ,Event #43" "0,1" textline " " bitfld.long 0x0 12. " E44 ,Event #44" "0,1" bitfld.long 0x0 13. " E45 ,Event #45" "0,1" textline " " bitfld.long 0x0 14. " E46 ,Event #46" "0,1" bitfld.long 0x0 15. " E47 ,Event #47" "0,1" textline " " bitfld.long 0x0 16. " E48 ,Event #48" "0,1" bitfld.long 0x0 17. " E49 ,Event #49" "0,1" textline " " bitfld.long 0x0 18. " E50 ,Event #50" "0,1" bitfld.long 0x0 19. " E51 ,Event #51" "0,1" textline " " bitfld.long 0x0 20. " E52 ,Event #52" "0,1" bitfld.long 0x0 21. " E53 ,Event #53" "0,1" textline " " bitfld.long 0x0 22. " E54 ,Event #54" "0,1" bitfld.long 0x0 23. " E55 ,Event #55" "0,1" textline " " bitfld.long 0x0 24. " E56 ,Event #56" "0,1" bitfld.long 0x0 25. " E57 ,Event #57" "0,1" textline " " bitfld.long 0x0 26. " E58 ,Event #58" "0,1" bitfld.long 0x0 27. " E59 ,Event #59" "0,1" textline " " bitfld.long 0x0 28. " E60 ,Event #60" "0,1" bitfld.long 0x0 29. " E61 ,Event #61" "0,1" textline " " bitfld.long 0x0 30. " E62 ,Event #62" "0,1" bitfld.long 0x0 31. " E63 ,Event #63" "0,1" group.byte 0x2050++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_0,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2250++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_1,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2450++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_2,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2650++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_3,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2850++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_4,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_5,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_6,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E50++0x3 line.long 0x0 "EDMA_TPCC_IER_RN_k_7,Int Enable Register .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2054++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_0,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2254++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_1,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2454++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_2,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2654++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_3,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2854++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_4,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_5,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_6,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E54++0x3 line.long 0x0 "EDMA_TPCC_IERH_RN_k_7,Int Enable Register (High Part) .In is not directly writeable. Interrupts can be enabled via writes to and can be disabled via writes to register. .In = 0: .In is NOT enabled for interrupts. .In = 1: .In IS enabled for interrupts." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2058++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_0,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2258++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_1,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2458++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_2,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2658++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_3,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2858++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_4,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_5,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_6,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E58++0x3 line.long 0x0 "EDMA_TPCC_IECR_RN_k_7,Int Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x205C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_0,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x225C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_1,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x245C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_2,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x265C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_3,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x285C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_4,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_5,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_6,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E5C++0x3 line.long 0x0 "EDMA_TPCC_IECRH_RN_k_7,Int Enable Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2060++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_0,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2260++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_1,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2460++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_2,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2660++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_3,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2860++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_4,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_5,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_6,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E60++0x3 line.long 0x0 "EDMA_TPCC_IESR_RN_k_7,Int Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2064++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_0,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2264++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_1,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2464++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_2,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2664++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_3,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2864++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_4,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_5,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_6,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E64++0x3 line.long 0x0 "EDMA_TPCC_IESRH_RN_k_7,Int Enable Set Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be set." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2068++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_0,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2268++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_1,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2468++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_2,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2668++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_3,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2868++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_4,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_5,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_6,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E68++0x3 line.long 0x0 "EDMA_TPCC_IPR_RN_k_7,Interrupt Pending Register .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x206C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_0,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x226C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_1,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x246C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_2,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x266C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_3,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x286C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_4,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_5,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_6,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E6C++0x3 line.long 0x0 "EDMA_TPCC_IPRH_RN_k_7,Interrupt Pending Register (High Part) .In bit is set when a interrupt completion code with TCC of N is detected. .In bit is cleared via software by writing a '1' to .In bit." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2070++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_0,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2270++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_1,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2470++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_2,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2670++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_3,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2870++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_4,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2A70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_5,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2C70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_6,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2E70++0x3 line.long 0x0 "EDMA_TPCC_ICR_RN_k_7,Interrupt Clear Register CPU writes of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I0 ,Interrupt associated with TCC #0" "0,1" bitfld.long 0x0 1. " I1 ,Interrupt associated with TCC #1" "0,1" textline " " bitfld.long 0x0 2. " I2 ,Interrupt associated with TCC #2" "0,1" bitfld.long 0x0 3. " I3 ,Interrupt associated with TCC #3" "0,1" textline " " bitfld.long 0x0 4. " I4 ,Interrupt associated with TCC #4" "0,1" bitfld.long 0x0 5. " I5 ,Interrupt associated with TCC #5" "0,1" textline " " bitfld.long 0x0 6. " I6 ,Interrupt associated with TCC #6" "0,1" bitfld.long 0x0 7. " I7 ,Interrupt associated with TCC #7" "0,1" textline " " bitfld.long 0x0 8. " I8 ,Interrupt associated with TCC #8" "0,1" bitfld.long 0x0 9. " I9 ,Interrupt associated with TCC #9" "0,1" textline " " bitfld.long 0x0 10. " I10 ,Interrupt associated with TCC #10" "0,1" bitfld.long 0x0 11. " I11 ,Interrupt associated with TCC #11" "0,1" textline " " bitfld.long 0x0 12. " I12 ,Interrupt associated with TCC #12" "0,1" bitfld.long 0x0 13. " I13 ,Interrupt associated with TCC #13" "0,1" textline " " bitfld.long 0x0 14. " I14 ,Interrupt associated with TCC #14" "0,1" bitfld.long 0x0 15. " I15 ,Interrupt associated with TCC #15" "0,1" textline " " bitfld.long 0x0 16. " I16 ,Interrupt associated with TCC #16" "0,1" bitfld.long 0x0 17. " I17 ,Interrupt associated with TCC #17" "0,1" textline " " bitfld.long 0x0 18. " I18 ,Interrupt associated with TCC #18" "0,1" bitfld.long 0x0 19. " I19 ,Interrupt associated with TCC #19" "0,1" textline " " bitfld.long 0x0 20. " I20 ,Interrupt associated with TCC #20" "0,1" bitfld.long 0x0 21. " I21 ,Interrupt associated with TCC #21" "0,1" textline " " bitfld.long 0x0 22. " I22 ,Interrupt associated with TCC #22" "0,1" bitfld.long 0x0 23. " I23 ,Interrupt associated with TCC #23" "0,1" textline " " bitfld.long 0x0 24. " I24 ,Interrupt associated with TCC #24" "0,1" bitfld.long 0x0 25. " I25 ,Interrupt associated with TCC #25" "0,1" textline " " bitfld.long 0x0 26. " I26 ,Interrupt associated with TCC #26" "0,1" bitfld.long 0x0 27. " I27 ,Interrupt associated with TCC #27" "0,1" textline " " bitfld.long 0x0 28. " I28 ,Interrupt associated with TCC #28" "0,1" bitfld.long 0x0 29. " I29 ,Interrupt associated with TCC #29" "0,1" textline " " bitfld.long 0x0 30. " I30 ,Interrupt associated with TCC #30" "0,1" bitfld.long 0x0 31. " I31 ,Interrupt associated with TCC #31" "0,1" group.byte 0x2074++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_0,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2274++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_1,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2474++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_2,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2674++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_3,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2874++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_4,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2A74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_5,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2C74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_6,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2E74++0x3 line.long 0x0 "EDMA_TPCC_ICRH_RN_k_7,Interrupt Clear Register (High Part) CPU write of '0' has no effect. CPU write of '1' to the .In bit causes the .In bit to be cleared. All .In bits must be cleared before additional interrupts will be asserted by CC." bitfld.long 0x0 0. " I32 ,Interrupt associated with TCC #32" "0,1" bitfld.long 0x0 1. " I33 ,Interrupt associated with TCC #33" "0,1" textline " " bitfld.long 0x0 2. " I34 ,Interrupt associated with TCC #34" "0,1" bitfld.long 0x0 3. " I35 ,Interrupt associated with TCC #35" "0,1" textline " " bitfld.long 0x0 4. " I36 ,Interrupt associated with TCC #36" "0,1" bitfld.long 0x0 5. " I37 ,Interrupt associated with TCC #37" "0,1" textline " " bitfld.long 0x0 6. " I38 ,Interrupt associated with TCC #38" "0,1" bitfld.long 0x0 7. " I39 ,Interrupt associated with TCC #39" "0,1" textline " " bitfld.long 0x0 8. " I40 ,Interrupt associated with TCC #40" "0,1" bitfld.long 0x0 9. " I41 ,Interrupt associated with TCC #41" "0,1" textline " " bitfld.long 0x0 10. " I42 ,Interrupt associated with TCC #42" "0,1" bitfld.long 0x0 11. " I43 ,Interrupt associated with TCC #43" "0,1" textline " " bitfld.long 0x0 12. " I44 ,Interrupt associated with TCC #44" "0,1" bitfld.long 0x0 13. " I45 ,Interrupt associated with TCC #45" "0,1" textline " " bitfld.long 0x0 14. " I46 ,Interrupt associated with TCC #46" "0,1" bitfld.long 0x0 15. " I47 ,Interrupt associated with TCC #47" "0,1" textline " " bitfld.long 0x0 16. " I48 ,Interrupt associated with TCC #48" "0,1" bitfld.long 0x0 17. " I49 ,Interrupt associated with TCC #49" "0,1" textline " " bitfld.long 0x0 18. " I50 ,Interrupt associated with TCC #50" "0,1" bitfld.long 0x0 19. " I51 ,Interrupt associated with TCC #51" "0,1" textline " " bitfld.long 0x0 20. " I52 ,Interrupt associated with TCC #52" "0,1" bitfld.long 0x0 21. " I53 ,Interrupt associated with TCC #53" "0,1" textline " " bitfld.long 0x0 22. " I54 ,Interrupt associated with TCC #54" "0,1" bitfld.long 0x0 23. " I55 ,Interrupt associated with TCC #55" "0,1" textline " " bitfld.long 0x0 24. " I56 ,Interrupt associated with TCC #56" "0,1" bitfld.long 0x0 25. " I57 ,Interrupt associated with TCC #57" "0,1" textline " " bitfld.long 0x0 26. " I58 ,Interrupt associated with TCC #58" "0,1" bitfld.long 0x0 27. " I59 ,Interrupt associated with TCC #59" "0,1" textline " " bitfld.long 0x0 28. " I60 ,Interrupt associated with TCC #60" "0,1" bitfld.long 0x0 29. " I61 ,Interrupt associated with TCC #61" "0,1" textline " " bitfld.long 0x0 30. " I62 ,Interrupt associated with TCC #62" "0,1" bitfld.long 0x0 31. " I63 ,Interrupt associated with TCC #63" "0,1" group.byte 0x2078++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_0,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2278++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_1,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2478++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_2,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2678++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_3,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2878++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_4,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2A78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_5,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2C78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_6,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2E78++0x3 line.long 0x0 "EDMA_TPCC_IEVAL_RN_k_7,Interrupt Eval Register" bitfld.long 0x0 0. " EVAL ,Interrupt EvaluateCPU writes 0x0 has no effect. . CPU writes 0x1 to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (EDMA_TPCC_IPRn). ." "0,1" bitfld.long 0x0 1. " SET ,Interrupt SetCPU writes 0x0 has no effect. . CPU writes 0x1 to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (EDMA_TPCC_IPRn). ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x2080++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_0,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2280++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_1,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2480++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_2,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2680++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_3,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2880++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_4,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_5,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_6,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E80++0x3 line.long 0x0 "EDMA_TPCC_QER_RN_k_7,QDMA Event Register If .En bit is set, then the corresponding QDMA channel is prioritized vs. other qdma events for submission to the TC. .En bit is set when a vbus write byte matches the address defined in the QCHMAPn register. .En bit is cleared when the corresponding event is prioritized and serviced. .En is also cleared when user writes a '1' to the .En bit. If the .En bit is already set and a new QDMA event is detected due to user write to QDMA trigger location and register is set, then the corresponding bit in the QDMA Event Missed Register is set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2084++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_0,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2284++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_1,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2484++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_2,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2684++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_3,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2884++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_4,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_5,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_6,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E84++0x3 line.long 0x0 "EDMA_TPCC_QEER_RN_k_7,QDMA Event Enable Register Enabled/disabled QDMA address comparator for QDMA Channel N. .En is not directly writeable. The corresponding QDMA channel comparator is enabled and Events will be recognized and latched in .En. .En = 0, The corresponding QDMA channel comparator is disabled. Events will not be recognized/latched in .En. QDMA channels can be enabled via writes to and can be disabled via writes to register. .En = 1," bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2088++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_0,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2288++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_1,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2488++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_2,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2688++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_3,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2888++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_4,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_5,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_6,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E88++0x3 line.long 0x0 "EDMA_TPCC_QEECR_RN_k_7,QDMA Event Enable Clear Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be cleared." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x208C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_0,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x228C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_1,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x248C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_2,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x268C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_3,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x288C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_4,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_5,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_6,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E8C++0x3 line.long 0x0 "EDMA_TPCC_QEESR_RN_k_7,QDMA Event Enable Set Register CPU write of '0' has no effect. CPU write of '1' to the .En bit causes the .En bit to be set." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2090++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_0,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2290++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_1,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2490++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_2,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2690++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_3,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2890++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_4,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2A90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_5,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_6,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2E90++0x3 line.long 0x0 "EDMA_TPCC_QSER_RN_k_7,QDMA Secondary Event Register The QDMA secondary event register is used along with the QDMA Event Register () to provide information on the state of a QDMA Event. En = 0 : Event is not currently in the Event Queue. En = 1 : Event is currently stored in Event Queue. Event arbiter will not prioritize additional events." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2094++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_0,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2294++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_1,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2494++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_2,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2694++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_3,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2894++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_4,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2A94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_5,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2C94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_6,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x2E94++0x3 line.long 0x0 "EDMA_TPCC_QSECR_RN_k_7,QDMA Secondary Event Clear Register CPU write of '0' has no effect. The secondary event clear register is used to clear the status of the and register (note that this is slightly different than the operation, which does not clear the .En register). CPU write of '1' to the .En bit clears the .En and .En register fields." bitfld.long 0x0 0. " E0 ,Event #0" "0,1" bitfld.long 0x0 1. " E1 ,Event #1" "0,1" textline " " bitfld.long 0x0 2. " E2 ,Event #2" "0,1" bitfld.long 0x0 3. " E3 ,Event #3" "0,1" textline " " bitfld.long 0x0 4. " E4 ,Event #4" "0,1" bitfld.long 0x0 5. " E5 ,Event #5" "0,1" textline " " bitfld.long 0x0 6. " E6 ,Event #6" "0,1" bitfld.long 0x0 7. " E7 ,Event #7" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,write 0's for future compatibility" group.byte 0x4000++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_0,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4020++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_1,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4040++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_2,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4060++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_3,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4080++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_4,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_5,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_6,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x40E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_7,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4100++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_8,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4120++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_9,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4140++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_10,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4160++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_11,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4180++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_12,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_13,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_14,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x41E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_15,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4200++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_16,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4220++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_17,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4240++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_18,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4260++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_19,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4280++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_20,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_21,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_22,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x42E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_23,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4300++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_24,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4320++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_25,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4340++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_26,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4360++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_27,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4380++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_28,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_29,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_30,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x43E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_31,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4400++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_32,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4420++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_33,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4440++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_34,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4460++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_35,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4480++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_36,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_37,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_38,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x44E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_39,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4500++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_40,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4520++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_41,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4540++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_42,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4560++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_43,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4580++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_44,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_45,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_46,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x45E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_47,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4600++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_48,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4620++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_49,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4640++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_50,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4660++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_51,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4680++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_52,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_53,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_54,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x46E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_55,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4700++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_56,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4720++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_57,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4740++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_58,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4760++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_59,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4780++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_60,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_61,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_62,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x47E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_63,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4800++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_64,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4820++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_65,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4840++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_66,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4860++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_67,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4880++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_68,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_69,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_70,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x48E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_71,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4900++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_72,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4920++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_73,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4940++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_74,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4960++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_75,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4980++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_76,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49A0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_77,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49C0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_78,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x49E0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_79,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_80,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_81,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_82,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_83,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4A80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_84,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_85,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_86,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4AE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_87,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_88,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_89,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_90,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_91,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4B80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_92,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_93,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_94,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4BE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_95,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_96,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_97,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_98,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_99,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4C80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_100,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_101,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_102,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4CE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_103,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_104,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_105,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_106,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_107,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4D80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_108,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_109,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_110,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4DE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_111,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_112,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_113,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_114,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_115,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4E80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_116,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_117,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_118,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4EE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_119,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F00++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_120,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F20++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_121,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F40++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_122,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F60++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_123,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4F80++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_124,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FA0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_125,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FC0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_126,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4FE0++0x3 line.long 0x0 "EDMA_TPCC_OPT_n_127,Options Parameter" bitfld.long 0x0 0. " SAM ,Source Address Mode: Source Address Mode within an array. Pass-thru to TC." "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode: Destination Address Mode within an array. Pass-thru to TC." "0,1" textline " " bitfld.long 0x0 2. " SYNCDIM ,Transfer Synchronization Dimension:" "0,1" bitfld.long 0x0 3. " STATIC ,Static Entry" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--10. " FWID ,FIFO width: Applies if either SAM or DAM is set to FIFO mode. Pass-thru to TC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " TCCMODE ,Transfer complete code mode: Indicates the point at which a transfer is considered completed. Applies to both chaining and interrupt." "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER (bit EDMA_TPCC_CER[TCC]) for chaining or in EDMA_TPCC_IER (bit EDMA_TPCC_IER[TCC]) for interrupts." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 19. " WIMODE ,Backward compatibility mode" "0,1" textline " " bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" bitfld.long 0x0 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "0,1" textline " " bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" bitfld.long 0x0 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "0,1" textline " " bitfld.long 0x0 24.--27. " PRIVID ,Privilege ID Privilege ID for the external host/cpu/dma that programmed this PaRAM Entry. This value is set with the vbus privid value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " PRIV ,Privilege level privilege level (supervisor vs. user) for the host/cpu/dma that programmed this PaRAM Entry. Value is set with the vbus priv value when any part of the PaRAM Entry is written. Not writeable via vbus wdata bus. Is readable via VBus rdata bus." "0,1" group.byte 0x4004++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_0,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4024++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_1,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4044++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_2,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4064++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_3,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4084++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_4,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_5,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_6,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_7,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4104++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_8,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4124++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_9,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4144++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_10,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4164++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_11,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4184++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_12,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_13,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_14,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_15,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4204++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_16,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4224++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_17,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4244++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_18,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4264++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_19,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4284++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_20,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_21,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_22,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_23,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4304++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_24,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4324++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_25,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4344++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_26,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4364++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_27,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4384++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_28,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_29,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_30,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_31,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4404++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_32,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4424++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_33,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4444++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_34,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4464++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_35,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4484++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_36,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_37,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_38,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_39,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4504++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_40,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4524++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_41,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4544++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_42,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4564++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_43,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4584++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_44,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_45,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_46,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_47,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4604++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_48,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4624++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_49,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4644++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_50,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4664++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_51,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4684++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_52,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_53,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_54,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_55,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4704++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_56,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4724++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_57,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4744++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_58,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4764++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_59,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4784++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_60,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_61,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_62,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_63,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4804++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_64,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4824++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_65,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4844++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_66,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4864++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_67,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4884++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_68,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_69,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_70,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_71,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4904++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_72,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4924++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_73,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4944++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_74,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4964++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_75,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4984++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_76,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49A4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_77,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49C4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_78,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49E4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_79,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_80,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_81,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_82,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_83,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_84,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_85,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_86,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_87,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_88,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_89,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_90,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_91,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_92,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_93,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_94,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_95,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_96,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_97,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_98,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_99,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_100,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_101,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_102,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_103,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_104,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_105,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_106,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_107,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_108,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_109,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_110,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_111,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_112,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_113,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_114,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_115,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_116,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_117,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_118,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_119,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F04++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_120,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F24++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_121,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F44++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_122,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F64++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_123,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F84++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_124,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FA4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_125,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FC4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_126,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FE4++0x3 line.long 0x0 "EDMA_TPCC_SRC_n_127,Source Address" hexmask.long 0x0 0.--31. 1. " SRC ,Source Address The 32-bit source address parameters specify the starting byte address of the source. If SAM is set to FIFO mode then the user should program the Source address to be aligned to the value specified by the EDMA_TPCC_OPT_n[10:8] FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4008++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_0,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4028++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_1,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4048++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_2,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4068++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_3,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4088++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_4,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_5,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_6,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x40E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_7,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4108++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_8,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4128++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_9,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4148++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_10,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4168++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_11,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4188++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_12,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_13,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_14,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x41E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_15,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4208++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_16,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4228++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_17,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4248++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_18,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4268++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_19,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4288++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_20,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_21,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_22,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x42E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_23,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4308++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_24,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4328++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_25,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4348++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_26,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4368++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_27,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4388++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_28,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_29,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_30,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x43E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_31,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4408++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_32,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4428++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_33,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4448++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_34,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4468++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_35,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4488++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_36,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_37,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_38,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x44E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_39,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4508++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_40,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4528++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_41,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4548++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_42,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4568++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_43,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4588++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_44,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_45,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_46,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x45E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_47,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4608++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_48,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4628++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_49,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4648++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_50,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4668++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_51,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4688++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_52,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_53,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_54,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x46E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_55,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4708++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_56,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4728++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_57,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4748++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_58,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4768++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_59,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4788++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_60,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_61,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_62,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x47E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_63,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4808++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_64,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4828++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_65,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4848++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_66,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4868++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_67,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4888++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_68,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_69,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_70,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x48E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_71,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4908++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_72,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4928++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_73,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4948++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_74,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4968++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_75,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4988++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_76,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49A8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_77,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49C8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_78,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x49E8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_79,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_80,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_81,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_82,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_83,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4A88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_84,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_85,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_86,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4AE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_87,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_88,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_89,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_90,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_91,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4B88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_92,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_93,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_94,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4BE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_95,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_96,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_97,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_98,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_99,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4C88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_100,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_101,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_102,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4CE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_103,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_104,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_105,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_106,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_107,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4D88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_108,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_109,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_110,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4DE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_111,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_112,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_113,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_114,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_115,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4E88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_116,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_117,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_118,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4EE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_119,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F08++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_120,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F28++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_121,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F48++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_122,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F68++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_123,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4F88++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_124,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FA8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_125,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FC8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_126,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x4FE8++0x3 line.long 0x0 "EDMA_TPCC_ABCNT_n_127,A and B byte count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,ACNT: number of bytes in 1st dimension: ACNT represents the number of bytes within the first dimension of a transfer. ACNT is a 16-bit unsigned value with valid values between 0 and 65535. Therefore, the maximum number of bytes in an array is 65535 bytes (64K-1 bytes). ACNT must be greater than or equal to '1' for a TR to be submitted to TC. An ACNT of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set then the ACNT field represents a word count. The CC must internally multiply by 4 to translate the word count to a byte count prior to submission to the TC. The 2 MSBs of the 16-bit ACNT are reserved and should always be written as 'b00 by the user. If user writes a value other than 0, it will still be treated as 0 since the multiply-by-4 operation (to translate between a word count and a byte count) will drop the 2 msbits. For dummy and null transfer definition, the ACNT definition will disregard the 2 msbits. I.e., a programmed ACNT value of 0x8000 in WI-mode will be treated as 0 byte transfer, resulting in null or dummy operation dependent on the state of BCNT and CCNT." hexmask.long.word 0x0 16.--31. 1. " BCNT ,BCNT: Count for 2nd Dimension: BCNT is a 16-bit unsigned value that specifies the number of arrays of length ACNT. For normal operation, valid values for BCNT can be anywhere between 1 and 65535. Therefore, the maximum number of arrays in a frame is 65535 (64K-1 arrays). BCNT=1 means 1 array in the frame, and BCNT=0 means 0 arrays in the frame. In normal mode, a BCNT of '0' is considered as either a Null or Dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. If the EDMA_TPCC_OPT_n.WIMODE bit is set, then the programmed BCNT value will be incremented by '1' before submission to TC. I.e., 0 means 1, 1 means 2, 2 means 3, ..., 0xFFFE means 0xFFFF. A value of 0xFFFF is an illegal value that will be treated as a Null TR." group.byte 0x400C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_0,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x402C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_1,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x404C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_2,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x406C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_3,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x408C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_4,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_5,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_6,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x40EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_7,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x410C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_8,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x412C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_9,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x414C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_10,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x416C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_11,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x418C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_12,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_13,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_14,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x41EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_15,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x420C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_16,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x422C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_17,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x424C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_18,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x426C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_19,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x428C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_20,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_21,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_22,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x42EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_23,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x430C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_24,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x432C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_25,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x434C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_26,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x436C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_27,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x438C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_28,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_29,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_30,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x43EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_31,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x440C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_32,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x442C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_33,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x444C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_34,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x446C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_35,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x448C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_36,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_37,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_38,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x44EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_39,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x450C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_40,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x452C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_41,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x454C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_42,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x456C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_43,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x458C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_44,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_45,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_46,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x45EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_47,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x460C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_48,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x462C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_49,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x464C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_50,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x466C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_51,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x468C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_52,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_53,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_54,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x46EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_55,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x470C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_56,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x472C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_57,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x474C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_58,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x476C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_59,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x478C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_60,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_61,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_62,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x47EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_63,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x480C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_64,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x482C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_65,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x484C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_66,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x486C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_67,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x488C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_68,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_69,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_70,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x48EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_71,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x490C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_72,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x492C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_73,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x494C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_74,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x496C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_75,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x498C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_76,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49AC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_77,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49CC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_78,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x49EC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_79,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_80,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_81,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_82,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_83,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4A8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_84,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_85,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ACC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_86,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4AEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_87,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_88,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_89,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_90,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_91,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4B8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_92,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_93,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_94,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4BEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_95,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_96,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_97,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_98,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_99,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4C8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_100,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_101,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_102,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4CEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_103,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_104,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_105,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_106,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_107,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4D8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_108,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_109,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_110,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4DEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_111,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_112,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_113,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_114,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_115,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4E8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_116,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_117,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4ECC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_118,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4EEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_119,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F0C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_120,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F2C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_121,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F4C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_122,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F6C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_123,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4F8C++0x3 line.long 0x0 "EDMA_TPCC_DST_n_124,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FAC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_125,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FCC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_126,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4FEC++0x3 line.long 0x0 "EDMA_TPCC_DST_n_127,Destination Address" hexmask.long 0x0 0.--31. 1. " DST ,Destination Address: The 32-bit destination address parameters specify the starting byte address of the destination. If DAM is set to FIFO mode then the user should program the Destination address to be aligned to the value specified by theEDMA_TPCC_OPT_n.FWID field. No errors are recognized here but TC will assert error if this is not true." group.byte 0x4010++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_0,EDMA_TPCC_BIDX_n_0" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4030++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_1,EDMA_TPCC_BIDX_n_1" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4050++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_2,EDMA_TPCC_BIDX_n_2" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4070++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_3,EDMA_TPCC_BIDX_n_3" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4090++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_4,EDMA_TPCC_BIDX_n_4" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_5,EDMA_TPCC_BIDX_n_5" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_6,EDMA_TPCC_BIDX_n_6" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x40F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_7,EDMA_TPCC_BIDX_n_7" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4110++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_8,EDMA_TPCC_BIDX_n_8" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4130++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_9,EDMA_TPCC_BIDX_n_9" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4150++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_10,EDMA_TPCC_BIDX_n_10" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4170++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_11,EDMA_TPCC_BIDX_n_11" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4190++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_12,EDMA_TPCC_BIDX_n_12" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_13,EDMA_TPCC_BIDX_n_13" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_14,EDMA_TPCC_BIDX_n_14" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x41F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_15,EDMA_TPCC_BIDX_n_15" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4210++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_16,EDMA_TPCC_BIDX_n_16" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4230++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_17,EDMA_TPCC_BIDX_n_17" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4250++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_18,EDMA_TPCC_BIDX_n_18" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4270++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_19,EDMA_TPCC_BIDX_n_19" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4290++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_20,EDMA_TPCC_BIDX_n_20" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_21,EDMA_TPCC_BIDX_n_21" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_22,EDMA_TPCC_BIDX_n_22" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x42F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_23,EDMA_TPCC_BIDX_n_23" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4310++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_24,EDMA_TPCC_BIDX_n_24" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4330++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_25,EDMA_TPCC_BIDX_n_25" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4350++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_26,EDMA_TPCC_BIDX_n_26" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4370++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_27,EDMA_TPCC_BIDX_n_27" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4390++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_28,EDMA_TPCC_BIDX_n_28" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_29,EDMA_TPCC_BIDX_n_29" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_30,EDMA_TPCC_BIDX_n_30" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x43F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_31,EDMA_TPCC_BIDX_n_31" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4410++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_32,EDMA_TPCC_BIDX_n_32" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4430++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_33,EDMA_TPCC_BIDX_n_33" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4450++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_34,EDMA_TPCC_BIDX_n_34" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4470++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_35,EDMA_TPCC_BIDX_n_35" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4490++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_36,EDMA_TPCC_BIDX_n_36" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_37,EDMA_TPCC_BIDX_n_37" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_38,EDMA_TPCC_BIDX_n_38" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x44F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_39,EDMA_TPCC_BIDX_n_39" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4510++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_40,EDMA_TPCC_BIDX_n_40" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4530++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_41,EDMA_TPCC_BIDX_n_41" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4550++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_42,EDMA_TPCC_BIDX_n_42" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4570++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_43,EDMA_TPCC_BIDX_n_43" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4590++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_44,EDMA_TPCC_BIDX_n_44" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_45,EDMA_TPCC_BIDX_n_45" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_46,EDMA_TPCC_BIDX_n_46" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x45F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_47,EDMA_TPCC_BIDX_n_47" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4610++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_48,EDMA_TPCC_BIDX_n_48" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4630++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_49,EDMA_TPCC_BIDX_n_49" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4650++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_50,EDMA_TPCC_BIDX_n_50" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4670++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_51,EDMA_TPCC_BIDX_n_51" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4690++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_52,EDMA_TPCC_BIDX_n_52" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_53,EDMA_TPCC_BIDX_n_53" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_54,EDMA_TPCC_BIDX_n_54" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x46F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_55,EDMA_TPCC_BIDX_n_55" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4710++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_56,EDMA_TPCC_BIDX_n_56" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4730++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_57,EDMA_TPCC_BIDX_n_57" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4750++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_58,EDMA_TPCC_BIDX_n_58" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4770++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_59,EDMA_TPCC_BIDX_n_59" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4790++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_60,EDMA_TPCC_BIDX_n_60" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_61,EDMA_TPCC_BIDX_n_61" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_62,EDMA_TPCC_BIDX_n_62" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x47F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_63,EDMA_TPCC_BIDX_n_63" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4810++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_64,EDMA_TPCC_BIDX_n_64" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4830++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_65,EDMA_TPCC_BIDX_n_65" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4850++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_66,EDMA_TPCC_BIDX_n_66" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4870++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_67,EDMA_TPCC_BIDX_n_67" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4890++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_68,EDMA_TPCC_BIDX_n_68" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_69,EDMA_TPCC_BIDX_n_69" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_70,EDMA_TPCC_BIDX_n_70" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x48F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_71,EDMA_TPCC_BIDX_n_71" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4910++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_72,EDMA_TPCC_BIDX_n_72" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4930++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_73,EDMA_TPCC_BIDX_n_73" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4950++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_74,EDMA_TPCC_BIDX_n_74" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4970++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_75,EDMA_TPCC_BIDX_n_75" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4990++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_76,EDMA_TPCC_BIDX_n_76" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49B0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_77,EDMA_TPCC_BIDX_n_77" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49D0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_78,EDMA_TPCC_BIDX_n_78" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x49F0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_79,EDMA_TPCC_BIDX_n_79" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_80,EDMA_TPCC_BIDX_n_80" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_81,EDMA_TPCC_BIDX_n_81" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_82,EDMA_TPCC_BIDX_n_82" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_83,EDMA_TPCC_BIDX_n_83" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4A90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_84,EDMA_TPCC_BIDX_n_84" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_85,EDMA_TPCC_BIDX_n_85" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_86,EDMA_TPCC_BIDX_n_86" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4AF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_87,EDMA_TPCC_BIDX_n_87" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_88,EDMA_TPCC_BIDX_n_88" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_89,EDMA_TPCC_BIDX_n_89" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_90,EDMA_TPCC_BIDX_n_90" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_91,EDMA_TPCC_BIDX_n_91" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4B90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_92,EDMA_TPCC_BIDX_n_92" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_93,EDMA_TPCC_BIDX_n_93" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_94,EDMA_TPCC_BIDX_n_94" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4BF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_95,EDMA_TPCC_BIDX_n_95" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_96,EDMA_TPCC_BIDX_n_96" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_97,EDMA_TPCC_BIDX_n_97" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_98,EDMA_TPCC_BIDX_n_98" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_99,EDMA_TPCC_BIDX_n_99" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4C90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_100,EDMA_TPCC_BIDX_n_100" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_101,EDMA_TPCC_BIDX_n_101" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_102,EDMA_TPCC_BIDX_n_102" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4CF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_103,EDMA_TPCC_BIDX_n_103" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_104,EDMA_TPCC_BIDX_n_104" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_105,EDMA_TPCC_BIDX_n_105" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_106,EDMA_TPCC_BIDX_n_106" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_107,EDMA_TPCC_BIDX_n_107" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4D90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_108,EDMA_TPCC_BIDX_n_108" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_109,EDMA_TPCC_BIDX_n_109" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_110,EDMA_TPCC_BIDX_n_110" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4DF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_111,EDMA_TPCC_BIDX_n_111" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_112,EDMA_TPCC_BIDX_n_112" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_113,EDMA_TPCC_BIDX_n_113" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_114,EDMA_TPCC_BIDX_n_114" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_115,EDMA_TPCC_BIDX_n_115" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4E90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_116,EDMA_TPCC_BIDX_n_116" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_117,EDMA_TPCC_BIDX_n_117" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4ED0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_118,EDMA_TPCC_BIDX_n_118" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4EF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_119,EDMA_TPCC_BIDX_n_119" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F10++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_120,EDMA_TPCC_BIDX_n_120" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F30++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_121,EDMA_TPCC_BIDX_n_121" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F50++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_122,EDMA_TPCC_BIDX_n_122" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F70++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_123,EDMA_TPCC_BIDX_n_123" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4F90++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_124,EDMA_TPCC_BIDX_n_124" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FB0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_125,EDMA_TPCC_BIDX_n_125" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FD0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_126,EDMA_TPCC_BIDX_n_126" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4FF0++0x3 line.long 0x0 "EDMA_TPCC_BIDX_n_127,EDMA_TPCC_BIDX_n_127" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source 2nd Dimension Index: SBIDX is a 16-bit signed value (2's complement) used for source address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the source array to the beginning of the next source array. It applies to both A-sync and AB-sync transfers." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination 2nd Dimension Index: DBIDX is a 16-bit signed value (2's complement) used for destination address modification in between each array in the 2nd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the destination array to the beginning of the next destination array within the current frame. It applies to both A-Sync and AB-Sync transfers." group.byte 0x4014++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_0,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4034++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_1,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4054++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_2,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4074++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_3,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4094++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_4,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_5,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_6,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x40F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_7,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4114++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_8,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4134++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_9,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4154++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_10,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4174++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_11,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4194++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_12,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_13,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_14,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x41F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_15,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4214++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_16,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4234++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_17,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4254++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_18,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4274++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_19,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4294++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_20,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_21,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_22,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x42F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_23,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4314++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_24,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4334++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_25,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4354++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_26,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4374++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_27,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4394++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_28,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_29,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_30,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x43F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_31,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4414++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_32,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4434++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_33,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4454++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_34,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4474++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_35,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4494++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_36,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_37,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_38,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x44F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_39,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4514++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_40,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4534++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_41,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4554++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_42,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4574++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_43,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4594++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_44,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_45,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_46,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x45F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_47,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4614++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_48,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4634++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_49,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4654++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_50,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4674++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_51,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4694++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_52,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_53,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_54,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x46F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_55,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4714++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_56,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4734++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_57,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4754++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_58,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4774++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_59,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4794++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_60,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_61,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_62,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x47F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_63,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4814++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_64,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4834++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_65,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4854++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_66,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4874++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_67,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4894++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_68,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_69,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_70,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x48F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_71,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4914++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_72,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4934++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_73,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4954++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_74,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4974++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_75,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4994++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_76,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49B4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_77,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49D4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_78,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x49F4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_79,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_80,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_81,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_82,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_83,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4A94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_84,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_85,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_86,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4AF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_87,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_88,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_89,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_90,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_91,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4B94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_92,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_93,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_94,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4BF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_95,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_96,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_97,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_98,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_99,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4C94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_100,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_101,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_102,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4CF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_103,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_104,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_105,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_106,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_107,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4D94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_108,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_109,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_110,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4DF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_111,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_112,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_113,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_114,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_115,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4E94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_116,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_117,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4ED4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_118,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4EF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_119,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F14++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_120,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F34++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_121,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F54++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_122,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F74++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_123,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4F94++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_124,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FB4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_125,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FD4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_126,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4FF4++0x3 line.long 0x0 "EDMA_TPCC_LNK_n_127,Link and Reload parameters" hexmask.long.word 0x0 0.--15. 1. " LINK ,Link Address: The CC provides a mechanism to reload the current PaRAM Entry upon its natural termination (i.e., after count fields are decremented to '0') with a new PaRAM Entry. This is called 'linking'. The 16-bit parameter LINK specifies the byte address offset in the PaRAM from which the CC loads/reloads the next PaRAM entry in the link. The CC should disregard the value in the upper 2 bits of the LINK field as well as the lower 5-bits of the LINK field. The upper two bits are ignored such that the user can program either the 'literal' byte address of the LINK parameter or the 'PaRAM base-relative' address of the link field. Therefore, if the user uses the literal address with a range from 0x4000 to 0x7FFF, it will be treated as a PaRAM-base-relative value of 0x0000 to 0x3FFF. The lower-5 bits are ignored and treated as 'b00000, thereby guaranteeing that all Link pointers point to a 32-byte aligned PaRAM entry. In the latter case (5-lsbs), behavior is undefined for the user (i.e., don't have to test it). In the former case (2 msbs), user should be able to take advantage of this feature (i.e., do have to test it). If a Link Update is requested to a PaRAM address that is beyond the actual range of implemented PaRAM, then the Link will be treated as a Null Linkand all 0s plus 0xFFFF will be written to the current entry location. A LINK value of 0xFFFF is referred to as a NULL link which should cause the CC to write 0x0 to all entries of the current PaRAM Entry except for the LINK field which is set to 0xFFFF. The Priv/Privid state is overwritten to 0x0 when linking. MSBs and LSBS should not be masked when comparing against the 0xFFFF value. I.e., a value of 0x3FFE is a non-NULL PaRAM link field." hexmask.long.word 0x0 16.--31. 1. " BCNTRLD ,BCNT Reload: BCNTRLD is a 16-bit unsigned value used to reload the BCNT field once the last array in the 2nd dimension is transferred. This field is only used for A-Sync'ed transfers. In this case, the CC decrements the BCNT value by one on each TR submission. When BCNT (conceptually) reaches zero, then the CC decrements CCNT and uses the BCNTRLD value to reinitialize the BCNT value. For AB-synchronized transfers, the CC submits the BCNT in the TR and therefore the TC is responsible to keep track of BCNT, not thus BCNTRLD is a don't care field." group.byte 0x4018++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_0,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4038++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_1,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4058++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_2,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4078++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_3,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4098++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_4,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_5,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_6,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x40F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_7,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4118++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_8,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4138++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_9,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4158++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_10,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4178++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_11,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4198++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_12,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_13,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_14,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x41F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_15,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4218++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_16,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4238++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_17,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4258++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_18,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4278++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_19,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4298++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_20,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_21,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_22,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x42F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_23,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4318++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_24,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4338++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_25,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4358++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_26,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4378++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_27,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4398++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_28,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_29,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_30,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x43F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_31,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4418++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_32,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4438++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_33,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4458++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_34,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4478++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_35,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4498++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_36,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_37,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_38,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x44F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_39,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4518++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_40,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4538++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_41,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4558++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_42,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4578++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_43,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4598++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_44,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_45,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_46,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x45F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_47,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4618++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_48,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4638++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_49,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4658++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_50,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4678++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_51,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4698++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_52,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_53,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_54,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x46F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_55,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4718++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_56,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4738++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_57,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4758++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_58,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4778++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_59,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4798++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_60,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_61,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_62,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x47F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_63,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4818++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_64,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4838++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_65,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4858++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_66,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4878++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_67,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4898++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_68,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_69,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_70,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x48F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_71,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4918++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_72,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4938++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_73,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4958++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_74,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4978++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_75,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4998++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_76,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49B8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_77,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49D8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_78,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x49F8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_79,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_80,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_81,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_82,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_83,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4A98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_84,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_85,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_86,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4AF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_87,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_88,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_89,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_90,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_91,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4B98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_92,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_93,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_94,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4BF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_95,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_96,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_97,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_98,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_99,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4C98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_100,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_101,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_102,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4CF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_103,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_104,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_105,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_106,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_107,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4D98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_108,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_109,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_110,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4DF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_111,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_112,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_113,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_114,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_115,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4E98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_116,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_117,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4ED8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_118,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4EF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_119,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F18++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_120,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F38++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_121,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F58++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_122,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F78++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_123,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4F98++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_124,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FB8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_125,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FD8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_126,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x4FF8++0x3 line.long 0x0 "EDMA_TPCC_CIDX_n_127,Source and destination frame indexes" hexmask.long.word 0x0 0.--15. 1. " SCIDX ,Source Frame Index: SCIDX is a 16-bit signed value (2's complement) used for source address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by SRC address) to the beginning of the first source array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when SCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a AB-sync transfer is the first array in the frame." hexmask.long.word 0x0 16.--31. 1. " DCIDX ,Destination Frame Index: DCIDX is a 16-bit signed value (2's complement) used for destination address modification for the 3rd dimension. It is a signed value between -32768 and 32767. It provides a byte address offset from the beginning of the current array (pointed to by DST address) to the beginning of the first destination array in the next frame. It applies to both A-sync and AB-sync transfers. Note that when DCIDX is applied, the current array in an A-sync transfer is the last array in the frame, while the current array in a ABsync transfer is the first array in the frame." group.byte 0x401C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_0,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x403C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_1,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x405C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_2,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x407C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_3,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x409C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_4,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_5,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_6,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_7,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x411C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_8,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x413C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_9,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x415C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_10,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x417C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_11,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x419C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_12,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_13,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_14,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x41FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_15,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x421C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_16,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x423C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_17,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x425C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_18,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x427C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_19,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x429C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_20,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_21,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_22,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x42FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_23,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x431C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_24,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x433C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_25,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x435C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_26,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x437C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_27,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x439C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_28,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_29,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_30,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x43FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_31,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x441C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_32,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x443C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_33,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x445C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_34,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x447C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_35,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x449C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_36,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_37,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_38,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x44FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_39,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x451C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_40,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x453C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_41,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x455C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_42,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x457C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_43,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x459C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_44,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_45,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_46,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x45FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_47,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x461C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_48,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x463C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_49,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x465C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_50,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x467C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_51,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x469C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_52,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_53,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_54,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x46FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_55,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x471C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_56,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x473C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_57,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x475C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_58,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x477C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_59,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x479C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_60,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_61,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_62,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x47FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_63,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x481C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_64,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x483C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_65,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x485C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_66,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x487C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_67,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x489C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_68,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_69,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_70,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x48FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_71,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x491C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_72,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x493C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_73,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x495C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_74,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x497C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_75,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x499C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_76,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49BC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_77,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49DC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_78,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x49FC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_79,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_80,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_81,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_82,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_83,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4A9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_84,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ABC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_85,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4ADC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_86,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4AFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_87,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_88,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_89,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_90,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_91,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4B9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_92,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_93,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_94,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4BFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_95,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_96,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_97,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_98,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_99,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4C9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_100,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_101,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_102,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4CFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_103,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_104,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_105,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_106,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_107,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4D9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_108,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_109,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_110,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4DFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_111,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_112,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_113,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_114,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_115,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4E9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_116,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_117,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_118,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4EFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_119,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F1C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_120,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F3C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_121,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F5C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_122,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F7C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_123,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4F9C++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_124,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FBC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_125,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FDC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_126,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4FFC++0x3 line.long 0x0 "EDMA_TPCC_CCNT_n_127,C byte count" hexmask.long.word 0x0 0.--15. 1. " CCNT ,CCNT: Count for 3rd Dimension: CCNT is a 16-bit unsigned value that specifies the number of frames in a block. Valid values for CCNT can be anywhere between 1 and 65535. Therefore, the maximum number of frames in a block is 65535 (64K-1 frames). CCNT of '1' means '1' frame in the block, and CCNT of '0' means '0' frames in the block. A CCNT value of '0' is considered as either a null or dummy transfer. A Dummy or Null transfer will generate a Completion code depending on the settings of the completion bit fields of the OPT field. WIMODE has no affect on CCNT operation." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP_EDMA_TPTC0" base ad:0x1D05000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP_EDMA_TPTC1" base ad:0x1D06000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_EDMA_TPTC0" base ad:0x40D05000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_EDMA_TPTC1" base ad:0x40D06000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_EDMA_TPTC0" base ad:0x41505000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_EDMA_TPTC1" base ad:0x41506000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "SYS_EDMA_TPTC0" base ad:0x43400000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "SYS_EDMA_TPTC1" base ad:0x43500000 width 24. group.byte 0x0++0x3 line.long 0x0 "EDMA_TPTCn_PID,Peripheral ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "EDMA_TPTCn_TCCFG,TC Configuration Register" bitfld.long 0x0 0.--2. " FIFOSIZE ,Fifo Size Parameterization" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reads return 0's" "0,1" textline " " bitfld.long 0x0 4.--5. " BUSWIDTH ,Bus Width Parameterization" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ,Reads return 0's" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " DREGDEPTH ,Dst Register FIFO Depth Parameterization" "0,1,2,3" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0's" group.byte 0x100++0x3 line.long 0x0 "EDMA_TPTCn_TCSTAT,TC Status Register" bitfld.long 0x0 0. " PROGBUSY ,Program Register Set Busy" "0,1" bitfld.long 0x0 1. " SRCACTV ,Source Active State" "0,1" textline " " bitfld.long 0x0 2. " WSACTV ,Write Status Active" "0,1" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--6. " DSTACTV ,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 8. " ACTV ,Channel Active Channel Active is a logical-OR of each of the *BUSY/ACTV signals. The ACTV bit must remain high through the life of a TR." "0,1" bitfld.long 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 11.--12. " DFSTRTPTR ,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO, in units of *entries*. Legal values = 0x0 to 0x3" "0,1,2,3" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x104++0x3 line.long 0x0 "EDMA_TPTCn_INTSTAT,Interrupt Status Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Status" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Status" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x108++0x3 line.long 0x0 "EDMA_TPTCn_INTEN,Interrupt Enable Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Enable" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x10C++0x3 line.long 0x0 "EDMA_TPTCn_INTCLR,Interrupt Clear Register" bitfld.long 0x0 0. " PROGEMPTY ,Program Set Empty Event Clear" "0,1" bitfld.long 0x0 1. " TRDONE ,TR Done Event Clear" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x110++0x3 line.long 0x0 "EDMA_TPTCn_INTCMD,Interrupt Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC interrupt" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x120++0x3 line.long 0x0 "EDMA_TPTCn_ERRSTAT,Error Status Register" bitfld.long 0x0 0. " BUSERR ,Bus Error Event" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,TR Error: TR detected that violates FIFO Mode transfer (SAM or DAM is '1') alignment rules or has ACNT or BCNT == 0. No additional error information is recorded." "0,1" bitfld.long 0x0 3. " MMRAERR ,MR Address Error" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x124++0x3 line.long 0x0 "EDMA_TPTCn_ERREN,Error Enable Register" bitfld.long 0x0 0. " BUSERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt enable forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x128++0x3 line.long 0x0 "EDMA_TPTCn_ERRCLR,Error Clear Register" bitfld.long 0x0 0. " BUSERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[0] BUSERR" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " TRERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[2] TRERR" "0,1" bitfld.long 0x0 3. " MMRAERR ,Interrupt clear forEDMA_TPTCn_ERRSTAT[3] MMRAERR" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x12C++0x3 line.long 0x0 "EDMA_TPTCn_ERRDET,Error Details Register" bitfld.long 0x0 0.--3. " STAT ,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs. write error code. If read status and write status are returned on the same cycle, then the TC chooses non-zero version. If both are non-zero then write status is treated as higher priority. Encoding of errors matches the CBA spec and is summarized here: 0xF =" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--13. " TCC ,Transfer Complete Code: Contains theEDMA_TPCC_OPT_n[13:8] TCC value programmed by the user for the Read or Write transaction that resulted in an error." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 16. " TCINTEN ,Contains theEDMA_TPCC_OPT_n[16] TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" bitfld.long 0x0 17. " TCCHEN ,Contains theEDMA_TPCC_OPT_n[17] TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "EDMA_TPTCn_ERRCMD,Error Command Register" bitfld.long 0x0 0. " EVAL ,Evaluate state of TPTC error interrupt Write of '1'" "0,1" bitfld.long 0x0 1. " SET ,Set TPTC error interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x140++0x3 line.long 0x0 "EDMA_TPTCn_RDRATE,Read Rate Register" bitfld.long 0x0 0.--2. " RDRATE ,Read Rate Control: Controls the number of cycles between read commands. This is a global setting that applies to all TRs for this TC." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "EDMA_TPTCn_POPT,Program Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority: 0x0: Priority 0 - Highest priority 0x1: Priority 1 ... 0x7: Priority 7 - Lowest priority" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control: Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER orEDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "EDMA_TPTCn_PSRC,Program Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Program Register Set" group.byte 0x208++0x3 line.long 0x0 "EDMA_TPTCn_PCNT,Program Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count. Number of bytes to be transferred in first dimension." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count. Number of arrays to be transferred, where each array is ACNT in length." group.byte 0x20C++0x3 line.long 0x0 "EDMA_TPTCn_PDST,Program Set Destination Address" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Program Register Set" group.byte 0x210++0x3 line.long 0x0 "EDMA_TPTCn_PBIDX,Program Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x214++0x3 line.long 0x0 "EDMA_TPTCn_PMPPRXY,Program Set Memory Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: EDMA_TPTCn_PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "EDMA_TPTCn_SAOPT,Source Actve Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in EDMA_TPCC_CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "EDMA_TPTCn_SASRC,Source Active Set Source Address" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address for Source Active Register Set: Initial value is copied from EDMA_TPTCn_PSRC.SADDR. TC updates value according to source addressing mode (EDMA_TPCC_OPT_n.SAM) and/or source index value (BIDX.SBIDX) after each read command is issued. When a TR is complete, the final value should be the address of the last read command issued." group.byte 0x248++0x3 line.long 0x0 "EDMA_TPTCn_SACNT,Source Active Set Count" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Dimension count: Number of bytes to be transferred in first dimension. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Dimension count: Number of arrays to be transferred, where each array is ACNT in length. Count Remaining for Source Active Register Set. Represents the amount of data remaining to be read. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each read command is issued. Final value should be 0 when TR is complete." group.byte 0x24C++0x3 line.long 0x0 "EDMA_TPTCn_SADST,Source Active Destination Address Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address is not applicable for Source Active Register Set. Reads return 0x0" group.byte 0x250++0x3 line.long 0x0 "EDMA_TPTCn_SABIDX,Source Active Set B-Dim Idx" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Source B-Idx for Source Active Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Destination B-Idx for Source Active Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x254++0x3 line.long 0x0 "EDMA_TPTCn_SAMPPRXY,Source Active Set Mem Protect Proxy" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID SAMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "EDMA_TPTCn_SACNTRLD,Source Active Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Source Active Register set. Value copied from EDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "EDMA_TPTCn_SASRCBREF,Source Active Set Source Address A-Reference" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference for Source Active Register Set: Represents the starting address for the array currently being read. The next array's starting address is calculated as the 'reference address' plus the 'source b-idx' value." group.byte 0x260++0x3 line.long 0x0 "EDMA_TPTCn_SADSTBREF,Source Active Destination Address B-Reference Register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference is not applicable for Src Active Register Set. Reads return 0x0." group.byte 0x280++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTRLD,Destination FIFO Set Count Reload" hexmask.long.word 0x0 0.--15. 1. " ACNTRLD ,A-Cnt Reload value for Destination FIFO Register set. Value copied fromEDMA_TPTCn_PCNT[15:0] ACNT: Represents the originally programmed value of ACNT. The Reload value is used to reinitialize ACNT after each array is serviced (i.e., ACNT decrements to 0). by the Src offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT bytes)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCBREF,Destination FIFO Set Destination Address B Reference Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDRBREF ,Source address reference is not applicable for Dst FIFO Register Set. Reads return 0x0." group.byte 0x288++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTBREF,Destination FIFO Set Destination Address A-Reference" hexmask.long 0x0 0.--31. 1. " DADDRBREF ,Destination address reference for Dst FIFO Register Set: Represents the starting address for the array currently being written. The next array's starting address is calculated as the 'reference address' plus the 'dest bidx' value." group.byte 0x300++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_0,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x340++0x3 line.long 0x0 "EDMA_TPTCn_DFOPTi_1,Destination FIFO Set Options" bitfld.long 0x0 0. " SAM ,Source Address Mode within an array" "0,1" bitfld.long 0x0 1. " DAM ,Destination Address Mode within an array" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4.--6. " PRI ,Transfer Priority... ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " FWID ,FIFO width control Applies if either SAM or DAM is set to FIFO mode." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--17. " TCC ,Transfer Complete Code The 6-bit code is used to set the relevant bit in CER or EDMA_TPCC_IPR of the TPCC module." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 18.--19. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 20. " TCINTEN ,Transfer complete interrupt enable" "0,1" textline " " bitfld.long 0x0 21. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 22. " TCCHEN ,Transfer complete chaining enable" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x304++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_0,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x344++0x3 line.long 0x0 "EDMA_TPTCn_DFSRCi_1,Destination FIFO source address register Reserved, return 0x0 w/o AERROR" hexmask.long 0x0 0.--31. 1. " SADDR ,Source address is not applicable for Dst FIFO Register Set: Reads return 0x0." group.byte 0x308++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_0,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x348++0x3 line.long 0x0 "EDMA_TPTCn_DFCNTi_1,Destination FIFO count register" hexmask.long.word 0x0 0.--15. 1. " ACNT ,A-Count Remaining for Dst Register Set: Number of bytes to be transferred in first dimension. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." hexmask.long.word 0x0 16.--31. 1. " BCNT ,B-Count Remaining for Dst Register Set: Number of arrays to be transferred, where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from EDMA_TPTCn_PCNT. TC decrements ACNT and BCNT as necessary after each write dataphase is issued. Final value should be 0 when TR is complete." group.byte 0x30C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_0,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x34C++0x3 line.long 0x0 "EDMA_TPTCn_DFDSTi_1,The destination FIFO destination address register" hexmask.long 0x0 0.--31. 1. " DADDR ,Destination address for Dst FIFO Register Set: Initial value is copied from EDMA_TPTCn_PDST[31:0] DADDR. TC updates value according to destination addressing mode (EDMA_TPCC_OPT_n. SAM) and/or dest index value (BIDX. DBIDX) after each write command is issued. When a TR is complete, the final value should be the address of the last write command issued." group.byte 0x310++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_0,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x350++0x3 line.long 0x0 "EDMA_TPTCn_DFBIDXi_1,The destination FIFO B-index register" hexmask.long.word 0x0 0.--15. 1. " SBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied fromEDMA_TPTCn_PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array (recall that there are BCNT arrays of ACNT elements). SBIDX is always used, regardless of whether SAM is Increment or FIFO mode." hexmask.long.word 0x0 16.--31. 1. " DBIDX ,Dest B-Idx for Dest FIFO Register Set. Value copied from EDMA_TPTCn_PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array (recall that there are BCNT arrays of ACNT elements). DBIDX is always used, regardless of whether DAM is Increment or FIFO mode." group.byte 0x314++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_0,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x354++0x3 line.long 0x0 "EDMA_TPTCn_DFMPPRXYi_1,The destination FIFO memory protection proxy register" bitfld.long 0x0 0.--3. " PRIVID ,Privilege ID: DFMPPRXY0.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register (trigger register). The PRIVID value for the SA Set and DF Set are copied from the value in the Program set along with the remainder of the parameter values. The privilege ID is issued on the VBusM read and write command bus such that the target endpoints can perform mMemory protection checks based on the privid of the external host that sets up the DMA transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PRIV ,Privilege Level" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "EVE1_MBOX0" base ad:0x4208B000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE1_MBOX1" base ad:0x4208C000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE1_MBOX2" base ad:0x4208D000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE1_MBOX3" base ad:0x4208E000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE1_MBOX4" base ad:0x4208F000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE2_MBOX0" base ad:0x4218B000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE2_MBOX1" base ad:0x4218C000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE2_MBOX2" base ad:0x4218D000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE2_MBOX3" base ad:0x4218E000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE2_MBOX4" base ad:0x4218F000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE3_MBOX0" base ad:0x4228B000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE3_MBOX1" base ad:0x4228C000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE3_MBOX2" base ad:0x4228D000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE3_MBOX3" base ad:0x4228E000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE3_MBOX4" base ad:0x4228F000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE4_MBOX0" base ad:0x4238B000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE4_MBOX1" base ad:0x4238C000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE4_MBOX2" base ad:0x4238D000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE4_MBOX3" base ad:0x4238E000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "EVE4_MBOX4" base ad:0x4238F000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x70++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_12,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x74++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_13,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x78++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_14,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x7C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_15,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_12,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_13,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xB8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_14,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xBC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_15,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_12,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_13,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xF8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_14,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xFC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_15,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX13" base ad:0x48802000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX2" base ad:0x4883A000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX3" base ad:0x4883C000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX4" base ad:0x4883E000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX5" base ad:0x48840000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX6" base ad:0x48842000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX7" base ad:0x48844000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX8" base ad:0x48846000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX9" base ad:0x4885E000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX10" base ad:0x48860000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX11" base ad:0x48862000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX12" base ad:0x48864000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x60++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_8,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x64++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_9,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x68++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_10,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x6C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_11,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA0++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_8,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA4++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_9,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xA8++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_10,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xAC++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_11,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_8,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_9,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xE8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_10,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xEC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_11,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "IVA_MBOX" base ad:0x5A05A800 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x130++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_3,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x134++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_3,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x138++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_3,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x13C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_3,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "MAILBOX1" base ad:0x4A0F4000 width 27. group.byte 0x0++0x3 line.long 0x0 "MAILBOX_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MAILBOX_SYSCONFIG,This register controls the various parameters of the communication interface" bitfld.long 0x0 0. " SOFTRESET ,Softreset" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " SIDLEMODE ,Idle Mode" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_0,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x44++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_1,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x48++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_2,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x4C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_3,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x50++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_4,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x54++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_5,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x58++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_6,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x5C++0x3 line.long 0x0 "MAILBOX_MESSAGE_m_7,The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." hexmask.long 0x0 0.--31. 1. " MESSAGEVALUEMBM ,Message in Mailbox" group.byte 0x80++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_0,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x84++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_1,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x88++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_2,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_3,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x90++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_4,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x94++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_5,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x98++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_6,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x9C++0x3 line.long 0x0 "MAILBOX_FIFOSTATUS_m_7,The FIFO status register has the status related to the mailbox internal FIFO" bitfld.long 0x0 0. " FIFOFULLMBM ,Full flag for Mailbox" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_0,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_1,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xC8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_2,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xCC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_3,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD0++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_4,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD4++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_5,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xD8++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_6,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0xDC++0x3 line.long 0x0 "MAILBOX_MSGSTATUS_m_7,The message status register has the status of the messages in the mailbox." bitfld.long 0x0 0.--2. " NBOFMSGMBM ,Number of unread messages in Mailbox Note: Limited to four messages per mailbox." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved. Read returns 0" group.byte 0x100++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_0,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x110++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_1,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x120++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_RAW_u_2,The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." bitfld.long 0x0 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x104++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_0,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x114++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_1,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x124++0x3 line.long 0x0 "MAILBOX_IRQSTATUS_CLR_u_2,The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" bitfld.long 0x0 0. " NEWMSGSTATUSENUUMB0 ,NewMessage Status bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLSTATUSENUUMB0 ,NotFull Status bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGSTATUSENUUMB1 ,NewMessage Status bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLSTATUSENUUMB1 ,NotFull Status bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGSTATUSENUUMB2 ,NewMessage Status bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLSTATUSENUUMB2 ,NotFull Status bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGSTATUSENUUMB3 ,NewMessage Status bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLSTATUSENUUMB3 ,NotFull Status bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGSTATUSENUUMB4 ,NewMessage Status bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLSTATUSENUUMB4 ,NotFull Status bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGSTATUSENUUMB5 ,NewMessage Status bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLSTATUSENUUMB5 ,NotFull Status bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGSTATUSENUUMB6 ,NewMessage Status bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLSTATUSENUUMB6 ,NotFull Status bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGSTATUSENUUMB7 ,NewMessage Status bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLSTATUSENUUMB7 ,NotFull Status bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGSTATUSENUUMB8 ,NewMessage Status bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLSTATUSENUUMB8 ,NotFull Status bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGSTATUSENUUMB9 ,NewMessage Status bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLSTATUSENUUMB9 ,NotFull Status bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGSTATUSENUUMB10 ,NewMessage Status bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLSTATUSENUUMB10 ,NotFull Status bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGSTATUSENUUMB11 ,NewMessage Status bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLSTATUSENUUMB11 ,NotFull Status bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGSTATUSENUUMB12 ,NewMessage Status bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLSTATUSENUUMB12 ,NotFull Status bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGSTATUSENUUMB13 ,NewMessage Status bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLSTATUSENUUMB13 ,NotFull Status bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGSTATUSENUUMB14 ,NewMessage Status bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLSTATUSENUUMB14 ,NotFull Status bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGSTATUSENUUMB15 ,NewMessage Status bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLSTATUSENUUMB15 ,NotFull Status bit for User u, Mailbox 15" "0,1" group.byte 0x108++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_0,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x118++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_1,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x128++0x3 line.long 0x0 "MAILBOX_IRQENABLE_SET_u_2,The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x10C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_0,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x11C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_1,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x12C++0x3 line.long 0x0 "MAILBOX_IRQENABLE_CLR_u_2,The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." bitfld.long 0x0 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u, Mailbox 0" "0,1" bitfld.long 0x0 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u, Mailbox 0" "0,1" textline " " bitfld.long 0x0 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u, Mailbox 1" "0,1" bitfld.long 0x0 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u, Mailbox 1" "0,1" textline " " bitfld.long 0x0 4. " NEWMSGENABLEUUMB2 ,NewMessage Enable bit for User u, Mailbox 2" "0,1" bitfld.long 0x0 5. " NOTFULLENABLEUUMB2 ,NotFull Enable bit for User u, Mailbox 2" "0,1" textline " " bitfld.long 0x0 6. " NEWMSGENABLEUUMB3 ,NewMessage Enable bit for User u, Mailbox 3" "0,1" bitfld.long 0x0 7. " NOTFULLENABLEUUMB3 ,NotFull Enable bit for User u, Mailbox 3" "0,1" textline " " bitfld.long 0x0 8. " NEWMSGENABLEUUMB4 ,NewMessage Enable bit for User u, Mailbox 4" "0,1" bitfld.long 0x0 9. " NOTFULLENABLEUUMB4 ,NotFull Enable bit for User u, Mailbox 4" "0,1" textline " " bitfld.long 0x0 10. " NEWMSGENABLEUUMB5 ,NewMessage Enable bit for User u, Mailbox 5" "0,1" bitfld.long 0x0 11. " NOTFULLENABLEUUMB5 ,NotFull Enable bit for User u, Mailbox 5" "0,1" textline " " bitfld.long 0x0 12. " NEWMSGENABLEUUMB6 ,NewMessage Enable bit for User u, Mailbox 6" "0,1" bitfld.long 0x0 13. " NOTFULLENABLEUUMB6 ,NotFull Enable bit for User u, Mailbox 6" "0,1" textline " " bitfld.long 0x0 14. " NEWMSGENABLEUUMB7 ,NewMessage Enable bit for User u, Mailbox 7" "0,1" bitfld.long 0x0 15. " NOTFULLENABLEUUMB7 ,NotFull Enable bit for User u, Mailbox 7" "0,1" textline " " bitfld.long 0x0 16. " NEWMSGENABLEUUMB8 ,NewMessage Enable bit for User u, Mailbox 8" "0,1" bitfld.long 0x0 17. " NOTFULLENABLEUUMB8 ,NotFull Enable bit for User u, Mailbox 8" "0,1" textline " " bitfld.long 0x0 18. " NEWMSGENABLEUUMB9 ,NewMessage Enable bit for User u, Mailbox 9" "0,1" bitfld.long 0x0 19. " NOTFULLENABLEUUMB9 ,NotFull Enable bit for User u, Mailbox 9" "0,1" textline " " bitfld.long 0x0 20. " NEWMSGENABLEUUMB10 ,NewMessage Enable bit for User u, Mailbox 10" "0,1" bitfld.long 0x0 21. " NOTFULLENABLEUUMB10 ,NotFull Enable bit for User u, Mailbox 10" "0,1" textline " " bitfld.long 0x0 22. " NEWMSGENABLEUUMB11 ,NewMessage Enable bit for User u, Mailbox 11" "0,1" bitfld.long 0x0 23. " NOTFULLENABLEUUMB11 ,NotFull Enable bit for User u, Mailbox 11" "0,1" textline " " bitfld.long 0x0 24. " NEWMSGENABLEUUMB12 ,NewMessage Enable bit for User u, Mailbox 12" "0,1" bitfld.long 0x0 25. " NOTFULLENABLEUUMB12 ,NotFull Enable bit for User u, Mailbox 12" "0,1" textline " " bitfld.long 0x0 26. " NEWMSGENABLEUUMB13 ,NewMessage Enable bit for User u, Mailbox 13" "0,1" bitfld.long 0x0 27. " NOTFULLENABLEUUMB13 ,NotFull Enable bit for User u, Mailbox 13" "0,1" textline " " bitfld.long 0x0 28. " NEWMSGENABLEUUMB14 ,NewMessage Enable bit for User u, Mailbox 14" "0,1" bitfld.long 0x0 29. " NOTFULLENABLEUUMB14 ,NotFull Enable bit for User u, Mailbox 14" "0,1" textline " " bitfld.long 0x0 30. " NEWMSGENABLEUUMB15 ,NewMessage Enable bit for User u, Mailbox 15" "0,1" bitfld.long 0x0 31. " NOTFULLENABLEUUMB15 ,NotFull Enable bit for User u, Mailbox 15" "0,1" group.byte 0x140++0x3 line.long 0x0 "MAILBOX_IRQ_EOI,This register is used for the software EOI clearance of the pulse. This register being write only gives 0 on read." bitfld.long 0x0 0.--1. " EOIVAL ,EOI value" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads returns 0" width 0x0B tree.end tree "IODELAYCONFIG" base ad:0x4844A000 width 25. group.byte 0xC++0x3 line.long 0x0 "CONFIG_REG_0,Calibration Control Register" bitfld.long 0x0 0. " CALIBRATION_START ,Triggers hardware calibration when '1' is written. Cleared when hardware completes calibration." "0,1" bitfld.long 0x0 1. " ROM_READ ,Triggers complete ROM read when '1' is written. Cleared when ROM read is complete." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "CONFIG_REG_2,Reference Clock Period Register." hexmask.long.word 0x0 0.--15. 1. " REFCLK_PERIOD ,15:0 stores the binary equivalent of reference clock period in units of 10ps. This value (along with calibration results) is used for computing the coarse/fine element delay Example: 0xF0 means 2400ps." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "CONFIG_REG_3,coarse calibration results register" hexmask.long.word 0x0 0.--15. 1. " COARSE_REF_COUNT ,Results of 16 bit counter clocked by 'reference' clock during coarse calibration." hexmask.long.word 0x0 16.--31. 1. " COARSE_DELAY_COUNT ,Results of 16 bit counter clocked by 'delay line oscillator' clock during calibration." group.byte 0x1C++0x3 line.long 0x0 "CONFIG_REG_4,fine calibration results register" hexmask.long.word 0x0 0.--15. 1. " FINE_REF_COUNT ,Results of 16 bit counter clocked by 'reference' clock during fine calibration." hexmask.long.word 0x0 16.--31. 1. " FINE_DELAY_COUNT ,Results of 16 bit counter clocked by 'delay line oscillator' clock during fine calibration." group.byte 0x2C++0x3 line.long 0x0 "CONFIG_REG_8,Global Lock Register." bitfld.long 0x0 0. " GLOBAL_LOCK_BIT ,Global Lock Bit Register. A '1' in this bit protects the writes to MMRs that store delay line select values. A '0' in this bit indicates that MMRs that store delay line select values are writeable. To write a '0' to this bit, signature of 0x5555 must be used on the MSB bits 16:1 of mdata." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "CFG_RMII_MHZ_50_CLK_IN,Delay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "CFG_RMII_MHZ_50_CLK_OEN,Delay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "CFG_RMII_MHZ_50_CLK_OUT,Delay Select Value in binary coded form for cfg_RMII_MHZ_50_CLK_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "CFG_WAKEUP0_IN,Delay Select Value in binary coded form for cfg_Wakeup0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "CFG_WAKEUP0_OEN,Delay Select Value in binary coded form for cfg_Wakeup0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "CFG_WAKEUP0_OUT,Delay Select Value in binary coded form for cfg_Wakeup0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "CFG_WAKEUP1_IN,Delay Select Value in binary coded form for cfg_Wakeup1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "CFG_WAKEUP1_OEN,Delay Select Value in binary coded form for cfg_Wakeup1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "CFG_WAKEUP1_OUT,Delay Select Value in binary coded form for cfg_Wakeup1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "CFG_WAKEUP2_IN,Delay Select Value in binary coded form for cfg_Wakeup2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x58++0x3 line.long 0x0 "CFG_WAKEUP2_OEN,Delay Select Value in binary coded form for cfg_Wakeup2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "CFG_WAKEUP2_OUT,Delay Select Value in binary coded form for cfg_Wakeup2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "CFG_WAKEUP3_IN,Delay Select Value in binary coded form for cfg_Wakeup3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "CFG_WAKEUP3_OEN,Delay Select Value in binary coded form for cfg_Wakeup3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "CFG_WAKEUP3_OUT,Delay Select Value in binary coded form for cfg_Wakeup3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "CFG_DCAN1_RX_IN,Delay Select Value in binary coded form for cfg_dcan1_rx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "CFG_DCAN1_RX_OEN,Delay Select Value in binary coded form for cfg_dcan1_rx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "CFG_DCAN1_RX_OUT,Delay Select Value in binary coded form for cfg_dcan1_rx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "CFG_DCAN1_TX_IN,Delay Select Value in binary coded form for cfg_dcan1_tx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "CFG_DCAN1_TX_OEN,Delay Select Value in binary coded form for cfg_dcan1_tx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "CFG_DCAN1_TX_OUT,Delay Select Value in binary coded form for cfg_dcan1_tx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "CFG_DCAN2_RX_IN,Delay Select Value in binary coded form for cfg_dcan2_rx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CFG_DCAN2_RX_OEN,Delay Select Value in binary coded form for cfg_dcan2_rx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "CFG_DCAN2_RX_OUT,Delay Select Value in binary coded form for cfg_dcan2_rx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "CFG_DCAN2_TX_IN,Delay Select Value in binary coded form for cfg_dcan2_tx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "CFG_DCAN2_TX_OEN,Delay Select Value in binary coded form for cfg_dcan2_tx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "CFG_DCAN2_TX_OUT,Delay Select Value in binary coded form for cfg_dcan2_tx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "CFG_EMU0_IN,Delay Select Value in binary coded form for cfg_emu0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "CFG_EMU0_OEN,Delay Select Value in binary coded form for cfg_emu0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "CFG_EMU0_OUT,Delay Select Value in binary coded form for cfg_emu0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "CFG_EMU1_IN,Delay Select Value in binary coded form for cfg_emu1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAC++0x3 line.long 0x0 "CFG_EMU1_OEN,Delay Select Value in binary coded form for cfg_emu1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB0++0x3 line.long 0x0 "CFG_EMU1_OUT,Delay Select Value in binary coded form for cfg_emu1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "CFG_EMU2_IN,Delay Select Value in binary coded form for cfg_emu2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "CFG_EMU2_OEN,Delay Select Value in binary coded form for cfg_emu2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "CFG_EMU2_OUT,Delay Select Value in binary coded form for cfg_emu2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC0++0x3 line.long 0x0 "CFG_EMU3_IN,Delay Select Value in binary coded form for cfg_emu3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC4++0x3 line.long 0x0 "CFG_EMU3_OEN,Delay Select Value in binary coded form for cfg_emu3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC8++0x3 line.long 0x0 "CFG_EMU3_OUT,Delay Select Value in binary coded form for cfg_emu3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCC++0x3 line.long 0x0 "CFG_EMU4_IN,Delay Select Value in binary coded form for cfg_emu4_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "CFG_EMU4_OEN,Delay Select Value in binary coded form for cfg_emu4_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD4++0x3 line.long 0x0 "CFG_EMU4_OUT,Delay Select Value in binary coded form for cfg_emu4_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD8++0x3 line.long 0x0 "CFG_GPIO6_10_IN,Delay Select Value in binary coded form for cfg_gpio6_10_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xDC++0x3 line.long 0x0 "CFG_GPIO6_10_OEN,Delay Select Value in binary coded form for cfg_gpio6_10_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "CFG_GPIO6_10_OUT,Delay Select Value in binary coded form for cfg_gpio6_10_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xE4++0x3 line.long 0x0 "CFG_GPIO6_11_IN,Delay Select Value in binary coded form for cfg_gpio6_11_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xE8++0x3 line.long 0x0 "CFG_GPIO6_11_OEN,Delay Select Value in binary coded form for cfg_gpio6_11_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xEC++0x3 line.long 0x0 "CFG_GPIO6_11_OUT,Delay Select Value in binary coded form for cfg_gpio6_11_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "CFG_GPIO6_14_IN,Delay Select Value in binary coded form for cfg_gpio6_14_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xF4++0x3 line.long 0x0 "CFG_GPIO6_14_OEN,Delay Select Value in binary coded form for cfg_gpio6_14_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xF8++0x3 line.long 0x0 "CFG_GPIO6_14_OUT,Delay Select Value in binary coded form for cfg_gpio6_14_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xFC++0x3 line.long 0x0 "CFG_GPIO6_15_IN,Delay Select Value in binary coded form for cfg_gpio6_15_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "CFG_GPIO6_15_OEN,Delay Select Value in binary coded form for cfg_gpio6_15_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "CFG_GPIO6_15_OUT,Delay Select Value in binary coded form for cfg_gpio6_15_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "CFG_GPIO6_16_IN,Delay Select Value in binary coded form for cfg_gpio6_16_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "CFG_GPIO6_16_OEN,Delay Select Value in binary coded form for cfg_gpio6_16_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "CFG_GPIO6_16_OUT,Delay Select Value in binary coded form for cfg_gpio6_16_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x114++0x3 line.long 0x0 "CFG_GPMC_A0_IN,Delay Select Value in binary coded form for cfg_gpmc_a0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x118++0x3 line.long 0x0 "CFG_GPMC_A0_OEN,Delay Select Value in binary coded form for cfg_gpmc_a0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x11C++0x3 line.long 0x0 "CFG_GPMC_A0_OUT,Delay Select Value in binary coded form for cfg_gpmc_a0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x120++0x3 line.long 0x0 "CFG_GPMC_A10_IN,Delay Select Value in binary coded form for cfg_gpmc_a10_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "CFG_GPMC_A10_OEN,Delay Select Value in binary coded form for cfg_gpmc_a10_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x128++0x3 line.long 0x0 "CFG_GPMC_A10_OUT,Delay Select Value in binary coded form for cfg_gpmc_a10_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x12C++0x3 line.long 0x0 "CFG_GPMC_A11_IN,Delay Select Value in binary coded form for cfg_gpmc_a11_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "CFG_GPMC_A11_OEN,Delay Select Value in binary coded form for cfg_gpmc_a11_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x134++0x3 line.long 0x0 "CFG_GPMC_A11_OUT,Delay Select Value in binary coded form for cfg_gpmc_a11_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x138++0x3 line.long 0x0 "CFG_GPMC_A12_IN,Delay Select Value in binary coded form for cfg_gpmc_a12_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x13C++0x3 line.long 0x0 "CFG_GPMC_A12_OEN,Delay Select Value in binary coded form for cfg_gpmc_a12_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x140++0x3 line.long 0x0 "CFG_GPMC_A12_OUT,Delay Select Value in binary coded form for cfg_gpmc_a12_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x144++0x3 line.long 0x0 "CFG_GPMC_A13_IN,Delay Select Value in binary coded form for cfg_gpmc_a13_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x148++0x3 line.long 0x0 "CFG_GPMC_A13_OEN,Delay Select Value in binary coded form for cfg_gpmc_a13_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14C++0x3 line.long 0x0 "CFG_GPMC_A13_OUT,Delay Select Value in binary coded form for cfg_gpmc_a13_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x150++0x3 line.long 0x0 "CFG_GPMC_A14_IN,Delay Select Value in binary coded form for cfg_gpmc_a14_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x154++0x3 line.long 0x0 "CFG_GPMC_A14_OEN,Delay Select Value in binary coded form for cfg_gpmc_a14_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x158++0x3 line.long 0x0 "CFG_GPMC_A14_OUT,Delay Select Value in binary coded form for cfg_gpmc_a14_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x15C++0x3 line.long 0x0 "CFG_GPMC_A15_IN,Delay Select Value in binary coded form for cfg_gpmc_a15_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x160++0x3 line.long 0x0 "CFG_GPMC_A15_OEN,Delay Select Value in binary coded form for cfg_gpmc_a15_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x164++0x3 line.long 0x0 "CFG_GPMC_A15_OUT,Delay Select Value in binary coded form for cfg_gpmc_a15_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x168++0x3 line.long 0x0 "CFG_GPMC_A16_IN,Delay Select Value in binary coded form for cfg_gpmc_a16_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x16C++0x3 line.long 0x0 "CFG_GPMC_A16_OEN,Delay Select Value in binary coded form for cfg_gpmc_a16_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x170++0x3 line.long 0x0 "CFG_GPMC_A16_OUT,Delay Select Value in binary coded form for cfg_gpmc_a16_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x174++0x3 line.long 0x0 "CFG_GPMC_A17_IN,Delay Select Value in binary coded form for cfg_gpmc_a17_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x178++0x3 line.long 0x0 "CFG_GPMC_A17_OEN,Delay Select Value in binary coded form for cfg_gpmc_a17_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x17C++0x3 line.long 0x0 "CFG_GPMC_A17_OUT,Delay Select Value in binary coded form for cfg_gpmc_a17_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x180++0x3 line.long 0x0 "CFG_GPMC_A18_IN,Delay Select Value in binary coded form for cfg_gpmc_a18_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x184++0x3 line.long 0x0 "CFG_GPMC_A18_OEN,Delay Select Value in binary coded form for cfg_gpmc_a18_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x188++0x3 line.long 0x0 "CFG_GPMC_A18_OUT,Delay Select Value in binary coded form for cfg_gpmc_a18_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x18C++0x3 line.long 0x0 "CFG_GPMC_A19_IN,Delay Select Value in binary coded form for cfg_gpmc_a19_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x190++0x3 line.long 0x0 "CFG_GPMC_A19_OEN,Delay Select Value in binary coded form for cfg_gpmc_a19_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x194++0x3 line.long 0x0 "CFG_GPMC_A19_OUT,Delay Select Value in binary coded form for cfg_gpmc_a19_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x198++0x3 line.long 0x0 "CFG_GPMC_A1_IN,Delay Select Value in binary coded form for cfg_gpmc_a1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x19C++0x3 line.long 0x0 "CFG_GPMC_A1_OEN,Delay Select Value in binary coded form for cfg_gpmc_a1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1A0++0x3 line.long 0x0 "CFG_GPMC_A1_OUT,Delay Select Value in binary coded form for cfg_gpmc_a1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1A4++0x3 line.long 0x0 "CFG_GPMC_A20_IN,Delay Select Value in binary coded form for cfg_gpmc_a20_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1A8++0x3 line.long 0x0 "CFG_GPMC_A20_OEN,Delay Select Value in binary coded form for cfg_gpmc_a20_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1AC++0x3 line.long 0x0 "CFG_GPMC_A20_OUT,Delay Select Value in binary coded form for cfg_gpmc_a20_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1B0++0x3 line.long 0x0 "CFG_GPMC_A21_IN,Delay Select Value in binary coded form for cfg_gpmc_a21_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1B4++0x3 line.long 0x0 "CFG_GPMC_A21_OEN,Delay Select Value in binary coded form for cfg_gpmc_a21_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1B8++0x3 line.long 0x0 "CFG_GPMC_A21_OUT,Delay Select Value in binary coded form for cfg_gpmc_a21_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1BC++0x3 line.long 0x0 "CFG_GPMC_A22_IN,Delay Select Value in binary coded form for cfg_gpmc_a22_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1C0++0x3 line.long 0x0 "CFG_GPMC_A22_OEN,Delay Select Value in binary coded form for cfg_gpmc_a22_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1C4++0x3 line.long 0x0 "CFG_GPMC_A22_OUT,Delay Select Value in binary coded form for cfg_gpmc_a22_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1C8++0x3 line.long 0x0 "CFG_GPMC_A23_IN,Delay Select Value in binary coded form for cfg_gpmc_a23_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1CC++0x3 line.long 0x0 "CFG_GPMC_A23_OEN,Delay Select Value in binary coded form for cfg_gpmc_a23_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1D0++0x3 line.long 0x0 "CFG_GPMC_A23_OUT,Delay Select Value in binary coded form for cfg_gpmc_a23_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1D4++0x3 line.long 0x0 "CFG_GPMC_A24_IN,Delay Select Value in binary coded form for cfg_gpmc_a24_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1D8++0x3 line.long 0x0 "CFG_GPMC_A24_OEN,Delay Select Value in binary coded form for cfg_gpmc_a24_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1DC++0x3 line.long 0x0 "CFG_GPMC_A24_OUT,Delay Select Value in binary coded form for cfg_gpmc_a24_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1E0++0x3 line.long 0x0 "CFG_GPMC_A25_IN,Delay Select Value in binary coded form for cfg_gpmc_a25_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1E4++0x3 line.long 0x0 "CFG_GPMC_A25_OEN,Delay Select Value in binary coded form for cfg_gpmc_a25_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1E8++0x3 line.long 0x0 "CFG_GPMC_A25_OUT,Delay Select Value in binary coded form for cfg_gpmc_a25_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1EC++0x3 line.long 0x0 "CFG_GPMC_A26_IN,Delay Select Value in binary coded form for cfg_gpmc_a26_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1F0++0x3 line.long 0x0 "CFG_GPMC_A26_OEN,Delay Select Value in binary coded form for cfg_gpmc_a26_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1F4++0x3 line.long 0x0 "CFG_GPMC_A26_OUT,Delay Select Value in binary coded form for cfg_gpmc_a26_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1F8++0x3 line.long 0x0 "CFG_GPMC_A27_IN,Delay Select Value in binary coded form for cfg_gpmc_a27_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1FC++0x3 line.long 0x0 "CFG_GPMC_A27_OEN,Delay Select Value in binary coded form for cfg_gpmc_a27_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x200++0x3 line.long 0x0 "CFG_GPMC_A27_OUT,Delay Select Value in binary coded form for cfg_gpmc_a27_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x204++0x3 line.long 0x0 "CFG_GPMC_A2_IN,Delay Select Value in binary coded form for cfg_gpmc_a2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "CFG_GPMC_A2_OEN,Delay Select Value in binary coded form for cfg_gpmc_a2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "CFG_GPMC_A2_OUT,Delay Select Value in binary coded form for cfg_gpmc_a2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "CFG_GPMC_A3_IN,Delay Select Value in binary coded form for cfg_gpmc_a3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "CFG_GPMC_A3_OEN,Delay Select Value in binary coded form for cfg_gpmc_a3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x218++0x3 line.long 0x0 "CFG_GPMC_A3_OUT,Delay Select Value in binary coded form for cfg_gpmc_a3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x21C++0x3 line.long 0x0 "CFG_GPMC_A4_IN,Delay Select Value in binary coded form for cfg_gpmc_a4_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x220++0x3 line.long 0x0 "CFG_GPMC_A4_OEN,Delay Select Value in binary coded form for cfg_gpmc_a4_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "CFG_GPMC_A4_OUT,Delay Select Value in binary coded form for cfg_gpmc_a4_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x228++0x3 line.long 0x0 "CFG_GPMC_A5_IN,Delay Select Value in binary coded form for cfg_gpmc_a5_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x22C++0x3 line.long 0x0 "CFG_GPMC_A5_OEN,Delay Select Value in binary coded form for cfg_gpmc_a5_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "CFG_GPMC_A5_OUT,Delay Select Value in binary coded form for cfg_gpmc_a5_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x234++0x3 line.long 0x0 "CFG_GPMC_A6_IN,Delay Select Value in binary coded form for cfg_gpmc_a6_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x238++0x3 line.long 0x0 "CFG_GPMC_A6_OEN,Delay Select Value in binary coded form for cfg_gpmc_a6_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x23C++0x3 line.long 0x0 "CFG_GPMC_A6_OUT,Delay Select Value in binary coded form for cfg_gpmc_a6_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x240++0x3 line.long 0x0 "CFG_GPMC_A7_IN,Delay Select Value in binary coded form for cfg_gpmc_a7_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x244++0x3 line.long 0x0 "CFG_GPMC_A7_OEN,Delay Select Value in binary coded form for cfg_gpmc_a7_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x248++0x3 line.long 0x0 "CFG_GPMC_A7_OUT,Delay Select Value in binary coded form for cfg_gpmc_a7_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x24C++0x3 line.long 0x0 "CFG_GPMC_A8_IN,Delay Select Value in binary coded form for cfg_gpmc_a8_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "CFG_GPMC_A8_OEN,Delay Select Value in binary coded form for cfg_gpmc_a8_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x254++0x3 line.long 0x0 "CFG_GPMC_A8_OUT,Delay Select Value in binary coded form for cfg_gpmc_a8_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x258++0x3 line.long 0x0 "CFG_GPMC_A9_IN,Delay Select Value in binary coded form for cfg_gpmc_a9_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x25C++0x3 line.long 0x0 "CFG_GPMC_A9_OEN,Delay Select Value in binary coded form for cfg_gpmc_a9_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x260++0x3 line.long 0x0 "CFG_GPMC_A9_OUT,Delay Select Value in binary coded form for cfg_gpmc_a9_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x264++0x3 line.long 0x0 "CFG_GPMC_AD0_IN,Delay Select Value in binary coded form for cfg_gpmc_ad0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x268++0x3 line.long 0x0 "CFG_GPMC_AD0_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x26C++0x3 line.long 0x0 "CFG_GPMC_AD0_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x270++0x3 line.long 0x0 "CFG_GPMC_AD10_IN,Delay Select Value in binary coded form for cfg_gpmc_ad10_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x274++0x3 line.long 0x0 "CFG_GPMC_AD10_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad10_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x278++0x3 line.long 0x0 "CFG_GPMC_AD10_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad10_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x27C++0x3 line.long 0x0 "CFG_GPMC_AD11_IN,Delay Select Value in binary coded form for cfg_gpmc_ad11_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x280++0x3 line.long 0x0 "CFG_GPMC_AD11_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad11_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x284++0x3 line.long 0x0 "CFG_GPMC_AD11_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad11_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x288++0x3 line.long 0x0 "CFG_GPMC_AD12_IN,Delay Select Value in binary coded form for cfg_gpmc_ad12_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x28C++0x3 line.long 0x0 "CFG_GPMC_AD12_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad12_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x290++0x3 line.long 0x0 "CFG_GPMC_AD12_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad12_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x294++0x3 line.long 0x0 "CFG_GPMC_AD13_IN,Delay Select Value in binary coded form for cfg_gpmc_ad13_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x298++0x3 line.long 0x0 "CFG_GPMC_AD13_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad13_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x29C++0x3 line.long 0x0 "CFG_GPMC_AD13_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad13_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2A0++0x3 line.long 0x0 "CFG_GPMC_AD14_IN,Delay Select Value in binary coded form for cfg_gpmc_ad14_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2A4++0x3 line.long 0x0 "CFG_GPMC_AD14_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad14_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2A8++0x3 line.long 0x0 "CFG_GPMC_AD14_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad14_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2AC++0x3 line.long 0x0 "CFG_GPMC_AD15_IN,Delay Select Value in binary coded form for cfg_gpmc_ad15_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2B0++0x3 line.long 0x0 "CFG_GPMC_AD15_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad15_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2B4++0x3 line.long 0x0 "CFG_GPMC_AD15_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad15_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2B8++0x3 line.long 0x0 "CFG_GPMC_AD1_IN,Delay Select Value in binary coded form for cfg_gpmc_ad1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2BC++0x3 line.long 0x0 "CFG_GPMC_AD1_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2C0++0x3 line.long 0x0 "CFG_GPMC_AD1_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2C4++0x3 line.long 0x0 "CFG_GPMC_AD2_IN,Delay Select Value in binary coded form for cfg_gpmc_ad2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2C8++0x3 line.long 0x0 "CFG_GPMC_AD2_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2CC++0x3 line.long 0x0 "CFG_GPMC_AD2_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2D0++0x3 line.long 0x0 "CFG_GPMC_AD3_IN,Delay Select Value in binary coded form for cfg_gpmc_ad3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2D4++0x3 line.long 0x0 "CFG_GPMC_AD3_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2D8++0x3 line.long 0x0 "CFG_GPMC_AD3_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2DC++0x3 line.long 0x0 "CFG_GPMC_AD4_IN,Delay Select Value in binary coded form for cfg_gpmc_ad4_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2E0++0x3 line.long 0x0 "CFG_GPMC_AD4_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad4_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2E4++0x3 line.long 0x0 "CFG_GPMC_AD4_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad4_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2E8++0x3 line.long 0x0 "CFG_GPMC_AD5_IN,Delay Select Value in binary coded form for cfg_gpmc_ad5_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2EC++0x3 line.long 0x0 "CFG_GPMC_AD5_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad5_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2F0++0x3 line.long 0x0 "CFG_GPMC_AD5_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad5_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2F4++0x3 line.long 0x0 "CFG_GPMC_AD6_IN,Delay Select Value in binary coded form for cfg_gpmc_ad6_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2F8++0x3 line.long 0x0 "CFG_GPMC_AD6_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad6_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x2FC++0x3 line.long 0x0 "CFG_GPMC_AD6_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad6_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x300++0x3 line.long 0x0 "CFG_GPMC_AD7_IN,Delay Select Value in binary coded form for cfg_gpmc_ad7_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x304++0x3 line.long 0x0 "CFG_GPMC_AD7_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad7_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x308++0x3 line.long 0x0 "CFG_GPMC_AD7_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad7_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x30C++0x3 line.long 0x0 "CFG_GPMC_AD8_IN,Delay Select Value in binary coded form for cfg_gpmc_ad8_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x310++0x3 line.long 0x0 "CFG_GPMC_AD8_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad8_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x314++0x3 line.long 0x0 "CFG_GPMC_AD8_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad8_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x318++0x3 line.long 0x0 "CFG_GPMC_AD9_IN,Delay Select Value in binary coded form for cfg_gpmc_ad9_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x31C++0x3 line.long 0x0 "CFG_GPMC_AD9_OEN,Delay Select Value in binary coded form for cfg_gpmc_ad9_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x320++0x3 line.long 0x0 "CFG_GPMC_AD9_OUT,Delay Select Value in binary coded form for cfg_gpmc_ad9_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x324++0x3 line.long 0x0 "CFG_GPMC_ADVN_ALE_IN,Delay Select Value in binary coded form for cfg_gpmc_advn_ale_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x328++0x3 line.long 0x0 "CFG_GPMC_ADVN_ALE_OEN,Delay Select Value in binary coded form for cfg_gpmc_advn_ale_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x32C++0x3 line.long 0x0 "CFG_GPMC_ADVN_ALE_OUT,Delay Select Value in binary coded form for cfg_gpmc_advn_ale_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x330++0x3 line.long 0x0 "CFG_GPMC_BEN0_IN,Delay Select Value in binary coded form for cfg_gpmc_ben0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x334++0x3 line.long 0x0 "CFG_GPMC_BEN0_OEN,Delay Select Value in binary coded form for cfg_gpmc_ben0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x338++0x3 line.long 0x0 "CFG_GPMC_BEN0_OUT,Delay Select Value in binary coded form for cfg_gpmc_ben0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x33C++0x3 line.long 0x0 "CFG_GPMC_BEN1_IN,Delay Select Value in binary coded form for cfg_gpmc_ben1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x340++0x3 line.long 0x0 "CFG_GPMC_BEN1_OEN,Delay Select Value in binary coded form for cfg_gpmc_ben1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x344++0x3 line.long 0x0 "CFG_GPMC_BEN1_OUT,Delay Select Value in binary coded form for cfg_gpmc_ben1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x348++0x3 line.long 0x0 "CFG_GPMC_CLK_IN,Delay Select Value in binary coded form for cfg_gpmc_clk_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x34C++0x3 line.long 0x0 "CFG_GPMC_CLK_OEN,Delay Select Value in binary coded form for cfg_gpmc_clk_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x350++0x3 line.long 0x0 "CFG_GPMC_CLK_OUT,Delay Select Value in binary coded form for cfg_gpmc_clk_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x354++0x3 line.long 0x0 "CFG_GPMC_CS0_IN,Delay Select Value in binary coded form for cfg_gpmc_cs0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x358++0x3 line.long 0x0 "CFG_GPMC_CS0_OEN,Delay Select Value in binary coded form for cfg_gpmc_cs0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x35C++0x3 line.long 0x0 "CFG_GPMC_CS0_OUT,Delay Select Value in binary coded form for cfg_gpmc_cs0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "CFG_GPMC_CS1_IN,Delay Select Value in binary coded form for cfg_gpmc_cs1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x364++0x3 line.long 0x0 "CFG_GPMC_CS1_OEN,Delay Select Value in binary coded form for cfg_gpmc_cs1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x368++0x3 line.long 0x0 "CFG_GPMC_CS1_OUT,Delay Select Value in binary coded form for cfg_gpmc_cs1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x36C++0x3 line.long 0x0 "CFG_GPMC_CS2_IN,Delay Select Value in binary coded form for cfg_gpmc_cs2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x370++0x3 line.long 0x0 "CFG_GPMC_CS2_OEN,Delay Select Value in binary coded form for cfg_gpmc_cs2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x374++0x3 line.long 0x0 "CFG_GPMC_CS2_OUT,Delay Select Value in binary coded form for cfg_gpmc_cs2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x378++0x3 line.long 0x0 "CFG_GPMC_CS3_IN,Delay Select Value in binary coded form for cfg_gpmc_cs3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x37C++0x3 line.long 0x0 "CFG_GPMC_CS3_OEN,Delay Select Value in binary coded form for cfg_gpmc_cs3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x380++0x3 line.long 0x0 "CFG_GPMC_CS3_OUT,Delay Select Value in binary coded form for cfg_gpmc_cs3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x384++0x3 line.long 0x0 "CFG_GPMC_OEN_REN_IN,Delay Select Value in binary coded form for cfg_gpmc_oen_ren_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x388++0x3 line.long 0x0 "CFG_GPMC_OEN_REN_OEN,Delay Select Value in binary coded form for cfg_gpmc_oen_ren_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x38C++0x3 line.long 0x0 "CFG_GPMC_OEN_REN_OUT,Delay Select Value in binary coded form for cfg_gpmc_oen_ren_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x390++0x3 line.long 0x0 "CFG_GPMC_WAIT0_IN,Delay Select Value in binary coded form for cfg_gpmc_wait0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x394++0x3 line.long 0x0 "CFG_GPMC_WAIT0_OEN,Delay Select Value in binary coded form for cfg_gpmc_wait0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x398++0x3 line.long 0x0 "CFG_GPMC_WAIT0_OUT,Delay Select Value in binary coded form for cfg_gpmc_wait0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x39C++0x3 line.long 0x0 "CFG_GPMC_WEN_IN,Delay Select Value in binary coded form for cfg_gpmc_wen_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3A0++0x3 line.long 0x0 "CFG_GPMC_WEN_OEN,Delay Select Value in binary coded form for cfg_gpmc_wen_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3A4++0x3 line.long 0x0 "CFG_GPMC_WEN_OUT,Delay Select Value in binary coded form for cfg_gpmc_wen_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3A8++0x3 line.long 0x0 "CFG_MCASP1_ACLKR_IN,Delay Select Value in binary coded form for cfg_mcasp1_aclkr_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3AC++0x3 line.long 0x0 "CFG_MCASP1_ACLKR_OEN,Delay Select Value in binary coded form for cfg_mcasp1_aclkr_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3B0++0x3 line.long 0x0 "CFG_MCASP1_ACLKR_OUT,Delay Select Value in binary coded form for cfg_mcasp1_aclkr_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3B4++0x3 line.long 0x0 "CFG_MCASP1_ACLKX_IN,Delay Select Value in binary coded form for cfg_mcasp1_aclkx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3B8++0x3 line.long 0x0 "CFG_MCASP1_ACLKX_OEN,Delay Select Value in binary coded form for cfg_mcasp1_aclkx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3BC++0x3 line.long 0x0 "CFG_MCASP1_ACLKX_OUT,Delay Select Value in binary coded form for cfg_mcasp1_aclkx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3C0++0x3 line.long 0x0 "CFG_MCASP1_AXR0_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3C4++0x3 line.long 0x0 "CFG_MCASP1_AXR0_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3C8++0x3 line.long 0x0 "CFG_MCASP1_AXR0_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3CC++0x3 line.long 0x0 "CFG_MCASP1_AXR10_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr10_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3D0++0x3 line.long 0x0 "CFG_MCASP1_AXR10_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr10_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3D4++0x3 line.long 0x0 "CFG_MCASP1_AXR10_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr10_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3D8++0x3 line.long 0x0 "CFG_MCASP1_AXR11_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr11_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3DC++0x3 line.long 0x0 "CFG_MCASP1_AXR11_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr11_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3E0++0x3 line.long 0x0 "CFG_MCASP1_AXR11_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr11_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3E4++0x3 line.long 0x0 "CFG_MCASP1_AXR12_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr12_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3E8++0x3 line.long 0x0 "CFG_MCASP1_AXR12_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr12_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3EC++0x3 line.long 0x0 "CFG_MCASP1_AXR12_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr12_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3F0++0x3 line.long 0x0 "CFG_MCASP1_AXR13_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr13_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3F4++0x3 line.long 0x0 "CFG_MCASP1_AXR13_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr13_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3F8++0x3 line.long 0x0 "CFG_MCASP1_AXR13_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr13_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x3FC++0x3 line.long 0x0 "CFG_MCASP1_AXR14_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr14_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x400++0x3 line.long 0x0 "CFG_MCASP1_AXR14_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr14_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x404++0x3 line.long 0x0 "CFG_MCASP1_AXR14_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr14_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x408++0x3 line.long 0x0 "CFG_MCASP1_AXR15_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr15_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x40C++0x3 line.long 0x0 "CFG_MCASP1_AXR15_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr15_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x410++0x3 line.long 0x0 "CFG_MCASP1_AXR15_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr15_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x414++0x3 line.long 0x0 "CFG_MCASP1_AXR1_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x418++0x3 line.long 0x0 "CFG_MCASP1_AXR1_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x41C++0x3 line.long 0x0 "CFG_MCASP1_AXR1_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x420++0x3 line.long 0x0 "CFG_MCASP1_AXR2_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x424++0x3 line.long 0x0 "CFG_MCASP1_AXR2_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x428++0x3 line.long 0x0 "CFG_MCASP1_AXR2_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x42C++0x3 line.long 0x0 "CFG_MCASP1_AXR3_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x430++0x3 line.long 0x0 "CFG_MCASP1_AXR3_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x434++0x3 line.long 0x0 "CFG_MCASP1_AXR3_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x438++0x3 line.long 0x0 "CFG_MCASP1_AXR4_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr4_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x43C++0x3 line.long 0x0 "CFG_MCASP1_AXR4_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr4_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x440++0x3 line.long 0x0 "CFG_MCASP1_AXR4_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr4_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x444++0x3 line.long 0x0 "CFG_MCASP1_AXR5_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr5_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x448++0x3 line.long 0x0 "CFG_MCASP1_AXR5_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr5_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x44C++0x3 line.long 0x0 "CFG_MCASP1_AXR5_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr5_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x450++0x3 line.long 0x0 "CFG_MCASP1_AXR6_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr6_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x454++0x3 line.long 0x0 "CFG_MCASP1_AXR6_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr6_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x458++0x3 line.long 0x0 "CFG_MCASP1_AXR6_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr6_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x45C++0x3 line.long 0x0 "CFG_MCASP1_AXR7_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr7_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x460++0x3 line.long 0x0 "CFG_MCASP1_AXR7_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr7_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x464++0x3 line.long 0x0 "CFG_MCASP1_AXR7_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr7_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x468++0x3 line.long 0x0 "CFG_MCASP1_AXR8_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr8_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x46C++0x3 line.long 0x0 "CFG_MCASP1_AXR8_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr8_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x470++0x3 line.long 0x0 "CFG_MCASP1_AXR8_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr8_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x474++0x3 line.long 0x0 "CFG_MCASP1_AXR9_IN,Delay Select Value in binary coded form for cfg_mcasp1_axr9_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x478++0x3 line.long 0x0 "CFG_MCASP1_AXR9_OEN,Delay Select Value in binary coded form for cfg_mcasp1_axr9_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x47C++0x3 line.long 0x0 "CFG_MCASP1_AXR9_OUT,Delay Select Value in binary coded form for cfg_mcasp1_axr9_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x480++0x3 line.long 0x0 "CFG_MCASP1_FSR_IN,Delay Select Value in binary coded form for cfg_mcasp1_fsr_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x484++0x3 line.long 0x0 "CFG_MCASP1_FSR_OEN,Delay Select Value in binary coded form for cfg_mcasp1_fsr_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x488++0x3 line.long 0x0 "CFG_MCASP1_FSR_OUT,Delay Select Value in binary coded form for cfg_mcasp1_fsr_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x48C++0x3 line.long 0x0 "CFG_MCASP1_FSX_IN,Delay Select Value in binary coded form for cfg_mcasp1_fsx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x490++0x3 line.long 0x0 "CFG_MCASP1_FSX_OEN,Delay Select Value in binary coded form for cfg_mcasp1_fsx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x494++0x3 line.long 0x0 "CFG_MCASP1_FSX_OUT,Delay Select Value in binary coded form for cfg_mcasp1_fsx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x498++0x3 line.long 0x0 "CFG_MCASP2_ACLKR_IN,Delay Select Value in binary coded form for cfg_mcasp2_aclkr_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x49C++0x3 line.long 0x0 "CFG_MCASP2_ACLKR_OEN,Delay Select Value in binary coded form for cfg_mcasp2_aclkr_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4A0++0x3 line.long 0x0 "CFG_MCASP2_ACLKR_OUT,Delay Select Value in binary coded form for cfg_mcasp2_aclkr_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4A4++0x3 line.long 0x0 "CFG_MCASP2_ACLKX_IN,Delay Select Value in binary coded form for cfg_mcasp2_aclkx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4A8++0x3 line.long 0x0 "CFG_MCASP2_ACLKX_OEN,Delay Select Value in binary coded form for cfg_mcasp2_aclkx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4AC++0x3 line.long 0x0 "CFG_MCASP2_ACLKX_OUT,Delay Select Value in binary coded form for cfg_mcasp2_aclkx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4B0++0x3 line.long 0x0 "CFG_MCASP2_AXR0_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4B4++0x3 line.long 0x0 "CFG_MCASP2_AXR0_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4B8++0x3 line.long 0x0 "CFG_MCASP2_AXR0_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4BC++0x3 line.long 0x0 "CFG_MCASP2_AXR1_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4C0++0x3 line.long 0x0 "CFG_MCASP2_AXR1_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4C4++0x3 line.long 0x0 "CFG_MCASP2_AXR1_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4C8++0x3 line.long 0x0 "CFG_MCASP2_AXR2_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4CC++0x3 line.long 0x0 "CFG_MCASP2_AXR2_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4D0++0x3 line.long 0x0 "CFG_MCASP2_AXR2_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4D4++0x3 line.long 0x0 "CFG_MCASP2_AXR3_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4D8++0x3 line.long 0x0 "CFG_MCASP2_AXR3_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4DC++0x3 line.long 0x0 "CFG_MCASP2_AXR3_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4E0++0x3 line.long 0x0 "CFG_MCASP2_AXR4_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr4_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4E4++0x3 line.long 0x0 "CFG_MCASP2_AXR4_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr4_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4E8++0x3 line.long 0x0 "CFG_MCASP2_AXR4_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr4_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4EC++0x3 line.long 0x0 "CFG_MCASP2_AXR5_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr5_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4F0++0x3 line.long 0x0 "CFG_MCASP2_AXR5_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr5_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4F4++0x3 line.long 0x0 "CFG_MCASP2_AXR5_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr5_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4F8++0x3 line.long 0x0 "CFG_MCASP2_AXR6_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr6_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x4FC++0x3 line.long 0x0 "CFG_MCASP2_AXR6_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr6_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x500++0x3 line.long 0x0 "CFG_MCASP2_AXR6_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr6_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x504++0x3 line.long 0x0 "CFG_MCASP2_AXR7_IN,Delay Select Value in binary coded form for cfg_mcasp2_axr7_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x508++0x3 line.long 0x0 "CFG_MCASP2_AXR7_OEN,Delay Select Value in binary coded form for cfg_mcasp2_axr7_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x50C++0x3 line.long 0x0 "CFG_MCASP2_AXR7_OUT,Delay Select Value in binary coded form for cfg_mcasp2_axr7_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x510++0x3 line.long 0x0 "CFG_MCASP2_FSR_IN,Delay Select Value in binary coded form for cfg_mcasp2_fsr_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x514++0x3 line.long 0x0 "CFG_MCASP2_FSR_OEN,Delay Select Value in binary coded form for cfg_mcasp2_fsr_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x518++0x3 line.long 0x0 "CFG_MCASP2_FSR_OUT,Delay Select Value in binary coded form for cfg_mcasp2_fsr_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x51C++0x3 line.long 0x0 "CFG_MCASP2_FSX_IN,Delay Select Value in binary coded form for cfg_mcasp2_fsx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x520++0x3 line.long 0x0 "CFG_MCASP2_FSX_OEN,Delay Select Value in binary coded form for cfg_mcasp2_fsx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x524++0x3 line.long 0x0 "CFG_MCASP2_FSX_OUT,Delay Select Value in binary coded form for cfg_mcasp2_fsx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x528++0x3 line.long 0x0 "CFG_MCASP3_ACLKX_IN,Delay Select Value in binary coded form for cfg_mcasp3_aclkx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x52C++0x3 line.long 0x0 "CFG_MCASP3_ACLKX_OEN,Delay Select Value in binary coded form for cfg_mcasp3_aclkx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x530++0x3 line.long 0x0 "CFG_MCASP3_ACLKX_OUT,Delay Select Value in binary coded form for cfg_mcasp3_aclkx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x534++0x3 line.long 0x0 "CFG_MCASP3_AXR0_IN,Delay Select Value in binary coded form for cfg_mcasp3_axr0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x538++0x3 line.long 0x0 "CFG_MCASP3_AXR0_OEN,Delay Select Value in binary coded form for cfg_mcasp3_axr0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x53C++0x3 line.long 0x0 "CFG_MCASP3_AXR0_OUT,Delay Select Value in binary coded form for cfg_mcasp3_axr0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x540++0x3 line.long 0x0 "CFG_MCASP3_AXR1_IN,Delay Select Value in binary coded form for cfg_mcasp3_axr1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x544++0x3 line.long 0x0 "CFG_MCASP3_AXR1_OEN,Delay Select Value in binary coded form for cfg_mcasp3_axr1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x548++0x3 line.long 0x0 "CFG_MCASP3_AXR1_OUT,Delay Select Value in binary coded form for cfg_mcasp3_axr1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x54C++0x3 line.long 0x0 "CFG_MCASP3_FSX_IN,Delay Select Value in binary coded form for cfg_mcasp3_fsx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x550++0x3 line.long 0x0 "CFG_MCASP3_FSX_OEN,Delay Select Value in binary coded form for cfg_mcasp3_fsx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x554++0x3 line.long 0x0 "CFG_MCASP3_FSX_OUT,Delay Select Value in binary coded form for cfg_mcasp3_fsx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x558++0x3 line.long 0x0 "CFG_MCASP4_ACLKX_IN,Delay Select Value in binary coded form for cfg_mcasp4_aclkx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x55C++0x3 line.long 0x0 "CFG_MCASP4_ACLKX_OEN,Delay Select Value in binary coded form for cfg_mcasp4_aclkx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x560++0x3 line.long 0x0 "CFG_MCASP4_ACLKX_OUT,Delay Select Value in binary coded form for cfg_mcasp4_aclkx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x564++0x3 line.long 0x0 "CFG_MCASP4_AXR0_IN,Delay Select Value in binary coded form for cfg_mcasp4_axr0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x568++0x3 line.long 0x0 "CFG_MCASP4_AXR0_OEN,Delay Select Value in binary coded form for cfg_mcasp4_axr0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x56C++0x3 line.long 0x0 "CFG_MCASP4_AXR0_OUT,Delay Select Value in binary coded form for cfg_mcasp4_axr0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x570++0x3 line.long 0x0 "CFG_MCASP4_AXR1_IN,Delay Select Value in binary coded form for cfg_mcasp4_axr1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x574++0x3 line.long 0x0 "CFG_MCASP4_AXR1_OEN,Delay Select Value in binary coded form for cfg_mcasp4_axr1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x578++0x3 line.long 0x0 "CFG_MCASP4_AXR1_OUT,Delay Select Value in binary coded form for cfg_mcasp4_axr1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x57C++0x3 line.long 0x0 "CFG_MCASP4_FSX_IN,Delay Select Value in binary coded form for cfg_mcasp4_fsx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x580++0x3 line.long 0x0 "CFG_MCASP4_FSX_OEN,Delay Select Value in binary coded form for cfg_mcasp4_fsx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x584++0x3 line.long 0x0 "CFG_MCASP4_FSX_OUT,Delay Select Value in binary coded form for cfg_mcasp4_fsx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x588++0x3 line.long 0x0 "CFG_MCASP5_ACLKX_IN,Delay Select Value in binary coded form for cfg_mcasp5_aclkx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x58C++0x3 line.long 0x0 "CFG_MCASP5_ACLKX_OEN,Delay Select Value in binary coded form for cfg_mcasp5_aclkx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x590++0x3 line.long 0x0 "CFG_MCASP5_ACLKX_OUT,Delay Select Value in binary coded form for cfg_mcasp5_aclkx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x594++0x3 line.long 0x0 "CFG_MCASP5_AXR0_IN,Delay Select Value in binary coded form for cfg_mcasp5_axr0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x598++0x3 line.long 0x0 "CFG_MCASP5_AXR0_OEN,Delay Select Value in binary coded form for cfg_mcasp5_axr0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x59C++0x3 line.long 0x0 "CFG_MCASP5_AXR0_OUT,Delay Select Value in binary coded form for cfg_mcasp5_axr0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5A0++0x3 line.long 0x0 "CFG_MCASP5_AXR1_IN,Delay Select Value in binary coded form for cfg_mcasp5_axr1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5A4++0x3 line.long 0x0 "CFG_MCASP5_AXR1_OEN,Delay Select Value in binary coded form for cfg_mcasp5_axr1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5A8++0x3 line.long 0x0 "CFG_MCASP5_AXR1_OUT,Delay Select Value in binary coded form for cfg_mcasp5_axr1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5AC++0x3 line.long 0x0 "CFG_MCASP5_FSX_IN,Delay Select Value in binary coded form for cfg_mcasp5_fsx_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5B0++0x3 line.long 0x0 "CFG_MCASP5_FSX_OEN,Delay Select Value in binary coded form for cfg_mcasp5_fsx_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5B4++0x3 line.long 0x0 "CFG_MCASP5_FSX_OUT,Delay Select Value in binary coded form for cfg_mcasp5_fsx_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5B8++0x3 line.long 0x0 "CFG_MDIO_D_IN,Delay Select Value in binary coded form for cfg_mdio_d_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5BC++0x3 line.long 0x0 "CFG_MDIO_D_OEN,Delay Select Value in binary coded form for cfg_mdio_d_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5C0++0x3 line.long 0x0 "CFG_MDIO_D_OUT,Delay Select Value in binary coded form for cfg_mdio_d_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5C4++0x3 line.long 0x0 "CFG_MDIO_MCLK_IN,Delay Select Value in binary coded form for cfg_mdio_mclk_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5C8++0x3 line.long 0x0 "CFG_MDIO_MCLK_OEN,Delay Select Value in binary coded form for cfg_mdio_mclk_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5CC++0x3 line.long 0x0 "CFG_MDIO_MCLK_OUT,Delay Select Value in binary coded form for cfg_mdio_mclk_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5D0++0x3 line.long 0x0 "CFG_MLBP_CLK_N_IN,Delay Select Value in binary coded form for cfg_mlbp_clk_n_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5D4++0x3 line.long 0x0 "CFG_MLBP_CLK_N_OEN,Delay Select Value in binary coded form for cfg_mlbp_clk_n_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5D8++0x3 line.long 0x0 "CFG_MLBP_CLK_N_OUT,Delay Select Value in binary coded form for cfg_mlbp_clk_n_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5DC++0x3 line.long 0x0 "CFG_MLBP_CLK_P_IN,Delay Select Value in binary coded form for cfg_mlbp_clk_p_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5E0++0x3 line.long 0x0 "CFG_MLBP_CLK_P_OEN,Delay Select Value in binary coded form for cfg_mlbp_clk_p_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5E4++0x3 line.long 0x0 "CFG_MLBP_CLK_P_OUT,Delay Select Value in binary coded form for cfg_mlbp_clk_p_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5E8++0x3 line.long 0x0 "CFG_MLBP_DAT_N_IN,Delay Select Value in binary coded form for cfg_mlbp_dat_n_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5EC++0x3 line.long 0x0 "CFG_MLBP_DAT_N_OEN,Delay Select Value in binary coded form for cfg_mlbp_dat_n_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5F0++0x3 line.long 0x0 "CFG_MLBP_DAT_N_OUT,Delay Select Value in binary coded form for cfg_mlbp_dat_n_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5F4++0x3 line.long 0x0 "CFG_MLBP_DAT_P_IN,Delay Select Value in binary coded form for cfg_mlbp_dat_p_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5F8++0x3 line.long 0x0 "CFG_MLBP_DAT_P_OEN,Delay Select Value in binary coded form for cfg_mlbp_dat_p_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x5FC++0x3 line.long 0x0 "CFG_MLBP_DAT_P_OUT,Delay Select Value in binary coded form for cfg_mlbp_dat_p_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x600++0x3 line.long 0x0 "CFG_MLBP_SIG_N_IN,Delay Select Value in binary coded form for cfg_mlbp_sig_n_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x604++0x3 line.long 0x0 "CFG_MLBP_SIG_N_OEN,Delay Select Value in binary coded form for cfg_mlbp_sig_n_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x608++0x3 line.long 0x0 "CFG_MLBP_SIG_N_OUT,Delay Select Value in binary coded form for cfg_mlbp_sig_n_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x60C++0x3 line.long 0x0 "CFG_MLBP_SIG_P_IN,Delay Select Value in binary coded form for cfg_mlbp_sig_p_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x610++0x3 line.long 0x0 "CFG_MLBP_SIG_P_OEN,Delay Select Value in binary coded form for cfg_mlbp_sig_p_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x614++0x3 line.long 0x0 "CFG_MLBP_SIG_P_OUT,Delay Select Value in binary coded form for cfg_mlbp_sig_p_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x618++0x3 line.long 0x0 "CFG_MMC1_CLK_IN,Delay Select Value in binary coded form for cfg_mmc1_clk_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x61C++0x3 line.long 0x0 "CFG_MMC1_CLK_OEN,Delay Select Value in binary coded form for cfg_mmc1_clk_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x620++0x3 line.long 0x0 "CFG_MMC1_CLK_OUT,Delay Select Value in binary coded form for cfg_mmc1_clk_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x624++0x3 line.long 0x0 "CFG_MMC1_CMD_IN,Delay Select Value in binary coded form for cfg_mmc1_cmd_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x628++0x3 line.long 0x0 "CFG_MMC1_CMD_OEN,Delay Select Value in binary coded form for cfg_mmc1_cmd_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x62C++0x3 line.long 0x0 "CFG_MMC1_CMD_OUT,Delay Select Value in binary coded form for cfg_mmc1_cmd_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x630++0x3 line.long 0x0 "CFG_MMC1_DAT0_IN,Delay Select Value in binary coded form for cfg_mmc1_dat0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x634++0x3 line.long 0x0 "CFG_MMC1_DAT0_OEN,Delay Select Value in binary coded form for cfg_mmc1_dat0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x638++0x3 line.long 0x0 "CFG_MMC1_DAT0_OUT,Delay Select Value in binary coded form for cfg_mmc1_dat0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x63C++0x3 line.long 0x0 "CFG_MMC1_DAT1_IN,Delay Select Value in binary coded form for cfg_mmc1_dat1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x640++0x3 line.long 0x0 "CFG_MMC1_DAT1_OEN,Delay Select Value in binary coded form for cfg_mmc1_dat1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x644++0x3 line.long 0x0 "CFG_MMC1_DAT1_OUT,Delay Select Value in binary coded form for cfg_mmc1_dat1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x648++0x3 line.long 0x0 "CFG_MMC1_DAT2_IN,Delay Select Value in binary coded form for cfg_mmc1_dat2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x64C++0x3 line.long 0x0 "CFG_MMC1_DAT2_OEN,Delay Select Value in binary coded form for cfg_mmc1_dat2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x650++0x3 line.long 0x0 "CFG_MMC1_DAT2_OUT,Delay Select Value in binary coded form for cfg_mmc1_dat2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x654++0x3 line.long 0x0 "CFG_MMC1_DAT3_IN,Delay Select Value in binary coded form for cfg_mmc1_dat3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x658++0x3 line.long 0x0 "CFG_MMC1_DAT3_OEN,Delay Select Value in binary coded form for cfg_mmc1_dat3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x65C++0x3 line.long 0x0 "CFG_MMC1_DAT3_OUT,Delay Select Value in binary coded form for cfg_mmc1_dat3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x660++0x3 line.long 0x0 "CFG_MMC1_SDCD_IN,Delay Select Value in binary coded form for cfg_mmc1_sdcd_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x664++0x3 line.long 0x0 "CFG_MMC1_SDCD_OEN,Delay Select Value in binary coded form for cfg_mmc1_sdcd_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x668++0x3 line.long 0x0 "CFG_MMC1_SDCD_OUT,Delay Select Value in binary coded form for cfg_mmc1_sdcd_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x66C++0x3 line.long 0x0 "CFG_MMC1_SDWP_IN,Delay Select Value in binary coded form for cfg_mmc1_sdwp_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x670++0x3 line.long 0x0 "CFG_MMC1_SDWP_OEN,Delay Select Value in binary coded form for cfg_mmc1_sdwp_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x674++0x3 line.long 0x0 "CFG_MMC1_SDWP_OUT,Delay Select Value in binary coded form for cfg_mmc1_sdwp_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x678++0x3 line.long 0x0 "CFG_MMC3_CLK_IN,Delay Select Value in binary coded form for cfg_mmc3_clk_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x67C++0x3 line.long 0x0 "CFG_MMC3_CLK_OEN,Delay Select Value in binary coded form for cfg_mmc3_clk_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x680++0x3 line.long 0x0 "CFG_MMC3_CLK_OUT,Delay Select Value in binary coded form for cfg_mmc3_clk_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x684++0x3 line.long 0x0 "CFG_MMC3_CMD_IN,Delay Select Value in binary coded form for cfg_mmc3_cmd_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x688++0x3 line.long 0x0 "CFG_MMC3_CMD_OEN,Delay Select Value in binary coded form for cfg_mmc3_cmd_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x68C++0x3 line.long 0x0 "CFG_MMC3_CMD_OUT,Delay Select Value in binary coded form for cfg_mmc3_cmd_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x690++0x3 line.long 0x0 "CFG_MMC3_DAT0_IN,Delay Select Value in binary coded form for cfg_mmc3_dat0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x694++0x3 line.long 0x0 "CFG_MMC3_DAT0_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x698++0x3 line.long 0x0 "CFG_MMC3_DAT0_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x69C++0x3 line.long 0x0 "CFG_MMC3_DAT1_IN,Delay Select Value in binary coded form for cfg_mmc3_dat1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6A0++0x3 line.long 0x0 "CFG_MMC3_DAT1_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6A4++0x3 line.long 0x0 "CFG_MMC3_DAT1_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6A8++0x3 line.long 0x0 "CFG_MMC3_DAT2_IN,Delay Select Value in binary coded form for cfg_mmc3_dat2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6AC++0x3 line.long 0x0 "CFG_MMC3_DAT2_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6B0++0x3 line.long 0x0 "CFG_MMC3_DAT2_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6B4++0x3 line.long 0x0 "CFG_MMC3_DAT3_IN,Delay Select Value in binary coded form for cfg_mmc3_dat3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6B8++0x3 line.long 0x0 "CFG_MMC3_DAT3_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6BC++0x3 line.long 0x0 "CFG_MMC3_DAT3_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C0++0x3 line.long 0x0 "CFG_MMC3_DAT4_IN,Delay Select Value in binary coded form for cfg_mmc3_dat4_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C4++0x3 line.long 0x0 "CFG_MMC3_DAT4_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat4_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C8++0x3 line.long 0x0 "CFG_MMC3_DAT4_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat4_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6CC++0x3 line.long 0x0 "CFG_MMC3_DAT5_IN,Delay Select Value in binary coded form for cfg_mmc3_dat5_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6D0++0x3 line.long 0x0 "CFG_MMC3_DAT5_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat5_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6D4++0x3 line.long 0x0 "CFG_MMC3_DAT5_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat5_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6D8++0x3 line.long 0x0 "CFG_MMC3_DAT6_IN,Delay Select Value in binary coded form for cfg_mmc3_dat6_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6DC++0x3 line.long 0x0 "CFG_MMC3_DAT6_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat6_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6E0++0x3 line.long 0x0 "CFG_MMC3_DAT6_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat6_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6E4++0x3 line.long 0x0 "CFG_MMC3_DAT7_IN,Delay Select Value in binary coded form for cfg_mmc3_dat7_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6E8++0x3 line.long 0x0 "CFG_MMC3_DAT7_OEN,Delay Select Value in binary coded form for cfg_mmc3_dat7_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6EC++0x3 line.long 0x0 "CFG_MMC3_DAT7_OUT,Delay Select Value in binary coded form for cfg_mmc3_dat7_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6F0++0x3 line.long 0x0 "CFG_RGMII0_RXC_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxc_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6F4++0x3 line.long 0x0 "CFG_RGMII0_RXC_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxc_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6F8++0x3 line.long 0x0 "CFG_RGMII0_RXC_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxc_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6FC++0x3 line.long 0x0 "CFG_RGMII0_RXCTL_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxctl_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x700++0x3 line.long 0x0 "CFG_RGMII0_RXCTL_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxctl_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x704++0x3 line.long 0x0 "CFG_RGMII0_RXCTL_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxctl_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x708++0x3 line.long 0x0 "CFG_RGMII0_RXD0_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxd0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x70C++0x3 line.long 0x0 "CFG_RGMII0_RXD0_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxd0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x710++0x3 line.long 0x0 "CFG_RGMII0_RXD0_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxd0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x714++0x3 line.long 0x0 "CFG_RGMII0_RXD1_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxd1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x718++0x3 line.long 0x0 "CFG_RGMII0_RXD1_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxd1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x71C++0x3 line.long 0x0 "CFG_RGMII0_RXD1_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxd1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x720++0x3 line.long 0x0 "CFG_RGMII0_RXD2_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxd2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x724++0x3 line.long 0x0 "CFG_RGMII0_RXD2_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxd2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x728++0x3 line.long 0x0 "CFG_RGMII0_RXD2_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxd2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x72C++0x3 line.long 0x0 "CFG_RGMII0_RXD3_IN,Delay Select Value in binary coded form for cfg_rgmii0_rxd3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x730++0x3 line.long 0x0 "CFG_RGMII0_RXD3_OEN,Delay Select Value in binary coded form for cfg_rgmii0_rxd3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x734++0x3 line.long 0x0 "CFG_RGMII0_RXD3_OUT,Delay Select Value in binary coded form for cfg_rgmii0_rxd3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x738++0x3 line.long 0x0 "CFG_RGMII0_TXC_IN,Delay Select Value in binary coded form for cfg_rgmii0_txc_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x73C++0x3 line.long 0x0 "CFG_RGMII0_TXC_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txc_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x740++0x3 line.long 0x0 "CFG_RGMII0_TXC_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txc_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x744++0x3 line.long 0x0 "CFG_RGMII0_TXCTL_IN,Delay Select Value in binary coded form for cfg_rgmii0_txctl_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x748++0x3 line.long 0x0 "CFG_RGMII0_TXCTL_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txctl_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x74C++0x3 line.long 0x0 "CFG_RGMII0_TXCTL_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txctl_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x750++0x3 line.long 0x0 "CFG_RGMII0_TXD0_IN,Delay Select Value in binary coded form for cfg_rgmii0_txd0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x754++0x3 line.long 0x0 "CFG_RGMII0_TXD0_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txd0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x758++0x3 line.long 0x0 "CFG_RGMII0_TXD0_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txd0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x75C++0x3 line.long 0x0 "CFG_RGMII0_TXD1_IN,Delay Select Value in binary coded form for cfg_rgmii0_txd1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x760++0x3 line.long 0x0 "CFG_RGMII0_TXD1_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txd1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x764++0x3 line.long 0x0 "CFG_RGMII0_TXD1_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txd1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x768++0x3 line.long 0x0 "CFG_RGMII0_TXD2_IN,Delay Select Value in binary coded form for cfg_rgmii0_txd2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x76C++0x3 line.long 0x0 "CFG_RGMII0_TXD2_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txd2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x770++0x3 line.long 0x0 "CFG_RGMII0_TXD2_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txd2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x774++0x3 line.long 0x0 "CFG_RGMII0_TXD3_IN,Delay Select Value in binary coded form for cfg_rgmii0_txd3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x778++0x3 line.long 0x0 "CFG_RGMII0_TXD3_OEN,Delay Select Value in binary coded form for cfg_rgmii0_txd3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x77C++0x3 line.long 0x0 "CFG_RGMII0_TXD3_OUT,Delay Select Value in binary coded form for cfg_rgmii0_txd3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x780++0x3 line.long 0x0 "CFG_RTCK_IN,Delay Select Value in binary coded form for cfg_rtck_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x784++0x3 line.long 0x0 "CFG_RTCK_OEN,Delay Select Value in binary coded form for cfg_rtck_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x788++0x3 line.long 0x0 "CFG_RTCK_OUT,Delay Select Value in binary coded form for cfg_rtck_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x78C++0x3 line.long 0x0 "CFG_SPI1_CS0_IN,Delay Select Value in binary coded form for cfg_spi1_cs0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x790++0x3 line.long 0x0 "CFG_SPI1_CS0_OEN,Delay Select Value in binary coded form for cfg_spi1_cs0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x794++0x3 line.long 0x0 "CFG_SPI1_CS0_OUT,Delay Select Value in binary coded form for cfg_spi1_cs0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x798++0x3 line.long 0x0 "CFG_SPI1_CS1_IN,Delay Select Value in binary coded form for cfg_spi1_cs1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x79C++0x3 line.long 0x0 "CFG_SPI1_CS1_OEN,Delay Select Value in binary coded form for cfg_spi1_cs1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7A0++0x3 line.long 0x0 "CFG_SPI1_CS1_OUT,Delay Select Value in binary coded form for cfg_spi1_cs1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7A4++0x3 line.long 0x0 "CFG_SPI1_CS2_IN,Delay Select Value in binary coded form for cfg_spi1_cs2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7A8++0x3 line.long 0x0 "CFG_SPI1_CS2_OEN,Delay Select Value in binary coded form for cfg_spi1_cs2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7AC++0x3 line.long 0x0 "CFG_SPI1_CS2_OUT,Delay Select Value in binary coded form for cfg_spi1_cs2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7B0++0x3 line.long 0x0 "CFG_SPI1_CS3_IN,Delay Select Value in binary coded form for cfg_spi1_cs3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7B4++0x3 line.long 0x0 "CFG_SPI1_CS3_OEN,Delay Select Value in binary coded form for cfg_spi1_cs3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7B8++0x3 line.long 0x0 "CFG_SPI1_CS3_OUT,Delay Select Value in binary coded form for cfg_spi1_cs3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7BC++0x3 line.long 0x0 "CFG_SPI1_D0_IN,Delay Select Value in binary coded form for cfg_spi1_d0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7C0++0x3 line.long 0x0 "CFG_SPI1_D0_OEN,Delay Select Value in binary coded form for cfg_spi1_d0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7C4++0x3 line.long 0x0 "CFG_SPI1_D0_OUT,Delay Select Value in binary coded form for cfg_spi1_d0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7C8++0x3 line.long 0x0 "CFG_SPI1_D1_IN,Delay Select Value in binary coded form for cfg_spi1_d1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7CC++0x3 line.long 0x0 "CFG_SPI1_D1_OEN,Delay Select Value in binary coded form for cfg_spi1_d1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7D0++0x3 line.long 0x0 "CFG_SPI1_D1_OUT,Delay Select Value in binary coded form for cfg_spi1_d1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7D4++0x3 line.long 0x0 "CFG_SPI1_SCLK_IN,Delay Select Value in binary coded form for cfg_spi1_sclk_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7D8++0x3 line.long 0x0 "CFG_SPI1_SCLK_OEN,Delay Select Value in binary coded form for cfg_spi1_sclk_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7DC++0x3 line.long 0x0 "CFG_SPI1_SCLK_OUT,Delay Select Value in binary coded form for cfg_spi1_sclk_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7E0++0x3 line.long 0x0 "CFG_SPI2_CS0_IN,Delay Select Value in binary coded form for cfg_spi2_cs0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7E4++0x3 line.long 0x0 "CFG_SPI2_CS0_OEN,Delay Select Value in binary coded form for cfg_spi2_cs0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7E8++0x3 line.long 0x0 "CFG_SPI2_CS0_OUT,Delay Select Value in binary coded form for cfg_spi2_cs0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7EC++0x3 line.long 0x0 "CFG_SPI2_D0_IN,Delay Select Value in binary coded form for cfg_spi2_d0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7F0++0x3 line.long 0x0 "CFG_SPI2_D0_OEN,Delay Select Value in binary coded form for cfg_spi2_d0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7F4++0x3 line.long 0x0 "CFG_SPI2_D0_OUT,Delay Select Value in binary coded form for cfg_spi2_d0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7F8++0x3 line.long 0x0 "CFG_SPI2_D1_IN,Delay Select Value in binary coded form for cfg_spi2_d1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x7FC++0x3 line.long 0x0 "CFG_SPI2_D1_OEN,Delay Select Value in binary coded form for cfg_spi2_d1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x800++0x3 line.long 0x0 "CFG_SPI2_D1_OUT,Delay Select Value in binary coded form for cfg_spi2_d1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x804++0x3 line.long 0x0 "CFG_SPI2_SCLK_IN,Delay Select Value in binary coded form for cfg_spi2_sclk_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x808++0x3 line.long 0x0 "CFG_SPI2_SCLK_OEN,Delay Select Value in binary coded form for cfg_spi2_sclk_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x80C++0x3 line.long 0x0 "CFG_SPI2_SCLK_OUT,Delay Select Value in binary coded form for cfg_spi2_sclk_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x810++0x3 line.long 0x0 "CFG_TDI_IN,Delay Select Value in binary coded form for cfg_tdi_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x814++0x3 line.long 0x0 "CFG_TDI_OEN,Delay Select Value in binary coded form for cfg_tdi_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x818++0x3 line.long 0x0 "CFG_TDI_OUT,Delay Select Value in binary coded form for cfg_tdi_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x81C++0x3 line.long 0x0 "CFG_TDO_IN,Delay Select Value in binary coded form for cfg_tdo_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x820++0x3 line.long 0x0 "CFG_TDO_OEN,Delay Select Value in binary coded form for cfg_tdo_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x824++0x3 line.long 0x0 "CFG_TDO_OUT,Delay Select Value in binary coded form for cfg_tdo_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x828++0x3 line.long 0x0 "CFG_TMS_IN,Delay Select Value in binary coded form for cfg_tms_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x82C++0x3 line.long 0x0 "CFG_TMS_OEN,Delay Select Value in binary coded form for cfg_tms_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x830++0x3 line.long 0x0 "CFG_TMS_OUT,Delay Select Value in binary coded form for cfg_tms_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x834++0x3 line.long 0x0 "CFG_TRSTN_IN,Delay Select Value in binary coded form for cfg_trstn_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x838++0x3 line.long 0x0 "CFG_TRSTN_OEN,Delay Select Value in binary coded form for cfg_trstn_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x83C++0x3 line.long 0x0 "CFG_TRSTN_OUT,Delay Select Value in binary coded form for cfg_trstn_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x840++0x3 line.long 0x0 "CFG_UART1_CTSN_IN,Delay Select Value in binary coded form for cfg_uart1_ctsn_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x844++0x3 line.long 0x0 "CFG_UART1_CTSN_OEN,Delay Select Value in binary coded form for cfg_uart1_ctsn_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x848++0x3 line.long 0x0 "CFG_UART1_CTSN_OUT,Delay Select Value in binary coded form for cfg_uart1_ctsn_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x84C++0x3 line.long 0x0 "CFG_UART1_RTSN_IN,Delay Select Value in binary coded form for cfg_uart1_rtsn_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x850++0x3 line.long 0x0 "CFG_UART1_RTSN_OEN,Delay Select Value in binary coded form for cfg_uart1_rtsn_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x854++0x3 line.long 0x0 "CFG_UART1_RTSN_OUT,Delay Select Value in binary coded form for cfg_uart1_rtsn_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x858++0x3 line.long 0x0 "CFG_UART1_RXD_IN,Delay Select Value in binary coded form for cfg_uart1_rxd_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x85C++0x3 line.long 0x0 "CFG_UART1_RXD_OEN,Delay Select Value in binary coded form for cfg_uart1_rxd_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x860++0x3 line.long 0x0 "CFG_UART1_RXD_OUT,Delay Select Value in binary coded form for cfg_uart1_rxd_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x864++0x3 line.long 0x0 "CFG_UART1_TXD_IN,Delay Select Value in binary coded form for cfg_uart1_txd_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x868++0x3 line.long 0x0 "CFG_UART1_TXD_OEN,Delay Select Value in binary coded form for cfg_uart1_txd_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x86C++0x3 line.long 0x0 "CFG_UART1_TXD_OUT,Delay Select Value in binary coded form for cfg_uart1_txd_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x870++0x3 line.long 0x0 "CFG_UART2_CTSN_IN,Delay Select Value in binary coded form for cfg_uart2_ctsn_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x874++0x3 line.long 0x0 "CFG_UART2_CTSN_OEN,Delay Select Value in binary coded form for cfg_uart2_ctsn_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x878++0x3 line.long 0x0 "CFG_UART2_CTSN_OUT,Delay Select Value in binary coded form for cfg_uart2_ctsn_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x87C++0x3 line.long 0x0 "CFG_UART2_RTSN_IN,Delay Select Value in binary coded form for cfg_uart2_rtsn_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x880++0x3 line.long 0x0 "CFG_UART2_RTSN_OEN,Delay Select Value in binary coded form for cfg_uart2_rtsn_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x884++0x3 line.long 0x0 "CFG_UART2_RTSN_OUT,Delay Select Value in binary coded form for cfg_uart2_rtsn_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x888++0x3 line.long 0x0 "CFG_UART2_RXD_IN,Delay Select Value in binary coded form for cfg_uart2_rxd_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x88C++0x3 line.long 0x0 "CFG_UART2_RXD_OEN,Delay Select Value in binary coded form for cfg_uart2_rxd_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x890++0x3 line.long 0x0 "CFG_UART2_RXD_OUT,Delay Select Value in binary coded form for cfg_uart2_rxd_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x894++0x3 line.long 0x0 "CFG_UART2_TXD_IN,Delay Select Value in binary coded form for cfg_uart2_txd_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x898++0x3 line.long 0x0 "CFG_UART2_TXD_OEN,Delay Select Value in binary coded form for cfg_uart2_txd_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x89C++0x3 line.long 0x0 "CFG_UART2_TXD_OUT,Delay Select Value in binary coded form for cfg_uart2_txd_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8A0++0x3 line.long 0x0 "CFG_UART3_RXD_IN,Delay Select Value in binary coded form for cfg_uart3_rxd_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8A4++0x3 line.long 0x0 "CFG_UART3_RXD_OEN,Delay Select Value in binary coded form for cfg_uart3_rxd_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8A8++0x3 line.long 0x0 "CFG_UART3_RXD_OUT,Delay Select Value in binary coded form for cfg_uart3_rxd_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8AC++0x3 line.long 0x0 "CFG_UART3_TXD_IN,Delay Select Value in binary coded form for cfg_uart3_txd_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8B0++0x3 line.long 0x0 "CFG_UART3_TXD_OEN,Delay Select Value in binary coded form for cfg_uart3_txd_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8B4++0x3 line.long 0x0 "CFG_UART3_TXD_OUT,Delay Select Value in binary coded form for cfg_uart3_txd_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8B8++0x3 line.long 0x0 "CFG_USB1_DRVVBUS_IN,Delay Select Value in binary coded form for cfg_usb1_drvvbus_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8BC++0x3 line.long 0x0 "CFG_USB1_DRVVBUS_OEN,Delay Select Value in binary coded form for cfg_usb1_drvvbus_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8C0++0x3 line.long 0x0 "CFG_USB1_DRVVBUS_OUT,Delay Select Value in binary coded form for cfg_usb1_drvvbus_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8C4++0x3 line.long 0x0 "CFG_USB2_DRVVBUS_IN,Delay Select Value in binary coded form for cfg_usb2_drvvbus_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8C8++0x3 line.long 0x0 "CFG_USB2_DRVVBUS_OEN,Delay Select Value in binary coded form for cfg_usb2_drvvbus_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8CC++0x3 line.long 0x0 "CFG_USB2_DRVVBUS_OUT,Delay Select Value in binary coded form for cfg_usb2_drvvbus_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8D0++0x3 line.long 0x0 "CFG_VIN1A_CLK0_IN,Delay Select Value in binary coded form for cfg_vin1a_clk0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8D4++0x3 line.long 0x0 "CFG_VIN1A_CLK0_OEN,Delay Select Value in binary coded form for cfg_vin1a_clk0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8D8++0x3 line.long 0x0 "CFG_VIN1A_CLK0_OUT,Delay Select Value in binary coded form for cfg_vin1a_clk0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8DC++0x3 line.long 0x0 "CFG_VIN1A_D0_IN,Delay Select Value in binary coded form for cfg_vin1a_d0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8E0++0x3 line.long 0x0 "CFG_VIN1A_D0_OEN,Delay Select Value in binary coded form for cfg_vin1a_d0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8E4++0x3 line.long 0x0 "CFG_VIN1A_D0_OUT,Delay Select Value in binary coded form for cfg_vin1a_d0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8E8++0x3 line.long 0x0 "CFG_VIN1A_D10_IN,Delay Select Value in binary coded form for cfg_vin1a_d10_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8EC++0x3 line.long 0x0 "CFG_VIN1A_D10_OEN,Delay Select Value in binary coded form for cfg_vin1a_d10_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8F0++0x3 line.long 0x0 "CFG_VIN1A_D10_OUT,Delay Select Value in binary coded form for cfg_vin1a_d10_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8F4++0x3 line.long 0x0 "CFG_VIN1A_D11_IN,Delay Select Value in binary coded form for cfg_vin1a_d11_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8F8++0x3 line.long 0x0 "CFG_VIN1A_D11_OEN,Delay Select Value in binary coded form for cfg_vin1a_d11_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x8FC++0x3 line.long 0x0 "CFG_VIN1A_D11_OUT,Delay Select Value in binary coded form for cfg_vin1a_d11_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x900++0x3 line.long 0x0 "CFG_VIN1A_D12_IN,Delay Select Value in binary coded form for cfg_vin1a_d12_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x904++0x3 line.long 0x0 "CFG_VIN1A_D12_OEN,Delay Select Value in binary coded form for cfg_vin1a_d12_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x908++0x3 line.long 0x0 "CFG_VIN1A_D12_OUT,Delay Select Value in binary coded form for cfg_vin1a_d12_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x90C++0x3 line.long 0x0 "CFG_VIN1A_D13_IN,Delay Select Value in binary coded form for cfg_vin1a_d13_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x910++0x3 line.long 0x0 "CFG_VIN1A_D13_OEN,Delay Select Value in binary coded form for cfg_vin1a_d13_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x914++0x3 line.long 0x0 "CFG_VIN1A_D13_OUT,Delay Select Value in binary coded form for cfg_vin1a_d13_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x918++0x3 line.long 0x0 "CFG_VIN1A_D14_IN,Delay Select Value in binary coded form for cfg_vin1a_d14_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x91C++0x3 line.long 0x0 "CFG_VIN1A_D14_OEN,Delay Select Value in binary coded form for cfg_vin1a_d14_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x920++0x3 line.long 0x0 "CFG_VIN1A_D14_OUT,Delay Select Value in binary coded form for cfg_vin1a_d14_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x924++0x3 line.long 0x0 "CFG_VIN1A_D15_IN,Delay Select Value in binary coded form for cfg_vin1a_d15_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x928++0x3 line.long 0x0 "CFG_VIN1A_D15_OEN,Delay Select Value in binary coded form for cfg_vin1a_d15_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x92C++0x3 line.long 0x0 "CFG_VIN1A_D15_OUT,Delay Select Value in binary coded form for cfg_vin1a_d15_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x930++0x3 line.long 0x0 "CFG_VIN1A_D16_IN,Delay Select Value in binary coded form for cfg_vin1a_d16_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x934++0x3 line.long 0x0 "CFG_VIN1A_D16_OEN,Delay Select Value in binary coded form for cfg_vin1a_d16_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x938++0x3 line.long 0x0 "CFG_VIN1A_D16_OUT,Delay Select Value in binary coded form for cfg_vin1a_d16_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x93C++0x3 line.long 0x0 "CFG_VIN1A_D17_IN,Delay Select Value in binary coded form for cfg_vin1a_d17_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x940++0x3 line.long 0x0 "CFG_VIN1A_D17_OEN,Delay Select Value in binary coded form for cfg_vin1a_d17_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x944++0x3 line.long 0x0 "CFG_VIN1A_D17_OUT,Delay Select Value in binary coded form for cfg_vin1a_d17_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x948++0x3 line.long 0x0 "CFG_VIN1A_D18_IN,Delay Select Value in binary coded form for cfg_vin1a_d18_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x94C++0x3 line.long 0x0 "CFG_VIN1A_D18_OEN,Delay Select Value in binary coded form for cfg_vin1a_d18_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x950++0x3 line.long 0x0 "CFG_VIN1A_D18_OUT,Delay Select Value in binary coded form for cfg_vin1a_d18_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x954++0x3 line.long 0x0 "CFG_VIN1A_D19_IN,Delay Select Value in binary coded form for cfg_vin1a_d19_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x958++0x3 line.long 0x0 "CFG_VIN1A_D19_OEN,Delay Select Value in binary coded form for cfg_vin1a_d19_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x95C++0x3 line.long 0x0 "CFG_VIN1A_D19_OUT,Delay Select Value in binary coded form for cfg_vin1a_d19_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x960++0x3 line.long 0x0 "CFG_VIN1A_D1_IN,Delay Select Value in binary coded form for cfg_vin1a_d1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x964++0x3 line.long 0x0 "CFG_VIN1A_D1_OEN,Delay Select Value in binary coded form for cfg_vin1a_d1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x968++0x3 line.long 0x0 "CFG_VIN1A_D1_OUT,Delay Select Value in binary coded form for cfg_vin1a_d1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x96C++0x3 line.long 0x0 "CFG_VIN1A_D20_IN,Delay Select Value in binary coded form for cfg_vin1a_d20_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x970++0x3 line.long 0x0 "CFG_VIN1A_D20_OEN,Delay Select Value in binary coded form for cfg_vin1a_d20_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x974++0x3 line.long 0x0 "CFG_VIN1A_D20_OUT,Delay Select Value in binary coded form for cfg_vin1a_d20_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x978++0x3 line.long 0x0 "CFG_VIN1A_D21_IN,Delay Select Value in binary coded form for cfg_vin1a_d21_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x97C++0x3 line.long 0x0 "CFG_VIN1A_D21_OEN,Delay Select Value in binary coded form for cfg_vin1a_d21_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x980++0x3 line.long 0x0 "CFG_VIN1A_D21_OUT,Delay Select Value in binary coded form for cfg_vin1a_d21_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x984++0x3 line.long 0x0 "CFG_VIN1A_D22_IN,Delay Select Value in binary coded form for cfg_vin1a_d22_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x988++0x3 line.long 0x0 "CFG_VIN1A_D22_OEN,Delay Select Value in binary coded form for cfg_vin1a_d22_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x98C++0x3 line.long 0x0 "CFG_VIN1A_D22_OUT,Delay Select Value in binary coded form for cfg_vin1a_d22_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x990++0x3 line.long 0x0 "CFG_VIN1A_D23_IN,Delay Select Value in binary coded form for cfg_vin1a_d23_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x994++0x3 line.long 0x0 "CFG_VIN1A_D23_OEN,Delay Select Value in binary coded form for cfg_vin1a_d23_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x998++0x3 line.long 0x0 "CFG_VIN1A_D23_OUT,Delay Select Value in binary coded form for cfg_vin1a_d23_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x99C++0x3 line.long 0x0 "CFG_VIN1A_D2_IN,Delay Select Value in binary coded form for cfg_vin1a_d2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9A0++0x3 line.long 0x0 "CFG_VIN1A_D2_OEN,Delay Select Value in binary coded form for cfg_vin1a_d2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9A4++0x3 line.long 0x0 "CFG_VIN1A_D2_OUT,Delay Select Value in binary coded form for cfg_vin1a_d2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9A8++0x3 line.long 0x0 "CFG_VIN1A_D3_IN,Delay Select Value in binary coded form for cfg_vin1a_d3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9AC++0x3 line.long 0x0 "CFG_VIN1A_D3_OEN,Delay Select Value in binary coded form for cfg_vin1a_d3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9B0++0x3 line.long 0x0 "CFG_VIN1A_D3_OUT,Delay Select Value in binary coded form for cfg_vin1a_d3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9B4++0x3 line.long 0x0 "CFG_VIN1A_D4_IN,Delay Select Value in binary coded form for cfg_vin1a_d4_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9B8++0x3 line.long 0x0 "CFG_VIN1A_D4_OEN,Delay Select Value in binary coded form for cfg_vin1a_d4_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9BC++0x3 line.long 0x0 "CFG_VIN1A_D4_OUT,Delay Select Value in binary coded form for cfg_vin1a_d4_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9C0++0x3 line.long 0x0 "CFG_VIN1A_D5_IN,Delay Select Value in binary coded form for cfg_vin1a_d5_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9C4++0x3 line.long 0x0 "CFG_VIN1A_D5_OEN,Delay Select Value in binary coded form for cfg_vin1a_d5_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9C8++0x3 line.long 0x0 "CFG_VIN1A_D5_OUT,Delay Select Value in binary coded form for cfg_vin1a_d5_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9CC++0x3 line.long 0x0 "CFG_VIN1A_D6_IN,Delay Select Value in binary coded form for cfg_vin1a_d6_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9D0++0x3 line.long 0x0 "CFG_VIN1A_D6_OEN,Delay Select Value in binary coded form for cfg_vin1a_d6_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9D4++0x3 line.long 0x0 "CFG_VIN1A_D6_OUT,Delay Select Value in binary coded form for cfg_vin1a_d6_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9D8++0x3 line.long 0x0 "CFG_VIN1A_D7_IN,Delay Select Value in binary coded form for cfg_vin1a_d7_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9DC++0x3 line.long 0x0 "CFG_VIN1A_D7_OEN,Delay Select Value in binary coded form for cfg_vin1a_d7_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9E0++0x3 line.long 0x0 "CFG_VIN1A_D7_OUT,Delay Select Value in binary coded form for cfg_vin1a_d7_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9E4++0x3 line.long 0x0 "CFG_VIN1A_D8_IN,Delay Select Value in binary coded form for cfg_vin1a_d8_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9E8++0x3 line.long 0x0 "CFG_VIN1A_D8_OEN,Delay Select Value in binary coded form for cfg_vin1a_d8_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9EC++0x3 line.long 0x0 "CFG_VIN1A_D8_OUT,Delay Select Value in binary coded form for cfg_vin1a_d8_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9F0++0x3 line.long 0x0 "CFG_VIN1A_D9_IN,Delay Select Value in binary coded form for cfg_vin1a_d9_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9F4++0x3 line.long 0x0 "CFG_VIN1A_D9_OEN,Delay Select Value in binary coded form for cfg_vin1a_d9_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9F8++0x3 line.long 0x0 "CFG_VIN1A_D9_OUT,Delay Select Value in binary coded form for cfg_vin1a_d9_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x9FC++0x3 line.long 0x0 "CFG_VIN1A_DE0_IN,Delay Select Value in binary coded form for cfg_vin1a_de0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA00++0x3 line.long 0x0 "CFG_VIN1A_DE0_OEN,Delay Select Value in binary coded form for cfg_vin1a_de0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA04++0x3 line.long 0x0 "CFG_VIN1A_DE0_OUT,Delay Select Value in binary coded form for cfg_vin1a_de0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA08++0x3 line.long 0x0 "CFG_VIN1A_FLD0_IN,Delay Select Value in binary coded form for cfg_vin1a_fld0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA0C++0x3 line.long 0x0 "CFG_VIN1A_FLD0_OEN,Delay Select Value in binary coded form for cfg_vin1a_fld0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA10++0x3 line.long 0x0 "CFG_VIN1A_FLD0_OUT,Delay Select Value in binary coded form for cfg_vin1a_fld0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA14++0x3 line.long 0x0 "CFG_VIN1A_HSYNC0_IN,Delay Select Value in binary coded form for cfg_vin1a_hsync0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA18++0x3 line.long 0x0 "CFG_VIN1A_HSYNC0_OEN,Delay Select Value in binary coded form for cfg_vin1a_hsync0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA1C++0x3 line.long 0x0 "CFG_VIN1A_HSYNC0_OUT,Delay Select Value in binary coded form for cfg_vin1a_hsync0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA20++0x3 line.long 0x0 "CFG_VIN1A_VSYNC0_IN,Delay Select Value in binary coded form for cfg_vin1a_vsync0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA24++0x3 line.long 0x0 "CFG_VIN1A_VSYNC0_OEN,Delay Select Value in binary coded form for cfg_vin1a_vsync0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA28++0x3 line.long 0x0 "CFG_VIN1A_VSYNC0_OUT,Delay Select Value in binary coded form for cfg_vin1a_vsync0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA2C++0x3 line.long 0x0 "CFG_VIN1B_CLK1_IN,Delay Select Value in binary coded form for cfg_vin1b_clk1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA30++0x3 line.long 0x0 "CFG_VIN1B_CLK1_OEN,Delay Select Value in binary coded form for cfg_vin1b_clk1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA34++0x3 line.long 0x0 "CFG_VIN1B_CLK1_OUT,Delay Select Value in binary coded form for cfg_vin1b_clk1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA38++0x3 line.long 0x0 "CFG_VIN2A_CLK0_IN,Delay Select Value in binary coded form for cfg_vin2a_clk0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA3C++0x3 line.long 0x0 "CFG_VIN2A_CLK0_OEN,Delay Select Value in binary coded form for cfg_vin2a_clk0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA40++0x3 line.long 0x0 "CFG_VIN2A_CLK0_OUT,Delay Select Value in binary coded form for cfg_vin2a_clk0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA44++0x3 line.long 0x0 "CFG_VIN2A_D0_IN,Delay Select Value in binary coded form for cfg_vin2a_d0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA48++0x3 line.long 0x0 "CFG_VIN2A_D0_OEN,Delay Select Value in binary coded form for cfg_vin2a_d0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA4C++0x3 line.long 0x0 "CFG_VIN2A_D0_OUT,Delay Select Value in binary coded form for cfg_vin2a_d0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA50++0x3 line.long 0x0 "CFG_VIN2A_D10_IN,Delay Select Value in binary coded form for cfg_vin2a_d10_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA54++0x3 line.long 0x0 "CFG_VIN2A_D10_OEN,Delay Select Value in binary coded form for cfg_vin2a_d10_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA58++0x3 line.long 0x0 "CFG_VIN2A_D10_OUT,Delay Select Value in binary coded form for cfg_vin2a_d10_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA5C++0x3 line.long 0x0 "CFG_VIN2A_D11_IN,Delay Select Value in binary coded form for cfg_vin2a_d11_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA60++0x3 line.long 0x0 "CFG_VIN2A_D11_OEN,Delay Select Value in binary coded form for cfg_vin2a_d11_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA64++0x3 line.long 0x0 "CFG_VIN2A_D11_OUT,Delay Select Value in binary coded form for cfg_vin2a_d11_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA68++0x3 line.long 0x0 "CFG_VIN2A_D12_IN,Delay Select Value in binary coded form for cfg_vin2a_d12_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA6C++0x3 line.long 0x0 "CFG_VIN2A_D12_OEN,Delay Select Value in binary coded form for cfg_vin2a_d12_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA70++0x3 line.long 0x0 "CFG_VIN2A_D12_OUT,Delay Select Value in binary coded form for cfg_vin2a_d12_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA74++0x3 line.long 0x0 "CFG_VIN2A_D13_IN,Delay Select Value in binary coded form for cfg_vin2a_d13_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA78++0x3 line.long 0x0 "CFG_VIN2A_D13_OEN,Delay Select Value in binary coded form for cfg_vin2a_d13_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA7C++0x3 line.long 0x0 "CFG_VIN2A_D13_OUT,Delay Select Value in binary coded form for cfg_vin2a_d13_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA80++0x3 line.long 0x0 "CFG_VIN2A_D14_IN,Delay Select Value in binary coded form for cfg_vin2a_d14_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA84++0x3 line.long 0x0 "CFG_VIN2A_D14_OEN,Delay Select Value in binary coded form for cfg_vin2a_d14_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA88++0x3 line.long 0x0 "CFG_VIN2A_D14_OUT,Delay Select Value in binary coded form for cfg_vin2a_d14_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA8C++0x3 line.long 0x0 "CFG_VIN2A_D15_IN,Delay Select Value in binary coded form for cfg_vin2a_d15_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA90++0x3 line.long 0x0 "CFG_VIN2A_D15_OEN,Delay Select Value in binary coded form for cfg_vin2a_d15_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA94++0x3 line.long 0x0 "CFG_VIN2A_D15_OUT,Delay Select Value in binary coded form for cfg_vin2a_d15_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA98++0x3 line.long 0x0 "CFG_VIN2A_D16_IN,Delay Select Value in binary coded form for cfg_vin2a_d16_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xA9C++0x3 line.long 0x0 "CFG_VIN2A_D16_OEN,Delay Select Value in binary coded form for cfg_vin2a_d16_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAA0++0x3 line.long 0x0 "CFG_VIN2A_D16_OUT,Delay Select Value in binary coded form for cfg_vin2a_d16_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAA4++0x3 line.long 0x0 "CFG_VIN2A_D17_IN,Delay Select Value in binary coded form for cfg_vin2a_d17_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAA8++0x3 line.long 0x0 "CFG_VIN2A_D17_OEN,Delay Select Value in binary coded form for cfg_vin2a_d17_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAAC++0x3 line.long 0x0 "CFG_VIN2A_D17_OUT,Delay Select Value in binary coded form for cfg_vin2a_d17_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAB0++0x3 line.long 0x0 "CFG_VIN2A_D18_IN,Delay Select Value in binary coded form for cfg_vin2a_d18_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAB4++0x3 line.long 0x0 "CFG_VIN2A_D18_OEN,Delay Select Value in binary coded form for cfg_vin2a_d18_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAB8++0x3 line.long 0x0 "CFG_VIN2A_D18_OUT,Delay Select Value in binary coded form for cfg_vin2a_d18_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xABC++0x3 line.long 0x0 "CFG_VIN2A_D19_IN,Delay Select Value in binary coded form for cfg_vin2a_d19_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAC0++0x3 line.long 0x0 "CFG_VIN2A_D19_OEN,Delay Select Value in binary coded form for cfg_vin2a_d19_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAC4++0x3 line.long 0x0 "CFG_VIN2A_D19_OUT,Delay Select Value in binary coded form for cfg_vin2a_d19_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAC8++0x3 line.long 0x0 "CFG_VIN2A_D1_IN,Delay Select Value in binary coded form for cfg_vin2a_d1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xACC++0x3 line.long 0x0 "CFG_VIN2A_D1_OEN,Delay Select Value in binary coded form for cfg_vin2a_d1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAD0++0x3 line.long 0x0 "CFG_VIN2A_D1_OUT,Delay Select Value in binary coded form for cfg_vin2a_d1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAD4++0x3 line.long 0x0 "CFG_VIN2A_D20_IN,Delay Select Value in binary coded form for cfg_vin2a_d20_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAD8++0x3 line.long 0x0 "CFG_VIN2A_D20_OEN,Delay Select Value in binary coded form for cfg_vin2a_d20_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xADC++0x3 line.long 0x0 "CFG_VIN2A_D20_OUT,Delay Select Value in binary coded form for cfg_vin2a_d20_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAE0++0x3 line.long 0x0 "CFG_VIN2A_D21_IN,Delay Select Value in binary coded form for cfg_vin2a_d21_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAE4++0x3 line.long 0x0 "CFG_VIN2A_D21_OEN,Delay Select Value in binary coded form for cfg_vin2a_d21_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAE8++0x3 line.long 0x0 "CFG_VIN2A_D21_OUT,Delay Select Value in binary coded form for cfg_vin2a_d21_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAEC++0x3 line.long 0x0 "CFG_VIN2A_D22_IN,Delay Select Value in binary coded form for cfg_vin2a_d22_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAF0++0x3 line.long 0x0 "CFG_VIN2A_D22_OEN,Delay Select Value in binary coded form for cfg_vin2a_d22_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAF4++0x3 line.long 0x0 "CFG_VIN2A_D22_OUT,Delay Select Value in binary coded form for cfg_vin2a_d22_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAF8++0x3 line.long 0x0 "CFG_VIN2A_D23_IN,Delay Select Value in binary coded form for cfg_vin2a_d23_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xAFC++0x3 line.long 0x0 "CFG_VIN2A_D23_OEN,Delay Select Value in binary coded form for cfg_vin2a_d23_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB00++0x3 line.long 0x0 "CFG_VIN2A_D23_OUT,Delay Select Value in binary coded form for cfg_vin2a_d23_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB04++0x3 line.long 0x0 "CFG_VIN2A_D2_IN,Delay Select Value in binary coded form for cfg_vin2a_d2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB08++0x3 line.long 0x0 "CFG_VIN2A_D2_OEN,Delay Select Value in binary coded form for cfg_vin2a_d2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB0C++0x3 line.long 0x0 "CFG_VIN2A_D2_OUT,Delay Select Value in binary coded form for cfg_vin2a_d2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB10++0x3 line.long 0x0 "CFG_VIN2A_D3_IN,Delay Select Value in binary coded form for cfg_vin2a_d3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB14++0x3 line.long 0x0 "CFG_VIN2A_D3_OEN,Delay Select Value in binary coded form for cfg_vin2a_d3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB18++0x3 line.long 0x0 "CFG_VIN2A_D3_OUT,Delay Select Value in binary coded form for cfg_vin2a_d3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB1C++0x3 line.long 0x0 "CFG_VIN2A_D4_IN,Delay Select Value in binary coded form for cfg_vin2a_d4_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB20++0x3 line.long 0x0 "CFG_VIN2A_D4_OEN,Delay Select Value in binary coded form for cfg_vin2a_d4_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB24++0x3 line.long 0x0 "CFG_VIN2A_D4_OUT,Delay Select Value in binary coded form for cfg_vin2a_d4_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB28++0x3 line.long 0x0 "CFG_VIN2A_D5_IN,Delay Select Value in binary coded form for cfg_vin2a_d5_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB2C++0x3 line.long 0x0 "CFG_VIN2A_D5_OEN,Delay Select Value in binary coded form for cfg_vin2a_d5_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB30++0x3 line.long 0x0 "CFG_VIN2A_D5_OUT,Delay Select Value in binary coded form for cfg_vin2a_d5_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB34++0x3 line.long 0x0 "CFG_VIN2A_D6_IN,Delay Select Value in binary coded form for cfg_vin2a_d6_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB38++0x3 line.long 0x0 "CFG_VIN2A_D6_OEN,Delay Select Value in binary coded form for cfg_vin2a_d6_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB3C++0x3 line.long 0x0 "CFG_VIN2A_D6_OUT,Delay Select Value in binary coded form for cfg_vin2a_d6_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB40++0x3 line.long 0x0 "CFG_VIN2A_D7_IN,Delay Select Value in binary coded form for cfg_vin2a_d7_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB44++0x3 line.long 0x0 "CFG_VIN2A_D7_OEN,Delay Select Value in binary coded form for cfg_vin2a_d7_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB48++0x3 line.long 0x0 "CFG_VIN2A_D7_OUT,Delay Select Value in binary coded form for cfg_vin2a_d7_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB4C++0x3 line.long 0x0 "CFG_VIN2A_D8_IN,Delay Select Value in binary coded form for cfg_vin2a_d8_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB50++0x3 line.long 0x0 "CFG_VIN2A_D8_OEN,Delay Select Value in binary coded form for cfg_vin2a_d8_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB54++0x3 line.long 0x0 "CFG_VIN2A_D8_OUT,Delay Select Value in binary coded form for cfg_vin2a_d8_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB58++0x3 line.long 0x0 "CFG_VIN2A_D9_IN,Delay Select Value in binary coded form for cfg_vin2a_d9_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB5C++0x3 line.long 0x0 "CFG_VIN2A_D9_OEN,Delay Select Value in binary coded form for cfg_vin2a_d9_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB60++0x3 line.long 0x0 "CFG_VIN2A_D9_OUT,Delay Select Value in binary coded form for cfg_vin2a_d9_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB64++0x3 line.long 0x0 "CFG_VIN2A_DE0_IN,Delay Select Value in binary coded form for cfg_vin2a_de0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB68++0x3 line.long 0x0 "CFG_VIN2A_DE0_OEN,Delay Select Value in binary coded form for cfg_vin2a_de0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB6C++0x3 line.long 0x0 "CFG_VIN2A_DE0_OUT,Delay Select Value in binary coded form for cfg_vin2a_de0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB70++0x3 line.long 0x0 "CFG_VIN2A_FLD0_IN,Delay Select Value in binary coded form for cfg_vin2a_fld0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB74++0x3 line.long 0x0 "CFG_VIN2A_FLD0_OEN,Delay Select Value in binary coded form for cfg_vin2a_fld0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB78++0x3 line.long 0x0 "CFG_VIN2A_FLD0_OUT,Delay Select Value in binary coded form for cfg_vin2a_fld0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB7C++0x3 line.long 0x0 "CFG_VIN2A_HSYNC0_IN,Delay Select Value in binary coded form for cfg_vin2a_hsync0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB80++0x3 line.long 0x0 "CFG_VIN2A_HSYNC0_OEN,Delay Select Value in binary coded form for cfg_vin2a_hsync0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB84++0x3 line.long 0x0 "CFG_VIN2A_HSYNC0_OUT,Delay Select Value in binary coded form for cfg_vin2a_hsync0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB88++0x3 line.long 0x0 "CFG_VIN2A_VSYNC0_IN,Delay Select Value in binary coded form for cfg_vin2a_vsync0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB8C++0x3 line.long 0x0 "CFG_VIN2A_VSYNC0_OEN,Delay Select Value in binary coded form for cfg_vin2a_vsync0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB90++0x3 line.long 0x0 "CFG_VIN2A_VSYNC0_OUT,Delay Select Value in binary coded form for cfg_vin2a_vsync0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB94++0x3 line.long 0x0 "CFG_VOUT1_CLK_IN,Delay Select Value in binary coded form for cfg_vout1_clk_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB98++0x3 line.long 0x0 "CFG_VOUT1_CLK_OEN,Delay Select Value in binary coded form for cfg_vout1_clk_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xB9C++0x3 line.long 0x0 "CFG_VOUT1_CLK_OUT,Delay Select Value in binary coded form for cfg_vout1_clk_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBA0++0x3 line.long 0x0 "CFG_VOUT1_D0_IN,Delay Select Value in binary coded form for cfg_vout1_d0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBA4++0x3 line.long 0x0 "CFG_VOUT1_D0_OEN,Delay Select Value in binary coded form for cfg_vout1_d0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBA8++0x3 line.long 0x0 "CFG_VOUT1_D0_OUT,Delay Select Value in binary coded form for cfg_vout1_d0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBAC++0x3 line.long 0x0 "CFG_VOUT1_D10_IN,Delay Select Value in binary coded form for cfg_vout1_d10_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBB0++0x3 line.long 0x0 "CFG_VOUT1_D10_OEN,Delay Select Value in binary coded form for cfg_vout1_d10_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBB4++0x3 line.long 0x0 "CFG_VOUT1_D10_OUT,Delay Select Value in binary coded form for cfg_vout1_d10_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBB8++0x3 line.long 0x0 "CFG_VOUT1_D11_IN,Delay Select Value in binary coded form for cfg_vout1_d11_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBBC++0x3 line.long 0x0 "CFG_VOUT1_D11_OEN,Delay Select Value in binary coded form for cfg_vout1_d11_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBC0++0x3 line.long 0x0 "CFG_VOUT1_D11_OUT,Delay Select Value in binary coded form for cfg_vout1_d11_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBC4++0x3 line.long 0x0 "CFG_VOUT1_D12_IN,Delay Select Value in binary coded form for cfg_vout1_d12_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBC8++0x3 line.long 0x0 "CFG_VOUT1_D12_OEN,Delay Select Value in binary coded form for cfg_vout1_d12_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBCC++0x3 line.long 0x0 "CFG_VOUT1_D12_OUT,Delay Select Value in binary coded form for cfg_vout1_d12_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBD0++0x3 line.long 0x0 "CFG_VOUT1_D13_IN,Delay Select Value in binary coded form for cfg_vout1_d13_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBD4++0x3 line.long 0x0 "CFG_VOUT1_D13_OEN,Delay Select Value in binary coded form for cfg_vout1_d13_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBD8++0x3 line.long 0x0 "CFG_VOUT1_D13_OUT,Delay Select Value in binary coded form for cfg_vout1_d13_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBDC++0x3 line.long 0x0 "CFG_VOUT1_D14_IN,Delay Select Value in binary coded form for cfg_vout1_d14_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBE0++0x3 line.long 0x0 "CFG_VOUT1_D14_OEN,Delay Select Value in binary coded form for cfg_vout1_d14_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBE4++0x3 line.long 0x0 "CFG_VOUT1_D14_OUT,Delay Select Value in binary coded form for cfg_vout1_d14_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBE8++0x3 line.long 0x0 "CFG_VOUT1_D15_IN,Delay Select Value in binary coded form for cfg_vout1_d15_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBEC++0x3 line.long 0x0 "CFG_VOUT1_D15_OEN,Delay Select Value in binary coded form for cfg_vout1_d15_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBF0++0x3 line.long 0x0 "CFG_VOUT1_D15_OUT,Delay Select Value in binary coded form for cfg_vout1_d15_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBF4++0x3 line.long 0x0 "CFG_VOUT1_D16_IN,Delay Select Value in binary coded form for cfg_vout1_d16_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBF8++0x3 line.long 0x0 "CFG_VOUT1_D16_OEN,Delay Select Value in binary coded form for cfg_vout1_d16_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xBFC++0x3 line.long 0x0 "CFG_VOUT1_D16_OUT,Delay Select Value in binary coded form for cfg_vout1_d16_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC00++0x3 line.long 0x0 "CFG_VOUT1_D17_IN,Delay Select Value in binary coded form for cfg_vout1_d17_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC04++0x3 line.long 0x0 "CFG_VOUT1_D17_OEN,Delay Select Value in binary coded form for cfg_vout1_d17_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC08++0x3 line.long 0x0 "CFG_VOUT1_D17_OUT,Delay Select Value in binary coded form for cfg_vout1_d17_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC0C++0x3 line.long 0x0 "CFG_VOUT1_D18_IN,Delay Select Value in binary coded form for cfg_vout1_d18_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC10++0x3 line.long 0x0 "CFG_VOUT1_D18_OEN,Delay Select Value in binary coded form for cfg_vout1_d18_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC14++0x3 line.long 0x0 "CFG_VOUT1_D18_OUT,Delay Select Value in binary coded form for cfg_vout1_d18_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC18++0x3 line.long 0x0 "CFG_VOUT1_D19_IN,Delay Select Value in binary coded form for cfg_vout1_d19_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC1C++0x3 line.long 0x0 "CFG_VOUT1_D19_OEN,Delay Select Value in binary coded form for cfg_vout1_d19_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC20++0x3 line.long 0x0 "CFG_VOUT1_D19_OUT,Delay Select Value in binary coded form for cfg_vout1_d19_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC24++0x3 line.long 0x0 "CFG_VOUT1_D1_IN,Delay Select Value in binary coded form for cfg_vout1_d1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC28++0x3 line.long 0x0 "CFG_VOUT1_D1_OEN,Delay Select Value in binary coded form for cfg_vout1_d1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC2C++0x3 line.long 0x0 "CFG_VOUT1_D1_OUT,Delay Select Value in binary coded form for cfg_vout1_d1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC30++0x3 line.long 0x0 "CFG_VOUT1_D20_IN,Delay Select Value in binary coded form for cfg_vout1_d20_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC34++0x3 line.long 0x0 "CFG_VOUT1_D20_OEN,Delay Select Value in binary coded form for cfg_vout1_d20_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC38++0x3 line.long 0x0 "CFG_VOUT1_D20_OUT,Delay Select Value in binary coded form for cfg_vout1_d20_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC3C++0x3 line.long 0x0 "CFG_VOUT1_D21_IN,Delay Select Value in binary coded form for cfg_vout1_d21_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC40++0x3 line.long 0x0 "CFG_VOUT1_D21_OEN,Delay Select Value in binary coded form for cfg_vout1_d21_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC44++0x3 line.long 0x0 "CFG_VOUT1_D21_OUT,Delay Select Value in binary coded form for cfg_vout1_d21_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC48++0x3 line.long 0x0 "CFG_VOUT1_D22_IN,Delay Select Value in binary coded form for cfg_vout1_d22_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC4C++0x3 line.long 0x0 "CFG_VOUT1_D22_OEN,Delay Select Value in binary coded form for cfg_vout1_d22_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC50++0x3 line.long 0x0 "CFG_VOUT1_D22_OUT,Delay Select Value in binary coded form for cfg_vout1_d22_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC54++0x3 line.long 0x0 "CFG_VOUT1_D23_IN,Delay Select Value in binary coded form for cfg_vout1_d23_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC58++0x3 line.long 0x0 "CFG_VOUT1_D23_OEN,Delay Select Value in binary coded form for cfg_vout1_d23_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC5C++0x3 line.long 0x0 "CFG_VOUT1_D23_OUT,Delay Select Value in binary coded form for cfg_vout1_d23_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC60++0x3 line.long 0x0 "CFG_VOUT1_D2_IN,Delay Select Value in binary coded form for cfg_vout1_d2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC64++0x3 line.long 0x0 "CFG_VOUT1_D2_OEN,Delay Select Value in binary coded form for cfg_vout1_d2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC68++0x3 line.long 0x0 "CFG_VOUT1_D2_OUT,Delay Select Value in binary coded form for cfg_vout1_d2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC6C++0x3 line.long 0x0 "CFG_VOUT1_D3_IN,Delay Select Value in binary coded form for cfg_vout1_d3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC70++0x3 line.long 0x0 "CFG_VOUT1_D3_OEN,Delay Select Value in binary coded form for cfg_vout1_d3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC74++0x3 line.long 0x0 "CFG_VOUT1_D3_OUT,Delay Select Value in binary coded form for cfg_vout1_d3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC78++0x3 line.long 0x0 "CFG_VOUT1_D4_IN,Delay Select Value in binary coded form for cfg_vout1_d4_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC7C++0x3 line.long 0x0 "CFG_VOUT1_D4_OEN,Delay Select Value in binary coded form for cfg_vout1_d4_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC80++0x3 line.long 0x0 "CFG_VOUT1_D4_OUT,Delay Select Value in binary coded form for cfg_vout1_d4_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC84++0x3 line.long 0x0 "CFG_VOUT1_D5_IN,Delay Select Value in binary coded form for cfg_vout1_d5_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC88++0x3 line.long 0x0 "CFG_VOUT1_D5_OEN,Delay Select Value in binary coded form for cfg_vout1_d5_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC8C++0x3 line.long 0x0 "CFG_VOUT1_D5_OUT,Delay Select Value in binary coded form for cfg_vout1_d5_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC90++0x3 line.long 0x0 "CFG_VOUT1_D6_IN,Delay Select Value in binary coded form for cfg_vout1_d6_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC94++0x3 line.long 0x0 "CFG_VOUT1_D6_OEN,Delay Select Value in binary coded form for cfg_vout1_d6_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC98++0x3 line.long 0x0 "CFG_VOUT1_D6_OUT,Delay Select Value in binary coded form for cfg_vout1_d6_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xC9C++0x3 line.long 0x0 "CFG_VOUT1_D7_IN,Delay Select Value in binary coded form for cfg_vout1_d7_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCA0++0x3 line.long 0x0 "CFG_VOUT1_D7_OEN,Delay Select Value in binary coded form for cfg_vout1_d7_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCA4++0x3 line.long 0x0 "CFG_VOUT1_D7_OUT,Delay Select Value in binary coded form for cfg_vout1_d7_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCA8++0x3 line.long 0x0 "CFG_VOUT1_D8_IN,Delay Select Value in binary coded form for cfg_vout1_d8_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCAC++0x3 line.long 0x0 "CFG_VOUT1_D8_OEN,Delay Select Value in binary coded form for cfg_vout1_d8_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCB0++0x3 line.long 0x0 "CFG_VOUT1_D8_OUT,Delay Select Value in binary coded form for cfg_vout1_d8_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCB4++0x3 line.long 0x0 "CFG_VOUT1_D9_IN,Delay Select Value in binary coded form for cfg_vout1_d9_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCB8++0x3 line.long 0x0 "CFG_VOUT1_D9_OEN,Delay Select Value in binary coded form for cfg_vout1_d9_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCBC++0x3 line.long 0x0 "CFG_VOUT1_D9_OUT,Delay Select Value in binary coded form for cfg_vout1_d9_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCC0++0x3 line.long 0x0 "CFG_VOUT1_DE_IN,Delay Select Value in binary coded form for cfg_vout1_de_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCC4++0x3 line.long 0x0 "CFG_VOUT1_DE_OEN,Delay Select Value in binary coded form for cfg_vout1_de_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCC8++0x3 line.long 0x0 "CFG_VOUT1_DE_OUT,Delay Select Value in binary coded form for cfg_vout1_de_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCCC++0x3 line.long 0x0 "CFG_VOUT1_FLD_IN,Delay Select Value in binary coded form for cfg_vout1_fld_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCD0++0x3 line.long 0x0 "CFG_VOUT1_FLD_OEN,Delay Select Value in binary coded form for cfg_vout1_fld_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCD4++0x3 line.long 0x0 "CFG_VOUT1_FLD_OUT,Delay Select Value in binary coded form for cfg_vout1_fld_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCD8++0x3 line.long 0x0 "CFG_VOUT1_HSYNC_IN,Delay Select Value in binary coded form for cfg_vout1_hsync_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCDC++0x3 line.long 0x0 "CFG_VOUT1_HSYNC_OEN,Delay Select Value in binary coded form for cfg_vout1_hsync_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCE0++0x3 line.long 0x0 "CFG_VOUT1_HSYNC_OUT,Delay Select Value in binary coded form for cfg_vout1_hsync_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCE4++0x3 line.long 0x0 "CFG_VOUT1_VSYNC_IN,Delay Select Value in binary coded form for cfg_vout1_vsync_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCE8++0x3 line.long 0x0 "CFG_VOUT1_VSYNC_OEN,Delay Select Value in binary coded form for cfg_vout1_vsync_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCEC++0x3 line.long 0x0 "CFG_VOUT1_VSYNC_OUT,Delay Select Value in binary coded form for cfg_vout1_vsync_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCF0++0x3 line.long 0x0 "CFG_XREF_CLK0_IN,Delay Select Value in binary coded form for cfg_xref_clk0_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCF4++0x3 line.long 0x0 "CFG_XREF_CLK0_OEN,Delay Select Value in binary coded form for cfg_xref_clk0_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCF8++0x3 line.long 0x0 "CFG_XREF_CLK0_OUT,Delay Select Value in binary coded form for cfg_xref_clk0_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xCFC++0x3 line.long 0x0 "CFG_XREF_CLK1_IN,Delay Select Value in binary coded form for cfg_xref_clk1_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD00++0x3 line.long 0x0 "CFG_XREF_CLK1_OEN,Delay Select Value in binary coded form for cfg_xref_clk1_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD04++0x3 line.long 0x0 "CFG_XREF_CLK1_OUT,Delay Select Value in binary coded form for cfg_xref_clk1_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD08++0x3 line.long 0x0 "CFG_XREF_CLK2_IN,Delay Select Value in binary coded form for cfg_xref_clk2_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD0C++0x3 line.long 0x0 "CFG_XREF_CLK2_OEN,Delay Select Value in binary coded form for cfg_xref_clk2_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD10++0x3 line.long 0x0 "CFG_XREF_CLK2_OUT,Delay Select Value in binary coded form for cfg_xref_clk2_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD14++0x3 line.long 0x0 "CFG_XREF_CLK3_IN,Delay Select Value in binary coded form for cfg_xref_clk3_in interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD18++0x3 line.long 0x0 "CFG_XREF_CLK3_OEN,Delay Select Value in binary coded form for cfg_xref_clk3_oen interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xD1C++0x3 line.long 0x0 "CFG_XREF_CLK3_OUT,Delay Select Value in binary coded form for cfg_xref_clk3_out interface" hexmask.long.word 0x0 0.--9. 1. " BINARY_DELAY ,Delay Select Value in binary coded form. Indicates the number of coarse (9:5) and fine (4:0) delay elements to be used on the delay line connected to this pad." bitfld.long 0x0 10. " LOCK_BIT ,When '1', prevents HW update to this MMR. When '0', allows HW update of this MMR." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--17. " SIGNATURE ,Write to this register will succeed only if data on these bits carries a signature of 6'h29 (6'b101001)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," width 0x0B tree.end tree "CTRL_MODULE_CORE" base ad:0x4A002000 width 49. group.byte 0x134++0x3 line.long 0x0 "CTRL_CORE_STATUS,Control Module Status Register" bitfld.long 0x0 0.--5. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--8. " DEVICE_TYPE ,Device type captured at reset time. Read 0x3 = General Purpose (GP)" "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x148++0x3 line.long 0x0 "CTRL_CORE_SEC_ERR_STATUS_FUNC_1,Firewall Error Status functional Register 1" bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " L3RAM1_FW_ERROR ,L3RAM1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 2. " GPMC_FW_ERROR ,GPMC firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 3. " EMIF_FW_ERROR ,EMIF firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 4. " IVAHD_FW_ERROR ,IVAHD firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 5. " IPU1_FW_ERROR ,IPU1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 6. " IVAHD_SL2_FW_ERROR ,IVAHD SL2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 7.--12. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 13. " GPU_FW_ERROR ,GPU firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 14. " DSS_FW_ERROR ,DSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 15. " RESERVED ," "0,1" bitfld.long 0x0 16. " L4_PERIPH1_FW_ERROR ,L4 periph1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 17. " L4_CONFIG_FW_ERROR ,L4 config firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 18. " DEBUGSS_FW_ERROR ,DebugSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 19.--21. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 22. " L4_WAKEUP_FW_ERROR ,L4 wakeup firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 23. " BB2D_FW_ERROR ,BB2D firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 24.--27. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28. " EVE1_FW_ERROR ,EVE1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 29. " EVE2_FW_ERROR ,EVE2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 30. " EVE3_FW_ERROR ,EVE3 firewall 0x0: No error firewall 0x1: Error from firewall" "0,1" bitfld.long 0x0 31. " EVE4_FW_ERROR ,EVE4 firewall 0x0: No error firewall 0x1: Error from firewall" "0,1" group.byte 0x150++0x3 line.long 0x0 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_1,Firewall Error Status Debug Register 1" bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " L3RAM1_DBGFW_ERROR ,L3RAM1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 2. " GPMC_DBGFW_ERROR ,GPMC debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 3. " EMIF_DBGFW_ERROR ,EMIF debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 4. " IVAHD_DBGFW_ERROR ,IVAHD debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 5. " IPU1_DBGFW_ERROR ,IPU1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 6. " IVAHD_SL2_DBGFW_ERROR ,IVAHD SL2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 7.--12. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 13. " GPU_DBGFW_ERROR ,GPU debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 14. " DSS_DBGFW_ERROR ,DSS debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 15. " RESERVED ," "0,1" bitfld.long 0x0 16. " L4_PERIPH1_DBGFW_ERROR ,L4 periph1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 17. " L4_CONFIG_DBGFW_ERROR ,L4 config firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 18. " DEBUGSS_DBGFW_ERROR ,DebugSS firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 19.--21. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 22. " L4_WAKEUP_DBGFW_ERROR ,L4 wakeup firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 23. " BB2D_DBGFW_ERROR ,BB2D firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 24.--27. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 28. " EVE1_DBGFW_ERROR ,EVE1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 29. " EVE2_DBGFW_ERROR ,EVE2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 30. " EVE3_DBGFW_ERROR ,EVE3 firewall 0x0: No error firewall 0x1: Error from firewall" "0,1" bitfld.long 0x0 31. " EVE4_DBGFW_ERROR ,EVE4 firewall 0x0: No error firewall 0x1: Error from firewall" "0,1" group.byte 0x15C++0x3 line.long 0x0 "CTRL_CORE_MPU_FORCEWRNP,FORCE WRITE NON POSTED" bitfld.long 0x0 0. " MPU_FORCEWRNP ,Force mpu write non posted transactions 0x0 = disable force wrnp 0x1 = force wrnp" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x194++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_0,Standard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_0 ," group.byte 0x198++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_1,Standard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_1 ," group.byte 0x19C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_2,Standard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_2 ," group.byte 0x1A0++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_3,Standard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_3 ," group.byte 0x1A4++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_4,Standard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_4 ," group.byte 0x1A8++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_5,Standard Fuse OPP VDD_GPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_5 ," group.byte 0x1AC++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_0,Standard Fuse OPP VDD_MPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_0 ," group.byte 0x1B0++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_1,Standard Fuse OPP VDD_MPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_1 ," group.byte 0x1B4++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_2,Standard Fuse OPP VDD_MPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_2 ," group.byte 0x1B8++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_3,Standard Fuse OPP VDD_MPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_3 ," group.byte 0x1BC++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_4,Standard Fuse OPP VDD_MPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_4 ," group.byte 0x1C0++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_5,Standard Fuse OPP VDD_MPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_5 ," group.byte 0x1C4++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_6,Standard Fuse OPP VDD_MPU [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_6 ," group.byte 0x1C8++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_7,Standard Fuse OPP VDD_MPU [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_7 ," group.byte 0x1CC++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_0,Standard Fuse OPP VDD_CORE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_CORE_0 ," group.byte 0x1D0++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_1,Standard Fuse OPP VDD_CORE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_CORE_1 ," group.byte 0x1D4++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_2,Standard Fuse OPP VDD_CORE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_CORE_2 ," group.byte 0x1D8++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_3,Standard Fuse OPP VDD_CORE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_CORE_3 ," group.byte 0x1DC++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_4,Standard Fuse OPP VDD_CORE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_CORE_4 ," group.byte 0x1E0++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_BGAP_GPU,Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 0.--7. 1. " STD_FUSE_OPP_BGAP_GPU_3 ,Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 8.--15. 1. " STD_FUSE_OPP_BGAP_GPU_2 ,Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." textline " " hexmask.long.byte 0x0 16.--23. 1. " STD_FUSE_OPP_BGAP_GPU_1 ,Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 24.--31. 1. " STD_FUSE_OPP_BGAP_GPU_0 ,Trim values for GPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." group.byte 0x1E4++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_BGAP_MPU,Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 0.--7. 1. " STD_FUSE_OPP_BGAP_MPU_3 ,Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 8.--15. 1. " STD_FUSE_OPP_BGAP_MPU_2 ,Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." textline " " hexmask.long.byte 0x0 16.--23. 1. " STD_FUSE_OPP_BGAP_MPU_1 ,Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 24.--31. 1. " STD_FUSE_OPP_BGAP_MPU_0 ,Trim values for MPU associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." group.byte 0x1E8++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_BGAP_CORE,Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 0.--7. 1. " STD_FUSE_OPP_BGAP_CORE_3 ,Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 8.--15. 1. " STD_FUSE_OPP_BGAP_CORE_2 ,Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." textline " " hexmask.long.byte 0x0 16.--23. 1. " STD_FUSE_OPP_BGAP_CORE_1 ,Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 24.--31. 1. " STD_FUSE_OPP_BGAP_CORE_0 ,Trim values for CORE associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." group.byte 0x1EC++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_BGAP_MPU23,Standard Fuse OPP BGAP. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long.word 0x0 0.--15. 1. " STD_FUSE_OPP_BGAP_MPU2 ," hexmask.long.word 0x0 16.--31. 1. " STD_FUSE_OPP_BGAP_MPU3 ," group.byte 0x220++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_MPK_0,Standard Fuse keys. Root_public_key_hash [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_MPK_0 ," group.byte 0x224++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_MPK_1,Standard Fuse keys. Root_public_key_hash [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_MPK_1 ," group.byte 0x228++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_MPK_2,Standard Fuse keys. Root_public_key_hash [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_MPK_2 ," group.byte 0x22C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_MPK_3,Standard Fuse keys. Root_public_key_hash [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_MPK_3 ," group.byte 0x230++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_MPK_4,Standard Fuse keys. Root_public_key_hash [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_MPK_4 ," group.byte 0x234++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_MPK_5,Standard Fuse keys. Root_public_key_hash [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_MPK_5 ," group.byte 0x238++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_MPK_6,Standard Fuse keys. Root_public_key_hash [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_MPK_6 ," group.byte 0x23C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_MPK_7,Standard Fuse keys. Root_public_key_hash [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_MPK_7 ," group.byte 0x240++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_0,Standard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_LVT_0 ," group.byte 0x244++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_1,Standard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_LVT_1 ," group.byte 0x248++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_2,Standard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_LVT_2 ," group.byte 0x24C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_3,Standard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_LVT_3 ," group.byte 0x250++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_4,Standard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_LVT_4 ," group.byte 0x254++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_GPU_LVT_5,Standard Fuse OPP VDD_GPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_GPU_LVT_5 ," group.byte 0x258++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_0,Standard Fuse OPP VDD_MPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_LVT_0 ," group.byte 0x25C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_1,Standard Fuse OPP VDD_MPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_LVT_1 ," group.byte 0x260++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_2,Standard Fuse OPP VDD_MPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_LVT_2 ," group.byte 0x264++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_3,Standard Fuse OPP VDD_MPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_LVT_3 ," group.byte 0x268++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_4,Standard Fuse OPP VDD_MPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_LVT_4 ," group.byte 0x26C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_5,Standard Fuse OPP VDD_MPU [191:160]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_LVT_5 ," group.byte 0x270++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_6,Standard Fuse OPP VDD_MPU [223:192]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_LVT_6 ," group.byte 0x274++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_MPU_LVT_7,Standard Fuse OPP VDD_MPU [255:224]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_MPU_LVT_7 ," group.byte 0x2BC++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_SWRV_0,Customer Fuse keys. Software Version Control [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_SWRV_0 ," group.byte 0x2C0++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_SWRV_1,Customer Fuse keys. Software Version Control [063:032] (16 bits upper Redundant field) [FIELD F]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_SWRV_1 ," group.byte 0x2C4++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_SWRV_2,Customer Fuse keys. Software Version Control [095:064] (16 bits upper Redundant field) [FIELD E]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_SWRV_2 ," group.byte 0x2C8++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_SWRV_3,Customer Fuse keys. Software Version Control [127:096] (16 bits upper Redundant field) [FIELD D]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_SWRV_3 ," group.byte 0x2CC++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_SWRV_4,Customer Fuse keys. Software Version Control [159:127] (16 bits upper Redundant field) [FIELD C]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_SWRV_4 ," group.byte 0x2D0++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_SWRV_5,Customer Fuse keys. Software Version Control [191:160] (16 bits upper Redundant field) [FIELD B]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_SWRV_5 ," group.byte 0x2D4++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_SWRV_6,Customer Fuse keys. Software Version Control [223:192] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_SWRV_6 ," group.byte 0x300++0x3 line.long 0x0 "CTRL_CORE_DEV_CONF,This register is used to power down the USB2_PHY1" bitfld.long 0x0 0. " USBPHY_PD ,Power down the entire USB2_PHY1 (data, common module and UTMI). 0x0: Normal operation 0x1: Power down the USB2_PHY1" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x32C++0x3 line.long 0x0 "CTRL_CORE_TEMP_SENSOR_MPU,Control VBGAPTS temperature sensor and thermal comparator shutdown register" hexmask.long.word 0x0 0.--9. 1. " BGAP_DTEMP_MPU ,Temperature data from the ADC. Valid if EOCZ is low." bitfld.long 0x0 10. " BGAP_EOCZ_MPU ,ADC End of Conversion. Active low, when BGAP_DTEMP_MPU is valid." "0,1" textline " " bitfld.long 0x0 11. " BGAP_TMPSOFF_MPU ,This bit indicates the temperature sensor state." "0,1" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x330++0x3 line.long 0x0 "CTRL_CORE_TEMP_SENSOR_GPU,Control VBGAPTS temperature sensor and thermal comparator shutdown register" hexmask.long.word 0x0 0.--9. 1. " BGAP_DTEMP_GPU ,Temperature data from the ADC. Valid if EOCZ is low." bitfld.long 0x0 10. " BGAP_EOCZ_GPU ,ADC End of Conversion. Active low, when BGAP_DTEMP_GPU is valid." "0,1" textline " " bitfld.long 0x0 11. " BGAP_TMPSOFF_GPU ,This bit indicates the temperature sensor state." "0,1" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x334++0x3 line.long 0x0 "CTRL_CORE_TEMP_SENSOR_CORE,Control VBGAPTS temperature sensor and thermal comparator shutdown register" hexmask.long.word 0x0 0.--9. 1. " BGAP_DTEMP_CORE ,Temperature data from the ADC. Valid if EOCZ is low." bitfld.long 0x0 10. " BGAP_EOCZ_CORE ,ADC End of Conversion. Active low, when BGAP_DTEMP_CORE is valid." "0,1" textline " " bitfld.long 0x0 11. " BGAP_TMPSOFF_CORE ,This bit indicates the temperature sensor state." "0,1" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x358++0x3 line.long 0x0 "CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR,Cortex M4 register" hexmask.long.tbyte 0x0 0.--19. 1. " CORTEX_M4_MMUADDRTRANSLTR ,Used to save the mmu address boot" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x35C++0x3 line.long 0x0 "CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR,CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR" hexmask.long.tbyte 0x0 0.--19. 1. " CORTEX_M4_MMUADDRLOGICTR ," hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x360++0x3 line.long 0x0 "CTRL_CORE_HWOBS_CONTROL,HW observability control. This register enables or disables HW observability outputs (to save power primarily)" bitfld.long 0x0 0. " HWOBS_MACRO_ENABLE ,Used to gate observable signals coming from macros using the 32:bit HWOBS bus definition. When deasserted all outputs of the HWOBS busdef are set to zero. 0x0 = hw observability ports from macros are gated and set to zero 0x1 = hw observability ports from macros are not gated" "0,1" bitfld.long 0x0 1. " HWOBS_ALL_ONE_MODE ,Used to gate observable signals. When set all outputs are set to one (can be used to check the path from HW observability to external pads). 0x0 = hw observability ports are not gated 0x1 = hw observability ports are all set to 1" "0,1" textline " " bitfld.long 0x0 2. " HWOBS_ALL_ZERO_MODE ,Used to gate observable signals. When set all outputs are set to zero (can be used to check the path from HW observability to external pads). 0x0 = hw observability ports are not gated 0x1 = hw observability ports are all set to 0" "0,1" bitfld.long 0x0 3.--7. " HWOBS_CLKDIV_SEL ,Clock divider selection on po_hwobs(0). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9.--13. " HWOBS_CLKDIV_SEL_1 ,Clock divider selection on po_hwobs(1). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 14.--18. " HWOBS_CLKDIV_SEL_2 ,Clock divider selection on po_hwobs(2). 0x1 = output is not divided 0x2 = output is divided by 2 0x4 = output is divided by 4 0x8 = output is divided by 8 0x10 = output is divided by 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x370++0x3 line.long 0x0 "CTRL_CORE_PHY_POWER_USB,phy_power_usb" hexmask.long.word 0x0 0.--13. 1. " RESERVED ,Reserved" hexmask.long.byte 0x0 14.--21. 1. " USB_PWRCTL_CLK_CMD ,Powers up/down the USB3_PHY_TX and USB3_PHY_RX modules. This bit field is also used for partially power down these TX and RX modules. Each bit has the following meaning: Bit[14] - 0x1: Powers-up the USB3_PHY_RX Bit[15] - 0x1: Powers-up the USB3_PHY_TX Bit[16] - A dont care bit. Not used. Bit[17] - A dont care bit. Not used. Bit[18] - 0x1: Disables the synchronized power-up of USB3_PHY_TX with USB3_PHY_RX. The TX power-up is independent of the RX power-up. Bit[19] - 0x1: Disables the automatic power-cycling of USB3_PHY_RX in P3 power state when PLL_CLK stops and starts. Bit[20] - 0x1: Partially powers-down the USB3_PHY_RX when it is in P3 power state. DCC, Phase interpolator, Equalizer are disabled. Bit[21] - A dont care bit. Not used." textline " " hexmask.long.word 0x0 22.--31. 1. " USB_PWRCTL_CLK_FREQ ,Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." group.byte 0x374++0x3 line.long 0x0 "CTRL_CORE_PHY_POWER_SATA,phy_power_sata" hexmask.long.word 0x0 0.--13. 1. " RESERVED ,Reserved" hexmask.long.byte 0x0 14.--21. 1. " SATA_PWRCTL_CLK_CMD ,Powers up/down the SATA_PHY_TX and SATA_PHY_RX modules. 0x0: Powers down SATA_PHY_TX and SATA_PHY_RX 0x1: Powers up SATA_PHY_RX 0x2: Powers up SATA_PHY_TX 0x3: Powers up SATA_PHY_TX and SATA_PHY_RX 0x4-0xFF: Reserved" textline " " hexmask.long.word 0x0 22.--31. 1. " SATA_PWRCTL_CLK_FREQ ,Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." group.byte 0x380++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_MASK_1,bgap_mask" bitfld.long 0x0 0. " MASK_COLD_MPU ,Mask for cold event MPU 0x0 = cold event is masked 0x1 = cold event is not masked" "0,1" bitfld.long 0x0 1. " MASK_HOT_MPU ,Mask for hot event MPU 0x0 = hot event is masked 0x1 = hot event is not masked" "0,1" textline " " bitfld.long 0x0 2. " MASK_COLD_GPU ,Mask for cold event GPU 0x0 = cold event is masked 0x1 = cold event is not masked" "0,1" bitfld.long 0x0 3. " MASK_HOT_GPU ,Mask for hot event GPU 0x0 = hot event is masked 0x1 = hot event is not masked" "0,1" textline " " bitfld.long 0x0 4. " MASK_COLD_CORE ,Mask for cold event CORE 0x0 = cold event is masked 0x1 = cold event is not masked" "0,1" bitfld.long 0x0 5. " MASK_HOT_CORE ,Mask for hot event CORE 0x0 = hot event is masked 0x1 = hot event is not masked" "0,1" textline " " hexmask.long.word 0x0 6.--17. 1. " RESERVED ," bitfld.long 0x0 18. " CLEAR_MPU ,Reset the FIFO MPU 0x0 = No operation 0x1 = Reset the FIFO" "0,1" textline " " bitfld.long 0x0 19. " CLEAR_GPU ,Reset the FIFO GPU 0x0 = No operation 0x1 = Reset the FIFO" "0,1" bitfld.long 0x0 20. " CLEAR_CORE ,Reset the FIFO CORE 0x0 = No operation 0x1 = Reset the FIFO" "0,1" textline " " bitfld.long 0x0 21. " FREEZE_MPU ,Freeze the FIFO MPU 0x0 = No operation 0x1 = Freeze the FIFO" "0,1" bitfld.long 0x0 22. " FREEZE_GPU ,Freeze the FIFO GPU 0x0 = No operation 0x1 = Freeze the FIFO" "0,1" textline " " bitfld.long 0x0 23. " FREEZE_CORE ,Freeze the FIFO CORE 0x0 = No operation 0x1 = Freeze the FIFO" "0,1" bitfld.long 0x0 24.--26. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--29. " COUNTER_DELAY ,Counter delay 0x0 = Imediat 0x1 = Delay of 1ms 0x2 = Delay of 10ms 0x3 = Delay of 100ms 0x4 = Delay of 250ms 0x5 = Delay of 500ms" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SIDLEMODE ,sidlemode for bandgap 0x0 = No Idle 0x1 = Force Idle 0x2 = Smart Idle 0x3 = Reserved" "0,1,2,3" group.byte 0x384++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_THRESHOLD_MPU,BGAP THRESHOLD MPU" hexmask.long.word 0x0 0.--9. 1. " THOLD_COLD_MPU ,Value for the low temperature threshold. The values for loading this bit field are listed in." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " THOLD_HOT_MPU ,Value for the high temperature threshold. The values for loading this bit field are listed in." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x388++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_THRESHOLD_GPU,BGAP THRESHOLD MM" hexmask.long.word 0x0 0.--9. 1. " THOLD_COLD_GPU ,Value for the low temperature threshold. The values for loading this bit field are listed in." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " THOLD_HOT_GPU ,Value for the high temperature threshold. The values for loading this bit field are listed in." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x38C++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_THRESHOLD_CORE,BGAP THRESHOLD CORE" hexmask.long.word 0x0 0.--9. 1. " THOLD_COLD_CORE ,Value for the low temperature threshold. The values for loading this bit field are listed in." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " THOLD_HOT_CORE ,Value for the high temperature threshold. The values for loading this bit field are listed in." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x390++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_TSHUT_MPU,BGAP TSHUT THRESHOLD MPU" hexmask.long.word 0x0 0.--9. 1. " TSHUT_COLD_MPU ,tshut value cold Software should not modify this bit field." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " TSHUT_HOT_MPU ,tshut value hot Software should not modify this bit field." bitfld.long 0x0 26.--30. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 31. " RESERVED ,Software should not modify this bit." "0,1" group.byte 0x394++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_TSHUT_GPU,BGAP TSHUT THRESHOLD GPU" hexmask.long.word 0x0 0.--9. 1. " TSHUT_COLD_GPU ,tshut value cold Software should not modify this bit field." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " TSHUT_HOT_GPU ,tshut value hot Software should not modify this bit field." bitfld.long 0x0 26.--30. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 31. " RESERVED ,Software should not modify this bit." "0,1" group.byte 0x398++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_TSHUT_CORE,BGAP TSHUT THRESHOLD CORE" hexmask.long.word 0x0 0.--9. 1. " TSHUT_COLD_CORE ,tshut value cold Software should not modify this bit field." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " TSHUT_HOT_CORE ,tshut value hot Software should not modify this bit field." bitfld.long 0x0 26.--30. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 31. " RESERVED ,Software should not modify this bit." "0,1" group.byte 0x3A8++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_STATUS_1,BGAP STATUS" bitfld.long 0x0 0. " COLD_MPU ,Event for cold temperature core bandgap when '1' 0x0 = event not detected 0x1 = event detected" "0,1" bitfld.long 0x0 1. " HOT_MPU ,Event for hot temperature core bandgap when '1' 0x0 = event not detected 0x1 = event detected" "0,1" textline " " bitfld.long 0x0 2. " COLD_GPU ,Event for cold temperature gpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" "0,1" bitfld.long 0x0 3. " HOT_GPU ,Event for hot temperature gpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" "0,1" textline " " bitfld.long 0x0 4. " COLD_CORE ,Event for cold temperature mpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" "0,1" bitfld.long 0x0 5. " HOT_CORE ,Event for hot temperature mpu bandgap when '1' 0x0 = event not detected 0x1 = event detected" "0,1" textline " " hexmask.long 0x0 6.--30. 1. " RESERVED ," bitfld.long 0x0 31. " ALERT ,Alert temperature when '1'" "0,1" group.byte 0x3AC++0x3 line.long 0x0 "CTRL_CORE_SATA_EXT_MODE,SATA EXTENDED MODE" bitfld.long 0x0 0. " SATA_EXTENDED_MODE ,sata extended mode 0x0 = no extended mode 0x1 = extended mode" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x3C0++0x3 line.long 0x0 "CTRL_CORE_DTEMP_MPU_0,TAGGED TEMPERATURE MPU DOMAIN. Most recent sample" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_MPU_0 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_MPU_0 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3C4++0x3 line.long 0x0 "CTRL_CORE_DTEMP_MPU_1,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_MPU_1 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_MPU_1 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3C8++0x3 line.long 0x0 "CTRL_CORE_DTEMP_MPU_2,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_MPU_2 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_MPU_2 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3CC++0x3 line.long 0x0 "CTRL_CORE_DTEMP_MPU_3,TAGGED TEMPERATURE MPU DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_MPU_3 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_MPU_3 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3D0++0x3 line.long 0x0 "CTRL_CORE_DTEMP_MPU_4,TAGGED TEMPERATURE MPU DOMAIN. Oldest sample" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_MPU_4 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_MPU_4 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3D4++0x3 line.long 0x0 "CTRL_CORE_DTEMP_GPU_0,TAGGED TEMPERATURE GPU DOMAIN. Most recent sample." hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_GPU_0 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_GPU_0 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3D8++0x3 line.long 0x0 "CTRL_CORE_DTEMP_GPU_1,TAGGED TEMPERATURE GPU DOMAIN." hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_GPU_1 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_GPU_1 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3DC++0x3 line.long 0x0 "CTRL_CORE_DTEMP_GPU_2,TAGGED TEMPERATURE GPU DOMAIN." hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_GPU_2 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_GPU_2 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3E0++0x3 line.long 0x0 "CTRL_CORE_DTEMP_GPU_3,TAGGED TEMPERATURE GPU DOMAIN." hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_GPU_3 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_GPU_3 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3E4++0x3 line.long 0x0 "CTRL_CORE_DTEMP_GPU_4,TAGGED TEMPERATURE GPU DOMAIN. Oldest sample." hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_GPU_4 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_GPU_4 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3E8++0x3 line.long 0x0 "CTRL_CORE_DTEMP_CORE_0,TAGGED TEMPERATURE CORE DOMAIN. Most recent sample." hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_CORE_0 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_CORE_0 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3EC++0x3 line.long 0x0 "CTRL_CORE_DTEMP_CORE_1,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_CORE_1 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_CORE_1 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3F0++0x3 line.long 0x0 "CTRL_CORE_DTEMP_CORE_2,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_CORE_2 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_CORE_2 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3F4++0x3 line.long 0x0 "CTRL_CORE_DTEMP_CORE_3,TAGGED TEMPERATURE CORE DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_CORE_3 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_CORE_3 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3F8++0x3 line.long 0x0 "CTRL_CORE_DTEMP_CORE_4,TAGGED TEMPERATURE CORE DOMAIN. Oldest sample." hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_CORE_4 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_CORE_4 ,tag. Indicate number of times in the bgap state machine." group.byte 0x3FC++0x3 line.long 0x0 "CTRL_CORE_SMA_SW_0,OCP Spare Register" bitfld.long 0x0 0. " EMIF1_CKE_GATING_CTRL ,Forces the EMIF1 CKE pad to tri-state. 0x0: The CKE pad is not in tri-state and can be controlled by EMIF1 0x1: The CKE pad is in tri-state" "0,1" bitfld.long 0x0 1. " EMIF2_CKE_GATING_CTRL ,Forces the EMIF2 CKE pad to tri-state. 0x0: The CKE pad is not in tri-state and can be controlled by EMIF2 0x1: The CKE pad is in tri-state" "0,1" textline " " bitfld.long 0x0 2. " ISOLATE ,This bit is used during the isolation/de-isolation sequence described in, Isolation Requirements." "0,1" hexmask.long.word 0x0 3.--17. 1. " RESERVED ," textline " " bitfld.long 0x0 18. " SATA_PLL_SOFT_RESET ,Software reset control for SATA PLL" "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x414++0x3 line.long 0x0 "CTRL_CORE_SEC_ERR_STATUS_FUNC_2,Firewall Error Status functional Register 2" bitfld.long 0x0 0. " DSP1_FW_ERROR ,DSP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 1. " DSP2_FW_ERROR ,DSP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 2. " L3RAM2_FW_ERROR ,L3RAM2 target firewall. 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 3. " L3RAM3_FW_ERROR ,L3RAM3 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 4. " L4_PERIPH2_FW_ERROR ,L4 periph2 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 5. " L4_PERIPH3_FW_ERROR ,L4 periph3 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 6. " IPU2_FW_ERROR ,IPU2 firewall. 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 7. " PCIESS1_FW_ERROR ,PCIeSS1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 8. " PCIESS2_FW_ERROR ,PCIeSS2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 9. " VCP1_FW_ERROR ,VCP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 10. " VCP2_FW_ERROR ,VCP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 11. " MCASP1_FW_ERROR ,McASP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 12. " MCASP2_FW_ERROR ,McASP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 13. " MCASP3_FW_ERROR ,McASP3 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" bitfld.long 0x0 16. " TC0_EDMA_FW_ERROR ,EDMA TC0 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 17. " TPCC_EDMA_FW_ERROR ,EDMA TPCC firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 20. " PRUSS1_FW_ERROR ,PRU-ICSS1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 21. " PRUSS2_FW_ERROR ,PRU-ICSS2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 22. " QSPI_FW_ERROR ,QSPI firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 23.--25. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 26. " TC1_EDMA_FW_ERROR ,EDMA TC1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x41C++0x3 line.long 0x0 "CTRL_CORE_SEC_ERR_STATUS_DEBUG_2,Firewall Error Status debug Register 2" bitfld.long 0x0 0. " DSP1_DBGFW_ERROR ,DSP1 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 1. " DSP2_DBGFW_ERROR ,DSP2 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 2. " L3RAM2_DBGFW_ERROR ,L3RAM2 target debug firewall. 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 3. " L3RAM3_DBGFW_ERROR ,L3RAM3 firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 4. " L4_PERIPH2_DBGFW_ERROR ,L4 periph2 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 5. " L4_PERIPH3_DBGFW_ERROR ,L4 periph3 init firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 6. " IPU2_DBGFW_ERROR ,IPU2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 7. " PCIESS1_DBGFW_ERROR ,PCIeSS1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 8. " PCIESS2_DBGFW_ERROR ,PCIeSS2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 9. " VCP1_DBGFW_ERROR ,VCP1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 10. " VCP2_DBGFW_ERROR ,VCP2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 11. " MCASP1_DBGFW_ERROR ,McASP1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 12. " MCASP2_DBGFW_ERROR ,McASP2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 13. " MCASP3_DBGFW_ERROR ,McASP3 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" bitfld.long 0x0 16. " TC0_EDMA_DBGFW_ERROR ,EDMA TC0 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 17. " TPCC_EDMA_DBGFW_ERROR ,EDMA TPCC debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 20. " PRUSS1_DBGFW_ERROR ,PRU-ICSS1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 21. " PRUSS2_DBGFW_ERROR ,PRU-ICSS2 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" textline " " bitfld.long 0x0 22. " QSPI_DBGFW_ERROR ,QSPI debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 23.--25. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 26. " TC1_EDMA_DBGFW_ERROR ,EDMA TC1 debug firewall 0x0 = No error from firewall 0x1 = Error from firewall" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x420++0x3 line.long 0x0 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_1,Register for priority settings for EMIF arbitration" bitfld.long 0x0 0.--2. " DSP2_CFG_EMIF_PRIORITY ,DSP2 CFG priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " DSP2_EDMA_EMIF_PRIORITY ,DSP2 EDMA priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " DSP1_EDMA_EMIF_PRIORITY ,DSP1 EDMA priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " DSP1_CFG_EMIF_PRIORITY ,DSP1 CFG priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " DSP1_MDMA_EMIF_PRIORITY ,DSP1 MDMA priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28.--30. " MPU_EMIF_PRIORITY ,MPU priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x424++0x3 line.long 0x0 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_2,Register for priority settings for EMIF arbitration" bitfld.long 0x0 0.--2. " PRUSS1_PRU0_EMIF_PRIORITY ,PRU-ICSS1 PRU0 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " EVE4_TC0_EMIF_PRIORITY ,EVE4 TC0 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " EVE3_TC0_EMIF_PRIORITY ,EVE3 TC0 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " EVE2_TC0_EMIF_PRIORITY ,EVE2 TC0 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " EVE1_TC0_EMIF_PRIORITY ,EVE1 TC0 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 24.--26. " IVA_ICONT1_EMIF_PRIORITY ,IVA ICONT1 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " DSP2_MDMA_EMIF_PRIORITY ,DSP2 MDMA priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x428++0x3 line.long 0x0 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_3,Register for priority settings for EMIF arbitration" bitfld.long 0x0 0.--2. " EDMA_TC0_EMIF_PRIORITY ,EDMA TC0 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 8.--10. " DMA_SYSTEM_EMIF_PRIORITY ,DMA SYSTEM priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " IPU2_EMIF_PRIORITY ,IPU2 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " IPU1_EMIF_PRIORITY ,IPU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRUSS2_PRU1_EMIF_PRIORITY ,PRU-ICSS2 PRU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRUSS2_PRU0_EMIF_PRIORITY ,PRU-ICSS2 PRU0 priority setting 0x0 = highest prioroty 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRUSS1_PRU1_EMIF_PRIORITY ,PRU-ICSS1 PRU1 priority setting 0x0 = highest prioroty 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x42C++0x3 line.long 0x0 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_4,Register for priority settings for EMIF arbitration" bitfld.long 0x0 0.--2. " VIP3_P1_P2_EMIF_PRIORITY ,VIP3 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " VIP2_P1_P2_EMIF_PRIORITY ,VIP2 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " VIP1_P1_P2_EMIF_PRIORITY ,VIP1 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PCIESS2_EMIF_PRIORITY ,PCIeSS2 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PCIESS1_EMIF_PRIORITY ,PCIeSS1 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " MLB_MMU1_EMIF_PRIORITY ,MLB, MMU1 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " DSS_EMIF_PRIORITY ,DSS priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " EDMA_TC1_EMIF_PRIORITY ,EDMA TC1 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x430++0x3 line.long 0x0 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_5,Register for priority settings for EMIF arbitration" bitfld.long 0x0 0.--2. " USB3_EMIF_PRIORITY ,USB3 priority setting 0x0 = highest priority 0x7 = lowest priorty" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " USB2_EMIF_PRIORITY ,USB2 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " USB1_EMIF_PRIORITY ,USB1 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " GMAC_SW_EMIF_PRIORITY ,GMAC_SW priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " BB2D_P1_P2_EMIF_PRIORITY ,BB2D priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " MMC2_GPU_P2_EMIF_PRIORITY ,MMC2, GPU P2 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " MMC1_GPU_P1_EMIF_PRIORITY ,MMC1, GPU P1 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " VPE_P1_P2_EMIF_PRIORITY ,VPE priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x434++0x3 line.long 0x0 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_6,Register for priority settings for EMIF arbitration" bitfld.long 0x0 0.--2. " EVE3_TC1_EMIF_PRIORITY ,EVE3 TC1 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " EVE2_TC1_EMIF_PRIORITY ,EVE2 TC1 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " EVE1_TC1_EMIF_PRIORITY ,EVE1 TC1 priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " SATA_EMIF_PRIORITY ,SATA priority setting 0x0 = highest priority 0x7 = lowest priority" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 15.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28.--30. " USB4_EMIF_PRIORITY ,USB4 priority setting 0x0 = highest priority 0x7 = lowest prority" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x438++0x3 line.long 0x0 "CTRL_CORE_EMIF_INITIATOR_PRIORITY_7,Register for priority settings for EMIF arbitration" hexmask.long 0x0 0.--27. 1. " RESERVED ," bitfld.long 0x0 28.--30. " EVE4_TC1_EMIF_PRIORITY ,EVE4 TC1 priority setting0x0 = highest priority enum=HIGHESTPRIORITY . 0x7 = lowest priority enum=LOWESTPRIORITY ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x43C++0x3 line.long 0x0 "CTRL_CORE_L3_INITIATOR_PRESSURE_1,Register for pressure settings for L3 arbitration" hexmask.long.word 0x0 0.--8. 1. " RESERVED ," bitfld.long 0x0 9.--10. " DSP2_CFG_L3_PRESSURE ,DSP2 CFG pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" textline " " bitfld.long 0x0 11.--16. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 17.--18. " DSP1_CFG_L3_PRESSURE ,DSP1 CFG pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" textline " " hexmask.long.byte 0x0 19.--25. 1. " RESERVED ," bitfld.long 0x0 26.--27. " MPU_L3_PRESSURE ,MPU pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x440++0x3 line.long 0x0 "CTRL_CORE_L3_INITIATOR_PRESSURE_2,Register for pressure settings for L3 arbitration" bitfld.long 0x0 0.--1. " PRUSS2_PRU0_L3_PRESSURE ,PRU-ICSS2 PRU0 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3.--4. " PRUSS1_PRU1_L3_PRESSURE ,PRU-ICSS1 PRU1 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6.--7. " PRUSS1_PRU0_L3_PRESSURE ,PRU-ICSS1 PRU0 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" bitfld.long 0x0 8. " RESERVED ," "0,1" textline " " bitfld.long 0x0 9.--10. " IPU2_L3_PRESSURE ,IPU2 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--13. " IPU1_L3_PRESSURE ,IPU1 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x444++0x3 line.long 0x0 "CTRL_CORE_L3_INITIATOR_PRESSURE_3,Register for pressure settings for L3 arbitration" hexmask.long 0x0 0.--25. 1. " RESERVED ," bitfld.long 0x0 26.--27. " PRUSS2_PRU1_L3_PRESSURE ,PRU-ICSS2 PRU1 pressure setting0x0 = lowest enum=LOWEST . 0x3 = highest enum=HIGHEST ." "0,1,2,3" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x448++0x3 line.long 0x0 "CTRL_CORE_L3_INITIATOR_PRESSURE_4,Register for pressure settings for L3 arbitration" hexmask.long.tbyte 0x0 0.--19. 1. " RESERVED ," bitfld.long 0x0 20.--21. " GPU_P2_L3_PRESSURE ,GPU P2 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" textline " " bitfld.long 0x0 22. " RESERVED ," "0,1" bitfld.long 0x0 23.--24. " GPU_P1_L3_PRESSURE ,GPU P1 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x44C++0x3 line.long 0x0 "CTRL_CORE_L3_INITIATOR_PRESSURE_5,Register for pressure settings for L3 arbitration" bitfld.long 0x0 0.--1. " MMC1_L3_PRESSURE ,MMC1 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3.--4. " SATA_L3_PRESSURE ,SATA pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x450++0x3 line.long 0x0 "CTRL_CORE_L3_INITIATOR_PRESSURE_6,Register for pressure settings for L3 arbitration" bitfld.long 0x0 0.--5. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " USB4_L3_PRESSURE ,USB4 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9.--10. " USB3_L3_PRESSURE ,USB3 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " USB2_L3_PRESSURE ,USB2 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" textline " " bitfld.long 0x0 14. " RESERVED ," "0,1" bitfld.long 0x0 15.--16. " USB1_L3_PRESSURE ,USB1 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" textline " " bitfld.long 0x0 17.--18. " MMC2_L3_PRESSURE ,MMC2 pressure setting 0x0 = lowest 0x3 = highest" "0,1,2,3" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x458++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_0,Standard Fuse OPP VDD_iva [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_IVA_0 ," group.byte 0x45C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_1,Standard Fuse OPP VDD_iva [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_IVA_1 ," group.byte 0x460++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_2,Standard Fuse OPP VDD_iva [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_IVA_2 ," group.byte 0x464++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_3,Standard Fuse OPP VDD_iva [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_IVA_3 ," group.byte 0x468++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_4,Standard Fuse OPP VDD_iva [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_IVA_4 ," group.byte 0x46C++0x3 line.long 0x0 "CTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL,DSPEVE Voltage Body Bias LDO Control register" bitfld.long 0x0 0.--4. " LDOVBBDSPEVE_FBB_VSET_OUT ,Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_x[24:20] VSETABB bit fields. This value applies if LDOVBBDSPEVE_FBB_MUX_CTRL is set to 0x1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOVBBDSPEVE_FBB_VSET_IN ,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOVBBDSPEVE_FBB_MUX_CTRL ,Override control of EFUSE Forward Body Bias voltage value 0x0 = efuse value is used 0x1 = override value is used" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x470++0x3 line.long 0x0 "CTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL,IVA Voltage Body Bias LDO Control register" bitfld.long 0x0 0.--4. " LDOVBBIVA_FBB_VSET_OUT ,Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_x[24:20] VSETABB bit fields. This value applies if LDOVBBIVA_FBB_MUX_CTRL is set to 0x1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOVBBIVA_FBB_VSET_IN ,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOVBBIVA_FBB_MUX_CTRL ,Override control of EFUSE Forward Body Bias voltage value 0x0 = efuse value is used 0x1 = override value is used" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x4E8++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_UID_0,Customer Fuse keys. UID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_UID_0 ," group.byte 0x4EC++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_UID_1,Customer Fuse keys. UID [063:032] (16 bits upper Redundant field) [FIELD F]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_UID_1 ," group.byte 0x4F0++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_UID_2,Customer Fuse keys. UID [095:064] (16 bits upper Redundant field) [FIELD E]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_UID_2 ," group.byte 0x4F4++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_UID_3,Customer Fuse keys. UID [127:096] (16 bits upper Redundant field) [FIELD D]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_UID_3 ," group.byte 0x4F8++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_UID_4,Customer Fuse keys. UID [159:127] (16 bits upper Redundant field) [FIELD C]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_UID_4 ," group.byte 0x4FC++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_UID_5,Customer Fuse keys. UID [191:160] (16 bits upper Redundant field) [FIELD B]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_UID_5 ," group.byte 0x500++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_UID_6,Customer Fuse keys. UID [223:192] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_UID_6 ," group.byte 0x508++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_PCIE_ID_0,Customer Fuse keys. PCIe ID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_PCIE_ID_0 ," group.byte 0x510++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_USB_ID_0,Customer Fuse keys. USB ID [031:000] (16 bits upper Redundant field) [FIELD OVERFLOW]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_USB_ID_0 ," group.byte 0x514++0x3 line.long 0x0 "CTRL_CORE_MAC_ID_SW_0,Standard Fuse keys, MAC ID_1 [63:32]." hexmask.long 0x0 0.--24. 1. " STD_FUSE_MAC_ID_SW_0 ,This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 0. Bits [23:16] contain the 4th octet of the MAC address. Bits [15:8] contain the 5th octet of the MAC address. Bits [7:0] contain the last (6th) octet of the MAC address." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x518++0x3 line.long 0x0 "CTRL_CORE_MAC_ID_SW_1,Standard Fuse keys, MAC ID_1 [31:0]." hexmask.long 0x0 0.--24. 1. " STD_FUSE_MAC_ID_SW_1 ,This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 0. Bits [23:16] contain the first octet of the MAC address. Bits [15:8] contain the second octet of the MAC address. Bits [7:0] contain the third octet of the MAC address." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x51C++0x3 line.long 0x0 "CTRL_CORE_MAC_ID_SW_2,Standard Fuse keys, MAC ID_2 [63:32]." hexmask.long 0x0 0.--24. 1. " STD_FUSE_MAC_ID_SW_2 ,This bit field contains the last three octets (NIC specific) of the MAC address of the GMAC_SW port 1. Bits [23:16] contain the 4th octet of the MAC address. Bits [15:8] contain the 5th octet of the MAC address. Bits [7:0] contain the last (6th) octet of the MAC address." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x520++0x3 line.long 0x0 "CTRL_CORE_MAC_ID_SW_3,Standard Fuse keys, MAC ID_2 [31:0]." hexmask.long 0x0 0.--24. 1. " STD_FUSE_MAC_ID_SW_3 ,This bit field contains the first three octets (the OUI) of the MAC address of the GMAC_SW port 1. Bits [23:16] contain the first octet of the MAC address. Bits [15:8] contain the second octet of the MAC address. Bits [7:0] contain the third octet of the MAC address." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x534++0x3 line.long 0x0 "CTRL_CORE_SMA_SW_1,OCP Spare Register" bitfld.long 0x0 0. " VIP1_CLK_INV_PORT_1A ,VIP1 Slice 0 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" "0,1" bitfld.long 0x0 1. " VIP1_CLK_INV_PORT_2A ,VIP1 Slice 1 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" "0,1" textline " " bitfld.long 0x0 2. " VIP1_CLK_INV_PORT_1B ,VIP1 Slice 0 Clock inversion for Port B enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" "0,1" bitfld.long 0x0 3. " VIP1_CLK_INV_PORT_2B ,VIP1 Slice 1 Clock inversion for Port B enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" "0,1" textline " " bitfld.long 0x0 4. " VIP2_CLK_INV_PORT_1A ,VIP2 Slice 0 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" "0,1" bitfld.long 0x0 5. " VIP2_CLK_INV_PORT_2A ,VIP2 Slice 1 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" "0,1" textline " " bitfld.long 0x0 6. " VIP2_CLK_INV_PORT_1B ,VIP2 Slice 0 Clock inversion for Port B enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" "0,1" bitfld.long 0x0 7. " VIP2_CLK_INV_PORT_2B ,VIP2 Slice 1 Clock inversion for Port B enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" "0,1" textline " " bitfld.long 0x0 8. " VPE_CLK_DIV_BY_2_EN ,Selects alternative clock source for VPE. 0x0: Default clock source from DPLL_CORE is selected 0x1: Alternative clock source from DPLL_VIDEO1 is selected" "0,1" bitfld.long 0x0 9. " VIP3_CLK_INV_PORT_2A ,VIP3 Slice 0 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" "0,1" textline " " bitfld.long 0x0 10. " VIP3_CLK_INV_PORT_1A ,VIP3 Slice 1 Clock inversion for Port A enable 0x0: clock inversion is disabled 0x1: clock inversion is enabled" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16. " DSS_CH0_RF ,DSS Channel 0 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH0_ON_OFF set to 1)" "0,1" bitfld.long 0x0 17. " DSS_CH1_RF ,DSS Channel 1 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH1_ON_OFF set to 1)" "0,1" textline " " bitfld.long 0x0 18. " DSS_CH2_RF ,DSS Channel 2 Rise/Fall control 0x0: HSYNC and VSYNC are driven on falling edge of pixel clock (if bit DSS_CH2_ON_OFF set to 1) 0x1: HSYNC and VSYNC are driven on rising edge of pixel clock (if bit DSS_CH2_ON_OFF set to 1)" "0,1" bitfld.long 0x0 19. " DSS_CH0_IPC ,DSS Channel 0 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" "0,1" textline " " bitfld.long 0x0 20. " DSS_CH1_IPC ,DSS Channel 1 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" "0,1" bitfld.long 0x0 21. " DSS_CH2_IPC ,DSS Channel 2 IPC control 0x0: Data is driven on the LCD data lines on the rising edge of the pixel clock 0x1: Data is driven on the LCD data lines on the falling edge of the pixel clock" "0,1" textline " " bitfld.long 0x0 22. " DSS_CH0_ON_OFF ,DSS Channel 0 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH0_RF" "0,1" bitfld.long 0x0 23. " DSS_CH1_ON_OFF ,DSS Channel 1 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH1_RF" "0,1" textline " " bitfld.long 0x0 24. " DSS_CH2_ON_OFF ,DSS Channel 2 Pixel clock control On/Off 0x0: HSYNC and VSYNC are driven on opposite edges of pixel clock than pixel data 0x1: HSYNC and VSYNC are driven according to bit DSS_CH2_RF" "0,1" bitfld.long 0x0 25. " RGMII1_ID_MODE_N ,Ethernet RGMII port 1 internal delay on transmit(SR2.0) 0x0: Internal delay enabled 0x1: Internal delay disabled" "0,1" textline " " bitfld.long 0x0 26. " RGMII2_ID_MODE_N ,Ethernet RGMII port 2 internal delay on transmit(SR2.0) 0x0: Internal delay enabled 0x1: Internal delay disabled" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x538++0x3 line.long 0x0 "CTRL_CORE_DSS_PLL_CONTROL,DSS PLLs Mux control register" bitfld.long 0x0 0. " PLL_VIDEO1_DSS_CONTROL_DISABLE ,VIDEO1 PLL disable 0x0: PLL enabled 0x1: PLL disabled" "0,1" bitfld.long 0x0 1. " PLL_VIDEO2_DSS_CONTROL_DISABLE ,VIDEO2 PLL disable 0x0: PLL enabled 0x1: PLL disabled" "0,1" textline " " bitfld.long 0x0 2. " PLL_HDMI_DSS_CONTROL_DISABLE ,HDMI PLL disable 0x0: PLL enabled 0x1: PLL disabled" "0,1" bitfld.long 0x0 3.--4. " DSI1_A_CLK1_SELECTION ,DSI1_A_CLK1 mux configuration 0x0: DPLL_VIDEO1 0x1: DPLL_HDMI" "0,1,2,3" textline " " bitfld.long 0x0 5.--6. " DSI1_B_CLK1_SELECTION ,DSI1_B_CLK1 mux configuration 0x0: DPLL_VIDEO1 0x1: DPLL_VIDEO2 0x2: DPLL_HDMI 0x3: DPLL_ABE" "0,1,2,3" bitfld.long 0x0 7.--8. " DSI1_C_CLK1_SELECTION ,DSI1_C_CLK1 mux configuration 0x0: DPLL_VIDEO2 0x1: DPLL_VIDEO1 0x2: DPLL_HDMI" "0,1,2,3" textline " " bitfld.long 0x0 9.--10. " SDVENC_CLK_SELECTION ,SDVENC_CLK mux configuration 0x0: HDMI_CLK 0x1: DPLL_VIDEO1_HSDIVIDER_clkout3" "0,1,2,3" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Reserved" group.byte 0x540++0x3 line.long 0x0 "CTRL_CORE_MMR_LOCK_1,Register to lock memory region starting at address offset 0x0000 0100 and ending at address offset 0x0000 079F" hexmask.long 0x0 0.--31. 1. " MMR_LOCK_1 ,Lock value for region 0x0000 0100 to 0x0000 079F 0x1A1C8144 = lock value 0x2FF1AC2B = unlock value" group.byte 0x544++0x3 line.long 0x0 "CTRL_CORE_MMR_LOCK_2,Register to lock memory region starting at address offset 0x0000 07A0 and ending at address offset 0x0000 0D9F" hexmask.long 0x0 0.--31. 1. " MMR_LOCK_2 ,Lock value for region 0x0000 07A0 to 0x0000 0D9F 0xFDF45530 = lock value 0xF757FDC0 = unlock value" group.byte 0x548++0x3 line.long 0x0 "CTRL_CORE_MMR_LOCK_3,Register to lock memory region starting at address offset 0x0000 0DA0 and ending at address offset 0x0000 0FFF" hexmask.long 0x0 0.--31. 1. " MMR_LOCK_3 ,Lock value for region 0x0000 0DA0 to 0x0000 0FFF 0x1AE6E320 = lock value 0xE2BC3A6D = unlock value" group.byte 0x54C++0x3 line.long 0x0 "CTRL_CORE_MMR_LOCK_4,Register to lock memory region starting at address offset 0x0000 1000 and ending at address offset 0x0000 13FF" hexmask.long 0x0 0.--31. 1. " MMR_LOCK_4 ,Lock value for region 0x0000 1000 to 0x0000 13FF 0x2FFA927C = lock value 0x1EBF131D = unlock value" group.byte 0x550++0x3 line.long 0x0 "CTRL_CORE_MMR_LOCK_5,Register to lock memory region starting at address offset 0x0000 1400 and ending at address offset 0x0000 1FFF" hexmask.long 0x0 0.--31. 1. " MMR_LOCK_5 ,Lock value for region 0x0000 1400 to 0x0000 1FFF 0x143F832C = lock value 0x6F361E05 = unlock value" group.byte 0x554++0x3 line.long 0x0 "CTRL_CORE_CONTROL_IO_1,Register to configure some IP level signals" bitfld.long 0x0 0.--1. " GMII1_SEL ,GMII1 selection setting 0x0: GMII/MII 0x1: RMII 0x2: RGMII 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " GMII2_SEL ,GMII2 selection setting 0x0: GMII/MII 0x1: RMII 0x2: RGMII 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " TC0_DEFAULT_BURST_SIZE ,EDMA TC0 Default Burst Size (DBS) setting 0x0: 16 byte burst 0x1: 32 byte burst 0x2: 64 byte burst 0x3: 128 byte burst" "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " TC1_DEFAULT_BURST_SIZE ,EDMA TC1 Default Burst Size (DBS) setting 0x0: 16 byte burst 0x1: 32 byte burst 0x2: 64 byte burst 0x3: 128 byte burst" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16. " MMU1_DISABLE ,MMU1 DISABLE setting" "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " MMU2_DISABLE ,MMU2 DISABLE setting" "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x558++0x3 line.long 0x0 "CTRL_CORE_CONTROL_IO_2,Register to configure some IP level signals" bitfld.long 0x0 0. " DSS_DESHDCP_CLKEN ,DSS DESHDCP CLOCK ENABLE setting" "0,1" bitfld.long 0x0 1. " DCAN1_RAMINIT_DONE ,DCAN1 RAM INIT DONE status" "0,1" textline " " bitfld.long 0x0 2. " DCAN2_RAMINIT_DONE ,DCAN2 RAM INIT DONE status" "0,1" bitfld.long 0x0 3. " DCAN1_RAMINIT_START ,DCAN1 RAM INIT START setting To initialize DCAN1 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. Note: If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." "0,1" textline " " bitfld.long 0x0 4. " DSS_DESHDCP_DISABLE ,DSS DESHDCP DISABLE setting" "0,1" bitfld.long 0x0 5. " DCAN2_RAMINIT_START ,DCAN2 RAM INIT START setting To initialize DCAN2 RAM, the bit should be set to 0x1. It is not auto cleared by hardware. Note: If DCAN RAMINIT sequence needs to be redone, this bit should be first cleared and then set again." "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8.--10. " QSPI_MEMMAPPED_CS ,QSPI CS MAPPING setting. 0x0: The QSPI configuration registers are accessed 0x1: An external device connected to CS0 is accessed 0x2: An external device connected to CS1 is accessed 0x3: An external device connected to CS2 is accessed 0x4-0x7: An external device connected to CS3 is accessed" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13. " PCIE_1LANE_2LANE_SELECTION ,Reserved" "0,1" textline " " bitfld.long 0x0 14.--19. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 20. " PWMSS1_TBCLKEN ,PWMSS1 CLOCK ENABLE setting" "0,1" textline " " bitfld.long 0x0 21. " PWMSS2_TBCLKEN ,PWMSS2 CLOCK ENABLE setting" "0,1" bitfld.long 0x0 22. " PWMSS3_TBCLKEN ,PWMSS3 CLOCK ENABLE setting" "0,1" textline " " bitfld.long 0x0 23. " GMAC_RESET_ISOLATION_ENABLE ,Reset isolation enable setting 0x0 = Reset is not isolated 0x1 = Reset is isolated" "0,1" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x55C++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DSP1_RST_VECT,Register for storing DSP1 reset vector" hexmask.long.tbyte 0x0 0.--21. 1. " DSP1_RST_VECT ,DSP1 reset vector address" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24.--26. " DSP1_NUM_MM ,Number of DSP instances in the SoC 0x1 = 1 0x2 = 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x560++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DSP2_RST_VECT,Register for storing DSP2 reset vector" hexmask.long.tbyte 0x0 0.--21. 1. " DSP2_RST_VECT ,DSP2 reset vector address" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24.--26. " DSP2_NUM_MM ,Number of DSP instances in the SoC 0x1 = 1 0x2 = 2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x564++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_BGAP_DSPEVE,Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 0.--7. 1. " STD_FUSE_OPP_BGAP_DSPEVE_1 ,Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 8.--15. 1. " STD_FUSE_OPP_BGAP_DSPEVE_0 ,Trim values for DSPEVE associated bandgap. Contains TI Internal information, not intended for application use." textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x568++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_BGAP_IVA,Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 0.--7. 1. " STD_FUSE_OPP_BGAP_IVA_3 ,Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 8.--15. 1. " STD_FUSE_OPP_BGAP_IVA_2 ,Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." textline " " hexmask.long.byte 0x0 16.--23. 1. " STD_FUSE_OPP_BGAP_IVA_1 ,Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." hexmask.long.byte 0x0 24.--31. 1. " STD_FUSE_OPP_BGAP_IVA_0 ,Trim values for IVA associated temperature sensor and bandgap. Contains TI Internal information, not intended for application use." group.byte 0x56C++0x3 line.long 0x0 "CTRL_CORE_LDOSRAM_DSPEVE_VOLTAGE_CTRL,DSPEVE SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMDSPEVE_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMDSPEVE_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMDSPEVE_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMDSPEVE_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMDSPEVE_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMDSPEVE_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x570++0x3 line.long 0x0 "CTRL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL,IVA SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMIVA_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMIVA_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMIVA_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMIVA_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMIVA_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMIVA_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x574++0x3 line.long 0x0 "CTRL_CORE_TEMP_SENSOR_DSPEVE,Control VBGAPTS temperature sensor and thermal comparator shutdown register" hexmask.long.word 0x0 0.--9. 1. " BGAP_DTEMP_DSPEVE ,Temperature data from the ADC. Valid if EOCZ is low." bitfld.long 0x0 10. " BGAP_EOCZ_DSPEVE ,ADC End of Conversion. Active low, when BGAP_DTEMP_DSPEVE is valid." "0,1" textline " " bitfld.long 0x0 11. " BGAP_TMPSOFF_DSPEVE ,This bit indicates the temperature sensor state." "0,1" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x578++0x3 line.long 0x0 "CTRL_CORE_TEMP_SENSOR_IVA,Control VBGAPTS temperature sensor and thermal comparator shutdown register" hexmask.long.word 0x0 0.--9. 1. " BGAP_DTEMP_IVA ,Temperature data from the ADC. Valid if EOCZ is low." bitfld.long 0x0 10. " BGAP_EOCZ_IVA ,ADC End of Conversion. Active low, when BGAP_DTEMP_IVA is valid." "0,1" textline " " bitfld.long 0x0 11. " BGAP_TMPSOFF_IVA ,This bit indicates the temperature sensor state." "0,1" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x57C++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_MASK_2,bgap_mask" bitfld.long 0x0 0. " MASK_COLD_DSPEVE ,Mask for cold event DSPEVE 0x0 = cold event is masked 0x1 = cold event is not masked" "0,1" bitfld.long 0x0 1. " MASK_HOT_DSPEVE ,Mask for hot event DSPEVE 0x0 = hot event is masked 0x1 = hot event is not masked" "0,1" textline " " bitfld.long 0x0 2. " MASK_COLD_IVA ,Mask for cold event IVA 0x0 = cold event is masked 0x1 = cold event is not masked" "0,1" bitfld.long 0x0 3. " MASK_HOT_IVA ,Mask for hot event IVA 0x0 = hot event is masked 0x1 = hot event is not masked" "0,1" textline " " hexmask.long.word 0x0 4.--17. 1. " RESERVED ," bitfld.long 0x0 18. " CLEAR_DSPEVE ,Reset the FIFO DSPEVE 0x0 = No operation 0x1 = Reset the FIFO" "0,1" textline " " bitfld.long 0x0 19. " CLEAR_IVA ,Reset the FIFO IVA 0x0 = No operation 0x1 = Reset the FIFO" "0,1" bitfld.long 0x0 20. " RESERVED ," "0,1" textline " " bitfld.long 0x0 21. " FREEZE_DSPEVE ,Freeze the FIFO DSPEVE 0x0 = No operation 0x1 = Freeze the FIFO" "0,1" bitfld.long 0x0 22. " FREEZE_IVA ,Freeze the FIFO IVA 0x0 = No operation 0x1 = Freeze the FIFO" "0,1" textline " " hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x580++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_THRESHOLD_DSPEVE,BGAP THRESHOLD DSPEVE" hexmask.long.word 0x0 0.--9. 1. " THOLD_COLD_DSPEVE ,Value for the low temperature threshold. The values for loading this bit field are listed in." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " THOLD_HOT_DSPEVE ,Value for the high temperature threshold. The values for loading this bit field are listed in." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x584++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_THRESHOLD_IVA,BGAP THRESHOLD IVA" hexmask.long.word 0x0 0.--9. 1. " THOLD_COLD_IVA ,Value for the low temperature threshold. The values for loading this bit field are listed in." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " THOLD_HOT_IVA ,Value for the high temperature threshold. The values for loading this bit field are listed in." bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x588++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_TSHUT_DSPEVE,BGAP TSHUT THRESHOLD IVA" hexmask.long.word 0x0 0.--9. 1. " TSHUT_COLD_DSPEVE ,tshut value cold Software should not modify this bit field." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " TSHUT_HOT_DSPEVE ,tshut value hot Software should not modify this bit field." bitfld.long 0x0 26.--30. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 31. " RESERVED ,Software should not modify this bit." "0,1" group.byte 0x58C++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_TSHUT_IVA,BGAP TSHUT THRESHOLD IVA" hexmask.long.word 0x0 0.--9. 1. " TSHUT_COLD_IVA ,tshut value cold Software should not modify this bit field." bitfld.long 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 16.--25. 1. " TSHUT_HOT_IVA ,tshut value hot Software should not modify this bit field." bitfld.long 0x0 26.--30. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 31. " RESERVED ,Software should not modify this bit." "0,1" group.byte 0x598++0x3 line.long 0x0 "CTRL_CORE_BANDGAP_STATUS_2,BGAP STATUS" bitfld.long 0x0 0. " COLD_DSPEVE ,Event for cold temperature dspeve bandgap when '1' 0x0 = event not detected 0x1 = event detected" "0,1" bitfld.long 0x0 1. " HOT_DSPEVE ,Event for hot temperature dspeve bandgap when '1' 0x0 = event not detected 0x1 = event detected" "0,1" textline " " bitfld.long 0x0 2. " COLD_IVA ,Event for cold temperature iva bandgap when '1' 0x0 = event not detected 0x1 = event detected" "0,1" bitfld.long 0x0 3. " HOT_IVA ,Event for hot temperature iva bandgap when '1' 0x0 = event not detected 0x1 = event detected" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x59C++0x3 line.long 0x0 "CTRL_CORE_DTEMP_DSPEVE_0,TAGGED TEMPERATURE DSPEVE DOMAIN. Most recent sample" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_DSPEVE_0 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_DSPEVE_0 ,tag. Indicate number of times in the bgap state machine." group.byte 0x5A0++0x3 line.long 0x0 "CTRL_CORE_DTEMP_DSPEVE_1,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_DSPEVE_1 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_DSPEVE_1 ,tag. Indicate number of times in the bgap state machine." group.byte 0x5A4++0x3 line.long 0x0 "CTRL_CORE_DTEMP_DSPEVE_2,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_DSPEVE_2 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_DSPEVE_2 ,tag. Indicate number of times in the bgap state machine." group.byte 0x5A8++0x3 line.long 0x0 "CTRL_CORE_DTEMP_DSPEVE_3,TAGGED TEMPERATURE DSPEVE DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_DSPEVE_3 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_DSPEVE_3 ,tag. Indicate number of times in the bgap state machine." group.byte 0x5AC++0x3 line.long 0x0 "CTRL_CORE_DTEMP_DSPEVE_4,TAGGED TEMPERATURE DSPEVE DOMAIN. Oldest sample" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_DSPEVE_4 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_DSPEVE_4 ,tag. Indicate number of times in the bgap state machine." group.byte 0x5B0++0x3 line.long 0x0 "CTRL_CORE_DTEMP_IVA_0,TAGGED TEMPERATURE IVA DOMAIN. Most recent sample" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_IVA_0 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_IVA_0 ,tag. Indicate number of times in the bgap state machine." group.byte 0x5B4++0x3 line.long 0x0 "CTRL_CORE_DTEMP_IVA_1,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_IVA_1 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_IVA_1 ,tag. Indicate number of times in the bgap state machine." group.byte 0x5B8++0x3 line.long 0x0 "CTRL_CORE_DTEMP_IVA_2,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_IVA_2 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_IVA_2 ,tag. Indicate number of times in the bgap state machine." group.byte 0x5BC++0x3 line.long 0x0 "CTRL_CORE_DTEMP_IVA_3,TAGGED TEMPERATURE IVA DOMAIN" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_IVA_3 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_IVA_3 ,tag. Indicate number of times in the bgap state machine." group.byte 0x5C0++0x3 line.long 0x0 "CTRL_CORE_DTEMP_IVA_4,TAGGED TEMPERATURE IVA DOMAIN. Oldest sample" hexmask.long.word 0x0 0.--9. 1. " DTEMP_TEMPERATURE_IVA_4 ,temperature" hexmask.long.tbyte 0x0 10.--31. 1. " DTEMP_TAG_IVA_4 ,tag. Indicate number of times in the bgap state machine." group.byte 0x5CC++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_2,This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_IVA_2 ,AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x5D0++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_3,This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_IVA_3 ,AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x5D4++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_IVA_4,This register contains the AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_IVA_4 ,AVS Class 0 voltage value for the vdd_iva voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_CORE_LDOVBB_IVA_VOLTAGE_CTRL [4:0] LDOVBBIVA_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x5E0++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_2,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_DSPEVE_2 ,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x5E4++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_3,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_DSPEVE_3 ,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x5E8++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_DSPEVE_4,This register contains the AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_DSPEVE_4 ,AVS Class 0 voltage value for the vdd_dspeve voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_CORE_LDOVBB_DSPEVE_VOLTAGE_CTRL [4:0] LDOVBBDSPEVE_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x5F4++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_CORE_2,This register contains the AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_CORE_2 ,AVS Class 0 voltage value for the vdd voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reserved" group.byte 0x680++0x3 line.long 0x0 "CTRL_CORE_LDOSRAM_CORE_2_VOLTAGE_CTRL,CORE 2nd SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMCORE_2_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMCORE_2_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMCORE_2_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMCORE_2_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMCORE_2_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMCORE_2_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x684++0x3 line.long 0x0 "CTRL_CORE_LDOSRAM_CORE_3_VOLTAGE_CTRL,CORE 3rd SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMCORE_3_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMCORE_3_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMCORE_3_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMCORE_3_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMCORE_3_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMCORE_3_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x68C++0x3 line.long 0x0 "CTRL_CORE_NMI_DESTINATION_1,Register for routing NMI interrupt to respective cores" hexmask.long.byte 0x0 0.--7. 1. " IPU1_C1 ,Enable IPU1 CORE1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" hexmask.long.byte 0x0 8.--15. 1. " IPU2_C0 ,Enable IPU2 CORE0 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" textline " " hexmask.long.byte 0x0 16.--23. 1. " IPU2_C1 ,Enable IPU2 CORE1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reserved" group.byte 0x690++0x3 line.long 0x0 "CTRL_CORE_NMI_DESTINATION_2,Register for routing NMI interrupt to respective cores" hexmask.long.byte 0x0 0.--7. 1. " MPU ,Comes from Efuse (MPU_EN) 0x0 = NMI disabled 0x1 = NMI enabled" hexmask.long.byte 0x0 8.--15. 1. " DSP1 ,Enable DSP1 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" textline " " hexmask.long.byte 0x0 16.--23. 1. " DSP2 ,Enable DSP2 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" hexmask.long.byte 0x0 24.--31. 1. " IPU1_C0 ,Enable IPU1 CORE0 to receive the NMI interrupt 0x0 = NMI disabled 0x1 = NMI enabled" group.byte 0x698++0x3 line.long 0x0 "CTRL_CORE_IP_PRESSURE,Register to override the L3 pressure setting for the MLB module." bitfld.long 0x0 0.--1. " MLB_L3_PRESSURE ,MLB L3 pressure setting 0x0 = Lowest 0x3 = Highest" "0,1,2,3" bitfld.long 0x0 2. " MLB_L3_PRESSURE_ENABLE ,Override enable for the MLB L3 pressure setting 0x0 = Overriding of the L3 pressure setting for the MLB module is disabled 0x1 = Overriding of the L3 pressure setting for the MLB module is enabled" "0,1" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x6A0++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_0,Standard Fuse OPP VDD_DSPEVE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_DSPEVE_0 ," group.byte 0x6A4++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_1,Standard Fuse OPP VDD_DSPEVE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_DSPEVE_1 ," group.byte 0x6A8++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_2,Standard Fuse OPP VDD_DSPEVE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_DSPEVE_2 ," group.byte 0x6AC++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_3,Standard Fuse OPP VDD_DSPEVE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_DSPEVE_3 ," group.byte 0x6B0++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_4,Standard Fuse OPP VDD_DSPEVE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_DSPEVE_4 ," group.byte 0x6B4++0x3 line.long 0x0 "CTRL_CORE_CUST_FUSE_SWRV_7,Customer Fuse keys. SWRV [31:0] (16 bits upper Redundant field) [FIELD A]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " CUST_FUSE_SWRV_7 ," group.byte 0x6B8++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0,Standard Fuse Calibration override value [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_CALIBRATION_OVERRIDE_VALUE_0 ," group.byte 0x6BC++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1,Standard Fuse Calibration override value [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_CALIBRATION_OVERRIDE_VALUE_1 ," group.byte 0x6C0++0x3 line.long 0x0 "CTRL_CORE_PCIE_POWER_STATE,Register to PCIe related controls" hexmask.long.word 0x0 0.--15. 1. " EFUSE_TRIM_PCIE_PLL ,MMR override capability for PCIe PLL efuse trim bits" hexmask.long.word 0x0 16.--25. 1. " EFUSE_TRIM_ACS_PCIE ,MMR override capability for ACS_PCIe efuse trim bits" textline " " bitfld.long 0x0 26.--29. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 30. " CLKOOUTEN_APLL_PCIE ,Clock output enable bit setting for APLL_PCIe" "0,1" textline " " bitfld.long 0x0 31. " BYPASS_EN_APLL_PCIE ,Bypass enable bit setting for APLL_PCIe" "0,1" group.byte 0x6C4++0x3 line.long 0x0 "CTRL_CORE_BOOTSTRAP,Register to view all the sysboot settings" bitfld.long 0x0 0.--5. " BOOTMODE ,SYSBOOT mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " SYSBOOT_76 ,Sector offset for the location of the redundant SBL images in QSPI.0x0: 64 KB offset0x1: 128 KB offset0x2: 256 KB offset0x3: 512 KB offset" "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " SPEEDSELECT ,Indicates the SYS_CLK1 frequency (from osc0). Note that the internal FUNC_32K_CLK is equal to SYS_CLK1/610, which is nominally 32.7869 kHz with 20 MHz clock. 0x0: Reserved 0x1: 20 MHz 0x2: 27 MHz 0x3: 19.2 MHz" "0,1,2,3" bitfld.long 0x0 10. " BOOTWAITEN ,Enable the monitoring on CS0 of the wait pin at IC reset release time for read accesses. 0x0: Wait pin is not monitored for read accesses 0x1: Wait pin is monitored for read accesses" "0,1" textline " " bitfld.long 0x0 11.--12. " MUXCS0DEVICE ,Select IC boot sequence to be executed from a multiplexed address and data device attached to CS0. 0x0: Non-muxed device attached 0x1: Addr-Data Mux device attached 0x2: Reserved 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 13. " BOOTDEVICESIZE ,Select the size of the flash device on CS0. 0x0: 8-bit 0x1: 16-bit" "0,1" textline " " bitfld.long 0x0 14. " RESERVED ,For proper device operation, a value of 0 is required on sysboot14" "0,1" bitfld.long 0x0 15. " DSP_CLOCK_DIVIDER ,SR1.x Only:Divide factor for DSP clockSR2.0 Only:Permanently disables the internal PU/PD resistors on pads gpmc_a[27:24, 22:19].0x0: Internal pull-down resistors are enabled0x1: Internal pull-down resistors are permanently disabled" "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x6C8++0x3 line.long 0x0 "CTRL_CORE_MLB_SIG_IO_CTRL,Register to set the MLB's SIG IO characteristics" bitfld.long 0x0 0.--2. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " SIG_EN_EXT_RES ,disables internal resistors 0x0 = Disabled 0x1 = Enabled" "0,1" textline " " bitfld.long 0x0 4. " SIG_PWRDNTX ,powerdown transmitter, active high 0x0 = Powered ON 0x1 = Powered OFF" "0,1" bitfld.long 0x0 5. " SIG_PWRDNRX ,powerdown receiver, active high 0x0 = Powered ON 0x1 = Powered OFF" "0,1" textline " " bitfld.long 0x0 6. " SIG_REMOVE_SKEW ,Adjust for skew generated by the receiver due to asymmetric inputs. 0x0: skew compensation is disabled 0x1: skew compensation is enabled" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--13. " SIG_PC_IN ,efuse trim for Pmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--21. " SIG_NC_IN ,efuse trim for Nmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x6CC++0x3 line.long 0x0 "CTRL_CORE_MLB_DAT_IO_CTRL,Register to set the MLB's DAT IO characteristics" bitfld.long 0x0 0.--2. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " DAT_EN_EXT_RES ,Enable/disable internal resistors 0x0 = Disabled 0x1 = Enabled" "0,1" textline " " bitfld.long 0x0 4. " DAT_PWRDNTX ,powerdown transmitter, active high 0x0 = Powered ON 0x1 = Powered OFF" "0,1" bitfld.long 0x0 5. " DAT_PWRDNRX ,powerdown receiver, active high 0x0 = Powered ON 0x1 = Powered OFF" "0,1" textline " " bitfld.long 0x0 6. " DAT_REMOVE_SKEW ,Adjust for skew generated by the receiver due to asymmetric inputs. 0x0: skew compensation is disabled 0x1: skew compensation is enabled" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--13. " DAT_PC_IN ,efuse trim for Pmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--21. " DAT_NC_IN ,efuse trim for Nmos impedance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x6D0++0x3 line.long 0x0 "CTRL_CORE_MLB_CLK_BG_CTRL,Register to set the MLB's clock receiver IO and bandgap characteristics." bitfld.long 0x0 0. " CLK_PWRDN ,Enable the MLB differential clock receiver. 0x0 = MLB differential clock receiver is enabled 0x1 = MLB differential clock receiver is disabled" "0,1" bitfld.long 0x0 1. " BG_PWRDN ,MLB bandgap cell enable. 0x0 = The MLB bandgap cell is powered (enabled) 0x1 = The MLB bandgap cell is disabled" "0,1" textline " " bitfld.long 0x0 2.--7. " BG_TRIM ,Trim values for MLB bandgap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " T_HYSTERISIS_EN ,Hysterisis enable 0x0 = Disabled 0x1 = Enabled" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x7A0++0x3 line.long 0x0 "CTRL_CORE_EVE1_IRQ_0_1,CTRL_CORE_EVE1_IRQ_0_1" hexmask.long.word 0x0 0.--8. 1. " EVE1_IRQ_0 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE1_IRQ_1 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7A4++0x3 line.long 0x0 "CTRL_CORE_EVE1_IRQ_2_3,CTRL_CORE_EVE1_IRQ_2_3" hexmask.long.word 0x0 0.--8. 1. " EVE1_IRQ_2 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE1_IRQ_3 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7A8++0x3 line.long 0x0 "CTRL_CORE_EVE1_IRQ_4_5,CTRL_CORE_EVE1_IRQ_4_5" hexmask.long.word 0x0 0.--8. 1. " EVE1_IRQ_4 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE1_IRQ_5 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7AC++0x3 line.long 0x0 "CTRL_CORE_EVE1_IRQ_6_7,CTRL_CORE_EVE1_IRQ_6_7" hexmask.long.word 0x0 0.--8. 1. " EVE1_IRQ_6 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE1_IRQ_7 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7B0++0x3 line.long 0x0 "CTRL_CORE_EVE2_IRQ_0_1,CTRL_CORE_EVE2_IRQ_0_1" hexmask.long.word 0x0 0.--8. 1. " EVE2_IRQ_0 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE2_IRQ_1 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7B4++0x3 line.long 0x0 "CTRL_CORE_EVE2_IRQ_2_3,CTRL_CORE_EVE2_IRQ_2_3" hexmask.long.word 0x0 0.--8. 1. " EVE2_IRQ_2 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE2_IRQ_3 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7B8++0x3 line.long 0x0 "CTRL_CORE_EVE2_IRQ_4_5,CTRL_CORE_EVE2_IRQ_4_5" hexmask.long.word 0x0 0.--8. 1. " EVE2_IRQ_4 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE2_IRQ_5 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7BC++0x3 line.long 0x0 "CTRL_CORE_EVE2_IRQ_6_7,CTRL_CORE_EVE2_IRQ_6_7" hexmask.long.word 0x0 0.--8. 1. " EVE2_IRQ_6 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE2_IRQ_7 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7C0++0x3 line.long 0x0 "CTRL_CORE_EVE3_IRQ_0_1,CTRL_CORE_EVE3_IRQ_0_1" hexmask.long.word 0x0 0.--8. 1. " EVE3_IRQ_0 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE3_IRQ_1 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7C4++0x3 line.long 0x0 "CTRL_CORE_EVE3_IRQ_2_3,CTRL_CORE_EVE3_IRQ_2_3" hexmask.long.word 0x0 0.--8. 1. " EVE3_IRQ_2 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE3_IRQ_3 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7C8++0x3 line.long 0x0 "CTRL_CORE_EVE3_IRQ_4_5,CTRL_CORE_EVE3_IRQ_4_5" hexmask.long.word 0x0 0.--8. 1. " EVE3_IRQ_4 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE3_IRQ_5 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7CC++0x3 line.long 0x0 "CTRL_CORE_EVE3_IRQ_6_7,CTRL_CORE_EVE3_IRQ_6_7" hexmask.long.word 0x0 0.--8. 1. " EVE3_IRQ_6 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE3_IRQ_7 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7D0++0x3 line.long 0x0 "CTRL_CORE_EVE4_IRQ_0_1,CTRL_CORE_EVE4_IRQ_0_1" hexmask.long.word 0x0 0.--8. 1. " EVE4_IRQ_0 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE4_IRQ_1 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7D4++0x3 line.long 0x0 "CTRL_CORE_EVE4_IRQ_2_3,CTRL_CORE_EVE4_IRQ_2_3" hexmask.long.word 0x0 0.--8. 1. " EVE4_IRQ_2 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE4_IRQ_3 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7D8++0x3 line.long 0x0 "CTRL_CORE_EVE4_IRQ_4_5,CTRL_CORE_EVE4_IRQ_4_5" hexmask.long.word 0x0 0.--8. 1. " EVE4_IRQ_4 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE4_IRQ_5 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7DC++0x3 line.long 0x0 "CTRL_CORE_EVE4_IRQ_6_7,CTRL_CORE_EVE4_IRQ_6_7" hexmask.long.word 0x0 0.--8. 1. " EVE4_IRQ_6 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " EVE4_IRQ_7 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7E0++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_23_24,CTRL_CORE_IPU1_IRQ_23_24" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_23 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_24 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7E4++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_25_26,CTRL_CORE_IPU1_IRQ_25_26" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_25 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_26 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7E8++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_27_28,CTRL_CORE_IPU1_IRQ_27_28" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_27 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_28 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7EC++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_29_30,CTRL_CORE_IPU1_IRQ_29_30" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_29 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_30 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7F0++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_31_32,CTRL_CORE_IPU1_IRQ_31_32" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_31 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_32 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7F4++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_33_34,CTRL_CORE_IPU1_IRQ_33_34" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_33 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_34 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7F8++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_35_36,CTRL_CORE_IPU1_IRQ_35_36" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_35 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_36 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x7FC++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_37_38,CTRL_CORE_IPU1_IRQ_37_38" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_37 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_38 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x800++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_39_40,CTRL_CORE_IPU1_IRQ_39_40" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_39 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_40 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x804++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_41_42,CTRL_CORE_IPU1_IRQ_41_42" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_41 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_42 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x808++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_43_44,CTRL_CORE_IPU1_IRQ_43_44" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_43 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_44 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x80C++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_45_46,CTRL_CORE_IPU1_IRQ_45_46" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_45 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_46 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x810++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_47_48,CTRL_CORE_IPU1_IRQ_47_48" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_47 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_48 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x814++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_49_50,CTRL_CORE_IPU1_IRQ_49_50" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_49 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_50 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x818++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_51_52,CTRL_CORE_IPU1_IRQ_51_52" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_51 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_52 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x81C++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_53_54,CTRL_CORE_IPU1_IRQ_53_54" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_53 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_54 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x820++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_55_56,CTRL_CORE_IPU1_IRQ_55_56" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_55 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_56 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x824++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_57_58,CTRL_CORE_IPU1_IRQ_57_58" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_57 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_58 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x828++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_59_60,CTRL_CORE_IPU1_IRQ_59_60" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_59 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_60 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x82C++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_61_62,CTRL_CORE_IPU1_IRQ_61_62" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_61 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_62 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x830++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_63_64,CTRL_CORE_IPU1_IRQ_63_64" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_63 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_64 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x834++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_65_66,CTRL_CORE_IPU1_IRQ_65_66" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_65 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_66 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x838++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_67_68,CTRL_CORE_IPU1_IRQ_67_68" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_67 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_68 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x83C++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_69_70,CTRL_CORE_IPU1_IRQ_69_70" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_69 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_70 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x840++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_71_72,CTRL_CORE_IPU1_IRQ_71_72" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_71 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_72 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x844++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_73_74,CTRL_CORE_IPU1_IRQ_73_74" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_73 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_74 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x848++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_75_76,CTRL_CORE_IPU1_IRQ_75_76" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_75 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_76 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x84C++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_77_78,CTRL_CORE_IPU1_IRQ_77_78" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_77 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU1_IRQ_78 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x850++0x3 line.long 0x0 "CTRL_CORE_IPU1_IRQ_79_80,CTRL_CORE_IPU1_IRQ_79_80" hexmask.long.word 0x0 0.--8. 1. " IPU1_IRQ_79 ," hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x854++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_23_24,CTRL_CORE_IPU2_IRQ_23_24" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_23 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_24 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x858++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_25_26,CTRL_CORE_IPU2_IRQ_25_26" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_25 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_26 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x85C++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_27_28,CTRL_CORE_IPU2_IRQ_27_28" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_27 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_28 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x860++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_29_30,CTRL_CORE_IPU2_IRQ_29_30" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_29 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_30 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x864++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_31_32,CTRL_CORE_IPU2_IRQ_31_32" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_31 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_32 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x868++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_33_34,CTRL_CORE_IPU2_IRQ_33_34" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_33 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_34 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x86C++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_35_36,CTRL_CORE_IPU2_IRQ_35_36" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_35 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_36 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x870++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_37_38,CTRL_CORE_IPU2_IRQ_37_38" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_37 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_38 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x874++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_39_40,CTRL_CORE_IPU2_IRQ_39_40" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_39 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_40 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x878++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_41_42,CTRL_CORE_IPU2_IRQ_41_42" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_41 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_42 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x87C++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_43_44,CTRL_CORE_IPU2_IRQ_43_44" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_43 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_44 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x880++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_45_46,CTRL_CORE_IPU2_IRQ_45_46" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_45 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_46 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x884++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_47_48,CTRL_CORE_IPU2_IRQ_47_48" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_47 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_48 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x888++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_49_50,CTRL_CORE_IPU2_IRQ_49_50" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_49 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_50 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x88C++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_51_52,CTRL_CORE_IPU2_IRQ_51_52" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_51 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_52 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x890++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_53_54,CTRL_CORE_IPU2_IRQ_53_54" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_53 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_54 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x894++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_55_56,CTRL_CORE_IPU2_IRQ_55_56" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_55 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_56 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x898++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_57_58,CTRL_CORE_IPU2_IRQ_57_58" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_57 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_58 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x89C++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_59_60,CTRL_CORE_IPU2_IRQ_59_60" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_59 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_60 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8A0++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_61_62,CTRL_CORE_IPU2_IRQ_61_62" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_61 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_62 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8A4++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_63_64,CTRL_CORE_IPU2_IRQ_63_64" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_63 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_64 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8A8++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_65_66,CTRL_CORE_IPU2_IRQ_65_66" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_65 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_66 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8AC++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_67_68,CTRL_CORE_IPU2_IRQ_67_68" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_67 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_68 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8B0++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_69_70,CTRL_CORE_IPU2_IRQ_69_70" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_69 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_70 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8B4++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_71_72,CTRL_CORE_IPU2_IRQ_71_72" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_71 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_72 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8B8++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_73_74,CTRL_CORE_IPU2_IRQ_73_74" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_73 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_74 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8BC++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_75_76,CTRL_CORE_IPU2_IRQ_75_76" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_75 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_76 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8C0++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_77_78,CTRL_CORE_IPU2_IRQ_77_78" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_77 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " IPU2_IRQ_78 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8C4++0x3 line.long 0x0 "CTRL_CORE_IPU2_IRQ_79_80,CTRL_CORE_IPU2_IRQ_79_80" hexmask.long.word 0x0 0.--8. 1. " IPU2_IRQ_79 ," hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x8C8++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_32_33,CTRL_CORE_PRUSS1_IRQ_32_33" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_32 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_33 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8CC++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_34_35,CTRL_CORE_PRUSS1_IRQ_34_35" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_34 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_35 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8D0++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_36_37,CTRL_CORE_PRUSS1_IRQ_36_37" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_36 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_37 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8D4++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_38_39,CTRL_CORE_PRUSS1_IRQ_38_39" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_38 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_39 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8D8++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_40_41,CTRL_CORE_PRUSS1_IRQ_40_41" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_40 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_41 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8DC++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_42_43,CTRL_CORE_PRUSS1_IRQ_42_43" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_42 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_43 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8E0++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_44_45,CTRL_CORE_PRUSS1_IRQ_44_45" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_44 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_45 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8E4++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_46_47,CTRL_CORE_PRUSS1_IRQ_46_47" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_46 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_47 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8E8++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_48_49,CTRL_CORE_PRUSS1_IRQ_48_49" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_48 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_49 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8EC++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_50_51,CTRL_CORE_PRUSS1_IRQ_50_51" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_50 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_51 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8F0++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_52_53,CTRL_CORE_PRUSS1_IRQ_52_53" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_52 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_53 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8F4++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_54_55,CTRL_CORE_PRUSS1_IRQ_54_55" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_54 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_55 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8F8++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_56_57,CTRL_CORE_PRUSS1_IRQ_56_57" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_56 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_57 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8FC++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_58_59,CTRL_CORE_PRUSS1_IRQ_58_59" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_58 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_59 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x900++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_60_61,CTRL_CORE_PRUSS1_IRQ_60_61" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_60 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_61 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x904++0x3 line.long 0x0 "CTRL_CORE_PRUSS1_IRQ_62_63,CTRL_CORE_PRUSS1_IRQ_62_63" hexmask.long.word 0x0 0.--8. 1. " PRUSS1_IRQ_62 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS1_IRQ_63 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x908++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_32_33,CTRL_CORE_PRUSS2_IRQ_32_33" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_32 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_33 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x90C++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_34_35,CTRL_CORE_PRUSS2_IRQ_34_35" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_34 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_35 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x910++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_36_37,CTRL_CORE_PRUSS2_IRQ_36_37" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_36 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_37 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x914++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_38_39,CTRL_CORE_PRUSS2_IRQ_38_39" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_38 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_39 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x918++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_40_41,CTRL_CORE_PRUSS2_IRQ_40_41" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_40 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_41 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x91C++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_42_43,CTRL_CORE_PRUSS2_IRQ_42_43" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_42 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_43 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x920++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_44_45,CTRL_CORE_PRUSS2_IRQ_44_45" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_44 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_45 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x924++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_46_47,CTRL_CORE_PRUSS2_IRQ_46_47" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_46 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_47 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x928++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_48_49,CTRL_CORE_PRUSS2_IRQ_48_49" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_48 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_49 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x92C++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_50_51,CTRL_CORE_PRUSS2_IRQ_50_51" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_50 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_51 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x930++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_52_53,CTRL_CORE_PRUSS2_IRQ_52_53" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_52 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_53 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x934++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_54_55,CTRL_CORE_PRUSS2_IRQ_54_55" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_54 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_55 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x938++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_56_57,CTRL_CORE_PRUSS2_IRQ_56_57" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_56 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_57 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x93C++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_58_59,CTRL_CORE_PRUSS2_IRQ_58_59" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_58 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_59 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x940++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_60_61,CTRL_CORE_PRUSS2_IRQ_60_61" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_60 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_61 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x944++0x3 line.long 0x0 "CTRL_CORE_PRUSS2_IRQ_62_63,CTRL_CORE_PRUSS2_IRQ_62_63" hexmask.long.word 0x0 0.--8. 1. " PRUSS2_IRQ_62 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " PRUSS2_IRQ_63 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x948++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_32_33,CTRL_CORE_DSP1_IRQ_32_33" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_32 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_33 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x94C++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_34_35,CTRL_CORE_DSP1_IRQ_34_35" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_34 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_35 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x950++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_36_37,CTRL_CORE_DSP1_IRQ_36_37" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_36 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_37 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x954++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_38_39,CTRL_CORE_DSP1_IRQ_38_39" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_38 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_39 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x958++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_40_41,CTRL_CORE_DSP1_IRQ_40_41" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_40 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_41 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x95C++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_42_43,CTRL_CORE_DSP1_IRQ_42_43" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_42 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_43 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x960++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_44_45,CTRL_CORE_DSP1_IRQ_44_45" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_44 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_45 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x964++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_46_47,CTRL_CORE_DSP1_IRQ_46_47" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_46 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_47 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x968++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_48_49,CTRL_CORE_DSP1_IRQ_48_49" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_48 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_49 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x96C++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_50_51,CTRL_CORE_DSP1_IRQ_50_51" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_50 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_51 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x970++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_52_53,CTRL_CORE_DSP1_IRQ_52_53" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_52 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_53 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x974++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_54_55,CTRL_CORE_DSP1_IRQ_54_55" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_54 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_55 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x978++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_56_57,CTRL_CORE_DSP1_IRQ_56_57" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_56 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_57 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x97C++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_58_59,CTRL_CORE_DSP1_IRQ_58_59" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_58 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_59 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x980++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_60_61,CTRL_CORE_DSP1_IRQ_60_61" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_60 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_61 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x984++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_62_63,CTRL_CORE_DSP1_IRQ_62_63" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_62 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_63 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x988++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_64_65,CTRL_CORE_DSP1_IRQ_64_65" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_64 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_65 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x98C++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_66_67,CTRL_CORE_DSP1_IRQ_66_67" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_66 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_67 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x990++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_68_69,CTRL_CORE_DSP1_IRQ_68_69" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_68 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_69 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x994++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_70_71,CTRL_CORE_DSP1_IRQ_70_71" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_70 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_71 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x998++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_72_73,CTRL_CORE_DSP1_IRQ_72_73" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_72 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_73 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x99C++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_74_75,CTRL_CORE_DSP1_IRQ_74_75" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_74 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_75 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9A0++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_76_77,CTRL_CORE_DSP1_IRQ_76_77" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_76 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_77 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9A4++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_78_79,CTRL_CORE_DSP1_IRQ_78_79" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_78 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_79 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9A8++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_80_81,CTRL_CORE_DSP1_IRQ_80_81" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_80 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_81 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9AC++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_82_83,CTRL_CORE_DSP1_IRQ_82_83" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_82 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_83 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9B0++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_84_85,CTRL_CORE_DSP1_IRQ_84_85" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_84 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_85 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9B4++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_86_87,CTRL_CORE_DSP1_IRQ_86_87" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_86 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_87 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9B8++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_88_89,CTRL_CORE_DSP1_IRQ_88_89" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_88 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_89 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9BC++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_90_91,CTRL_CORE_DSP1_IRQ_90_91" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_90 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_91 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9C0++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_92_93,CTRL_CORE_DSP1_IRQ_92_93" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_92 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_93 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9C4++0x3 line.long 0x0 "CTRL_CORE_DSP1_IRQ_94_95,CTRL_CORE_DSP1_IRQ_94_95" hexmask.long.word 0x0 0.--8. 1. " DSP1_IRQ_94 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP1_IRQ_95 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9C8++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_32_33,CTRL_CORE_DSP2_IRQ_32_33" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_32 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_33 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9CC++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_34_35,CTRL_CORE_DSP2_IRQ_34_35" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_34 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_35 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9D0++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_36_37,CTRL_CORE_DSP2_IRQ_36_37" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_36 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_37 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9D4++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_38_39,CTRL_CORE_DSP2_IRQ_38_39" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_38 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_39 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9D8++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_40_41,CTRL_CORE_DSP2_IRQ_40_41" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_40 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_41 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9DC++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_42_43,CTRL_CORE_DSP2_IRQ_42_43" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_42 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_43 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9E0++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_44_45,CTRL_CORE_DSP2_IRQ_44_45" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_44 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_45 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9E4++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_46_47,CTRL_CORE_DSP2_IRQ_46_47" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_46 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_47 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9E8++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_48_49,CTRL_CORE_DSP2_IRQ_48_49" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_48 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_49 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9EC++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_50_51,CTRL_CORE_DSP2_IRQ_50_51" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_50 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_51 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9F0++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_52_53,CTRL_CORE_DSP2_IRQ_52_53" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_52 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_53 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9F4++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_54_55,CTRL_CORE_DSP2_IRQ_54_55" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_54 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_55 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9F8++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_56_57,CTRL_CORE_DSP2_IRQ_56_57" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_56 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_57 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x9FC++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_58_59,CTRL_CORE_DSP2_IRQ_58_59" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_58 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_59 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA00++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_60_61,CTRL_CORE_DSP2_IRQ_60_61" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_60 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_61 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA04++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_62_63,CTRL_CORE_DSP2_IRQ_62_63" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_62 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_63 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA08++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_64_65,CTRL_CORE_DSP2_IRQ_64_65" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_64 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_65 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA0C++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_66_67,CTRL_CORE_DSP2_IRQ_66_67" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_66 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_67 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA10++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_68_69,CTRL_CORE_DSP2_IRQ_68_69" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_68 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_69 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA14++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_70_71,CTRL_CORE_DSP2_IRQ_70_71" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_70 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_71 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA18++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_72_73,CTRL_CORE_DSP2_IRQ_72_73" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_72 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_73 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA1C++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_74_75,CTRL_CORE_DSP2_IRQ_74_75" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_74 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_75 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA20++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_76_77,CTRL_CORE_DSP2_IRQ_76_77" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_76 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_77 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA24++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_78_79,CTRL_CORE_DSP2_IRQ_78_79" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_78 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_79 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA28++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_80_81,CTRL_CORE_DSP2_IRQ_80_81" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_80 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_81 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA2C++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_82_83,CTRL_CORE_DSP2_IRQ_82_83" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_82 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_83 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA30++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_84_85,CTRL_CORE_DSP2_IRQ_84_85" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_84 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_85 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA34++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_86_87,CTRL_CORE_DSP2_IRQ_86_87" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_86 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_87 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA38++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_88_89,CTRL_CORE_DSP2_IRQ_88_89" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_88 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_89 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA3C++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_90_91,CTRL_CORE_DSP2_IRQ_90_91" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_90 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_91 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA40++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_92_93,CTRL_CORE_DSP2_IRQ_92_93" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_92 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_93 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA44++0x3 line.long 0x0 "CTRL_CORE_DSP2_IRQ_94_95,CTRL_CORE_DSP2_IRQ_94_95" hexmask.long.word 0x0 0.--8. 1. " DSP2_IRQ_94 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " DSP2_IRQ_95 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA48++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_4_7,CTRL_CORE_MPU_IRQ_4_7" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_4 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_7 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA4C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_8_9,CTRL_CORE_MPU_IRQ_8_9" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_8 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_9 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA50++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_10_11,CTRL_CORE_MPU_IRQ_10_11" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_10 ,NOTE: This bit field is not functional" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_11 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA54++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_12_13,CTRL_CORE_MPU_IRQ_12_13" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_12 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_13 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA58++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_14_15,CTRL_CORE_MPU_IRQ_14_15" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_14 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_15 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA5C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_16_17,CTRL_CORE_MPU_IRQ_16_17" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_16 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_17 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA60++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_18_19,CTRL_CORE_MPU_IRQ_18_19" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_18 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_19 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA64++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_20_21,CTRL_CORE_MPU_IRQ_20_21" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_20 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_21 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA68++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_22_23,CTRL_CORE_MPU_IRQ_22_23" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_22 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_23 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA6C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_24_25,CTRL_CORE_MPU_IRQ_24_25" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_24 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_25 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA70++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_26_27,CTRL_CORE_MPU_IRQ_26_27" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_26 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_27 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA74++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_28_29,CTRL_CORE_MPU_IRQ_28_29" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_28 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_29 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA78++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_30_31,CTRL_CORE_MPU_IRQ_30_31" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_30 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_31 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA7C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_32_33,CTRL_CORE_MPU_IRQ_32_33" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_32 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_33 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA80++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_34_35,CTRL_CORE_MPU_IRQ_34_35" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_34 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_35 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA84++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_36_37,CTRL_CORE_MPU_IRQ_36_37" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_36 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_37 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA88++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_38_39,CTRL_CORE_MPU_IRQ_38_39" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_38 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_39 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA8C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_40_41,CTRL_CORE_MPU_IRQ_40_41" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_40 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_41 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA90++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_42_43,CTRL_CORE_MPU_IRQ_42_43" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_42 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_43 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA94++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_44_45,CTRL_CORE_MPU_IRQ_44_45" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_44 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_45 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA98++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_46_47,CTRL_CORE_MPU_IRQ_46_47" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_46 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_47 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xA9C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_48_49,CTRL_CORE_MPU_IRQ_48_49" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_48 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_49 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAA0++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_50_51,CTRL_CORE_MPU_IRQ_50_51" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_50 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_51 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAA4++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_52_53,CTRL_CORE_MPU_IRQ_52_53" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_52 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_53 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAA8++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_54_55,CTRL_CORE_MPU_IRQ_54_55" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_54 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_55 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAAC++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_56_57,CTRL_CORE_MPU_IRQ_56_57" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_56 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_57 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAB0++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_58_59,CTRL_CORE_MPU_IRQ_58_59" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_58 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_59 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAB4++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_60_61,CTRL_CORE_MPU_IRQ_60_61" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_60 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_61 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAB8++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_62_63,CTRL_CORE_MPU_IRQ_62_63" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_62 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_63 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xABC++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_64_65,CTRL_CORE_MPU_IRQ_64_65" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_64 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_65 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAC0++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_66_67,CTRL_CORE_MPU_IRQ_66_67" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_66 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_67 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAC4++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_68_69,CTRL_CORE_MPU_IRQ_68_69" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_68 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_69 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAC8++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_70_71,CTRL_CORE_MPU_IRQ_70_71" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_70 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_71 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xACC++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_72_73,CTRL_CORE_MPU_IRQ_72_73" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_72 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_73 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAD0++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_74_75,CTRL_CORE_MPU_IRQ_74_75" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_74 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_75 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAD4++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_76_77,CTRL_CORE_MPU_IRQ_76_77" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_76 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_77 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAD8++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_78_79,CTRL_CORE_MPU_IRQ_78_79" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_78 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_79 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xADC++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_80_81,CTRL_CORE_MPU_IRQ_80_81" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_80 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_81 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAE0++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_82_83,CTRL_CORE_MPU_IRQ_82_83" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_82 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_83 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAE4++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_84_85,CTRL_CORE_MPU_IRQ_84_85" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_84 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_85 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAE8++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_86_87,CTRL_CORE_MPU_IRQ_86_87" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_86 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_87 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAEC++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_88_89,CTRL_CORE_MPU_IRQ_88_89" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_88 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_89 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAF0++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_90_91,CTRL_CORE_MPU_IRQ_90_91" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_90 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_91 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAF4++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_92_93,CTRL_CORE_MPU_IRQ_92_93" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_92 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_93 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAF8++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_94_95,CTRL_CORE_MPU_IRQ_94_95" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_94 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_95 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xAFC++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_96_97,CTRL_CORE_MPU_IRQ_96_97" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_96 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_97 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB00++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_98_99,CTRL_CORE_MPU_IRQ_98_99" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_98 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_99 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB04++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_100_101,CTRL_CORE_MPU_IRQ_100_101" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_100 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_101 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB08++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_102_103,CTRL_CORE_MPU_IRQ_102_103" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_102 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_103 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB0C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_104_105,CTRL_CORE_MPU_IRQ_104_105" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_104 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_105 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB10++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_106_107,CTRL_CORE_MPU_IRQ_106_107" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_106 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_107 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB14++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_108_109,CTRL_CORE_MPU_IRQ_108_109" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_108 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_109 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB18++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_110_111,CTRL_CORE_MPU_IRQ_110_111" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_110 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_111 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB1C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_112_113,CTRL_CORE_MPU_IRQ_112_113" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_112 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_113 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB20++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_114_115,CTRL_CORE_MPU_IRQ_114_115" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_114 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_115 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB24++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_116_117,CTRL_CORE_MPU_IRQ_116_117" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_116 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_117 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB28++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_118_119,CTRL_CORE_MPU_IRQ_118_119" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_118 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_119 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB2C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_120_121,CTRL_CORE_MPU_IRQ_120_121" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_120 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_121 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB30++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_122_123,CTRL_CORE_MPU_IRQ_122_123" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_122 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_123 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB34++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_124_125,CTRL_CORE_MPU_IRQ_124_125" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_124 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_125 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB38++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_126_127,CTRL_CORE_MPU_IRQ_126_127" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_126 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_127 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB3C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_128_129,CTRL_CORE_MPU_IRQ_128_129" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_128 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_129 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB40++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_130_133,CTRL_CORE_MPU_IRQ_130_133" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_130 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_133 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB44++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_134_135,CTRL_CORE_MPU_IRQ_134_135" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_134 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_135 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB48++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_136_137,CTRL_CORE_MPU_IRQ_136_137" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_136 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_137 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB4C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_138_139,CTRL_CORE_MPU_IRQ_138_139" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_138 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_139 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB50++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_140_141,CTRL_CORE_MPU_IRQ_140_141" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_140 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_141 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB54++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_142_143,CTRL_CORE_MPU_IRQ_142_143" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_142 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_143 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB58++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_144_145,CTRL_CORE_MPU_IRQ_144_145" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_144 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_145 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB5C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_146_147,CTRL_CORE_MPU_IRQ_146_147" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_146 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_147 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB60++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_148_149,CTRL_CORE_MPU_IRQ_148_149" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_148 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_149 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB64++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_150_151,CTRL_CORE_MPU_IRQ_150_151" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_150 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_151 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB68++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_152_153,CTRL_CORE_MPU_IRQ_152_153" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_152 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_153 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB6C++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_154_155,CTRL_CORE_MPU_IRQ_154_155" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_154 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_155 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB70++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_156_157,CTRL_CORE_MPU_IRQ_156_157" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_156 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_157 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB74++0x3 line.long 0x0 "CTRL_CORE_MPU_IRQ_158_159,CTRL_CORE_MPU_IRQ_158_159" hexmask.long.word 0x0 0.--8. 1. " MPU_IRQ_158 ," hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " MPU_IRQ_159 ," hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0xB78++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_0_1,CTRL_CORE_DMA_SYSTEM_DREQ_0_1" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_0_IRQ_0 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_1_IRQ_1 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB7C++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_2_3,CTRL_CORE_DMA_SYSTEM_DREQ_2_3" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_2_IRQ_2 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_3_IRQ_3 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB80++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_4_5,CTRL_CORE_DMA_SYSTEM_DREQ_4_5" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_4_IRQ_4 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_5_IRQ_5 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB84++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_6_7,CTRL_CORE_DMA_SYSTEM_DREQ_6_7" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_6_IRQ_6 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_7_IRQ_7 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB88++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_8_9,CTRL_CORE_DMA_SYSTEM_DREQ_8_9" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_8_IRQ_8 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_9_IRQ_9 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB8C++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_10_11,CTRL_CORE_DMA_SYSTEM_DREQ_10_11" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_10_IRQ_10 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_11_IRQ_11 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB90++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_12_13,CTRL_CORE_DMA_SYSTEM_DREQ_12_13" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_12_IRQ_12 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_13_IRQ_13 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB94++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_14_15,CTRL_CORE_DMA_SYSTEM_DREQ_14_15" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_14_IRQ_14 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_15_IRQ_15 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB98++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_16_17,CTRL_CORE_DMA_SYSTEM_DREQ_16_17" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_16_IRQ_16 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_17_IRQ_17 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB9C++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_18_19,CTRL_CORE_DMA_SYSTEM_DREQ_18_19" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_18_IRQ_18 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_19_IRQ_19 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBA0++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_20_21,CTRL_CORE_DMA_SYSTEM_DREQ_20_21" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_20_IRQ_20 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_21_IRQ_21 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBA4++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_22_23,CTRL_CORE_DMA_SYSTEM_DREQ_22_23" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_22_IRQ_22 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_23_IRQ_23 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBA8++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_24_25,CTRL_CORE_DMA_SYSTEM_DREQ_24_25" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_24_IRQ_24 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_25_IRQ_25 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBAC++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_26_27,CTRL_CORE_DMA_SYSTEM_DREQ_26_27" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_26_IRQ_26 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_27_IRQ_27 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBB0++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_28_29,CTRL_CORE_DMA_SYSTEM_DREQ_28_29" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_28_IRQ_28 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_29_IRQ_29 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBB4++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_30_31,CTRL_CORE_DMA_SYSTEM_DREQ_30_31" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_30_IRQ_30 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_31_IRQ_31 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBB8++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_32_33,CTRL_CORE_DMA_SYSTEM_DREQ_32_33" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_32_IRQ_32 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_33_IRQ_33 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBBC++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_34_35,CTRL_CORE_DMA_SYSTEM_DREQ_34_35" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_34_IRQ_34 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_35_IRQ_35 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBC0++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_36_37,CTRL_CORE_DMA_SYSTEM_DREQ_36_37" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_36_IRQ_36 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_37_IRQ_37 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBC4++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_38_39,CTRL_CORE_DMA_SYSTEM_DREQ_38_39" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_38_IRQ_38 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_39_IRQ_39 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBC8++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_40_41,CTRL_CORE_DMA_SYSTEM_DREQ_40_41" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_40_IRQ_40 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_41_IRQ_41 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBCC++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_42_43,CTRL_CORE_DMA_SYSTEM_DREQ_42_43" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_42_IRQ_42 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_43_IRQ_43 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBD0++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_44_45,CTRL_CORE_DMA_SYSTEM_DREQ_44_45" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_44_IRQ_44 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_45_IRQ_45 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBD4++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_46_47,CTRL_CORE_DMA_SYSTEM_DREQ_46_47" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_46_IRQ_46 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_47_IRQ_47 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBD8++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_48_49,CTRL_CORE_DMA_SYSTEM_DREQ_48_49" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_48_IRQ_48 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_49_IRQ_49 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBDC++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_50_51,CTRL_CORE_DMA_SYSTEM_DREQ_50_51" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_50_IRQ_50 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_51_IRQ_51 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBE0++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_52_53,CTRL_CORE_DMA_SYSTEM_DREQ_52_53" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_52_IRQ_52 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_53_IRQ_53 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBE4++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_54_55,CTRL_CORE_DMA_SYSTEM_DREQ_54_55" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_54_IRQ_54 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_55_IRQ_55 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBE8++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_56_57,CTRL_CORE_DMA_SYSTEM_DREQ_56_57" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_56_IRQ_56 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_57_IRQ_57 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBEC++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_58_59,CTRL_CORE_DMA_SYSTEM_DREQ_58_59" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_58_IRQ_58 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_59_IRQ_59 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBF0++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_60_61,CTRL_CORE_DMA_SYSTEM_DREQ_60_61" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_60_IRQ_60 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_61_IRQ_61 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBF4++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_62_63,CTRL_CORE_DMA_SYSTEM_DREQ_62_63" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_62_IRQ_62 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_63_IRQ_63 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBF8++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_64_65,CTRL_CORE_DMA_SYSTEM_DREQ_64_65" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_64_IRQ_64 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_65_IRQ_65 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xBFC++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_66_67,CTRL_CORE_DMA_SYSTEM_DREQ_66_67" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_66_IRQ_66 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_67_IRQ_67 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC00++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_68_69,CTRL_CORE_DMA_SYSTEM_DREQ_68_69" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_68_IRQ_68 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_69_IRQ_69 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC04++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_70_71,CTRL_CORE_DMA_SYSTEM_DREQ_70_71" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_70_IRQ_70 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_71_IRQ_71 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC08++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_72_73,CTRL_CORE_DMA_SYSTEM_DREQ_72_73" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_72_IRQ_72 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_73_IRQ_73 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC0C++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_74_75,CTRL_CORE_DMA_SYSTEM_DREQ_74_75" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_74_IRQ_74 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_75_IRQ_75 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC10++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_76_77,CTRL_CORE_DMA_SYSTEM_DREQ_76_77" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_76_IRQ_76 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_77_IRQ_77 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC14++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_78_79,CTRL_CORE_DMA_SYSTEM_DREQ_78_79" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_78_IRQ_78 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_79_IRQ_79 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC18++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_80_81,CTRL_CORE_DMA_SYSTEM_DREQ_80_81" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_80_IRQ_80 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_81_IRQ_81 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC1C++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_82_83,CTRL_CORE_DMA_SYSTEM_DREQ_82_83" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_82_IRQ_82 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_83_IRQ_83 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC20++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_84_85,CTRL_CORE_DMA_SYSTEM_DREQ_84_85" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_84_IRQ_84 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_85_IRQ_85 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC24++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_86_87,CTRL_CORE_DMA_SYSTEM_DREQ_86_87" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_86_IRQ_86 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_87_IRQ_87 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC28++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_88_89,CTRL_CORE_DMA_SYSTEM_DREQ_88_89" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_88_IRQ_88 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_89_IRQ_89 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC2C++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_90_91,CTRL_CORE_DMA_SYSTEM_DREQ_90_91" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_90_IRQ_90 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_91_IRQ_91 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC30++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_92_93,CTRL_CORE_DMA_SYSTEM_DREQ_92_93" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_92_IRQ_92 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_93_IRQ_93 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC34++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_94_95,CTRL_CORE_DMA_SYSTEM_DREQ_94_95" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_94_IRQ_94 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_95_IRQ_95 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC38++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_96_97,CTRL_CORE_DMA_SYSTEM_DREQ_96_97" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_96_IRQ_96 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_97_IRQ_97 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC3C++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_98_99,CTRL_CORE_DMA_SYSTEM_DREQ_98_99" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_98_IRQ_98 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_99_IRQ_99 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC40++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_100_101,CTRL_CORE_DMA_SYSTEM_DREQ_100_101" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_100_IRQ_100 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_101_IRQ_101 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC44++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_102_103,CTRL_CORE_DMA_SYSTEM_DREQ_102_103" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_102_IRQ_102 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_103_IRQ_103 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC48++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_104_105,CTRL_CORE_DMA_SYSTEM_DREQ_104_105" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_104_IRQ_104 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_105_IRQ_105 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC4C++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_106_107,CTRL_CORE_DMA_SYSTEM_DREQ_106_107" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_106_IRQ_106 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_107_IRQ_107 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC50++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_108_109,CTRL_CORE_DMA_SYSTEM_DREQ_108_109" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_108_IRQ_108 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_109_IRQ_109 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC54++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_110_111,CTRL_CORE_DMA_SYSTEM_DREQ_110_111" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_110_IRQ_110 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_111_IRQ_111 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC58++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_112_113,CTRL_CORE_DMA_SYSTEM_DREQ_112_113" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_112_IRQ_112 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_113_IRQ_113 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC5C++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_114_115,CTRL_CORE_DMA_SYSTEM_DREQ_114_115" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_114_IRQ_114 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_115_IRQ_115 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC60++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_116_117,CTRL_CORE_DMA_SYSTEM_DREQ_116_117" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_116_IRQ_116 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_117_IRQ_117 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC64++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_118_119,CTRL_CORE_DMA_SYSTEM_DREQ_118_119" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_118_IRQ_118 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_119_IRQ_119 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC68++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_120_121,CTRL_CORE_DMA_SYSTEM_DREQ_120_121" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_120_IRQ_120 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_121_IRQ_121 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC6C++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_122_123,CTRL_CORE_DMA_SYSTEM_DREQ_122_123" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_122_IRQ_122 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_123_IRQ_123 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC70++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_124_125,CTRL_CORE_DMA_SYSTEM_DREQ_124_125" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_124_IRQ_124 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_SYSTEM_DREQ_125_IRQ_125 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC74++0x3 line.long 0x0 "CTRL_CORE_DMA_SYSTEM_DREQ_126_127,CTRL_CORE_DMA_SYSTEM_DREQ_126_127" hexmask.long.byte 0x0 0.--7. 1. " DMA_SYSTEM_DREQ_126_IRQ_126 ," hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0xC78++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_0_1,CTRL_CORE_DMA_EDMA_DREQ_0_1" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_0_IRQ_0 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_1_IRQ_1 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC7C++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_2_3,CTRL_CORE_DMA_EDMA_DREQ_2_3" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_2_IRQ_2 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_3_IRQ_3 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC80++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_4_5,CTRL_CORE_DMA_EDMA_DREQ_4_5" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_4_IRQ_4 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_5_IRQ_5 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC84++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_6_7,CTRL_CORE_DMA_EDMA_DREQ_6_7" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_6_IRQ_6 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_7_IRQ_7 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC88++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_8_9,CTRL_CORE_DMA_EDMA_DREQ_8_9" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_8_IRQ_8 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_9_IRQ_9 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC8C++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_10_11,CTRL_CORE_DMA_EDMA_DREQ_10_11" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_10_IRQ_10 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_11_IRQ_11 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC90++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_12_13,CTRL_CORE_DMA_EDMA_DREQ_12_13" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_12_IRQ_12 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_13_IRQ_13 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC94++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_14_15,CTRL_CORE_DMA_EDMA_DREQ_14_15" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_14_IRQ_14 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_15_IRQ_15 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC98++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_16_17,CTRL_CORE_DMA_EDMA_DREQ_16_17" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_16_IRQ_16 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_17_IRQ_17 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC9C++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_18_19,CTRL_CORE_DMA_EDMA_DREQ_18_19" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_18_IRQ_18 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_19_IRQ_19 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCA0++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_20_21,CTRL_CORE_DMA_EDMA_DREQ_20_21" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_20_IRQ_20 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_21_IRQ_21 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCA4++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_22_23,CTRL_CORE_DMA_EDMA_DREQ_22_23" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_22_IRQ_22 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_23_IRQ_23 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCA8++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_24_25,CTRL_CORE_DMA_EDMA_DREQ_24_25" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_24_IRQ_24 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_25_IRQ_25 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCAC++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_26_27,CTRL_CORE_DMA_EDMA_DREQ_26_27" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_26_IRQ_26 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_27_IRQ_27 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCB0++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_28_29,CTRL_CORE_DMA_EDMA_DREQ_28_29" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_28_IRQ_28 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_29_IRQ_29 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCB4++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_30_31,CTRL_CORE_DMA_EDMA_DREQ_30_31" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_30_IRQ_30 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_31_IRQ_31 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCB8++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_32_33,CTRL_CORE_DMA_EDMA_DREQ_32_33" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_32_IRQ_32 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_33_IRQ_33 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCBC++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_34_35,CTRL_CORE_DMA_EDMA_DREQ_34_35" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_34_IRQ_34 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_35_IRQ_35 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCC0++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_36_37,CTRL_CORE_DMA_EDMA_DREQ_36_37" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_36_IRQ_36 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_37_IRQ_37 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCC4++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_38_39,CTRL_CORE_DMA_EDMA_DREQ_38_39" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_38_IRQ_38 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_39_IRQ_39 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCC8++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_40_41,CTRL_CORE_DMA_EDMA_DREQ_40_41" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_40_IRQ_40 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_41_IRQ_41 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCCC++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_42_43,CTRL_CORE_DMA_EDMA_DREQ_42_43" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_42_IRQ_42 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_43_IRQ_43 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCD0++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_44_45,CTRL_CORE_DMA_EDMA_DREQ_44_45" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_44_IRQ_44 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_45_IRQ_45 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCD4++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_46_47,CTRL_CORE_DMA_EDMA_DREQ_46_47" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_46_IRQ_46 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_47_IRQ_47 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCD8++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_48_49,CTRL_CORE_DMA_EDMA_DREQ_48_49" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_48_IRQ_48 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_49_IRQ_49 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCDC++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_50_51,CTRL_CORE_DMA_EDMA_DREQ_50_51" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_50_IRQ_50 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_51_IRQ_51 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCE0++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_52_53,CTRL_CORE_DMA_EDMA_DREQ_52_53" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_52_IRQ_52 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_53_IRQ_53 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCE4++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_54_55,CTRL_CORE_DMA_EDMA_DREQ_54_55" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_54_IRQ_54 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_55_IRQ_55 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCE8++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_56_57,CTRL_CORE_DMA_EDMA_DREQ_56_57" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_56_IRQ_56 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_57_IRQ_57 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCEC++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_58_59,CTRL_CORE_DMA_EDMA_DREQ_58_59" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_58_IRQ_58 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_59_IRQ_59 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCF0++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_60_61,CTRL_CORE_DMA_EDMA_DREQ_60_61" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_60_IRQ_60 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_61_IRQ_61 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCF4++0x3 line.long 0x0 "CTRL_CORE_DMA_EDMA_DREQ_62_63,CTRL_CORE_DMA_EDMA_DREQ_62_63" hexmask.long.byte 0x0 0.--7. 1. " DMA_EDMA_DREQ_62_IRQ_62 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_EDMA_DREQ_63_IRQ_63 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCF8++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP1_DREQ_0_1,CTRL_CORE_DMA_DSP1_DREQ_0_1" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP1_DREQ_0_IRQ_0 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP1_DREQ_1_IRQ_1 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xCFC++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP1_DREQ_2_3,CTRL_CORE_DMA_DSP1_DREQ_2_3" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP1_DREQ_2_IRQ_2 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP1_DREQ_3_IRQ_3 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD00++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP1_DREQ_4_5,CTRL_CORE_DMA_DSP1_DREQ_4_5" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP1_DREQ_4_IRQ_4 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP1_DREQ_5_IRQ_5 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD04++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP1_DREQ_6_7,CTRL_CORE_DMA_DSP1_DREQ_6_7" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP1_DREQ_6_IRQ_6 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP1_DREQ_7_IRQ_7 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD08++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP1_DREQ_8_9,CTRL_CORE_DMA_DSP1_DREQ_8_9" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP1_DREQ_8_IRQ_8 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP1_DREQ_9_IRQ_9 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD0C++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP1_DREQ_10_11,CTRL_CORE_DMA_DSP1_DREQ_10_11" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP1_DREQ_10_IRQ_10 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP1_DREQ_11_IRQ_11 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD10++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP1_DREQ_12_13,CTRL_CORE_DMA_DSP1_DREQ_12_13" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP1_DREQ_12_IRQ_12 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP1_DREQ_13_IRQ_13 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD14++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP1_DREQ_14_15,CTRL_CORE_DMA_DSP1_DREQ_14_15" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP1_DREQ_14_IRQ_14 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP1_DREQ_15_IRQ_15 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD18++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP1_DREQ_16_17,CTRL_CORE_DMA_DSP1_DREQ_16_17" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP1_DREQ_16_IRQ_16 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP1_DREQ_17_IRQ_17 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD1C++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP1_DREQ_18_19,CTRL_CORE_DMA_DSP1_DREQ_18_19" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP1_DREQ_18_IRQ_18 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP1_DREQ_19_IRQ_19 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD20++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP2_DREQ_0_1,CTRL_CORE_DMA_DSP2_DREQ_0_1" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP2_DREQ_0_IRQ_0 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP2_DREQ_1_IRQ_1 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD24++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP2_DREQ_2_3,CTRL_CORE_DMA_DSP2_DREQ_2_3" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP2_DREQ_2_IRQ_2 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP2_DREQ_3_IRQ_3 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD28++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP2_DREQ_4_5,CTRL_CORE_DMA_DSP2_DREQ_4_5" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP2_DREQ_4_IRQ_4 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP2_DREQ_5_IRQ_5 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD2C++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP2_DREQ_6_7,CTRL_CORE_DMA_DSP2_DREQ_6_7" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP2_DREQ_6_IRQ_6 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP2_DREQ_7_IRQ_7 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD30++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP2_DREQ_8_9,CTRL_CORE_DMA_DSP2_DREQ_8_9" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP2_DREQ_8_IRQ_8 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP2_DREQ_9_IRQ_9 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD34++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP2_DREQ_10_11,CTRL_CORE_DMA_DSP2_DREQ_10_11" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP2_DREQ_10_IRQ_10 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP2_DREQ_11_IRQ_11 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD38++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP2_DREQ_12_13,CTRL_CORE_DMA_DSP2_DREQ_12_13" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP2_DREQ_12_IRQ_12 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP2_DREQ_13_IRQ_13 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD3C++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP2_DREQ_14_15,CTRL_CORE_DMA_DSP2_DREQ_14_15" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP2_DREQ_14_IRQ_14 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP2_DREQ_15_IRQ_15 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD40++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP2_DREQ_16_17,CTRL_CORE_DMA_DSP2_DREQ_16_17" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP2_DREQ_16_IRQ_16 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP2_DREQ_17_IRQ_17 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD44++0x3 line.long 0x0 "CTRL_CORE_DMA_DSP2_DREQ_18_19,CTRL_CORE_DMA_DSP2_DREQ_18_19" hexmask.long.byte 0x0 0.--7. 1. " DMA_DSP2_DREQ_18_IRQ_18 ," hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " DMA_DSP2_DREQ_19_IRQ_19 ," hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xD4C++0x3 line.long 0x0 "CTRL_CORE_OVS_DMARQ_IO_MUX,CTRL_CORE_OVS_DMARQ_IO_MUX" hexmask.long.byte 0x0 0.--7. 1. " OVS_DMARQ_IO_MUX_1 ," hexmask.long.byte 0x0 8.--15. 1. " OVS_DMARQ_IO_MUX_2 ," textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xD50++0x3 line.long 0x0 "CTRL_CORE_OVS_IRQ_IO_MUX,CTRL_CORE_OVS_IRQ_IO_MUX" hexmask.long.word 0x0 0.--8. 1. " OVS_IRQ_IO_MUX_1 ," hexmask.long.word 0x0 9.--17. 1. " OVS_IRQ_IO_MUX_2 ," textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0xE00++0x3 line.long 0x0 "CTRL_CORE_CONTROL_PBIAS,PBIASLITE control" hexmask.long.tbyte 0x0 0.--20. 1. " RESERVED ," bitfld.long 0x0 21. " SDCARD_BIAS_VMODE ,VMODE control to SDCARD PBIAS 0x0 = VDDS = 1.8V 0x1 = VDDS = 3.3V" "0,1" textline " " bitfld.long 0x0 22. " RESERVED ," "0,1" bitfld.long 0x0 23. " SDCARD_BIAS_VMODE_ERROR ,VMODE ERROR from SDCARD PBIAS 0x0 = VMODE level is same as SUPPLY_HI_OUT 0x1 = VMODE level is not same as SUPPLY_HI_OUT" "0,1" textline " " bitfld.long 0x0 24. " SDCARD_BIAS_SUPPLY_HI_OUT ,SUPPLY_HI_OUT from SDCARD PBIAS 0x0 = VDDS = 1.8V 0x1 = VDDS = 3.3V" "0,1" bitfld.long 0x0 25. " SDCARD_BIAS_HIZ_MODE ,HIZ_MODE from SDCARD PBIAS 0x0 = PBIAS in normal operation mode 0x1 = PBIAS output is in high impedance state" "0,1" textline " " bitfld.long 0x0 26. " SDCARD_IO_PWRDNZ ,PWRDNZ control to SDCARD IO 0x0 = This signal is used to protect SDCARD IOs when VDDS is not stable 0x1 = SW keep this bit to 1'b1 after VDDS stabilizing" "0,1" bitfld.long 0x0 27. " SDCARD_BIAS_PWRDNZ ,PWRDNZ control to SDCARD BIAS 0x0 = This signal is used to protect SDCARD BIAS when VDDS is not stable 0x1 = SW keep this bit to 1'b1 after VDDS stabilizing" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xE0C++0x3 line.long 0x0 "CTRL_CORE_CONTROL_HDMI_TX_PHY,HDMI TX PHY control" hexmask.long 0x0 0.--27. 1. " RESERVED ," bitfld.long 0x0 28. " HDMITXPHY_PD_PULLUPDET ,0x0 = Set this bit to 0x0 if RX connection is required to be detected, even when HDMI_TXPHY is powered down 0x1 = Disables the low power RX detection functionality" "0,1" textline " " bitfld.long 0x0 29. " HDMITXPHY_ENBYPASSCLK ,0x1 = Enables the HFBYPASSCLK to be used in place of the HFBITCLK" "0,1" bitfld.long 0x0 30. " HDMITXPHY_TXVALID ,0x1= Valid data on the HDMI_TXPHY input data interface , sampled on the rising edge of TMDSCLK" "0,1" textline " " bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xE1C++0x3 line.long 0x0 "CTRL_CORE_CONTROL_USB2PHYCORE,This register is related to the USB2_PHY1." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " USB2PHY_RESETDONETCLK ,resetdonetclk status from USB2PHY" "0,1" textline " " bitfld.long 0x0 6. " USBDPLL_FREQLOCK ,Status from USB DPLL" "0,1" bitfld.long 0x0 7. " USB2PHY_DATAPOLARITYN ,Data polarity 0x0 = DP functionality is on DP and DM funcationality is on DM 0x1 = DP functionality is on DM and DM functionality is on DP" "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " USB2PHY_UTMIRESETDONE ,UTMI FSM reset status 0x0 = UTMI FSMs are in reset 0x1 = UTMI FSMs are out of reset" "0,1" textline " " bitfld.long 0x0 10. " USB2PHY_RESETDONEMCLK ,OCP reset status 0x0 = OCP domain is in reset 0x1 = OCP domain is out of reset" "0,1" bitfld.long 0x0 11. " USB2PHY_MCPCMODEEN ,MCPC Mode enable 0x0 = disable MCPC mode 0x1 = enable MCPC mode" "0,1" textline " " bitfld.long 0x0 12. " USB2PHY_MCPCPUEN ,MCPC Pull up enable 0x0 = disable the MCPC pull up 0x1 = enable the 4.7K to10K pull up on receive line DP when datapolarityn is 0 and DM when datapolarityn is 1" "0,1" bitfld.long 0x0 13. " USB2PHY_CHGDETECTED ,Output of the charger detection protocol 0x0 = charger not detected 0x1 = charger detected" "0,1" textline " " bitfld.long 0x0 14. " USB2PHY_CHGDETDONE ,Status indicates that charger detection protocol is over 0x0 = charger detection protocol is not over 0x1 = charger detection protocol is over" "0,1" bitfld.long 0x0 15. " USB2PHY_RESTARTCHGDET ,restartchgdet = '1' for 1 msec cause the CD_START to reset 0x0 = Default value 0x1 = a high pulse of 1 msec causes the charger detect to restart on negative edge of restartchgdet" "0,1" textline " " bitfld.long 0x0 16. " USB2PHY_SRCONDM ,When '1' voltage source is connected to DP instead of DM 0x0 = Default value 0x1 = enable the VSRC on DM instead of DP" "0,1" bitfld.long 0x0 17. " USB2PHY_SINKONDP ,When '1' current sink is connected to DP instead of DM 0x0 = Default value 0x1 = enables the ISINK on DP instead of DM" "0,1" textline " " bitfld.long 0x0 18. " USB2PHY_DATADET ,Output of the charger detect comparator 0x0 = DM line is below 0.25V to 0.4V 0x1 = DM line is above 0.25V to 0.4V" "0,1" bitfld.long 0x0 19. " USB2PHY_CHG_DET_DP_COMP ,Output of the comparator on DP during the resistor host detect protocol 0x0 = DP line is below 0.75V to 0.95V 0x1 = DP line is above 0.75V to 0.95V" "0,1" textline " " bitfld.long 0x0 20. " USB2PHY_CHG_DET_DM_COMP ,Output of the comparator on DM during the resistor host detect protocol 0x0 = DM line is below 0.75V to 0.95V 0x1 = DM line is above 0.75V to 0.95V" "0,1" bitfld.long 0x0 21.--23. " USB2PHY_CHG_DET_STATUS ,Status of charger detection 0x0 = Wait state 0x1 = No contact 0x2 = PS/2 0x3 = Unknown error 0x4 = Dedicated charger 0x5 = HOST charger 0x6 = PC 0x7 = Interrupt" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24. " USB2PHY_CHG_ISINK_EN ,ISINK enable on DM line:Host charger case 0x0 = disable the isink on DM 0x1 = enables the ISINK (100uA) on DM line" "0,1" bitfld.long 0x0 25. " USB2PHY_CHG_VSRC_EN ,VSRC enable on DP line:Host charger case 0x0 = disable VSRC drive on DP 0x1 = drives VSRC 600mV on DP line" "0,1" textline " " bitfld.long 0x0 26. " USB2PHY_RDP_PU_CHGDET_EN ,DP Pull up control 0x0 = PU disabled 0x1 = PU enabled" "0,1" bitfld.long 0x0 27. " USB2PHY_RDM_PD_CHGDET_EN ,DM Pull down control 0x0 = PD disabled 0x1 = PD enabled" "0,1" textline " " bitfld.long 0x0 28. " USB2PHY_CHG_DET_EXT_CTL ,Charge detect external control 0x0 = charger detect internal state machine used 0x1 = charge detect statemachine is bypassed" "0,1" bitfld.long 0x0 29. " USB2PHY_GPIOMODE ,GPIO mode 0x0 = USB mode enabled 0x1 = GPIO mode enabled" "0,1" textline " " bitfld.long 0x0 30. " USB2PHY_DISCHGDET ,Disable charger detect 0x0 = charger detect function enabled 0x1 = charger detect function disabled" "0,1" bitfld.long 0x0 31. " USB2PHY_AUTORESUME_EN ,Auto resume enable 0x0 = disable autoresume 0x1 = enable autoresume" "0,1" group.byte 0xE20++0x3 line.long 0x0 "CTRL_CORE_CONTROL_HDMI_1,HDMI pads control 1" hexmask.long 0x0 0.--25. 1. " RESERVED ," bitfld.long 0x0 26. " HDMI_DDC_SCL_HSMODE ,Active-high selection for I2C High-Speed mode" "0,1" textline " " bitfld.long 0x0 27. " HDMI_DDC_SDA_HSMODE ,Active-high selection for I2C High-Speed mode" "0,1" bitfld.long 0x0 28. " HDMI_DDC_SCL_PULLUPRESX ,Active_low internal pull_up resistor enabled for hdmi_ddc_scl" "0,1" textline " " bitfld.long 0x0 29. " HDMI_DDC_SCL_GLFENB ,Active_high glitch free operation enable pin for hdmi_ddc_scl receiver" "0,1" bitfld.long 0x0 30. " HDMI_DDC_SDA_PULLUPRESX ,Active_low internal pull_up resistor enabled for hdmi_ddc_sda" "0,1" textline " " bitfld.long 0x0 31. " HDMI_DDC_SDA_GLFENB ,Active_high glitch free operation enable pin for hdmi_ddc_sda receiver" "0,1" group.byte 0xE30++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DDRCACH1_0,ddrcaCH1 control" bitfld.long 0x0 0.--1. " DDRCH1_PART6_WD ,PART6 Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 2.--4. " DDRCH1_PART6_SR ,PART6 Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 5.--7. " DDRCH1_PART6_I ,PART6 Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " DDRCH1_PART5B_WD ,PART5B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 10.--12. " DDRCH1_PART5B_SR ,PART5B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13.--15. " DDRCH1_PART5B_I ,PART5B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--17. " DDRCH1_PART5A_WD ,PART5A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 18.--20. " DDRCH1_PART5A_SR ,PART5A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 21.--23. " DDRCH1_PART5A_I ,PART5A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " DDRCH1_PART0_WD ,PART0 Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 26.--28. " DDRCH1_PART0_SR ,PART0 Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 29.--31. " DDRCH1_PART0_I ,PART0 Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" group.byte 0xE34++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DDRCACH2_0,ddrcaCH2 control" bitfld.long 0x0 0.--1. " DDRCH2_PART6_WD ,PART6 Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 2.--4. " DDRCH2_PART6_SR ,PART6 Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 5.--7. " DDRCH2_PART6_I ,PART6 Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " DDRCH2_PART5B_WD ,PART5B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 10.--12. " DDRCH2_PART5B_SR ,PART5B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13.--15. " DDRCH2_PART5B_I ,PART5B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--17. " DDRCH2_PART5A_WD ,PART5A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 18.--20. " DDRCH2_PART5A_SR ,PART5A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 21.--23. " DDRCH2_PART5A_I ,PART5A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " DDRCH2_PART0_WD ,PART0 Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 26.--28. " DDRCH2_PART0_SR ,PART0 Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 29.--31. " DDRCH2_PART0_I ,PART0 Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" group.byte 0xE38++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DDRCH1_0,DDRCH1 control 0" bitfld.long 0x0 0.--1. " DDRCH1_PART2B_WD ,PART2B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 2.--4. " DDRCH1_PART2B_SR ,PART2B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 5.--7. " DDRCH1_PART2B_I ,PART2B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " DDRCH1_PART2A_WD ,PART2A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 10.--12. " DDRCH1_PART2A_SR ,PART2A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13.--15. " DDRCH1_PART2A_I ,PART2A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--17. " DDRCH1_PART1B_WD ,PART1B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 18.--20. " DDRCH1_PART1B_SR ,PART1B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 21.--23. " DDRCH1_PART1B_I ,PART1B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " DDRCH1_PART1A_WD ,PART1A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 26.--28. " DDRCH1_PART1A_SR ,PART1A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 29.--31. " DDRCH1_PART1A_I ,PART1A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" group.byte 0xE3C++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DDRCH1_1,DDRCH1 control 1" bitfld.long 0x0 0.--1. " DDRCH1_PART4B_WD ,PART4B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 2.--4. " DDRCH1_PART4B_SR ,PART4B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 5.--7. " DDRCH1_PART4B_I ,PART4B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " DDRCH1_PART4A_WD ,PART4A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 10.--12. " DDRCH1_PART4A_SR ,PART4A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13.--15. " DDRCH1_PART4A_I ,PART4A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--17. " DDRCH1_PART3B_WD ,PART3B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 18.--20. " DDRCH1_PART3B_SR ,PART3B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 21.--23. " DDRCH1_PART3B_I ,PART3B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " DDRCH1_PART3A_WD ,PART3A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 26.--28. " DDRCH1_PART3A_SR ,PART3A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 29.--31. " DDRCH1_PART3A_I ,PART3A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" group.byte 0xE40++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DDRCH2_0,DDRCH2 control 0" bitfld.long 0x0 0.--1. " DDRCH2_PART2B_WD ,PART2B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 2.--4. " DDRCH2_PART2B_SR ,PART2B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 5.--7. " DDRCH2_PART2B_I ,PART2B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " DDRCH2_PART2A_WD ,PART2A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 10.--12. " DDRCH2_PART2A_SR ,PART2A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13.--15. " DDRCH2_PART2A_I ,PART2A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--17. " DDRCH2_PART1B_WD ,PART1B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 18.--20. " DDRCH2_PART1B_SR ,PART1B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 21.--23. " DDRCH2_PART1B_I ,PART1B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " DDRCH2_PART1A_WD ,PART1A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 26.--28. " DDRCH2_PART1A_SR ,PART1A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 29.--31. " DDRCH2_PART1A_I ,PART1A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" group.byte 0xE44++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DDRCH2_1,DDRCH2 control 1" bitfld.long 0x0 0.--1. " DDRCH2_PART4B_WD ,PART4B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 2.--4. " DDRCH2_PART4B_SR ,PART4B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 5.--7. " DDRCH2_PART4B_I ,PART4B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " DDRCH2_PART4A_WD ,PART4A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 10.--12. " DDRCH2_PART4A_SR ,PART4A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13.--15. " DDRCH2_PART4A_I ,PART4A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--17. " DDRCH2_PART3B_WD ,PART3B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 18.--20. " DDRCH2_PART3B_SR ,PART3B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 21.--23. " DDRCH2_PART3B_I ,PART3B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--25. " DDRCH2_PART3A_WD ,PART3A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 26.--28. " DDRCH2_PART3A_SR ,PART3A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 29.--31. " DDRCH2_PART3A_I ,PART3A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" group.byte 0xE48++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DDRCH1_2,CTRL_CORE_CONTROL_DDRCH1_2" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8.--9. " DDRCH1_PART7B_WD ,PART7B Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" textline " " bitfld.long 0x0 10.--12. " DDRCH1_PART7B_SR ,PART7B Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13.--15. " DDRCH1_PART7B_I ,PART7B Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--17. " DDRCH1_PART7A_WD ,PART7A Weak driver control WD[1:0] -For single-ended operation: 0x0: Pull logic is disabled 0x1: Pull-up selected 0x2: Pull-down selected 0x3: Maintain the previous output value -For differential pair operation: 0x0: Pull logic is disabled 0x1: Pull-up selected for padp, pull-down selected for padn 0x2: Pull-down selected for padp, pull-up selected for padn 0x3: Maintain the previous output value" "0,1,2,3" bitfld.long 0x0 18.--20. " DDRCH1_PART7A_SR ,PART7A Slew Rate control SR[2:0]. All 8 values are valid. 0x0: Fastest .... 0x7: Slowest" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 21.--23. " DDRCH1_PART7A_I ,PART7A Impedence control I[2:0] 0x0: Imp80 0x1: Imp60 0x2: Imp48 0x3: Imp40 0x4: Imp34 0x5: Reserved 0x6: Reserved 0x7: Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xE50++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DDRIO_0,CTRL_CORE_CONTROL_DDRIO_0" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," bitfld.long 0x0 10. " DDRCH1_VREF_DQ1_INT_EN ,Enable" "0,1" textline " " bitfld.long 0x0 11. " DDRCH1_VREF_DQ1_INT_TAP1 ,Selection for internal reference voltage drive" "0,1" bitfld.long 0x0 12. " DDRCH1_VREF_DQ1_INT_TAP0 ,Selection for internal reference voltage drive" "0,1" textline " " bitfld.long 0x0 13. " DDRCH1_VREF_DQ1_INT_CCAP1 ,Selection for coupling cap connection" "0,1" bitfld.long 0x0 14. " DDRCH1_VREF_DQ1_INT_CCAP0 ,Selection for coupling cap connection" "0,1" textline " " bitfld.long 0x0 15. " DDRCH1_VREF_DQ0_INT_EN ,Enable" "0,1" bitfld.long 0x0 16. " DDRCH1_VREF_DQ0_INT_TAP1 ,Selection for internal reference voltage drive" "0,1" textline " " bitfld.long 0x0 17. " DDRCH1_VREF_DQ0_INT_TAP0 ,Selection for internal reference voltage drive" "0,1" bitfld.long 0x0 18. " DDRCH1_VREF_DQ0_INT_CCAP1 ,Selection for coupling cap connection" "0,1" textline " " bitfld.long 0x0 19. " DDRCH1_VREF_DQ0_INT_CCAP0 ,Selection for coupling cap connection" "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0xE54++0x3 line.long 0x0 "CTRL_CORE_CONTROL_DDRIO_1,CTRL_CORE_CONTROL_DDRIO_1" hexmask.long.tbyte 0x0 0.--16. 1. " RESERVED ," bitfld.long 0x0 17. " DDRCH2_VREF_DQ1_INT_EN ,Enable" "0,1" textline " " bitfld.long 0x0 18. " DDRCH2_VREF_DQ1_INT_TAP1 ,Selection for internal reference voltage drive" "0,1" bitfld.long 0x0 19. " DDRCH2_VREF_DQ1_INT_TAP0 ,Selection for internal reference voltage drive" "0,1" textline " " bitfld.long 0x0 20. " DDRCH2_VREF_DQ1_INT_CCAP1 ,Selection for coupling cap connection" "0,1" bitfld.long 0x0 21. " DDRCH2_VREF_DQ1_INT_CCAP0 ,Selection for coupling cap connection" "0,1" textline " " bitfld.long 0x0 22. " DDRCH2_VREF_DQ0_INT_EN ,Enable" "0,1" bitfld.long 0x0 23. " DDRCH2_VREF_DQ0_INT_TAP1 ,Selection for internal reference voltage drive" "0,1" textline " " bitfld.long 0x0 24. " DDRCH2_VREF_DQ0_INT_TAP0 ,Selection for internal reference voltage drive" "0,1" bitfld.long 0x0 25. " DDRCH2_VREF_DQ0_INT_CCAP1 ,Selection for coupling cap connection" "0,1" textline " " bitfld.long 0x0 26. " DDRCH2_VREF_DQ0_INT_CCAP0 ,Selection for coupling cap connection" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xE5C++0x3 line.long 0x0 "CTRL_CORE_CONTROL_HYST_1,Register for hysteresis and impedance control of the MMC1 pads. Effective when corresponding MUXMODE field is not configured for MMC operation." hexmask.long 0x0 0.--28. 1. " RESERVED ," bitfld.long 0x0 29.--30. " SDCARD_IC ,Drive strength control for MMC1 pads In 3.3V signaling mode: 0x0: 50 Ohms Drive Strength 0x1: 33 Ohms Drive Strength 0x2: 66 Ohms Drive Strength 0x3: Reserved In 1.8V signaling mode: 0x0: 44 Ohms Drive Strength 0x1: 33 Ohms Drive Strength 0x2: 58 Ohms Drive Strength 0x3: 100 Ohms Drive Strength" "0,1,2,3" textline " " bitfld.long 0x0 31. " SDCARD_HYST ,Hysteresis control for sdcard 0x0 = Disabled 0x1 = Enabled" "0,1" group.byte 0xE68++0x3 line.long 0x0 "CTRL_CORE_CONTROL_SPARE_RW,CTRL_CORE_CONTROL_SPARE_RW" bitfld.long 0x0 0. " CORE_CONTROL_SPARE_RW_MMC1_LOOPBACK ,Selects the source of loopback clock for mmc1_clk. 0x0: Loopback clock from the I/O pad is selected 0x1: Internal loopback clock is selected" "0,1" bitfld.long 0x0 1. " CORE_CONTROL_SPARE_RW_MMC2_LOOPBACK ,Selects the source of loopback clock for mmc2_clk. 0x0: Loopback clock from the I/O pad is selected 0x1: Internal loopback clock is selected" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " CORE_CONTROL_SPARE_RW ,Spare bits" group.byte 0xE74++0x3 line.long 0x0 "CTRL_CORE_SRCOMP_NORTH_SIDE,This register is related to the USB2_PHY2." bitfld.long 0x0 0. " USB2PHY_DATAPOLARITYN ,Data polarity 0x0: DP functionality is on DP and DM funcationality is on DM 0x1: DP functionality is on DM and DM functionality is on DP" "0,1" bitfld.long 0x0 1. " USB2PHY_MCPCMODEEN ,MCPC Mode enable 0x0: disable MCPC mode 0x1: enable MCPC mode" "0,1" textline " " bitfld.long 0x0 2. " USB2PHY_MCPCPUEN ,MCPC Pull up enable 0x0: disable the MCPC pull up 0x1: enable the 4.7K to10K pull up on receive line DP when datapolarityn is 0 and DM when datapolarityn is 1" "0,1" bitfld.long 0x0 3. " USB2PHY_RESTARTCHGDET ,restartchgdet: '1' for 1 msec cause the CD_START to reset 0x0: Default value 0x1: a high pulse of 1 msec causes the charger detect to restart on negative edge of restartchgdet" "0,1" textline " " bitfld.long 0x0 4. " USB2PHY_SRCONDM ,When '1' voltage source is connected to DP instead of DM 0x0: Default value 0x1: enable the VSRC on DM instead of DP" "0,1" bitfld.long 0x0 5. " USB2PHY_SINKONDP ,When '1' current sink is connected to DP instead of DM 0x0: Default value 0x1: enables the ISINK on DP instead of DM" "0,1" textline " " bitfld.long 0x0 6. " USB2PHY_CHG_ISINK_EN ,ISINK enable on DM line: Host charger case 0x0: disable the ISINK on DM 0x1: enables the ISINK (100uA) on DM line" "0,1" bitfld.long 0x0 7. " USB2PHY_CHG_VSRC_EN ,VSRC enable on DP line: Host charger case 0x0: disable VSRC drive on DP 0x1: drives VSRC 600mV on DP line" "0,1" textline " " bitfld.long 0x0 8. " USB2PHY_RDP_PU_CHGDET_EN ,DP Pull up control 0x0: PU disabled 0x1: PU enabled" "0,1" bitfld.long 0x0 9. " USB2PHY_RDM_PD_CHGDET_EN ,DM Pull down control 0x0: PD disabled 0x1: PD enabled" "0,1" textline " " bitfld.long 0x0 10. " USB2PHY_CHG_DET_EXT_CTL ,Charge detect external control 0x0: charger detect internal state machine used 0x1: charge detect statemachine is bypassed" "0,1" bitfld.long 0x0 11. " USB2PHY_GPIOMODE ,GPIO mode 0x0: USB mode enabled 0x1: GPIO mode enabled" "0,1" textline " " bitfld.long 0x0 12. " USB2PHY_RESETDONETCLK ,resetdonetclk status from USB2_PHY2" "0,1" bitfld.long 0x0 13. " USBDPLL_FREQLOCK ,Status from USB DPLL" "0,1" textline " " bitfld.long 0x0 14. " USB2PHY_UTMIRESETDONE ,UTMI FSM reset status 0x0: UTMI FSMs are in reset 0x1: UTMI FSMs are out of reset" "0,1" bitfld.long 0x0 15. " USB2PHY_RESETDONEMCLK ,OCP reset status 0x0: OCP domain is in reset 0x1: OCP domain is out of reset" "0,1" textline " " bitfld.long 0x0 16. " USB2PHY_CHGDETECTED ,Output of the charger detection protocol 0x0: charger not detected 0x1: charger detected" "0,1" bitfld.long 0x0 17. " USB2PHY_CHGDETDONE ,Status indicates that charger detection protocol is over 0x0: charger detection protocol is not over 0x1: charger detection protocol is over" "0,1" textline " " bitfld.long 0x0 18. " USB2PHY_DATADET ,Output of the charger detect comparator 0x0: DM line is below 0.25V to 0.4V 0x1: DM line is above 0.25V to 0.4V" "0,1" bitfld.long 0x0 19. " USB2PHY_CHG_DET_DP_COMP ,Output of the comparator on DP during the resistor host detect protocol 0x0: DP line is below 0.75V to 0.95V 0x1: DP line is above 0.75V to 0.95V" "0,1" textline " " bitfld.long 0x0 20. " USB2PHY_CHG_DET_DM_COMP ,Output of the comparator on DM during the resistor host detect protocol 0x0: DM line is below 0.75V to 0.95V 0x1: DM line is above 0.75V to 0.95V" "0,1" hexmask.long.byte 0x0 21.--27. 1. " RESERVED ," textline " " bitfld.long 0x0 28. " USB2PHY_PD ,Power down the entire USB2_PHY2 (data, common module and UTMI). 0x0: Normal operation 0x1: Power down the USB2_PHY2" "0,1" bitfld.long 0x0 29. " USB2PHY_DISCHGDET ,Disable charger detect 0x0: charger detect function enabled 0x1: charger detect function disabled" "0,1" textline " " bitfld.long 0x0 30. " USB2PHY_AUTORESUME_EN ,Auto resume enable 0x0: disable autoresume 0x1: enable autoresume" "0,1" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0xE78++0x3 line.long 0x0 "CTRL_CORE_SRCOMP_SOUTH_SIDE,This register is related to the USB2_PHY2." hexmask.long.word 0x0 0.--11. 1. " RESERVED ," bitfld.long 0x0 12.--14. " USB2PHY_CHG_DET_STATUS ,Status of charger detection 0x0: Wait state 0x1: No contact 0x2: PS/2 0x3: Unknown error 0x4: Dedicated charger 0x5: HOST charger 0x6: PC 0x7: Interrupt" "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x1400++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD0,CTRL_CORE_PAD_GPMC_AD0" bitfld.long 0x0 0.--3. " GPMC_AD0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode.Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in , Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1404++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD1,CTRL_CORE_PAD_GPMC_AD1" bitfld.long 0x0 0.--3. " GPMC_AD1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1408++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD2,CTRL_CORE_PAD_GPMC_AD2" bitfld.long 0x0 0.--3. " GPMC_AD2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x140C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD3,CTRL_CORE_PAD_GPMC_AD3" bitfld.long 0x0 0.--3. " GPMC_AD3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1410++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD4,CTRL_CORE_PAD_GPMC_AD4" bitfld.long 0x0 0.--3. " GPMC_AD4_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD4_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD4_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD4_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD4_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD4_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD4_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD4_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD4_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1414++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD5,CTRL_CORE_PAD_GPMC_AD5" bitfld.long 0x0 0.--3. " GPMC_AD5_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD5_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD5_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD5_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD5_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD5_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD5_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD5_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD5_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1418++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD6,CTRL_CORE_PAD_GPMC_AD6" bitfld.long 0x0 0.--3. " GPMC_AD6_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD6_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD6_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD6_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD6_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD6_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD6_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD6_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD6_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x141C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD7,CTRL_CORE_PAD_GPMC_AD7" bitfld.long 0x0 0.--3. " GPMC_AD7_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD7_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD7_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD7_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD7_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD7_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD7_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD7_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD7_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1420++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD8,CTRL_CORE_PAD_GPMC_AD8" bitfld.long 0x0 0.--3. " GPMC_AD8_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD8_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD8_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD8_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD8_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD8_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD8_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD8_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD8_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1424++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD9,CTRL_CORE_PAD_GPMC_AD9" bitfld.long 0x0 0.--3. " GPMC_AD9_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD9_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD9_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD9_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD9_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD9_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD9_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD9_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD9_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1428++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD10,CTRL_CORE_PAD_GPMC_AD10" bitfld.long 0x0 0.--3. " GPMC_AD10_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD10_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD10_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD10_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD10_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD10_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD10_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD10_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD10_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x142C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD11,CTRL_CORE_PAD_GPMC_AD11" bitfld.long 0x0 0.--3. " GPMC_AD11_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD11_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD11_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD11_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD11_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD11_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD11_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD11_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD11_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1430++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD12,CTRL_CORE_PAD_GPMC_AD12" bitfld.long 0x0 0.--3. " GPMC_AD12_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD12_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD12_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD12_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD12_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD12_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD12_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD12_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD12_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1434++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD13,CTRL_CORE_PAD_GPMC_AD13" bitfld.long 0x0 0.--3. " GPMC_AD13_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD13_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD13_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD13_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD13_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD13_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD13_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD13_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD13_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1438++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD14,CTRL_CORE_PAD_GPMC_AD14" bitfld.long 0x0 0.--3. " GPMC_AD14_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD14_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD14_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD14_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD14_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD14_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD14_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD14_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD14_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x143C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_AD15,CTRL_CORE_PAD_GPMC_AD15" bitfld.long 0x0 0.--3. " GPMC_AD15_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_AD15_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_AD15_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_AD15_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_AD15_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_AD15_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_AD15_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_AD15_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_AD15_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1440++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A0,CTRL_CORE_PAD_GPMC_A0" bitfld.long 0x0 0.--3. " GPMC_A0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1444++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A1,CTRL_CORE_PAD_GPMC_A1" bitfld.long 0x0 0.--3. " GPMC_A1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1448++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A2,CTRL_CORE_PAD_GPMC_A2" bitfld.long 0x0 0.--3. " GPMC_A2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x144C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A3,CTRL_CORE_PAD_GPMC_A3" bitfld.long 0x0 0.--3. " GPMC_A3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1450++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A4,CTRL_CORE_PAD_GPMC_A4" bitfld.long 0x0 0.--3. " GPMC_A4_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A4_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A4_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A4_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A4_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A4_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A4_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A4_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A4_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1454++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A5,CTRL_CORE_PAD_GPMC_A5" bitfld.long 0x0 0.--3. " GPMC_A5_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A5_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A5_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A5_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A5_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A5_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A5_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A5_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A5_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1458++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A6,CTRL_CORE_PAD_GPMC_A6" bitfld.long 0x0 0.--3. " GPMC_A6_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A6_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A6_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A6_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A6_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A6_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A6_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A6_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A6_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x145C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A7,CTRL_CORE_PAD_GPMC_A7" bitfld.long 0x0 0.--3. " GPMC_A7_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A7_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A7_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A7_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A7_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A7_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A7_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A7_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A7_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1460++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A8,CTRL_CORE_PAD_GPMC_A8" bitfld.long 0x0 0.--3. " GPMC_A8_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A8_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A8_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A8_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A8_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A8_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A8_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A8_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A8_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1464++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A9,CTRL_CORE_PAD_GPMC_A9" bitfld.long 0x0 0.--3. " GPMC_A9_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A9_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A9_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A9_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A9_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A9_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A9_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A9_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A9_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1468++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A10,CTRL_CORE_PAD_GPMC_A10" bitfld.long 0x0 0.--3. " GPMC_A10_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A10_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A10_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A10_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A10_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A10_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A10_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A10_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A10_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x146C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A11,CTRL_CORE_PAD_GPMC_A11" bitfld.long 0x0 0.--3. " GPMC_A11_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A11_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A11_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A11_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A11_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A11_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A11_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A11_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A11_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1470++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A12,CTRL_CORE_PAD_GPMC_A12" bitfld.long 0x0 0.--3. " GPMC_A12_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A12_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A12_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A12_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A12_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A12_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A12_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A12_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A12_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1474++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A13,CTRL_CORE_PAD_GPMC_A13" bitfld.long 0x0 0.--3. " GPMC_A13_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A13_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A13_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A13_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A13_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A13_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A13_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A13_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A13_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1478++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A14,CTRL_CORE_PAD_GPMC_A14" bitfld.long 0x0 0.--3. " GPMC_A14_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A14_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A14_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A14_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A14_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A14_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A14_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A14_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A14_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x147C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A15,CTRL_CORE_PAD_GPMC_A15" bitfld.long 0x0 0.--3. " GPMC_A15_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A15_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A15_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A15_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A15_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A15_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A15_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A15_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A15_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1480++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A16,CTRL_CORE_PAD_GPMC_A16" bitfld.long 0x0 0.--3. " GPMC_A16_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A16_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A16_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A16_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A16_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A16_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A16_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A16_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A16_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1484++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A17,CTRL_CORE_PAD_GPMC_A17" bitfld.long 0x0 0.--3. " GPMC_A17_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A17_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A17_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A17_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A17_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A17_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A17_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A17_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A17_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1488++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A18,CTRL_CORE_PAD_GPMC_A18" bitfld.long 0x0 0.--3. " GPMC_A18_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A18_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A18_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A18_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A18_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A18_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A18_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A18_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A18_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x148C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A19,CTRL_CORE_PAD_GPMC_A19" bitfld.long 0x0 0.--3. " GPMC_A19_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A19_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A19_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A19_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A19_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A19_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A19_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A19_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A19_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1490++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A20,CTRL_CORE_PAD_GPMC_A20" bitfld.long 0x0 0.--3. " GPMC_A20_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A20_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A20_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A20_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A20_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A20_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A20_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A20_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A20_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1494++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A21,CTRL_CORE_PAD_GPMC_A21" bitfld.long 0x0 0.--3. " GPMC_A21_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A21_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A21_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A21_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A21_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A21_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A21_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A21_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A21_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1498++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A22,CTRL_CORE_PAD_GPMC_A22" bitfld.long 0x0 0.--3. " GPMC_A22_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A22_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A22_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A22_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A22_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A22_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A22_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A22_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A22_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x149C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A23,CTRL_CORE_PAD_GPMC_A23" bitfld.long 0x0 0.--3. " GPMC_A23_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A23_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A23_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A23_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A23_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A23_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A23_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A23_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A23_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14A0++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A24,CTRL_CORE_PAD_GPMC_A24" bitfld.long 0x0 0.--3. " GPMC_A24_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A24_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A24_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A24_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A24_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A24_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A24_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A24_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A24_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14A4++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A25,CTRL_CORE_PAD_GPMC_A25" bitfld.long 0x0 0.--3. " GPMC_A25_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A25_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A25_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A25_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A25_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A25_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A25_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A25_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A25_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14A8++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A26,CTRL_CORE_PAD_GPMC_A26" bitfld.long 0x0 0.--3. " GPMC_A26_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A26_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A26_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A26_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A26_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A26_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A26_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A26_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A26_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14AC++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_A27,CTRL_CORE_PAD_GPMC_A27" bitfld.long 0x0 0.--3. " GPMC_A27_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_A27_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_A27_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_A27_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_A27_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A27_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_A27_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_A27_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_A27_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14B0++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_CS1,CTRL_CORE_PAD_GPMC_CS1" bitfld.long 0x0 0.--3. " GPMC_CS1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_CS1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_CS1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_CS1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_CS1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_CS1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_CS1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_CS1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_CS1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14B4++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_CS0,CTRL_CORE_PAD_GPMC_CS0" bitfld.long 0x0 0.--3. " GPMC_CS0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_CS0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_CS0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_CS0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_CS0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_CS0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_CS0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_CS0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_CS0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14B8++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_CS2,CTRL_CORE_PAD_GPMC_CS2" bitfld.long 0x0 0.--3. " GPMC_CS2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_CS2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_CS2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_CS2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_CS2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_CS2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_CS2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_CS2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_CS2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14BC++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_CS3,CTRL_CORE_PAD_GPMC_CS3" bitfld.long 0x0 0.--3. " GPMC_CS3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_CS3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_CS3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_CS3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_CS3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_CS3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_CS3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_CS3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_CS3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14C0++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_CLK,CTRL_CORE_PAD_GPMC_CLK" bitfld.long 0x0 0.--3. " GPMC_CLK_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_CLK_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_CLK_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_CLK_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_CLK_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_CLK_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_CLK_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_CLK_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_CLK_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14C4++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_ADVN_ALE,CTRL_CORE_PAD_GPMC_ADVN_ALE" bitfld.long 0x0 0.--3. " GPMC_ADVN_ALE_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_ADVN_ALE_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_ADVN_ALE_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_ADVN_ALE_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_ADVN_ALE_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_ADVN_ALE_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_ADVN_ALE_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_ADVN_ALE_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_ADVN_ALE_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14C8++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_OEN_REN,CTRL_CORE_PAD_GPMC_OEN_REN" bitfld.long 0x0 0.--3. " GPMC_OEN_REN_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_OEN_REN_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_OEN_REN_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_OEN_REN_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_OEN_REN_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_OEN_REN_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_OEN_REN_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_OEN_REN_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_OEN_REN_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14CC++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_WEN,CTRL_CORE_PAD_GPMC_WEN" bitfld.long 0x0 0.--3. " GPMC_WEN_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_WEN_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_WEN_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_WEN_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_WEN_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_WEN_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_WEN_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_WEN_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_WEN_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14D0++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_BEN0,CTRL_CORE_PAD_GPMC_BEN0" bitfld.long 0x0 0.--3. " GPMC_BEN0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_BEN0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_BEN0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_BEN0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_BEN0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_BEN0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_BEN0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_BEN0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_BEN0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14D4++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_BEN1,CTRL_CORE_PAD_GPMC_BEN1" bitfld.long 0x0 0.--3. " GPMC_BEN1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_BEN1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_BEN1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_BEN1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_BEN1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_BEN1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_BEN1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_BEN1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_BEN1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14D8++0x3 line.long 0x0 "CTRL_CORE_PAD_GPMC_WAIT0,CTRL_CORE_PAD_GPMC_WAIT0" bitfld.long 0x0 0.--3. " GPMC_WAIT0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPMC_WAIT0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPMC_WAIT0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPMC_WAIT0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPMC_WAIT0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_WAIT0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPMC_WAIT0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPMC_WAIT0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPMC_WAIT0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14DC++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_CLK0,CTRL_CORE_PAD_VIN1A_CLK0" bitfld.long 0x0 0.--3. " VIN1A_CLK0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_CLK0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_CLK0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_CLK0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_CLK0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_CLK0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_CLK0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_CLK0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_CLK0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14E0++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1B_CLK1,CTRL_CORE_PAD_VIN1B_CLK1" bitfld.long 0x0 0.--3. " VIN1B_CLK1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1B_CLK1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1B_CLK1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1B_CLK1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1B_CLK1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1B_CLK1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1B_CLK1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1B_CLK1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1B_CLK1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14E4++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_DE0,CTRL_CORE_PAD_VIN1A_DE0" bitfld.long 0x0 0.--3. " VIN1A_DE0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_DE0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_DE0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_DE0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_DE0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_DE0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_DE0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_DE0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_DE0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14E8++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_FLD0,CTRL_CORE_PAD_VIN1A_FLD0" bitfld.long 0x0 0.--3. " VIN1A_FLD0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_FLD0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_FLD0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_FLD0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_FLD0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_FLD0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_FLD0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_FLD0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_FLD0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14EC++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_HSYNC0,CTRL_CORE_PAD_VIN1A_HSYNC0" bitfld.long 0x0 0.--3. " VIN1A_HSYNC0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_HSYNC0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_HSYNC0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_HSYNC0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_HSYNC0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_HSYNC0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_HSYNC0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_HSYNC0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_HSYNC0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14F0++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_VSYNC0,CTRL_CORE_PAD_VIN1A_VSYNC0" bitfld.long 0x0 0.--3. " VIN1A_VSYNC0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_VSYNC0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_VSYNC0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_VSYNC0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_VSYNC0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_VSYNC0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_VSYNC0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_VSYNC0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_VSYNC0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14F4++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D0,CTRL_CORE_PAD_VIN1A_D0" bitfld.long 0x0 0.--3. " VIN1A_D0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14F8++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D1,CTRL_CORE_PAD_VIN1A_D1" bitfld.long 0x0 0.--3. " VIN1A_D1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x14FC++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D2,CTRL_CORE_PAD_VIN1A_D2" bitfld.long 0x0 0.--3. " VIN1A_D2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1500++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D3,CTRL_CORE_PAD_VIN1A_D3" bitfld.long 0x0 0.--3. " VIN1A_D3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1504++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D4,CTRL_CORE_PAD_VIN1A_D4" bitfld.long 0x0 0.--3. " VIN1A_D4_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D4_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D4_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D4_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D4_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D4_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D4_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D4_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D4_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1508++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D5,CTRL_CORE_PAD_VIN1A_D5" bitfld.long 0x0 0.--3. " VIN1A_D5_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D5_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D5_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D5_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D5_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D5_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D5_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D5_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D5_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x150C++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D6,CTRL_CORE_PAD_VIN1A_D6" bitfld.long 0x0 0.--3. " VIN1A_D6_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D6_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D6_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D6_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D6_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D6_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D6_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D6_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D6_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1510++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D7,CTRL_CORE_PAD_VIN1A_D7" bitfld.long 0x0 0.--3. " VIN1A_D7_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D7_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D7_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D7_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D7_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D7_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D7_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D7_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D7_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1514++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D8,CTRL_CORE_PAD_VIN1A_D8" bitfld.long 0x0 0.--3. " VIN1A_D8_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D8_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D8_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D8_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D8_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D8_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D8_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D8_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D8_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1518++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D9,CTRL_CORE_PAD_VIN1A_D9" bitfld.long 0x0 0.--3. " VIN1A_D9_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D9_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D9_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D9_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D9_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D9_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D9_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D9_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D9_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x151C++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D10,CTRL_CORE_PAD_VIN1A_D10" bitfld.long 0x0 0.--3. " VIN1A_D10_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D10_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D10_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D10_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D10_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D10_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D10_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D10_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D10_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1520++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D11,CTRL_CORE_PAD_VIN1A_D11" bitfld.long 0x0 0.--3. " VIN1A_D11_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D11_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D11_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D11_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D11_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D11_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D11_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D11_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D11_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1524++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D12,CTRL_CORE_PAD_VIN1A_D12" bitfld.long 0x0 0.--3. " VIN1A_D12_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D12_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D12_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D12_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D12_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D12_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D12_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D12_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D12_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1528++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D13,CTRL_CORE_PAD_VIN1A_D13" bitfld.long 0x0 0.--3. " VIN1A_D13_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D13_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D13_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D13_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D13_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D13_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D13_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D13_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D13_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x152C++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D14,CTRL_CORE_PAD_VIN1A_D14" bitfld.long 0x0 0.--3. " VIN1A_D14_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D14_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D14_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D14_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D14_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D14_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D14_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D14_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D14_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1530++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D15,CTRL_CORE_PAD_VIN1A_D15" bitfld.long 0x0 0.--3. " VIN1A_D15_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D15_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D15_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D15_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D15_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D15_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D15_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D15_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D15_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1534++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D16,CTRL_CORE_PAD_VIN1A_D16" bitfld.long 0x0 0.--3. " VIN1A_D16_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D16_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D16_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D16_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D16_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D16_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D16_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D16_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D16_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1538++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D17,CTRL_CORE_PAD_VIN1A_D17" bitfld.long 0x0 0.--3. " VIN1A_D17_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D17_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D17_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D17_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D17_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D17_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D17_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D17_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D17_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x153C++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D18,CTRL_CORE_PAD_VIN1A_D18" bitfld.long 0x0 0.--3. " VIN1A_D18_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D18_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D18_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D18_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D18_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D18_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D18_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D18_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D18_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1540++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D19,CTRL_CORE_PAD_VIN1A_D19" bitfld.long 0x0 0.--3. " VIN1A_D19_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D19_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D19_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D19_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D19_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D19_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D19_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D19_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D19_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1544++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D20,CTRL_CORE_PAD_VIN1A_D20" bitfld.long 0x0 0.--3. " VIN1A_D20_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D20_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D20_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D20_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D20_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D20_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D20_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D20_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D20_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1548++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D21,CTRL_CORE_PAD_VIN1A_D21" bitfld.long 0x0 0.--3. " VIN1A_D21_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D21_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D21_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D21_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D21_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D21_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D21_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D21_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D21_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x154C++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D22,CTRL_CORE_PAD_VIN1A_D22" bitfld.long 0x0 0.--3. " VIN1A_D22_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D22_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D22_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D22_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D22_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D22_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D22_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D22_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D22_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1550++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN1A_D23,CTRL_CORE_PAD_VIN1A_D23" bitfld.long 0x0 0.--3. " VIN1A_D23_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN1A_D23_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN1A_D23_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN1A_D23_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN1A_D23_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D23_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN1A_D23_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN1A_D23_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN1A_D23_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1554++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_CLK0,CTRL_CORE_PAD_VIN2A_CLK0" bitfld.long 0x0 0.--3. " VIN2A_CLK0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_CLK0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_CLK0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_CLK0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_CLK0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_CLK0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_CLK0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_CLK0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_CLK0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1558++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_DE0,CTRL_CORE_PAD_VIN2A_DE0" bitfld.long 0x0 0.--3. " VIN2A_DE0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_DE0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_DE0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_DE0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_DE0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_DE0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_DE0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_DE0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_DE0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x155C++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_FLD0,CTRL_CORE_PAD_VIN2A_FLD0" bitfld.long 0x0 0.--3. " VIN2A_FLD0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_FLD0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_FLD0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_FLD0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_FLD0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_FLD0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_FLD0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_FLD0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_FLD0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1560++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_HSYNC0,CTRL_CORE_PAD_VIN2A_HSYNC0" bitfld.long 0x0 0.--3. " VIN2A_HSYNC0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_HSYNC0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_HSYNC0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_HSYNC0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_HSYNC0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_HSYNC0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_HSYNC0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_HSYNC0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_HSYNC0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1564++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_VSYNC0,CTRL_CORE_PAD_VIN2A_VSYNC0" bitfld.long 0x0 0.--3. " VIN2A_VSYNC0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_VSYNC0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_VSYNC0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_VSYNC0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_VSYNC0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_VSYNC0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_VSYNC0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_VSYNC0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_VSYNC0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1568++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D0,CTRL_CORE_PAD_VIN2A_D0" bitfld.long 0x0 0.--3. " VIN2A_D0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x156C++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D1,CTRL_CORE_PAD_VIN2A_D1" bitfld.long 0x0 0.--3. " VIN2A_D1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1570++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D2,CTRL_CORE_PAD_VIN2A_D2" bitfld.long 0x0 0.--3. " VIN2A_D2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1574++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D3,CTRL_CORE_PAD_VIN2A_D3" bitfld.long 0x0 0.--3. " VIN2A_D3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1578++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D4,CTRL_CORE_PAD_VIN2A_D4" bitfld.long 0x0 0.--3. " VIN2A_D4_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D4_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D4_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D4_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D4_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D4_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D4_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D4_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D4_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x157C++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D5,CTRL_CORE_PAD_VIN2A_D5" bitfld.long 0x0 0.--3. " VIN2A_D5_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D5_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D5_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D5_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D5_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D5_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D5_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D5_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D5_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1580++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D6,CTRL_CORE_PAD_VIN2A_D6" bitfld.long 0x0 0.--3. " VIN2A_D6_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D6_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D6_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D6_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D6_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D6_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D6_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D6_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D6_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1584++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D7,CTRL_CORE_PAD_VIN2A_D7" bitfld.long 0x0 0.--3. " VIN2A_D7_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D7_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D7_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D7_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D7_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D7_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D7_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D7_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D7_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1588++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D8,CTRL_CORE_PAD_VIN2A_D8" bitfld.long 0x0 0.--3. " VIN2A_D8_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D8_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D8_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D8_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D8_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D8_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D8_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D8_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D8_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x158C++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D9,CTRL_CORE_PAD_VIN2A_D9" bitfld.long 0x0 0.--3. " VIN2A_D9_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D9_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D9_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D9_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D9_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D9_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D9_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D9_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D9_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1590++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D10,CTRL_CORE_PAD_VIN2A_D10" bitfld.long 0x0 0.--3. " VIN2A_D10_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D10_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D10_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D10_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D10_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D10_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D10_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D10_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D10_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1594++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D11,CTRL_CORE_PAD_VIN2A_D11" bitfld.long 0x0 0.--3. " VIN2A_D11_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D11_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D11_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D11_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D11_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D11_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D11_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D11_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D11_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1598++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D12,CTRL_CORE_PAD_VIN2A_D12" bitfld.long 0x0 0.--3. " VIN2A_D12_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D12_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D12_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D12_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D12_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D12_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D12_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D12_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D12_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x159C++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D13,CTRL_CORE_PAD_VIN2A_D13" bitfld.long 0x0 0.--3. " VIN2A_D13_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D13_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D13_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D13_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D13_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D13_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D13_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D13_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D13_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15A0++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D14,CTRL_CORE_PAD_VIN2A_D14" bitfld.long 0x0 0.--3. " VIN2A_D14_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D14_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D14_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D14_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D14_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D14_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D14_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D14_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D14_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15A4++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D15,CTRL_CORE_PAD_VIN2A_D15" bitfld.long 0x0 0.--3. " VIN2A_D15_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D15_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D15_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D15_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D15_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D15_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D15_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D15_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D15_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15A8++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D16,CTRL_CORE_PAD_VIN2A_D16" bitfld.long 0x0 0.--3. " VIN2A_D16_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D16_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D16_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D16_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D16_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D16_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D16_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D16_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D16_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15AC++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D17,CTRL_CORE_PAD_VIN2A_D17" bitfld.long 0x0 0.--3. " VIN2A_D17_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D17_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D17_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D17_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D17_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D17_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D17_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D17_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D17_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15B0++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D18,CTRL_CORE_PAD_VIN2A_D18" bitfld.long 0x0 0.--3. " VIN2A_D18_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D18_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D18_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D18_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D18_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D18_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D18_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D18_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D18_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15B4++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D19,CTRL_CORE_PAD_VIN2A_D19" bitfld.long 0x0 0.--3. " VIN2A_D19_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D19_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D19_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D19_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D19_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D19_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D19_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D19_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D19_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15B8++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D20,CTRL_CORE_PAD_VIN2A_D20" bitfld.long 0x0 0.--3. " VIN2A_D20_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D20_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D20_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D20_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D20_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D20_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D20_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D20_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D20_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15BC++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D21,CTRL_CORE_PAD_VIN2A_D21" bitfld.long 0x0 0.--3. " VIN2A_D21_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D21_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D21_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D21_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D21_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D21_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D21_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D21_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D21_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15C0++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D22,CTRL_CORE_PAD_VIN2A_D22" bitfld.long 0x0 0.--3. " VIN2A_D22_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D22_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D22_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D22_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D22_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D22_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D22_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D22_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D22_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15C4++0x3 line.long 0x0 "CTRL_CORE_PAD_VIN2A_D23,CTRL_CORE_PAD_VIN2A_D23" bitfld.long 0x0 0.--3. " VIN2A_D23_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VIN2A_D23_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VIN2A_D23_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VIN2A_D23_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VIN2A_D23_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VIN2A_D23_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VIN2A_D23_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VIN2A_D23_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VIN2A_D23_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15C8++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_CLK,CTRL_CORE_PAD_VOUT1_CLK" bitfld.long 0x0 0.--3. " VOUT1_CLK_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_CLK_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_CLK_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_CLK_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_CLK_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_CLK_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_CLK_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_CLK_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_CLK_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15CC++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_DE,CTRL_CORE_PAD_VOUT1_DE" bitfld.long 0x0 0.--3. " VOUT1_DE_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_DE_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_DE_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_DE_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_DE_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_DE_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_DE_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_DE_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_DE_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15D0++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_FLD,CTRL_CORE_PAD_VOUT1_FLD" bitfld.long 0x0 0.--3. " VOUT1_FLD_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_FLD_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_FLD_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_FLD_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_FLD_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_FLD_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_FLD_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_FLD_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_FLD_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15D4++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_HSYNC,CTRL_CORE_PAD_VOUT1_HSYNC" bitfld.long 0x0 0.--3. " VOUT1_HSYNC_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_HSYNC_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_HSYNC_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_HSYNC_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_HSYNC_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_HSYNC_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_HSYNC_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_HSYNC_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_HSYNC_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15D8++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_VSYNC,CTRL_CORE_PAD_VOUT1_VSYNC" bitfld.long 0x0 0.--3. " VOUT1_VSYNC_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_VSYNC_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_VSYNC_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_VSYNC_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_VSYNC_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_VSYNC_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_VSYNC_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_VSYNC_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_VSYNC_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15DC++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D0,CTRL_CORE_PAD_VOUT1_D0" bitfld.long 0x0 0.--3. " VOUT1_D0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15E0++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D1,CTRL_CORE_PAD_VOUT1_D1" bitfld.long 0x0 0.--3. " VOUT1_D1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15E4++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D2,CTRL_CORE_PAD_VOUT1_D2" bitfld.long 0x0 0.--3. " VOUT1_D2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15E8++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D3,CTRL_CORE_PAD_VOUT1_D3" bitfld.long 0x0 0.--3. " VOUT1_D3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15EC++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D4,CTRL_CORE_PAD_VOUT1_D4" bitfld.long 0x0 0.--3. " VOUT1_D4_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D4_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D4_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D4_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D4_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D4_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D4_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D4_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D4_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15F0++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D5,CTRL_CORE_PAD_VOUT1_D5" bitfld.long 0x0 0.--3. " VOUT1_D5_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D5_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D5_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D5_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D5_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D5_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D5_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D5_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D5_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15F4++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D6,CTRL_CORE_PAD_VOUT1_D6" bitfld.long 0x0 0.--3. " VOUT1_D6_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D6_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D6_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D6_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D6_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D6_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D6_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D6_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D6_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15F8++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D7,CTRL_CORE_PAD_VOUT1_D7" bitfld.long 0x0 0.--3. " VOUT1_D7_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D7_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D7_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D7_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D7_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D7_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D7_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D7_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D7_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x15FC++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D8,CTRL_CORE_PAD_VOUT1_D8" bitfld.long 0x0 0.--3. " VOUT1_D8_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D8_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D8_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D8_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D8_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D8_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D8_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D8_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D8_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1600++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D9,CTRL_CORE_PAD_VOUT1_D9" bitfld.long 0x0 0.--3. " VOUT1_D9_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D9_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D9_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D9_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D9_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D9_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D9_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D9_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D9_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1604++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D10,CTRL_CORE_PAD_VOUT1_D10" bitfld.long 0x0 0.--3. " VOUT1_D10_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D10_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D10_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D10_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D10_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D10_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D10_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D10_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D10_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1608++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D11,CTRL_CORE_PAD_VOUT1_D11" bitfld.long 0x0 0.--3. " VOUT1_D11_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D11_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D11_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D11_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D11_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D11_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D11_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D11_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D11_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x160C++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D12,CTRL_CORE_PAD_VOUT1_D12" bitfld.long 0x0 0.--3. " VOUT1_D12_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D12_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D12_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D12_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D12_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D12_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D12_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D12_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D12_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1610++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D13,CTRL_CORE_PAD_VOUT1_D13" bitfld.long 0x0 0.--3. " VOUT1_D13_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D13_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D13_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D13_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D13_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D13_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D13_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D13_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D13_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1614++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D14,CTRL_CORE_PAD_VOUT1_D14" bitfld.long 0x0 0.--3. " VOUT1_D14_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D14_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D14_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D14_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D14_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D14_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D14_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D14_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D14_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1618++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D15,CTRL_CORE_PAD_VOUT1_D15" bitfld.long 0x0 0.--3. " VOUT1_D15_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D15_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D15_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D15_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D15_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D15_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D15_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D15_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D15_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x161C++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D16,CTRL_CORE_PAD_VOUT1_D16" bitfld.long 0x0 0.--3. " VOUT1_D16_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D16_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D16_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D16_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D16_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D16_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D16_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D16_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D16_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1620++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D17,CTRL_CORE_PAD_VOUT1_D17" bitfld.long 0x0 0.--3. " VOUT1_D17_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D17_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D17_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D17_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D17_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D17_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D17_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D17_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D17_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1624++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D18,CTRL_CORE_PAD_VOUT1_D18" bitfld.long 0x0 0.--3. " VOUT1_D18_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D18_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D18_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D18_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D18_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D18_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D18_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D18_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D18_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1628++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D19,CTRL_CORE_PAD_VOUT1_D19" bitfld.long 0x0 0.--3. " VOUT1_D19_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D19_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D19_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D19_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D19_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D19_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D19_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D19_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D19_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x162C++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D20,CTRL_CORE_PAD_VOUT1_D20" bitfld.long 0x0 0.--3. " VOUT1_D20_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D20_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D20_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D20_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D20_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D20_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D20_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D20_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D20_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1630++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D21,CTRL_CORE_PAD_VOUT1_D21" bitfld.long 0x0 0.--3. " VOUT1_D21_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D21_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D21_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D21_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D21_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D21_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D21_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D21_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D21_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1634++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D22,CTRL_CORE_PAD_VOUT1_D22" bitfld.long 0x0 0.--3. " VOUT1_D22_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D22_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D22_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D22_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D22_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D22_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D22_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D22_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D22_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1638++0x3 line.long 0x0 "CTRL_CORE_PAD_VOUT1_D23,CTRL_CORE_PAD_VOUT1_D23" bitfld.long 0x0 0.--3. " VOUT1_D23_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " VOUT1_D23_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " VOUT1_D23_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " VOUT1_D23_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " VOUT1_D23_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_D23_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " VOUT1_D23_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " VOUT1_D23_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " VOUT1_D23_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x163C++0x3 line.long 0x0 "CTRL_CORE_PAD_MDIO_MCLK,CTRL_CORE_PAD_MDIO_MCLK" bitfld.long 0x0 0.--3. " MDIO_MCLK_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MDIO_MCLK_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MDIO_MCLK_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MDIO_MCLK_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MDIO_MCLK_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MDIO_MCLK_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MDIO_MCLK_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MDIO_MCLK_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MDIO_MCLK_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1640++0x3 line.long 0x0 "CTRL_CORE_PAD_MDIO_D,CTRL_CORE_PAD_MDIO_D" bitfld.long 0x0 0.--3. " MDIO_D_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MDIO_D_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MDIO_D_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MDIO_D_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MDIO_D_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MDIO_D_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MDIO_D_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MDIO_D_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MDIO_D_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1644++0x3 line.long 0x0 "CTRL_CORE_PAD_RMII_MHZ_50_CLK,CTRL_CORE_PAD_RMII_MHZ_50_CLK" bitfld.long 0x0 0.--3. " RMII_MHZ_50_CLK_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RMII_MHZ_50_CLK_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RMII_MHZ_50_CLK_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RMII_MHZ_50_CLK_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RMII_MHZ_50_CLK_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RMII_MHZ_50_CLK_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RMII_MHZ_50_CLK_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RMII_MHZ_50_CLK_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RMII_MHZ_50_CLK_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1648++0x3 line.long 0x0 "CTRL_CORE_PAD_UART3_RXD,CTRL_CORE_PAD_UART3_RXD" bitfld.long 0x0 0.--3. " UART3_RXD_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " UART3_RXD_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " UART3_RXD_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " UART3_RXD_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " UART3_RXD_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " UART3_RXD_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " UART3_RXD_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " UART3_RXD_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " UART3_RXD_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x164C++0x3 line.long 0x0 "CTRL_CORE_PAD_UART3_TXD,CTRL_CORE_PAD_UART3_TXD" bitfld.long 0x0 0.--3. " UART3_TXD_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " UART3_TXD_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " UART3_TXD_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " UART3_TXD_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " UART3_TXD_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " UART3_TXD_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " UART3_TXD_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " UART3_TXD_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " UART3_TXD_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1650++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_TXC,CTRL_CORE_PAD_RGMII0_TXC" bitfld.long 0x0 0.--3. " RGMII0_TXC_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_TXC_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_TXC_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_TXC_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_TXC_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_TXC_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_TXC_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_TXC_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_TXC_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1654++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_TXCTL,CTRL_CORE_PAD_RGMII0_TXCTL" bitfld.long 0x0 0.--3. " RGMII0_TXCTL_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_TXCTL_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_TXCTL_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_TXCTL_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_TXCTL_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_TXCTL_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_TXCTL_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_TXCTL_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_TXCTL_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1658++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_TXD3,CTRL_CORE_PAD_RGMII0_TXD3" bitfld.long 0x0 0.--3. " RGMII0_TXD3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_TXD3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_TXD3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_TXD3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_TXD3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_TXD3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_TXD3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_TXD3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_TXD3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x165C++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_TXD2,CTRL_CORE_PAD_RGMII0_TXD2" bitfld.long 0x0 0.--3. " RGMII0_TXD2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_TXD2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_TXD2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_TXD2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_TXD2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_TXD2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_TXD2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_TXD2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_TXD2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1660++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_TXD1,CTRL_CORE_PAD_RGMII0_TXD1" bitfld.long 0x0 0.--3. " RGMII0_TXD1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_TXD1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_TXD1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_TXD1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_TXD1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_TXD1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_TXD1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_TXD1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_TXD1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1664++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_TXD0,CTRL_CORE_PAD_RGMII0_TXD0" bitfld.long 0x0 0.--3. " RGMII0_TXD0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_TXD0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_TXD0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_TXD0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_TXD0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_TXD0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_TXD0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_TXD0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_TXD0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1668++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_RXC,CTRL_CORE_PAD_RGMII0_RXC" bitfld.long 0x0 0.--3. " RGMII0_RXC_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_RXC_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_RXC_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_RXC_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_RXC_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_RXC_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_RXC_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_RXC_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_RXC_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x166C++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_RXCTL,CTRL_CORE_PAD_RGMII0_RXCTL" bitfld.long 0x0 0.--3. " RGMII0_RXCTL_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_RXCTL_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_RXCTL_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_RXCTL_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_RXCTL_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_RXCTL_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_RXCTL_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_RXCTL_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_RXCTL_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1670++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_RXD3,CTRL_CORE_PAD_RGMII0_RXD3" bitfld.long 0x0 0.--3. " RGMII0_RXD3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_RXD3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_RXD3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_RXD3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_RXD3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_RXD3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_RXD3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_RXD3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_RXD3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1674++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_RXD2,CTRL_CORE_PAD_RGMII0_RXD2" bitfld.long 0x0 0.--3. " RGMII0_RXD2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_RXD2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_RXD2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_RXD2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_RXD2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_RXD2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_RXD2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_RXD2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_RXD2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1678++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_RXD1,CTRL_CORE_PAD_RGMII0_RXD1" bitfld.long 0x0 0.--3. " RGMII0_RXD1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_RXD1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_RXD1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_RXD1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_RXD1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_RXD1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_RXD1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_RXD1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_RXD1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x167C++0x3 line.long 0x0 "CTRL_CORE_PAD_RGMII0_RXD0,CTRL_CORE_PAD_RGMII0_RXD0" bitfld.long 0x0 0.--3. " RGMII0_RXD0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RGMII0_RXD0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RGMII0_RXD0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RGMII0_RXD0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RGMII0_RXD0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RGMII0_RXD0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RGMII0_RXD0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RGMII0_RXD0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RGMII0_RXD0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1680++0x3 line.long 0x0 "CTRL_CORE_PAD_USB1_DRVVBUS,CTRL_CORE_PAD_USB1_DRVVBUS" bitfld.long 0x0 0.--3. " USB1_DRVVBUS_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " USB1_DRVVBUS_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " USB1_DRVVBUS_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " USB1_DRVVBUS_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " USB1_DRVVBUS_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " USB1_DRVVBUS_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " USB1_DRVVBUS_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " USB1_DRVVBUS_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " USB1_DRVVBUS_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1684++0x3 line.long 0x0 "CTRL_CORE_PAD_USB2_DRVVBUS,CTRL_CORE_PAD_USB2_DRVVBUS" bitfld.long 0x0 0.--3. " USB2_DRVVBUS_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " USB2_DRVVBUS_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " USB2_DRVVBUS_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " USB2_DRVVBUS_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " USB2_DRVVBUS_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " USB2_DRVVBUS_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " USB2_DRVVBUS_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " USB2_DRVVBUS_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " USB2_DRVVBUS_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1688++0x3 line.long 0x0 "CTRL_CORE_PAD_GPIO6_14,CTRL_CORE_PAD_GPIO6_14" bitfld.long 0x0 0.--3. " GPIO6_14_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPIO6_14_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPIO6_14_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPIO6_14_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPIO6_14_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPIO6_14_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPIO6_14_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPIO6_14_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPIO6_14_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x168C++0x3 line.long 0x0 "CTRL_CORE_PAD_GPIO6_15,CTRL_CORE_PAD_GPIO6_15" bitfld.long 0x0 0.--3. " GPIO6_15_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPIO6_15_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPIO6_15_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPIO6_15_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPIO6_15_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPIO6_15_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPIO6_15_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPIO6_15_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPIO6_15_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1690++0x3 line.long 0x0 "CTRL_CORE_PAD_GPIO6_16,CTRL_CORE_PAD_GPIO6_16" bitfld.long 0x0 0.--3. " GPIO6_16_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPIO6_16_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPIO6_16_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPIO6_16_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPIO6_16_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPIO6_16_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPIO6_16_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPIO6_16_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPIO6_16_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1694++0x3 line.long 0x0 "CTRL_CORE_PAD_XREF_CLK0,CTRL_CORE_PAD_XREF_CLK0" bitfld.long 0x0 0.--3. " XREF_CLK0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " XREF_CLK0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " XREF_CLK0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " XREF_CLK0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " XREF_CLK0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " XREF_CLK0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " XREF_CLK0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " XREF_CLK0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " XREF_CLK0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1698++0x3 line.long 0x0 "CTRL_CORE_PAD_XREF_CLK1,CTRL_CORE_PAD_XREF_CLK1" bitfld.long 0x0 0.--3. " XREF_CLK1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " XREF_CLK1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " XREF_CLK1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " XREF_CLK1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " XREF_CLK1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " XREF_CLK1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " XREF_CLK1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " XREF_CLK1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " XREF_CLK1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x169C++0x3 line.long 0x0 "CTRL_CORE_PAD_XREF_CLK2,CTRL_CORE_PAD_XREF_CLK2" bitfld.long 0x0 0.--3. " XREF_CLK2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " XREF_CLK2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " XREF_CLK2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " XREF_CLK2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " XREF_CLK2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " XREF_CLK2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " XREF_CLK2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " XREF_CLK2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " XREF_CLK2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16A0++0x3 line.long 0x0 "CTRL_CORE_PAD_XREF_CLK3,CTRL_CORE_PAD_XREF_CLK3" bitfld.long 0x0 0.--3. " XREF_CLK3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " XREF_CLK3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " XREF_CLK3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " XREF_CLK3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " XREF_CLK3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " XREF_CLK3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " XREF_CLK3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " XREF_CLK3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " XREF_CLK3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16A4++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_ACLKX,CTRL_CORE_PAD_MCASP1_ACLKX" bitfld.long 0x0 0.--3. " MCASP1_ACLKX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_ACLKX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_ACLKX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_ACLKX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_ACLKX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_ACLKX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_ACLKX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_ACLKX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_ACLKX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16A8++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_FSX,CTRL_CORE_PAD_MCASP1_FSX" bitfld.long 0x0 0.--3. " MCASP1_FSX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_FSX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_FSX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_FSX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_FSX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_FSX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_FSX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_FSX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_FSX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16AC++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_ACLKR,CTRL_CORE_PAD_MCASP1_ACLKR" bitfld.long 0x0 0.--3. " MCASP1_ACLKR_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_ACLKR_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_ACLKR_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_ACLKR_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_ACLKR_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_ACLKR_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_ACLKR_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_ACLKR_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_ACLKR_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16B0++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_FSR,CTRL_CORE_PAD_MCASP1_FSR" bitfld.long 0x0 0.--3. " MCASP1_FSR_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_FSR_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_FSR_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_FSR_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_FSR_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_FSR_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_FSR_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_FSR_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_FSR_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16B4++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR0,CTRL_CORE_PAD_MCASP1_AXR0" bitfld.long 0x0 0.--3. " MCASP1_AXR0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16B8++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR1,CTRL_CORE_PAD_MCASP1_AXR1" bitfld.long 0x0 0.--3. " MCASP1_AXR1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16BC++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR2,CTRL_CORE_PAD_MCASP1_AXR2" bitfld.long 0x0 0.--3. " MCASP1_AXR2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16C0++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR3,CTRL_CORE_PAD_MCASP1_AXR3" bitfld.long 0x0 0.--3. " MCASP1_AXR3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16C4++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR4,CTRL_CORE_PAD_MCASP1_AXR4" bitfld.long 0x0 0.--3. " MCASP1_AXR4_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR4_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR4_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR4_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR4_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR4_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR4_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR4_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR4_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16C8++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR5,CTRL_CORE_PAD_MCASP1_AXR5" bitfld.long 0x0 0.--3. " MCASP1_AXR5_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR5_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR5_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR5_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR5_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR5_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR5_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR5_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR5_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16CC++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR6,CTRL_CORE_PAD_MCASP1_AXR6" bitfld.long 0x0 0.--3. " MCASP1_AXR6_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR6_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR6_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR6_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR6_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR6_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR6_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR6_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR6_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16D0++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR7,CTRL_CORE_PAD_MCASP1_AXR7" bitfld.long 0x0 0.--3. " MCASP1_AXR7_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR7_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR7_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR7_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR7_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR7_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR7_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR7_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR7_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16D4++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR8,CTRL_CORE_PAD_MCASP1_AXR8" bitfld.long 0x0 0.--3. " MCASP1_AXR8_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR8_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR8_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR8_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR8_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR8_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR8_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR8_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR8_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16D8++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR9,CTRL_CORE_PAD_MCASP1_AXR9" bitfld.long 0x0 0.--3. " MCASP1_AXR9_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR9_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR9_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR9_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR9_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR9_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR9_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR9_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR9_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16DC++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR10,CTRL_CORE_PAD_MCASP1_AXR10" bitfld.long 0x0 0.--3. " MCASP1_AXR10_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR10_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR10_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR10_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR10_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR10_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR10_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR10_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR10_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16E0++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR11,CTRL_CORE_PAD_MCASP1_AXR11" bitfld.long 0x0 0.--3. " MCASP1_AXR11_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR11_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR11_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR11_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR11_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR11_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR11_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR11_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR11_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16E4++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR12,CTRL_CORE_PAD_MCASP1_AXR12" bitfld.long 0x0 0.--3. " MCASP1_AXR12_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR12_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR12_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR12_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR12_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR12_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR12_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR12_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR12_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16E8++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR13,CTRL_CORE_PAD_MCASP1_AXR13" bitfld.long 0x0 0.--3. " MCASP1_AXR13_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR13_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR13_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR13_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR13_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR13_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR13_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR13_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR13_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16EC++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR14,CTRL_CORE_PAD_MCASP1_AXR14" bitfld.long 0x0 0.--3. " MCASP1_AXR14_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR14_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR14_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR14_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR14_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR14_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR14_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR14_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR14_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16F0++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP1_AXR15,CTRL_CORE_PAD_MCASP1_AXR15" bitfld.long 0x0 0.--3. " MCASP1_AXR15_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP1_AXR15_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP1_AXR15_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP1_AXR15_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR15_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR15_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR15_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP1_AXR15_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP1_AXR15_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16F4++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_ACLKX,CTRL_CORE_PAD_MCASP2_ACLKX" bitfld.long 0x0 0.--3. " MCASP2_ACLKX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_ACLKX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_ACLKX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_ACLKX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_ACLKX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_ACLKX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_ACLKX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_ACLKX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_ACLKX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16F8++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_FSX,CTRL_CORE_PAD_MCASP2_FSX" bitfld.long 0x0 0.--3. " MCASP2_FSX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_FSX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_FSX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_FSX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_FSX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_FSX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_FSX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_FSX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_FSX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x16FC++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_ACLKR,CTRL_CORE_PAD_MCASP2_ACLKR" bitfld.long 0x0 0.--3. " MCASP2_ACLKR_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_ACLKR_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_ACLKR_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_ACLKR_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_ACLKR_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_ACLKR_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_ACLKR_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_ACLKR_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_ACLKR_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1700++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_FSR,CTRL_CORE_PAD_MCASP2_FSR" bitfld.long 0x0 0.--3. " MCASP2_FSR_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_FSR_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_FSR_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_FSR_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_FSR_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_FSR_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_FSR_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_FSR_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_FSR_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1704++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_AXR0,CTRL_CORE_PAD_MCASP2_AXR0" bitfld.long 0x0 0.--3. " MCASP2_AXR0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_AXR0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_AXR0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_AXR0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_AXR0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_AXR0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_AXR0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_AXR0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_AXR0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1708++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_AXR1,CTRL_CORE_PAD_MCASP2_AXR1" bitfld.long 0x0 0.--3. " MCASP2_AXR1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_AXR1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_AXR1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_AXR1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_AXR1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_AXR1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_AXR1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_AXR1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_AXR1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x170C++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_AXR2,CTRL_CORE_PAD_MCASP2_AXR2" bitfld.long 0x0 0.--3. " MCASP2_AXR2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_AXR2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_AXR2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_AXR2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_AXR2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_AXR2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_AXR2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_AXR2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_AXR2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1710++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_AXR3,CTRL_CORE_PAD_MCASP2_AXR3" bitfld.long 0x0 0.--3. " MCASP2_AXR3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_AXR3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_AXR3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_AXR3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_AXR3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_AXR3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_AXR3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_AXR3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_AXR3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1714++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_AXR4,CTRL_CORE_PAD_MCASP2_AXR4" bitfld.long 0x0 0.--3. " MCASP2_AXR4_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_AXR4_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_AXR4_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_AXR4_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_AXR4_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_AXR4_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_AXR4_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_AXR4_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_AXR4_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1718++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_AXR5,CTRL_CORE_PAD_MCASP2_AXR5" bitfld.long 0x0 0.--3. " MCASP2_AXR5_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_AXR5_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_AXR5_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_AXR5_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_AXR5_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_AXR5_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_AXR5_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_AXR5_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_AXR5_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x171C++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_AXR6,CTRL_CORE_PAD_MCASP2_AXR6" bitfld.long 0x0 0.--3. " MCASP2_AXR6_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_AXR6_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_AXR6_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_AXR6_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_AXR6_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_AXR6_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_AXR6_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_AXR6_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_AXR6_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1720++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP2_AXR7,CTRL_CORE_PAD_MCASP2_AXR7" bitfld.long 0x0 0.--3. " MCASP2_AXR7_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP2_AXR7_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP2_AXR7_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP2_AXR7_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP2_AXR7_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP2_AXR7_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP2_AXR7_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP2_AXR7_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP2_AXR7_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1724++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP3_ACLKX,CTRL_CORE_PAD_MCASP3_ACLKX" bitfld.long 0x0 0.--3. " MCASP3_ACLKX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP3_ACLKX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP3_ACLKX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP3_ACLKX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP3_ACLKX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP3_ACLKX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP3_ACLKX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP3_ACLKX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP3_ACLKX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1728++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP3_FSX,CTRL_CORE_PAD_MCASP3_FSX" bitfld.long 0x0 0.--3. " MCASP3_FSX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP3_FSX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP3_FSX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP3_FSX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP3_FSX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP3_FSX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP3_FSX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP3_FSX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP3_FSX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x172C++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP3_AXR0,CTRL_CORE_PAD_MCASP3_AXR0" bitfld.long 0x0 0.--3. " MCASP3_AXR0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP3_AXR0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP3_AXR0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP3_AXR0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP3_AXR0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP3_AXR0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP3_AXR0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP3_AXR0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP3_AXR0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1730++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP3_AXR1,CTRL_CORE_PAD_MCASP3_AXR1" bitfld.long 0x0 0.--3. " MCASP3_AXR1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP3_AXR1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP3_AXR1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP3_AXR1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP3_AXR1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP3_AXR1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP3_AXR1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP3_AXR1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP3_AXR1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1734++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP4_ACLKX,CTRL_CORE_PAD_MCASP4_ACLKX" bitfld.long 0x0 0.--3. " MCASP4_ACLKX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP4_ACLKX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP4_ACLKX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP4_ACLKX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP4_ACLKX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP4_ACLKX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP4_ACLKX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP4_ACLKX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP4_ACLKX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1738++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP4_FSX,CTRL_CORE_PAD_MCASP4_FSX" bitfld.long 0x0 0.--3. " MCASP4_FSX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP4_FSX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP4_FSX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP4_FSX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP4_FSX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP4_FSX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP4_FSX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP4_FSX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP4_FSX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x173C++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP4_AXR0,CTRL_CORE_PAD_MCASP4_AXR0" bitfld.long 0x0 0.--3. " MCASP4_AXR0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP4_AXR0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP4_AXR0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP4_AXR0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP4_AXR0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP4_AXR0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP4_AXR0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP4_AXR0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP4_AXR0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1740++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP4_AXR1,CTRL_CORE_PAD_MCASP4_AXR1" bitfld.long 0x0 0.--3. " MCASP4_AXR1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP4_AXR1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP4_AXR1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP4_AXR1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP4_AXR1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP4_AXR1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP4_AXR1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP4_AXR1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP4_AXR1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1744++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP5_ACLKX,CTRL_CORE_PAD_MCASP5_ACLKX" bitfld.long 0x0 0.--3. " MCASP5_ACLKX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP5_ACLKX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP5_ACLKX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP5_ACLKX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP5_ACLKX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP5_ACLKX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP5_ACLKX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP5_ACLKX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP5_ACLKX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1748++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP5_FSX,CTRL_CORE_PAD_MCASP5_FSX" bitfld.long 0x0 0.--3. " MCASP5_FSX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP5_FSX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP5_FSX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP5_FSX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP5_FSX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP5_FSX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP5_FSX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP5_FSX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP5_FSX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x174C++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP5_AXR0,CTRL_CORE_PAD_MCASP5_AXR0" bitfld.long 0x0 0.--3. " MCASP5_AXR0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP5_AXR0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP5_AXR0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP5_AXR0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP5_AXR0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP5_AXR0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP5_AXR0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP5_AXR0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP5_AXR0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1750++0x3 line.long 0x0 "CTRL_CORE_PAD_MCASP5_AXR1,CTRL_CORE_PAD_MCASP5_AXR1" bitfld.long 0x0 0.--3. " MCASP5_AXR1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MCASP5_AXR1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MCASP5_AXR1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCASP5_AXR1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MCASP5_AXR1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP5_AXR1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MCASP5_AXR1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MCASP5_AXR1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MCASP5_AXR1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1754++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC1_CLK,CTRL_CORE_PAD_MMC1_CLK" bitfld.long 0x0 0.--3. " MMC1_CLK_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC1_CLK_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC1_CLK_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC1_CLK_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC1_CLK_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC1_CLK_ACTIVE ,Controls enabling/disabling of the input buffer. 0x0: Input buffer is disabled 0x1: Input buffer is enabled" "0,1" bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 24. " MMC1_CLK_WAKEUPENABLE ," "0,1" bitfld.long 0x0 25. " MMC1_CLK_WAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1758++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC1_CMD,CTRL_CORE_PAD_MMC1_CMD" bitfld.long 0x0 0.--3. " MMC1_CMD_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC1_CMD_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC1_CMD_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC1_CMD_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC1_CMD_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC1_CMD_ACTIVE ,Controls enabling/disabling of the input buffer. 0x0: Input buffer is disabled 0x1: Input buffer is enabled" "0,1" bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 24. " MMC1_CMD_WAKEUPENABLE ," "0,1" bitfld.long 0x0 25. " MMC1_CMD_WAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x175C++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC1_DAT0,CTRL_CORE_PAD_MMC1_DAT0" bitfld.long 0x0 0.--3. " MMC1_DAT0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC1_DAT0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC1_DAT0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC1_DAT0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC1_DAT0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC1_DAT0_ACTIVE ,Controls enabling/disabling of the input buffer. 0x0: Input buffer is disabled 0x1: Input buffer is enabled" "0,1" bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 24. " MMC1_DAT0_WAKEUPENABLE ," "0,1" bitfld.long 0x0 25. " MMC1_DAT0_WAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1760++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC1_DAT1,CTRL_CORE_PAD_MMC1_DAT1" bitfld.long 0x0 0.--3. " MMC1_DAT1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC1_DAT1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC1_DAT1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC1_DAT1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC1_DAT1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC1_DAT1_ACTIVE ,Controls enabling/disabling of the input buffer. 0x0: Input buffer is disabled 0x1: Input buffer is enabled" "0,1" bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 24. " MMC1_DAT1_WAKEUPENABLE ," "0,1" bitfld.long 0x0 25. " MMC1_DAT1_WAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1764++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC1_DAT2,CTRL_CORE_PAD_MMC1_DAT2" bitfld.long 0x0 0.--3. " MMC1_DAT2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC1_DAT2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC1_DAT2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC1_DAT2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC1_DAT2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC1_DAT2_ACTIVE ,Controls enabling/disabling of the input buffer. 0x0: Input buffer is disabled 0x1: Input buffer is enabled" "0,1" bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 24. " MMC1_DAT2_WAKEUPENABLE ," "0,1" bitfld.long 0x0 25. " MMC1_DAT2_WAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1768++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC1_DAT3,CTRL_CORE_PAD_MMC1_DAT3" bitfld.long 0x0 0.--3. " MMC1_DAT3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC1_DAT3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC1_DAT3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC1_DAT3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC1_DAT3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC1_DAT3_ACTIVE ,Controls enabling/disabling of the input buffer. 0x0: Input buffer is disabled 0x1: Input buffer is enabled" "0,1" bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 24. " MMC1_DAT3_WAKEUPENABLE ," "0,1" bitfld.long 0x0 25. " MMC1_DAT3_WAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x176C++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC1_SDCD,CTRL_CORE_PAD_MMC1_SDCD" bitfld.long 0x0 0.--3. " MMC1_SDCD_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC1_SDCD_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC1_SDCD_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC1_SDCD_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC1_SDCD_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC1_SDCD_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC1_SDCD_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC1_SDCD_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC1_SDCD_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1770++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC1_SDWP,CTRL_CORE_PAD_MMC1_SDWP" bitfld.long 0x0 0.--3. " MMC1_SDWP_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC1_SDWP_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC1_SDWP_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC1_SDWP_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC1_SDWP_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC1_SDWP_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC1_SDWP_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC1_SDWP_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC1_SDWP_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1774++0x3 line.long 0x0 "CTRL_CORE_PAD_GPIO6_10,CTRL_CORE_PAD_GPIO6_10" bitfld.long 0x0 0.--3. " GPIO6_10_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPIO6_10_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPIO6_10_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPIO6_10_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPIO6_10_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPIO6_10_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPIO6_10_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPIO6_10_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPIO6_10_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1778++0x3 line.long 0x0 "CTRL_CORE_PAD_GPIO6_11,CTRL_CORE_PAD_GPIO6_11" bitfld.long 0x0 0.--3. " GPIO6_11_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " GPIO6_11_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " GPIO6_11_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " GPIO6_11_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " GPIO6_11_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " GPIO6_11_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " GPIO6_11_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " GPIO6_11_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " GPIO6_11_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x177C++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC3_CLK,CTRL_CORE_PAD_MMC3_CLK" bitfld.long 0x0 0.--3. " MMC3_CLK_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC3_CLK_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC3_CLK_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC3_CLK_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC3_CLK_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC3_CLK_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC3_CLK_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC3_CLK_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC3_CLK_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1780++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC3_CMD,CTRL_CORE_PAD_MMC3_CMD" bitfld.long 0x0 0.--3. " MMC3_CMD_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC3_CMD_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC3_CMD_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC3_CMD_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC3_CMD_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC3_CMD_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC3_CMD_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC3_CMD_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC3_CMD_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1784++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC3_DAT0,CTRL_CORE_PAD_MMC3_DAT0" bitfld.long 0x0 0.--3. " MMC3_DAT0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC3_DAT0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC3_DAT0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC3_DAT0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC3_DAT0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC3_DAT0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC3_DAT0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC3_DAT0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC3_DAT0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1788++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC3_DAT1,CTRL_CORE_PAD_MMC3_DAT1" bitfld.long 0x0 0.--3. " MMC3_DAT1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC3_DAT1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC3_DAT1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC3_DAT1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC3_DAT1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC3_DAT1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC3_DAT1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC3_DAT1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC3_DAT1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x178C++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC3_DAT2,CTRL_CORE_PAD_MMC3_DAT2" bitfld.long 0x0 0.--3. " MMC3_DAT2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC3_DAT2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC3_DAT2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC3_DAT2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC3_DAT2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC3_DAT2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC3_DAT2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC3_DAT2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC3_DAT2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1790++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC3_DAT3,CTRL_CORE_PAD_MMC3_DAT3" bitfld.long 0x0 0.--3. " MMC3_DAT3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC3_DAT3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC3_DAT3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC3_DAT3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC3_DAT3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC3_DAT3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC3_DAT3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC3_DAT3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC3_DAT3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1794++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC3_DAT4,CTRL_CORE_PAD_MMC3_DAT4" bitfld.long 0x0 0.--3. " MMC3_DAT4_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC3_DAT4_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC3_DAT4_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC3_DAT4_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC3_DAT4_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC3_DAT4_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC3_DAT4_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC3_DAT4_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC3_DAT4_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1798++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC3_DAT5,CTRL_CORE_PAD_MMC3_DAT5" bitfld.long 0x0 0.--3. " MMC3_DAT5_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC3_DAT5_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC3_DAT5_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC3_DAT5_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC3_DAT5_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC3_DAT5_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC3_DAT5_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC3_DAT5_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC3_DAT5_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x179C++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC3_DAT6,CTRL_CORE_PAD_MMC3_DAT6" bitfld.long 0x0 0.--3. " MMC3_DAT6_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC3_DAT6_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC3_DAT6_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC3_DAT6_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC3_DAT6_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC3_DAT6_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC3_DAT6_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC3_DAT6_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC3_DAT6_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17A0++0x3 line.long 0x0 "CTRL_CORE_PAD_MMC3_DAT7,CTRL_CORE_PAD_MMC3_DAT7" bitfld.long 0x0 0.--3. " MMC3_DAT7_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " MMC3_DAT7_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " MMC3_DAT7_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MMC3_DAT7_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " MMC3_DAT7_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " MMC3_DAT7_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " MMC3_DAT7_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " MMC3_DAT7_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " MMC3_DAT7_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17A4++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI1_SCLK,CTRL_CORE_PAD_SPI1_SCLK" bitfld.long 0x0 0.--3. " SPI1_SCLK_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI1_SCLK_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI1_SCLK_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI1_SCLK_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI1_SCLK_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI1_SCLK_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI1_SCLK_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI1_SCLK_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI1_SCLK_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17A8++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI1_D1,CTRL_CORE_PAD_SPI1_D1" bitfld.long 0x0 0.--3. " SPI1_D1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI1_D1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI1_D1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI1_D1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI1_D1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI1_D1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI1_D1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI1_D1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI1_D1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17AC++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI1_D0,CTRL_CORE_PAD_SPI1_D0" bitfld.long 0x0 0.--3. " SPI1_D0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI1_D0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI1_D0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI1_D0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI1_D0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI1_D0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI1_D0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI1_D0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI1_D0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17B0++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI1_CS0,CTRL_CORE_PAD_SPI1_CS0" bitfld.long 0x0 0.--3. " SPI1_CS0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI1_CS0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI1_CS0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI1_CS0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI1_CS0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI1_CS0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI1_CS0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI1_CS0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI1_CS0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17B4++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI1_CS1,CTRL_CORE_PAD_SPI1_CS1" bitfld.long 0x0 0.--3. " SPI1_CS1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI1_CS1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI1_CS1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI1_CS1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI1_CS1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI1_CS1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI1_CS1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI1_CS1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI1_CS1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17B8++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI1_CS2,CTRL_CORE_PAD_SPI1_CS2" bitfld.long 0x0 0.--3. " SPI1_CS2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI1_CS2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI1_CS2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI1_CS2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI1_CS2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI1_CS2_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI1_CS2_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI1_CS2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI1_CS2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17BC++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI1_CS3,CTRL_CORE_PAD_SPI1_CS3" bitfld.long 0x0 0.--3. " SPI1_CS3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI1_CS3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI1_CS3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI1_CS3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI1_CS3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI1_CS3_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI1_CS3_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI1_CS3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI1_CS3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17C0++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI2_SCLK,CTRL_CORE_PAD_SPI2_SCLK" bitfld.long 0x0 0.--3. " SPI2_SCLK_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI2_SCLK_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI2_SCLK_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI2_SCLK_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI2_SCLK_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI2_SCLK_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI2_SCLK_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI2_SCLK_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI2_SCLK_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17C4++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI2_D1,CTRL_CORE_PAD_SPI2_D1" bitfld.long 0x0 0.--3. " SPI2_D1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI2_D1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI2_D1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI2_D1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI2_D1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI2_D1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI2_D1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI2_D1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI2_D1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17C8++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI2_D0,CTRL_CORE_PAD_SPI2_D0" bitfld.long 0x0 0.--3. " SPI2_D0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI2_D0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI2_D0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI2_D0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI2_D0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI2_D0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI2_D0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI2_D0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI2_D0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17CC++0x3 line.long 0x0 "CTRL_CORE_PAD_SPI2_CS0,CTRL_CORE_PAD_SPI2_CS0" bitfld.long 0x0 0.--3. " SPI2_CS0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPI2_CS0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " SPI2_CS0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " SPI2_CS0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " SPI2_CS0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " SPI2_CS0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " SPI2_CS0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SPI2_CS0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " SPI2_CS0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17D0++0x3 line.long 0x0 "CTRL_CORE_PAD_DCAN1_TX,CTRL_CORE_PAD_DCAN1_TX" bitfld.long 0x0 0.--3. " DCAN1_TX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " DCAN1_TX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " DCAN1_TX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " DCAN1_TX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " DCAN1_TX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " DCAN1_TX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " DCAN1_TX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " DCAN1_TX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " DCAN1_TX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17D4++0x3 line.long 0x0 "CTRL_CORE_PAD_DCAN1_RX,CTRL_CORE_PAD_DCAN1_RX" bitfld.long 0x0 0.--3. " DCAN1_RX_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " DCAN1_RX_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " DCAN1_RX_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " DCAN1_RX_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " DCAN1_RX_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " DCAN1_RX_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " DCAN1_RX_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " DCAN1_RX_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " DCAN1_RX_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17E0++0x3 line.long 0x0 "CTRL_CORE_PAD_UART1_RXD,CTRL_CORE_PAD_UART1_RXD" bitfld.long 0x0 0.--3. " UART1_RXD_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " UART1_RXD_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " UART1_RXD_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " UART1_RXD_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " UART1_RXD_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " UART1_RXD_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " UART1_RXD_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " UART1_RXD_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " UART1_RXD_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17E4++0x3 line.long 0x0 "CTRL_CORE_PAD_UART1_TXD,CTRL_CORE_PAD_UART1_TXD" bitfld.long 0x0 0.--3. " UART1_TXD_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " UART1_TXD_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " UART1_TXD_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " UART1_TXD_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " UART1_TXD_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " UART1_TXD_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " UART1_TXD_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " UART1_TXD_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " UART1_TXD_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17E8++0x3 line.long 0x0 "CTRL_CORE_PAD_UART1_CTSN,CTRL_CORE_PAD_UART1_CTSN" bitfld.long 0x0 0.--3. " UART1_CTSN_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " UART1_CTSN_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " UART1_CTSN_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " UART1_CTSN_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " UART1_CTSN_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " UART1_CTSN_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " UART1_CTSN_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " UART1_CTSN_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " UART1_CTSN_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17EC++0x3 line.long 0x0 "CTRL_CORE_PAD_UART1_RTSN,CTRL_CORE_PAD_UART1_RTSN" bitfld.long 0x0 0.--3. " UART1_RTSN_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " UART1_RTSN_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " UART1_RTSN_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " UART1_RTSN_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " UART1_RTSN_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " UART1_RTSN_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " UART1_RTSN_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " UART1_RTSN_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " UART1_RTSN_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17F0++0x3 line.long 0x0 "CTRL_CORE_PAD_UART2_RXD,CTRL_CORE_PAD_UART2_RXD" bitfld.long 0x0 0.--3. " UART2_RXD_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " UART2_RXD_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " UART2_RXD_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " UART2_RXD_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " UART2_RXD_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " UART2_RXD_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " UART2_RXD_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " UART2_RXD_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " UART2_RXD_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17F4++0x3 line.long 0x0 "CTRL_CORE_PAD_UART2_TXD,CTRL_CORE_PAD_UART2_TXD" bitfld.long 0x0 0.--3. " UART2_TXD_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " UART2_TXD_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " UART2_TXD_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " UART2_TXD_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " UART2_TXD_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " UART2_TXD_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " UART2_TXD_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " UART2_TXD_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " UART2_TXD_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17F8++0x3 line.long 0x0 "CTRL_CORE_PAD_UART2_CTSN,CTRL_CORE_PAD_UART2_CTSN" bitfld.long 0x0 0.--3. " UART2_CTSN_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " UART2_CTSN_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " UART2_CTSN_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " UART2_CTSN_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " UART2_CTSN_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " UART2_CTSN_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " UART2_CTSN_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " UART2_CTSN_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " UART2_CTSN_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x17FC++0x3 line.long 0x0 "CTRL_CORE_PAD_UART2_RTSN,CTRL_CORE_PAD_UART2_RTSN" bitfld.long 0x0 0.--3. " UART2_RTSN_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " UART2_RTSN_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " UART2_RTSN_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " UART2_RTSN_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " UART2_RTSN_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " UART2_RTSN_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " UART2_RTSN_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " UART2_RTSN_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " UART2_RTSN_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1800++0x3 line.long 0x0 "CTRL_CORE_PAD_I2C1_SDA,CTRL_CORE_PAD_I2C1_SDA" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " I2C1_SDA_PULLUDENABLE ," "0,1" textline " " bitfld.long 0x0 17. " I2C1_SDA_PULLTYPESELECT ," "0,1" bitfld.long 0x0 18. " I2C1_SDA_INPUTENABLE ," "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24. " I2C1_SDA_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " I2C1_SDA_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1804++0x3 line.long 0x0 "CTRL_CORE_PAD_I2C1_SCL,CTRL_CORE_PAD_I2C1_SCL" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " I2C1_SCL_PULLUDENABLE ," "0,1" textline " " bitfld.long 0x0 17. " I2C1_SCL_PULLTYPESELECT ," "0,1" bitfld.long 0x0 18. " I2C1_SCL_INPUTENABLE ," "0,1" textline " " bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 24. " I2C1_SCL_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " I2C1_SCL_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1808++0x3 line.long 0x0 "CTRL_CORE_PAD_I2C2_SDA,CTRL_CORE_PAD_I2C2_SDA" bitfld.long 0x0 0.--3. " I2C2_SDA_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " I2C2_SDA_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " I2C2_SDA_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " I2C2_SDA_INPUTENABLE ," "0,1" bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 24. " I2C2_SDA_WAKEUPENABLE ," "0,1" bitfld.long 0x0 25. " I2C2_SDA_WAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x180C++0x3 line.long 0x0 "CTRL_CORE_PAD_I2C2_SCL,CTRL_CORE_PAD_I2C2_SCL" bitfld.long 0x0 0.--3. " I2C2_SCL_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " I2C2_SCL_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " I2C2_SCL_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " I2C2_SCL_INPUTENABLE ," "0,1" bitfld.long 0x0 19.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 24. " I2C2_SCL_WAKEUPENABLE ," "0,1" bitfld.long 0x0 25. " I2C2_SCL_WAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1818++0x3 line.long 0x0 "CTRL_CORE_PAD_WAKEUP0,CTRL_CORE_PAD_WAKEUP0" bitfld.long 0x0 0.--3. " WAKEUP0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " WAKEUP0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " WAKEUP0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " WAKEUP0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " WAKEUP0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 24. " WAKEUP0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " WAKEUP0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x181C++0x3 line.long 0x0 "CTRL_CORE_PAD_WAKEUP1,CTRL_CORE_PAD_WAKEUP1" bitfld.long 0x0 0.--3. " WAKEUP1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " WAKEUP1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " WAKEUP1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " WAKEUP1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " WAKEUP1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 24. " WAKEUP1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " WAKEUP1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1820++0x3 line.long 0x0 "CTRL_CORE_PAD_WAKEUP2,CTRL_CORE_PAD_WAKEUP2" bitfld.long 0x0 0.--3. " WAKEUP2_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " WAKEUP2_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " WAKEUP2_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " WAKEUP2_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " WAKEUP2_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 24. " WAKEUP2_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " WAKEUP2_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1824++0x3 line.long 0x0 "CTRL_CORE_PAD_WAKEUP3,CTRL_CORE_PAD_WAKEUP3" bitfld.long 0x0 0.--3. " WAKEUP3_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " WAKEUP3_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " WAKEUP3_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " WAKEUP3_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " WAKEUP3_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 24. " WAKEUP3_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " WAKEUP3_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1828++0x3 line.long 0x0 "CTRL_CORE_PAD_ON_OFF,CTRL_CORE_PAD_ON_OFF" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " ON_OFF_PULLUDENABLE ," "0,1" textline " " bitfld.long 0x0 17. " ON_OFF_PULLTYPESELECT ," "0,1" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x182C++0x3 line.long 0x0 "CTRL_CORE_PAD_RTC_PORZ,CTRL_CORE_PAD_RTC_PORZ" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " RTC_PORZ_PULLUDENABLE ," "0,1" textline " " bitfld.long 0x0 17. " RTC_PORZ_PULLTYPESELECT ," "0,1" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1830++0x3 line.long 0x0 "CTRL_CORE_PAD_TMS,CTRL_CORE_PAD_TMS" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " TMS_PULLUDENABLE ," "0,1" textline " " bitfld.long 0x0 17. " TMS_PULLTYPESELECT ," "0,1" bitfld.long 0x0 18. " TMS_INPUTENABLE ," "0,1" textline " " bitfld.long 0x0 19. " TMS_SLEWCONTROL ," "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x1834++0x3 line.long 0x0 "CTRL_CORE_PAD_TDI,CTRL_CORE_PAD_TDI" bitfld.long 0x0 0.--3. " TDI_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " TDI_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " TDI_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " TDI_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " TDI_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " TDI_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " TDI_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " TDI_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " TDI_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1838++0x3 line.long 0x0 "CTRL_CORE_PAD_TDO,CTRL_CORE_PAD_TDO" bitfld.long 0x0 0.--3. " TDO_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " TDO_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " TDO_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " TDO_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " TDO_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " TDO_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " TDO_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " TDO_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " TDO_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x183C++0x3 line.long 0x0 "CTRL_CORE_PAD_TCLK,CTRL_CORE_PAD_TCLK" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " TCLK_PULLUDENABLE ," "0,1" textline " " bitfld.long 0x0 17. " TCLK_PULLTYPESELECT ," "0,1" bitfld.long 0x0 18. " TCLK_INPUTENABLE ," "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x1840++0x3 line.long 0x0 "CTRL_CORE_PAD_TRSTN,CTRL_CORE_PAD_TRSTN" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " TRSTN_PULLUDENABLE ," "0,1" textline " " bitfld.long 0x0 17. " TRSTN_PULLTYPESELECT ," "0,1" bitfld.long 0x0 18. " TRSTN_INPUTENABLE ," "0,1" textline " " bitfld.long 0x0 19. " TRSTN_SLEWCONTROL ," "0,1" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x1844++0x3 line.long 0x0 "CTRL_CORE_PAD_RTCK,CTRL_CORE_PAD_RTCK" bitfld.long 0x0 0.--3. " RTCK_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RTCK_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RTCK_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " RTCK_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " RTCK_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " RTCK_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " RTCK_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " RTCK_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " RTCK_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1848++0x3 line.long 0x0 "CTRL_CORE_PAD_EMU0,CTRL_CORE_PAD_EMU0" bitfld.long 0x0 0.--3. " EMU0_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " EMU0_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " EMU0_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " EMU0_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " EMU0_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " EMU0_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " EMU0_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " EMU0_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " EMU0_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x184C++0x3 line.long 0x0 "CTRL_CORE_PAD_EMU1,CTRL_CORE_PAD_EMU1" bitfld.long 0x0 0.--3. " EMU1_MUXMODE ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " EMU1_DELAYMODE ,This bit field selects the Virtual Timing Mode used when the MODESELECT bit is set to 0b1. See, Virtual IO Timing Modes for details." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " EMU1_MODESELECT ,Selects between the Default IO Timing Mode and a Virtual or Manual IO Timing Mode. Refer to the device Data Manual for definition of the required settings for a given mode of operation. When this bit is 0b1, a Virtual IO Timing Mode can be selected via the DELAYMODE field of this register, as described in, Virtual IO Timing Modes. Manual IO Timing Modes are selected via the procedure described in , Manual IO Timing Modes." "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " EMU1_PULLUDENABLE ," "0,1" bitfld.long 0x0 17. " EMU1_PULLTYPESELECT ," "0,1" textline " " bitfld.long 0x0 18. " EMU1_INPUTENABLE ," "0,1" bitfld.long 0x0 19. " EMU1_SLEWCONTROL ," "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " EMU1_WAKEUPENABLE ," "0,1" textline " " bitfld.long 0x0 25. " EMU1_WAKEUPEVENT ," "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x185C++0x3 line.long 0x0 "CTRL_CORE_PAD_RESETN,CTRL_CORE_PAD_RESETN" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " RESETN_PULLUDENABLE ," "0,1" textline " " bitfld.long 0x0 17. " RESETN_PULLTYPESELECT ," "0,1" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1860++0x3 line.long 0x0 "CTRL_CORE_PAD_NMIN_DSP,CTRL_CORE_PAD_NMIN_DSP" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " NMIN_PULLUDENABLE ," "0,1" textline " " bitfld.long 0x0 17. " NMIN_PULLTYPESELECT ," "0,1" bitfld.long 0x0 18.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 24. " NMIN_WAKEUPENABLE ," "0,1" bitfld.long 0x0 25. " NMIN_WAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1864++0x3 line.long 0x0 "CTRL_CORE_PAD_RSTOUTN,CTRL_CORE_PAD_RSTOUTN" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " RSTOUTN_PULLUDENABLE ," "0,1" textline " " bitfld.long 0x0 17. " RSTOUTN_PULLTYPESELECT ," "0,1" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1868++0x3 line.long 0x0 "CTRL_CORE_PADCONF_WAKEUPEVENT_0,CTRL_CORE_PADCONF_WAKEUPEVENT_0" bitfld.long 0x0 0. " GPMC_AD0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 1. " GPMC_AD1_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 2. " GPMC_AD2_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 3. " GPMC_AD3_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 4. " GPMC_AD4_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 5. " GPMC_AD5_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 6. " GPMC_AD6_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 7. " GPMC_AD7_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 8. " GPMC_AD8_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 9. " GPMC_AD9_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 10. " GPMC_AD10_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 11. " GPMC_AD11_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 12. " GPMC_AD12_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 13. " GPMC_AD13_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 14. " GPMC_AD14_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 15. " GPMC_AD15_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 16. " GPMC_A0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 17. " GPMC_A1_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_A2_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 19. " GPMC_A3_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 20. " GPMC_A4_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 21. " GPMC_A5_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 22. " GPMC_A6_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 23. " GPMC_A7_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 24. " GPMC_A8_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 25. " GPMC_A9_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26. " GPMC_A10_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 27. " GPMC_A11_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 28. " GPMC_A12_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 29. " GPMC_A13_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 30. " GPMC_A14_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 31. " GPMC_A15_DUPLICATEWAKEUPEVENT ," "0,1" group.byte 0x186C++0x3 line.long 0x0 "CTRL_CORE_PADCONF_WAKEUPEVENT_1,CTRL_CORE_PADCONF_WAKEUPEVENT_1" bitfld.long 0x0 0. " GPMC_A16_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 1. " GPMC_A17_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 2. " GPMC_A18_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 3. " GPMC_A19_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 4. " GPMC_A20_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 5. " GPMC_A21_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 6. " GPMC_A22_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 7. " GPMC_A23_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 8. " GPMC_A24_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 9. " GPMC_A25_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 10. " GPMC_A26_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 11. " GPMC_A27_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 12. " GPMC_CS1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 13. " GPMC_CS0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 14. " GPMC_CS2_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 15. " GPMC_CS3_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 16. " GPMC_CLK_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 17. " GPMC_ADVN_ALE_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 18. " GPMC_OEN_REN_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 19. " GPMC_WEN_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 20. " GPMC_BEN0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 21. " GPMC_BEN1_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 22. " GPMC_WAIT0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 23. " VIN1A_CLK0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 24. " VIN1B_CLK1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 25. " VIN1A_DE0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26. " VIN1A_FLD0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 27. " VIN1A_HSYNC0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 28. " VIN1A_VSYNC0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 29. " VIN1A_D0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 30. " VIN1A_D1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 31. " VIN1A_D2_DUPLICATEWAKEUPEVENT ," "0,1" group.byte 0x1870++0x3 line.long 0x0 "CTRL_CORE_PADCONF_WAKEUPEVENT_2,CTRL_CORE_PADCONF_WAKEUPEVENT_2" bitfld.long 0x0 0. " VIN1A_D3_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 1. " VIN1A_D4_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 2. " VIN1A_D5_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 3. " VIN1A_D6_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 4. " VIN1A_D7_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 5. " VIN1A_D8_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 6. " VIN1A_D9_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 7. " VIN1A_D10_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 8. " VIN1A_D11_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 9. " VIN1A_D12_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 10. " VIN1A_D13_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 11. " VIN1A_D14_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 12. " VIN1A_D15_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 13. " VIN1A_D16_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 14. " VIN1A_D17_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 15. " VIN1A_D18_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 16. " VIN1A_D19_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 17. " VIN1A_D20_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 18. " VIN1A_D21_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 19. " VIN1A_D22_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 20. " VIN1A_D23_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 21. " VIN2A_CLK0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 22. " VIN2A_DE0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 23. " VIN2A_FLD0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 24. " VIN2A_HSYNC0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 25. " VIN2A_VSYNC0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26. " VIN2A_D0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 27. " VIN2A_D1_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 28. " VIN2A_D2_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 29. " VIN2A_D3_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 30. " VIN2A_D4_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 31. " VIN2A_D5_DUPLICATEWAKEUPEVENT ," "0,1" group.byte 0x1874++0x3 line.long 0x0 "CTRL_CORE_PADCONF_WAKEUPEVENT_3,CTRL_CORE_PADCONF_WAKEUPEVENT_3" bitfld.long 0x0 0. " VIN2A_D6_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 1. " VIN2A_D7_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 2. " VIN2A_D8_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 3. " VIN2A_D9_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 4. " VIN2A_D10_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 5. " VIN2A_D11_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 6. " VIN2A_D12_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 7. " VIN2A_D13_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 8. " VIN2A_D14_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 9. " VIN2A_D15_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 10. " VIN2A_D16_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 11. " VIN2A_D17_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 12. " VIN2A_D18_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 13. " VIN2A_D19_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 14. " VIN2A_D20_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 15. " VIN2A_D21_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 16. " VIN2A_D22_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 17. " VIN2A_D23_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 18. " VOUT1_CLK_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 19. " VOUT1_DE_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 20. " VOUT1_FLD_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 21. " VOUT1_HSYNC_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 22. " VOUT1_VSYNC_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 23. " VOUT1_D0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 24. " VOUT1_D1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 25. " VOUT1_D2_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26. " VOUT1_D3_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 27. " VOUT1_D4_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 28. " VOUT1_D5_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 29. " VOUT1_D6_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 30. " VOUT1_D7_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 31. " VOUT1_D8_DUPLICATEWAKEUPEVENT ," "0,1" group.byte 0x1878++0x3 line.long 0x0 "CTRL_CORE_PADCONF_WAKEUPEVENT_4,CTRL_CORE_PADCONF_WAKEUPEVENT_4" bitfld.long 0x0 0. " VOUT1_D9_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 1. " VOUT1_D10_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 2. " VOUT1_D11_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 3. " VOUT1_D12_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 4. " VOUT1_D13_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 5. " VOUT1_D14_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 6. " VOUT1_D15_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 7. " VOUT1_D16_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 8. " VOUT1_D17_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 9. " VOUT1_D18_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 10. " VOUT1_D19_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 11. " VOUT1_D20_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 12. " VOUT1_D21_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 13. " VOUT1_D22_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 14. " VOUT1_D23_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 15. " MDIO_MCLK_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 16. " MDIO_D_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 17. " RMII_MHZ_50_CLK_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 18. " UART3_RXD_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 19. " UART3_TXD_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 20. " RGMII0_TXC_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 21. " RGMII0_TXCTL_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 22. " RGMII0_TXD3_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 23. " RGMII0_TXD2_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 24. " RGMII0_TXD1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 25. " RGMII0_TXD0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26. " RGMII0_RXC_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 27. " RGMII0_RXCTL_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 28. " RGMII0_RXD3_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 29. " RGMII0_RXD2_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 30. " RGMII0_RXD1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 31. " RGMII0_RXD0_DUPLICATEWAKEUPEVENT ," "0,1" group.byte 0x187C++0x3 line.long 0x0 "CTRL_CORE_PADCONF_WAKEUPEVENT_5,CTRL_CORE_PADCONF_WAKEUPEVENT_5" bitfld.long 0x0 0. " USB1_DRVVBUS_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 1. " USB2_DRVVBUS_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 2. " GPIO6_14_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 3. " GPIO6_15_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 4. " GPIO6_16_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 5. " XREF_CLK0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 6. " XREF_CLK1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 7. " XREF_CLK2_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 8. " XREF_CLK3_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 9. " MCASP1_ACLKX_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 10. " MCASP1_FSX_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 11. " MCASP1_ACLKR_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 12. " MCASP1_FSR_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 13. " MCASP1_AXR0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 14. " MCASP1_AXR1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 15. " MCASP1_AXR2_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 16. " MCASP1_AXR3_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 17. " MCASP1_AXR4_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP1_AXR5_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 19. " MCASP1_AXR6_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 20. " MCASP1_AXR7_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 21. " MCASP1_AXR8_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 22. " MCASP1_AXR9_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 23. " MCASP1_AXR10_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 24. " MCASP1_AXR11_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 25. " MCASP1_AXR12_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26. " MCASP1_AXR13_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 27. " MCASP1_AXR14_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 28. " MCASP1_AXR15_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 29. " MCASP2_ACLKX_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 30. " MCASP2_FSX_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 31. " MCASP2_ACLKR_DUPLICATEWAKEUPEVENT ," "0,1" group.byte 0x1880++0x3 line.long 0x0 "CTRL_CORE_PADCONF_WAKEUPEVENT_6,CTRL_CORE_PADCONF_WAKEUPEVENT_6" bitfld.long 0x0 0. " MCASP2_FSR_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 1. " MCASP2_AXR0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 2. " MCASP2_AXR1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 3. " MCASP2_AXR2_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 4. " MCASP2_AXR3_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 5. " MCASP2_AXR4_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 6. " MCASP2_AXR5_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 7. " MCASP2_AXR6_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 8. " MCASP2_AXR7_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 9. " MCASP3_ACLKX_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 10. " MCASP3_FSX_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 11. " MCASP3_AXR0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 12. " MCASP3_AXR1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 13. " MCASP4_ACLKX_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 14. " MCASP4_FSX_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 15. " MCASP4_AXR0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 16. " MCASP4_AXR1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 17. " MCASP5_ACLKX_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 18. " MCASP5_FSX_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 19. " MCASP5_AXR0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 20. " MCASP5_AXR1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 21. " MMC1_CLK_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 22. " MMC1_CMD_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 23. " MMC1_DAT0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 24. " MMC1_DAT1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 25. " MMC1_DAT2_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26. " MMC1_DAT3_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 27. " MMC1_SDCD_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 28. " MMC1_SDWP_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 29. " GPIO6_10_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 30. " GPIO6_11_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 31. " MMC3_CLK_DUPLICATEWAKEUPEVENT ," "0,1" group.byte 0x1884++0x3 line.long 0x0 "CTRL_CORE_PADCONF_WAKEUPEVENT_7,CTRL_CORE_PADCONF_WAKEUPEVENT_7" bitfld.long 0x0 0. " MMC3_CMD_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 1. " MMC3_DAT0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 2. " MMC3_DAT1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 3. " MMC3_DAT2_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 4. " MMC3_DAT3_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 5. " MMC3_DAT4_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 6. " MMC3_DAT5_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 7. " MMC3_DAT6_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 8. " MMC3_DAT7_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 9. " SPI1_SCLK_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 10. " SPI1_D1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 11. " SPI1_D0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 12. " SPI1_CS0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 13. " SPI1_CS1_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 14. " SPI1_CS2_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 15. " SPI1_CS3_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 16. " SPI2_SCLK_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 17. " SPI2_D1_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 18. " SPI2_D0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 19. " SPI2_CS0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 20. " DCAN1_TX_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 21. " DCAN1_RX_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 22. " DCAN2_TX_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 23. " DCAN2_RX_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 24. " UART1_RXD_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 25. " UART1_TXD_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 26. " UART1_CTSN_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 27. " UART1_RTSN_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 28. " UART2_RXD_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 29. " UART2_TXD_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 30. " UART2_CTSN_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 31. " UART2_RTSN_DUPLICATEWAKEUPEVENT ," "0,1" group.byte 0x1888++0x3 line.long 0x0 "CTRL_CORE_PADCONF_WAKEUPEVENT_8,CTRL_CORE_PADCONF_WAKEUPEVENT_8" bitfld.long 0x0 0. " I2C1_SDA_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 1. " I2C1_SCL_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 2. " I2C2_SDA_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 3. " I2C2_SCL_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 4. " I2C3_SDA_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 5. " I2C3_SCL_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 6. " WAKEUP0_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 7. " WAKEUP1_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 8. " WAKEUP2_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 9. " WAKEUP3_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 10. " TDI_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 11. " TDO_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 12. " RTCK_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 13. " EMU0_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 14. " EMU1_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 15. " EMU2_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 16. " EMU3_DUPLICATEWAKEUPEVENT ," "0,1" bitfld.long 0x0 17. " EMU4_DUPLICATEWAKEUPEVENT ," "0,1" textline " " bitfld.long 0x0 18. " NMIN_DUPLICATEWAKEUPEVENT ," "0,1" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0x1B08++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_2,This register contains the AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_NOM. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_GPU_2 ,AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL [4:0] LDOVBBGPU_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1B0C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_3,This register contains the AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_OD. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_GPU_3 ,AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL [4:0] LDOVBBGPU_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1B10++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_4,This register contains the AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_HIGH. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_GPU_4 ,AVS Class 0 voltage value for the vdd_gpu voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL [4:0] LDOVBBGPU_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1B20++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_2,This register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_NOM. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_MPU_2 ,AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_NOM. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_NOM which has to be written to theCTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL [4:0] LDOVBBMPU_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1B24++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_3,This register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_OD. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_MPU_3 ,AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_OD. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_OD which has to be written to theCTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL [4:0] LDOVBBMPU_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1B28++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_4,This register contains the AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_HIGH. This register also stores information about ABB configuration for that OPP." hexmask.long.word 0x0 0.--11. 1. " STD_FUSE_OPP_VMIN_MPU_4 ,AVS Class 0 voltage value for the vdd_mpu voltage rail when running at OPP_HIGH. To get the actual value in mV, the value read from this bit field must be converted to decimal value." hexmask.long.byte 0x0 12.--19. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 20.--24. " VSETABB ,This bit field shows the ABB LDO target value for OPP_HIGH which has to be written to theCTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL [4:0] LDOVBBMPU_FBB_VSET_OUT bit field, if ABB is enabled." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 25. " ABBEN ," "0,1" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1B38++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_0,Standard Fuse OPP VDD_GPU [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_DSPEVE_LVT_0 ," group.byte 0x1B3C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_1,Standard Fuse OPP VDD_GPU [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_DSPEVE_LVT_1 ," group.byte 0x1B40++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_2,Standard Fuse OPP VDD_GPU [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_DSPEVE_LVT_2 ," group.byte 0x1B44++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_3,Standard Fuse OPP VDD_GPU [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_DSPEVE_LVT_3 ," group.byte 0x1B48++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_DSPEVE_LVT_4,Standard Fuse OPP VDD_GPU [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_DSPEVE_LVT_4 ," group.byte 0x1B4C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_0,Standard Fuse OPP VDD_IVA [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_IVA_LVT_0 ," group.byte 0x1B50++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_1,Standard Fuse OPP VDD_IVA [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_IVA_LVT_1 ," group.byte 0x1B54++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_2,Standard Fuse OPP VDD_IVA [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_IVA_LVT_2 ," group.byte 0x1B58++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_3,Standard Fuse OPP VDD_IVA [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_IVA_LVT_3 ," group.byte 0x1B5C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_IVA_LVT_4,Standard Fuse OPP VDD_IVA [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_IVA_LVT_4 ," group.byte 0x1B60++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_0,Standard Fuse OPP VDD_CORE [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_CORE_LVT_0 ," group.byte 0x1B64++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_1,Standard Fuse OPP VDD_CORE [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_CORE_LVT_1 ," group.byte 0x1B68++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_2,Standard Fuse OPP VDD_CORE [95:64]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_CORE_LVT_2 ," group.byte 0x1B6C++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_3,Standard Fuse OPP VDD_CORE [127:96]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_CORE_LVT_3 ," group.byte 0x1B70++0x3 line.long 0x0 "CTRL_CORE_STD_FUSE_OPP_VDD_CORE_LVT_4,Standard Fuse OPP VDD_CORE [159:128]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_OPP_VDD_CORE_LVT_4 ," group.byte 0x1B74++0x3 line.long 0x0 "CTRL_CORE_LDOSRAM_CORE_4_VOLTAGE_CTRL,CORE 4th SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMCORE_4_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMCORE_4_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMCORE_4_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMCORE_4_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMCORE_4_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMCORE_4_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x1B78++0x3 line.long 0x0 "CTRL_CORE_LDOSRAM_CORE_5_VOLTAGE_CTRL,CORE 5th SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMCORE_5_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMCORE_5_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMCORE_5_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMCORE_5_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMCORE_5_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMCORE_5_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x1B7C++0x3 line.long 0x0 "CTRL_CORE_LDOSRAM_DSPEVE_2_VOLTAGE_CTRL,DSPEVE 2nd SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMDSPEVE_2_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMDSPEVE_2_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMDSPEVE_2_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMDSPEVE_2_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMDSPEVE_2_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMDSPEVE_2_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x1C04++0x3 line.long 0x0 "CTRL_CORE_SMA_SW_2,OCP Spare Register" hexmask.long 0x0 0.--31. 1. " SMA_SW_2 ,OCP spare register" group.byte 0x1C08++0x3 line.long 0x0 "CTRL_CORE_SMA_SW_3,OCP Spare Register" hexmask.long 0x0 0.--31. 1. " SMA_SW_3 ,OCP spare register" group.byte 0x1C14++0x3 line.long 0x0 "CTRL_CORE_SMA_SW_6,OCP Spare Register" bitfld.long 0x0 0. " MUXSEL_32K_CLKIN ,Setting for mux to select 32KHz clock input to PRCM. This bit must NOT be modified by software. The 32kHz clock selection is done through the device sysboot[9:8] signals." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ," textline " " bitfld.long 0x0 8. " RMII_CLK_SETTING ,RMII CLK setting 0x0: Internal clock from DPLL_GMAC 0x1: External clock from RMII_MHZ_50_CLK pin" "0,1" hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " PCIE_TX_RX_CONTROL ,PCIe RX and TX control of ACSPCIe. 0x0: ACSPCIe Power Down Mode 0x1: ACSPCIe TX Mode 0x2: ACSPCIe RX Mode 0x3: Reserved" "0,1,2,3" hexmask.long.word 0x0 18.--26. 1. " RESERVED ," textline " " bitfld.long 0x0 27.--28. " PLLEN_CONTROL ,PLLEN control setting. Bit [28]  Controls the CLKOUT of DPLL_USB_OTG. 0x0: CLKOUT is disabled 0x1: CLKOUT is enabled Bit [27]  Controls the CLKOUT of DPLL_SATA 0x0: CLKOUT is disabled 0x1: CLKOUT is enabled" "0,1,2,3" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x1C18++0x3 line.long 0x0 "CTRL_CORE_SMA_SW_7,OCP Spare Register" bitfld.long 0x0 0. " PCIE_SS2_AXI2OCP_LEGACY_MODE_ENABLE ,PCIe_SS2 AXI2OCP legacy mode enable" "0,1" bitfld.long 0x0 1. " PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE ,PCIe_SS1 AXI2OCP legacy mode enable" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " EDMA_TC1_WR_MMU_ROUTE_ENABLE ,EDMA TC1 WR traffic MMU route enable" "0,1" textline " " bitfld.long 0x0 9. " EDMA_TC0_WR_MMU_ROUTE_ENABLE ,EDMA TC0 WR traffic MMU route enable" "0,1" bitfld.long 0x0 10. " EDMA_TC1_RD_MMU_ROUTE_ENABLE ,EDMA TC1 RD traffic MMU route enable" "0,1" textline " " bitfld.long 0x0 11. " EDMA_TC0_RD_MMU_ROUTE_ENABLE ,EDMA TC0 RD traffic MMU route enable" "0,1" bitfld.long 0x0 12. " PCIE_SS2_MMU_ROUTE_ENABLE ,PCIe_SS2 MMU route enable" "0,1" textline " " bitfld.long 0x0 13. " PCIE_SS1_MMU_ROUTE_ENABLE ,PCIe_SS1 MMU route enable" "0,1" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16. " MMU1_ABORT_ENABLE ,MMU1 abort enable" "0,1" bitfld.long 0x0 17. " MMU2_ABORT_ENABLE ,MMU2 abort enable" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x1C1C++0x3 line.long 0x0 "CTRL_CORE_SMA_SW_8,Test control inputs used by the module" hexmask.long 0x0 0.--31. 1. " PCIE_PLL_TEST_INPUT_1 ,Test control inputs used by the module" group.byte 0x1C20++0x3 line.long 0x0 "CTRL_CORE_SMA_SW_9,Test control inputs used by the module" hexmask.long 0x0 0.--31. 1. " PCIE_PLL_TEST_INPUT_2 ,Test control inputs used by the module" group.byte 0x1C24++0x3 line.long 0x0 "CTRL_CORE_PCIESS1_PCS1,CTRL_CORE_PCIESS1_PCS1" bitfld.long 0x0 0.--3. " PCIESS1_PCS_DET_DELAY ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0 4.--11. 1. " PCIESS1_PCS_CFG_HOLDOFF ," textline " " hexmask.long.word 0x0 12.--21. 1. " PCIESS1_PCS_ERR_BIT_EN ," hexmask.long.word 0x0 22.--31. 1. " PCIESS1_PCS_TEST_TXDATA ," group.byte 0x1C28++0x3 line.long 0x0 "CTRL_CORE_PCIESS1_PCS2,CTRL_CORE_PCIESS1_PCS2" bitfld.long 0x0 0. " PCIESS1_PCS_SHORT_TIMES ," "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2.--3. " PCIESS1_PCS_ERR_LN_EN ," "0,1,2,3" bitfld.long 0x0 4. " PCIESS1_PCS_TEST_MODE ," "0,1" textline " " bitfld.long 0x0 5. " PCIESS1_PCS_L1_SLEEP ," "0,1" bitfld.long 0x0 6.--7. " PCIESS1_PCS_ERR_MODE ," "0,1,2,3" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " PCIESS1_PCS_TEST_LSEL ," "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12.--14. " PCIESS1_PCS_TEST_OSEL ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--18. " PCIESS1_PCS_CFG_EQ_INIT ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 19.--22. " PCIESS1_PCS_CFG_EQ_HOLD ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 23.--26. " PCIESS1_PCS_CFG_EQ_FUNC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 27.--31. " PCIESS1_PCS_CFG_SYNC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x1C2C++0x3 line.long 0x0 "CTRL_CORE_PCIESS2_PCS1,CTRL_CORE_PCIESS2_PCS1" bitfld.long 0x0 0.--3. " PCIESS2_PCS_DET_DELAY ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0 4.--11. 1. " PCIESS2_PCS_CFG_HOLDOFF ," textline " " hexmask.long.word 0x0 12.--21. 1. " PCIESS2_PCS_ERR_BIT_EN ," hexmask.long.word 0x0 22.--31. 1. " PCIESS2_PCS_TEST_TXDATA ," group.byte 0x1C30++0x3 line.long 0x0 "CTRL_CORE_PCIESS2_PCS2,CTRL_CORE_PCIESS2_PCS2" bitfld.long 0x0 0. " PCIESS2_PCS_SHORT_TIMES ," "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2.--3. " PCIESS2_PCS_ERR_LN_EN ," "0,1,2,3" bitfld.long 0x0 4. " PCIESS2_PCS_TEST_MODE ," "0,1" textline " " bitfld.long 0x0 5. " PCIESS2_PCS_L1_SLEEP ," "0,1" bitfld.long 0x0 6.--7. " PCIESS2_PCS_ERR_MODE ," "0,1,2,3" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " PCIESS2_PCS_TEST_LSEL ," "0,1" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12.--14. " PCIESS2_PCS_TEST_OSEL ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--18. " PCIESS2_PCS_CFG_EQ_INIT ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 19.--22. " PCIESS2_PCS_CFG_EQ_HOLD ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 23.--26. " PCIESS2_PCS_CFG_EQ_FUNC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 27.--31. " PCIESS2_PCS_CFG_SYNC ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x1C34++0x3 line.long 0x0 "CTRL_CORE_PCIE_PCS,CTRL_CORE_PCIE_PCS" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," hexmask.long.byte 0x0 16.--23. 1. " PCIESS_PCS_RC_DELAY_COUNT ,Set to 0x96 for proper functional and compliance-mode behavior on both PCIESS1 and PCIESS2." textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x1C38++0x3 line.long 0x0 "CTRL_CORE_PCIE_PCS_REVISION,pcs_revision" hexmask.long.tbyte 0x0 0.--19. 1. " RESERVED ," bitfld.long 0x0 20.--22. " PCIESS1_PCS_REVISION ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23.--25. " PCIESS2_PCS_REVISION ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x1C3C++0x3 line.long 0x0 "CTRL_CORE_PCIE_CONTROL,serdes control selection PCIE C0 (0 default) vs PCIE B1 (1)" bitfld.long 0x0 0. " PCIE_B0_B1_TSYNCEN ,0x0: PCIESS1 x1 Mode and/or PCIESS2 x1 Mode 0x1: PCIESS1 x2 Mode, PCIESS2 Unused" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " PCIE_B1C0_MODE_SEL ,0x0: PCIESS1 x1 Mode and/or PCIESS2 x1 Mode 0x1: PCIESS1 x2 Mode, PCIESS2 Unused" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1C40++0x3 line.long 0x0 "CTRL_CORE_PHY_POWER_PCIESS1,CTRL_CORE_PHY_POWER_PCIESS1" hexmask.long.word 0x0 0.--13. 1. " RESERVED ,Reserved" hexmask.long.byte 0x0 14.--21. 1. " PCIESS1_PWRCTL_CMD ,Powers up/down the PCIESS1_PHY_TX and PCIESS1_PHY_RX modules. 0x0: Powers down PCIESS1_PHY_TX and PCIESS1_PHY_RX 0x1: Powers up PCIESS1_PHY_RX 0x2: Powers up PCIESS1_PHY_TX 0x3: Powers up PCIESS1_PHY_TX and PCIESS1_PHY_RX 0x4-0xFF: Reserved" textline " " hexmask.long.word 0x0 22.--31. 1. " PCIESS1_PWRCTL_CLKFREQ ,Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." group.byte 0x1C44++0x3 line.long 0x0 "CTRL_CORE_PHY_POWER_PCIESS2,CTRL_CORE_PHY_POWER_PCIESS2" hexmask.long.word 0x0 0.--13. 1. " RESERVED ,Reserved" hexmask.long.byte 0x0 14.--21. 1. " PCIESS2_PWRCTL_CMD ,Powers up/down the PCIESS2_PHY_TX and PCIESS2_PHY_RX modules. 0x0: Powers down PCIESS2_PHY_TX and PCIESS2_PHY_RX 0x1: Powers up PCIESS2_PHY_RX 0x2: Powers up PCIESS2_PHY_TX 0x3: Powers up PCIESS2_PHY_TX and PCIESS2_PHY_RX 0x4-0xFF: Reserved" textline " " hexmask.long.word 0x0 22.--31. 1. " PCIESS2_PWRCTL_CLKFREQ ,Frequency of SYSCLK1 in MHz (rounded). For example, for 20MHz, program 0x14." width 0x0B tree.end tree "CTRL_MODULE_WKUP" base ad:0x4AE0C000 width 38. group.byte 0x100++0x3 line.long 0x0 "CTRL_WKUP_SEC_CTRL,Control Register" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " SECURE_EMIF_CONFIG_RO_EN ,Access mode for registers: CTRL_WKUP_EMIF1_SDRAM_CONFIG CTRL_WKUP_EMIF2_SDRAM_CONFIG 0x0 = These registers are RW 0x1 = These registers are RO" "0,1" textline " " hexmask.long 0x0 5.--30. 1. " RESERVED ," bitfld.long 0x0 31. " SECCTRLWRDISABLE ,Control Register write disable control. 0x0 = Write in this register is allowed 0x1 = Write in this register is forbidden" "0,1" group.byte 0x108++0x3 line.long 0x0 "CTRL_WKUP_SEC_TAP,TAP controllers register." bitfld.long 0x0 0. " DAP_TAPENABLE ,DAP TAP control" "0,1" bitfld.long 0x0 1. " DSP1_TAPENABLE ,DSP1 TAP control" "0,1" textline " " bitfld.long 0x0 2. " IPU1_TAPENABLE ,IPU1 TAP control" "0,1" bitfld.long 0x0 3. " P1500_ENABLE ,P1500 access enable" "0,1" textline " " bitfld.long 0x0 4. " IEEE1500_ENABLE ,IEEE1500 and P1500 access enable" "0,1" bitfld.long 0x0 5.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 9. " MPUGLOBALDEBUG_ENABLE ,MPU TAP control" "0,1" bitfld.long 0x0 10. " IVA_TAPENABLE ,IVA TAP control" "0,1" textline " " bitfld.long 0x0 11. " JTAGEXT_TAPENABLE ,External JTAG expansion TAP control." "0,1" bitfld.long 0x0 12. " DSP2_TAPENABLE ,DSP2 TAP control" "0,1" textline " " bitfld.long 0x0 13. " IPU2_TAPENABLE ,IPU2 TAP control" "0,1" hexmask.long.word 0x0 14.--25. 1. " RESERVED ," textline " " bitfld.long 0x0 26. " RESERVED ,Reserved. This bit must not be modified." "0,1" bitfld.long 0x0 27.--30. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 31. " SECTAPWR_DISABLE ,TAP controllers register write disable control" "0,1" group.byte 0x10C++0x3 line.long 0x0 "CTRL_WKUP_OCPREG_SPARE,OCP Spare Register" bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " OCPREG_SPARE1 ,OCP spare register 1" "0,1" textline " " bitfld.long 0x0 2. " OCPREG_SPARE2 ,OCP spare register 2" "0,1" bitfld.long 0x0 3. " OCPREG_SPARE3 ,OCP spare register 3" "0,1" textline " " bitfld.long 0x0 4. " OCPREG_SPARE4 ,OCP spare register 4" "0,1" bitfld.long 0x0 5. " OCPREG_SPARE5 ,OCP spare register 5" "0,1" textline " " bitfld.long 0x0 6. " OCPREG_SPARE6 ,OCP spare register 6" "0,1" bitfld.long 0x0 7. " OCPREG_SPARE7 ,OCP spare register 7" "0,1" textline " " bitfld.long 0x0 8. " OCPREG_SPARE8 ,OCP spare register 8" "0,1" bitfld.long 0x0 9. " OCPREG_SPARE9 ,OCP spare register 9" "0,1" textline " " bitfld.long 0x0 10. " OCPREG_SPARE10 ,OCP spare register 10" "0,1" bitfld.long 0x0 11. " OCPREG_SPARE11 ,OCP spare register 11" "0,1" textline " " bitfld.long 0x0 12. " OCPREG_SPARE12 ,OCP spare register 12" "0,1" bitfld.long 0x0 13. " OCPREG_SPARE13 ,OCP spare register 13" "0,1" textline " " bitfld.long 0x0 14. " OCPREG_SPARE14 ,OCP spare register 14" "0,1" bitfld.long 0x0 15. " OCPREG_SPARE15 ,OCP spare register 15" "0,1" textline " " bitfld.long 0x0 16. " OCPREG_SPARE16 ,OCP spare register 16" "0,1" bitfld.long 0x0 17. " OCPREG_SPARE17 ,OCP spare register 17" "0,1" textline " " bitfld.long 0x0 18. " OCPREG_SPARE18 ,OCP spare register 18" "0,1" bitfld.long 0x0 19. " OCPREG_SPARE19 ,OCP spare register 19" "0,1" textline " " bitfld.long 0x0 20. " OCPREG_SPARE20 ,OCP spare register 20" "0,1" bitfld.long 0x0 21. " OCPREG_SPARE21 ,OCP spare register 21" "0,1" textline " " bitfld.long 0x0 22. " OCPREG_SPARE22 ,OCP spare register 22" "0,1" bitfld.long 0x0 23. " OCPREG_SPARE23 ,OCP spare register 23" "0,1" textline " " bitfld.long 0x0 24. " OCPREG_SPARE24 ,OCP spare register 24" "0,1" bitfld.long 0x0 25. " OCPREG_SPARE25 ,OCP spare register 25" "0,1" textline " " bitfld.long 0x0 26. " OCPREG_SPARE26 ,OCP spare register 26" "0,1" bitfld.long 0x0 27. " OCPREG_SPARE27 ,OCP spare register 27" "0,1" textline " " bitfld.long 0x0 28. " OCPREG_SPARE28 ,OCP spare register 28" "0,1" bitfld.long 0x0 29. " OCPREG_SPARE29 ,OCP spare register 29" "0,1" textline " " bitfld.long 0x0 30. " OCPREG_SPARE30 ,OCP spare register 30" "0,1" bitfld.long 0x0 31. " OCPREG_SPARE31 ,OCP spare register 31" "0,1" group.byte 0x110++0x3 line.long 0x0 "CTRL_WKUP_SECURE_EMIF1_SDRAM_CONFIG,EMIF1 SDRAM configuration register. Its values are exported to EMIF_SDRAM_CONFIG register at POR. For bit field descriptions see EMIF_SDRAM_CONFIG register in, EMIF Controller, in , Memory Subsystem. Write to this register is allowed if the [4] SECURE_EMIF_CONFIG_RO_EN bit is set to 0x0 (default)." bitfld.long 0x0 0.--2. " EMIF1_SDRAM_PAGESIZE ,Page Size." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " EMIF1_SDRAM_IBANK ,Internal Bank setup." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7.--9. " EMIF1_SDRAM_ROWSIZE ,Row Size." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 10.--13. " EMIF1_SDRAM_CL ,CAS Latency." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " EMIF1_SDRAM_CWL ,DDR3 CAS Write latency." "0,1,2,3" bitfld.long 0x0 18.--19. " EMIF1_SDRAM_DRIVE ,SDRAM drive strength." "0,1,2,3" textline " " bitfld.long 0x0 20. " EMIF1_SDRAM_DDR_DISABLE_DLL ,Disable DLL select." "0,1" bitfld.long 0x0 21.--22. " EMIF1_SDRAM_DYN_ODT ,DDR3 Dynamic ODT." "0,1,2,3" textline " " bitfld.long 0x0 23. " EMIF1_SDRAM_DDR2_DDQS ,DDR2 differential DQS enable." "0,1" bitfld.long 0x0 24.--26. " EMIF1_SDRAM_DDR_TERM ,DDR2 and DDR3 termination resistor value." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--28. " EMIF1_SDRAM_IBANK_POS ,Internal bank position." "0,1,2,3" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x118++0x3 line.long 0x0 "CTRL_WKUP_SECURE_EMIF2_SDRAM_CONFIG,EMIF2 SDRAM register. Its values are exported to EMIF_SDRAM_CONFIG register at POR. For bit field descriptions see EMIF_SDRAM_CONFIG register in, EMIF Controller, in , Memory Subsystem. Write to this register is allowed if the [4] SECURE_EMIF_CONFIG_RO_EN bit is set to 0x0 (default)." bitfld.long 0x0 0.--2. " EMIF2_SDRAM_PAGESIZE ,Page Size." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " EMIF2_SDRAM_IBANK ,Internal Bank setup." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7.--9. " EMIF2_SDRAM_ROWSIZE ,Row Size." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 10.--13. " EMIF2_SDRAM_CL ,CAS Latency." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " EMIF2_SDRAM_CWL ,DDR3 CAS Write latency." "0,1,2,3" bitfld.long 0x0 18.--19. " EMIF2_SDRAM_DRIVE ,SDRAM drive strength." "0,1,2,3" textline " " bitfld.long 0x0 20. " EMIF2_SDRAM_DDR_DISABLE_DLL ,Disable DLL select." "0,1" bitfld.long 0x0 21.--22. " EMIF2_SDRAM_DYN_ODT ,DDR3 Dynamic ODT." "0,1,2,3" textline " " bitfld.long 0x0 23. " EMIF2_SDRAM_DDR2_DDQS ,DDR2 differential DQS enable." "0,1" bitfld.long 0x0 24.--26. " EMIF2_SDRAM_DDR_TERM ,DDR2 and DDR3 termination resistor value." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--28. " EMIF2_SDRAM_IBANK_POS ,Internal bank position." "0,1,2,3" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x138++0x3 line.long 0x0 "CTRL_WKUP_STD_FUSE_USB_CONF,Standard Fuse conf [31:0]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long.word 0x0 0.--15. 1. " USB_VENDOR_ID ,USB Vendor Identification" hexmask.long.word 0x0 16.--31. 1. " USB_PROD_ID ,USB Product Identification" group.byte 0x13C++0x3 line.long 0x0 "CTRL_WKUP_STD_FUSE_CONF,Standard Fuse conf [63:32]. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." bitfld.long 0x0 0.--2. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " STD_FUSE_SGX540_3D_DISABLE ,Disable the 3D accelerator engine 0x1 = SGX is disabled 0x0 = SGX is enable" "0,1" textline " " bitfld.long 0x0 4. " STD_FUSE_SGX540_3D_CLOCK_SOURCE ,Functional clock selection for the 3D accelerator engine 0x0 = GPU is fully enabled (DPLL_CORE/PER) 0x1 = GPU is partially enabled (DPLL_PER/8 max)" "0,1" hexmask.long.byte 0x0 5.--11. 1. " RESERVED ," textline " " bitfld.long 0x0 12. " STD_FUSE_CH_SPEEDUP_DISABLE ,ROM code settings for configuration header block and speedup block. Only SW access (no hardware access). 0x0 = enables CH and speedup 0x1 = disables CH and speedup" "0,1" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " STD_FUSE_HDCP_ENABLE ,Enable hdcp 0x0 = enables hdcp 0x1 = disables hdcp" "0,1" bitfld.long 0x0 17. " RESERVED ," "0,1" textline " " bitfld.long 0x0 18. " STD_FUSE_EMIF1_DDR3_LPDDR2N ,EMIF1 DDR3 0x1 = DDR3 configured 0x0 = reserved" "0,1" bitfld.long 0x0 19. " STD_FUSE_EMIF1_INITREF_DEF_DIS ,Disable EMIF1 DDR refresh and initialization sequence 0x1 = refresh and initialization sequence are disabled 0x0 = refresh and initialization sequence are enabled" "0,1" textline " " bitfld.long 0x0 20. " STD_FUSE_EMIF2_DDR3_LPDDR2N ,EMIF2 DDR3 0x1= DDR3 configured 0x0 = reserved" "0,1" bitfld.long 0x0 21. " STD_FUSE_EMIF2_INITREF_DEF_DIS ,Disable EMIF2 DDR refresh and initialization sequence 0x1 = refresh and initialization sequence are disabled 0x0 = refresh and initialization sequence are enabled" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x144++0x3 line.long 0x0 "CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT,SLICE register for emif1 and emif2" bitfld.long 0x0 0. " EMIF1_EN_SLICE_0 ,Enable command PHY 0. 0x1 is the mandatory setting if DDR3 is used. EMIF1_EN_SLICE_0 and EMIF1_EN_SLICE_1 have to be programmed with the same value." "0,1" bitfld.long 0x0 1. " EMIF1_EN_SLICE_1 ,Enable command PHY 1. 0x1 is the mandatory setting if DDR3 is used. EMIF1_EN_SLICE_0 and EMIF1_EN_SLICE_1 have to be programmed with the same value." "0,1" textline " " bitfld.long 0x0 2. " EMIF1_EN_SLICE_2 ,Enable command PHY 2. When using DDR3 this bit can be set to 0x0 or 0x1. For lower power consumption 0x0 is used." "0,1" bitfld.long 0x0 3. " EMIF1_DFI_CLOCK_PHASE_CTRL ,EMIF_FICLK clock phase control (shifting by 1800). For normal operation this bit must always be set to 0x0 (disabled)." "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5.--6. " EMIF1_PHY_RD_LOCAL_ODT ,Control of ODT (on  die termination) settings for the device DDR I/Os. ODT is enabled only during read operations when termination is required. 0x0 = ODT disabled 0x1= 60 Ohms 0x2 = 80 Ohms 0x3 =120 Ohms" "0,1,2,3" textline " " bitfld.long 0x0 7. " EMIF1_SDRAM_DISABLE_RESET ,DDR3 SDRAM reset disable. 0x0 = DDR3 SDRAM reset signal is enabled. It can be asserted by EMIF 0x1 = DDR3 SDRAM reset signal is disabled. It is forbidden to EMIF to assert it." "0,1" bitfld.long 0x0 8. " RESERVED ," "0,1" textline " " bitfld.long 0x0 9.--11. " EMIF1_REG_PHY_OUTPUT_STATUS_SELECT ,Selects the status to be observed on the outputs of the DDR PHYs through 0x0 = selects phy_reg_rdlvl_start_ratio[7:0] 0x1 = selects phy_reg_rdlvl_start_ratio[15:8] 0x2 = selects phy_reg_rdlvl_end_ratio[7:0] 0x3 = selects phy_reg_rdlvl_end_ratio[15:8]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. " EMIF1_REG_PHY_ALL_DQ_MPR_RD_RESP ,Analysis method of DQ bits during read leveling. 0x0: if the DRAM provides a read response on only one DQ bit (this can be any bit, since in this mode all 8 DQ bits are OR-ed together). This is the default setting and works with all memory types (memories send responses on all DQ bits or on a single DQ bit). 0x1: if the DRAM provides a read response on all DQ bits." "0,1" textline " " bitfld.long 0x0 13. " EMIF1_REG_PHY_SEL_LOGIC ,Selects an algorithm for read leveling. The use of algorithm 1 (set by default) is recommended. 0x0 = Algorithm 1 is used 0x1 = Algorithm 2 is used" "0,1" bitfld.long 0x0 14.--15. " EMIF1_REG_PHY_NUM_OF_SAMPLES ,Controls the number of DQ samples required for read leveling. The recommended setting for full leveling is 0x3 (128 samples) and for incremental leveling is 0x0 (4 samples). 0x0 = 4 samples 0x1 = 8 samples. 0x2 = 16 samples 0x3 = 128 samples" "0,1,2,3" textline " " bitfld.long 0x0 16. " EMIF1_EN_ECC ,EMIF1 ECC enable 0x0 = ECC is disabled 0x1 = ECC is enabled" "0,1" bitfld.long 0x0 17. " EMIF1_NARROW_ONLY ,EMIF1 operates in narrow mode, to allow for data macros to be powered down to save power 0x0 = narrow mode disabled 0x1 = narrow mode enabled" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x148++0x3 line.long 0x0 "CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT,SLICE register for emif1 and emif2" bitfld.long 0x0 0. " EMIF2_EN_SLICE_0 ,Enable command PHY 0. 0x1 is the mandatory setting if DDR3 is used. EMIF2_EN_SLICE_0 and EMIF2_EN_SLICE_1 have to be programmed with the same value." "0,1" bitfld.long 0x0 1. " EMIF2_EN_SLICE_1 ,Enable command PHY 1. 0x1 is the mandatory setting if DDR3 is used. EMIF2_EN_SLICE_0 and EMIF2_EN_SLICE_1 have to be programmed with the same value." "0,1" textline " " bitfld.long 0x0 2. " EMIF2_EN_SLICE_2 ,Enable command PHY 2. When using DDR3 this bit can be set to 0x0 or 0x1. For lower power consumption 0x0 is used." "0,1" bitfld.long 0x0 3. " EMIF2_DFI_CLOCK_PHASE_CTRL ,EMIF_FICLK clock phase control (shifting by 1800). For normal operation this bit must always be set to 0x0 (disabled)." "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5.--6. " EMIF2_PHY_RD_LOCAL_ODT ,Control of ODT (on  die termination) settings for the device DDR I/Os. ODT is enabled only during read operations when termination is required. 0x0 = ODT disabled 0x1= 60 Ohms 0x2 = 80 Ohms 0x3 =120 Ohms" "0,1,2,3" textline " " bitfld.long 0x0 7. " EMIF2_SDRAM_DISABLE_RESET ,DDR3 SDRAM reset disable. 0x0 = DDR3 SDRAM reset signal is enabled. It can be asserted by EMIF 0x1 = DDR3 SDRAM reset signal is disabled. It is forbidden to EMIF to assert it." "0,1" bitfld.long 0x0 8. " RESERVED ," "0,1" textline " " bitfld.long 0x0 9.--11. " EMIF2_REG_PHY_OUTPUT_STATUS_SELECT ,Selects the status to be observed on the outputs of the DDR PHYs through 0x0 = selects phy_reg_rdlvl_start_ratio[7:0] 0x1 = selects phy_reg_rdlvl_start_ratio[15:8] 0x2 = selects phy_reg_rdlvl_end_ratio[7:0] 0x3 = selects phy_reg_rdlvl_end_ratio[15:8]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12. " EMIF2_REG_PHY_ALL_DQ_MPR_RD_RESP ,Analysis method of DQ bits during read leveling. 0x0: if the DRAM provides a read response on only one DQ bit (this can be any bit, since in this mode all 8 DQ bits are OR-ed together). This is the default setting and works with all memory types (memories send responses on all DQ bits or on a single DQ bit). 0x1: if the DRAM provides a read response on all DQ bits." "0,1" textline " " bitfld.long 0x0 13. " EMIF2_REG_PHY_SEL_LOGIC ,Selects an algorithm for read leveling. The use of algorithm 1 (set by default) is recommended. 0x0 = Algorithm 1 is used 0x1 = Algorithm 2 is used" "0,1" bitfld.long 0x0 14.--15. " EMIF2_REG_PHY_NUM_OF_SAMPLES ,Controls the number of DQ samples required for read leveling. The recommended setting for full leveling is 0x3 (128 samples) and for incremental leveling is 0x0 (4 samples). 0x0 = 4 samples 0x1 = 8 samples. 0x2 = 16 samples 0x3 = 128 samples" "0,1,2,3" textline " " bitfld.long 0x0 16. " RESERVED ," "0,1" bitfld.long 0x0 17. " EMIF2_NARROW_ONLY ,EMIF2 operates in narrow mode, to allow for data macros to be powered down to save power 0x0 = narrow mode disabled 0x1 = narrow mode enabled" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14C++0x3 line.long 0x0 "CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT_1,CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT_1" hexmask.long 0x0 0.--31. 1. " EMIF1_PHY_REG_READ_DATA_EYE_LVL ," group.byte 0x150++0x3 line.long 0x0 "CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT_2,CTRL_WKUP_EMIF2_SDRAM_CONFIG_EXT_2" hexmask.long 0x0 0.--31. 1. " EMIF2_PHY_REG_READ_DATA_EYE_LVL ," group.byte 0x154++0x3 line.long 0x0 "CTRL_WKUP_LDOVBB_GPU_VOLTAGE_CTRL,GPU Voltage Body Bias LDO Control register" bitfld.long 0x0 0.--4. " LDOVBBGPU_FBB_VSET_OUT ,Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_GPU_x[24:20] VSETABB bit fields. This value applies if LDOVBBGPU_FBB_MUX_CTRL is set to 0x1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOVBBGPU_FBB_VSET_IN ,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOVBBGPU_FBB_MUX_CTRL ,Override control of EFUSE Forward Body Bias voltage value 0x0 = efuse value is used 0x1 = override value is used" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x158++0x3 line.long 0x0 "CTRL_WKUP_LDOVBB_MPU_VOLTAGE_CTRL,MPU Voltage Body Bias LDO Control register" bitfld.long 0x0 0.--4. " LDOVBBMPU_FBB_VSET_OUT ,Override value for Forward Body Bias voltage. If ABB is used, depending on the OPP this bit field should be loaded with a value read from one of the CTRL_CORE_STD_FUSE_OPP_VMIN_MPU_x[24:20] VSETABB bit fields. This value applies if LDOVBBMPU_FBB_MUX_CTRL is set to 0x1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOVBBMPU_FBB_VSET_IN ,EFUSE Forward Body Bias voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOVBBMPU_FBB_MUX_CTRL ,Override control of EFUSE Forward Body Bias voltage value 0x0 = efuse value is used 0x1 = override value is used" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x15C++0x3 line.long 0x0 "CTRL_WKUP_LDOSRAM_GPU_VOLTAGE_CTRL,GPU SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMGPU_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMGPU_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMGPU_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMGPU_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMGPU_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMGPU_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x160++0x3 line.long 0x0 "CTRL_WKUP_LDOSRAM_MPU_VOLTAGE_CTRL,MPU SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMMPU_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMMPU_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMMPU_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMMPU_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMMPU_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMMPU_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x164++0x3 line.long 0x0 "CTRL_WKUP_LDOSRAM_CORE_VOLTAGE_CTRL,Core SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMCORE_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMCORE_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMCORE_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMCORE_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMCORE_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMCORE_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x168++0x3 line.long 0x0 "CTRL_WKUP_LDOSRAM_MPU_2_VOLTAGE_CTRL,MPU 2nd SRAM LDO Control register" bitfld.long 0x0 0.--4. " LDOSRAMMPU_2_ACTMODE_VSET_OUT ,Override value for Active Mode Voltage value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--9. " LDOSRAMMPU_2_ACTMODE_VSET_IN ,EFUSE Active Mode Voltage value (vset[4:0])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 10. " LDOSRAMMPU_2_ACTMODE_MUX_CTRL ,Override control of EFUSE Active Mode Voltage value" "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " LDOSRAMMPU_2_RETMODE_VSET_OUT ,Override value for Retention Mode Voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21.--25. " LDOSRAMMPU_2_RETMODE_VSET_IN ,EFUSE Retention Mode Voltage value (vset[9:5])" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 26. " LDOSRAMMPU_2_RETMODE_MUX_CTRL ,Override control of EFUSE Retention Mode Voltage value" "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x200++0x3 line.long 0x0 "CTRL_WKUP_STD_FUSE_DIE_ID_0,Die ID Register : Part 0. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_DIE_ID_0 ," group.byte 0x204++0x3 line.long 0x0 "CTRL_WKUP_ID_CODE,ID_CODE Key Register" hexmask.long 0x0 0.--31. 1. " STD_FUSE_IDCODE ," group.byte 0x208++0x3 line.long 0x0 "CTRL_WKUP_STD_FUSE_DIE_ID_1,Die ID Register : Part 1. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_DIE_ID_1 ," group.byte 0x20C++0x3 line.long 0x0 "CTRL_WKUP_STD_FUSE_DIE_ID_2,Die ID Register : Part 2. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_DIE_ID_2 ," group.byte 0x210++0x3 line.long 0x0 "CTRL_WKUP_STD_FUSE_DIE_ID_3,Die ID Register : Part 3. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_DIE_ID_3 ," group.byte 0x214++0x3 line.long 0x0 "CTRL_WKUP_STD_FUSE_PROD_ID_0,Prod ID Register : Part 0. Register shows part of the chip eFuse configuration on the OCP interface. Reading at the address of one of these registers provides a direct view into a part of the eFuse chain." hexmask.long 0x0 0.--31. 1. " STD_FUSE_PROD_ID ," group.byte 0x5AC++0x3 line.long 0x0 "CTRL_WKUP_CONTROL_XTAL_OSCILLATOR,XTAL OSCILLATOR control" hexmask.long 0x0 0.--27. 1. " RESERVED ," bitfld.long 0x0 28. " OSCILLATOR1_OS_OUT ,Oscillator output of OSC1 0x0 = low to high transition in BOOST mode 0x1 = BOOST is disabled" "0,1" textline " " bitfld.long 0x0 29. " OSCILLATOR1_BOOST ,Fast startup control of OSC1 0x0 = Fast startup is disabled 0x1 = Fast startup is enabled" "0,1" bitfld.long 0x0 30. " OSCILLATOR0_OS_OUT ,Oscillator output of OSC0 0x0 = low to high transition in BOOST mode 0x1 = BOOST is disabled" "0,1" textline " " bitfld.long 0x0 31. " OSCILLATOR0_BOOST ,Fast startup control of OSC0 0x0 = Fast startup is disabled 0x1 = Fast startup is enabled" "0,1" group.byte 0x5C8++0x3 line.long 0x0 "CTRL_WKUP_EFUSE_1,EFUSE compensation 1" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " DDRDIFF_PTV_EAST_SIDE_P0 ," "0,1" textline " " bitfld.long 0x0 9. " DDRDIFF_PTV_EAST_SIDE_P1 ," "0,1" bitfld.long 0x0 10. " DDRDIFF_PTV_EAST_SIDE_P2 ," "0,1" textline " " bitfld.long 0x0 11. " DDRDIFF_PTV_EAST_SIDE_P3 ," "0,1" bitfld.long 0x0 12. " DDRDIFF_PTV_EAST_SIDE_P4 ," "0,1" textline " " bitfld.long 0x0 13. " DDRDIFF_PTV_EAST_SIDE_P5 ," "0,1" bitfld.long 0x0 14. " DDRDIFF_PTV_EAST_SIDE_N0 ," "0,1" textline " " bitfld.long 0x0 15. " DDRDIFF_PTV_EAST_SIDE_N1 ," "0,1" bitfld.long 0x0 16. " DDRDIFF_PTV_EAST_SIDE_N2 ," "0,1" textline " " bitfld.long 0x0 17. " DDRDIFF_PTV_EAST_SIDE_N3 ," "0,1" bitfld.long 0x0 18. " DDRDIFF_PTV_EAST_SIDE_N4 ," "0,1" textline " " bitfld.long 0x0 19. " DDRDIFF_PTV_EAST_SIDE_N5 ," "0,1" bitfld.long 0x0 20. " DDRDIFF_PTV_NORTH_SIDE_P0 ," "0,1" textline " " bitfld.long 0x0 21. " DDRDIFF_PTV_NORTH_SIDE_P1 ," "0,1" bitfld.long 0x0 22. " DDRDIFF_PTV_NORTH_SIDE_P2 ," "0,1" textline " " bitfld.long 0x0 23. " DDRDIFF_PTV_NORTH_SIDE_P3 ," "0,1" bitfld.long 0x0 24. " DDRDIFF_PTV_NORTH_SIDE_P4 ," "0,1" textline " " bitfld.long 0x0 25. " DDRDIFF_PTV_NORTH_SIDE_P5 ," "0,1" bitfld.long 0x0 26. " DDRDIFF_PTV_NORTH_SIDE_N0 ," "0,1" textline " " bitfld.long 0x0 27. " DDRDIFF_PTV_NORTH_SIDE_N1 ," "0,1" bitfld.long 0x0 28. " DDRDIFF_PTV_NORTH_SIDE_N2 ," "0,1" textline " " bitfld.long 0x0 29. " DDRDIFF_PTV_NORTH_SIDE_N3 ," "0,1" bitfld.long 0x0 30. " DDRDIFF_PTV_NORTH_SIDE_N4 ," "0,1" textline " " bitfld.long 0x0 31. " DDRDIFF_PTV_NORTH_SIDE_N5 ," "0,1" group.byte 0x5CC++0x3 line.long 0x0 "CTRL_WKUP_EFUSE_2,EFUSE compensation 2" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " DDRDIFF_PTV_WEST_SIDE_P0 ," "0,1" textline " " bitfld.long 0x0 9. " DDRDIFF_PTV_WEST_SIDE_P1 ," "0,1" bitfld.long 0x0 10. " DDRDIFF_PTV_WEST_SIDE_P2 ," "0,1" textline " " bitfld.long 0x0 11. " DDRDIFF_PTV_WEST_SIDE_P3 ," "0,1" bitfld.long 0x0 12. " DDRDIFF_PTV_WEST_SIDE_P4 ," "0,1" textline " " bitfld.long 0x0 13. " DDRDIFF_PTV_WEST_SIDE_P5 ," "0,1" bitfld.long 0x0 14. " DDRDIFF_PTV_WEST_SIDE_N0 ," "0,1" textline " " bitfld.long 0x0 15. " DDRDIFF_PTV_WEST_SIDE_N1 ," "0,1" bitfld.long 0x0 16. " DDRDIFF_PTV_WEST_SIDE_N2 ," "0,1" textline " " bitfld.long 0x0 17. " DDRDIFF_PTV_WEST_SIDE_N3 ," "0,1" bitfld.long 0x0 18. " DDRDIFF_PTV_WEST_SIDE_N4 ," "0,1" textline " " bitfld.long 0x0 19. " DDRDIFF_PTV_WEST_SIDE_N5 ," "0,1" bitfld.long 0x0 20. " DDRDIFF_PTV_SOUTH_SIDE_P0 ," "0,1" textline " " bitfld.long 0x0 21. " DDRDIFF_PTV_SOUTH_SIDE_P1 ," "0,1" bitfld.long 0x0 22. " DDRDIFF_PTV_SOUTH_SIDE_P2 ," "0,1" textline " " bitfld.long 0x0 23. " DDRDIFF_PTV_SOUTH_SIDE_P3 ," "0,1" bitfld.long 0x0 24. " DDRDIFF_PTV_SOUTH_SIDE_P4 ," "0,1" textline " " bitfld.long 0x0 25. " DDRDIFF_PTV_SOUTH_SIDE_P5 ," "0,1" bitfld.long 0x0 26. " DDRDIFF_PTV_SOUTH_SIDE_N0 ," "0,1" textline " " bitfld.long 0x0 27. " DDRDIFF_PTV_SOUTH_SIDE_N1 ," "0,1" bitfld.long 0x0 28. " DDRDIFF_PTV_SOUTH_SIDE_N2 ," "0,1" textline " " bitfld.long 0x0 29. " DDRDIFF_PTV_SOUTH_SIDE_N3 ," "0,1" bitfld.long 0x0 30. " DDRDIFF_PTV_SOUTH_SIDE_N4 ," "0,1" textline " " bitfld.long 0x0 31. " DDRDIFF_PTV_SOUTH_SIDE_N5 ," "0,1" group.byte 0x5D0++0x3 line.long 0x0 "CTRL_WKUP_EFUSE_3,EFUSE compensation 3" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " DDRSE_PTV_EAST_SIDE_P0 ," "0,1" textline " " bitfld.long 0x0 9. " DDRSE_PTV_EAST_SIDE_P1 ," "0,1" bitfld.long 0x0 10. " DDRSE_PTV_EAST_SIDE_P2 ," "0,1" textline " " bitfld.long 0x0 11. " DDRSE_PTV_EAST_SIDE_P3 ," "0,1" bitfld.long 0x0 12. " DDRSE_PTV_EAST_SIDE_P4 ," "0,1" textline " " bitfld.long 0x0 13. " DDRSE_PTV_EAST_SIDE_P5 ," "0,1" bitfld.long 0x0 14. " DDRSE_PTV_EAST_SIDE_N0 ," "0,1" textline " " bitfld.long 0x0 15. " DDRSE_PTV_EAST_SIDE_N1 ," "0,1" bitfld.long 0x0 16. " DDRSE_PTV_EAST_SIDE_N2 ," "0,1" textline " " bitfld.long 0x0 17. " DDRSE_PTV_EAST_SIDE_N3 ," "0,1" bitfld.long 0x0 18. " DDRSE_PTV_EAST_SIDE_N4 ," "0,1" textline " " bitfld.long 0x0 19. " DDRSE_PTV_EAST_SIDE_N5 ," "0,1" bitfld.long 0x0 20. " DDRSE_PTV_NORTH_SIDE_P0 ," "0,1" textline " " bitfld.long 0x0 21. " DDRSE_PTV_NORTH_SIDE_P1 ," "0,1" bitfld.long 0x0 22. " DDRSE_PTV_NORTH_SIDE_P2 ," "0,1" textline " " bitfld.long 0x0 23. " DDRSE_PTV_NORTH_SIDE_P3 ," "0,1" bitfld.long 0x0 24. " DDRSE_PTV_NORTH_SIDE_P4 ," "0,1" textline " " bitfld.long 0x0 25. " DDRSE_PTV_NORTH_SIDE_P5 ," "0,1" bitfld.long 0x0 26. " DDRSE_PTV_NORTH_SIDE_N0 ," "0,1" textline " " bitfld.long 0x0 27. " DDRSE_PTV_NORTH_SIDE_N1 ," "0,1" bitfld.long 0x0 28. " DDRSE_PTV_NORTH_SIDE_N2 ," "0,1" textline " " bitfld.long 0x0 29. " DDRSE_PTV_NORTH_SIDE_N3 ," "0,1" bitfld.long 0x0 30. " DDRSE_PTV_NORTH_SIDE_N4 ," "0,1" textline " " bitfld.long 0x0 31. " DDRSE_PTV_NORTH_SIDE_N5 ," "0,1" group.byte 0x5D4++0x3 line.long 0x0 "CTRL_WKUP_EFUSE_4,EFUSE compensation 4" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8. " DDRSE_PTV_WEST_SIDE_P0 ," "0,1" textline " " bitfld.long 0x0 9. " DDRSE_PTV_WEST_SIDE_P1 ," "0,1" bitfld.long 0x0 10. " DDRSE_PTV_WEST_SIDE_P2 ," "0,1" textline " " bitfld.long 0x0 11. " DDRSE_PTV_WEST_SIDE_P3 ," "0,1" bitfld.long 0x0 12. " DDRSE_PTV_WEST_SIDE_P4 ," "0,1" textline " " bitfld.long 0x0 13. " DDRSE_PTV_WEST_SIDE_P5 ," "0,1" bitfld.long 0x0 14. " DDRSE_PTV_WEST_SIDE_N0 ," "0,1" textline " " bitfld.long 0x0 15. " DDRSE_PTV_WEST_SIDE_N1 ," "0,1" bitfld.long 0x0 16. " DDRSE_PTV_WEST_SIDE_N2 ," "0,1" textline " " bitfld.long 0x0 17. " DDRSE_PTV_WEST_SIDE_N3 ," "0,1" bitfld.long 0x0 18. " DDRSE_PTV_WEST_SIDE_N4 ," "0,1" textline " " bitfld.long 0x0 19. " DDRSE_PTV_WEST_SIDE_N5 ," "0,1" bitfld.long 0x0 20. " DDRSE_PTV_SOUTH_SIDE_P0 ," "0,1" textline " " bitfld.long 0x0 21. " DDRSE_PTV_SOUTH_SIDE_P1 ," "0,1" bitfld.long 0x0 22. " DDRSE_PTV_SOUTH_SIDE_P2 ," "0,1" textline " " bitfld.long 0x0 23. " DDRSE_PTV_SOUTH_SIDE_P3 ," "0,1" bitfld.long 0x0 24. " DDRSE_PTV_SOUTH_SIDE_P4 ," "0,1" textline " " bitfld.long 0x0 25. " DDRSE_PTV_SOUTH_SIDE_P5 ," "0,1" bitfld.long 0x0 26. " DDRSE_PTV_SOUTH_SIDE_N0 ," "0,1" textline " " bitfld.long 0x0 27. " DDRSE_PTV_SOUTH_SIDE_N1 ," "0,1" bitfld.long 0x0 28. " DDRSE_PTV_SOUTH_SIDE_N2 ," "0,1" textline " " bitfld.long 0x0 29. " DDRSE_PTV_SOUTH_SIDE_N3 ," "0,1" bitfld.long 0x0 30. " DDRSE_PTV_SOUTH_SIDE_N4 ," "0,1" textline " " bitfld.long 0x0 31. " DDRSE_PTV_SOUTH_SIDE_N5 ," "0,1" group.byte 0x5F8++0x3 line.long 0x0 "CTRL_WKUP_EFUSE_13,CTRL_WKUP_EFUSE_13" hexmask.long.tbyte 0x0 0.--19. 1. " RESERVED ," bitfld.long 0x0 20. " SDIO1833_PTV_P0 ," "0,1" textline " " bitfld.long 0x0 21. " SDIO1833_PTV_P1 ," "0,1" bitfld.long 0x0 22. " SDIO1833_PTV_P2 ," "0,1" textline " " bitfld.long 0x0 23. " SDIO1833_PTV_P3 ," "0,1" bitfld.long 0x0 24. " SDIO1833_PTV_P4 ," "0,1" textline " " bitfld.long 0x0 25. " SDIO1833_PTV_P5 ," "0,1" bitfld.long 0x0 26. " SDIO1833_PTV_N0 ," "0,1" textline " " bitfld.long 0x0 27. " SDIO1833_PTV_N1 ," "0,1" bitfld.long 0x0 28. " SDIO1833_PTV_N2 ," "0,1" textline " " bitfld.long 0x0 29. " SDIO1833_PTV_N3 ," "0,1" bitfld.long 0x0 30. " SDIO1833_PTV_N4 ," "0,1" textline " " bitfld.long 0x0 31. " SDIO1833_PTV_N5 ," "0,1" width 0x0B tree.end tree "DSP1_MMU0_DSP" base ad:0x1D01000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_MMU0_DSP" base ad:0x1D01000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_MMU1_DSP" base ad:0x1D02000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_MMU1_DSP" base ad:0x1D02000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_MMU0_L3_MAIN" base ad:0x40D01000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP1_MMU1_L3_MAIN" base ad:0x40D02000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_MMU0_L3_MAIN" base ad:0x41501000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DSP2_MMU1_L3_MAIN" base ad:0x41502000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "SYS_MMU1_L3_MAIN" base ad:0x4881C000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "SYS_MMU2_L3_MAIN" base ad:0x4881E000 width 25. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" group.byte 0x90++0x3 line.long 0x0 "MMU_BYPASS_REGION1_ADDR,This register contains the start address of the first NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION1_SIZE" group.byte 0x94++0x3 line.long 0x0 "MMU_BYPASS_REGION1_SIZE,This register contains the size of first NO TRANSLATION REGION for" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "MMU_BYPASS_REGION2_ADDR,This register contains the start address of the second NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0x9C++0x3 line.long 0x0 "MMU_BYPASS_REGION2_SIZE,This register contains the size of second NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MMU_BYPASS_REGION3_ADDR,This register contains the start address of the third NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xA4++0x3 line.long 0x0 "MMU_BYPASS_REGION3_SIZE,This register contains the size of third NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0xA8++0x3 line.long 0x0 "MMU_BYPASS_REGION4_ADDR,This register contains the start address of the forth NO TRANSLATION REGION for 2D bursts" hexmask.long.word 0x0 0.--15. 1. " RESERVED ,Reserved" hexmask.long.word 0x0 16.--31. 1. " START_ADDR ,Start address of NO TRANSLATION REGION for 2D bursts. This has to be aligned to SIZE inMMU_BYPASS_REGION2_SIZE." group.byte 0xAC++0x3 line.long 0x0 "MMU_BYPASS_REGION4_SIZE,This register contains the size of forth NO TRANSLATION REGION for 2D bursts" bitfld.long 0x0 0.--3. " SIZE ,Size of the NO TRANSLATION REGION of 2D bursts. 0x0 = region not valid 0x1 = 64K bytes 0x2 = 128K bytes 0x3 = 256K bytes 0x4 = 512K bytes 0x5 = 1M bytes 0x6 = 2M bytes 0x7 = 4M bytes 0x8 = 8M bytes 0x9 = 16M bytes 0xA = 32M bytes 0xB = 64M bytes 0xC = 128M bytes 0xD = 256M bytes 0xE = 512M bytes 0xF = 1G bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "IPU1_MMU_IPU1" base ad:0x55082000 width 18. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" width 0x0B tree.end tree "IPU2_MMU_IPU2" base ad:0x55082000 width 18. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" width 0x0B tree.end tree "IPU2_MMU_L3_MAIN" base ad:0x55082000 width 18. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" width 0x0B tree.end tree "IPU1_MMU_L3_MAIN" base ad:0x58882000 width 18. group.byte 0x0++0x3 line.long 0x0 "MMU_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "MMU_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. This bit is automatically reset by the hardware. During reads, it always return 0" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Write 0's for future compatibility Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x14++0x3 line.long 0x0 "MMU_SYSSTATUS,This register provides status information about the module, excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "MMU_IRQSTATUS,This interrupt status register regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility. Read returns 0" group.byte 0x1C++0x3 line.long 0x0 "MMU_IRQENABLE,The interrupt enable register allows to mask/unmask the module internal sources of interrupt, on a event-by-event basis." bitfld.long 0x0 0. " TLBMISS ,Unrecoverable TLB miss (hardware TWL disabled)" "0,1" bitfld.long 0x0 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (translation fault)" "0,1" textline " " bitfld.long 0x0 2. " EMUMISS ,Unrecoverable TLB miss during debug (hardware TWL disabled)" "0,1" bitfld.long 0x0 3. " TABLEWALKFAULT ,Error response received during a Table Walk" "0,1" textline " " bitfld.long 0x0 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ,Write 0's for future compatibility Read returns 0" group.byte 0x40++0x3 line.long 0x0 "MMU_WALKING_ST,This register provides status information about the table walking logic" bitfld.long 0x0 0. " TWLRUNNING ,Table Walking Logic is running" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0" group.byte 0x44++0x3 line.long 0x0 "MMU_CNTL,This register programs the MMU features" bitfld.long 0x0 0. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 1. " MMUENABLE ,MMU enable" "0,1" textline " " bitfld.long 0x0 2. " TWLENABLE ,Table Walking Logic enable" "0,1" bitfld.long 0x0 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x48++0x3 line.long 0x0 "MMU_FAULT_AD,This register contains the virtual address that generated the interrupt" hexmask.long 0x0 0.--31. 1. " FAULTADDRESS ,Virtual address of the access that generated a fault" group.byte 0x4C++0x3 line.long 0x0 "MMU_TTB,This register contains the Translation Table Base address" hexmask.long.byte 0x0 0.--6. 1. " RESERVED ,Write 0's for future compatibility. Reads retiurn 0" hexmask.long 0x0 7.--31. 1. " TTBADDRESS ,Translation Table Base Address" group.byte 0x50++0x3 line.long 0x0 "MMU_LOCK,This register locks some of the TLB entries" bitfld.long 0x0 0.--3. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " CURRENTVICTIM ,Current entry to be updated either by the TWL or by the software." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 9. " RESERVED ,Write 0's for future compatibility. Reads return 0" "0,1" bitfld.long 0x0 10.--14. " BASEVALUE ,Locked entries base value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x54++0x3 line.long 0x0 "MMU_LD_TLB,This register loads a TLB entry (CAM+RAM)" bitfld.long 0x0 0. " LDTLBITEM ,Write (load) data in the TLB. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x58++0x3 line.long 0x0 "MMU_CAM,This register holds a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x5C++0x3 line.long 0x0 "MMU_RAM,This register contains bits [31:12] of the physical address to be written to a TLB entry pointed to by CURRENTVICTIM field of register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x60++0x3 line.long 0x0 "MMU_GFLUSH,This register flushes all the non-protected TLB entries" bitfld.long 0x0 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries when set. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x64++0x3 line.long 0x0 "MMU_FLUSH_ENTRY,This register flushes the entry pointed to by the CAM virtual address" bitfld.long 0x0 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address (VATag) inMMU_CAM register, even if this entry is set protected. Reads return 0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0" group.byte 0x68++0x3 line.long 0x0 "MMU_READ_CAM,This register reads CAM data from a CAM entry" bitfld.long 0x0 0.--1. " PAGESIZE ,Page size" "0,1,2,3" bitfld.long 0x0 2. " V ,Valid bit" "0,1" textline " " bitfld.long 0x0 3. " P ,Preserved bit" "0,1" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ,Reads return 0" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " VATAG ,Virtual address tag" group.byte 0x6C++0x3 line.long 0x0 "MMU_READ_RAM,This register reads bits [31:12] of the physical address from the TLB entry pointed to by CURRENTVICTIM field of the register." hexmask.long.word 0x0 0.--11. 1. " RESERVED ,Reads return 0" hexmask.long.tbyte 0x0 12.--31. 1. " PHYSICALADDRESS ,Physical address of the page" group.byte 0x70++0x3 line.long 0x0 "MMU_EMU_FAULT_AD,This register contains the last virtual address of a fault caused by the debugger" hexmask.long 0x0 0.--31. 1. " EMUFAULTADDRESS ,Virtual address of the last emulator access that generated a fault" group.byte 0x80++0x3 line.long 0x0 "MMU_FAULT_PC,Typically CPU program counter value of instruction generating MMU fault. The address value is captured at [31:0] EMUFAULTADDRESS. Data-Read-access : corresponding PC. Data-write-access : not perfect accuracy due to posted-write." hexmask.long 0x0 0.--31. 1. " PC ,Typically CPU program counter value of instruction generating MMU fault" group.byte 0x84++0x3 line.long 0x0 "MMU_FAULT_STATUS,Fault status register" bitfld.long 0x0 0. " FAULTINDICATION ,Indicates an MMU fault" "0,1" bitfld.long 0x0 1.--2. " MMU_FAULT_TYPE ,MReqInfo[1:0] is captured as fault type" "0,1,2,3" textline " " bitfld.long 0x0 3. " RD_WR ,Indicates read or write" "0,1" bitfld.long 0x0 4.--8. " MMU_FAULT_TRANS_ID ,MtagID of the transaction that caused fault" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "MMU_GPR,General purpose register" bitfld.long 0x0 0. " FAULT_INTR_DIS ,Disable generation of interrupt on fault. Error response is returned instead on the slave port" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ,Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " GPO ,General purpose output sent out as MMU output" width 0x0B tree.end tree "Spinlock" base ad:0x4A0F6000 width 25. group.byte 0x0++0x3 line.long 0x0 "SPINLOCK_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "SPINLOCK_SYSCONFIG,This register controls the various parameters of the OCP interface. Note that most fields are read-only." bitfld.long 0x0 0. " AUTOGATING ,Internal interface clock gating strategy." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Module software reset." "0,1" textline " " bitfld.long 0x0 2. " ENWAKEUP ,Asynchronous wakeup gereration." "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Slave interface power management (IDLE request/acknowledgement control)." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved. Reads return 0." group.byte 0x14++0x3 line.long 0x0 "SPINLOCK_SYSTATUS,This register provides status information about this instance of the Spinlock module." bitfld.long 0x0 0. " RESETDONE ,Reset done status." "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Reserved. Reads return 0." textline " " bitfld.long 0x0 8. " IU0 ,In-Use flag 0, covering lock registers 0 - 31." "0,1" bitfld.long 0x0 9. " IU1 ,In-Use flag 0, covering lock registers 32 - 63." "0,1" textline " " bitfld.long 0x0 10. " IU2 ,In-Use flag 0, covering lock registers 64 - 95." "0,1" bitfld.long 0x0 11. " IU3 ,In-Use flag 0, covering lock registers 96 - 127." "0,1" textline " " bitfld.long 0x0 12. " IU4 ,In-Use flag 0, covering lock registers 128 - 159." "0,1" bitfld.long 0x0 13. " IU5 ,In-Use flag 0, covering lock registers 160 - 191." "0,1" textline " " bitfld.long 0x0 14. " IU6 ,In-Use flag 0, covering lock registers 192 - 223." "0,1" bitfld.long 0x0 15. " IU7 ,In-Use flag 0, covering lock registers 224 - 255." "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " RESERVED ,Reserved. Reads return 0." hexmask.long.byte 0x0 24.--31. 1. " NUMLOCKS ,Number of lock registers implemeted." group.byte 0x800++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_0,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x804++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_1,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x808++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_2,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x80C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_3,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x810++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_4,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x814++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_5,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x818++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_6,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x81C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_7,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x820++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_8,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x824++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_9,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x828++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_10,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x82C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_11,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x830++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_12,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x834++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_13,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x838++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_14,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x83C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_15,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x840++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_16,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x844++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_17,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x848++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_18,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x84C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_19,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x850++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_20,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x854++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_21,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x858++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_22,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x85C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_23,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x860++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_24,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x864++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_25,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x868++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_26,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x86C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_27,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x870++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_28,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x874++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_29,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x878++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_30,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x87C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_31,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x880++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_32,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x884++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_33,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x888++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_34,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x88C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_35,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x890++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_36,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x894++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_37,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x898++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_38,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x89C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_39,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8A0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_40,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8A4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_41,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8A8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_42,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8AC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_43,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8B0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_44,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8B4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_45,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8B8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_46,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8BC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_47,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8C0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_48,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8C4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_49,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8C8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_50,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8CC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_51,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8D0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_52,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8D4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_53,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8D8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_54,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8DC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_55,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8E0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_56,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8E4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_57,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8E8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_58,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8EC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_59,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8F0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_60,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8F4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_61,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8F8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_62,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x8FC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_63,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x900++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_64,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x904++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_65,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x908++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_66,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x90C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_67,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x910++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_68,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x914++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_69,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x918++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_70,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x91C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_71,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x920++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_72,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x924++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_73,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x928++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_74,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x92C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_75,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x930++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_76,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x934++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_77,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x938++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_78,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x93C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_79,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x940++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_80,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x944++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_81,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x948++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_82,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x94C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_83,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x950++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_84,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x954++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_85,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x958++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_86,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x95C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_87,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x960++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_88,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x964++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_89,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x968++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_90,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x96C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_91,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x970++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_92,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x974++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_93,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x978++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_94,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x97C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_95,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x980++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_96,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x984++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_97,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x988++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_98,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x98C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_99,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x990++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_100,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x994++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_101,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x998++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_102,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x99C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_103,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9A0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_104,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9A4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_105,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9A8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_106,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9AC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_107,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9B0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_108,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9B4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_109,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9B8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_110,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9BC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_111,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9C0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_112,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9C4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_113,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9C8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_114,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9CC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_115,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9D0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_116,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9D4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_117,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9D8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_118,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9DC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_119,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9E0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_120,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9E4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_121,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9E8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_122,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9EC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_123,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9F0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_124,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9F4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_125,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9F8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_126,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0x9FC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_127,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA00++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_128,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA04++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_129,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA08++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_130,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA0C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_131,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA10++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_132,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA14++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_133,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA18++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_134,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA1C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_135,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA20++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_136,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA24++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_137,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA28++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_138,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA2C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_139,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA30++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_140,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA34++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_141,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA38++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_142,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA3C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_143,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA40++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_144,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA44++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_145,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA48++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_146,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA4C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_147,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA50++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_148,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA54++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_149,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA58++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_150,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA5C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_151,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA60++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_152,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA64++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_153,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA68++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_154,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA6C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_155,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA70++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_156,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA74++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_157,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA78++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_158,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA7C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_159,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA80++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_160,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA84++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_161,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA88++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_162,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA8C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_163,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA90++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_164,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA94++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_165,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA98++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_166,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xA9C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_167,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAA0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_168,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAA4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_169,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAA8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_170,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAAC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_171,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAB0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_172,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAB4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_173,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAB8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_174,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xABC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_175,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAC0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_176,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAC4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_177,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAC8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_178,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xACC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_179,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAD0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_180,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAD4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_181,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAD8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_182,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xADC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_183,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAE0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_184,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAE4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_185,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAE8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_186,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAEC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_187,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAF0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_188,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAF4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_189,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAF8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_190,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xAFC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_191,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB00++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_192,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB04++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_193,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB08++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_194,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB0C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_195,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB10++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_196,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB14++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_197,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB18++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_198,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB1C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_199,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB20++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_200,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB24++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_201,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB28++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_202,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB2C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_203,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB30++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_204,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB34++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_205,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB38++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_206,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB3C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_207,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB40++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_208,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB44++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_209,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB48++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_210,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB4C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_211,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB50++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_212,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB54++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_213,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB58++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_214,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB5C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_215,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB60++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_216,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB64++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_217,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB68++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_218,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB6C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_219,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB70++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_220,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB74++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_221,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB78++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_222,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB7C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_223,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB80++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_224,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB84++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_225,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB88++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_226,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB8C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_227,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB90++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_228,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB94++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_229,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB98++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_230,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xB9C++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_231,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBA0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_232,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBA4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_233,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBA8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_234,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBAC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_235,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBB0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_236,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBB4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_237,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBB8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_238,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBBC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_239,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBC0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_240,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBC4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_241,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBC8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_242,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBCC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_243,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBD0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_244,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBD4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_245,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBD8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_246,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBDC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_247,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBE0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_248,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBE4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_249,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBE8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_250,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBEC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_251,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBF0++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_252,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBF4++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_253,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBF8++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_254,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." group.byte 0xBFC++0x3 line.long 0x0 "SPINLOCK_LOCK_REG_i_255,This register contains the state of one lock." bitfld.long 0x0 0. " TAKEN ,Lock State" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved. Reads return 0. Writes are ignored." width 0x0B tree.end tree "TIMER3_L4_PER1Interconnect" base ad:0x48034000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER4_L4_PER1Interconnect" base ad:0x48036000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER9_L4_PER1Interconnect" base ad:0x4803E000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER11_L4_PER1Interconnect" base ad:0x48088000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER5_L4_PER3Interconnect" base ad:0x48820000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER6_L4_PER3Interconnect" base ad:0x48822000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER7_L4_PER3Interconnect" base ad:0x48824000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER8_L4_PER3Interconnect" base ad:0x48826000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER13_L4_PER3Interconnect" base ad:0x48828000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER14_L4_PER3Interconnect" base ad:0x4882A000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER15_L4_PER3Interconnect" base ad:0x4882C000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER16_L4_PER3Interconnect" base ad:0x4882E000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER12_L4_WKUPInterconnect" base ad:0x4AE20000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQENABLE_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQENABLE_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" width 0x0B tree.end tree "TIMER2_L4_PER1Interconnect" base ad:0x48032000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" group.byte 0x5C++0x3 line.long 0x0 "TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment" group.byte 0x60++0x3 line.long 0x0 "TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment" group.byte 0x64++0x3 line.long 0x0 "TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. " COUNTER_VALUE ,Value of CVR counter" group.byte 0x68++0x3 line.long 0x0 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.tbyte 0x0 0.--23. 1. " OVF_COUNTER_VALUE ,Number of overflow events" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0." group.byte 0x6C++0x3 line.long 0x0 "TOWR,This register holds the number of masked overflow interrupts." hexmask.long.tbyte 0x0 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0." width 0x0B tree.end tree "TIMER10_L4_PER1Interconnect" base ad:0x48086000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" group.byte 0x5C++0x3 line.long 0x0 "TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment" group.byte 0x60++0x3 line.long 0x0 "TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment" group.byte 0x64++0x3 line.long 0x0 "TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. " COUNTER_VALUE ,Value of CVR counter" group.byte 0x68++0x3 line.long 0x0 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.tbyte 0x0 0.--23. 1. " OVF_COUNTER_VALUE ,Number of overflow events" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0." group.byte 0x6C++0x3 line.long 0x0 "TOWR,This register holds the number of masked overflow interrupts." hexmask.long.tbyte 0x0 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0." width 0x0B tree.end tree "TIMER1_L4_WKUPInterconnect" base ad:0x4AE18000 width 15. group.byte 0x0++0x3 line.long 0x0 "TIDR,This read-only register contains the revision number of the module. A write to this register has no effect. This register is used by software to track features, bugs, and compatibility." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "TIOCP_CFG,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " SOFTRESET ,Software reset" "0,1" bitfld.long 0x0 1. " EMUFREE ,Emulation mode" "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Power management, req/ack control" "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Write the number of the interrupt line to apply a SW EOI to it. Note that there is only a single line (i.e. number 0). Read: Read always returns 0 Write 0: SW EOI on interrupt line Write 1: No action" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "IRQSTATUS_RAW,Component interrupt-request status. Check the corresponding secondary status register. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Trigger IRQ event by software." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "IRQSTATUS,Component interrupt-request status. Check the corresponding secondary status register. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " MAT_IT_FLAG ,IRQ status for match Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" bitfld.long 0x0 1. " OVF_IT_FLAG ,IRQ status for overflow Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" textline " " bitfld.long 0x0 2. " TCAR_IT_FLAG ,IRQ status for capture Read 0: No event pending Write 0: No action Read 1: IRQ event pending Write 1: Clear any pending event." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "IRQSTATUS_SET,Component interrupt-request enable. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Set IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled Write 1: Set IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "IRQSTATUS_CLR,Component interrupt-request enable. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " MAT_EN_FLAG ,IRQ enable for match Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" bitfld.long 0x0 1. " OVF_EN_FLAG ,IRQ enable for overflow Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" textline " " bitfld.long 0x0 2. " TCAR_EN_FLAG ,IRQ enable for compare Read 0: IRQ event is disabled. Write 0: No action Read 1: IRQ event is enabled. Write 1: Clear IRQ enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "IRQWAKEEN,Wake-up-enabled events taking place when module is idle should generate an asynchronous wake-up." bitfld.long 0x0 0. " MAT_WUP_ENA ,Wake-up generation for match" "0,1" bitfld.long 0x0 1. " OVF_WUP_ENA ,Wake-up generation for overflow" "0,1" textline " " bitfld.long 0x0 2. " TCAR_WUP_ENA ,Wake-up generation for compare" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "TCLR,This register controls optional features specific to the timer functionality." bitfld.long 0x0 0. " ST ,Start/stop timer control" "0,1" bitfld.long 0x0 1. " AR ,Autoreload mode" "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Prescale clock timer value The timer counter is prescaled with the value 2. Example: PTV = 3, counter increases value (if started) after 16 functional clock periods." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " PRE ,Prescaler enable" "0,1" textline " " bitfld.long 0x0 6. " CE ,Compare enable" "0,1" bitfld.long 0x0 7. " SCPWM ,Pulse width modulation output pin default setting This bit must be set or clear while the timer is stopped or the trigger is off." "0,1" textline " " bitfld.long 0x0 8.--9. " TCM ,Transition capture mode on TIMERi_EVENT_CAPTURE input pin (When the TCM field passed from (00) to any other combination, the TCAR_IT_FLAG and the edge detection logic are cleared.)" "0,1,2,3" bitfld.long 0x0 10.--11. " TRG ,Trigger output mode on TIMERi_PWM_out output pin" "0,1,2,3" textline " " bitfld.long 0x0 12. " PT ,Pulse or toggle mode on TIMERi_PWM_out output pin" "0,1" bitfld.long 0x0 13. " CAPT_MODE ,Capture mode select bit (first/second)" "0,1" textline " " bitfld.long 0x0 14. " GPO_CFG ,General-purpose output - this register directly drives the PO_GPOCFG output. For specific use of the GPO_CFG bit, see, GP Timer External System Interface." "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "TCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of TIMER counter" group.byte 0x40++0x3 line.long 0x0 "TLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " LOAD_VALUE ,Timer counter value loaded on overflow in autoreload mode or onTTGR write access. LOAD_VALUE must be different than the timer overflow value (0xFFFF FFFF)." group.byte 0x44++0x3 line.long 0x0 "TTGR,The read value of this register is always 0xFFFF FFFF." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Writing to theTTGR register causes the TCRR to be loaded from TLDR and the prescaler counter to be cleared. Reload is done regardless of the AR field value of the TCLR register." group.byte 0x48++0x3 line.long 0x0 "TWPS,This register contains the write posting bits for all writable functional registers." bitfld.long 0x0 0. " W_PEND_TCLR ,When equal to 1, a write is pending to theTCLR register." "0,1" bitfld.long 0x0 1. " W_PEND_TCRR ,When equal to 1, a write is pending to theTCRR register." "0,1" textline " " bitfld.long 0x0 2. " W_PEND_TLDR ,When equal to 1, a write is pending to theTLDR register." "0,1" bitfld.long 0x0 3. " W_PEND_TTGR ,When equal to 1, a write is pending to theTTGR register." "0,1" textline " " bitfld.long 0x0 4. " W_PEND_TMAR ,When equal to 1, a write is pending to theTMAR register." "0,1" bitfld.long 0x0 5. " W_PEND_TPIR ,Write pending for theTPIR register" "0,1" textline " " bitfld.long 0x0 6. " W_PEND_TNIR ,Write pending for theTNIR register" "0,1" bitfld.long 0x0 7. " W_PEND_TCVR ,Write pending for theTCVR register" "0,1" textline " " bitfld.long 0x0 8. " W_PEND_TOCR ,Write pending for theTOCR register" "0,1" bitfld.long 0x0 9. " W_PEND_TOWR ,Write pending for theTOWR register" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "TMAR,The compare logic consists of a 32-bit-wide, read/write data register and logic to compare counter." hexmask.long 0x0 0.--31. 1. " COMPARE_VALUE ,Value to be compared to the timer counter" group.byte 0x50++0x3 line.long 0x0 "TCAR1,This register holds the first captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE1 ,First timer counter value captured on an external event trigger" group.byte 0x54++0x3 line.long 0x0 "TSICR,Timer synchronous interface control register" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " SFT ,This bit resets all the functional part of the module." "0,1" textline " " bitfld.long 0x0 2. " POSTED ,Posted mode selection" "0,1" bitfld.long 0x0 3. " READ_MODE ,Select posted/non-posted mode for read operation:NOTE: When the module is configured in posted mode (POSTED = '1'), this bit is not used. . NOTE: For GP TIMER1, TIMER2 and TIMER10 this bit is write only. ." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x58++0x3 line.long 0x0 "TCAR2,This register holds the second captured value of the counter register." hexmask.long 0x0 0.--31. 1. " CAPTURE_VALUE2 ,Second timer counter value captured on an external event trigger" group.byte 0x5C++0x3 line.long 0x0 "TPIR,This register is used for 1-ms tick generation. The register holds the value of the positive increment. The value of this register is added to the value of to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. " POSITIVE_INC_VALUE ,Value of the positive increment" group.byte 0x60++0x3 line.long 0x0 "TNIR,This register is used for 1-ms tick generation. The register holds the value of the negative increment. The value of this register is added to the value of the to determine whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. " NEGATIVE_INV_VALUE ,Value of the negative increment" group.byte 0x64++0x3 line.long 0x0 "TCVR,This register is used for 1-ms tick generation. The register determines whether next value loaded in is the subperiod value or the overperiod value." hexmask.long 0x0 0.--31. 1. " COUNTER_VALUE ,Value of CVR counter" group.byte 0x68++0x3 line.long 0x0 "TOCR,This register is used to mask the tick interrupt for a selected number of ticks." hexmask.long.tbyte 0x0 0.--23. 1. " OVF_COUNTER_VALUE ,Number of overflow events" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0." group.byte 0x6C++0x3 line.long 0x0 "TOWR,This register holds the number of masked overflow interrupts." hexmask.long.tbyte 0x0 0.--23. 1. " OVF_WRAPPING_VALUE ,Number of masked interrupts" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reads return 0." width 0x0B tree.end tree "WD_TIMER2" base ad:0x4AE14000 width 13. group.byte 0x0++0x3 line.long 0x0 "WIDR,IP revision identifier" hexmask.long 0x0 0.--31. 1. " REV ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "WDSC,This register controls the various parameters of the L4 interface." bitfld.long 0x0 0. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. (Optional)" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" textline " " bitfld.long 0x0 5. " EMUFREE ,Emulation mode" "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x14++0x3 line.long 0x0 "WDST,This register provides status information about the module." bitfld.long 0x0 0. " RESETDONE ,Internal module reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0." group.byte 0x18++0x3 line.long 0x0 "WISR,This register shows which interrupt events are pending inside the module." bitfld.long 0x0 0. " OVF_IT_FLAG ,Pending overflow interrupt status." "0,1" bitfld.long 0x0 1. " DLY_IT_FLAG ,Pending delay interrupt status." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reads return 0." group.byte 0x1C++0x3 line.long 0x0 "WIER,This register controls (enable/disable) the interrupt events." bitfld.long 0x0 0. " OVF_IT_ENA ,Overflow interrupt enable/disable" "0,1" bitfld.long 0x0 1. " DLY_IT_ENA ,Delay interrupt enable/disable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reads return 0." group.byte 0x20++0x3 line.long 0x0 "WWER,This register controls (enable/disable) the wake-up events." bitfld.long 0x0 0. " OVF_WK_ENA ,Overflow wake-up enable" "0,1" bitfld.long 0x0 1. " DLY_WK_ENA ,Delay wake-up enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x24++0x3 line.long 0x0 "WCLR,This register controls the prescaler stage of the counter." bitfld.long 0x0 0.--1. " RESERVED ,Write 0s for future compatibility. Reads return 0." "0,1,2,3" bitfld.long 0x0 2.--4. " PTV ,Prescaler value The timer counter is prescaled with the value: 2. Example: PTV = 3 -> counter increases value if started after 8 functional clock periods. On reset, it is loaded from PI_PTV_RESET_VALUE input port." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 5. " PRE ,Prescaler enable/disable configuration" "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ,Reads return 0." group.byte 0x28++0x3 line.long 0x0 "WCRR,This register holds the value of the internal counter." hexmask.long 0x0 0.--31. 1. " TIMER_COUNTER ,Value of the timer counter register" group.byte 0x2C++0x3 line.long 0x0 "WLDR,This register holds the timer load value." hexmask.long 0x0 0.--31. 1. " TIMER_LOAD ,Value of the timer load register" group.byte 0x30++0x3 line.long 0x0 "WTGR,Writing a different value than the one already written in this register does a watchdog counter reload." hexmask.long 0x0 0.--31. 1. " TTGR_VALUE ,Value of the trigger register" group.byte 0x34++0x3 line.long 0x0 "WWPS,This register contains the write posting bits for all writeable functional registers." bitfld.long 0x0 0. " W_PEND_WCLR ,Write pending for registerWCLR" "0,1" bitfld.long 0x0 1. " W_PEND_WCRR ,Write pending for registerWCRR" "0,1" textline " " bitfld.long 0x0 2. " W_PEND_WLDR ,Write pending for registerWLDR" "0,1" bitfld.long 0x0 3. " W_PEND_WTGR ,Write pending for registerWTGR" "0,1" textline " " bitfld.long 0x0 4. " W_PEND_WSPR ,Write pending for registerWSPR" "0,1" bitfld.long 0x0 5. " W_PEND_WDLY ,Write pending for registerWDLY" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x44++0x3 line.long 0x0 "WDLY,This register holds the delay value that controls the internal pre-overflow event detection." hexmask.long 0x0 0.--31. 1. " WDLY_VALUE ,Value of the delay register" group.byte 0x48++0x3 line.long 0x0 "WSPR,This register holds the start-stop value that controls the internal start-stop FSM." hexmask.long 0x0 0.--31. 1. " WSPR_VALUE ,Value of the start-stop register" group.byte 0x50++0x3 line.long 0x0 "WIRQEOI,Software End Of Interrupt" bitfld.long 0x0 0. " LINE_NUMBER ,EOI for interrupt output line Reads always 0 (no EOI memory)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Write 0's for future compatibility. Reads return 0." group.byte 0x54++0x3 line.long 0x0 "WIRQSTATRAW,IRQ unmasked status, status set per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " EVENT_OVF ,Settable raw status for overflow event" "0,1" bitfld.long 0x0 1. " EVENT_DLY ,Settable raw status for delay event" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x58++0x3 line.long 0x0 "WIRQSTAT,IRQ masked status, status clear per-event enabled interrupt status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." bitfld.long 0x0 0. " EVENT_OVF ,Clearable, enabled status for overflow event" "0,1" bitfld.long 0x0 1. " EVENT_DLY ,Clearable, enabled status for delay event" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x5C++0x3 line.long 0x0 "WIRQENSET,IRQ enable set per-event interrupt enable bit vector, line 0. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " ENABLE_OVF ,Enable for overflow event" "0,1" bitfld.long 0x0 1. " ENABLE_DLY ,Enable for delay event" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x60++0x3 line.long 0x0 "WIRQENCLR,IRQ enable clear per-event interrupt enable bit vector, line 0. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " ENABLE_OVF ,Enable for overflow event" "0,1" bitfld.long 0x0 1. " ENABLE_DLY ,Enable for delay event" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." group.byte 0x64++0x3 line.long 0x0 "WIRQWAKEEN,This register controls (enable/disable) the wake-up events." bitfld.long 0x0 0. " OVF_WK_ENA ,Enable overflow wakeup" "0,1" bitfld.long 0x0 1. " DLY_WK_ENA ,Enable delay wake-up" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Write 0s for future compatibility. Reads return 0." width 0x0B tree.end tree "L4_WKUP_COUNTER_32K" base ad:0x4AE04000 width 11. group.byte 0x0++0x3 line.long 0x0 "REVISION,This register contains the sync counter IP revision code." hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "SYSCONFIG,This register is used for idle modes only." bitfld.long 0x0 0. " SYNCMODE ,Synchronization scheme0x0 Gray synchronization scheme. Ensures that a stable value of the register is read. . 0x1 Legacy synchronization scheme. ." "0,1" bitfld.long 0x0 1.--2. " Reserved ,Reads return 0." "0,1,2,3" textline " " bitfld.long 0x0 3.--4. " IDLEMODE ,Power management REQ/ACK control" "0,1,2,3" hexmask.long 0x0 5.--31. 1. " Reserved ,Reads return 0." group.byte 0x30++0x3 line.long 0x0 "CR,This register contains the 32-kHz sync counter value." hexmask.long 0x0 0.--31. 1. " COUNTER_VALUE ,Counter register value" width 0x0B tree.end tree "RTC_SS" base ad:0x48838000 width 24. group.byte 0x0++0x3 line.long 0x0 "RTC_SECONDS_REG,Used to program the required seconds value of the current time. Seconds are stored in BCD format, the decimal numbers are encoded with their binary equivalent. That is, if seconds value is 45, then SEC0 = 5 and SEC1 = 4." bitfld.long 0x0 0.--3. " SEC0 ,First digit of seconds. Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " SEC1 ,Second digit of seconds. Range is 0 to 5" "0,1,2,3,4,5,6,7" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "RTC_MINUTES_REG,Used to program the required minutes value of the current time. Minutes are stored in BCD format, the decimal numbers are encoded with their binary equivalent. That is, if minutes value is 32, then MIN0 = 2 and MIN1 = 3." bitfld.long 0x0 0.--3. " MIN0 ,First digit of minutes Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " MIN1 ,Second digit of minutes Range is 0 to 5" "0,1,2,3,4,5,6,7" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "RTC_HOURS_REG,Used to program the hours value of the current time. Hours are stored in BCD format, the decimal numbers are encoded with their binary equivalent. That is, if hour is 18, then HOUR0 = 8 and HOUR1 = 1." bitfld.long 0x0 0.--3. " HOUR0 ,First digit of hours Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " HOUR1 ,Second digit of hours Range is 0 to 2" "0,1,2,3" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " PM_NAM ,Only used in PM_AM mode (otherwise 0) 0 = AM 1 = PM" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "RTC_DAYS_REG,Used to program the day of the month value of the current date. Days are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent. If the day value of the date is 28, DAY0 is set as 8 and DAY1 is set as 2." bitfld.long 0x0 0.--3. " DAY0 ,First digit of days Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " DAY1 ,Second digit of days Range from 0 to 3" "0,1,2,3" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "RTC_MONTHS_REG,MONTHS_REG is used to set the month in the year value of the current date. Months are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent." bitfld.long 0x0 0.--3. " MONTH0 ,First digit of months Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " MONTH1 ,Second digit of months Range from 0 to 1" "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "RTC_YEARS_REG,YEARS_REG is used to program the year value of the current date. The year value is represented by only the last two digits and is stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent. The year 1979 is programmed as 79 with YEAR0 set as 9 and YEAR1 set as 7." bitfld.long 0x0 0.--3. " YEAR0 ,First digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " YEAR1 ,Second digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "RTC_WEEKS_REG,WEEKS_REG is used to program the day of the week value of the current date. The day of the week is stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent." bitfld.long 0x0 0.--2. " WEEK ,First digit of Days in a week Range from 0 (Sunday) to 6 (Saturday)" "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "RTC_ALARM_SECONDS_REG,ALARM_SECONDS_REG is used to program the seconds value for the alarm interrupt. Seconds are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent." bitfld.long 0x0 0.--3. " ALARM_SEC0 ,First digit of seconds Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ALARM_SEC1 ,Second digit of seconds Range is 0 to 5" "0,1,2,3,4,5,6,7" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "RTC_ALARM_MINUTES_REG,ALARM_MINUTES_REG is used to program the minute value for the alarm interrupt. Minutes are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent." bitfld.long 0x0 0.--3. " ALARM_MIN0 ,First digit of minutes Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ALARM_MIN1 ,Second digit of minutes Range is 0 to 5" "0,1,2,3,4,5,6,7" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "RTC_ALARM_HOURS_REG,ALARM_HOURS_REG is used to program the hour value for the alarm interrupt. Hours are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent." bitfld.long 0x0 0.--3. " ALARM_HOUR0 ,First digit of hours. Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " ALARM_HOUR1 ,Second digit of hours. Range is 0 to 2" "0,1,2,3" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " ALARM_PM_NAM ,Only used in PM_AM mode (otherwise 0) 0 = AM 1 = PM" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x2C++0x3 line.long 0x0 "RTC_ALARM_DAYS_REG,ALARM_DAYS_REG is used to program the day of the month value for the alarm interrupt. Days are stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent." bitfld.long 0x0 0.--3. " ALARM_DAY0 ,First digit for days. Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " ALARM_DAY1 ,Second digit for days. Range from 0 to 3" "0,1,2,3" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "RTC_ALARM_MONTHS_REG,ALARM_MONTHS_REG is used to program the month in the year value for the alarm interrupt. The month is stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent" bitfld.long 0x0 0.--3. " ALARM_MONTH0 ,First digit of months. Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ALARM_MONTH1 ,Second digit of months. Range from 0 to 1" "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "RTC_ALARM_YEARS_REG,ALARM_YEARS_REG is used to program the year for the alarm interrupt. Only the last two digits are used to represent the year and is stored as BCD format. In BCD format, the decimal numbers 0 through 9 are encoded with their binary equivalent" bitfld.long 0x0 0.--3. " ALARM_YEAR0 ,First digit of years. Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " ALARM_YEAR1 ,Second digit of years. Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "RTC_CTRL_REG,CTRL_REG contains the controls to enable/disable RTC." bitfld.long 0x0 0. " STOP_RTC ,0: RTC is frozen. 1: RTC is running." "0,1" bitfld.long 0x0 1. " ROUND_30S ,0: No update 1: When a 1 is written, the time is rounded to the closest minute." "0,1" textline " " bitfld.long 0x0 2. " AUTO_COMP ,0: No auto compensation 1: Auto compensation enabled" "0,1" bitfld.long 0x0 3. " MODE_12_24 ,0: 24-hour mode 1: 12-hour mode (PM-AM mode)" "0,1" textline " " bitfld.long 0x0 4. " TEST_MODE ,0: Functional mode 1: Test mode (Auto compensation is enabled when the 32-kHz counter reaches its end.)" "0,1" bitfld.long 0x0 5. " SET_32_COUNTER ,0: No action 1: Set the 32-kHz counter with comp_reg value" "0,1" textline " " bitfld.long 0x0 6. " RTC_DISABLE ,0: RTC enable 1: RTC disable (no 32-kHz clock)" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x44++0x3 line.long 0x0 "RTC_STATUS_REG,RTC STATUS_REG contains bits that signal the status of interrupts, events to the processor. Status for the alarm interrupt and timer events are notified by the register." bitfld.long 0x0 0. " BUSY ,0: Updating event in more than 15 5s. 1: Updating event. This bit will give the status of RTC module. The time and alarm registers can be modified only when this bit is 0." "0,1" bitfld.long 0x0 1. " RUN ,0: RTC is frozen. 1: RTC is running." "0,1" textline " " bitfld.long 0x0 2. " EVENT_1S ,One second has occurred." "0,1" bitfld.long 0x0 3. " EVENT_1M ,One minute has occurred." "0,1" textline " " bitfld.long 0x0 4. " EVENT_1H ,One hour has occurred." "0,1" bitfld.long 0x0 5. " EVENT_1D ,One day has occurred." "0,1" textline " " bitfld.long 0x0 6. " ALARM ,Indicates that an alarm interrupt has been generated. Writing 1 to the bit clears the interrupt." "0,1" bitfld.long 0x0 7. " ALARM2 ,Indicates that an alarm2 interrupt has been generated. Software must wait 31 5s before it clears this status to allow PMIC_PWR_ENABLE 1 - 0 transmission." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "RTC_INTERRUPTS_REG,INTERRUPTS_REG is used to enable or disable RTC from generating interrupts. The timer interrupt and alarm interrupt can be controlled using this register." bitfld.long 0x0 0.--1. " EVERY ,Interrupt period: 0 - every second 1 - every minute 2 - every hour 3 - every day" "0,1,2,3" bitfld.long 0x0 2. " IT_TIMER ,Enable periodic interrupt 0 = interrupt disabled 1 = interrupt enabled" "0,1" textline " " bitfld.long 0x0 3. " IT_ALARM ,Enable one interrupt when the alarm value is reached (TC ALARM registers) by the TC registers" "0,1" bitfld.long 0x0 4. " IT_ALARM2 ,Enable one interrupt when the alarm value is reached (TC ALARM2 registers) by the TC registers" "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "RTC_COMP_LSB_REG,COMP_LSB_REG is used to program the LSB value of the 32-kHz periods to be added to the 32-kHz counter every hour. This is used to compensate the oscillator drift. The COMP_LSB_REG works with the compensation (MSB) register (COMP_MSB_REG). The AUTOCOMP bit in the control register (CTRL_REG) must be enabled for compensation to OCCUR." hexmask.long.byte 0x0 0.--7. 1. " RTC_COMP_LSB ,Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "RTC_COMP_MSB_REG,COMP_MSB_REG is used to program the MSB value of the 32-kHz periods to be added to the 32-kHz counter every hour. This is used to compensate the oscillator drift. The COMP_MSB_REG works with the compensation (LSB) register (COMP_LSB_REG) to set the hourly oscillator compensation value. The AUTOCOMP bit in the control register (CTRL_REG) must be enabled for compensation to OCCUR." hexmask.long.byte 0x0 0.--7. 1. " RTC_COMP_MSB ,Indicates number of 32-kHz periods to be added into the 32-kHz counter every hour" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "RTC_OSC_REG,OSC_REG is used to program the oscillator resistance value, and to select and enable the clock source." bitfld.long 0x0 0. " SW1 ,Inverter size adjustment." "0,1" bitfld.long 0x0 1. " SW2 ,Inverter size adjustment." "0,1" textline " " bitfld.long 0x0 2. " RES_SELECT ,External feedback resistor selection. 0: Internal 1: External" "0,1" bitfld.long 0x0 3. " K32CLK_SEL ,32-kHz clock source select. 0: Selects internal clock source, namely RTC_32K_AUX_CLK, from PRCM. 1: Selects external clock source namely RTC_32K_CLK, from the 32-kHz Oscillator." "0,1" textline " " bitfld.long 0x0 4. " OSC32K_GZ ,Disable the oscillator and applies high impedance to the output. 0: Enable 1: Disabled and high impedance" "0,1" bitfld.long 0x0 5. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 6. " K32CLK_EN ,32-kHz clock enable post clock mux of RTC_32K_AUX_CLK and RTC_32K_CLK." "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "RTC_SCRATCH0_REG,Used to hold some required values for the RTC register." hexmask.long 0x0 0.--31. 1. " RTCSCRATCH0 ,Scratch registers, available to program." group.byte 0x64++0x3 line.long 0x0 "RTC_SCRATCH1_REG,Used to hold some required values for the RTC register." hexmask.long 0x0 0.--31. 1. " RTCSCRATCH1 ,Scratch registers, available to program" group.byte 0x68++0x3 line.long 0x0 "RTC_SCRATCH2_REG,Used to hold some required values for the RTC register." hexmask.long 0x0 0.--31. 1. " RTCSCRATCH2 ,Scratch registers, available to program." group.byte 0x6C++0x3 line.long 0x0 "RTC_KICK0_REG,The KICK0 register allows writing to unlock the kick0 data. To disable RTC register write protection, the value of 83E7 0B13h must be written to KICK0, followed by the value of 95A4 F1E0h written to KICK1. RTC register write protection is enabled when any value is written to KICK0" hexmask.long 0x0 0.--31. 1. " KICK0 ,Kick0 data." group.byte 0x70++0x3 line.long 0x0 "RTC_KICK1_REG,Kick1 data. The KICK1 register allows writing to unlock the kick1 data and the kicker mechanism to write to other registers. To disable RTC register write protection, the value of 83E7 0B13h must be written to KICK0, followed by the value of 95A4 F1E0h written to KICK1." hexmask.long 0x0 0.--31. 1. " KICK1 ,Kick1 data." group.byte 0x74++0x3 line.long 0x0 "RTC_REVISION_REG,RTC_REVISION_REG" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x78++0x3 line.long 0x0 "RTC_SYSCONFIG_REG,RTC_SYSCONFIG_REG" bitfld.long 0x0 0.--1. " IDLEMODE ,Configuration of the local target state management mode, By definition target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x7C++0x3 line.long 0x0 "RTC_IRQWAKEEN,RTC_IRQWAKEEN" bitfld.long 0x0 0. " TIMMER_WAKEEN ,Wakeup generation for event Timer 0: Wakeup disabled 1: Wakeup enable Timer wakeup should not get used." "0,1" bitfld.long 0x0 1. " ALARM_WAKEEN ,Wakeup generation for event Alarm 0: Wakeup disabled 1: Wakeup enable" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "RTC_ALARM2_SECONDS_REG,ALARM2_SECONDS_REG is used to program the seconds value of the ALARM2 time" bitfld.long 0x0 0.--3. " ALARM2_SEC0 ,First digit of seconds Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ALARM2_SEC1 ,Second digit of seconds Range is 0 to 5" "0,1,2,3,4,5,6,7" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x84++0x3 line.long 0x0 "RTC_ALARM2_MINUTES_REG,RTC_ALARM2_MINUTES_REG" bitfld.long 0x0 0.--3. " ALARM2_MIN0 ,First digit of minutes Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ALARM2_MIN1 ,Second digit of minutes Range is 0 to 5" "0,1,2,3,4,5,6,7" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved" group.byte 0x88++0x3 line.long 0x0 "RTC_ALARM2_HOURS_REG,RTC_ALARM2_HOURS_REG" bitfld.long 0x0 0.--3. " ALARM2_HOUR0 ,First digit of hours Range is 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " ALARM2_HOUR1 ,Second digit of hours Range is 0 to 2" "0,1,2,3" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " ALARM2_PM_NAM ,Only used in PM_AM mode (otherwise 0) 0 = AM 1 = PM" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8C++0x3 line.long 0x0 "RTC_ALARM2_DAYS_REG,RTC_ALARM2_DAYS_REG" bitfld.long 0x0 0.--3. " ALARM_DAY0 ,First digit for days Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--5. " ALARM_DAY1 ,Second digit for days Range from 0 to 3" "0,1,2,3" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x90++0x3 line.long 0x0 "RTC_ALARM2_MONTHS_REG,RTC_ALARM2_MONTHS_REG" bitfld.long 0x0 0.--3. " ALARM2_MONTH0 ,First digit of months Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ALARM2_MONTH1 ,Second digit of months Range from 0 to 1" "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x94++0x3 line.long 0x0 "RTC_ALARM2_YEARS_REG,RTC_ALARM2_YEARS_REG" bitfld.long 0x0 0.--3. " ALARM2_YEAR0 ,First digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " ALARM2_YEAR1 ,Second digit of Years Range from 0 to 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x98++0x3 line.long 0x0 "RTC_PMIC_REG,RTC_PMIC_REG" bitfld.long 0x0 0.--3. " EXT_WAKEUP_EN ,Enable External wakeup inputs 0: Ext Wakeup disabled 1: Ext Wakeup enable EXT_WAKEUP_EN[0] controls ext_wakeup0; EXT_WAKEUP_EN[N] controls ext_wakeup n ;" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " EXT_WAKEUP_POL ,External wakeup inputs polarity 0: Active High 1: Active Low EXT_WAKEUP_POL[0] controls ext_wakeup0; EXT_WAKEUP_POL[N] controls ext_wakeup n ;" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " EXT_WAKEUP_DB_EN ,External wakeup debounce enabled 0: Disable 1: Enable EXT_WAKEUP_DB_EN[0] controls ext_wakeup0; EXT_WAKEUP_DB_EN[N] controls ext_wakeup n ; When enabled RTL_DEBOUNCE_REG defines the debounce time." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " EXT_WAKEUP_STATUS ,External wakeup status 0: External wakeup event has not occurred 1: External wakeup event has occurred Wrt 1 to Clear EXT_WAKEUP_STATUS[0] status of ext_wakeup0 event EXT_WAKEUP_STATUS[N] status of ext_wakeup n event. SW must clear the events before PMIC_PWR_ENABLE can go from 1 - 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " PWR_ENABLE_EN ,pwr_enable enable 0: Disable When Disabled, PMIC_PWR_ENABLE will always be drive 1, ON state 1: Enable When enabled: PMIC_PWR_ENABLE will be controlled by ext_wakeup 3:0 , alarm , and alarm2. ON - OFF (Turn OFF) By ALARM2 event OFF - ON (TURN ON) By ALARM event OR ext_wakeup n event" "0,1" bitfld.long 0x0 17.--18. " PWR_ENABLE_SM ,Power State Machine state 00 = Idle/Default 01 = Shutdown (ALARM2 and pwr_enable enable is set, note 31uS latency from ALARM2 event.) 10 = Time based wakeup (ALARM status is set) 11 = External event based wakeup (one or more bit set in EXT_WAKEUP_STATUS)" "0,1,2,3" textline " " bitfld.long 0x0 19.--22. " EXT_WAKEUP_POL_HL ,External wakeup inputs polarity enable for Active High and Active Low 0: Disabled 1: Enabled, Active High and Active Low EXT_WAKEUP_POL_HL[0] controls ext_wakeup0; EXT_WAKEUP_POL_HL[N] controls ext_wakeup n ; Note when enabled EXT_WAKEUP_POL_HL overrides EXT_WAKEUP_POL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 23.--31. 1. " RESERVED ,Reserved" group.byte 0x9C++0x3 line.long 0x0 "RTC_RTL_DEBOUNCE_REG,RTC_RTL_DEBOUNCE_REG" hexmask.long.byte 0x0 0.--7. 1. " DEBOUNCE_REG ,Debounce time, see for details." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "I2C3" base ad:0x48060000 width 21. group.byte 0x0++0x1 line.word 0x0 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility" hexmask.word 0x0 0.--15. 1. " REVISION ,IP Revision" group.byte 0x4++0x1 line.word 0x0 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility" hexmask.word 0x0 0.--15. 1. " REVISION ,IP Revision" group.byte 0x10++0x1 line.word 0x0 "I2C_SYSC,System Configuration register" bitfld.word 0x0 0. " AUTOIDLE ,Autoidle bit" "0,1" bitfld.word 0x0 1. " SRST ,SoftReset bit" "0,1" textline " " bitfld.word 0x0 2. " ENAWAKEUP ,Enable Wakeup control bit" "0,1" bitfld.word 0x0 3.--4. " IDLEMODE ,Idle Mode selection bits" "0,1,2,3" textline " " bitfld.word 0x0 5.--7. " RESERVED ,Reads return 0." "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "0,1,2,3" textline " " bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x20++0x1 line.word 0x0 "I2C_EOI,End Of Interrupt number specification" bitfld.word 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x24++0x1 line.word 0x0 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug" bitfld.word 0x0 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "0,1" bitfld.word 0x0 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "0,1" bitfld.word 0x0 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ status." "0,1" bitfld.word 0x0 7. " AERR ,Access Error IRQ status." "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ status." "0,1" bitfld.word 0x0 9. " AAS ,Address recognized as slave IRQ status." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun status. Writing into this bit has no effect." "0,1" textline " " bitfld.word 0x0 12. " BB ,Bus busy status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 13. " RDR ,Receive draining IRQ status." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit draining IRQ status." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x28++0x1 line.word 0x0 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.word 0x0 0. " AL ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" bitfld.word 0x0 3. " RRDY ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" textline " " bitfld.word 0x0 4. " XRDY ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" bitfld.word 0x0 5. " GC ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ enabled status." "0,1" bitfld.word 0x0 7. " AERR ,Access Error IRQ enabled status." "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ enabled status." "0,1" bitfld.word 0x0 9. " AAS ,Address recognized as slave IRQ enabled status." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enabled status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enabled status. Writing into this bit has no effect." "0,1" textline " " bitfld.word 0x0 12. " BB ,Bus busy enabled status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 13. " RDR ,Receive draining IRQ enabled status." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit draining IRQ enabled status." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x2C++0x1 line.word 0x0 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.word 0x0 0. " AL_IE ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AL]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 1. " NACK_IE ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [NACK]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 2. " ARDY_IE ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [ARDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 3. " RRDY_IE ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 4. " XRDY_IE ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XRDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 5. " GC_IE ,General call Interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [GC]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 6. " STC_IE ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [STC].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 7. " AERR_IE ,Access Error interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AERR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 8. " BF_IE ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [BF].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 9. " AAS_IE ,Addressed as Slave interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AAS].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enable set.Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enable set.Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR_IE ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [RDR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 14. " XDR_IE ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW[XDR].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x30++0x1 line.word 0x0 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.word 0x0 0. " AL_IE ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW[AL]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 1. " NACK_IE ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [NACK]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 2. " ARDY_IE ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [ARDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 3. " RRDY_IE ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 4. " XRDY_IE ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XRDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 5. " GC_IE ,General call Interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [GC]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 6. " STC_IE ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [STC].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 7. " AERR_IE ,Access Error interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AERR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 8. " BF_IE ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [BF].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 9. " AAS_IE ,Addressed as Slave interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AAS].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enable clear.Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enable clear.Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR_IE ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 14. " XDR_IE ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XDR].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x34++0x1 line.word 0x0 "I2C_WE,I2C wakeup enable vector." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x38++0x1 line.word 0x0 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.word 0x0 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x3C++0x1 line.word 0x0 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.word 0x0 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x40++0x1 line.word 0x0 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.word 0x0 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x44++0x1 line.word 0x0 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.word 0x0 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x48++0x1 line.word 0x0 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x4C++0x1 line.word 0x0 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x90++0x1 line.word 0x0 "I2C_SYSS,System Status register" bitfld.word 0x0 0. " RDONE ,Reset done bit" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x94++0x1 line.word 0x0 "I2C_BUF,Buffer Configuration register" bitfld.word 0x0 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 6. " TXFIFO_CLR ,Transmit FIFO clear" "0,1" textline " " bitfld.word 0x0 7. " XDMA_EN ,Transmit DMA channel enable" "0,1" bitfld.word 0x0 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x0 14. " RXFIFO_CLR ,Receive FIFO clear" "0,1" bitfld.word 0x0 15. " RDMA_EN ,Receive DMA channel enable" "0,1" group.byte 0x98++0x1 line.word 0x0 "I2C_CNT,Data counter register" hexmask.word 0x0 0.--15. 1. " DCOUNT ,Data count" group.byte 0x9C++0x1 line.word 0x0 "I2C_DATA,Data access register" hexmask.word.byte 0x0 0.--7. 1. " DATA ,Transmit/Receive data FIFO endpoint" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ,Reserved" group.byte 0xA4++0x1 line.word 0x0 "I2C_CON,I2C configuration register." bitfld.word 0x0 0. " STT ,Start condition (master mode only)." "0,1" bitfld.word 0x0 1. " STP ,Stop condition (master mode only)." "0,1" textline " " bitfld.word 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.word 0x0 4. " XOA3 ,Expand Own address 3." "0,1" textline " " bitfld.word 0x0 5. " XOA2 ,Expand Own address 2." "0,1" bitfld.word 0x0 6. " XOA1 ,Expand Own address 1." "0,1" textline " " bitfld.word 0x0 7. " XOA0 ,Expand Own address 0." "0,1" bitfld.word 0x0 8. " XSA ,Expand Slave address." "0,1" textline " " bitfld.word 0x0 9. " TRX ,Transmitter/Receiver mode (master mode only)." "0,1" bitfld.word 0x0 10. " MST ,Master/slave mode." "0,1" textline " " bitfld.word 0x0 11. " STB ,Start byte mode (master mode only)." "0,1" bitfld.word 0x0 12.--13. " OPMODE ,Operation mode selection." "0,1,2,3" textline " " bitfld.word 0x0 14. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 15. " I2C_EN ,I2C module enable." "0,1" group.byte 0xA8++0x1 line.word 0x0 "I2C_OA,Own address register" hexmask.word 0x0 0.--9. 1. " OA ,Own address" bitfld.word 0x0 10.--12. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 13.--15. " MCODE ,Master Code" "0,1,2,3,4,5,6,7" group.byte 0xAC++0x1 line.word 0x0 "I2C_SA,Slave address register" hexmask.word 0x0 0.--9. 1. " SA ,Slave address" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xB0++0x1 line.word 0x0 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x0 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 .............................. 0xFF: Divide by 256" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ,Reserved" group.byte 0xB4++0x1 line.word 0x0 "I2C_SCLL,I2C SCL Low Time Register." hexmask.word.byte 0x0 0.--7. 1. " SCLL ,Fast/standard mode SCL low timeThe value of the bit field is automatically increased by 7. ." hexmask.word.byte 0x0 8.--15. 1. " HSSCLL ,High speed mode SCL low timeThe value of the bit field is automatically increased by 7. ." group.byte 0xB8++0x1 line.word 0x0 "I2C_SCLH,I2C SCL High Time Register." hexmask.word.byte 0x0 0.--7. 1. " SCLH ,Fast/standard mode SCL high timeThe value of the bit field is automatically increased by 5. ." hexmask.word.byte 0x0 8.--15. 1. " HSSCLH ,High speed mode SCL high timeThe value of the bit field is automatically increased by 5. ." group.byte 0xBC++0x1 line.word 0x0 "I2C_SYSTEST,I2C System Test Register." bitfld.word 0x0 0. " SDA_O ,SDA line drive output value." "0,1" bitfld.word 0x0 1. " SDA_I ,SDA line sense input value." "0,1" textline " " bitfld.word 0x0 2. " SCL_O ,SCL line drive output value." "0,1" bitfld.word 0x0 3. " SCL_I ,SCL line sense input value" "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " SDA_O_FUNC ,SDA line output value (functional mode)." "0,1" textline " " bitfld.word 0x0 6. " SDA_I_FUNC ,SDA line input value (functional mode)." "0,1" bitfld.word 0x0 7. " SCL_O_FUNC ,SCL line output value (functional mode)." "0,1" textline " " bitfld.word 0x0 8. " SCL_I_FUNC ,SCL line input value (functional mode)." "0,1" bitfld.word 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.word 0x0 11. " SSB ,Set all status bits inI2C_IRQSTATUS_RAW [14:0]." "0,1" bitfld.word 0x0 12.--13. " TMODE ,Test mode select." "0,1,2,3" textline " " bitfld.word 0x0 14. " FREE ,Free running mode (on breakpoint)" "0,1" bitfld.word 0x0 15. " ST_EN ,System test enable." "0,1" group.byte 0xC0++0x1 line.word 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." bitfld.word 0x0 0.--5. " TXSTAT ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 6.--7. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.word 0x0 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 14.--15. " FIFODEPTH ,Internal FIFO buffers depth." "0,1,2,3" group.byte 0xC4++0x1 line.word 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x0 0.--9. 1. " OA1 ,Own address 1" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xC8++0x1 line.word 0x0 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x0 0.--9. 1. " OA2 ,Own address 2" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xCC++0x1 line.word 0x0 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x0 0.--9. 1. " OA3 ,Own address 3" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xD0++0x1 line.word 0x0 "I2C_ACTOA,I2C Active Own Address Register." bitfld.word 0x0 0. " OA0_ACT ,Own Address 0 active." "0,1" bitfld.word 0x0 1. " OA1_ACT ,Own Address 1 active." "0,1" textline " " bitfld.word 0x0 2. " OA2_ACT ,Own Address 2 active." "0,1" bitfld.word 0x0 3. " OA3_ACT ,Own Address 3 active." "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ,Reserved" group.byte 0xD4++0x1 line.word 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.word 0x0 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0." "0,1" bitfld.word 0x0 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1." "0,1" textline " " bitfld.word 0x0 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2." "0,1" bitfld.word 0x0 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3." "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "I2C1" base ad:0x48070000 width 21. group.byte 0x0++0x1 line.word 0x0 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility" hexmask.word 0x0 0.--15. 1. " REVISION ,IP Revision" group.byte 0x4++0x1 line.word 0x0 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility" hexmask.word 0x0 0.--15. 1. " REVISION ,IP Revision" group.byte 0x10++0x1 line.word 0x0 "I2C_SYSC,System Configuration register" bitfld.word 0x0 0. " AUTOIDLE ,Autoidle bit" "0,1" bitfld.word 0x0 1. " SRST ,SoftReset bit" "0,1" textline " " bitfld.word 0x0 2. " ENAWAKEUP ,Enable Wakeup control bit" "0,1" bitfld.word 0x0 3.--4. " IDLEMODE ,Idle Mode selection bits" "0,1,2,3" textline " " bitfld.word 0x0 5.--7. " RESERVED ,Reads return 0." "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "0,1,2,3" textline " " bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x20++0x1 line.word 0x0 "I2C_EOI,End Of Interrupt number specification" bitfld.word 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x24++0x1 line.word 0x0 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug" bitfld.word 0x0 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "0,1" bitfld.word 0x0 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "0,1" bitfld.word 0x0 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ status." "0,1" bitfld.word 0x0 7. " AERR ,Access Error IRQ status." "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ status." "0,1" bitfld.word 0x0 9. " AAS ,Address recognized as slave IRQ status." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun status. Writing into this bit has no effect." "0,1" textline " " bitfld.word 0x0 12. " BB ,Bus busy status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 13. " RDR ,Receive draining IRQ status." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit draining IRQ status." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x28++0x1 line.word 0x0 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.word 0x0 0. " AL ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" bitfld.word 0x0 3. " RRDY ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" textline " " bitfld.word 0x0 4. " XRDY ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" bitfld.word 0x0 5. " GC ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ enabled status." "0,1" bitfld.word 0x0 7. " AERR ,Access Error IRQ enabled status." "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ enabled status." "0,1" bitfld.word 0x0 9. " AAS ,Address recognized as slave IRQ enabled status." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enabled status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enabled status. Writing into this bit has no effect." "0,1" textline " " bitfld.word 0x0 12. " BB ,Bus busy enabled status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 13. " RDR ,Receive draining IRQ enabled status." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit draining IRQ enabled status." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x2C++0x1 line.word 0x0 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.word 0x0 0. " AL_IE ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AL]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 1. " NACK_IE ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [NACK]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 2. " ARDY_IE ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [ARDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 3. " RRDY_IE ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 4. " XRDY_IE ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XRDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 5. " GC_IE ,General call Interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [GC]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 6. " STC_IE ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [STC].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 7. " AERR_IE ,Access Error interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AERR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 8. " BF_IE ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [BF].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 9. " AAS_IE ,Addressed as Slave interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AAS].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enable set.Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enable set.Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR_IE ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [RDR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 14. " XDR_IE ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW[XDR].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x30++0x1 line.word 0x0 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.word 0x0 0. " AL_IE ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW[AL]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 1. " NACK_IE ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [NACK]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 2. " ARDY_IE ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [ARDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 3. " RRDY_IE ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 4. " XRDY_IE ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XRDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 5. " GC_IE ,General call Interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [GC]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 6. " STC_IE ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [STC].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 7. " AERR_IE ,Access Error interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AERR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 8. " BF_IE ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [BF].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 9. " AAS_IE ,Addressed as Slave interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AAS].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enable clear.Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enable clear.Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR_IE ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 14. " XDR_IE ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XDR].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x34++0x1 line.word 0x0 "I2C_WE,I2C wakeup enable vector." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x38++0x1 line.word 0x0 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.word 0x0 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x3C++0x1 line.word 0x0 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.word 0x0 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x40++0x1 line.word 0x0 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.word 0x0 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x44++0x1 line.word 0x0 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.word 0x0 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x48++0x1 line.word 0x0 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x4C++0x1 line.word 0x0 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x90++0x1 line.word 0x0 "I2C_SYSS,System Status register" bitfld.word 0x0 0. " RDONE ,Reset done bit" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x94++0x1 line.word 0x0 "I2C_BUF,Buffer Configuration register" bitfld.word 0x0 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 6. " TXFIFO_CLR ,Transmit FIFO clear" "0,1" textline " " bitfld.word 0x0 7. " XDMA_EN ,Transmit DMA channel enable" "0,1" bitfld.word 0x0 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x0 14. " RXFIFO_CLR ,Receive FIFO clear" "0,1" bitfld.word 0x0 15. " RDMA_EN ,Receive DMA channel enable" "0,1" group.byte 0x98++0x1 line.word 0x0 "I2C_CNT,Data counter register" hexmask.word 0x0 0.--15. 1. " DCOUNT ,Data count" group.byte 0x9C++0x1 line.word 0x0 "I2C_DATA,Data access register" hexmask.word.byte 0x0 0.--7. 1. " DATA ,Transmit/Receive data FIFO endpoint" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ,Reserved" group.byte 0xA4++0x1 line.word 0x0 "I2C_CON,I2C configuration register." bitfld.word 0x0 0. " STT ,Start condition (master mode only)." "0,1" bitfld.word 0x0 1. " STP ,Stop condition (master mode only)." "0,1" textline " " bitfld.word 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.word 0x0 4. " XOA3 ,Expand Own address 3." "0,1" textline " " bitfld.word 0x0 5. " XOA2 ,Expand Own address 2." "0,1" bitfld.word 0x0 6. " XOA1 ,Expand Own address 1." "0,1" textline " " bitfld.word 0x0 7. " XOA0 ,Expand Own address 0." "0,1" bitfld.word 0x0 8. " XSA ,Expand Slave address." "0,1" textline " " bitfld.word 0x0 9. " TRX ,Transmitter/Receiver mode (master mode only)." "0,1" bitfld.word 0x0 10. " MST ,Master/slave mode." "0,1" textline " " bitfld.word 0x0 11. " STB ,Start byte mode (master mode only)." "0,1" bitfld.word 0x0 12.--13. " OPMODE ,Operation mode selection." "0,1,2,3" textline " " bitfld.word 0x0 14. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 15. " I2C_EN ,I2C module enable." "0,1" group.byte 0xA8++0x1 line.word 0x0 "I2C_OA,Own address register" hexmask.word 0x0 0.--9. 1. " OA ,Own address" bitfld.word 0x0 10.--12. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 13.--15. " MCODE ,Master Code" "0,1,2,3,4,5,6,7" group.byte 0xAC++0x1 line.word 0x0 "I2C_SA,Slave address register" hexmask.word 0x0 0.--9. 1. " SA ,Slave address" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xB0++0x1 line.word 0x0 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x0 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 .............................. 0xFF: Divide by 256" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ,Reserved" group.byte 0xB4++0x1 line.word 0x0 "I2C_SCLL,I2C SCL Low Time Register." hexmask.word.byte 0x0 0.--7. 1. " SCLL ,Fast/standard mode SCL low timeThe value of the bit field is automatically increased by 7. ." hexmask.word.byte 0x0 8.--15. 1. " HSSCLL ,High speed mode SCL low timeThe value of the bit field is automatically increased by 7. ." group.byte 0xB8++0x1 line.word 0x0 "I2C_SCLH,I2C SCL High Time Register." hexmask.word.byte 0x0 0.--7. 1. " SCLH ,Fast/standard mode SCL high timeThe value of the bit field is automatically increased by 5. ." hexmask.word.byte 0x0 8.--15. 1. " HSSCLH ,High speed mode SCL high timeThe value of the bit field is automatically increased by 5. ." group.byte 0xBC++0x1 line.word 0x0 "I2C_SYSTEST,I2C System Test Register." bitfld.word 0x0 0. " SDA_O ,SDA line drive output value." "0,1" bitfld.word 0x0 1. " SDA_I ,SDA line sense input value." "0,1" textline " " bitfld.word 0x0 2. " SCL_O ,SCL line drive output value." "0,1" bitfld.word 0x0 3. " SCL_I ,SCL line sense input value" "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " SDA_O_FUNC ,SDA line output value (functional mode)." "0,1" textline " " bitfld.word 0x0 6. " SDA_I_FUNC ,SDA line input value (functional mode)." "0,1" bitfld.word 0x0 7. " SCL_O_FUNC ,SCL line output value (functional mode)." "0,1" textline " " bitfld.word 0x0 8. " SCL_I_FUNC ,SCL line input value (functional mode)." "0,1" bitfld.word 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.word 0x0 11. " SSB ,Set all status bits inI2C_IRQSTATUS_RAW [14:0]." "0,1" bitfld.word 0x0 12.--13. " TMODE ,Test mode select." "0,1,2,3" textline " " bitfld.word 0x0 14. " FREE ,Free running mode (on breakpoint)" "0,1" bitfld.word 0x0 15. " ST_EN ,System test enable." "0,1" group.byte 0xC0++0x1 line.word 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." bitfld.word 0x0 0.--5. " TXSTAT ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 6.--7. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.word 0x0 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 14.--15. " FIFODEPTH ,Internal FIFO buffers depth." "0,1,2,3" group.byte 0xC4++0x1 line.word 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x0 0.--9. 1. " OA1 ,Own address 1" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xC8++0x1 line.word 0x0 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x0 0.--9. 1. " OA2 ,Own address 2" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xCC++0x1 line.word 0x0 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x0 0.--9. 1. " OA3 ,Own address 3" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xD0++0x1 line.word 0x0 "I2C_ACTOA,I2C Active Own Address Register." bitfld.word 0x0 0. " OA0_ACT ,Own Address 0 active." "0,1" bitfld.word 0x0 1. " OA1_ACT ,Own Address 1 active." "0,1" textline " " bitfld.word 0x0 2. " OA2_ACT ,Own Address 2 active." "0,1" bitfld.word 0x0 3. " OA3_ACT ,Own Address 3 active." "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ,Reserved" group.byte 0xD4++0x1 line.word 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.word 0x0 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0." "0,1" bitfld.word 0x0 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1." "0,1" textline " " bitfld.word 0x0 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2." "0,1" bitfld.word 0x0 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3." "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "I2C2" base ad:0x48072000 width 21. group.byte 0x0++0x1 line.word 0x0 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility" hexmask.word 0x0 0.--15. 1. " REVISION ,IP Revision" group.byte 0x4++0x1 line.word 0x0 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility" hexmask.word 0x0 0.--15. 1. " REVISION ,IP Revision" group.byte 0x10++0x1 line.word 0x0 "I2C_SYSC,System Configuration register" bitfld.word 0x0 0. " AUTOIDLE ,Autoidle bit" "0,1" bitfld.word 0x0 1. " SRST ,SoftReset bit" "0,1" textline " " bitfld.word 0x0 2. " ENAWAKEUP ,Enable Wakeup control bit" "0,1" bitfld.word 0x0 3.--4. " IDLEMODE ,Idle Mode selection bits" "0,1,2,3" textline " " bitfld.word 0x0 5.--7. " RESERVED ,Reads return 0." "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "0,1,2,3" textline " " bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x20++0x1 line.word 0x0 "I2C_EOI,End Of Interrupt number specification" bitfld.word 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x24++0x1 line.word 0x0 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug" bitfld.word 0x0 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "0,1" bitfld.word 0x0 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "0,1" bitfld.word 0x0 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ status." "0,1" bitfld.word 0x0 7. " AERR ,Access Error IRQ status." "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ status." "0,1" bitfld.word 0x0 9. " AAS ,Address recognized as slave IRQ status." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun status. Writing into this bit has no effect." "0,1" textline " " bitfld.word 0x0 12. " BB ,Bus busy status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 13. " RDR ,Receive draining IRQ status." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit draining IRQ status." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x28++0x1 line.word 0x0 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.word 0x0 0. " AL ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" bitfld.word 0x0 3. " RRDY ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" textline " " bitfld.word 0x0 4. " XRDY ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" bitfld.word 0x0 5. " GC ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ enabled status." "0,1" bitfld.word 0x0 7. " AERR ,Access Error IRQ enabled status." "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ enabled status." "0,1" bitfld.word 0x0 9. " AAS ,Address recognized as slave IRQ enabled status." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enabled status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enabled status. Writing into this bit has no effect." "0,1" textline " " bitfld.word 0x0 12. " BB ,Bus busy enabled status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 13. " RDR ,Receive draining IRQ enabled status." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit draining IRQ enabled status." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x2C++0x1 line.word 0x0 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.word 0x0 0. " AL_IE ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AL]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 1. " NACK_IE ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [NACK]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 2. " ARDY_IE ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [ARDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 3. " RRDY_IE ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 4. " XRDY_IE ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XRDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 5. " GC_IE ,General call Interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [GC]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 6. " STC_IE ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [STC].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 7. " AERR_IE ,Access Error interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AERR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 8. " BF_IE ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [BF].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 9. " AAS_IE ,Addressed as Slave interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AAS].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enable set.Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enable set.Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR_IE ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [RDR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 14. " XDR_IE ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW[XDR].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x30++0x1 line.word 0x0 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.word 0x0 0. " AL_IE ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW[AL]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 1. " NACK_IE ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [NACK]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 2. " ARDY_IE ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [ARDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 3. " RRDY_IE ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 4. " XRDY_IE ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XRDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 5. " GC_IE ,General call Interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [GC]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 6. " STC_IE ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [STC].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 7. " AERR_IE ,Access Error interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AERR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 8. " BF_IE ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [BF].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 9. " AAS_IE ,Addressed as Slave interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AAS].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enable clear.Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enable clear.Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR_IE ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 14. " XDR_IE ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XDR].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x34++0x1 line.word 0x0 "I2C_WE,I2C wakeup enable vector." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x38++0x1 line.word 0x0 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.word 0x0 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x3C++0x1 line.word 0x0 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.word 0x0 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x40++0x1 line.word 0x0 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.word 0x0 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x44++0x1 line.word 0x0 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.word 0x0 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x48++0x1 line.word 0x0 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x4C++0x1 line.word 0x0 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x90++0x1 line.word 0x0 "I2C_SYSS,System Status register" bitfld.word 0x0 0. " RDONE ,Reset done bit" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x94++0x1 line.word 0x0 "I2C_BUF,Buffer Configuration register" bitfld.word 0x0 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 6. " TXFIFO_CLR ,Transmit FIFO clear" "0,1" textline " " bitfld.word 0x0 7. " XDMA_EN ,Transmit DMA channel enable" "0,1" bitfld.word 0x0 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x0 14. " RXFIFO_CLR ,Receive FIFO clear" "0,1" bitfld.word 0x0 15. " RDMA_EN ,Receive DMA channel enable" "0,1" group.byte 0x98++0x1 line.word 0x0 "I2C_CNT,Data counter register" hexmask.word 0x0 0.--15. 1. " DCOUNT ,Data count" group.byte 0x9C++0x1 line.word 0x0 "I2C_DATA,Data access register" hexmask.word.byte 0x0 0.--7. 1. " DATA ,Transmit/Receive data FIFO endpoint" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ,Reserved" group.byte 0xA4++0x1 line.word 0x0 "I2C_CON,I2C configuration register." bitfld.word 0x0 0. " STT ,Start condition (master mode only)." "0,1" bitfld.word 0x0 1. " STP ,Stop condition (master mode only)." "0,1" textline " " bitfld.word 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.word 0x0 4. " XOA3 ,Expand Own address 3." "0,1" textline " " bitfld.word 0x0 5. " XOA2 ,Expand Own address 2." "0,1" bitfld.word 0x0 6. " XOA1 ,Expand Own address 1." "0,1" textline " " bitfld.word 0x0 7. " XOA0 ,Expand Own address 0." "0,1" bitfld.word 0x0 8. " XSA ,Expand Slave address." "0,1" textline " " bitfld.word 0x0 9. " TRX ,Transmitter/Receiver mode (master mode only)." "0,1" bitfld.word 0x0 10. " MST ,Master/slave mode." "0,1" textline " " bitfld.word 0x0 11. " STB ,Start byte mode (master mode only)." "0,1" bitfld.word 0x0 12.--13. " OPMODE ,Operation mode selection." "0,1,2,3" textline " " bitfld.word 0x0 14. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 15. " I2C_EN ,I2C module enable." "0,1" group.byte 0xA8++0x1 line.word 0x0 "I2C_OA,Own address register" hexmask.word 0x0 0.--9. 1. " OA ,Own address" bitfld.word 0x0 10.--12. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 13.--15. " MCODE ,Master Code" "0,1,2,3,4,5,6,7" group.byte 0xAC++0x1 line.word 0x0 "I2C_SA,Slave address register" hexmask.word 0x0 0.--9. 1. " SA ,Slave address" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xB0++0x1 line.word 0x0 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x0 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 .............................. 0xFF: Divide by 256" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ,Reserved" group.byte 0xB4++0x1 line.word 0x0 "I2C_SCLL,I2C SCL Low Time Register." hexmask.word.byte 0x0 0.--7. 1. " SCLL ,Fast/standard mode SCL low timeThe value of the bit field is automatically increased by 7. ." hexmask.word.byte 0x0 8.--15. 1. " HSSCLL ,High speed mode SCL low timeThe value of the bit field is automatically increased by 7. ." group.byte 0xB8++0x1 line.word 0x0 "I2C_SCLH,I2C SCL High Time Register." hexmask.word.byte 0x0 0.--7. 1. " SCLH ,Fast/standard mode SCL high timeThe value of the bit field is automatically increased by 5. ." hexmask.word.byte 0x0 8.--15. 1. " HSSCLH ,High speed mode SCL high timeThe value of the bit field is automatically increased by 5. ." group.byte 0xBC++0x1 line.word 0x0 "I2C_SYSTEST,I2C System Test Register." bitfld.word 0x0 0. " SDA_O ,SDA line drive output value." "0,1" bitfld.word 0x0 1. " SDA_I ,SDA line sense input value." "0,1" textline " " bitfld.word 0x0 2. " SCL_O ,SCL line drive output value." "0,1" bitfld.word 0x0 3. " SCL_I ,SCL line sense input value" "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " SDA_O_FUNC ,SDA line output value (functional mode)." "0,1" textline " " bitfld.word 0x0 6. " SDA_I_FUNC ,SDA line input value (functional mode)." "0,1" bitfld.word 0x0 7. " SCL_O_FUNC ,SCL line output value (functional mode)." "0,1" textline " " bitfld.word 0x0 8. " SCL_I_FUNC ,SCL line input value (functional mode)." "0,1" bitfld.word 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.word 0x0 11. " SSB ,Set all status bits inI2C_IRQSTATUS_RAW [14:0]." "0,1" bitfld.word 0x0 12.--13. " TMODE ,Test mode select." "0,1,2,3" textline " " bitfld.word 0x0 14. " FREE ,Free running mode (on breakpoint)" "0,1" bitfld.word 0x0 15. " ST_EN ,System test enable." "0,1" group.byte 0xC0++0x1 line.word 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." bitfld.word 0x0 0.--5. " TXSTAT ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 6.--7. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.word 0x0 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 14.--15. " FIFODEPTH ,Internal FIFO buffers depth." "0,1,2,3" group.byte 0xC4++0x1 line.word 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x0 0.--9. 1. " OA1 ,Own address 1" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xC8++0x1 line.word 0x0 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x0 0.--9. 1. " OA2 ,Own address 2" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xCC++0x1 line.word 0x0 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x0 0.--9. 1. " OA3 ,Own address 3" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xD0++0x1 line.word 0x0 "I2C_ACTOA,I2C Active Own Address Register." bitfld.word 0x0 0. " OA0_ACT ,Own Address 0 active." "0,1" bitfld.word 0x0 1. " OA1_ACT ,Own Address 1 active." "0,1" textline " " bitfld.word 0x0 2. " OA2_ACT ,Own Address 2 active." "0,1" bitfld.word 0x0 3. " OA3_ACT ,Own Address 3 active." "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ,Reserved" group.byte 0xD4++0x1 line.word 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.word 0x0 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0." "0,1" bitfld.word 0x0 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1." "0,1" textline " " bitfld.word 0x0 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2." "0,1" bitfld.word 0x0 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3." "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "I2C4" base ad:0x4807A000 width 21. group.byte 0x0++0x1 line.word 0x0 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility" hexmask.word 0x0 0.--15. 1. " REVISION ,IP Revision" group.byte 0x4++0x1 line.word 0x0 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility" hexmask.word 0x0 0.--15. 1. " REVISION ,IP Revision" group.byte 0x10++0x1 line.word 0x0 "I2C_SYSC,System Configuration register" bitfld.word 0x0 0. " AUTOIDLE ,Autoidle bit" "0,1" bitfld.word 0x0 1. " SRST ,SoftReset bit" "0,1" textline " " bitfld.word 0x0 2. " ENAWAKEUP ,Enable Wakeup control bit" "0,1" bitfld.word 0x0 3.--4. " IDLEMODE ,Idle Mode selection bits" "0,1,2,3" textline " " bitfld.word 0x0 5.--7. " RESERVED ,Reads return 0." "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "0,1,2,3" textline " " bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x20++0x1 line.word 0x0 "I2C_EOI,End Of Interrupt number specification" bitfld.word 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x24++0x1 line.word 0x0 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug" bitfld.word 0x0 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "0,1" bitfld.word 0x0 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "0,1" bitfld.word 0x0 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ status." "0,1" bitfld.word 0x0 7. " AERR ,Access Error IRQ status." "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ status." "0,1" bitfld.word 0x0 9. " AAS ,Address recognized as slave IRQ status." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun status. Writing into this bit has no effect." "0,1" textline " " bitfld.word 0x0 12. " BB ,Bus busy status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 13. " RDR ,Receive draining IRQ status." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit draining IRQ status." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x28++0x1 line.word 0x0 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.word 0x0 0. " AL ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" bitfld.word 0x0 3. " RRDY ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" textline " " bitfld.word 0x0 4. " XRDY ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" bitfld.word 0x0 5. " GC ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ enabled status." "0,1" bitfld.word 0x0 7. " AERR ,Access Error IRQ enabled status." "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ enabled status." "0,1" bitfld.word 0x0 9. " AAS ,Address recognized as slave IRQ enabled status." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enabled status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enabled status. Writing into this bit has no effect." "0,1" textline " " bitfld.word 0x0 12. " BB ,Bus busy enabled status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 13. " RDR ,Receive draining IRQ enabled status." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit draining IRQ enabled status." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x2C++0x1 line.word 0x0 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.word 0x0 0. " AL_IE ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AL]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 1. " NACK_IE ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [NACK]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 2. " ARDY_IE ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [ARDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 3. " RRDY_IE ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 4. " XRDY_IE ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XRDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 5. " GC_IE ,General call Interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [GC]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 6. " STC_IE ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [STC].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 7. " AERR_IE ,Access Error interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AERR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 8. " BF_IE ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [BF].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 9. " AAS_IE ,Addressed as Slave interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AAS].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enable set.Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enable set.Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR_IE ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [RDR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 14. " XDR_IE ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW[XDR].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x30++0x1 line.word 0x0 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.word 0x0 0. " AL_IE ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW[AL]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 1. " NACK_IE ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [NACK]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 2. " ARDY_IE ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [ARDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 3. " RRDY_IE ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 4. " XRDY_IE ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XRDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 5. " GC_IE ,General call Interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [GC]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 6. " STC_IE ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [STC].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 7. " AERR_IE ,Access Error interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AERR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 8. " BF_IE ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [BF].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 9. " AAS_IE ,Addressed as Slave interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AAS].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enable clear.Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enable clear.Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR_IE ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 14. " XDR_IE ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XDR].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x34++0x1 line.word 0x0 "I2C_WE,I2C wakeup enable vector." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x38++0x1 line.word 0x0 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.word 0x0 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x3C++0x1 line.word 0x0 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.word 0x0 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x40++0x1 line.word 0x0 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.word 0x0 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x44++0x1 line.word 0x0 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.word 0x0 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x48++0x1 line.word 0x0 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x4C++0x1 line.word 0x0 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x90++0x1 line.word 0x0 "I2C_SYSS,System Status register" bitfld.word 0x0 0. " RDONE ,Reset done bit" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x94++0x1 line.word 0x0 "I2C_BUF,Buffer Configuration register" bitfld.word 0x0 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 6. " TXFIFO_CLR ,Transmit FIFO clear" "0,1" textline " " bitfld.word 0x0 7. " XDMA_EN ,Transmit DMA channel enable" "0,1" bitfld.word 0x0 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x0 14. " RXFIFO_CLR ,Receive FIFO clear" "0,1" bitfld.word 0x0 15. " RDMA_EN ,Receive DMA channel enable" "0,1" group.byte 0x98++0x1 line.word 0x0 "I2C_CNT,Data counter register" hexmask.word 0x0 0.--15. 1. " DCOUNT ,Data count" group.byte 0x9C++0x1 line.word 0x0 "I2C_DATA,Data access register" hexmask.word.byte 0x0 0.--7. 1. " DATA ,Transmit/Receive data FIFO endpoint" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ,Reserved" group.byte 0xA4++0x1 line.word 0x0 "I2C_CON,I2C configuration register." bitfld.word 0x0 0. " STT ,Start condition (master mode only)." "0,1" bitfld.word 0x0 1. " STP ,Stop condition (master mode only)." "0,1" textline " " bitfld.word 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.word 0x0 4. " XOA3 ,Expand Own address 3." "0,1" textline " " bitfld.word 0x0 5. " XOA2 ,Expand Own address 2." "0,1" bitfld.word 0x0 6. " XOA1 ,Expand Own address 1." "0,1" textline " " bitfld.word 0x0 7. " XOA0 ,Expand Own address 0." "0,1" bitfld.word 0x0 8. " XSA ,Expand Slave address." "0,1" textline " " bitfld.word 0x0 9. " TRX ,Transmitter/Receiver mode (master mode only)." "0,1" bitfld.word 0x0 10. " MST ,Master/slave mode." "0,1" textline " " bitfld.word 0x0 11. " STB ,Start byte mode (master mode only)." "0,1" bitfld.word 0x0 12.--13. " OPMODE ,Operation mode selection." "0,1,2,3" textline " " bitfld.word 0x0 14. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 15. " I2C_EN ,I2C module enable." "0,1" group.byte 0xA8++0x1 line.word 0x0 "I2C_OA,Own address register" hexmask.word 0x0 0.--9. 1. " OA ,Own address" bitfld.word 0x0 10.--12. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 13.--15. " MCODE ,Master Code" "0,1,2,3,4,5,6,7" group.byte 0xAC++0x1 line.word 0x0 "I2C_SA,Slave address register" hexmask.word 0x0 0.--9. 1. " SA ,Slave address" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xB0++0x1 line.word 0x0 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x0 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 .............................. 0xFF: Divide by 256" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ,Reserved" group.byte 0xB4++0x1 line.word 0x0 "I2C_SCLL,I2C SCL Low Time Register." hexmask.word.byte 0x0 0.--7. 1. " SCLL ,Fast/standard mode SCL low timeThe value of the bit field is automatically increased by 7. ." hexmask.word.byte 0x0 8.--15. 1. " HSSCLL ,High speed mode SCL low timeThe value of the bit field is automatically increased by 7. ." group.byte 0xB8++0x1 line.word 0x0 "I2C_SCLH,I2C SCL High Time Register." hexmask.word.byte 0x0 0.--7. 1. " SCLH ,Fast/standard mode SCL high timeThe value of the bit field is automatically increased by 5. ." hexmask.word.byte 0x0 8.--15. 1. " HSSCLH ,High speed mode SCL high timeThe value of the bit field is automatically increased by 5. ." group.byte 0xBC++0x1 line.word 0x0 "I2C_SYSTEST,I2C System Test Register." bitfld.word 0x0 0. " SDA_O ,SDA line drive output value." "0,1" bitfld.word 0x0 1. " SDA_I ,SDA line sense input value." "0,1" textline " " bitfld.word 0x0 2. " SCL_O ,SCL line drive output value." "0,1" bitfld.word 0x0 3. " SCL_I ,SCL line sense input value" "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " SDA_O_FUNC ,SDA line output value (functional mode)." "0,1" textline " " bitfld.word 0x0 6. " SDA_I_FUNC ,SDA line input value (functional mode)." "0,1" bitfld.word 0x0 7. " SCL_O_FUNC ,SCL line output value (functional mode)." "0,1" textline " " bitfld.word 0x0 8. " SCL_I_FUNC ,SCL line input value (functional mode)." "0,1" bitfld.word 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.word 0x0 11. " SSB ,Set all status bits inI2C_IRQSTATUS_RAW [14:0]." "0,1" bitfld.word 0x0 12.--13. " TMODE ,Test mode select." "0,1,2,3" textline " " bitfld.word 0x0 14. " FREE ,Free running mode (on breakpoint)" "0,1" bitfld.word 0x0 15. " ST_EN ,System test enable." "0,1" group.byte 0xC0++0x1 line.word 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." bitfld.word 0x0 0.--5. " TXSTAT ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 6.--7. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.word 0x0 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 14.--15. " FIFODEPTH ,Internal FIFO buffers depth." "0,1,2,3" group.byte 0xC4++0x1 line.word 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x0 0.--9. 1. " OA1 ,Own address 1" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xC8++0x1 line.word 0x0 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x0 0.--9. 1. " OA2 ,Own address 2" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xCC++0x1 line.word 0x0 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x0 0.--9. 1. " OA3 ,Own address 3" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xD0++0x1 line.word 0x0 "I2C_ACTOA,I2C Active Own Address Register." bitfld.word 0x0 0. " OA0_ACT ,Own Address 0 active." "0,1" bitfld.word 0x0 1. " OA1_ACT ,Own Address 1 active." "0,1" textline " " bitfld.word 0x0 2. " OA2_ACT ,Own Address 2 active." "0,1" bitfld.word 0x0 3. " OA3_ACT ,Own Address 3 active." "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ,Reserved" group.byte 0xD4++0x1 line.word 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.word 0x0 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0." "0,1" bitfld.word 0x0 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1." "0,1" textline " " bitfld.word 0x0 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2." "0,1" bitfld.word 0x0 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3." "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "I2C5" base ad:0x4807C000 width 21. group.byte 0x0++0x1 line.word 0x0 "I2C_REVNB_LO,Module Revision Identifier Used by software to track features, bugs, and compatibility" hexmask.word 0x0 0.--15. 1. " REVISION ,IP Revision" group.byte 0x4++0x1 line.word 0x0 "I2C_REVNB_HI,Module Revision Identifeir Used by software to track features, bugs, and compatibility" hexmask.word 0x0 0.--15. 1. " REVISION ,IP Revision" group.byte 0x10++0x1 line.word 0x0 "I2C_SYSC,System Configuration register" bitfld.word 0x0 0. " AUTOIDLE ,Autoidle bit" "0,1" bitfld.word 0x0 1. " SRST ,SoftReset bit" "0,1" textline " " bitfld.word 0x0 2. " ENAWAKEUP ,Enable Wakeup control bit" "0,1" bitfld.word 0x0 3.--4. " IDLEMODE ,Idle Mode selection bits" "0,1,2,3" textline " " bitfld.word 0x0 5.--7. " RESERVED ,Reads return 0." "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "0,1,2,3" textline " " bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x20++0x1 line.word 0x0 "I2C_EOI,End Of Interrupt number specification" bitfld.word 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x24++0x1 line.word 0x0 "I2C_IRQSTATUS_RAW,Per-event raw interrupt status vector. The raw status is set even if event is not enabled. Write 1 to set the (raw) status. Used mostly for debug" bitfld.word 0x0 0. " AL ,Arbitration lost IRQ status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgement IRQ status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar." "0,1" bitfld.word 0x0 3. " RRDY ,Receive data ready IRQ status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 4. " XRDY ,Transmit data ready IRQ status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar." "0,1" bitfld.word 0x0 5. " GC ,General call IRQ status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ status." "0,1" bitfld.word 0x0 7. " AERR ,Access Error IRQ status." "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ status." "0,1" bitfld.word 0x0 9. " AAS ,Address recognized as slave IRQ status." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun status. Writing into this bit has no effect." "0,1" textline " " bitfld.word 0x0 12. " BB ,Bus busy status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 13. " RDR ,Receive draining IRQ status." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit draining IRQ status." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x28++0x1 line.word 0x0 "I2C_IRQSTATUS,Per-event enabled interrupt status vector" bitfld.word 0x0 0. " AL ,Arbitration lost IRQ enabled status. This bit is automatically set by the hardware when it loses the Arbitration in master transmit mode, an interrupt is signaled to IRQ_Crossbar. During reads, it always returns 0." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgement IRQ enabled status. Bit is set when No Acknowledge has been received, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear this bit." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ enabled status. When set to 1 it indicates that previous access has been performed and registers are ready to be accessed again. An interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" bitfld.word 0x0 3. " RRDY ,Receive data ready IRQ enabled status. Set to 1 by core when receiver mode, a new data is able to be read. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" textline " " bitfld.word 0x0 4. " XRDY ,Transmit data ready IRQ enabled status. Set to 1 by core when transmitter and when new data is requested. When set to 1 by core, an interrupt is signaled to IRQ_Crossbar. Write 1 to clear." "0,1" bitfld.word 0x0 5. " GC ,General call IRQ enabled status. Set to 1 by core when General call address detected and interrupt signaled to IRQ_Crossbar. Write 1 to clear." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ enabled status." "0,1" bitfld.word 0x0 7. " AERR ,Access Error IRQ enabled status." "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ enabled status." "0,1" bitfld.word 0x0 9. " AAS ,Address recognized as slave IRQ enabled status." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enabled status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enabled status. Writing into this bit has no effect." "0,1" textline " " bitfld.word 0x0 12. " BB ,Bus busy enabled status. Writing into this bit has no effect." "0,1" bitfld.word 0x0 13. " RDR ,Receive draining IRQ enabled status." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit draining IRQ enabled status." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x2C++0x1 line.word 0x0 "I2C_IRQENABLE_SET,Per-event interrupt enable bit vector." bitfld.word 0x0 0. " AL_IE ,Arbitration lost interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AL]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 1. " NACK_IE ,No acknowledgement interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [NACK]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 2. " ARDY_IE ,Register access ready interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [ARDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 3. " RRDY_IE ,Receive data ready interrupt enable set. Unmask the interrupt signaled by bit in I2C_IRQSTTUS_RAW [RRDY]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 4. " XRDY_IE ,Transmit data ready interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XRDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 5. " GC_IE ,General call Interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [GC]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 6. " STC_IE ,Start Condition interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [STC].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 7. " AERR_IE ,Access Error interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AERR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 8. " BF_IE ,Bus Free interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [BF].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 9. " AAS_IE ,Addressed as Slave interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AAS].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enable set.Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enable set.Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR_IE ,Receive Draining interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [RDR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 14. " XDR_IE ,Transmit Draining interrupt enable set. Unmask the interrupt signaled by bit inI2C_IRQSTATUS_RAW[XDR].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x30++0x1 line.word 0x0 "I2C_IRQENABLE_CLR,Per-event interrupt clear bit vector." bitfld.word 0x0 0. " AL_IE ,Arbitration lost interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW[AL]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 1. " NACK_IE ,No acknowledgement interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [NACK]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 2. " ARDY_IE ,Register access ready interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [ARDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 3. " RRDY_IE ,Receive data ready interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RRDY]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 4. " XRDY_IE ,Transmit data ready interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XRDY]Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 5. " GC_IE ,General call Interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [GC]Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 6. " STC_IE ,Start Condition interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [STC].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 7. " AERR_IE ,Access Error interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AERR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 8. " BF_IE ,Bus Free interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [BF].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 9. " AAS_IE ,Addressed as Slave interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [AAS].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow enable clear.Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun enable clear.Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR_IE ,Receive Draining interrupt enable clear. Mask the interrupt signaled by bit in I2C_IRQSTAUS_RAW [RDR].Read: enum=disable . Write: enum=enable ." "0,1" textline " " bitfld.word 0x0 14. " XDR_IE ,Transmit Draining interrupt enable clear. Mask the interrupt signaled by bit inI2C_IRQSTATUS_RAW [XDR].Read: enum=disable . Write: enum=enable ." "0,1" bitfld.word 0x0 15. " RESERVED ,Write 0s for future compatibility. Read returns 0." "0,1" group.byte 0x34++0x1 line.word 0x0 "I2C_WE,I2C wakeup enable vector." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x38++0x1 line.word 0x0 "I2C_DMARXENABLE_SET,Per-event DMA RX enable set." bitfld.word 0x0 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x3C++0x1 line.word 0x0 "I2C_DMATXENABLE_SET,Per-event DMA TX enable set." bitfld.word 0x0 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x40++0x1 line.word 0x0 "I2C_DMARXENABLE_CLR,Per-event DMA RX enable clear." bitfld.word 0x0 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x44++0x1 line.word 0x0 "I2C_DMATXENABLE_CLR,Per-event DMA TX enable clear." bitfld.word 0x0 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x48++0x1 line.word 0x0 "I2C_DMARXWAKE_EN,Per-event DMA RX wakeup enable." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x4C++0x1 line.word 0x0 "I2C_DMATXWAKE_EN,Per-event DMA TX wakeup enable." bitfld.word 0x0 0. " AL ,Arbitration lost IRQ wakeup set." "0,1" bitfld.word 0x0 1. " NACK ,No acknowledgment IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 2. " ARDY ,Register access ready IRQ wakeup set." "0,1" bitfld.word 0x0 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " GC ,General call IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 6. " STC ,Start Condition IRQ wakeup set." "0,1" bitfld.word 0x0 7. " RESERVED ,Reserved" "0,1" textline " " bitfld.word 0x0 8. " BF ,Bus Free IRQ wakeup set." "0,1" bitfld.word 0x0 9. " AAS ,Address as slave IRQ wakeup set." "0,1" textline " " bitfld.word 0x0 10. " XUDF ,Transmit underflow wakeup set." "0,1" bitfld.word 0x0 11. " ROVR ,Receive overrun wakeup set." "0,1" textline " " bitfld.word 0x0 12. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 13. " RDR ,Receive Draining wakeup set." "0,1" textline " " bitfld.word 0x0 14. " XDR ,Transmit Draining wakeup set." "0,1" bitfld.word 0x0 15. " RESERVED ,Reserved" "0,1" group.byte 0x90++0x1 line.word 0x0 "I2C_SYSS,System Status register" bitfld.word 0x0 0. " RDONE ,Reset done bit" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ,Reserved" group.byte 0x94++0x1 line.word 0x0 "I2C_BUF,Buffer Configuration register" bitfld.word 0x0 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 6. " TXFIFO_CLR ,Transmit FIFO clear" "0,1" textline " " bitfld.word 0x0 7. " XDMA_EN ,Transmit DMA channel enable" "0,1" bitfld.word 0x0 8.--13. " RXTRSH ,Threshold value for FIFO buffer in RX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.word 0x0 14. " RXFIFO_CLR ,Receive FIFO clear" "0,1" bitfld.word 0x0 15. " RDMA_EN ,Receive DMA channel enable" "0,1" group.byte 0x98++0x1 line.word 0x0 "I2C_CNT,Data counter register" hexmask.word 0x0 0.--15. 1. " DCOUNT ,Data count" group.byte 0x9C++0x1 line.word 0x0 "I2C_DATA,Data access register" hexmask.word.byte 0x0 0.--7. 1. " DATA ,Transmit/Receive data FIFO endpoint" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ,Reserved" group.byte 0xA4++0x1 line.word 0x0 "I2C_CON,I2C configuration register." bitfld.word 0x0 0. " STT ,Start condition (master mode only)." "0,1" bitfld.word 0x0 1. " STP ,Stop condition (master mode only)." "0,1" textline " " bitfld.word 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.word 0x0 4. " XOA3 ,Expand Own address 3." "0,1" textline " " bitfld.word 0x0 5. " XOA2 ,Expand Own address 2." "0,1" bitfld.word 0x0 6. " XOA1 ,Expand Own address 1." "0,1" textline " " bitfld.word 0x0 7. " XOA0 ,Expand Own address 0." "0,1" bitfld.word 0x0 8. " XSA ,Expand Slave address." "0,1" textline " " bitfld.word 0x0 9. " TRX ,Transmitter/Receiver mode (master mode only)." "0,1" bitfld.word 0x0 10. " MST ,Master/slave mode." "0,1" textline " " bitfld.word 0x0 11. " STB ,Start byte mode (master mode only)." "0,1" bitfld.word 0x0 12.--13. " OPMODE ,Operation mode selection." "0,1,2,3" textline " " bitfld.word 0x0 14. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 15. " I2C_EN ,I2C module enable." "0,1" group.byte 0xA8++0x1 line.word 0x0 "I2C_OA,Own address register" hexmask.word 0x0 0.--9. 1. " OA ,Own address" bitfld.word 0x0 10.--12. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 13.--15. " MCODE ,Master Code" "0,1,2,3,4,5,6,7" group.byte 0xAC++0x1 line.word 0x0 "I2C_SA,Slave address register" hexmask.word 0x0 0.--9. 1. " SA ,Slave address" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xB0++0x1 line.word 0x0 "I2C_PSC,I2C Clock Prescaler Register" hexmask.word.byte 0x0 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value 0x0: Divide by 1 0x1: Divide by 2 .............................. 0xFF: Divide by 256" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ,Reserved" group.byte 0xB4++0x1 line.word 0x0 "I2C_SCLL,I2C SCL Low Time Register." hexmask.word.byte 0x0 0.--7. 1. " SCLL ,Fast/standard mode SCL low timeThe value of the bit field is automatically increased by 7. ." hexmask.word.byte 0x0 8.--15. 1. " HSSCLL ,High speed mode SCL low timeThe value of the bit field is automatically increased by 7. ." group.byte 0xB8++0x1 line.word 0x0 "I2C_SCLH,I2C SCL High Time Register." hexmask.word.byte 0x0 0.--7. 1. " SCLH ,Fast/standard mode SCL high timeThe value of the bit field is automatically increased by 5. ." hexmask.word.byte 0x0 8.--15. 1. " HSSCLH ,High speed mode SCL high timeThe value of the bit field is automatically increased by 5. ." group.byte 0xBC++0x1 line.word 0x0 "I2C_SYSTEST,I2C System Test Register." bitfld.word 0x0 0. " SDA_O ,SDA line drive output value." "0,1" bitfld.word 0x0 1. " SDA_I ,SDA line sense input value." "0,1" textline " " bitfld.word 0x0 2. " SCL_O ,SCL line drive output value." "0,1" bitfld.word 0x0 3. " SCL_I ,SCL line sense input value" "0,1" textline " " bitfld.word 0x0 4. " RESERVED ,Reserved" "0,1" bitfld.word 0x0 5. " SDA_O_FUNC ,SDA line output value (functional mode)." "0,1" textline " " bitfld.word 0x0 6. " SDA_I_FUNC ,SDA line input value (functional mode)." "0,1" bitfld.word 0x0 7. " SCL_O_FUNC ,SCL line output value (functional mode)." "0,1" textline " " bitfld.word 0x0 8. " SCL_I_FUNC ,SCL line input value (functional mode)." "0,1" bitfld.word 0x0 9.--10. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.word 0x0 11. " SSB ,Set all status bits inI2C_IRQSTATUS_RAW [14:0]." "0,1" bitfld.word 0x0 12.--13. " TMODE ,Test mode select." "0,1,2,3" textline " " bitfld.word 0x0 14. " FREE ,Free running mode (on breakpoint)" "0,1" bitfld.word 0x0 15. " ST_EN ,System test enable." "0,1" group.byte 0xC0++0x1 line.word 0x0 "I2C_BUFSTAT,I2C Buffer Status Register." bitfld.word 0x0 0.--5. " TXSTAT ,TX Buffer Status." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 6.--7. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.word 0x0 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.word 0x0 14.--15. " FIFODEPTH ,Internal FIFO buffers depth." "0,1,2,3" group.byte 0xC4++0x1 line.word 0x0 "I2C_OA1,I2C Own Address 1 Register" hexmask.word 0x0 0.--9. 1. " OA1 ,Own address 1" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xC8++0x1 line.word 0x0 "I2C_OA2,I2C Own Address 2 Register" hexmask.word 0x0 0.--9. 1. " OA2 ,Own address 2" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xCC++0x1 line.word 0x0 "I2C_OA3,I2C Own Address 3 Register" hexmask.word 0x0 0.--9. 1. " OA3 ,Own address 3" bitfld.word 0x0 10.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0xD0++0x1 line.word 0x0 "I2C_ACTOA,I2C Active Own Address Register." bitfld.word 0x0 0. " OA0_ACT ,Own Address 0 active." "0,1" bitfld.word 0x0 1. " OA1_ACT ,Own Address 1 active." "0,1" textline " " bitfld.word 0x0 2. " OA2_ACT ,Own Address 2 active." "0,1" bitfld.word 0x0 3. " OA3_ACT ,Own Address 3 active." "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ,Reserved" group.byte 0xD4++0x1 line.word 0x0 "I2C_SBLOCK,I2C Clock Blocking Enable Register." bitfld.word 0x0 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0." "0,1" bitfld.word 0x0 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1." "0,1" textline " " bitfld.word 0x0 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2." "0,1" bitfld.word 0x0 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3." "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "HDQ1W" base ad:0x480B2000 width 17. group.byte 0x0++0x3 line.long 0x0 "HDQ_REVISION,This register contains the IP revision code" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x4++0x3 line.long 0x0 "HDQ_TX_DATA,This register contains the data to be transmitted." hexmask.long.byte 0x0 0.--7. 1. " TX_DATA ,Transmit data (used in both HDQ and 1-Wire modes)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x8++0x3 line.long 0x0 "HDQ_RX_DATA,This register contains the data to be received." hexmask.long.byte 0x0 0.--7. 1. " RX_DATA ,Receive data (used in both HDQ and 1-Wire modes)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reads returns 0" group.byte 0xC++0x3 line.long 0x0 "HDQ_CTRL_STATUS,This register provides status information about the module." bitfld.long 0x0 0. " MODE ,Mode selection bit 0x0: HDQ mode 0x1: 1-Wire mode" "0,1" bitfld.long 0x0 1. " DIR ,DIR bit, determines if next command is read or write 0x0: Write 0x1: Read" "0,1" textline " " bitfld.long 0x0 2. " INITIALIZATION ,Write 1 to send initialization pulse. Bit returns to 0 after pulse is sent." "0,1" bitfld.long 0x0 3. " PRESENCEDETECT ,Slave presence indicator. Actual only just after initialization time-out. Used in 1-Wire mode. Read-only flag. 0x0: No slave detected 0x1: Slave detected" "0,1" textline " " bitfld.long 0x0 4. " GO ,Go bit. Write 1 to start the appropriate operation. Bit returns to 0 after the operation is complete." "0,1" bitfld.long 0x0 5. " CLOCKENABLE ,Power-down mode bit 0x0: Clock disable (power down) 0x1: Clock enable" "0,1" textline " " bitfld.long 0x0 6. " INTERRUPTMASK ,Interrupt masking bit 0x0: Interrupts disable 0x1: Interrupts enable" "0,1" bitfld.long 0x0 7. " ONE_WIRE_SINGLE_BIT ,Single-bit mode for 1-Wire 0x0: Disabled 0x1: Enabled" "0,1" textline " " bitfld.long 0x0 8.--10. " BITFSM ,BITFSM delay value in 1.33 5s steps. 0x0 value corresponds to 1.33 5s." "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x10++0x3 line.long 0x0 "HDQ_INT_STATUS,This register controls interrupts status" bitfld.long 0x0 0. " TIMEOUT ,Presence detect/timeout interrupt flag. In 1-Wire mode, set to 1 if slave's presence detected. In HDQ mode, set to 1 if timeout on read occurs. Set to 0 when register read." "0,1" bitfld.long 0x0 1. " RXCOMPLETE ,Read-complete interrupt flag. Set to 1 if cause of interrupt. Set to 0 when register read." "0,1" textline " " bitfld.long 0x0 2. " TXCOMPLETE ,TX-complete interrupt flag. Set to 1 if cause of interrupt. Set to 0 when register read." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x14++0x3 line.long 0x0 "HDQ_SYSCONFIG,This register controls various bits" bitfld.long 0x0 0. " AUTOIDLE ,Interconnect idle. 0x0: Module clock is free-running. 0x1: Module is in power saving mode: Clock is running only when module is accessed or inside logic is in function to process events." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Start soft reset sequence. 0x0: Disabled 0x1: Enabled" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x18++0x3 line.long 0x0 "HDQ_SYSSTATUS,This register monitors the reset sequence." bitfld.long 0x0 0. " RESETDONE ,Reset monitoring. 0x0: The module is currently performing its reset. When the module is in power-down mode, set to 0 to indicate this fact. 0x1: The module has finished its reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0" width 0x0B tree.end tree "UART3" base ad:0x48020000 width 23. group.byte 0x0++0x3 line.long 0x0 "UART_DLL,This register, with, stores the 14-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.byte 0x0 0.--7. 1. " CLOCK_LSB ,Stores the 8-bit LSB divisor value" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the RHR. If the FIFO is disabled, location 0 of the FIFO stores the single data character.Note:If an overflow occurs, the data in the RHR is not overwritten." hexmask.long.byte 0x0 0.--7. 1. " RHR ,Receive holding register" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0" group.byte 0x0++0x3 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The THR is a 64-byte FIFO. The local host (LH) writes data to the THR. The data is placed in the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location 0 of the FIFO stores the data." hexmask.long.byte 0x0 0.--7. 1. " THR ,Transmit holding register" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_DLH,This register, with, stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." bitfld.long 0x0 0.--5. " CLOCK_MSB ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " RESERVED ,Read returns 0. Write has no effect." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_IER,Interrupt enable register" bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " LINE_STS_IT ," "0,1" bitfld.long 0x0 3. " MODEM_STS_IT ," "0,1" textline " " bitfld.long 0x0 4. " SLEEP_MODE ," "0,1" bitfld.long 0x0 5. " XOFF_IT ," "0,1" textline " " bitfld.long 0x0 6. " RTS_IT ," "0,1" bitfld.long 0x0 7. " CTS_IT ," "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated based on the value set in the BOF Length register (). In IR-CIR mode, contrary to the IR-IRDA mode, the TX_STATUS_IT has only one meaning corresponding to the case [0] = 0." bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " RX_STOP_IT ," "0,1" bitfld.long 0x0 3. " RX_OVERRUN_IT ," "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Not used in CIR mode" "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ," "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ,Not used in CIR mode" "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The TX_STATUS_IT interrupt reflects two possible conditions. The [0] should be read to determine the status in the event of this interrupt." bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " LAST_RX_BYTE_IT ," "0,1" bitfld.long 0x0 3. " RX_OVERRUN_IT ," "0,1" textline " " bitfld.long 0x0 4. " STS_FIFO_TRIG_IT ," "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ," "0,1" textline " " bitfld.long 0x0 6. " LINE_STS_IT ," "0,1" bitfld.long 0x0 7. " EOF_IT ," "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_EFR,Enhanced feature register" bitfld.long 0x0 0.--3. " SW_FLOW_CONTROL ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENHANCED_EN ,Enhanced functions write enable bit" "0,1" textline " " bitfld.long 0x0 5. " SPECIAL_CHAR_DETECT ," "0,1" bitfld.long 0x0 6. " AUTO_RTS_EN ,Auto-RTS enable bit" "0,1" textline " " bitfld.long 0x0 7. " AUTO_CTS_EN ,Auto-CTS enable bit" "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register" bitfld.long 0x0 0. " FIFO_EN ," "0,1" bitfld.long 0x0 1. " RX_FIFO_CLEAR ," "0,1" textline " " bitfld.long 0x0 2. " TX_FIFO_CLEAR ," "0,1" bitfld.long 0x0 3. " DMA_MODE ,This register is considered ifUART_SCR[0] = 0." "0,1" textline " " bitfld.long 0x0 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If UART_SCR[6] = 0 and UART_TLR[3:0] != 0000, TX_FIFO_TRIG is not considered. If UART_SCR[6] = 1, TX_FIFO_TRIG is 2 LSBs of the trigger level (1-63 on 6 bits) with the granularity 1" "0,1,2,3" bitfld.long 0x0 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If UART_SCR[7] = 0 and UART_TLR[7:4] != 0000, RX_FIFO_TRIG is not considered. If UART_SCR[7] = 1, RX_FIFO_TRIG is 2 LSBs of the trigger level (1-63 on 6 bits) with the granularity 1." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_IIR,Interrupt identification register." bitfld.long 0x0 0. " IT_PENDING ,Read 0x0: An interrupt is pending." "0,1" bitfld.long 0x0 1.--5. " IT_TYPE ,Read 0x0: Modem interrupt. Priority = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 6.--7. " FCR_MIRROR ,Mirror the contents ofUART_FCR[0] on both bits." "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." bitfld.long 0x0 0. " RHR_IT ,Read 0x0: RHR interrupt inactive" "0,1" bitfld.long 0x0 1. " THR_IT ,Read 0x0: THR interrupt inactive" "0,1" textline " " bitfld.long 0x0 2. " RX_STOP_IT ,Read 0x0: Receive stop interrupt inactive" "0,1" bitfld.long 0x0 3. " RX_OE_IT ,Read 0x0: RX overrun interrupt inactive" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Not used in CIR mode" "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ,Read 0x0: TX status interrupt inactive" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ,Not used in CIR mode" "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " RX_FIFO_LAST_BYTE_IT ," "0,1" bitfld.long 0x0 3. " RX_OE_IT ," "0,1" textline " " bitfld.long 0x0 4. " STS_FIFO_IT ," "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ," "0,1" textline " " bitfld.long 0x0 6. " LINE_STS_IT ," "0,1" bitfld.long 0x0 7. " EOF_IT ," "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0xC++0x3 line.long 0x0 "UART_LCR,Line control register" bitfld.long 0x0 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "0,1,2,3" bitfld.long 0x0 2. " NB_STOP ,Specifies the number of stop-bits" "0,1" textline " " bitfld.long 0x0 3. " PARITY_EN ,0x0: No parity" "0,1" bitfld.long 0x0 4. " PARITY_TYPE1 ," "0,1" textline " " bitfld.long 0x0 5. " PARITY_TYPE2 ,Selects the forced parity format (ifUART_LCR[3] = 1). If UART_LCR[5] = 1 and UART_LCR[4] = 0, the parity bit is forced to 1 in the transmitted and received data. If UART_LCR[5] = 1 and UART_LCR[4] = 1, the parity bit is forced to 0 in the transmitted and received data." "0,1" bitfld.long 0x0 6. " BREAK_EN ,Break control bit" "0,1" textline " " bitfld.long 0x0 7. " DIV_EN ," "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x10++0x3 line.long 0x0 "UART_MCR,Modem control register" bitfld.long 0x0 0. " DTR ,0x0: Force DTR* output to inactive (high)." "0,1" bitfld.long 0x0 1. " RTS ,In loopback, controls theUART_MSR[4] bit. If auto-RTS is enabled, the RTS* output is controlled by hardware flow control." "0,1" textline " " bitfld.long 0x0 2. " RI_STS_CH ,0x0: In loopback, forces RI* input high" "0,1" bitfld.long 0x0 3. " CD_STS_CH ,0x0: In loopback, forces DCD* input high and IRQ outputs to inactive state" "0,1" textline " " bitfld.long 0x0 4. " LOOPBACK_EN ,0x0: Normal operating mode" "0,1" bitfld.long 0x0 5. " XON_EN ,0x0: Disable XON any function." "0,1" textline " " bitfld.long 0x0 6. " TCR_TLR ,0x0: No action" "0,1" bitfld.long 0x0 7. " RESERVED ,Read returns 0. Write has no effect." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address" hexmask.long.byte 0x0 0.--7. 1. " XON_WORD1 ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x14++0x3 line.long 0x0 "UART_LSR,Line status register" bitfld.long 0x0 0. " RX_FIFO_E ,Read 0x0: No data in the RX FIFO" "0,1" bitfld.long 0x0 1. " RX_OE ,Read 0x0: No overrun error" "0,1" textline " " bitfld.long 0x0 2. " RX_PE ,Read 0x0: No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 3. " RX_FE ,Read 0x0: No framing error in data RX FIFO" "0,1" textline " " bitfld.long 0x0 4. " RX_BI ,Read 0x0: No break condition" "0,1" bitfld.long 0x0 5. " TX_FIFO_E ,Read 0x0: Transmit hold register (TX FIFO) is not empty." "0,1" textline " " bitfld.long 0x0 6. " TX_SR_E ,Read 0x0: Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 7. " RX_FIFO_STS ,Read 0x0: Normal operation" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" bitfld.long 0x0 0. " RX_FIFO_E ,Read 0x0: At least one data character in the RX FIFO" "0,1" bitfld.long 0x0 1.--4. " RESERVED ,Not used in CIR mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5. " RX_STOP ,The RX_STOP is generated based on the value set in the BOF Length register (UART_EBLR). It is cleared on a single read of the UART_LSR register." "0,1" bitfld.long 0x0 6. " RESERVED ,Not used in CIR mode" "0,1" textline " " bitfld.long 0x0 7. " THR_EMPTY ,Read 0x0: Transmit holding register (TX FIFO) is not empty." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." bitfld.long 0x0 0. " RX_FIFO_E ,Read 0x0: No data in the RX FIFO" "0,1" bitfld.long 0x0 1. " STS_FIFO_E ,Read 0x0: Status FIFO not empty" "0,1" textline " " bitfld.long 0x0 2. " CRC ,Read 0x0: No CRC error in frame" "0,1" bitfld.long 0x0 3. " ABORT ,Read 0x0: No abort pattern error in frame" "0,1" textline " " bitfld.long 0x0 4. " FRAME_TOO_LONG ,Read 0x0: No frame-too-long error in frame" "0,1" bitfld.long 0x0 5. " RX_LAST_BYTE ,Read 0x0: The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" textline " " bitfld.long 0x0 6. " STS_FIFO_FULL ,Read 0x0: Status FIFO not full" "0,1" bitfld.long 0x0 7. " THR_EMPTY ,Read 0x0: Transmit holding register (TX FIFO) is not empty." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.byte 0x0 0.--7. 1. " XON_WORD2 ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only." bitfld.long 0x0 0. " CTS_STS ," "0,1" bitfld.long 0x0 1. " DSR_STS ," "0,1" textline " " bitfld.long 0x0 2. " RI_STS ,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high. Cleared on a read." "0,1" bitfld.long 0x0 3. " DCD_STS ,Indicates that DCD* input (orUART_MCR[3] in loopback) changed. Cleared on a read." "0,1" textline " " bitfld.long 0x0 4. " NCTS_STS ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent toUART_MCR[1]." "0,1" bitfld.long 0x0 5. " NDSR_STS ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent toUART_MCR[0]." "0,1" textline " " bitfld.long 0x0 6. " NRI_STS ,This bit is the complement of the RI* input. In loopback mode, it is equivalent toUART_MCR[2]." "0,1" bitfld.long 0x0 7. " NCD_STS ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent toUART_MCR[3]." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register" bitfld.long 0x0 0.--3. " RX_FIFO_TRIG_HALT ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_FIFO_TRIG_START ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x18++0x3 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.byte 0x0 0.--7. 1. " XOFF_WORD1 ,Stores the 8-bit XOFF1 character used in UART modes" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x1C++0x3 line.long 0x0 "UART_SPR,Scratchpad register" hexmask.long.byte 0x0 0.--7. 1. " SPR_WORD ,Scratchpad register" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register" bitfld.long 0x0 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x1C++0x3 line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.byte 0x0 0.--7. 1. " XOFF_WORD2 ,Stores the 8-bit XOFF2 character used in UART modes." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x20++0x3 line.long 0x0 "UART_MDR1,Mode definition register 1" bitfld.long 0x0 0.--2. " MODE_SELECT ,0x0: UART 16x mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " IR_SLEEP ,0x0: IrDA/CIR sleep mode disabled" "0,1" textline " " bitfld.long 0x0 4. " SET_TXIR ,Used to configure the infrared transceiver" "0,1" bitfld.long 0x0 5. " SCT ,Store and control the transmission." "0,1" textline " " bitfld.long 0x0 6. " SIP_MODE ,MIR/FIR modes only" "0,1" bitfld.long 0x0 7. " FRAME_END_MODE ,IrDA mode only" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x24++0x3 line.long 0x0 "UART_MDR2,Mode definition register 2" bitfld.long 0x0 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt. When theUART_IIR[5] interrupt occurs, the meaning of the interrupt is:" "0,1" bitfld.long 0x0 1.--2. " STS_FIFO_TRIG ,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" textline " " bitfld.long 0x0 3. " UART_PULSE ,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x0 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" textline " " bitfld.long 0x0 6. " IRRXINVERT ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x0 7. " SET_TXIR_ALT ,Provide alternate function forUART_MDR1[4] (SET_TXIR)." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register" bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " CRC_ERROR ,Read 0x1: CRC error in frame at top of RX FIFO" "0,1" textline " " bitfld.long 0x0 2. " ABORT_DETECT ,Read 0x1: Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 3. " FRAME_TOO_LONG_ERROR ,Read 0x1: Frame-length too long error in frame at top of RX FIFO" "0,1" textline " " bitfld.long 0x0 4. " OE_ERROR ,Read 0x1: Overrun error in RX FIFO when frame at top of RX FIFO was received Note: Top of RX FIFO = Next frame to be read from RX FIFO" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low" hexmask.long.byte 0x0 0.--7. 1. " TXFLL ,LSB register used to specify the frame length" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist and reads always as 0x00." hexmask.long.byte 0x0 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "UART_TXFLH,Transmit frame length register high" bitfld.long 0x0 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write has no effect." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x30++0x3 line.long 0x0 "UART_RXFLL,Received frame length register low" hexmask.long.byte 0x0 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low" hexmask.long.byte 0x0 0.--7. 1. " SFREGL ,LSB part of the frame length" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high" bitfld.long 0x0 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Write has no effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high" bitfld.long 0x0 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register" bitfld.long 0x0 0.--5. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " XBOF_TYPE ,SIR xBOF select" "0,1" textline " " bitfld.long 0x0 7. " STS_FIFO_RESET ,Status FIFO reset. This bit is self-clearing." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register" bitfld.long 0x0 0.--4. " SPEED ,Used to report the speed identified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " BIT_BY_CHAR ,Read 0x0: 7-bit character identified" "0,1" textline " " bitfld.long 0x0 6.--7. " PARITY_TYPE ,Read 0x0: No parity identified" "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C++0x3 line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." bitfld.long 0x0 0. " EOT_EN ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" bitfld.long 0x0 1. " ABORT_EN ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty andUART_MDR1[5] = 1, UART IrDA starts a new transfer with data of the previous frame when the abort frame is sent. Therefore, TX FIFO must be reset before sending an abort frame." "0,1" textline " " bitfld.long 0x0 2. " SCTX_EN ,Store and controlled TX start. WhenUART_MDR1[5] = 1 and the LH writes 1 to this bit, the TX state-machine starts frame transmission. This bit is self-clearing." "0,1" bitfld.long 0x0 3. " SEND_SIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" textline " " bitfld.long 0x0 4. " DIS_TX_UNDERRUN ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by settingUART_ACREG[4] = 1, garbage data is sent over TX line." "0,1" bitfld.long 0x0 5. " DIS_IR_RX ,0x0: Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" textline " " bitfld.long 0x0 6. " SD_MOD ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 7. " PULSE_TYPE ,SIR pulse width select" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x40++0x3 line.long 0x0 "UART_SCR,Supplementary control register" bitfld.long 0x0 0. " DMA_MODE_CTL ,0x0: The DMA_MODE is set withUART_FCR[3]." "0,1" bitfld.long 0x0 1.--2. " DMA_MODE_2 ,Used to specify the DMA mode valid if theUART_SCR[0] bit = 1" "0,1,2,3" textline " " bitfld.long 0x0 3. " TX_EMPTY_CTL_IT ,0x0: Normal mode for THR interrupt (see UART mode interrupts table)" "0,1" bitfld.long 0x0 4. " RX_CTS_DSR_WAKE_UP_ENABLE ,0x0: Disables the wake-up interrupt and clears SSR[1]" "0,1" textline " " bitfld.long 0x0 5. " DSR_IT ,0x0: Disables DSR* interrupt" "0,1" bitfld.long 0x0 6. " TX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger TX level" "0,1" textline " " bitfld.long 0x0 7. " RX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger RX level" "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x44++0x3 line.long 0x0 "UART_SSR,Supplementary status register" bitfld.long 0x0 0. " TX_FIFO_FULL ,Read 0x0: TX FIFO is not full." "0,1" bitfld.long 0x0 1. " RX_CTS_DSR_WAKE_UP_STS ,Read 0x0: No falling edge event on RX, CTS*, and DSR*" "0,1" textline " " bitfld.long 0x0 2. " DMA_COUNTER_RST ,0x0: The DMA counter will not be reset if the corresponding FIFO is reset (throughUART_FCR[1] or UART_FCR[2])." "0,1" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x48++0x3 line.long 0x0 "UART_EBLR,BOF length register" hexmask.long.byte 0x0 0.--7. 1. " EBLR ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x50++0x3 line.long 0x0 "UART_MVR,Module version register" hexmask.long 0x0 0.--31. 1. " REV ,Revision number" group.byte 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up feature control" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5C++0x3 line.long 0x0 "UART_WER,Wake-up enable register" bitfld.long 0x0 0. " EVENT_0_CTS_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. " EVENT_1_DSR_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" textline " " bitfld.long 0x0 2. " EVENT_2_RI_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. " EVENT_3_DCD_CD_ACTIVITY ,0x0: Event is not allowed to wake up the system" "0,1" textline " " bitfld.long 0x0 4. " EVENT_4_RX_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. " EVENT_5_RHR_INTERRUPT ,0x0: Event is not allowed to wake up the system." "0,1" textline " " bitfld.long 0x0 6. " EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 7. " TX_WAKEUP_EN ,0x0: Event is not allowed to wake up the system." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x60++0x3 line.long 0x0 "UART_CFPS,Carrier frequency prescaler" hexmask.long.byte 0x0 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple). Examples for CFPS values:Target Freq (kHz) CFPS (decimal) Actual Freq (kHz) . 30 133 30.08 . 32.75 122 32.79 . 36 111 36.04 . 36.7 109 36.69 . 38* 105 38.1 . 40 100 40 . 56.8 70 57.14 . *configured at reset to this value . Note:CFPS = 0 is not supported. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x64++0x3 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.byte 0x0 0.--7. 1. " RXFIFO_LVL ,Shows the number of received bytes in the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x68++0x3 line.long 0x0 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.byte 0x0 0.--7. 1. " TXFIFO_LVL ,Shows the number of written bytes in the TX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6C++0x3 line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x0 0. " EN_RXFIFO_EMPTY ,Enables RX FIFO empty corresponding interrupt" "0,1" bitfld.long 0x0 1. " EN_TXFIFO_EMPTY ,Enables TX FIFO empty corresponding interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x70++0x3 line.long 0x0 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x0 0. " RXFIFO_EMPTY_STS ,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x0 1. " TXFIFO_EMPTY_STS ,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x74++0x3 line.long 0x0 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.byte 0x0 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if nondefault frequency is used.UART_MDR3[1] must be set to 1 after this value is set. Must be equal to or higher than 6." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x80++0x3 line.long 0x0 "UART_MDR3,Mode definition register 3" bitfld.long 0x0 0. " DISABLE_CIR_RX_DEMOD ,Used to enable CIR RX demodulation." "0,1" bitfld.long 0x0 1. " NONDEFAULT_FREQ ,Used to enable the NONDEFAULT fclk frequencies." "0,1" textline " " bitfld.long 0x0 2. " SET_DMA_TX_THRESHOLD ,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x84++0x3 line.long 0x0 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register." bitfld.long 0x0 0.--5. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "UART1" base ad:0x4806A000 width 23. group.byte 0x0++0x3 line.long 0x0 "UART_DLL,This register, with, stores the 14-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.byte 0x0 0.--7. 1. " CLOCK_LSB ,Stores the 8-bit LSB divisor value" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the RHR. If the FIFO is disabled, location 0 of the FIFO stores the single data character.Note:If an overflow occurs, the data in the RHR is not overwritten." hexmask.long.byte 0x0 0.--7. 1. " RHR ,Receive holding register" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0" group.byte 0x0++0x3 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The THR is a 64-byte FIFO. The local host (LH) writes data to the THR. The data is placed in the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location 0 of the FIFO stores the data." hexmask.long.byte 0x0 0.--7. 1. " THR ,Transmit holding register" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_DLH,This register, with, stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." bitfld.long 0x0 0.--5. " CLOCK_MSB ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " RESERVED ,Read returns 0. Write has no effect." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_IER,Interrupt enable register" bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " LINE_STS_IT ," "0,1" bitfld.long 0x0 3. " MODEM_STS_IT ," "0,1" textline " " bitfld.long 0x0 4. " SLEEP_MODE ," "0,1" bitfld.long 0x0 5. " XOFF_IT ," "0,1" textline " " bitfld.long 0x0 6. " RTS_IT ," "0,1" bitfld.long 0x0 7. " CTS_IT ," "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated based on the value set in the BOF Length register (). In IR-CIR mode, contrary to the IR-IRDA mode, the TX_STATUS_IT has only one meaning corresponding to the case [0] = 0." bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " RX_STOP_IT ," "0,1" bitfld.long 0x0 3. " RX_OVERRUN_IT ," "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Not used in CIR mode" "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ," "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ,Not used in CIR mode" "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The TX_STATUS_IT interrupt reflects two possible conditions. The [0] should be read to determine the status in the event of this interrupt." bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " LAST_RX_BYTE_IT ," "0,1" bitfld.long 0x0 3. " RX_OVERRUN_IT ," "0,1" textline " " bitfld.long 0x0 4. " STS_FIFO_TRIG_IT ," "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ," "0,1" textline " " bitfld.long 0x0 6. " LINE_STS_IT ," "0,1" bitfld.long 0x0 7. " EOF_IT ," "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_EFR,Enhanced feature register" bitfld.long 0x0 0.--3. " SW_FLOW_CONTROL ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENHANCED_EN ,Enhanced functions write enable bit" "0,1" textline " " bitfld.long 0x0 5. " SPECIAL_CHAR_DETECT ," "0,1" bitfld.long 0x0 6. " AUTO_RTS_EN ,Auto-RTS enable bit" "0,1" textline " " bitfld.long 0x0 7. " AUTO_CTS_EN ,Auto-CTS enable bit" "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register" bitfld.long 0x0 0. " FIFO_EN ," "0,1" bitfld.long 0x0 1. " RX_FIFO_CLEAR ," "0,1" textline " " bitfld.long 0x0 2. " TX_FIFO_CLEAR ," "0,1" bitfld.long 0x0 3. " DMA_MODE ,This register is considered ifUART_SCR[0] = 0." "0,1" textline " " bitfld.long 0x0 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If UART_SCR[6] = 0 and UART_TLR[3:0] != 0000, TX_FIFO_TRIG is not considered. If UART_SCR[6] = 1, TX_FIFO_TRIG is 2 LSBs of the trigger level (1-63 on 6 bits) with the granularity 1" "0,1,2,3" bitfld.long 0x0 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If UART_SCR[7] = 0 and UART_TLR[7:4] != 0000, RX_FIFO_TRIG is not considered. If UART_SCR[7] = 1, RX_FIFO_TRIG is 2 LSBs of the trigger level (1-63 on 6 bits) with the granularity 1." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_IIR,Interrupt identification register." bitfld.long 0x0 0. " IT_PENDING ,Read 0x0: An interrupt is pending." "0,1" bitfld.long 0x0 1.--5. " IT_TYPE ,Read 0x0: Modem interrupt. Priority = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 6.--7. " FCR_MIRROR ,Mirror the contents ofUART_FCR[0] on both bits." "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." bitfld.long 0x0 0. " RHR_IT ,Read 0x0: RHR interrupt inactive" "0,1" bitfld.long 0x0 1. " THR_IT ,Read 0x0: THR interrupt inactive" "0,1" textline " " bitfld.long 0x0 2. " RX_STOP_IT ,Read 0x0: Receive stop interrupt inactive" "0,1" bitfld.long 0x0 3. " RX_OE_IT ,Read 0x0: RX overrun interrupt inactive" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Not used in CIR mode" "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ,Read 0x0: TX status interrupt inactive" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ,Not used in CIR mode" "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " RX_FIFO_LAST_BYTE_IT ," "0,1" bitfld.long 0x0 3. " RX_OE_IT ," "0,1" textline " " bitfld.long 0x0 4. " STS_FIFO_IT ," "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ," "0,1" textline " " bitfld.long 0x0 6. " LINE_STS_IT ," "0,1" bitfld.long 0x0 7. " EOF_IT ," "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0xC++0x3 line.long 0x0 "UART_LCR,Line control register" bitfld.long 0x0 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "0,1,2,3" bitfld.long 0x0 2. " NB_STOP ,Specifies the number of stop-bits" "0,1" textline " " bitfld.long 0x0 3. " PARITY_EN ,0x0: No parity" "0,1" bitfld.long 0x0 4. " PARITY_TYPE1 ," "0,1" textline " " bitfld.long 0x0 5. " PARITY_TYPE2 ,Selects the forced parity format (ifUART_LCR[3] = 1). If UART_LCR[5] = 1 and UART_LCR[4] = 0, the parity bit is forced to 1 in the transmitted and received data. If UART_LCR[5] = 1 and UART_LCR[4] = 1, the parity bit is forced to 0 in the transmitted and received data." "0,1" bitfld.long 0x0 6. " BREAK_EN ,Break control bit" "0,1" textline " " bitfld.long 0x0 7. " DIV_EN ," "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x10++0x3 line.long 0x0 "UART_MCR,Modem control register" bitfld.long 0x0 0. " DTR ,0x0: Force DTR* output to inactive (high)." "0,1" bitfld.long 0x0 1. " RTS ,In loopback, controls theUART_MSR[4] bit. If auto-RTS is enabled, the RTS* output is controlled by hardware flow control." "0,1" textline " " bitfld.long 0x0 2. " RI_STS_CH ,0x0: In loopback, forces RI* input high" "0,1" bitfld.long 0x0 3. " CD_STS_CH ,0x0: In loopback, forces DCD* input high and IRQ outputs to inactive state" "0,1" textline " " bitfld.long 0x0 4. " LOOPBACK_EN ,0x0: Normal operating mode" "0,1" bitfld.long 0x0 5. " XON_EN ,0x0: Disable XON any function." "0,1" textline " " bitfld.long 0x0 6. " TCR_TLR ,0x0: No action" "0,1" bitfld.long 0x0 7. " RESERVED ,Read returns 0. Write has no effect." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address" hexmask.long.byte 0x0 0.--7. 1. " XON_WORD1 ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x14++0x3 line.long 0x0 "UART_LSR,Line status register" bitfld.long 0x0 0. " RX_FIFO_E ,Read 0x0: No data in the RX FIFO" "0,1" bitfld.long 0x0 1. " RX_OE ,Read 0x0: No overrun error" "0,1" textline " " bitfld.long 0x0 2. " RX_PE ,Read 0x0: No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 3. " RX_FE ,Read 0x0: No framing error in data RX FIFO" "0,1" textline " " bitfld.long 0x0 4. " RX_BI ,Read 0x0: No break condition" "0,1" bitfld.long 0x0 5. " TX_FIFO_E ,Read 0x0: Transmit hold register (TX FIFO) is not empty." "0,1" textline " " bitfld.long 0x0 6. " TX_SR_E ,Read 0x0: Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 7. " RX_FIFO_STS ,Read 0x0: Normal operation" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" bitfld.long 0x0 0. " RX_FIFO_E ,Read 0x0: At least one data character in the RX FIFO" "0,1" bitfld.long 0x0 1.--4. " RESERVED ,Not used in CIR mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5. " RX_STOP ,The RX_STOP is generated based on the value set in the BOF Length register (UART_EBLR). It is cleared on a single read of the UART_LSR register." "0,1" bitfld.long 0x0 6. " RESERVED ,Not used in CIR mode" "0,1" textline " " bitfld.long 0x0 7. " THR_EMPTY ,Read 0x0: Transmit holding register (TX FIFO) is not empty." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." bitfld.long 0x0 0. " RX_FIFO_E ,Read 0x0: No data in the RX FIFO" "0,1" bitfld.long 0x0 1. " STS_FIFO_E ,Read 0x0: Status FIFO not empty" "0,1" textline " " bitfld.long 0x0 2. " CRC ,Read 0x0: No CRC error in frame" "0,1" bitfld.long 0x0 3. " ABORT ,Read 0x0: No abort pattern error in frame" "0,1" textline " " bitfld.long 0x0 4. " FRAME_TOO_LONG ,Read 0x0: No frame-too-long error in frame" "0,1" bitfld.long 0x0 5. " RX_LAST_BYTE ,Read 0x0: The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" textline " " bitfld.long 0x0 6. " STS_FIFO_FULL ,Read 0x0: Status FIFO not full" "0,1" bitfld.long 0x0 7. " THR_EMPTY ,Read 0x0: Transmit holding register (TX FIFO) is not empty." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.byte 0x0 0.--7. 1. " XON_WORD2 ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only." bitfld.long 0x0 0. " CTS_STS ," "0,1" bitfld.long 0x0 1. " DSR_STS ," "0,1" textline " " bitfld.long 0x0 2. " RI_STS ,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high. Cleared on a read." "0,1" bitfld.long 0x0 3. " DCD_STS ,Indicates that DCD* input (orUART_MCR[3] in loopback) changed. Cleared on a read." "0,1" textline " " bitfld.long 0x0 4. " NCTS_STS ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent toUART_MCR[1]." "0,1" bitfld.long 0x0 5. " NDSR_STS ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent toUART_MCR[0]." "0,1" textline " " bitfld.long 0x0 6. " NRI_STS ,This bit is the complement of the RI* input. In loopback mode, it is equivalent toUART_MCR[2]." "0,1" bitfld.long 0x0 7. " NCD_STS ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent toUART_MCR[3]." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register" bitfld.long 0x0 0.--3. " RX_FIFO_TRIG_HALT ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_FIFO_TRIG_START ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x18++0x3 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.byte 0x0 0.--7. 1. " XOFF_WORD1 ,Stores the 8-bit XOFF1 character used in UART modes" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x1C++0x3 line.long 0x0 "UART_SPR,Scratchpad register" hexmask.long.byte 0x0 0.--7. 1. " SPR_WORD ,Scratchpad register" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register" bitfld.long 0x0 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x1C++0x3 line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.byte 0x0 0.--7. 1. " XOFF_WORD2 ,Stores the 8-bit XOFF2 character used in UART modes." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x20++0x3 line.long 0x0 "UART_MDR1,Mode definition register 1" bitfld.long 0x0 0.--2. " MODE_SELECT ,0x0: UART 16x mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " IR_SLEEP ,0x0: IrDA/CIR sleep mode disabled" "0,1" textline " " bitfld.long 0x0 4. " SET_TXIR ,Used to configure the infrared transceiver" "0,1" bitfld.long 0x0 5. " SCT ,Store and control the transmission." "0,1" textline " " bitfld.long 0x0 6. " SIP_MODE ,MIR/FIR modes only" "0,1" bitfld.long 0x0 7. " FRAME_END_MODE ,IrDA mode only" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x24++0x3 line.long 0x0 "UART_MDR2,Mode definition register 2" bitfld.long 0x0 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt. When theUART_IIR[5] interrupt occurs, the meaning of the interrupt is:" "0,1" bitfld.long 0x0 1.--2. " STS_FIFO_TRIG ,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" textline " " bitfld.long 0x0 3. " UART_PULSE ,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x0 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" textline " " bitfld.long 0x0 6. " IRRXINVERT ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x0 7. " SET_TXIR_ALT ,Provide alternate function forUART_MDR1[4] (SET_TXIR)." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register" bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " CRC_ERROR ,Read 0x1: CRC error in frame at top of RX FIFO" "0,1" textline " " bitfld.long 0x0 2. " ABORT_DETECT ,Read 0x1: Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 3. " FRAME_TOO_LONG_ERROR ,Read 0x1: Frame-length too long error in frame at top of RX FIFO" "0,1" textline " " bitfld.long 0x0 4. " OE_ERROR ,Read 0x1: Overrun error in RX FIFO when frame at top of RX FIFO was received Note: Top of RX FIFO = Next frame to be read from RX FIFO" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low" hexmask.long.byte 0x0 0.--7. 1. " TXFLL ,LSB register used to specify the frame length" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist and reads always as 0x00." hexmask.long.byte 0x0 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "UART_TXFLH,Transmit frame length register high" bitfld.long 0x0 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write has no effect." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x30++0x3 line.long 0x0 "UART_RXFLL,Received frame length register low" hexmask.long.byte 0x0 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low" hexmask.long.byte 0x0 0.--7. 1. " SFREGL ,LSB part of the frame length" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high" bitfld.long 0x0 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Write has no effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high" bitfld.long 0x0 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register" bitfld.long 0x0 0.--5. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " XBOF_TYPE ,SIR xBOF select" "0,1" textline " " bitfld.long 0x0 7. " STS_FIFO_RESET ,Status FIFO reset. This bit is self-clearing." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register" bitfld.long 0x0 0.--4. " SPEED ,Used to report the speed identified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " BIT_BY_CHAR ,Read 0x0: 7-bit character identified" "0,1" textline " " bitfld.long 0x0 6.--7. " PARITY_TYPE ,Read 0x0: No parity identified" "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C++0x3 line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." bitfld.long 0x0 0. " EOT_EN ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" bitfld.long 0x0 1. " ABORT_EN ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty andUART_MDR1[5] = 1, UART IrDA starts a new transfer with data of the previous frame when the abort frame is sent. Therefore, TX FIFO must be reset before sending an abort frame." "0,1" textline " " bitfld.long 0x0 2. " SCTX_EN ,Store and controlled TX start. WhenUART_MDR1[5] = 1 and the LH writes 1 to this bit, the TX state-machine starts frame transmission. This bit is self-clearing." "0,1" bitfld.long 0x0 3. " SEND_SIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" textline " " bitfld.long 0x0 4. " DIS_TX_UNDERRUN ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by settingUART_ACREG[4] = 1, garbage data is sent over TX line." "0,1" bitfld.long 0x0 5. " DIS_IR_RX ,0x0: Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" textline " " bitfld.long 0x0 6. " SD_MOD ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 7. " PULSE_TYPE ,SIR pulse width select" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x40++0x3 line.long 0x0 "UART_SCR,Supplementary control register" bitfld.long 0x0 0. " DMA_MODE_CTL ,0x0: The DMA_MODE is set withUART_FCR[3]." "0,1" bitfld.long 0x0 1.--2. " DMA_MODE_2 ,Used to specify the DMA mode valid if theUART_SCR[0] bit = 1" "0,1,2,3" textline " " bitfld.long 0x0 3. " TX_EMPTY_CTL_IT ,0x0: Normal mode for THR interrupt (see UART mode interrupts table)" "0,1" bitfld.long 0x0 4. " RX_CTS_DSR_WAKE_UP_ENABLE ,0x0: Disables the wake-up interrupt and clears SSR[1]" "0,1" textline " " bitfld.long 0x0 5. " DSR_IT ,0x0: Disables DSR* interrupt" "0,1" bitfld.long 0x0 6. " TX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger TX level" "0,1" textline " " bitfld.long 0x0 7. " RX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger RX level" "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x44++0x3 line.long 0x0 "UART_SSR,Supplementary status register" bitfld.long 0x0 0. " TX_FIFO_FULL ,Read 0x0: TX FIFO is not full." "0,1" bitfld.long 0x0 1. " RX_CTS_DSR_WAKE_UP_STS ,Read 0x0: No falling edge event on RX, CTS*, and DSR*" "0,1" textline " " bitfld.long 0x0 2. " DMA_COUNTER_RST ,0x0: The DMA counter will not be reset if the corresponding FIFO is reset (throughUART_FCR[1] or UART_FCR[2])." "0,1" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x48++0x3 line.long 0x0 "UART_EBLR,BOF length register" hexmask.long.byte 0x0 0.--7. 1. " EBLR ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x50++0x3 line.long 0x0 "UART_MVR,Module version register" hexmask.long 0x0 0.--31. 1. " REV ,Revision number" group.byte 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up feature control" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5C++0x3 line.long 0x0 "UART_WER,Wake-up enable register" bitfld.long 0x0 0. " EVENT_0_CTS_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. " EVENT_1_DSR_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" textline " " bitfld.long 0x0 2. " EVENT_2_RI_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. " EVENT_3_DCD_CD_ACTIVITY ,0x0: Event is not allowed to wake up the system" "0,1" textline " " bitfld.long 0x0 4. " EVENT_4_RX_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. " EVENT_5_RHR_INTERRUPT ,0x0: Event is not allowed to wake up the system." "0,1" textline " " bitfld.long 0x0 6. " EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 7. " TX_WAKEUP_EN ,0x0: Event is not allowed to wake up the system." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x60++0x3 line.long 0x0 "UART_CFPS,Carrier frequency prescaler" hexmask.long.byte 0x0 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple). Examples for CFPS values:Target Freq (kHz) CFPS (decimal) Actual Freq (kHz) . 30 133 30.08 . 32.75 122 32.79 . 36 111 36.04 . 36.7 109 36.69 . 38* 105 38.1 . 40 100 40 . 56.8 70 57.14 . *configured at reset to this value . Note:CFPS = 0 is not supported. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x64++0x3 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.byte 0x0 0.--7. 1. " RXFIFO_LVL ,Shows the number of received bytes in the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x68++0x3 line.long 0x0 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.byte 0x0 0.--7. 1. " TXFIFO_LVL ,Shows the number of written bytes in the TX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6C++0x3 line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x0 0. " EN_RXFIFO_EMPTY ,Enables RX FIFO empty corresponding interrupt" "0,1" bitfld.long 0x0 1. " EN_TXFIFO_EMPTY ,Enables TX FIFO empty corresponding interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x70++0x3 line.long 0x0 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x0 0. " RXFIFO_EMPTY_STS ,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x0 1. " TXFIFO_EMPTY_STS ,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x74++0x3 line.long 0x0 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.byte 0x0 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if nondefault frequency is used.UART_MDR3[1] must be set to 1 after this value is set. Must be equal to or higher than 6." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x80++0x3 line.long 0x0 "UART_MDR3,Mode definition register 3" bitfld.long 0x0 0. " DISABLE_CIR_RX_DEMOD ,Used to enable CIR RX demodulation." "0,1" bitfld.long 0x0 1. " NONDEFAULT_FREQ ,Used to enable the NONDEFAULT fclk frequencies." "0,1" textline " " bitfld.long 0x0 2. " SET_DMA_TX_THRESHOLD ,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x84++0x3 line.long 0x0 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register." bitfld.long 0x0 0.--5. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "UART2" base ad:0x4806C000 width 23. group.byte 0x0++0x3 line.long 0x0 "UART_DLL,This register, with, stores the 14-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." hexmask.long.byte 0x0 0.--7. 1. " CLOCK_LSB ,Stores the 8-bit LSB divisor value" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x0++0x3 line.long 0x0 "UART_RHR,The receiver section consists of the receiver holding register (RHR) and the receiver shift register. The RHR is a 64-byte FIFO. The receiver shift register receives serial data from RX input. The data is converted to parallel data and moved to the RHR. If the FIFO is disabled, location 0 of the FIFO stores the single data character.Note:If an overflow occurs, the data in the RHR is not overwritten." hexmask.long.byte 0x0 0.--7. 1. " RHR ,Receive holding register" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0" group.byte 0x0++0x3 line.long 0x0 "UART_THR,The transmitter section consists of the transmit holding register (THR) and the transmit shift register. The THR is a 64-byte FIFO. The local host (LH) writes data to the THR. The data is placed in the transmit shift register where it is shifted out serially on the TX output. If the FIFO is disabled, location 0 of the FIFO stores the data." hexmask.long.byte 0x0 0.--7. 1. " THR ,Transmit holding register" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_DLH,This register, with, stores the 14-bit divisor for generating the baud clock in the baud rate generator. DLH stores the most-significant part of the divisor. DLL stores the least-significant part of the divisor." bitfld.long 0x0 0.--5. " CLOCK_MSB ,Stores the 6-bit MSB divisor value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " RESERVED ,Read returns 0. Write has no effect." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_IER,Interrupt enable register" bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " LINE_STS_IT ," "0,1" bitfld.long 0x0 3. " MODEM_STS_IT ," "0,1" textline " " bitfld.long 0x0 4. " SLEEP_MODE ," "0,1" bitfld.long 0x0 5. " XOFF_IT ," "0,1" textline " " bitfld.long 0x0 6. " RTS_IT ," "0,1" bitfld.long 0x0 7. " CTS_IT ," "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_IER_CIR,There are 6 types of interrupt in these modes, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Notes: The RX_STOP_IT interrupt is generated based on the value set in the BOF Length register (). In IR-CIR mode, contrary to the IR-IRDA mode, the TX_STATUS_IT has only one meaning corresponding to the case [0] = 0." bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " RX_STOP_IT ," "0,1" bitfld.long 0x0 3. " RX_OVERRUN_IT ," "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Not used in CIR mode" "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ," "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ,Not used in CIR mode" "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x4++0x3 line.long 0x0 "UART_IER_IRDA,There are 8 types of interrupt in these modes, received EOF, LSR interrupt, TX status, status FIFO interrupt, RX overrun, last byte in RX FIFO, THR interrupt and RHR interrupt and they can be enabled/disabled individually. Note: The TX_STATUS_IT interrupt reflects two possible conditions. The [0] should be read to determine the status in the event of this interrupt." bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " LAST_RX_BYTE_IT ," "0,1" bitfld.long 0x0 3. " RX_OVERRUN_IT ," "0,1" textline " " bitfld.long 0x0 4. " STS_FIFO_TRIG_IT ," "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ," "0,1" textline " " bitfld.long 0x0 6. " LINE_STS_IT ," "0,1" bitfld.long 0x0 7. " EOF_IT ," "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_EFR,Enhanced feature register" bitfld.long 0x0 0.--3. " SW_FLOW_CONTROL ,Combinations of software flow control can be selected by programming bit 3 - bit 0. See." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENHANCED_EN ,Enhanced functions write enable bit" "0,1" textline " " bitfld.long 0x0 5. " SPECIAL_CHAR_DETECT ," "0,1" bitfld.long 0x0 6. " AUTO_RTS_EN ,Auto-RTS enable bit" "0,1" textline " " bitfld.long 0x0 7. " AUTO_CTS_EN ,Auto-CTS enable bit" "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_FCR,FIFO control register" bitfld.long 0x0 0. " FIFO_EN ," "0,1" bitfld.long 0x0 1. " RX_FIFO_CLEAR ," "0,1" textline " " bitfld.long 0x0 2. " TX_FIFO_CLEAR ," "0,1" bitfld.long 0x0 3. " DMA_MODE ,This register is considered ifUART_SCR[0] = 0." "0,1" textline " " bitfld.long 0x0 4.--5. " TX_FIFO_TRIG ,Sets the trigger level for the TX FIFO: If UART_SCR[6] = 0 and UART_TLR[3:0] = 0000: 00: 8 spaces 01: 16 spaces 10: 32 spaces 11: 56 spaces If UART_SCR[6] = 0 and UART_TLR[3:0] != 0000, TX_FIFO_TRIG is not considered. If UART_SCR[6] = 1, TX_FIFO_TRIG is 2 LSBs of the trigger level (1-63 on 6 bits) with the granularity 1" "0,1,2,3" bitfld.long 0x0 6.--7. " RX_FIFO_TRIG ,Sets the trigger level for the RX FIFO: If UART_SCR[7] = 0 and UART_TLR[7:4] = 0000: 00: 8 characters 01: 16 characters 10: 56 characters 11: 60 characters If UART_SCR[7] = 0 and UART_TLR[7:4] != 0000, RX_FIFO_TRIG is not considered. If UART_SCR[7] = 1, RX_FIFO_TRIG is 2 LSBs of the trigger level (1-63 on 6 bits) with the granularity 1." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_IIR,Interrupt identification register." bitfld.long 0x0 0. " IT_PENDING ,Read 0x0: An interrupt is pending." "0,1" bitfld.long 0x0 1.--5. " IT_TYPE ,Read 0x0: Modem interrupt. Priority = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 6.--7. " FCR_MIRROR ,Mirror the contents ofUART_FCR[0] on both bits." "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_IIR_CIR,The interrupt line is activated whenever one of the 6 interrupts is active." bitfld.long 0x0 0. " RHR_IT ,Read 0x0: RHR interrupt inactive" "0,1" bitfld.long 0x0 1. " THR_IT ,Read 0x0: THR interrupt inactive" "0,1" textline " " bitfld.long 0x0 2. " RX_STOP_IT ,Read 0x0: Receive stop interrupt inactive" "0,1" bitfld.long 0x0 3. " RX_OE_IT ,Read 0x0: RX overrun interrupt inactive" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Not used in CIR mode" "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ,Read 0x0: TX status interrupt inactive" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ,Not used in CIR mode" "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x8++0x3 line.long 0x0 "UART_IIR_IRDA,The interrupt line is activated whenever one of the 8 interrupts is active." bitfld.long 0x0 0. " RHR_IT ," "0,1" bitfld.long 0x0 1. " THR_IT ," "0,1" textline " " bitfld.long 0x0 2. " RX_FIFO_LAST_BYTE_IT ," "0,1" bitfld.long 0x0 3. " RX_OE_IT ," "0,1" textline " " bitfld.long 0x0 4. " STS_FIFO_IT ," "0,1" bitfld.long 0x0 5. " TX_STATUS_IT ," "0,1" textline " " bitfld.long 0x0 6. " LINE_STS_IT ," "0,1" bitfld.long 0x0 7. " EOF_IT ," "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0xC++0x3 line.long 0x0 "UART_LCR,Line control register" bitfld.long 0x0 0.--1. " CHAR_LENGTH ,Specifies the word length to be transmitted or received" "0,1,2,3" bitfld.long 0x0 2. " NB_STOP ,Specifies the number of stop-bits" "0,1" textline " " bitfld.long 0x0 3. " PARITY_EN ,0x0: No parity" "0,1" bitfld.long 0x0 4. " PARITY_TYPE1 ," "0,1" textline " " bitfld.long 0x0 5. " PARITY_TYPE2 ,Selects the forced parity format (ifUART_LCR[3] = 1). If UART_LCR[5] = 1 and UART_LCR[4] = 0, the parity bit is forced to 1 in the transmitted and received data. If UART_LCR[5] = 1 and UART_LCR[4] = 1, the parity bit is forced to 0 in the transmitted and received data." "0,1" bitfld.long 0x0 6. " BREAK_EN ,Break control bit" "0,1" textline " " bitfld.long 0x0 7. " DIV_EN ," "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x10++0x3 line.long 0x0 "UART_MCR,Modem control register" bitfld.long 0x0 0. " DTR ,0x0: Force DTR* output to inactive (high)." "0,1" bitfld.long 0x0 1. " RTS ,In loopback, controls theUART_MSR[4] bit. If auto-RTS is enabled, the RTS* output is controlled by hardware flow control." "0,1" textline " " bitfld.long 0x0 2. " RI_STS_CH ,0x0: In loopback, forces RI* input high" "0,1" bitfld.long 0x0 3. " CD_STS_CH ,0x0: In loopback, forces DCD* input high and IRQ outputs to inactive state" "0,1" textline " " bitfld.long 0x0 4. " LOOPBACK_EN ,0x0: Normal operating mode" "0,1" bitfld.long 0x0 5. " XON_EN ,0x0: Disable XON any function." "0,1" textline " " bitfld.long 0x0 6. " TCR_TLR ,0x0: No action" "0,1" bitfld.long 0x0 7. " RESERVED ,Read returns 0. Write has no effect." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x10++0x3 line.long 0x0 "UART_XON1_ADDR1,UART mode: XON1 character, IrDA mode: ADDR1 address" hexmask.long.byte 0x0 0.--7. 1. " XON_WORD1 ,Stores the 8-bit XON1 character in UART modes and ADDR1 address 1 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x14++0x3 line.long 0x0 "UART_LSR,Line status register" bitfld.long 0x0 0. " RX_FIFO_E ,Read 0x0: No data in the RX FIFO" "0,1" bitfld.long 0x0 1. " RX_OE ,Read 0x0: No overrun error" "0,1" textline " " bitfld.long 0x0 2. " RX_PE ,Read 0x0: No parity error in data from RX FIFO" "0,1" bitfld.long 0x0 3. " RX_FE ,Read 0x0: No framing error in data RX FIFO" "0,1" textline " " bitfld.long 0x0 4. " RX_BI ,Read 0x0: No break condition" "0,1" bitfld.long 0x0 5. " TX_FIFO_E ,Read 0x0: Transmit hold register (TX FIFO) is not empty." "0,1" textline " " bitfld.long 0x0 6. " TX_SR_E ,Read 0x0: Transmitter hold (TX FIFO) and shift registers are not empty." "0,1" bitfld.long 0x0 7. " RX_FIFO_STS ,Read 0x0: Normal operation" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x14++0x3 line.long 0x0 "UART_LSR_CIR,Line status register in CIR mode" bitfld.long 0x0 0. " RX_FIFO_E ,Read 0x0: At least one data character in the RX FIFO" "0,1" bitfld.long 0x0 1.--4. " RESERVED ,Not used in CIR mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 5. " RX_STOP ,The RX_STOP is generated based on the value set in the BOF Length register (UART_EBLR). It is cleared on a single read of the UART_LSR register." "0,1" bitfld.long 0x0 6. " RESERVED ,Not used in CIR mode" "0,1" textline " " bitfld.long 0x0 7. " THR_EMPTY ,Read 0x0: Transmit holding register (TX FIFO) is not empty." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x14++0x3 line.long 0x0 "UART_LSR_IRDA,When the LSR is read, LSR[4:2] reflect the error bits [FL, CRC, ABORT] of the frame at the top of the STATUS FIFO (next frame status to be read)." bitfld.long 0x0 0. " RX_FIFO_E ,Read 0x0: No data in the RX FIFO" "0,1" bitfld.long 0x0 1. " STS_FIFO_E ,Read 0x0: Status FIFO not empty" "0,1" textline " " bitfld.long 0x0 2. " CRC ,Read 0x0: No CRC error in frame" "0,1" bitfld.long 0x0 3. " ABORT ,Read 0x0: No abort pattern error in frame" "0,1" textline " " bitfld.long 0x0 4. " FRAME_TOO_LONG ,Read 0x0: No frame-too-long error in frame" "0,1" bitfld.long 0x0 5. " RX_LAST_BYTE ,Read 0x0: The RX FIFO (RHR) does not contain the last byte of the frame to be read." "0,1" textline " " bitfld.long 0x0 6. " STS_FIFO_FULL ,Read 0x0: Status FIFO not full" "0,1" bitfld.long 0x0 7. " THR_EMPTY ,Read 0x0: Transmit holding register (TX FIFO) is not empty." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x14++0x3 line.long 0x0 "UART_XON2_ADDR2,Stores the 8-bit XON2 character in UART moldes and ADDR2 address 2 for IrDA modes" hexmask.long.byte 0x0 0.--7. 1. " XON_WORD2 ,Stores the 8-bit XON2 character in UART modes and ADDR2 address 2 for IrDA modes" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x18++0x3 line.long 0x0 "UART_MSR,Modem status register. UART mode only." bitfld.long 0x0 0. " CTS_STS ," "0,1" bitfld.long 0x0 1. " DSR_STS ," "0,1" textline " " bitfld.long 0x0 2. " RI_STS ,Indicates that RI* input (orUART_MCR[2] in loopback) changed state from low to high. Cleared on a read." "0,1" bitfld.long 0x0 3. " DCD_STS ,Indicates that DCD* input (orUART_MCR[3] in loopback) changed. Cleared on a read." "0,1" textline " " bitfld.long 0x0 4. " NCTS_STS ,This bit is the complement of the CTS* input. In loopback mode, it is equivalent toUART_MCR[1]." "0,1" bitfld.long 0x0 5. " NDSR_STS ,This bit is the complement of the DSR* input. In loopback mode, it is equivalent toUART_MCR[0]." "0,1" textline " " bitfld.long 0x0 6. " NRI_STS ,This bit is the complement of the RI* input. In loopback mode, it is equivalent toUART_MCR[2]." "0,1" bitfld.long 0x0 7. " NCD_STS ,This bit is the complement of the DCD* input. In loopback mode, it is equivalent toUART_MCR[3]." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x18++0x3 line.long 0x0 "UART_TCR,Transmission control register" bitfld.long 0x0 0.--3. " RX_FIFO_TRIG_HALT ,RX FIFO trigger level to HALT transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_FIFO_TRIG_START ,RX FIFO trigger level to RESTORE transmission (0 - 60)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x18++0x3 line.long 0x0 "UART_XOFF1,UART mode XOFF1 character" hexmask.long.byte 0x0 0.--7. 1. " XOFF_WORD1 ,Stores the 8-bit XOFF1 character used in UART modes" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x1C++0x3 line.long 0x0 "UART_SPR,Scratchpad register" hexmask.long.byte 0x0 0.--7. 1. " SPR_WORD ,Scratchpad register" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x1C++0x3 line.long 0x0 "UART_TLR,Trigger level register" bitfld.long 0x0 0.--3. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_FIFO_TRIG_DMA ,Receive FIFO trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x1C++0x3 line.long 0x0 "UART_XOFF2,UART mode XOFF2 character" hexmask.long.byte 0x0 0.--7. 1. " XOFF_WORD2 ,Stores the 8-bit XOFF2 character used in UART modes." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x20++0x3 line.long 0x0 "UART_MDR1,Mode definition register 1" bitfld.long 0x0 0.--2. " MODE_SELECT ,0x0: UART 16x mode" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " IR_SLEEP ,0x0: IrDA/CIR sleep mode disabled" "0,1" textline " " bitfld.long 0x0 4. " SET_TXIR ,Used to configure the infrared transceiver" "0,1" bitfld.long 0x0 5. " SCT ,Store and control the transmission." "0,1" textline " " bitfld.long 0x0 6. " SIP_MODE ,MIR/FIR modes only" "0,1" bitfld.long 0x0 7. " FRAME_END_MODE ,IrDA mode only" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x24++0x3 line.long 0x0 "UART_MDR2,Mode definition register 2" bitfld.long 0x0 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt. When theUART_IIR[5] interrupt occurs, the meaning of the interrupt is:" "0,1" bitfld.long 0x0 1.--2. " STS_FIFO_TRIG ,IR-IrDA mode only. Frame status FIFO threshold select:" "0,1,2,3" textline " " bitfld.long 0x0 3. " UART_PULSE ,UART mode only. Allows pulse shaping in UART mode." "0,1" bitfld.long 0x0 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition. Defines high level of the pulse width associated with a digit:" "0,1,2,3" textline " " bitfld.long 0x0 6. " IRRXINVERT ,IR mode only (IrDA and CIR). Invert RX pin in the module before the voting or sampling system logic of the infrared block. This does not affect the RX path in UART modem modes." "0,1" bitfld.long 0x0 7. " SET_TXIR_ALT ,Provide alternate function forUART_MDR1[4] (SET_TXIR)." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x28++0x3 line.long 0x0 "UART_SFLSR,Status FIFO line status register" bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " CRC_ERROR ,Read 0x1: CRC error in frame at top of RX FIFO" "0,1" textline " " bitfld.long 0x0 2. " ABORT_DETECT ,Read 0x1: Abort pattern detected in frame at top of RX FIFO" "0,1" bitfld.long 0x0 3. " FRAME_TOO_LONG_ERROR ,Read 0x1: Frame-length too long error in frame at top of RX FIFO" "0,1" textline " " bitfld.long 0x0 4. " OE_ERROR ,Read 0x1: Overrun error in RX FIFO when frame at top of RX FIFO was received Note: Top of RX FIFO = Next frame to be read from RX FIFO" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x28++0x3 line.long 0x0 "UART_TXFLL,Transmit frame length register low" hexmask.long.byte 0x0 0.--7. 1. " TXFLL ,LSB register used to specify the frame length" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x2C++0x3 line.long 0x0 "UART_RESUME,IR-IrDA and IR-CIR modes only. This register is used to clear internal flags, which halt transmission/reception when an underrun/overrun error occurs. Reading this register resumes the halted operation. This register does not physically exist and reads always as 0x00." hexmask.long.byte 0x0 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x2C++0x3 line.long 0x0 "UART_TXFLH,Transmit frame length register high" bitfld.long 0x0 0.--4. " TXFLH ,MSB register used to specify the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ,Write has no effect." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x30++0x3 line.long 0x0 "UART_RXFLL,Received frame length register low" hexmask.long.byte 0x0 0.--7. 1. " RXFLL ,LSB register used to specify the frame length in reception" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x30++0x3 line.long 0x0 "UART_SFREGL,Status FIFO register low" hexmask.long.byte 0x0 0.--7. 1. " SFREGL ,LSB part of the frame length" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x34++0x3 line.long 0x0 "UART_RXFLH,Received frame length register high" bitfld.long 0x0 0.--3. " RXFLH ,MSB register used to specify the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Write has no effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Write has no effect." group.byte 0x34++0x3 line.long 0x0 "UART_SFREGH,Status FIFO register high" bitfld.long 0x0 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x38++0x3 line.long 0x0 "UART_BLR,BOF control register" bitfld.long 0x0 0.--5. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " XBOF_TYPE ,SIR xBOF select" "0,1" textline " " bitfld.long 0x0 7. " STS_FIFO_RESET ,Status FIFO reset. This bit is self-clearing." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x38++0x3 line.long 0x0 "UART_UASR,UART autobauding status register" bitfld.long 0x0 0.--4. " SPEED ,Used to report the speed identified" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " BIT_BY_CHAR ,Read 0x0: 7-bit character identified" "0,1" textline " " bitfld.long 0x0 6.--7. " PARITY_TYPE ,Read 0x0: No parity identified" "0,1,2,3" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x3C++0x3 line.long 0x0 "UART_ACREG,Auxiliary control register. IR-IrDA and IR-CIR modes only." bitfld.long 0x0 0. " EOT_EN ,EOT (end of transmission) bit. The LH writes 1 to this bit just before it writes the last byte to the TX FIFO in set-EOT bit frame closing method. This bit is cleared automatically when the LH writes to the THR (TX FIFO)." "0,1" bitfld.long 0x0 1. " ABORT_EN ,Frame abort. The LH can intentionally abort transmission of a frame by writing 1 to this bit. Neither the end flag nor the CRC bits are appended to the frame. If TX FIFO is not empty andUART_MDR1[5] = 1, UART IrDA starts a new transfer with data of the previous frame when the abort frame is sent. Therefore, TX FIFO must be reset before sending an abort frame." "0,1" textline " " bitfld.long 0x0 2. " SCTX_EN ,Store and controlled TX start. WhenUART_MDR1[5] = 1 and the LH writes 1 to this bit, the TX state-machine starts frame transmission. This bit is self-clearing." "0,1" bitfld.long 0x0 3. " SEND_SIP ,MIR/FIR modes only. Send serial infrared interaction pulse (SIP). If this bit is set during an MIR/FIR transmission, the SIP is sent at the end of it. This bit is cleared automatically at the end of the SIP transmission." "0,1" textline " " bitfld.long 0x0 4. " DIS_TX_UNDERRUN ,It is recommended to disable TX FIFO underrun capability by masking corresponding underrun interrupt. When disabling underrun by settingUART_ACREG[4] = 1, garbage data is sent over TX line." "0,1" bitfld.long 0x0 5. " DIS_IR_RX ,0x0: Normal operation (RX input automatically disabled during transmit but enabled outside of transmit operation)" "0,1" textline " " bitfld.long 0x0 6. " SD_MOD ,Primary output used to configure transceivers. Connected to the SD/MODE input pin of IrDA transceivers." "0,1" bitfld.long 0x0 7. " PULSE_TYPE ,SIR pulse width select" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x40++0x3 line.long 0x0 "UART_SCR,Supplementary control register" bitfld.long 0x0 0. " DMA_MODE_CTL ,0x0: The DMA_MODE is set withUART_FCR[3]." "0,1" bitfld.long 0x0 1.--2. " DMA_MODE_2 ,Used to specify the DMA mode valid if theUART_SCR[0] bit = 1" "0,1,2,3" textline " " bitfld.long 0x0 3. " TX_EMPTY_CTL_IT ,0x0: Normal mode for THR interrupt (see UART mode interrupts table)" "0,1" bitfld.long 0x0 4. " RX_CTS_DSR_WAKE_UP_ENABLE ,0x0: Disables the wake-up interrupt and clears SSR[1]" "0,1" textline " " bitfld.long 0x0 5. " DSR_IT ,0x0: Disables DSR* interrupt" "0,1" bitfld.long 0x0 6. " TX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger TX level" "0,1" textline " " bitfld.long 0x0 7. " RX_TRIG_GRANU1 ,0x0: Disables the granularity of 1 for trigger RX level" "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x44++0x3 line.long 0x0 "UART_SSR,Supplementary status register" bitfld.long 0x0 0. " TX_FIFO_FULL ,Read 0x0: TX FIFO is not full." "0,1" bitfld.long 0x0 1. " RX_CTS_DSR_WAKE_UP_STS ,Read 0x0: No falling edge event on RX, CTS*, and DSR*" "0,1" textline " " bitfld.long 0x0 2. " DMA_COUNTER_RST ,0x0: The DMA counter will not be reset if the corresponding FIFO is reset (throughUART_FCR[1] or UART_FCR[2])." "0,1" bitfld.long 0x0 3.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x48++0x3 line.long 0x0 "UART_EBLR,BOF length register" hexmask.long.byte 0x0 0.--7. 1. " EBLR ,IR-IrDA mode: This register allows definition of up to 176 xBOFs, the maximum required by IrDA specification." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x50++0x3 line.long 0x0 "UART_MVR,Module version register" hexmask.long 0x0 0.--31. 1. " REV ,Revision number" group.byte 0x54++0x3 line.long 0x0 "UART_SYSC,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. This bit is automatically reset by the hardware. Read returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up feature control" "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Power management req/ack control ref: OCP Design Guidelines Version 1.1" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Read returns 0." "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x58++0x3 line.long 0x0 "UART_SYSS,System status register" bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x5C++0x3 line.long 0x0 "UART_WER,Wake-up enable register" bitfld.long 0x0 0. " EVENT_0_CTS_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 1. " EVENT_1_DSR_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" textline " " bitfld.long 0x0 2. " EVENT_2_RI_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 3. " EVENT_3_DCD_CD_ACTIVITY ,0x0: Event is not allowed to wake up the system" "0,1" textline " " bitfld.long 0x0 4. " EVENT_4_RX_ACTIVITY ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 5. " EVENT_5_RHR_INTERRUPT ,0x0: Event is not allowed to wake up the system." "0,1" textline " " bitfld.long 0x0 6. " EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT ,0x0: Event is not allowed to wake up the system." "0,1" bitfld.long 0x0 7. " TX_WAKEUP_EN ,0x0: Event is not allowed to wake up the system." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x60++0x3 line.long 0x0 "UART_CFPS,Carrier frequency prescaler" hexmask.long.byte 0x0 0.--7. 1. " CFPS ,System clock frequency prescaler at (12x multiple). Examples for CFPS values:Target Freq (kHz) CFPS (decimal) Actual Freq (kHz) . 30 133 30.08 . 32.75 122 32.79 . 36 111 36.04 . 36.7 109 36.69 . 38* 105 38.1 . 40 100 40 . 56.8 70 57.14 . *configured at reset to this value . Note:CFPS = 0 is not supported. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x64++0x3 line.long 0x0 "UART_RXFIFO_LVL,Level of the RX FIFO" hexmask.long.byte 0x0 0.--7. 1. " RXFIFO_LVL ,Shows the number of received bytes in the RX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x68++0x3 line.long 0x0 "UART_TXFIFO_LVL,Level of the TX FIFO" hexmask.long.byte 0x0 0.--7. 1. " TXFIFO_LVL ,Shows the number of written bytes in the TX FIFO" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0." group.byte 0x6C++0x3 line.long 0x0 "UART_IER2,Enables RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x0 0. " EN_RXFIFO_EMPTY ,Enables RX FIFO empty corresponding interrupt" "0,1" bitfld.long 0x0 1. " EN_TXFIFO_EMPTY ,Enables TX FIFO empty corresponding interrupt" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x70++0x3 line.long 0x0 "UART_ISR2,Status of RX/TX FIFOs empty corresponding interrupts" bitfld.long 0x0 0. " RXFIFO_EMPTY_STS ,Used to generate interrupt if the RX_FIFO is empty (software flow control)" "0,1" bitfld.long 0x0 1. " TXFIFO_EMPTY_STS ,Used to generate interrupt if the TX_FIFO is empty (software flow control)" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x74++0x3 line.long 0x0 "UART_FREQ_SEL,Sample per bit selector" hexmask.long.byte 0x0 0.--7. 1. " FREQ_SEL ,Sets the sample per bit if nondefault frequency is used.UART_MDR3[1] must be set to 1 after this value is set. Must be equal to or higher than 6." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x80++0x3 line.long 0x0 "UART_MDR3,Mode definition register 3" bitfld.long 0x0 0. " DISABLE_CIR_RX_DEMOD ,Used to enable CIR RX demodulation." "0,1" bitfld.long 0x0 1. " NONDEFAULT_FREQ ,Used to enable the NONDEFAULT fclk frequencies." "0,1" textline " " bitfld.long 0x0 2. " SET_DMA_TX_THRESHOLD ,Enable to set different TXDMA threshold inUART_TX_DMA_THRESHOLD register." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Read returns 0. Write has no effect." group.byte 0x84++0x3 line.long 0x0 "UART_TX_DMA_THRESHOLD,Use to manually set the TX DMA threshold level. [2] SET_TX_DMA_THRESHOLD must be 1 and must be value + tx_trigger_level = 64 (TX FIFO size). If not, 64-tx_trigger_level will be used without modifying the value of this register." bitfld.long 0x0 0.--5. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCSPI1" base ad:0x48098000 width 20. group.byte 0x0++0x3 line.long 0x0 "MCSPI_HL_REV,McSPI module revision identifier Used by software to track features, bugs, and compatibility" hexmask.long 0x0 0.--31. 1. " REVISION ,McSPI Module Revision" group.byte 0x4++0x3 line.long 0x0 "MCSPI_HL_HWINFO,Information about the module's hardware configuration." bitfld.long 0x0 0. " USEFIFO ,Use of a FIFO enable. This bit indicates if a FIFO is integrated within controller design with its management." "0,1" bitfld.long 0x0 1.--5. " FFNBYTE ,FIFO number of bytes parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 6. " RETMODE ,Retention Mode. This bit field indicates whether the retention mode is supported. 0x0: Retention mode disabled 0x1: Retention mode enabled" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Reserved These bits are initialized to 0, and writes to them are ignored." group.byte 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 0. " SOFTRESET ,Software reset. (Optional)" "0,1" bitfld.long 0x0 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal." "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the McSPI revision number." hexmask.long.byte 0x0 0.--7. 1. " REVISION ,McSPI core revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0, 0x21 for 2.1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reads return 0" group.byte 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the configuration interface and is not affected by software reset." bitfld.long 0x0 0. " AUTOIDLE ,Internal interface clock-gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. During reads it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up feature control" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Power management" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clocks activity during wake-up mode period" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads return 0" group.byte 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved for future module specific status information. Read returns 0." group.byte 0x118++0x3 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TX0_EMPTY ,Transmitter register empty or almost empty. Channel 0" "0,1" bitfld.long 0x0 1. " TX0_UNDERFLOW ,Transmitter register underflow. Channel 0" "0,1" textline " " bitfld.long 0x0 2. " RX0_FULL ,Receiver register full or almost full. Channel 0" "0,1" bitfld.long 0x0 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only). Channel 0" "0,1" textline " " bitfld.long 0x0 4. " TX1_EMPTY ,Transmitter register empty or almost empty. Channel 1" "0,1" bitfld.long 0x0 5. " TX1_UNDERFLOW ,Transmitter register underflow. Channel 1" "0,1" textline " " bitfld.long 0x0 6. " RX1_FULL ,Receiver register full or almost full. Channel 1" "0,1" bitfld.long 0x0 7. " RESERVED ,Reads returns 0" "0,1" textline " " bitfld.long 0x0 8. " TX2_EMPTY ,Transmitter register empty or almost empty. Channel 2" "0,1" bitfld.long 0x0 9. " TX2_UNDERFLOW ,Transmitter register underflow. Channel 2" "0,1" textline " " bitfld.long 0x0 10. " RX2_FULL ,Receiver register full or almost full. Channel 2" "0,1" bitfld.long 0x0 11. " RESERVED ,Reads returns 0." "0,1" textline " " bitfld.long 0x0 12. " TX3_EMPTY ,Transmitter register is empty or almost empty. Note: Enabling the channel automatically rises this event." "0,1" bitfld.long 0x0 13. " TX3_UNDERFLOW ,Transmitter register underflow. Only when Channel 3 is enabled. The transmitter register is empty (not updated by host or DMA with new data) before its time slot assignment. Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled." "0,1" textline " " bitfld.long 0x0 14. " RX3_FULL ,Receiver register is full or almost full. Only when Channel 3 is enabled" "0,1" bitfld.long 0x0 15. " RESERVED ,Reads returns 0" "0,1" textline " " bitfld.long 0x0 16. " WKS ,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the fieldMCSPI_CHxCONF[22:21] SPIENSLV" "0,1" bitfld.long 0x0 17. " EOW ,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[31:16] WCNT." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reads return 0" group.byte 0x11C++0x3 line.long 0x0 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis." bitfld.long 0x0 0. " TX0_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 0" "0,1" bitfld.long 0x0 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0" "0,1" textline " " bitfld.long 0x0 2. " RX0_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 0" "0,1" bitfld.long 0x0 3. " RX0_OVERFLOW_ENABLE ,Receiver register Overflow Interrupt Enable. Channel 0" "0,1" textline " " bitfld.long 0x0 4. " TX1_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 1" "0,1" bitfld.long 0x0 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1" "0,1" textline " " bitfld.long 0x0 6. " RX1_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 1" "0,1" bitfld.long 0x0 7. " RESERVED ,Reads return 0." "0,1" textline " " bitfld.long 0x0 8. " TX2_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 2" "0,1" bitfld.long 0x0 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2" "0,1" textline " " bitfld.long 0x0 10. " RX2_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 2" "0,1" bitfld.long 0x0 11. " RESERVED ,Reads return 0." "0,1" textline " " bitfld.long 0x0 12. " TX3_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 3" "0,1" bitfld.long 0x0 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3" "0,1" textline " " bitfld.long 0x0 14. " RX3_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 3" "0,1" bitfld.long 0x0 15. " RESERVED ,Reads returns 0." "0,1" textline " " bitfld.long 0x0 16. " WKE ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in theMCSPI_CHxCONF[22:21] SPIENSLV bits" "0,1" bitfld.long 0x0 17. " EOW_ENABLE ,End of Word count Interrupt Enable." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reads return 0." group.byte 0x120++0x3 line.long 0x0 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis." bitfld.long 0x0 0. " WKEN ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in theMCSPI_CHxCONF[22:21] SPIENSLV bits" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x124++0x3 line.long 0x0 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode." bitfld.long 0x0 0. " SPIEN_0 ,SPIEN[0] line (signal data value) If [10] SPIENDIR = 0 (output mode direction), the SPIENT[0] line is driven high or low according to the value written into this bit. If [10] SPIENDIR = 1 (input mode direction), this bit returns the value on the SPIEN[0] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 1. " SPIEN_1 ,SPIEN[1] line (signal data value) If [10] SPIENDIR = 0 (output mode direction), the SPIENT[1] line is driven high or low according to the value written into this bit. If [10] SPIENDIR = 1 (input mode direction), this bit returns the value on the SPIEN[1] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " SPIEN_2 ,SPIEN[2] line (signal data value) If [10] SPIENDIR = 0 (output mode direction), the SPIENT[2] line is driven high or low according to the value written into this bit. If [10] SPIENDIR = 1 (input mode direction), this bit returns the value on the SPIEN[2] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 3. " SPIEN_3 ,SPIEN[3] line (signal data value) If [10] SPIENDIR = 0 (output mode direction), the SPIENT[3] line is driven high or low according to the value written into this bit. If [10] SPIENDIR = 1 (input mode direction), this bit returns the value on the SPIEN[3] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 4. " SPIDAT_0 ,SPIDAT[0] line (signal data value) If [8] SPIDATDIR0 = 0 (output mode direction), the SPIDAT[0] line is driven high or low according to the value written into this bit. If [8] SPIDATDIR0 = 1 (input mode direction), this bit returns the value on the SPIDAT[0] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 5. " SPIDAT_1 ,SPIDAT[1] line (signal data value) If [9] SPIDATDIR1 = 0 (output mode direction), the SPIDAT[1] line is driven high or low according to the value written into this bit. If [9] SPIDATDIR1 = 1 (input mode direction), this bit returns the value on the SPIDAT[1] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " SPICLK ,SPICLK line (signal data value) If [10] SPIENDIR = 1 (input mode direction), this bit returns the value on the CLKSPI line (high or low), and a write into this bit has no effect. If [10] SPIENDIR = 0 (output mode direction), the CLKSPI line is driven high or low according to the value written into this bit." "0,1" bitfld.long 0x0 7. " WAKD ,SWAKEUP output (signal data value of internal signal to system). The signal is driven high or low according to the value written into this bit." "0,1" textline " " bitfld.long 0x0 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]." "0,1" bitfld.long 0x0 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]." "0,1" textline " " bitfld.long 0x0 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line." "0,1" bitfld.long 0x0 11. " SSB ,Set status bit" "0,1" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x128++0x3 line.long 0x0 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial peripheral interface." bitfld.long 0x0 0. " SINGLE ,Single channel/Multi Channel (master mode only)" "0,1" bitfld.long 0x0 1. " PIN34 ,Pin mode selection: This bit is used in master or slave mode to configure the SPI pin mode (3-pin or 4-pin). If asserted the controller only uses SIMO, SOMI, and SPICLK clock pin for SPI transfers." "0,1" textline " " bitfld.long 0x0 2. " MS ,Master/slave" "0,1" bitfld.long 0x0 3. " SYSTEM_TEST ,Enables the system test mode" "0,1" textline " " bitfld.long 0x0 4.--6. " INITDLY ,Initial SPI delay for first transfer: this field is an option only available in SINGLE master mode. The controller waits for a delay to transmit the first SPI word after channel enabled and corresponding TX register filled. This delay is based on SPI output frequency clock. No clock output provided to the boundary and chip select is not active in 4-pin mode within this period." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " MOA ,Multiple word interface access: this bit can only be used when a channel is enabled using a FIFO. It allows the system to perform multiple SPI word access for a single 32-bit interface word access. This is possible for WL < 16." "0,1" textline " " bitfld.long 0x0 8. " FDAA ,FIFO DMA address 256-bit aligned This bit is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address. If this bit is set the enabled channel which uses the FIFO has its data managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TXx and MCSPI_RXx registers." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x12C++0x3 line.long 0x0 "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel x" bitfld.long 0x0 0. " PHA ,SPICLK phase (see, Transfer Format)" "0,1" bitfld.long 0x0 1. " POL ,SPICLK polarity (see, Transfer Format)" "0,1" textline " " bitfld.long 0x0 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (FCLK) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default, the clock divider ratio has a power of 2 granularity when [29] CLKG is cleared. Otherwise, this field is the 4-LSB bit of a 12-bit register concatenated with clock divider extensionMCSPI_CHxCTRL[15:8] EXTCLK register. The value description below defines the clock ratio when [29] CLKG is set to 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " EPOL ,SPIEN polarity" "0,1" textline " " bitfld.long 0x0 7.--11. " WL ,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 12.--13. " TRM ,Transmit/receive modes" "0,1,2,3" textline " " bitfld.long 0x0 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter register of the channel." "0,1" bitfld.long 0x0 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the channel." "0,1" textline " " bitfld.long 0x0 16. " DPE0 ,Transmission Enable for data line 0" "0,1" bitfld.long 0x0 17. " DPE1 ,Transmission enable for data line 1" "0,1" textline " " bitfld.long 0x0 18. " IS ,Input Select" "0,1" bitfld.long 0x0 19. " TURBO ,Turbo mode" "0,1" textline " " bitfld.long 0x0 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)." "0,1" bitfld.long 0x0 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases." "0,1,2,3" textline " " bitfld.long 0x0 23. " SBE ,Start-bit enable for SPI transfer" "0,1" bitfld.long 0x0 24. " SBPOL ,Start-bit polarity" "0,1" textline " " bitfld.long 0x0 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock." "0,1,2,3" bitfld.long 0x0 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set." "0,1" textline " " bitfld.long 0x0 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set." "0,1" bitfld.long 0x0 29. " CLKG ,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHxCTRL[15:8] EXTCLK must be configured to reach a maximum of 4096 clock divider ratio. Then the clock divider ratio is a concatenation of [5:2] CLKD and MCSPI_CHxCTRL[15:8] EXTCLK values" "0,1" textline " " bitfld.long 0x0 30.--31. " RESERVED ,Read returns 0." "0,1,2,3" group.byte 0x140++0x3 line.long 0x0 "MCSPI_CHxCONF_1,This register is dedicated to the configuration of the channel x" bitfld.long 0x0 0. " PHA ,SPICLK phase (see, Transfer Format)" "0,1" bitfld.long 0x0 1. " POL ,SPICLK polarity (see, Transfer Format)" "0,1" textline " " bitfld.long 0x0 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (FCLK) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default, the clock divider ratio has a power of 2 granularity when [29] CLKG is cleared. Otherwise, this field is the 4-LSB bit of a 12-bit register concatenated with clock divider extensionMCSPI_CHxCTRL[15:8] EXTCLK register. The value description below defines the clock ratio when [29] CLKG is set to 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " EPOL ,SPIEN polarity" "0,1" textline " " bitfld.long 0x0 7.--11. " WL ,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 12.--13. " TRM ,Transmit/receive modes" "0,1,2,3" textline " " bitfld.long 0x0 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter register of the channel." "0,1" bitfld.long 0x0 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the channel." "0,1" textline " " bitfld.long 0x0 16. " DPE0 ,Transmission Enable for data line 0" "0,1" bitfld.long 0x0 17. " DPE1 ,Transmission enable for data line 1" "0,1" textline " " bitfld.long 0x0 18. " IS ,Input Select" "0,1" bitfld.long 0x0 19. " TURBO ,Turbo mode" "0,1" textline " " bitfld.long 0x0 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)." "0,1" bitfld.long 0x0 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases." "0,1,2,3" textline " " bitfld.long 0x0 23. " SBE ,Start-bit enable for SPI transfer" "0,1" bitfld.long 0x0 24. " SBPOL ,Start-bit polarity" "0,1" textline " " bitfld.long 0x0 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock." "0,1,2,3" bitfld.long 0x0 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set." "0,1" textline " " bitfld.long 0x0 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set." "0,1" bitfld.long 0x0 29. " CLKG ,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHxCTRL[15:8] EXTCLK must be configured to reach a maximum of 4096 clock divider ratio. Then the clock divider ratio is a concatenation of [5:2] CLKD and MCSPI_CHxCTRL[15:8] EXTCLK values" "0,1" textline " " bitfld.long 0x0 30.--31. " RESERVED ,Read returns 0." "0,1,2,3" group.byte 0x154++0x3 line.long 0x0 "MCSPI_CHxCONF_2,This register is dedicated to the configuration of the channel x" bitfld.long 0x0 0. " PHA ,SPICLK phase (see, Transfer Format)" "0,1" bitfld.long 0x0 1. " POL ,SPICLK polarity (see, Transfer Format)" "0,1" textline " " bitfld.long 0x0 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (FCLK) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default, the clock divider ratio has a power of 2 granularity when [29] CLKG is cleared. Otherwise, this field is the 4-LSB bit of a 12-bit register concatenated with clock divider extensionMCSPI_CHxCTRL[15:8] EXTCLK register. The value description below defines the clock ratio when [29] CLKG is set to 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " EPOL ,SPIEN polarity" "0,1" textline " " bitfld.long 0x0 7.--11. " WL ,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 12.--13. " TRM ,Transmit/receive modes" "0,1,2,3" textline " " bitfld.long 0x0 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter register of the channel." "0,1" bitfld.long 0x0 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the channel." "0,1" textline " " bitfld.long 0x0 16. " DPE0 ,Transmission Enable for data line 0" "0,1" bitfld.long 0x0 17. " DPE1 ,Transmission enable for data line 1" "0,1" textline " " bitfld.long 0x0 18. " IS ,Input Select" "0,1" bitfld.long 0x0 19. " TURBO ,Turbo mode" "0,1" textline " " bitfld.long 0x0 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)." "0,1" bitfld.long 0x0 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases." "0,1,2,3" textline " " bitfld.long 0x0 23. " SBE ,Start-bit enable for SPI transfer" "0,1" bitfld.long 0x0 24. " SBPOL ,Start-bit polarity" "0,1" textline " " bitfld.long 0x0 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock." "0,1,2,3" bitfld.long 0x0 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set." "0,1" textline " " bitfld.long 0x0 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set." "0,1" bitfld.long 0x0 29. " CLKG ,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHxCTRL[15:8] EXTCLK must be configured to reach a maximum of 4096 clock divider ratio. Then the clock divider ratio is a concatenation of [5:2] CLKD and MCSPI_CHxCTRL[15:8] EXTCLK values" "0,1" textline " " bitfld.long 0x0 30.--31. " RESERVED ,Read returns 0." "0,1,2,3" group.byte 0x168++0x3 line.long 0x0 "MCSPI_CHxCONF_3,This register is dedicated to the configuration of the channel x" bitfld.long 0x0 0. " PHA ,SPICLK phase (see, Transfer Format)" "0,1" bitfld.long 0x0 1. " POL ,SPICLK polarity (see, Transfer Format)" "0,1" textline " " bitfld.long 0x0 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (FCLK) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default, the clock divider ratio has a power of 2 granularity when [29] CLKG is cleared. Otherwise, this field is the 4-LSB bit of a 12-bit register concatenated with clock divider extensionMCSPI_CHxCTRL[15:8] EXTCLK register. The value description below defines the clock ratio when [29] CLKG is set to 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " EPOL ,SPIEN polarity" "0,1" textline " " bitfld.long 0x0 7.--11. " WL ,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 12.--13. " TRM ,Transmit/receive modes" "0,1,2,3" textline " " bitfld.long 0x0 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter register of the channel." "0,1" bitfld.long 0x0 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the channel." "0,1" textline " " bitfld.long 0x0 16. " DPE0 ,Transmission Enable for data line 0" "0,1" bitfld.long 0x0 17. " DPE1 ,Transmission enable for data line 1" "0,1" textline " " bitfld.long 0x0 18. " IS ,Input Select" "0,1" bitfld.long 0x0 19. " TURBO ,Turbo mode" "0,1" textline " " bitfld.long 0x0 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)." "0,1" bitfld.long 0x0 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases." "0,1,2,3" textline " " bitfld.long 0x0 23. " SBE ,Start-bit enable for SPI transfer" "0,1" bitfld.long 0x0 24. " SBPOL ,Start-bit polarity" "0,1" textline " " bitfld.long 0x0 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock." "0,1,2,3" bitfld.long 0x0 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set." "0,1" textline " " bitfld.long 0x0 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set." "0,1" bitfld.long 0x0 29. " CLKG ,Clock divider granularity this bit defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHxCTRL[15:8] EXTCLK must be configured to reach a maximum of 4096 clock divider ratio. Then the clock divider ratio is a concatenation of [5:2] CLKD and MCSPI_CHxCTRL[15:8] EXTCLK values" "0,1" textline " " bitfld.long 0x0 30.--31. " RESERVED ,Read returns 0." "0,1,2,3" group.byte 0x130++0x3 line.long 0x0 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel x." bitfld.long 0x0 0. " RXS ,Channel x receiver register status" "0,1" bitfld.long 0x0 1. " TXS ,Channel x transmitter register status" "0,1" textline " " bitfld.long 0x0 2. " EOT ,Channel x end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details." "0,1" bitfld.long 0x0 3. " TXFFE ,Channel x FIFO transmit buffer empty status" "0,1" textline " " bitfld.long 0x0 4. " TXFFF ,Channel x FIFO transmit buffer full status" "0,1" bitfld.long 0x0 5. " RXFFE ,Channel x FIFO receive buffer empty status" "0,1" textline " " bitfld.long 0x0 6. " RXFFF ,Channel x FIFO receive buffer full status" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Read returns 0." group.byte 0x144++0x3 line.long 0x0 "MCSPI_CHxSTAT_1,This register provides status information about transmitter and receiver registers of channel x." bitfld.long 0x0 0. " RXS ,Channel x receiver register status" "0,1" bitfld.long 0x0 1. " TXS ,Channel x transmitter register status" "0,1" textline " " bitfld.long 0x0 2. " EOT ,Channel x end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details." "0,1" bitfld.long 0x0 3. " TXFFE ,Channel x FIFO transmit buffer empty status" "0,1" textline " " bitfld.long 0x0 4. " TXFFF ,Channel x FIFO transmit buffer full status" "0,1" bitfld.long 0x0 5. " RXFFE ,Channel x FIFO receive buffer empty status" "0,1" textline " " bitfld.long 0x0 6. " RXFFF ,Channel x FIFO receive buffer full status" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Read returns 0." group.byte 0x158++0x3 line.long 0x0 "MCSPI_CHxSTAT_2,This register provides status information about transmitter and receiver registers of channel x." bitfld.long 0x0 0. " RXS ,Channel x receiver register status" "0,1" bitfld.long 0x0 1. " TXS ,Channel x transmitter register status" "0,1" textline " " bitfld.long 0x0 2. " EOT ,Channel x end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details." "0,1" bitfld.long 0x0 3. " TXFFE ,Channel x FIFO transmit buffer empty status" "0,1" textline " " bitfld.long 0x0 4. " TXFFF ,Channel x FIFO transmit buffer full status" "0,1" bitfld.long 0x0 5. " RXFFE ,Channel x FIFO receive buffer empty status" "0,1" textline " " bitfld.long 0x0 6. " RXFFF ,Channel x FIFO receive buffer full status" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Read returns 0." group.byte 0x16C++0x3 line.long 0x0 "MCSPI_CHxSTAT_3,This register provides status information about transmitter and receiver registers of channel x." bitfld.long 0x0 0. " RXS ,Channel x receiver register status" "0,1" bitfld.long 0x0 1. " TXS ,Channel x transmitter register status" "0,1" textline " " bitfld.long 0x0 2. " EOT ,Channel x end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details." "0,1" bitfld.long 0x0 3. " TXFFE ,Channel x FIFO transmit buffer empty status" "0,1" textline " " bitfld.long 0x0 4. " TXFFF ,Channel x FIFO transmit buffer full status" "0,1" bitfld.long 0x0 5. " RXFFE ,Channel x FIFO receive buffer empty status" "0,1" textline " " bitfld.long 0x0 6. " RXFFF ,Channel x FIFO receive buffer full status" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Read returns 0." group.byte 0x134++0x3 line.long 0x0 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel x." bitfld.long 0x0 0. " EN ,Channel enable" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 8.--15. 1. " EXTCLK ,Clock ratio extension: this field is used to concatenate with MCSPI_CHxCONF[5:2] CLKD register for clock ratio only when granularity is one clock cycle (MCSPI_CHxCONF[29] CLKG set to 1). Then the maximum value reached is 4096 clock divider ratio." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x148++0x3 line.long 0x0 "MCSPI_CHxCTRL_1,This register is dedicated to enable channel x." bitfld.long 0x0 0. " EN ,Channel enable" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 8.--15. 1. " EXTCLK ,Clock ratio extension: this field is used to concatenate with MCSPI_CHxCONF[5:2] CLKD register for clock ratio only when granularity is one clock cycle (MCSPI_CHxCONF[29] CLKG set to 1). Then the maximum value reached is 4096 clock divider ratio." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x15C++0x3 line.long 0x0 "MCSPI_CHxCTRL_2,This register is dedicated to enable channel x." bitfld.long 0x0 0. " EN ,Channel enable" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 8.--15. 1. " EXTCLK ,Clock ratio extension: this field is used to concatenate with MCSPI_CHxCONF[5:2] CLKD register for clock ratio only when granularity is one clock cycle (MCSPI_CHxCONF[29] CLKG set to 1). Then the maximum value reached is 4096 clock divider ratio." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x170++0x3 line.long 0x0 "MCSPI_CHxCTRL_3,This register is dedicated to enable channel x." bitfld.long 0x0 0. " EN ,Channel enable" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 8.--15. 1. " EXTCLK ,Clock ratio extension: this field is used to concatenate with MCSPI_CHxCONF[5:2] CLKD register for clock ratio only when granularity is one clock cycle (MCSPI_CHxCONF[29] CLKG set to 1). Then the maximum value reached is 4096 clock divider ratio." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x138++0x3 line.long 0x0 "MCSPI_TXx_0,This register contains a single SPI word for channel x to transmit on the serial link, whatever SPI word length is." hexmask.long 0x0 0.--31. 1. " TDATA ,Channel x data to transmit" group.byte 0x14C++0x3 line.long 0x0 "MCSPI_TXx_1,This register contains a single SPI word for channel x to transmit on the serial link, whatever SPI word length is." hexmask.long 0x0 0.--31. 1. " TDATA ,Channel x data to transmit" group.byte 0x160++0x3 line.long 0x0 "MCSPI_TXx_2,This register contains a single SPI word for channel x to transmit on the serial link, whatever SPI word length is." hexmask.long 0x0 0.--31. 1. " TDATA ,Channel x data to transmit" group.byte 0x174++0x3 line.long 0x0 "MCSPI_TXx_3,This register contains a single SPI word for channel x to transmit on the serial link, whatever SPI word length is." hexmask.long 0x0 0.--31. 1. " TDATA ,Channel x data to transmit" group.byte 0x13C++0x3 line.long 0x0 "MCSPI_RXx_0,This register contains a single SPI word for channel x received through the serial link, whatever SPI word length is." hexmask.long 0x0 0.--31. 1. " RDATA ,Channel x received data" group.byte 0x150++0x3 line.long 0x0 "MCSPI_RXx_1,This register contains a single SPI word for channel x received through the serial link, whatever SPI word length is." hexmask.long 0x0 0.--31. 1. " RDATA ,Channel x received data" group.byte 0x164++0x3 line.long 0x0 "MCSPI_RXx_2,This register contains a single SPI word for channel x received through the serial link, whatever SPI word length is." hexmask.long 0x0 0.--31. 1. " RDATA ,Channel x received data" group.byte 0x178++0x3 line.long 0x0 "MCSPI_RXx_3,This register contains a single SPI word for channel x received through the serial link, whatever SPI word length is." hexmask.long 0x0 0.--31. 1. " RDATA ,Channel x received data" group.byte 0x17C++0x3 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.byte 0x0 0.--7. 1. " AEL ,Buffer almost empty. this field holds the programmable almost-empty level value used to determine almost empty buffer condition. If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes, then the buffer AEL must be set with n-1." hexmask.long.byte 0x0 8.--15. 1. " AFL ,Buffer almost full This field holds the programmable almost-full level value used to determine almost full buffer condition. If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes, then the buffer AFL must be set with n-1." textline " " hexmask.long.word 0x0 16.--31. 1. " WCNT ,SPI word counter. This field holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO buffer. When transfer had started, a read back in this field returns the current SPI word transfer index." group.byte 0x180++0x3 line.long 0x0 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. " DAFTDATA ,FIFO data to transmit with DMA 256 bit aligned address.This field is only used when[8] FDAA is set to 0x1 and only one of the enabled channels has the [27] FFEW bit set to 0x1. If these conditions are not met any access to this field returns a null value. enum=Disable ." group.byte 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. " DAFRDATA ,FIFO data received with DMA 256 bit aligned address.This field is only used when[8] FDAA is set to 0x1 and only one of the enabled channels has the [28] FFER bit set to 0x1. If these conditions are not met any access to this field returns a null value. enum=Disable ." width 0x0B tree.end tree "MCSPI2" base ad:0x4809A000 width 20. group.byte 0x0++0x3 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." bitfld.long 0x0 0. " USEFIFO ,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management." "0,1" bitfld.long 0x0 1.--5. " FFNBYTE ,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter, only MSB bits from 8 down to 4 are taken into account." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 6. " RETMODE ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET. 0x0: Retention mode disabled 0x1: Retention mode enabled" "0,1" hexmask.long 0x0 7.--31. 1. " RSVD ,Reserved These bits are initialized to 0, and writes to them are ignored." group.byte 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 0. " SOFTRESET ,Software reset. (Optional)" "0,1" bitfld.long 0x0 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal." "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RSVD ," group.byte 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface and is not affected by software reset." bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock-gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. During reads it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up feature control" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Power management" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clocks activity during wake-up mode period" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved for module specific status information. Read returns 0." group.byte 0x118++0x3 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TX0_EMPTY ,Transmitter register empty or almost empty. Channel 0" "0,1" bitfld.long 0x0 1. " TX0_UNDERFLOW ,Transmitter register underflow. Channel 0" "0,1" textline " " bitfld.long 0x0 2. " RX0_FULL ,Receiver register full or almost full. Channel 0" "0,1" bitfld.long 0x0 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only). Channel 0" "0,1" textline " " bitfld.long 0x0 4. " TX1_EMPTY ,Transmitter register empty or almost empty. Channel 1" "0,1" bitfld.long 0x0 5. " TX1_UNDERFLOW ,Transmitter register underflow. Channel 1" "0,1" textline " " bitfld.long 0x0 6. " RX1_FULL ,Receiver register full or almost full. Channel 1" "0,1" bitfld.long 0x0 7. " RESERVED ,Reads returns 0" "0,1" textline " " bitfld.long 0x0 8. " TX2_EMPTY ,Transmitter register empty or almost empty. Channel 2" "0,1" bitfld.long 0x0 9. " TX2_UNDERFLOW ,Transmitter register underflow. Channel 2" "0,1" textline " " bitfld.long 0x0 10. " RX2_FULL ,Receiver register full or almost full. Channel 2" "0,1" bitfld.long 0x0 11. " RESERVED ,Reads returns 0." "0,1" textline " " bitfld.long 0x0 12. " TX3_EMPTY ,Transmitter register is empty or almost empty. Note: Enabling the channel automatically rises this event." "0,1" bitfld.long 0x0 13. " TX3_UNDERFLOW ,Transmitter register underflow. Only when Channel 3 is enabled. The transmitter register is empty (not updated by host or DMA with new data) before its time slot assignment. Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled." "0,1" textline " " bitfld.long 0x0 14. " RX3_FULL ,Receiver register is full or almost full. Only when Channel 3 is enabled" "0,1" bitfld.long 0x0 15. " RESERVED ,Reads returns 0" "0,1" textline " " bitfld.long 0x0 16. " WKS ,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0x0 17. " EOW ,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x11C++0x3 line.long 0x0 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis." bitfld.long 0x0 0. " TX0_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 0" "0,1" bitfld.long 0x0 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0" "0,1" textline " " bitfld.long 0x0 2. " RX0_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 0" "0,1" bitfld.long 0x0 3. " RX0_OVERFLOW_ENABLE ,Receiver register Overflow Interrupt Enable. Channel 0" "0,1" textline " " bitfld.long 0x0 4. " TX1_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 1" "0,1" bitfld.long 0x0 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1" "0,1" textline " " bitfld.long 0x0 6. " RX1_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 1" "0,1" bitfld.long 0x0 7. " RESERVED ,Reads return 0." "0,1" textline " " bitfld.long 0x0 8. " TX2_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 2" "0,1" bitfld.long 0x0 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2" "0,1" textline " " bitfld.long 0x0 10. " RX2_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 2" "0,1" bitfld.long 0x0 11. " RESERVED ,Reads return 0." "0,1" textline " " bitfld.long 0x0 12. " TX3_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 3" "0,1" bitfld.long 0x0 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3" "0,1" textline " " bitfld.long 0x0 14. " RX3_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 3" "0,1" bitfld.long 0x0 15. " RESERVED ,Reads returns 0." "0,1" textline " " bitfld.long 0x0 16. " WKE ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "0,1" bitfld.long 0x0 17. " EOW_ENABLE ,End of Word count Interrupt Enable." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reads return 0." group.byte 0x120++0x3 line.long 0x0 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis." bitfld.long 0x0 0. " WKEN ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x124++0x3 line.long 0x0 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode." bitfld.long 0x0 0. " SPIEN_0 ,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[0] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 1. " SPIEN_1 ,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[1] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " SPIEN_2 ,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[2] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[2] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 3. " SPIEN_3 ,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[3] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[3] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 4. " SPIDAT_0 ,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction), the SPIDAT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR0] = 1 (input mode direction), this bit returns the value on the SPIDAT[0] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 5. " SPIDAT_1 ,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction), the SPIDAT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR1] = 1 (input mode direction), this bit returns the value on the SPIDAT[1] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " SPICLK ,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the CLKSPI line (high or low), and a write into this bit has no effect. If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the CLKSPI line is driven high or low according to the value written into this register." "0,1" bitfld.long 0x0 7. " WAKD ,SWAKEUP output (signal data value of internal signal to system). The signal is driven high or low according to the value written into this register bit." "0,1" textline " " bitfld.long 0x0 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]." "0,1" bitfld.long 0x0 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]." "0,1" textline " " bitfld.long 0x0 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line." "0,1" bitfld.long 0x0 11. " SSB ,Set status bit" "0,1" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x128++0x3 line.long 0x0 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." bitfld.long 0x0 0. " SINGLE ,Single channel/Multi Channel (master mode only)" "0,1" bitfld.long 0x0 1. " PIN34 ,Pin mode selection: This register is used to configure the SPI pin mode, in master or slave mode. If asserted the controller only use SIMO, SOMI, and SPICLK clock pin for SPI transfers." "0,1" textline " " bitfld.long 0x0 2. " MS ,Master/slave" "0,1" bitfld.long 0x0 3. " SYSTEM_TEST ,Enables the system test mode" "0,1" textline " " bitfld.long 0x0 4.--6. " INITDLY ,Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode. The controller waits for a delay to transmit the first SPI word after channel enabled and corresponding TX register filled. This delay is based on SPI output frequency clock. No clock output provided to the boundary and chip select is not active in 4-pin mode within this period." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " MOA ,Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO. It allows the system to perform multiple SPI word access for a single 32-bit OCP word access. This is possible for WL < 16." "0,1" textline " " bitfld.long 0x0 8. " FDAA ,FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address. If this bit is set the enabled channel which uses the FIFO has its data managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX(i) and MCSPI_RX(i) registers." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x12C++0x3 line.long 0x0 "MCSPI_CHxCONF_0,This register is dedicated to the configuration of the channel 0" bitfld.long 0x0 0. " PHA ,SPICLK phase (see, )" "0,1" bitfld.long 0x0 1. " POL ,SPICLK polarity (see, )" "0,1" textline " " bitfld.long 0x0 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when MCSPI_CHCONF[CLKG] is cleared. Otherwise this register is the 4-LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] register. The value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " EPOL ,SPIEN polarity" "0,1" textline " " bitfld.long 0x0 7.--11. " WL ,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 12.--13. " TRM ,Transmit/receive modes" "0,1,2,3" textline " " bitfld.long 0x0 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter register of the channel." "0,1" bitfld.long 0x0 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the channel." "0,1" textline " " bitfld.long 0x0 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0])" "0,1" bitfld.long 0x0 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1])" "0,1" textline " " bitfld.long 0x0 18. " IS ,Input Select" "0,1" bitfld.long 0x0 19. " TURBO ,Turbo mode" "0,1" textline " " bitfld.long 0x0 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)." "0,1" bitfld.long 0x0 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases." "0,1,2,3" textline " " bitfld.long 0x0 23. " SBE ,Start-bit enable for SPI transfer" "0,1" bitfld.long 0x0 24. " SBPOL ,Start-bit polarity" "0,1" textline " " bitfld.long 0x0 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock." "0,1,2,3" bitfld.long 0x0 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set." "0,1" textline " " bitfld.long 0x0 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set." "0,1" bitfld.long 0x0 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio. Then the clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values" "0,1" textline " " bitfld.long 0x0 30.--31. " RESERVED ,Read returns 0." "0,1,2,3" group.byte 0x140++0x3 line.long 0x0 "MCSPI_CHxCONF_1,This register is dedicated to the configuration of the channel 0" bitfld.long 0x0 0. " PHA ,SPICLK phase (see, )" "0,1" bitfld.long 0x0 1. " POL ,SPICLK polarity (see, )" "0,1" textline " " bitfld.long 0x0 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when MCSPI_CHCONF[CLKG] is cleared. Otherwise this register is the 4-LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] register. The value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " EPOL ,SPIEN polarity" "0,1" textline " " bitfld.long 0x0 7.--11. " WL ,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 12.--13. " TRM ,Transmit/receive modes" "0,1,2,3" textline " " bitfld.long 0x0 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter register of the channel." "0,1" bitfld.long 0x0 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the channel." "0,1" textline " " bitfld.long 0x0 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0])" "0,1" bitfld.long 0x0 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1])" "0,1" textline " " bitfld.long 0x0 18. " IS ,Input Select" "0,1" bitfld.long 0x0 19. " TURBO ,Turbo mode" "0,1" textline " " bitfld.long 0x0 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)." "0,1" bitfld.long 0x0 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases." "0,1,2,3" textline " " bitfld.long 0x0 23. " SBE ,Start-bit enable for SPI transfer" "0,1" bitfld.long 0x0 24. " SBPOL ,Start-bit polarity" "0,1" textline " " bitfld.long 0x0 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock." "0,1,2,3" bitfld.long 0x0 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set." "0,1" textline " " bitfld.long 0x0 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set." "0,1" bitfld.long 0x0 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio. Then the clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values" "0,1" textline " " bitfld.long 0x0 30.--31. " RESERVED ,Read returns 0." "0,1,2,3" group.byte 0x130++0x3 line.long 0x0 "MCSPI_CHxSTAT_0,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x0 0. " RXS ,Channel 'i' receiver register status" "0,1" bitfld.long 0x0 1. " TXS ,Channel 'i' transmitter register status" "0,1" textline " " bitfld.long 0x0 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details." "0,1" bitfld.long 0x0 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status" "0,1" textline " " bitfld.long 0x0 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status" "0,1" bitfld.long 0x0 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status" "0,1" textline " " bitfld.long 0x0 6. " RXFFF ,Channel 'i' FIFO receive buffer full status" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Read returns 0." group.byte 0x144++0x3 line.long 0x0 "MCSPI_CHxSTAT_1,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x0 0. " RXS ,Channel 'i' receiver register status" "0,1" bitfld.long 0x0 1. " TXS ,Channel 'i' transmitter register status" "0,1" textline " " bitfld.long 0x0 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details." "0,1" bitfld.long 0x0 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status" "0,1" textline " " bitfld.long 0x0 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status" "0,1" bitfld.long 0x0 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status" "0,1" textline " " bitfld.long 0x0 6. " RXFFF ,Channel 'i' FIFO receive buffer full status" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Read returns 0." group.byte 0x134++0x3 line.long 0x0 "MCSPI_CHxCTRL_0,This register is dedicated to enable channel 0." bitfld.long 0x0 0. " EN ,Channel enable" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x148++0x3 line.long 0x0 "MCSPI_CHxCTRL_1,This register is dedicated to enable channel 0." bitfld.long 0x0 0. " EN ,Channel enable" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x138++0x3 line.long 0x0 "MCSPI_TXx_0,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x0 0.--31. 1. " TDATA ,Channel 0 data to transmit" group.byte 0x14C++0x3 line.long 0x0 "MCSPI_TXx_1,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x0 0.--31. 1. " TDATA ,Channel 0 data to transmit" group.byte 0x13C++0x3 line.long 0x0 "MCSPI_RXx_0,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x0 0.--31. 1. " RDATA ,Channel 0 received data" group.byte 0x150++0x3 line.long 0x0 "MCSPI_RXx_1,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x0 0.--31. 1. " RDATA ,Channel 0 received data" group.byte 0x17C++0x3 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.byte 0x0 0.--7. 1. " AEL ,Buffer almost empty. This register holds the programmable almost empty level value used to determine almost empty buffer condition. If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes, then the bufferMCSPI_XFERLEVEL[AEL] must be set with  1." hexmask.long.byte 0x0 8.--15. 1. " AFL ,Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition. If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes, then the buffer MCSPI_XFERLEVEL[AFL] must be set with n1.The size of this register is defined by the generic parameter FFNBYTE." textline " " hexmask.long.word 0x0 16.--31. 1. " WCNT ,SPI word counter. This register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO buffer. When transfer had started, a read back in this register returns the current SPI word transfer index." group.byte 0x180++0x3 line.long 0x0 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. " DAFTDATA ,FIFO data to transmit with DMA 256 bit aligned address.This register is only used when[8] FDAA is set to 0x1 and only one of the enabled channels has the [27] FFEW bit set to 0x1. If these conditions are not met any access to this register returns a null value. enum=Disable ." group.byte 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. " DAFRDATA ,FIFO data received with DMA 256 bit aligned address.This register is only used when[8] FDAA is set to 0x1 and only one of the enabled channels has the [28] FFER bit set to 0x1. If these conditions are not met any access to this register returns a null value. enum=Disable ." width 0x0B tree.end tree "MCSPI3" base ad:0x480B8000 width 20. group.byte 0x0++0x3 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." bitfld.long 0x0 0. " USEFIFO ,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management." "0,1" bitfld.long 0x0 1.--5. " FFNBYTE ,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter, only MSB bits from 8 down to 4 are taken into account." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 6. " RETMODE ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET. 0x0: Retention mode disabled 0x1: Retention mode enabled" "0,1" hexmask.long 0x0 7.--31. 1. " RSVD ,Reserved These bits are initialized to 0, and writes to them are ignored." group.byte 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 0. " SOFTRESET ,Software reset. (Optional)" "0,1" bitfld.long 0x0 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal." "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RSVD ," group.byte 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface and is not affected by software reset." bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock-gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. During reads it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up feature control" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Power management" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clocks activity during wake-up mode period" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved for module specific status information. Read returns 0." group.byte 0x118++0x3 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TX0_EMPTY ,Transmitter register empty or almost empty. Channel 0" "0,1" bitfld.long 0x0 1. " TX0_UNDERFLOW ,Transmitter register underflow. Channel 0" "0,1" textline " " bitfld.long 0x0 2. " RX0_FULL ,Receiver register full or almost full. Channel 0" "0,1" bitfld.long 0x0 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only). Channel 0" "0,1" textline " " bitfld.long 0x0 4. " TX1_EMPTY ,Transmitter register empty or almost empty. Channel 1" "0,1" bitfld.long 0x0 5. " TX1_UNDERFLOW ,Transmitter register underflow. Channel 1" "0,1" textline " " bitfld.long 0x0 6. " RX1_FULL ,Receiver register full or almost full. Channel 1" "0,1" bitfld.long 0x0 7. " RESERVED ,Reads returns 0" "0,1" textline " " bitfld.long 0x0 8. " TX2_EMPTY ,Transmitter register empty or almost empty. Channel 2" "0,1" bitfld.long 0x0 9. " TX2_UNDERFLOW ,Transmitter register underflow. Channel 2" "0,1" textline " " bitfld.long 0x0 10. " RX2_FULL ,Receiver register full or almost full. Channel 2" "0,1" bitfld.long 0x0 11. " RESERVED ,Reads returns 0." "0,1" textline " " bitfld.long 0x0 12. " TX3_EMPTY ,Transmitter register is empty or almost empty. Note: Enabling the channel automatically rises this event." "0,1" bitfld.long 0x0 13. " TX3_UNDERFLOW ,Transmitter register underflow. Only when Channel 3 is enabled. The transmitter register is empty (not updated by host or DMA with new data) before its time slot assignment. Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled." "0,1" textline " " bitfld.long 0x0 14. " RX3_FULL ,Receiver register is full or almost full. Only when Channel 3 is enabled" "0,1" bitfld.long 0x0 15. " RESERVED ,Reads returns 0" "0,1" textline " " bitfld.long 0x0 16. " WKS ,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0x0 17. " EOW ,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x11C++0x3 line.long 0x0 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis." bitfld.long 0x0 0. " TX0_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 0" "0,1" bitfld.long 0x0 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0" "0,1" textline " " bitfld.long 0x0 2. " RX0_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 0" "0,1" bitfld.long 0x0 3. " RX0_OVERFLOW_ENABLE ,Receiver register Overflow Interrupt Enable. Channel 0" "0,1" textline " " bitfld.long 0x0 4. " TX1_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 1" "0,1" bitfld.long 0x0 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1" "0,1" textline " " bitfld.long 0x0 6. " RX1_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 1" "0,1" bitfld.long 0x0 7. " RESERVED ,Reads return 0." "0,1" textline " " bitfld.long 0x0 8. " TX2_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 2" "0,1" bitfld.long 0x0 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2" "0,1" textline " " bitfld.long 0x0 10. " RX2_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 2" "0,1" bitfld.long 0x0 11. " RESERVED ,Reads return 0." "0,1" textline " " bitfld.long 0x0 12. " TX3_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 3" "0,1" bitfld.long 0x0 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3" "0,1" textline " " bitfld.long 0x0 14. " RX3_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 3" "0,1" bitfld.long 0x0 15. " RESERVED ,Reads returns 0." "0,1" textline " " bitfld.long 0x0 16. " WKE ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "0,1" bitfld.long 0x0 17. " EOW_ENABLE ,End of Word count Interrupt Enable." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reads return 0." group.byte 0x120++0x3 line.long 0x0 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis." bitfld.long 0x0 0. " WKEN ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x124++0x3 line.long 0x0 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode." bitfld.long 0x0 0. " SPIEN_0 ,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[0] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 1. " SPIEN_1 ,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[1] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " SPIEN_2 ,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[2] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[2] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 3. " SPIEN_3 ,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[3] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[3] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 4. " SPIDAT_0 ,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction), the SPIDAT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR0] = 1 (input mode direction), this bit returns the value on the SPIDAT[0] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 5. " SPIDAT_1 ,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction), the SPIDAT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR1] = 1 (input mode direction), this bit returns the value on the SPIDAT[1] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " SPICLK ,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the CLKSPI line (high or low), and a write into this bit has no effect. If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the CLKSPI line is driven high or low according to the value written into this register." "0,1" bitfld.long 0x0 7. " WAKD ,SWAKEUP output (signal data value of internal signal to system). The signal is driven high or low according to the value written into this register bit." "0,1" textline " " bitfld.long 0x0 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]." "0,1" bitfld.long 0x0 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]." "0,1" textline " " bitfld.long 0x0 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line." "0,1" bitfld.long 0x0 11. " SSB ,Set status bit" "0,1" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x128++0x3 line.long 0x0 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." bitfld.long 0x0 0. " SINGLE ,Single channel/Multi Channel (master mode only)" "0,1" bitfld.long 0x0 1. " PIN34 ,Pin mode selection: This register is used to configure the SPI pin mode, in master or slave mode. If asserted the controller only use SIMO, SOMI, and SPICLK clock pin for SPI transfers." "0,1" textline " " bitfld.long 0x0 2. " MS ,Master/slave" "0,1" bitfld.long 0x0 3. " SYSTEM_TEST ,Enables the system test mode" "0,1" textline " " bitfld.long 0x0 4.--6. " INITDLY ,Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode. The controller waits for a delay to transmit the first SPI word after channel enabled and corresponding TX register filled. This delay is based on SPI output frequency clock. No clock output provided to the boundary and chip select is not active in 4-pin mode within this period." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " MOA ,Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO. It allows the system to perform multiple SPI word access for a single 32-bit OCP word access. This is possible for WL < 16." "0,1" textline " " bitfld.long 0x0 8. " FDAA ,FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address. If this bit is set the enabled channel which uses the FIFO has its data managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX(i) and MCSPI_RX(i) registers." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x12C++0x3 line.long 0x0 "MCSPI_CHxCONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x0 0. " PHA ,SPICLK phase (see, )" "0,1" bitfld.long 0x0 1. " POL ,SPICLK polarity (see, )" "0,1" textline " " bitfld.long 0x0 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when MCSPI_CHCONF[CLKG] is cleared. Otherwise this register is the 4-LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] register. The value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " EPOL ,SPIEN polarity" "0,1" textline " " bitfld.long 0x0 7.--11. " WL ,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 12.--13. " TRM ,Transmit/receive modes" "0,1,2,3" textline " " bitfld.long 0x0 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter register of the channel." "0,1" bitfld.long 0x0 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the channel." "0,1" textline " " bitfld.long 0x0 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0])" "0,1" bitfld.long 0x0 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1])" "0,1" textline " " bitfld.long 0x0 18. " IS ,Input Select" "0,1" bitfld.long 0x0 19. " TURBO ,Turbo mode" "0,1" textline " " bitfld.long 0x0 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)." "0,1" bitfld.long 0x0 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases." "0,1,2,3" textline " " bitfld.long 0x0 23. " SBE ,Start-bit enable for SPI transfer" "0,1" bitfld.long 0x0 24. " SBPOL ,Start-bit polarity" "0,1" textline " " bitfld.long 0x0 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock." "0,1,2,3" bitfld.long 0x0 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set." "0,1" textline " " bitfld.long 0x0 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set." "0,1" bitfld.long 0x0 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio. Then the clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values" "0,1" textline " " bitfld.long 0x0 30.--31. " RESERVED ,Read returns 0." "0,1,2,3" group.byte 0x130++0x3 line.long 0x0 "MCSPI_CHxSTAT,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x0 0. " RXS ,Channel 'i' receiver register status" "0,1" bitfld.long 0x0 1. " TXS ,Channel 'i' transmitter register status" "0,1" textline " " bitfld.long 0x0 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details." "0,1" bitfld.long 0x0 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status" "0,1" textline " " bitfld.long 0x0 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status" "0,1" bitfld.long 0x0 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status" "0,1" textline " " bitfld.long 0x0 6. " RXFFF ,Channel 'i' FIFO receive buffer full status" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Read returns 0." group.byte 0x134++0x3 line.long 0x0 "MCSPI_CHxCTRL,This register is dedicated to enable channel 0." bitfld.long 0x0 0. " EN ,Channel enable" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x138++0x3 line.long 0x0 "MCSPI_TXx,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x0 0.--31. 1. " TDATA ,Channel 0 data to transmit" group.byte 0x13C++0x3 line.long 0x0 "MCSPI_RXx,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x0 0.--31. 1. " RDATA ,Channel 0 received data" group.byte 0x17C++0x3 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.byte 0x0 0.--7. 1. " AEL ,Buffer almost empty. This register holds the programmable almost empty level value used to determine almost empty buffer condition. If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes, then the bufferMCSPI_XFERLEVEL[AEL] must be set with  1." hexmask.long.byte 0x0 8.--15. 1. " AFL ,Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition. If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes, then the buffer MCSPI_XFERLEVEL[AFL] must be set with n1.The size of this register is defined by the generic parameter FFNBYTE." textline " " hexmask.long.word 0x0 16.--31. 1. " WCNT ,SPI word counter. This register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO buffer. When transfer had started, a read back in this register returns the current SPI word transfer index." group.byte 0x180++0x3 line.long 0x0 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. " DAFTDATA ,FIFO data to transmit with DMA 256 bit aligned address.This register is only used when[8] FDAA is set to 0x1 and only one of the enabled channels has the [27] FFEW bit set to 0x1. If these conditions are not met any access to this register returns a null value. enum=Disable ." group.byte 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. " DAFRDATA ,FIFO data received with DMA 256 bit aligned address.This register is only used when[8] FDAA is set to 0x1 and only one of the enabled channels has the [28] FFER bit set to 0x1. If these conditions are not met any access to this register returns a null value. enum=Disable ." width 0x0B tree.end tree "MCSPI4" base ad:0x480BA000 width 20. group.byte 0x0++0x3 line.long 0x0 "MCSPI_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "MCSPI_HL_HWINFO,Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." bitfld.long 0x0 0. " USEFIFO ,Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management." "0,1" bitfld.long 0x0 1.--5. " FFNBYTE ,FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter, only MSB bits from 8 down to 4 are taken into account." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 6. " RETMODE ,Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET. 0x0: Retention mode disabled 0x1: Retention mode enabled" "0,1" hexmask.long 0x0 7.--31. 1. " RSVD ,Reserved These bits are initialized to 0, and writes to them are ignored." group.byte 0x10++0x3 line.long 0x0 "MCSPI_HL_SYSCONFIG,Clock management configuration" bitfld.long 0x0 0. " SOFTRESET ,Software reset. (Optional)" "0,1" bitfld.long 0x0 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal." "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RSVD ," group.byte 0x100++0x3 line.long 0x0 "MCSPI_REVISION,This register contains the revision number." hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x110++0x3 line.long 0x0 "MCSPI_SYSCONFIG,This register allows controlling various parameters of the OCP interface and is not affected by software reset." bitfld.long 0x0 0. " AUTOIDLE ,Internal OCP clock-gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. During reads it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up feature control" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Power management" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,Reads returns 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clocks activity during wake-up mode period" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x114++0x3 line.long 0x0 "MCSPI_SYSSTATUS,This register provides status information about the module excluding the interrupt status information." bitfld.long 0x0 0. " RESETDONE ,Internal reset monitoring" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved for module specific status information. Read returns 0." group.byte 0x118++0x3 line.long 0x0 "MCSPI_IRQSTATUS,The interrupt status regroups all the status of the module internal events that can generate an interrupt." bitfld.long 0x0 0. " TX0_EMPTY ,Transmitter register empty or almost empty. Channel 0" "0,1" bitfld.long 0x0 1. " TX0_UNDERFLOW ,Transmitter register underflow. Channel 0" "0,1" textline " " bitfld.long 0x0 2. " RX0_FULL ,Receiver register full or almost full. Channel 0" "0,1" bitfld.long 0x0 3. " RX0_OVERFLOW ,Receiver register overflow (slave mode only). Channel 0" "0,1" textline " " bitfld.long 0x0 4. " TX1_EMPTY ,Transmitter register empty or almost empty. Channel 1" "0,1" bitfld.long 0x0 5. " TX1_UNDERFLOW ,Transmitter register underflow. Channel 1" "0,1" textline " " bitfld.long 0x0 6. " RX1_FULL ,Receiver register full or almost full. Channel 1" "0,1" bitfld.long 0x0 7. " RESERVED ,Reads returns 0" "0,1" textline " " bitfld.long 0x0 8. " TX2_EMPTY ,Transmitter register empty or almost empty. Channel 2" "0,1" bitfld.long 0x0 9. " TX2_UNDERFLOW ,Transmitter register underflow. Channel 2" "0,1" textline " " bitfld.long 0x0 10. " RX2_FULL ,Receiver register full or almost full. Channel 2" "0,1" bitfld.long 0x0 11. " RESERVED ,Reads returns 0." "0,1" textline " " bitfld.long 0x0 12. " TX3_EMPTY ,Transmitter register is empty or almost empty. Note: Enabling the channel automatically rises this event." "0,1" bitfld.long 0x0 13. " TX3_UNDERFLOW ,Transmitter register underflow. Only when Channel 3 is enabled. The transmitter register is empty (not updated by host or DMA with new data) before its time slot assignment. Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled." "0,1" textline " " bitfld.long 0x0 14. " RX3_FULL ,Receiver register is full or almost full. Only when Channel 3 is enabled" "0,1" bitfld.long 0x0 15. " RESERVED ,Reads returns 0" "0,1" textline " " bitfld.long 0x0 16. " WKS ,Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]" "0,1" bitfld.long 0x0 17. " EOW ,End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reads returns 0" group.byte 0x11C++0x3 line.long 0x0 "MCSPI_IRQENABLE,This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis." bitfld.long 0x0 0. " TX0_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 0" "0,1" bitfld.long 0x0 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 0" "0,1" textline " " bitfld.long 0x0 2. " RX0_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 0" "0,1" bitfld.long 0x0 3. " RX0_OVERFLOW_ENABLE ,Receiver register Overflow Interrupt Enable. Channel 0" "0,1" textline " " bitfld.long 0x0 4. " TX1_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 1" "0,1" bitfld.long 0x0 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 1" "0,1" textline " " bitfld.long 0x0 6. " RX1_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 1" "0,1" bitfld.long 0x0 7. " RESERVED ,Reads return 0." "0,1" textline " " bitfld.long 0x0 8. " TX2_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 2" "0,1" bitfld.long 0x0 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 2" "0,1" textline " " bitfld.long 0x0 10. " RX2_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 2" "0,1" bitfld.long 0x0 11. " RESERVED ,Reads return 0." "0,1" textline " " bitfld.long 0x0 12. " TX3_EMPTY_ENABLE ,Transmitter register Empty Interrupt Enable. Channel 3" "0,1" bitfld.long 0x0 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register Underflow Interrupt Enable. Channel 3" "0,1" textline " " bitfld.long 0x0 14. " RX3_FULL_ENABLE ,Receiver register Full Interrupt Enable. Channel 3" "0,1" bitfld.long 0x0 15. " RESERVED ,Reads returns 0." "0,1" textline " " bitfld.long 0x0 16. " WKE ,Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "0,1" bitfld.long 0x0 17. " EOW_ENABLE ,End of Word count Interrupt Enable." "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reads return 0." group.byte 0x120++0x3 line.long 0x0 "MCSPI_WAKEUPENABLE,The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis." bitfld.long 0x0 0. " WKEN ,Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x124++0x3 line.long 0x0 "MCSPI_SYST,This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode." bitfld.long 0x0 0. " SPIEN_0 ,SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[0] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 1. " SPIEN_1 ,SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[1] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " SPIEN_2 ,SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[2] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[2] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 3. " SPIEN_3 ,SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[3] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[3] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 4. " SPIDAT_0 ,SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction), the SPIDAT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR0] = 1 (input mode direction), this bit returns the value on the SPIDAT[0] line (high or low), and a write into this bit has no effect." "0,1" bitfld.long 0x0 5. " SPIDAT_1 ,SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction), the SPIDAT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR1] = 1 (input mode direction), this bit returns the value on the SPIDAT[1] line (high or low), and a write into this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " SPICLK ,SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the CLKSPI line (high or low), and a write into this bit has no effect. If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the CLKSPI line is driven high or low according to the value written into this register." "0,1" bitfld.long 0x0 7. " WAKD ,SWAKEUP output (signal data value of internal signal to system). The signal is driven high or low according to the value written into this register bit." "0,1" textline " " bitfld.long 0x0 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]." "0,1" bitfld.long 0x0 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]." "0,1" textline " " bitfld.long 0x0 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line." "0,1" bitfld.long 0x0 11. " SSB ,Set status bit" "0,1" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x128++0x3 line.long 0x0 "MCSPI_MODULCTRL,This register is dedicated to the configuration of the serial port interface." bitfld.long 0x0 0. " SINGLE ,Single channel/Multi Channel (master mode only)" "0,1" bitfld.long 0x0 1. " PIN34 ,Pin mode selection: This register is used to configure the SPI pin mode, in master or slave mode. If asserted the controller only use SIMO, SOMI, and SPICLK clock pin for SPI transfers." "0,1" textline " " bitfld.long 0x0 2. " MS ,Master/slave" "0,1" bitfld.long 0x0 3. " SYSTEM_TEST ,Enables the system test mode" "0,1" textline " " bitfld.long 0x0 4.--6. " INITDLY ,Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode. The controller waits for a delay to transmit the first SPI word after channel enabled and corresponding TX register filled. This delay is based on SPI output frequency clock. No clock output provided to the boundary and chip select is not active in 4-pin mode within this period." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " MOA ,Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO. It allows the system to perform multiple SPI word access for a single 32-bit OCP word access. This is possible for WL < 16." "0,1" textline " " bitfld.long 0x0 8. " FDAA ,FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address. If this bit is set the enabled channel which uses the FIFO has its data managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX(i) and MCSPI_RX(i) registers." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reads returns 0." group.byte 0x12C++0x3 line.long 0x0 "MCSPI_CHxCONF,This register is dedicated to the configuration of the channel 0" bitfld.long 0x0 0. " PHA ,SPICLK phase (see, )" "0,1" bitfld.long 0x0 1. " POL ,SPICLK polarity (see, )" "0,1" textline " " bitfld.long 0x0 2.--5. " CLKD ,Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when MCSPI_CHCONF[CLKG] is cleared. Otherwise this register is the 4-LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] register. The value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " EPOL ,SPIEN polarity" "0,1" textline " " bitfld.long 0x0 7.--11. " WL ,SPI word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 12.--13. " TRM ,Transmit/receive modes" "0,1,2,3" textline " " bitfld.long 0x0 14. " DMAW ,DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter register of the channel." "0,1" bitfld.long 0x0 15. " DMAR ,DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the channel." "0,1" textline " " bitfld.long 0x0 16. " DPE0 ,Transmission Enable for data line 0 (SPIDATAGZEN[0])" "0,1" bitfld.long 0x0 17. " DPE1 ,Transmission enable for data line 1 (SPIDATAGZEN[1])" "0,1" textline " " bitfld.long 0x0 18. " IS ,Input Select" "0,1" bitfld.long 0x0 19. " TURBO ,Turbo mode" "0,1" textline " " bitfld.long 0x0 20. " FORCE ,Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)." "0,1" bitfld.long 0x0 21.--22. " SPIENSLV ,Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases." "0,1,2,3" textline " " bitfld.long 0x0 23. " SBE ,Start-bit enable for SPI transfer" "0,1" bitfld.long 0x0 24. " SBPOL ,Start-bit polarity" "0,1" textline " " bitfld.long 0x0 25.--26. " TCS0 ,Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock." "0,1,2,3" bitfld.long 0x0 27. " FFEW ,FIFO enabled for transmit: Only one channel can have this bit field set." "0,1" textline " " bitfld.long 0x0 28. " FFER ,FIFO enabled for receive: Only one channel can have this bit field set." "0,1" bitfld.long 0x0 29. " CLKG ,Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio. Then the clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values" "0,1" textline " " bitfld.long 0x0 30.--31. " RESERVED ,Read returns 0." "0,1,2,3" group.byte 0x130++0x3 line.long 0x0 "MCSPI_CHxSTAT,This register provides status information about transmitter and receiver registers of channel 0." bitfld.long 0x0 0. " RXS ,Channel 'i' receiver register status" "0,1" bitfld.long 0x0 1. " TXS ,Channel 'i' transmitter register status" "0,1" textline " " bitfld.long 0x0 2. " EOT ,Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details." "0,1" bitfld.long 0x0 3. " TXFFE ,Channel 'i' FIFO transmit buffer empty status" "0,1" textline " " bitfld.long 0x0 4. " TXFFF ,Channel 'i' FIFO transmit buffer full status" "0,1" bitfld.long 0x0 5. " RXFFE ,Channel 'i' FIFO receive buffer empty status" "0,1" textline " " bitfld.long 0x0 6. " RXFFF ,Channel 'i' FIFO receive buffer full status" "0,1" hexmask.long 0x0 7.--31. 1. " RESERVED ,Read returns 0." group.byte 0x134++0x3 line.long 0x0 "MCSPI_CHxCTRL,This register is dedicated to enable channel 0." bitfld.long 0x0 0. " EN ,Channel enable" "0,1" hexmask.long.byte 0x0 1.--7. 1. " RESERVED ,Read returns 0." textline " " hexmask.long.byte 0x0 8.--15. 1. " EXTCLK ,Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Read returns 0." group.byte 0x138++0x3 line.long 0x0 "MCSPI_TXx,This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." hexmask.long 0x0 0.--31. 1. " TDATA ,Channel 0 data to transmit" group.byte 0x13C++0x3 line.long 0x0 "MCSPI_RXx,This register contains a single SPI word received through the serial link, what ever SPI word length is." hexmask.long 0x0 0.--31. 1. " RDATA ,Channel 0 received data" group.byte 0x17C++0x3 line.long 0x0 "MCSPI_XFERLEVEL,This register provides transfer levels needed while using FIFO buffer during transfer." hexmask.long.byte 0x0 0.--7. 1. " AEL ,Buffer almost empty. This register holds the programmable almost empty level value used to determine almost empty buffer condition. If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes, then the bufferMCSPI_XFERLEVEL[AEL] must be set with  1." hexmask.long.byte 0x0 8.--15. 1. " AFL ,Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition. If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes, then the buffer MCSPI_XFERLEVEL[AFL] must be set with n1.The size of this register is defined by the generic parameter FFNBYTE." textline " " hexmask.long.word 0x0 16.--31. 1. " WCNT ,SPI word counter. This register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO buffer. When transfer had started, a read back in this register returns the current SPI word transfer index." group.byte 0x180++0x3 line.long 0x0 "MCSPI_DAFTX,This register contains the SPI words to be transmitted on the SPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. " DAFTDATA ,FIFO data to transmit with DMA 256 bit aligned address.This register is only used when[8] FDAA is set to 0x1 and only one of the enabled channels has the [27] FFEW bit set to 0x1. If these conditions are not met any access to this register returns a null value. enum=Disable ." group.byte 0x1A0++0x3 line.long 0x0 "MCSPI_DAFRX,This register contains the SPI words received from the SPI bus when FIFO is used and DMA address is aligned on 256 bit. This register is an image of one of the registers corresponding to the channel which has its FIFO enabled." hexmask.long 0x0 0.--31. 1. " DAFRDATA ,FIFO data received with DMA 256 bit aligned address.This register is only used when[8] FDAA is set to 0x1 and only one of the enabled channels has the [28] FFER bit set to 0x1. If these conditions are not met any access to this register returns a null value. enum=Disable ." width 0x0B tree.end tree "QSPI" base ad:0x4B300000 width 32. group.byte 0x0++0x3 line.long 0x0 "QSPI_PID,Revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "QSPI_SYSCONFIG,QSPI_SYSCONFIG" bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLE_MODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state. 0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode 0x3: Reserved." "0,1,2,3" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "QSPI_INTR_STATUS_RAW_SET,This register contains raw interrupt status flags." bitfld.long 0x0 0. " FIRQ_RAW ,Frame Interrupt Status. Read indicates the raw status.Read: . Write: ." "0,1" bitfld.long 0x0 1. " WIRQ_RAW ,Word Interrupt Status. Read indicates the raw status.Read: . Write: ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "QSPI_INTR_STATUS_ENABLED_CLEAR,This register contains status flags of the enabled interrupts." bitfld.long 0x0 0. " FIRQ_ENA ,Frame Interrupt Enabled Status. Read indicates enabled status.Read: . Write: ." "0,1" bitfld.long 0x0 1. " WIRQ_ENA ,Word Interrupt Enabled Status. Read indicates enabled status.Read: . Write: ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "QSPI_INTR_ENABLE_SET_REG,This register enables the interrupts." bitfld.long 0x0 0. " FIRQ_ENA_SET ,Frame interrupt enable.Read: . Write: ." "0,1" bitfld.long 0x0 1. " WIRQ_ENA_SET ,Word interrupt enable.Read: . Write: ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "QSPI_INTR_ENABLE_CLEAR_REG,This register disables the interrupts." bitfld.long 0x0 0. " FIRQ_ENA_CLR ,Frame interrupt disable.Read: . Write: ." "0,1" bitfld.long 0x0 1. " WIRQ_ENA_CLR ,Word interrupt disable.Read: . Write: ." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "QSPI_INTC_EOI_REG,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if a new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." hexmask.long 0x0 0.--31. 1. " EOI_VECTOR ,Number associated with the interrupt outputs. There is one interrupt output. Write 0x0 after servicing the interrupt to be able to generate another interrupt if pulse interrupts are used. Any other write value is ignored." group.byte 0x40++0x3 line.long 0x0 "QSPI_SPI_CLOCK_CNTRL_REG,This register controls the external SPI clock generation. This register can only be written when the QSPI module is not busy, as identified by the[0] BUSY bit." hexmask.long.word 0x0 0.--15. 1. " DCLK_DIV ,Divide ratio for the external SPI clock (qspi1_sclk)" hexmask.long.word 0x0 16.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " CLKEN ,External SPI clock (qspi1_sclk) enable." "0,1" group.byte 0x44++0x3 line.long 0x0 "QSPI_SPI_DC_REG,This register controls the different modes for each output chip select. This register can only be written when the QSPI module is not busy, as identified by the[0] BUSY bit." bitfld.long 0x0 0. " CKP0 ,Clock polarity for chip select 0." "0,1" bitfld.long 0x0 1. " CSP0 ,Chip select polarity for chip select 0." "0,1" textline " " bitfld.long 0x0 2. " CKPH0 ,Clock phase for chip select 0. If CKP0 = 0: 0x0: Data shifted out on falling edge; input on 0x1: Data shifted out on rising edge; input on If CKP0 = 1: 0x0: Data shifted out on rising edge; input on 0x1: Data shifted out on falling edge; input on" "0,1" bitfld.long 0x0 3.--4. " DD0 ,Data delay for chip select 0 0x0: Data is output on the same cycle as the qspi1_cs[0] goes active 0x1: Data is output 1 qspi1_sclk cycle after the qspi1_cs[0] goes active 0x2: Data is output 2 qspi1_sclk cycles after the qspi1_cs[0] goes active 0x3: Data is output 3 qspi1_sclk cycles after the qspi1_cs[0] goes active" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. " CKP1 ,Clock polarity for chip select 1." "0,1" textline " " bitfld.long 0x0 9. " CSP1 ,Chip select polarity for chip select 1." "0,1" bitfld.long 0x0 10. " CKPH1 ,Clock phase for chip select 1. If CKP1 = 0: 0x0: Data shifted out on falling edge; input on 0x1: Data shifted out on rising edge; input on If CKP1 = 1: 0x0: Data shifted out on rising edge; input on 0x1: Data shifted out on falling edge; input on" "0,1" textline " " bitfld.long 0x0 11.--12. " DD1 ,Data delay for chip select 1 0x0: Data is output on the same cycle as the qspi1_cs[1] goes active 0x1: Data is output 1 qspi1_sclk cycle after the qspi1_cs[1] goes active 0x2: Data is output 2 qspi1_sclk cycles after the qspi1_cs[1] goes active 0x3: Data is output 3 qspi1_sclk cycles after the qspi1_cs[1] goes active" "0,1,2,3" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " CKP2 ,Clock polarity for chip select 2." "0,1" bitfld.long 0x0 17. " CSP2 ,Chip select polarity for chip select 2." "0,1" textline " " bitfld.long 0x0 18. " CKPH2 ,Clock phase for chip select 2. If CKP2 = 0: 0x0: Data shifted out on falling edge; input on 0x1: Data shifted out on rising edge; input on If CKP2 = 1: 0x0: Data shifted out on rising edge; input on 0x1: Data shifted out on falling edge; input on" "0,1" bitfld.long 0x0 19.--20. " DD2 ,Data delay for chip select 2 0x0: Data is output on the same cycle as the qspi1_cs[2] goes active 0x1: Data is output 1 qspi1_sclk cycle after the qspi1_cs[2] goes active 0x2: Data is output 2 qspi1_sclk cycles after the qspi1_cs[2] goes active 0x3: Data is output 3 qspi1_sclk cycles after the qspi1_cs[2] goes active" "0,1,2,3" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. " CKP3 ,Clock polarity for chip select 3." "0,1" textline " " bitfld.long 0x0 25. " CSP3 ,Chip select polarity for chip select 3." "0,1" bitfld.long 0x0 26. " CKPH3 ,Clock phase for chip select 3. If CKP3 = 0: 0x0: Data shifted out on falling edge; input on 0x1: Data shifted out on rising edge; input on If CKP3 = 1: 0x0: Data shifted out on rising edge; input on 0x1: Data shifted out on falling edge; input on" "0,1" textline " " bitfld.long 0x0 27.--28. " DD3 ,Data delay for chip select 3 0x0: Data is output on the same cycle as the qspi1_cs[3] goes active 0x1: Data is output 1 qspi1_sclk cycle after the qspi1_cs[3] goes active 0x2: Data is output 2 qspi1_sclk cycles after the qspi1_cs[3] goes active 0x3: Data is output 3 qspi1_sclk cycles after the qspi1_cs[3] goes active" "0,1,2,3" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x48++0x3 line.long 0x0 "QSPI_SPI_CMD_REG,This register sets up the SPI command. This register can only be written when the QSPI module is not busy, as identified by the[0] BUSY bit." hexmask.long.word 0x0 0.--11. 1. " FLEN ,Frame Length. 0x0: 1 word 0x1: 2 words ... 0xFFF: 4096 words" bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " WIRQ ,Word complete interrupt enable" "0,1" bitfld.long 0x0 15. " FIRQ ,Frame complete interrupt enable." "0,1" textline " " bitfld.long 0x0 16.--18. " CMD ,Transfer command. 0x0: Reserved 0x1: 4-pin Read Single 0x2: 4-pin Write Single 0x3: 4-pin Read Dual 0x4: Reserved 0x5: 3-pin Read Single 0x6: 3-pin Write Single 0x7: 6-pin Read Quad" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 19.--25. 1. " WLEN ,Word length. Sets the size of the individual transfers from 1 to 128 bits. When a word length greater than 32 bits is configured, not only the 0x0: 1 bit 0x1: 2 bits ... 0x7F: 128 bits" textline " " bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" bitfld.long 0x0 28.--29. " CSNUM ,Device select. Sets the active chip select for the current transfer. 0x0: Chip Select 0 active 0x1: Chip Select 1 active 0x2: Chip Select 2 active 0x3: Chip Select 3 active" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x4C++0x3 line.long 0x0 "QSPI_SPI_STATUS_REG,This register contains indicators to allow the user to monitor the progression of a frame transfer. This register can only be written when the QSPI module is not busy, as identified by the[0] BUSY bit." bitfld.long 0x0 0. " BUSY ,Busy bit. Active transfer in progress. This bit is only set during an active word transfer. Between words it is cleared." "0,1" bitfld.long 0x0 1. " WC ,Word complete. This bit is set after each word transfer completes. This bit is reset whenQSPI_SPI_STATUS_REG register is read." "0,1" textline " " bitfld.long 0x0 2. " FC ,Frame complete. This bit is set after the transmision of all the requested words completes. This bit is reset whenQSPI_SPI_STATUS_REG register is read." "0,1" hexmask.long.word 0x0 3.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--27. 1. " WDCNT ,Word count. This field will reflect the 1-4096 words transferred" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x50++0x3 line.long 0x0 "QSPI_SPI_DATA_REG,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left. This register acts as the first 32-bit register of the 128-bit shift in/out register. This register is cleared between reads or writes and can only be written when the QSPI module is not busy, as identified by the[0] BUSY bit." hexmask.long 0x0 0.--31. 1. " DATA ,Data register for read and write operations" group.byte 0x54++0x3 line.long 0x0 "QSPI_SPI_SETUP0_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 0 output). By default (reset), the device uses a write command of 2, read command of 3 and address bytes number of 3. This default covers most of the serial flash devices, but can be changed." hexmask.long.byte 0x0 0.--7. 1. " RCMD ,Read Command" bitfld.long 0x0 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent. 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: 4 bytes" "0,1,2,3" textline " " bitfld.long 0x0 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read. 0x0: No dummy bytes required. Use the value in NUM_D_BITS 0x1: Use 8 bits 0x2: Use 16 bits 0x3: Use 24 bits" "0,1,2,3" bitfld.long 0x0 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command. 0x0: Normal read (all data input on qspi1_d[1]) 0x1: Dual read (odd bytes input on qspi1_d[1]; even bytes on qspi1_d[0]) 0x2: Normal read (all data input on qspi1_d[1]) 0x3: Quad read (uses also qspi1_d[2] and qspi1_d[3])" "0,1,2,3" textline " " bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" hexmask.long.byte 0x0 16.--23. 1. " WCMD ,Write command" textline " " bitfld.long 0x0 24.--28. " NUM_D_BITS ,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x58++0x3 line.long 0x0 "QSPI_SPI_SETUP1_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 1 output). By default (reset), the device uses a write command of 2, read command of 3 and address bytes number of 3. This default covers most of the serial flash devices, but can be changed." hexmask.long.byte 0x0 0.--7. 1. " RCMD ,Read Command" bitfld.long 0x0 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent. 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: 4 bytes" "0,1,2,3" textline " " bitfld.long 0x0 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read. 0x0: No dummy bytes required. Use the value in NUM_D_BITS 0x1: Use 8 bits 0x2: Use 16 bits 0x3: Use 24 bits" "0,1,2,3" bitfld.long 0x0 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command. 0x0: Normal read (all data input on qspi1_d[1]) 0x1: Dual read (odd bytes input on qspi1_d[1]; even bytes on qspi1_d[0]) 0x2: Normal read (all data input on qspi1_d[1]) 0x3: Quad read (uses also qspi1_d[2] and qspi1_d[3])" "0,1,2,3" textline " " bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" hexmask.long.byte 0x0 16.--23. 1. " WCMD ,Write command" textline " " bitfld.long 0x0 24.--28. " NUM_D_BITS ,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x5C++0x3 line.long 0x0 "QSPI_SPI_SETUP2_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 2 output). By default (reset), the device uses a write command of 2, read command of 3 and address bytes number of 3. This default covers most of the serial flash devices, but can be changed." hexmask.long.byte 0x0 0.--7. 1. " RCMD ,Read Command" bitfld.long 0x0 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent. 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: 4 bytes" "0,1,2,3" textline " " bitfld.long 0x0 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read. 0x0: No dummy bytes required. Use the value in NUM_D_BITS 0x1: Use 8 bits 0x2: Use 16 bits 0x3: Use 24 bits" "0,1,2,3" bitfld.long 0x0 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command. 0x0: Normal read (all data input on qspi1_d[1]) 0x1: Dual read (odd bytes input on qspi1_d[1]; even bytes on qspi1_d[0]) 0x2: Normal read (all data input on qspi1_d[1]) 0x3: Quad read (uses also qspi1_d[2] and qspi1_d[3])" "0,1,2,3" textline " " bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" hexmask.long.byte 0x0 16.--23. 1. " WCMD ,Write command" textline " " bitfld.long 0x0 24.--28. " NUM_D_BITS ,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x60++0x3 line.long 0x0 "QSPI_SPI_SETUP3_REG,This register contains the read/write command setup for the memory mapped protocol translator (effecting chip select 3 output). By default (reset), the device uses a write command of 2, read command of 3 and address bytes number of 3. This default covers most of the serial flash devices, but can be changed." hexmask.long.byte 0x0 0.--7. 1. " RCMD ,Read Command" bitfld.long 0x0 8.--9. " NUM_A_BYTES ,Number of address bytes to be sent. 0x0: 1 byte 0x1: 2 bytes 0x2: 3 bytes 0x3: 4 bytes" "0,1,2,3" textline " " bitfld.long 0x0 10.--11. " NUM_D_BYTES ,Number of dummy bytes to be used for fast read. 0x0: No dummy bytes required. Use the value in NUM_D_BITS 0x1: Use 8 bits 0x2: Use 16 bits 0x3: Use 24 bits" "0,1,2,3" bitfld.long 0x0 12.--13. " READ_TYPE ,Determines if the read command is a single, dual or quad read mode command. 0x0: Normal read (all data input on qspi1_d[1]) 0x1: Dual read (odd bytes input on qspi1_d[1]; even bytes on qspi1_d[0]) 0x2: Normal read (all data input on qspi1_d[1]) 0x3: Quad read (uses also qspi1_d[2] and qspi1_d[3])" "0,1,2,3" textline " " bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" hexmask.long.byte 0x0 16.--23. 1. " WCMD ,Write command" textline " " bitfld.long 0x0 24.--28. " NUM_D_BITS ,Number of dummy bits to use if NUM_D_BYTES = 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x64++0x3 line.long 0x0 "QSPI_SPI_SWITCH_REG,This register allows initiators to switch control of the SPI core port between the configuration port and the SFI translator. In addition, an interrupt enable field is defined which is used to enable or disable word complete interrupt generation in memory mapped mode." bitfld.long 0x0 0. " MMPT_S ,MPT select." "0,1" bitfld.long 0x0 1. " MM_INT_EN ,Memory mapped mode interrupt enable." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "QSPI_SPI_DATA_REG_1,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left. This register acts as the second 32-bit register of the 128-bit shift in/out register. This register is cleared between reads or writes and can only be written when the QSPI module is not busy, as identified by the[0] BUSY bit." hexmask.long 0x0 0.--31. 1. " DATA ,Data register for read and write operations" group.byte 0x6C++0x3 line.long 0x0 "QSPI_SPI_DATA_REG_2,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left. This register acts as the third 32-bit register of the 128-bit shift in/out register. This register is cleared between reads or writes and can only be written when the QSPI module is not busy, as identified by the[0] BUSY bit." hexmask.long 0x0 0.--31. 1. " DATA ,Data register for read and write operations" group.byte 0x70++0x3 line.long 0x0 "QSPI_SPI_DATA_REG_3,The data received in this register is shifted to the LSB position and the content of the register is shifted to the left. This register acts as the fourth 32-bit register of the 128-bit shift in/out register. This register is cleared between reads or writes and can only be written when the QSPI module is not busy, as identified by the[0] BUSY bit." hexmask.long 0x0 0.--31. 1. " DATA ,Data register for read and write operations" width 0x0B tree.end tree "MCASP1_CFG" base ad:0x48460000 width 19. group.byte 0x0++0x3 line.long 0x0 "MCASP_PID,Peripheral identification register" bitfld.long 0x0 0.--5. " REVMINOR ,Minor revision number." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Non-custom. Indicates a special version for a given device." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " REVMAJOR ,Major revision number." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNCTION ,McASP. Indicates a software-compatible module family." bitfld.long 0x0 28.--29. " RESV ,Reserved." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,Scheme. Distinguishes between old scheme and current." "0,1,2,3" group.byte 0x4++0x3 line.long 0x0 "PWRIDLESYSCONFIG,Power idle module configuration register." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode - default state 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 2.--5. " OTHER ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "MCASP_PFUNC,Specifies the function of the pins as either a McASP pin or a GPIO pin." bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin functions as McASP or GPIO." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin functions as McASP or GPIO." "0,1" group.byte 0x14++0x3 line.long 0x0 "MCASP_PDIR,Pin direction register - specifies the direction of the McASP pins as either an input or an output pin." bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin functions as an input or output." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin functions as an input or output." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin functions as an input or output." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin functions as an input or output." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin functions as an input or output." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin functions as an input or output." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin functions as an input or output." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin functions as an input or output." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin functions as an input or output." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin functions as an input or output." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin functions as an input or output." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin functions as an input or output." "0,1" group.byte 0x18++0x3 line.long 0x0 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times, and may be read back at all times. The value held by is not affected by writing to and . However, the data value in is driven out onto the McASP pin only if the corresponding bit in is set to 1 (GPIO function) and the corresponding bit in is set to 1 (output)." bitfld.long 0x0 0. " AXR0 ,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1." "0,1" bitfld.long 0x0 7. " AXR ,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1." "0,1" bitfld.long 0x0 28. " AFSX ,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "0,1" bitfld.long 0x0 30. " AHCLKR ,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1." "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDIN,Pin data input register - holds the state of all the McASP pins. allows reading the actual value of the pin, regardless of the state of and ." bitfld.long 0x0 0. " AXR0 ,Logic level on AXR0 pin" "0,1" bitfld.long 0x0 1. " AXR1 ,Logic level on AXR1 pin" "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Logic level on AXR2 pin" "0,1" bitfld.long 0x0 3. " AXR3 ,Logic level on AXR3 pin" "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Logic level on AXR4 pin" "0,1" bitfld.long 0x0 5. " AXR5 ,Logic level on AXR5 pin" "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Logic level on AXR6 pin" "0,1" bitfld.long 0x0 7. " AXR7 ,Logic level on AXR7 pin" "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Logic level on AXR8 pin" "0,1" bitfld.long 0x0 9. " AXR9 ,Logic level on AXR9 pin" "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Logic level on AXR10 pin" "0,1" bitfld.long 0x0 11. " AXR11 ,Logic level on AXR11 pin" "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Logic level on AXR12 pin" "0,1" bitfld.long 0x0 13. " AXR13 ,Logic level on AXR13 pin" "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Logic level on AXR14 pin" "0,1" bitfld.long 0x0 15. " AXR15 ,Logic level on AXR15 pin" "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Logic level on ACLKX pin" "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Logic level on AHCLKX pin" "0,1" bitfld.long 0x0 28. " AFSX ,Logic level on AFSX pin" "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Logic level on ACLKR pin" "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Logic level on AFSR pin" "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only. Writing a 1 to the bit sets the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic high on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x20++0x3 line.long 0x0 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only. Writing a 1 to the bit clears the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic low on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x44++0x3 line.long 0x0 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections. The bit fields in are synchronized and latched by the transmitter and receiver corresponding clocks - ACLKX (bits [12:8]) and ACLKR (bits [4:0]), respectively. Before programming , ensure that the serial clocks are running. If the corresponding external serial clocks - ACLKX and ACLKR, are not yet running, select the internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL and ACLKRCTL before programming the . Also, after programming any bits in , do not proceed until reading back from and verifying that the bits in are latched." bitfld.long 0x0 0. " RCLKRST ,Receive clock divider reset enable bit." "0,1" bitfld.long 0x0 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit." "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed." "0,1" bitfld.long 0x0 3. " RSMRST ,Receive state machine reset enable bit." "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,Transmit clock divider reset enable bit" "0,1" bitfld.long 0x0 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,Transmit serializer clear enable bit. By clearing and then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the next active time slot, an underrun occurs." "0,1" bitfld.long 0x0 11. " XSMRST ,Transmit state-machine reset enable bitAXR[n] pin state: If[n] = 0 and [n] = 1, the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot. ." "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Transmit frame-sync generator reset enable bit" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "MCASP_AMUTE,Mute control register - Controls the McASP mute output pin - AMUTE (Not implemented at device level)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "MCASP_LBCTL,The digital loopback control register () controls the internal (McASP module)- level and chip-level loopback settings of the McASP in TDM mode. Note that loopback is NOT supported if McASP is configured in DIT mode." bitfld.long 0x0 0. " DLBEN ,Loop back mode enable bit." "0,1" bitfld.long 0x0 1. " ORD ,Loopback order bit when loopback mode is enabled (DLBEN = 1)." "0,1" textline " " bitfld.long 0x0 2.--3. " MODE ,Loopback generator mode bits.0x2, 0x3: Reserved enum=RESERVED ." "0,1,2,3" bitfld.long 0x0 4. " IOLBEN ,If DLBEN=0b1, the IOLBEN bit selects betweeninternal-level (McASP module-level) and chip I/O-level loopback modes. IOLBEN bit value is irrelevant, If DLBEN=0b0." "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "MCASP_TXDITCTL,Transmit DIT mode control register, controls DIT operations of the McASP" bitfld.long 0x0 0. " DITEN ,DIT mode enable bit" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " VA ,Valid bit for even time slots (DIT left subframe)." "0,1" bitfld.long 0x0 3. " VB ,Valid bit for odd time slots (DIT right subframe)." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "MCASP_GBLCTLR,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12). Reads return GBLCTL" bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU." hexmask.long 0x0 0.--31. 1. " RMASK_31_0 ,Receive data mask enable bit." group.byte 0x68++0x3 line.long 0x0 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format." bitfld.long 0x0 0.--2. " RROT ,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RBUSEL ,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " RSSZ ,Receive slot size.0x0 - 0x2: Reserved enum=RSVD ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " RPBIT ,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits. This field only applies when RPAD = 2h.0x01 - 0x1F: Pad with value of the bit positioned within the range RBUFn[31:1]. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " RRVRS ,Receive serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " RDATDLY ,Receive Frame sync delay of AXR[n]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)." bitfld.long 0x0 0. " FSRP ,Receive frame sync polarity select bit." "0,1" bitfld.long 0x0 1. " FSRM ,Receive frame sync generation select bit." "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " FRWID ,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " RMOD ,Receive frame sync mode select bits.0x3 - 0x20: 3-slot TDM to 32-slot TDM mode . 0x21 - 0x17F: Reserved . 0x181 - 0x1FF: Reserved ." textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator." bitfld.long 0x0 0.--4. " CLKRDIV ,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0.0x2 - 0x1F: Divide-by-3 to divide-by-32 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKRM ,Receive bit clock source bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " CLKRP ,Receive bitstream clock polarity select bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKRADJ ,CLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0.If CLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR.0x2 - 0xFFF: Divide-by-3 to divide-by-4096 ." bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKRM ,High Freq. RCV clock Source" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKRADJ ,HCLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active." hexmask.long 0x0 0.--31. 1. " RTDMS_31_0 ,Receiver mode during TDM time slot n." group.byte 0x7C++0x3 line.long 0x0 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP condition(s) generates RINT." bitfld.long 0x0 0. " ROVRN ,Receiver overrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " RDMAERR ,Receive DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " RDATA ,Receive data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " RSTAFRM ,Receive start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number." bitfld.long 0x0 0. " ROVRN ,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync (AFSR) occurs before it is expected. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 3. " RTDMSLOT ,Returns the LSB of RSLOT. Allows a single read ofMCASP_RXSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 5. " RDATA ,Receive data ready flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " RSTAFRM ,Receive start of frame flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 7. " RDMAERR ,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the DMA port in a given time slot than were programmed as receivers. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 8. " RERR ,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame." hexmask.long.word 0x0 0.--8. 1. " RSLOTCNT ,0x0 - 0x17F: Current receive time slot count. Legal values: 0 to 383 (17Fh). TDM function is not supported for > 32 time slots. However, TDM time slot counter may count to 383 when used to receive a DIR block (transferred over TDM format)." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." bitfld.long 0x0 0.--3. " RPS ,Receive clock check prescaler value.0x9 - 0xF: Reserved enum=DIVBY8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " RMIN ,0x00 - 0xFF: Receive clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If RCNT is less than RMIN after counting 32 AHCLKR signals, RCKFAIL in RSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " RMAX ,0x00-0xFF: Receive clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If the current counter value is greater than RMAX after counting 32 AHCLKR signals, RCKFAIL inMCASP_RXSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " RCNT ,0x0 - 0xFF: Receive clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 receive high-frequency master clock (AHCLKR) signals, and stores the count in RCNT until the next measurement is taken." group.byte 0x8C++0x3 line.long 0x0 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x0 0. " RDATDMA ,Receive data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MCASP_GBLCTLX,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12.). Reads return GBLCTL." bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLKR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the McASP" hexmask.long 0x0 0.--31. 1. " XMASK_31_0 ,Transmit data mask enable bit" group.byte 0xA8++0x3 line.long 0x0 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x0 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " XBUSEL ,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " XSSZ ,Transmit slot size0x0 - 0x2: Reserved enum=RSV8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " XPBIT ,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting. This field only applies when XPAD = 0x2.0x1 - 0x1F: Pad with bit 1 to bit 31 value. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " XRVRS ,Transmit serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " XDATDLY ,Transmit sync bit delay" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xAC++0x3 line.long 0x0 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (AFSX)." bitfld.long 0x0 0. " FSXP ,Transmit frame-sync polarity select bit" "0,1" bitfld.long 0x0 1. " FSXM ,Transmit frame-sync generation select bit" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4. " FXWID ,The transmit frame-sync width select bit indicates the width of the transmit frame sync (AFSX) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " XMOD ,Transmit frame-sync mode select bits 0x0: Burst mode 0x1: Reserved 0x2: 2-slot TDM mode (I2S transmit mode) 0x3 - 0x20: 3-slot TDM to 32-slot TDM mode 0x21 - 0x17F: Reserved 0x180: 384-slot DIT mode All other: Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (ACLKX) and the transmit clock generator." bitfld.long 0x0 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits, determine the divide-down ratio from AHCLKX to ACLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0x1F: Divide-by-3 to divide-by-32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKXM ,Transmit bit clock source bit" "0,1" textline " " bitfld.long 0x0 6. " ASYNC ,Transmit operation asynchronous enable bit" "0,1" bitfld.long 0x0 7. " CLKXP ,Transmit bitstream clock polarity select bit." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKXADJ ,CLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If CLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB4++0x3 line.long 0x0 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0xFFF: Divide-by-3 to divide-by-4096" bitfld.long 0x0 12.--13. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKXM ,Transmit high-frequency clock source bit" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKXADJ ,HCLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB8++0x3 line.long 0x0 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)." hexmask.long 0x0 0.--31. 1. " XTDMS_31_0 ,Transmitter mode during TDM time slot n (n = 0..31)" group.byte 0xBC++0x3 line.long 0x0 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP condition(s) generates XINT." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " XDMAERR ,Transmit DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " XSTAFRM ,Transmit start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "MCASP_TXSTAT,Transmitter status register - If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the McASP logic has priority and the flag remains set. This also causes the generation of a new interrupt request." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF[n] to XRSR[n], but XBUF[n] has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT) if this bit and XUNDRN inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT) if this bit and XSYNCERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt (XINT) if this bit and XCKFAIL inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 3. " XTDMSLOT ,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot flag. XLAST, along with XDATA, are set if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT) if this bit and XLAST inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data ready flag. Causes a transmit interrupt (XINT) if this bit and XDATA inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " XSTAFRM ,Transmit start of frame flag. Causes a transmit interrupt (XINT) if this bit and XSTAFRM inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" bitfld.long 0x0 7. " XDMAERR ,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more words to the DATA port of the McASP in a given time slot than it should. Causes a transmit interrupt (XINT) if this bit and XDMAERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 8. " XERR ,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x0 0.--8. 1. " XSLOTCNT ,Current transmit time slot count. the value of this register is 0b0101111111 (0x17f) during reset and 0 after reset." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit." bitfld.long 0x0 0.--3. " XPS ,Transmit clock check prescaler value 0x0: McASP interface clock divided by 1 0x1: McASP interface clock divided by 2 0x2: McASP interface clock divided by 4 0x3: McASP interface clock divided by 8 0x4: McASP interface clock divided by 16 0x5: McASP interface clock divided by 32 0x6: McASP interface clock divided by 64 0x7: McASP interface clock divided by 128 0x8: McASP interface clock divided by 256 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " XMIN ,0x0 to 0xFF: Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (AHCLKX) signals have been received. If XCNT is less than XMIN after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " XMAX ,0x0 to 0xFF: Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (AHCLKX) signals have been received. If the current counter value is greater than XMAX after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " XCNT ,Transmit clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 transmit high-frequency master clock (AHCLKX) signals, and stores the count in XCNT until the next measurement is taken" group.byte 0xCC++0x3 line.long 0x0 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x0 0. " XDATDMA ,Transmit data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD0++0x3 line.long 0x0 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x0 0. " ENABLE ,One-shot clock adjust enable. Not supported. Bit field must always be written as 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x104++0x3 line.long 0x0 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x108++0x3 line.long 0x0 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x10C++0x3 line.long 0x0 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x110++0x3 line.long 0x0 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x114++0x3 line.long 0x0 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x118++0x3 line.long 0x0 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x11C++0x3 line.long 0x0 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x120++0x3 line.long 0x0 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x124++0x3 line.long 0x0 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x128++0x3 line.long 0x0 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x12C++0x3 line.long 0x0 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x130++0x3 line.long 0x0 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x134++0x3 line.long 0x0 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x138++0x3 line.long 0x0 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x13C++0x3 line.long 0x0 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x140++0x3 line.long 0x0 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x144++0x3 line.long 0x0 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x148++0x3 line.long 0x0 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x14C++0x3 line.long 0x0 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x150++0x3 line.long 0x0 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x154++0x3 line.long 0x0 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x158++0x3 line.long 0x0 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x15C++0x3 line.long 0x0 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x180++0x3 line.long 0x0 "MCASP_XRSRCTLn_0,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "MCASP_XRSRCTLn_1,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "MCASP_XRSRCTLn_2,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "MCASP_XRSRCTLn_3,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "MCASP_XRSRCTLn_4,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x194++0x3 line.long 0x0 "MCASP_XRSRCTLn_5,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x198++0x3 line.long 0x0 "MCASP_XRSRCTLn_6,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x19C++0x3 line.long 0x0 "MCASP_XRSRCTLn_7,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1A0++0x3 line.long 0x0 "MCASP_XRSRCTLn_8,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1A4++0x3 line.long 0x0 "MCASP_XRSRCTLn_9,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1A8++0x3 line.long 0x0 "MCASP_XRSRCTLn_10,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1AC++0x3 line.long 0x0 "MCASP_XRSRCTLn_11,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1B0++0x3 line.long 0x0 "MCASP_XRSRCTLn_12,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1B4++0x3 line.long 0x0 "MCASP_XRSRCTLn_13,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1B8++0x3 line.long 0x0 "MCASP_XRSRCTLn_14,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1BC++0x3 line.long 0x0 "MCASP_XRSRCTLn_15,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x204++0x3 line.long 0x0 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x208++0x3 line.long 0x0 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x20C++0x3 line.long 0x0 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x210++0x3 line.long 0x0 "MCASP_TXBUFn_4,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x214++0x3 line.long 0x0 "MCASP_TXBUFn_5,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x218++0x3 line.long 0x0 "MCASP_TXBUFn_6,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x21C++0x3 line.long 0x0 "MCASP_TXBUFn_7,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x220++0x3 line.long 0x0 "MCASP_TXBUFn_8,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x224++0x3 line.long 0x0 "MCASP_TXBUFn_9,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x228++0x3 line.long 0x0 "MCASP_TXBUFn_10,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x22C++0x3 line.long 0x0 "MCASP_TXBUFn_11,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x230++0x3 line.long 0x0 "MCASP_TXBUFn_12,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x234++0x3 line.long 0x0 "MCASP_TXBUFn_13,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x238++0x3 line.long 0x0 "MCASP_TXBUFn_14,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x23C++0x3 line.long 0x0 "MCASP_TXBUFn_15,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x280++0x3 line.long 0x0 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x284++0x3 line.long 0x0 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x288++0x3 line.long 0x0 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x28C++0x3 line.long 0x0 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x290++0x3 line.long 0x0 "MCASP_RXBUFn_4,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x294++0x3 line.long 0x0 "MCASP_RXBUFn_5,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x298++0x3 line.long 0x0 "MCASP_RXBUFn_6,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x29C++0x3 line.long 0x0 "MCASP_RXBUFn_7,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2A0++0x3 line.long 0x0 "MCASP_RXBUFn_8,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2A4++0x3 line.long 0x0 "MCASP_RXBUFn_9,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2A8++0x3 line.long 0x0 "MCASP_RXBUFn_10,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2AC++0x3 line.long 0x0 "MCASP_RXBUFn_11,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2B0++0x3 line.long 0x0 "MCASP_RXBUFn_12,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2B4++0x3 line.long 0x0 "MCASP_RXBUFn_13,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2B8++0x3 line.long 0x0 "MCASP_RXBUFn_14,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2BC++0x3 line.long 0x0 "MCASP_RXBUFn_15,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" width 0x0B tree.end tree "MCASP2_CFG" base ad:0x48464000 width 19. group.byte 0x0++0x3 line.long 0x0 "MCASP_PID,Peripheral identification register" bitfld.long 0x0 0.--5. " REVMINOR ,Minor revision number." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Non-custom. Indicates a special version for a given device." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " REVMAJOR ,Major revision number." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNCTION ,McASP. Indicates a software-compatible module family." bitfld.long 0x0 28.--29. " RESV ,Reserved." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,Scheme. Distinguishes between old scheme and current." "0,1,2,3" group.byte 0x4++0x3 line.long 0x0 "PWRIDLESYSCONFIG,Power idle module configuration register." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode - default state 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 2.--5. " OTHER ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "MCASP_PFUNC,Specifies the function of the pins as either a McASP pin or a GPIO pin." bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin functions as McASP or GPIO." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin functions as McASP or GPIO." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin functions as McASP or GPIO." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin functions as McASP or GPIO." "0,1" group.byte 0x14++0x3 line.long 0x0 "MCASP_PDIR,Pin direction register - specifies the direction of the McASP pins as either an input or an output pin." bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin functions as an input or output." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin functions as an input or output." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin functions as an input or output." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin functions as an input or output." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin functions as an input or output." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin functions as an input or output." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin functions as an input or output." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin functions as an input or output." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin functions as an input or output." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin functions as an input or output." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin functions as an input or output." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin functions as an input or output." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin functions as an input or output." "0,1" group.byte 0x18++0x3 line.long 0x0 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times, and may be read back at all times. The value held by is not affected by writing to and . However, the data value in is driven out onto the McASP pin only if the corresponding bit in is set to 1 (GPIO function) and the corresponding bit in is set to 1 (output)." bitfld.long 0x0 0. " AXR0 ,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1." "0,1" bitfld.long 0x0 7. " AXR ,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1." "0,1" bitfld.long 0x0 28. " AFSX ,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "0,1" bitfld.long 0x0 30. " AHCLKR ,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1." "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDIN,Pin data input register - holds the state of all the McASP pins. allows reading the actual value of the pin, regardless of the state of and ." bitfld.long 0x0 0. " AXR0 ,Logic level on AXR0 pin" "0,1" bitfld.long 0x0 1. " AXR1 ,Logic level on AXR1 pin" "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Logic level on AXR2 pin" "0,1" bitfld.long 0x0 3. " AXR3 ,Logic level on AXR3 pin" "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Logic level on AXR4 pin" "0,1" bitfld.long 0x0 5. " AXR5 ,Logic level on AXR5 pin" "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Logic level on AXR6 pin" "0,1" bitfld.long 0x0 7. " AXR7 ,Logic level on AXR7 pin" "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Logic level on AXR8 pin" "0,1" bitfld.long 0x0 9. " AXR9 ,Logic level on AXR9 pin" "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Logic level on AXR10 pin" "0,1" bitfld.long 0x0 11. " AXR11 ,Logic level on AXR11 pin" "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Logic level on AXR12 pin" "0,1" bitfld.long 0x0 13. " AXR13 ,Logic level on AXR13 pin" "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Logic level on AXR14 pin" "0,1" bitfld.long 0x0 15. " AXR15 ,Logic level on AXR15 pin" "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Logic level on ACLKX pin" "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Logic level on AHCLKX pin" "0,1" bitfld.long 0x0 28. " AFSX ,Logic level on AFSX pin" "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Logic level on ACLKR pin" "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Logic level on AFSR pin" "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only. Writing a 1 to the bit sets the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic high on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x20++0x3 line.long 0x0 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only. Writing a 1 to the bit clears the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic low on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x44++0x3 line.long 0x0 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections. The bit fields in are synchronized and latched by the transmitter and receiver corresponding clocks - ACLKX (bits [12:8]) and ACLKR (bits [4:0]), respectively. Before programming , ensure that the serial clocks are running. If the corresponding external serial clocks - ACLKX and ACLKR, are not yet running, select the internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL and ACLKRCTL before programming the . Also, after programming any bits in , do not proceed until reading back from and verifying that the bits in are latched." bitfld.long 0x0 0. " RCLKRST ,Receive clock divider reset enable bit." "0,1" bitfld.long 0x0 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit." "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed." "0,1" bitfld.long 0x0 3. " RSMRST ,Receive state machine reset enable bit." "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,Transmit clock divider reset enable bit" "0,1" bitfld.long 0x0 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,Transmit serializer clear enable bit. By clearing and then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the next active time slot, an underrun occurs." "0,1" bitfld.long 0x0 11. " XSMRST ,Transmit state-machine reset enable bitAXR[n] pin state: If[n] = 0 and [n] = 1, the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot. ." "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Transmit frame-sync generator reset enable bit" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "MCASP_AMUTE,Mute control register - Controls the McASP mute output pin - AMUTE (Not implemented at device level)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "MCASP_LBCTL,The digital loopback control register () controls the internal (McASP module)- level and chip-level loopback settings of the McASP in TDM mode. Note that loopback is NOT supported if McASP is configured in DIT mode." bitfld.long 0x0 0. " DLBEN ,Loop back mode enable bit." "0,1" bitfld.long 0x0 1. " ORD ,Loopback order bit when loopback mode is enabled (DLBEN = 1)." "0,1" textline " " bitfld.long 0x0 2.--3. " MODE ,Loopback generator mode bits.0x2, 0x3: Reserved enum=RESERVED ." "0,1,2,3" bitfld.long 0x0 4. " IOLBEN ,If DLBEN=0b1, the IOLBEN bit selects betweeninternal-level (McASP module-level) and chip I/O-level loopback modes. IOLBEN bit value is irrelevant, If DLBEN=0b0." "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "MCASP_TXDITCTL,Transmit DIT mode control register, controls DIT operations of the McASP" bitfld.long 0x0 0. " DITEN ,DIT mode enable bit" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " VA ,Valid bit for even time slots (DIT left subframe)." "0,1" bitfld.long 0x0 3. " VB ,Valid bit for odd time slots (DIT right subframe)." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "MCASP_GBLCTLR,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12). Reads return GBLCTL" bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU." hexmask.long 0x0 0.--31. 1. " RMASK_31_0 ,Receive data mask enable bit." group.byte 0x68++0x3 line.long 0x0 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format." bitfld.long 0x0 0.--2. " RROT ,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RBUSEL ,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " RSSZ ,Receive slot size.0x0 - 0x2: Reserved enum=RSVD ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " RPBIT ,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits. This field only applies when RPAD = 2h.0x01 - 0x1F: Pad with value of the bit positioned within the range RBUFn[31:1]. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " RRVRS ,Receive serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " RDATDLY ,Receive Frame sync delay of AXR[n]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)." bitfld.long 0x0 0. " FSRP ,Receive frame sync polarity select bit." "0,1" bitfld.long 0x0 1. " FSRM ,Receive frame sync generation select bit." "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " FRWID ,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " RMOD ,Receive frame sync mode select bits.0x3 - 0x20: 3-slot TDM to 32-slot TDM mode . 0x21 - 0x17F: Reserved . 0x181 - 0x1FF: Reserved ." textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator." bitfld.long 0x0 0.--4. " CLKRDIV ,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0.0x2 - 0x1F: Divide-by-3 to divide-by-32 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKRM ,Receive bit clock source bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " CLKRP ,Receive bitstream clock polarity select bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKRADJ ,CLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0.If CLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR.0x2 - 0xFFF: Divide-by-3 to divide-by-4096 ." bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKRM ,High Freq. RCV clock Source" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKRADJ ,HCLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active." hexmask.long 0x0 0.--31. 1. " RTDMS_31_0 ,Receiver mode during TDM time slot n." group.byte 0x7C++0x3 line.long 0x0 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the McASP receive interrupt (RINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP condition(s) generates RINT." bitfld.long 0x0 0. " ROVRN ,Receiver overrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " RDMAERR ,Receive DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " RDATA ,Receive data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " RSTAFRM ,Receive start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number." bitfld.long 0x0 0. " ROVRN ,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync (AFSR) occurs before it is expected. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 3. " RTDMSLOT ,Returns the LSB of RSLOT. Allows a single read ofMCASP_RXSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 5. " RDATA ,Receive data ready flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " RSTAFRM ,Receive start of frame flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 7. " RDMAERR ,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the DMA port in a given time slot than were programmed as receivers. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 8. " RERR ,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame." hexmask.long.word 0x0 0.--8. 1. " RSLOTCNT ,0x0 - 0x17F: Current receive time slot count. Legal values: 0 to 383 (17Fh). TDM function is not supported for > 32 time slots. However, TDM time slot counter may count to 383 when used to receive a DIR block (transferred over TDM format)." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." bitfld.long 0x0 0.--3. " RPS ,Receive clock check prescaler value.0x9 - 0xF: Reserved enum=DIVBY8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " RMIN ,0x00 - 0xFF: Receive clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If RCNT is less than RMIN after counting 32 AHCLKR signals, RCKFAIL in RSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " RMAX ,0x00-0xFF: Receive clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If the current counter value is greater than RMAX after counting 32 AHCLKR signals, RCKFAIL inMCASP_RXSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " RCNT ,0x0 - 0xFF: Receive clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 receive high-frequency master clock (AHCLKR) signals, and stores the count in RCNT until the next measurement is taken." group.byte 0x8C++0x3 line.long 0x0 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x0 0. " RDATDMA ,Receive data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MCASP_GBLCTLX,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12.). Reads return GBLCTL." bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLKR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the McASP" hexmask.long 0x0 0.--31. 1. " XMASK_31_0 ,Transmit data mask enable bit" group.byte 0xA8++0x3 line.long 0x0 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x0 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " XBUSEL ,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " XSSZ ,Transmit slot size0x0 - 0x2: Reserved enum=RSV8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " XPBIT ,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting. This field only applies when XPAD = 0x2.0x1 - 0x1F: Pad with bit 1 to bit 31 value. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " XRVRS ,Transmit serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " XDATDLY ,Transmit sync bit delay" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xAC++0x3 line.long 0x0 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (AFSX)." bitfld.long 0x0 0. " FSXP ,Transmit frame-sync polarity select bit" "0,1" bitfld.long 0x0 1. " FSXM ,Transmit frame-sync generation select bit" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4. " FXWID ,The transmit frame-sync width select bit indicates the width of the transmit frame sync (AFSX) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " XMOD ,Transmit frame-sync mode select bits 0x0: Burst mode 0x1: Reserved 0x2: 2-slot TDM mode (I2S transmit mode) 0x3 - 0x20: 3-slot TDM to 32-slot TDM mode 0x21 - 0x17F: Reserved 0x180: 384-slot DIT mode All other: Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (ACLKX) and the transmit clock generator." bitfld.long 0x0 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits, determine the divide-down ratio from AHCLKX to ACLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0x1F: Divide-by-3 to divide-by-32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKXM ,Transmit bit clock source bit" "0,1" textline " " bitfld.long 0x0 6. " ASYNC ,Transmit operation asynchronous enable bit" "0,1" bitfld.long 0x0 7. " CLKXP ,Transmit bitstream clock polarity select bit." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKXADJ ,CLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If CLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB4++0x3 line.long 0x0 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0xFFF: Divide-by-3 to divide-by-4096" bitfld.long 0x0 12.--13. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKXM ,Transmit high-frequency clock source bit" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKXADJ ,HCLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB8++0x3 line.long 0x0 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)." hexmask.long 0x0 0.--31. 1. " XTDMS_31_0 ,Transmitter mode during TDM time slot n (n = 0..31)" group.byte 0xBC++0x3 line.long 0x0 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the McASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled McASP condition(s) generates XINT." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " XDMAERR ,Transmit DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " XSTAFRM ,Transmit start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "MCASP_TXSTAT,Transmitter status register - If the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the McASP logic has priority and the flag remains set. This also causes the generation of a new interrupt request." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF[n] to XRSR[n], but XBUF[n] has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT) if this bit and XUNDRN inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT) if this bit and XSYNCERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt (XINT) if this bit and XCKFAIL inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 3. " XTDMSLOT ,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot flag. XLAST, along with XDATA, are set if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT) if this bit and XLAST inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data ready flag. Causes a transmit interrupt (XINT) if this bit and XDATA inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " XSTAFRM ,Transmit start of frame flag. Causes a transmit interrupt (XINT) if this bit and XSTAFRM inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" bitfld.long 0x0 7. " XDMAERR ,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more words to the DATA port of the McASP in a given time slot than it should. Causes a transmit interrupt (XINT) if this bit and XDMAERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 8. " XERR ,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x0 0.--8. 1. " XSLOTCNT ,Current transmit time slot count. the value of this register is 0b0101111111 (0x17f) during reset and 0 after reset." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit." bitfld.long 0x0 0.--3. " XPS ,Transmit clock check prescaler value 0x0: McASP interface clock divided by 1 0x1: McASP interface clock divided by 2 0x2: McASP interface clock divided by 4 0x3: McASP interface clock divided by 8 0x4: McASP interface clock divided by 16 0x5: McASP interface clock divided by 32 0x6: McASP interface clock divided by 64 0x7: McASP interface clock divided by 128 0x8: McASP interface clock divided by 256 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " XMIN ,0x0 to 0xFF: Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (AHCLKX) signals have been received. If XCNT is less than XMIN after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " XMAX ,0x0 to 0xFF: Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (AHCLKX) signals have been received. If the current counter value is greater than XMAX after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " XCNT ,Transmit clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 transmit high-frequency master clock (AHCLKX) signals, and stores the count in XCNT until the next measurement is taken" group.byte 0xCC++0x3 line.long 0x0 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x0 0. " XDATDMA ,Transmit data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD0++0x3 line.long 0x0 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x0 0. " ENABLE ,One-shot clock adjust enable. Not supported. Bit field must always be written as 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x104++0x3 line.long 0x0 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x108++0x3 line.long 0x0 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x10C++0x3 line.long 0x0 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x110++0x3 line.long 0x0 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x114++0x3 line.long 0x0 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x118++0x3 line.long 0x0 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x11C++0x3 line.long 0x0 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x120++0x3 line.long 0x0 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x124++0x3 line.long 0x0 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x128++0x3 line.long 0x0 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x12C++0x3 line.long 0x0 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x130++0x3 line.long 0x0 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x134++0x3 line.long 0x0 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x138++0x3 line.long 0x0 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x13C++0x3 line.long 0x0 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x140++0x3 line.long 0x0 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x144++0x3 line.long 0x0 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x148++0x3 line.long 0x0 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x14C++0x3 line.long 0x0 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x150++0x3 line.long 0x0 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x154++0x3 line.long 0x0 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x158++0x3 line.long 0x0 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x15C++0x3 line.long 0x0 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x180++0x3 line.long 0x0 "MCASP_XRSRCTLn_0,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "MCASP_XRSRCTLn_1,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "MCASP_XRSRCTLn_2,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "MCASP_XRSRCTLn_3,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "MCASP_XRSRCTLn_4,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x194++0x3 line.long 0x0 "MCASP_XRSRCTLn_5,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x198++0x3 line.long 0x0 "MCASP_XRSRCTLn_6,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x19C++0x3 line.long 0x0 "MCASP_XRSRCTLn_7,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1A0++0x3 line.long 0x0 "MCASP_XRSRCTLn_8,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1A4++0x3 line.long 0x0 "MCASP_XRSRCTLn_9,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1A8++0x3 line.long 0x0 "MCASP_XRSRCTLn_10,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1AC++0x3 line.long 0x0 "MCASP_XRSRCTLn_11,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1B0++0x3 line.long 0x0 "MCASP_XRSRCTLn_12,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1B4++0x3 line.long 0x0 "MCASP_XRSRCTLn_13,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1B8++0x3 line.long 0x0 "MCASP_XRSRCTLn_14,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x1BC++0x3 line.long 0x0 "MCASP_XRSRCTLn_15,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a McASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x204++0x3 line.long 0x0 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x208++0x3 line.long 0x0 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x20C++0x3 line.long 0x0 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x210++0x3 line.long 0x0 "MCASP_TXBUFn_4,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x214++0x3 line.long 0x0 "MCASP_TXBUFn_5,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x218++0x3 line.long 0x0 "MCASP_TXBUFn_6,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x21C++0x3 line.long 0x0 "MCASP_TXBUFn_7,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x220++0x3 line.long 0x0 "MCASP_TXBUFn_8,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x224++0x3 line.long 0x0 "MCASP_TXBUFn_9,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x228++0x3 line.long 0x0 "MCASP_TXBUFn_10,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x22C++0x3 line.long 0x0 "MCASP_TXBUFn_11,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x230++0x3 line.long 0x0 "MCASP_TXBUFn_12,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x234++0x3 line.long 0x0 "MCASP_TXBUFn_13,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x238++0x3 line.long 0x0 "MCASP_TXBUFn_14,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x23C++0x3 line.long 0x0 "MCASP_TXBUFn_15,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x280++0x3 line.long 0x0 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x284++0x3 line.long 0x0 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x288++0x3 line.long 0x0 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x28C++0x3 line.long 0x0 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x290++0x3 line.long 0x0 "MCASP_RXBUFn_4,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x294++0x3 line.long 0x0 "MCASP_RXBUFn_5,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x298++0x3 line.long 0x0 "MCASP_RXBUFn_6,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x29C++0x3 line.long 0x0 "MCASP_RXBUFn_7,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2A0++0x3 line.long 0x0 "MCASP_RXBUFn_8,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2A4++0x3 line.long 0x0 "MCASP_RXBUFn_9,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2A8++0x3 line.long 0x0 "MCASP_RXBUFn_10,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2AC++0x3 line.long 0x0 "MCASP_RXBUFn_11,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2B0++0x3 line.long 0x0 "MCASP_RXBUFn_12,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2B4++0x3 line.long 0x0 "MCASP_RXBUFn_13,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2B8++0x3 line.long 0x0 "MCASP_RXBUFn_14,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x2BC++0x3 line.long 0x0 "MCASP_RXBUFn_15,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" width 0x0B tree.end tree "MCASP1_DAT" base ad:0x45800000 width 13. group.byte 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For receive operations through the DATA port, the Host should read from the same RBUF DATA port address to service all of the active receive serializers upon each receive data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the RBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " RXBUF ,Rx buffer data." group.byte 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port, the Host should write to the same DATA port address to service all of the active transmit serializers upon each transmit data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the XBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " TXBUF ,Tx buffer data." width 0x0B tree.end tree "MCASP2_DAT" base ad:0x45C00000 width 13. group.byte 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For receive operations through the DATA port, the Host should read from the same RBUF DATA port address to service all of the active receive serializers upon each receive data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the RBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " RXBUF ,Rx buffer data." group.byte 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port, the Host should write to the same DATA port address to service all of the active transmit serializers upon each transmit data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the XBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " TXBUF ,Tx buffer data." width 0x0B tree.end tree "MCASP3_DAT" base ad:0x46000000 width 13. group.byte 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For receive operations through the DATA port, the Host should read from the same RBUF DATA port address to service all of the active receive serializers upon each receive data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the RBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " RXBUF ,Rx buffer data." group.byte 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port, the Host should write to the same DATA port address to service all of the active transmit serializers upon each transmit data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the XBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " TXBUF ,Tx buffer data." width 0x0B tree.end tree "MCASP4_DAT" base ad:0x48436000 width 13. group.byte 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For receive operations through the DATA port, the Host should read from the same RBUF DATA port address to service all of the active receive serializers upon each receive data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the RBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " RXBUF ,Rx buffer data." group.byte 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port, the Host should write to the same DATA port address to service all of the active transmit serializers upon each transmit data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the XBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " TXBUF ,Tx buffer data." width 0x0B tree.end tree "MCASP5_DAT" base ad:0x4843A000 width 13. group.byte 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For receive operations through the DATA port, the Host should read from the same RBUF DATA port address to service all of the active receive serializers upon each receive data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the RBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " RXBUF ,Rx buffer data." group.byte 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port, the Host should write to the same DATA port address to service all of the active transmit serializers upon each transmit data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the XBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " TXBUF ,Tx buffer data." width 0x0B tree.end tree "MCASP6_DAT" base ad:0x4844C000 width 13. group.byte 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For receive operations through the DATA port, the Host should read from the same RBUF DATA port address to service all of the active receive serializers upon each receive data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the RBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " RXBUF ,Rx buffer data." group.byte 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port, the Host should write to the same DATA port address to service all of the active transmit serializers upon each transmit data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the XBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " TXBUF ,Tx buffer data." width 0x0B tree.end tree "MCASP7_DAT" base ad:0x48450000 width 13. group.byte 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For receive operations through the DATA port, the Host should read from the same RBUF DATA port address to service all of the active receive serializers upon each receive data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the RBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " RXBUF ,Rx buffer data." group.byte 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port, the Host should write to the same DATA port address to service all of the active transmit serializers upon each transmit data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the XBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " TXBUF ,Tx buffer data." width 0x0B tree.end tree "MCASP8_DAT" base ad:0x48454000 width 13. group.byte 0x0++0x3 line.long 0x0 "MCASP_RXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For receive operations through the DATA port, the Host should read from the same RBUF DATA port address to service all of the active receive serializers upon each receive data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the RBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " RXBUF ,Rx buffer data." group.byte 0x0++0x3 line.long 0x0 "MCASP_TXBUF,Through the DATA port, the Host can service all serializers through a single address and the McASP automatically cycles through the appropriate serializers. For transmit operations through the DATA port, the Host should write to the same DATA port address to service all of the active transmit serializers upon each transmit data ready event. To enable accesses from the Host to the McASP XRBUF registers through the DATA port, one must clear the XBUSEL bits to 0 in the respective registers in the MCASP_CFG Memory Map." hexmask.long 0x0 0.--31. 1. " TXBUF ,Tx buffer data." width 0x0B tree.end tree "MCASP3_CFG" base ad:0x48468000 width 18. group.byte 0x0++0x3 line.long 0x0 "MCASP_PID,Peripheral identification register" bitfld.long 0x0 0.--5. " REVMINOR ,Minor revision number." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Non-custom. Indicates a special version for a given device." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " REVMAJOR ,Major revision number." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNCTION ,MCASP. Indicates a software-compatible module family." bitfld.long 0x0 28.--29. " RESV ,Reserved." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,Scheme. Distinguishes between old scheme and current." "0,1,2,3" group.byte 0x4++0x3 line.long 0x0 "PWRIDLESYSCONFIG,Power idle module configuration register." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode - default state 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 2.--5. " OTHER ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO." "0,1" group.byte 0x14++0x3 line.long 0x0 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin." bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output." "0,1" group.byte 0x18++0x3 line.long 0x0 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times, and may be read back at all times. The value held by is not affected by writing to and . However, the data value in is driven out onto the MCASP pin only if the corresponding bit in is set to 1 (GPIO function) and the corresponding bit in is set to 1 (output)." bitfld.long 0x0 0. " AXR0 ,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1." "0,1" bitfld.long 0x0 28. " AFSX ,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "0,1" bitfld.long 0x0 30. " AHCLKR ,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1." "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins. allows reading the actual value of the pin, regardless of the state of and ." bitfld.long 0x0 0. " AXR0 ,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)." "0,1" bitfld.long 0x0 1. " AXR1 ,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)." "0,1" bitfld.long 0x0 3. " AXR3 ,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)." "0,1" bitfld.long 0x0 5. " AXR5 ,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)." "0,1" bitfld.long 0x0 7. " AXR7 ,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)." "0,1" bitfld.long 0x0 9. " AXR9 ,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)." "0,1" bitfld.long 0x0 11. " AXR11 ,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)." "0,1" bitfld.long 0x0 13. " AXR13 ,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)." "0,1" bitfld.long 0x0 15. " AXR15 ,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)." "0,1" bitfld.long 0x0 28. " AFSX ,Logic level on AFSX pin (device level: mcaspi_fsx signal)." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Logic level on AFSR pin (device level: mcaspi_fsr signal)." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only. Writing a 1 to the bit sets the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic high on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x20++0x3 line.long 0x0 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only. Writing a 1 to the bit clears the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic low on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x44++0x3 line.long 0x0 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections. The bit fields in are synchronized and latched by the transmitter and receiver corresponding clocks - mcaspi_aclkx clock ( bits [12:8] ) and mcaspi_aclkr ( bits [4:0] ), respectively. Before programming , ensure that the serial clocks are running. If the corresponding external serial clocks - mcaspi_aclkx and mcaspi_aclkr, are not yet running, select the internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL and ACLKRCTL before programming the . Also, after programming any bits in , do not proceed until reading back from and verifying that the bits in are latched." bitfld.long 0x0 0. " RCLKRST ,Receive clock divider reset enable bit." "0,1" bitfld.long 0x0 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit." "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed." "0,1" bitfld.long 0x0 3. " RSMRST ,Receive state machine reset enable bit." "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,Transmit clock divider reset enable bit" "0,1" bitfld.long 0x0 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,Transmit serializer clear enable bit. By clearing and then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the next active time slot, an underrun occurs." "0,1" bitfld.long 0x0 11. " XSMRST ,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1, the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot. ." "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Transmit frame-sync generator reset enable bit" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode. Note that loopback is NOT supported if MCASP is configured in DIT mode." bitfld.long 0x0 0. " DLBEN ,Loop back mode enable bit." "0,1" bitfld.long 0x0 1. " ORD ,Loopback order bit when loopback mode is enabled (DLBEN = 1)." "0,1" textline " " bitfld.long 0x0 2.--3. " MODE ,Loopback generator mode bits.0x2, 0x3: Reserved enum=RESERVED ." "0,1,2,3" bitfld.long 0x0 4. " IOLBEN ,If DLBEN=0b1, the IOLBEN bit selects between and loopback modes. IOLBEN bit value is irrelevant, If DLBEN=0b0." "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "MCASP_TXDITCTL,Transmit DIT mode control register, controls DIT operations of the MCASP" bitfld.long 0x0 0. " DITEN ,DIT mode enable bit" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " VA ,Valid bit for even time slots (DIT left subframe)." "0,1" bitfld.long 0x0 3. " VB ,Valid bit for odd time slots (DIT right subframe)." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "MCASP_GBLCTLR,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12). Reads return GBLCTL" bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU." hexmask.long 0x0 0.--31. 1. " RMASK_31_0 ,Receive data mask enable bit." group.byte 0x68++0x3 line.long 0x0 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format." bitfld.long 0x0 0.--2. " RROT ,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RBUSEL ,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " RSSZ ,Receive slot size.0x0 - 0x2 : Reserved enum=RSVD ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " RPBIT ,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits. This field only applies when RPAD = 2h.0x01 - 0x1F: Pad with value of the bit positioned within the range RBUFn[31:1]. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " RRVRS ,Receive serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " RDATDLY ,Receive Frame sync delay of AXR[n]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)." bitfld.long 0x0 0. " FSRP ,Receive frame sync polarity select bit." "0,1" bitfld.long 0x0 1. " FSRM ,Receive frame sync generation select bit." "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " FRWID ,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " RMOD ,Receive frame sync mode select bits.0x3 - 0x20: 3-slot TDM to 32-slot TDM mode . 0x21 - 0x17F: Reserved . 0x181 - 0x1FF: Reserved ." textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator." bitfld.long 0x0 0.--4. " CLKRDIV ,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0.0x2 - 0x1F: Divide-by-3 to divide-by-32 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKRM ,Receive bit clock source bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " CLKRP ,Receive bitstream clock polarity select bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKRADJ ,CLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0.If CLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR.0x2 - 0xFFF: Divide-by-3 to divide-by-4096 ." bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKRM ,High Freq. RCV clock Source" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKRADJ ,HCLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active." hexmask.long 0x0 0.--31. 1. " RTDMS_31_0 ,Receiver mode during TDM time slot n." group.byte 0x7C++0x3 line.long 0x0 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates RINT." bitfld.long 0x0 0. " ROVRN ,Receiver overrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " RDMAERR ,Receive DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " RDATA ,Receive data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " RSTAFRM ,Receive start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number." bitfld.long 0x0 0. " ROVRN ,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync (AFSR) occurs before it is expected. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 3. " RTDMSLOT ,Returns the LSB of RSLOT. Allows a single read ofMCASP_RXSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 5. " RDATA ,Receive data ready flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " RSTAFRM ,Receive start of frame flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 7. " RDMAERR ,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the DMA port in a given time slot than were programmed as receivers. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 8. " RERR ,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame." hexmask.long.word 0x0 0.--8. 1. " RSLOTCNT ,0x0 - 0x17F: Current receive time slot count. Legal values: 0 to 383 (17Fh). TDM function is not supported for > 32 time slots. However, TDM time slot counter may count to 383 when used to receive a DIR block (transferred over TDM format)." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." bitfld.long 0x0 0.--3. " RPS ,Receive clock check prescaler value.0x9 - 0xF: Reserved enum=DIVBY8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " RMIN ,0x00 - 0xFF: Receive clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If RCNT is less than RMIN after counting 32 AHCLKR signals, RCKFAIL in RSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " RMAX ,0x00-0xFF: Receive clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If the current counter value is greater than RMAX after counting 32 AHCLKR signals, RCKFAIL inMCASP_RXSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " RCNT ,0x0 - 0xFF: Receive clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 receive high-frequency master clock (AHCLKR) signals, and stores the count in RCNT until the next measurement is taken." group.byte 0x8C++0x3 line.long 0x0 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x0 0. " RDATDMA ,Receive data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MCASP_GBLCTLX,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12.). Reads return GBLCTL." bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLKR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" hexmask.long 0x0 0.--31. 1. " XMASK_31_0 ,Transmit data mask enable bit" group.byte 0xA8++0x3 line.long 0x0 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x0 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " XBUSEL ,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " XSSZ ,Transmit slot size0x0 - 0x2 : Reserved enum=RSV8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " XPBIT ,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting. This field only applies when XPAD = 0x2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " XRVRS ,Transmit serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " XDATDLY ,Transmit sync bit delay" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xAC++0x3 line.long 0x0 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)." bitfld.long 0x0 0. " FSXP ,Transmit frame-sync polarity select bit" "0,1" bitfld.long 0x0 1. " FSXM ,Transmit frame-sync generation select bit" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4. " FXWID ,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " XMOD ,Transmit frame-sync mode select bits 0x0: Burst mode 0x1: Reserved 0x2: 2-slot TDM mode () 0x3 - 0x20: 3-slot TDM to 32-slot TDM mode 0x21 - 0x17F: Reserved 0x180: 384-slot DIT mode All other: Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator." bitfld.long 0x0 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits, determine the divide-down ratio from AHCLKX to ACLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0x1F: Divide-by-3 to divide-by-32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKXM ,Transmit bit clock source bit" "0,1" textline " " bitfld.long 0x0 6. " ASYNC ,Transmit operation asynchronous enable bit" "0,1" bitfld.long 0x0 7. " CLKXP ,Transmit bitstream clock polarity select bit." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKXADJ ,CLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If CLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB4++0x3 line.long 0x0 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0xFFF: Divide-by-3 to divide-by-4096" bitfld.long 0x0 12.--13. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKXM ,Transmit high-frequency clock source bit" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKXADJ ,HCLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB8++0x3 line.long 0x0 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)." hexmask.long 0x0 0.--31. 1. " XTDMS_31_0 ,Transmitter mode during TDM time slot n (n = 0..31)" group.byte 0xBC++0x3 line.long 0x0 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates XINT." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " XDMAERR ,Transmit DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " XSTAFRM ,Transmit start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the MCASP logic has priority and the flag remains set. This also causes the generation of a new interrupt request." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF[n] to XRSR[n], but XBUF[n] has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT) if this bit and XUNDRN inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT) if this bit and XSYNCERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt (XINT) if this bit and XCKFAIL inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 3. " XTDMSLOT ,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot flag. XLAST, along with XDATA, are set if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT) if this bit and XLAST inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data ready flag. Causes a transmit interrupt (XINT) if this bit and XDATA inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " XSTAFRM ,Transmit start of frame flag. Causes a transmit interrupt (XINT) if this bit and XSTAFRM inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" bitfld.long 0x0 7. " XDMAERR ,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more words to the DATA port of the MCASP in a given time slot than it should. Causes a transmit interrupt (XINT) if this bit and XDMAERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 8. " XERR ,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x0 0.--8. 1. " XSLOTCNT ,Current transmit time slot count. the value of this register is 0b0101111111 (0x17f) during reset and 0 after reset." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit." bitfld.long 0x0 0.--3. " XPS ,Transmit clock check prescaler value 0x0: MCASP interface clock divided by 1 0x1: MCASP interface clock divided by 2 0x2: MCASP interface clock divided by 4 0x3: MCASP interface clock divided by 8 0x4: MCASP interface clock divided by 16 0x5: MCASP interface clock divided by 32 0x6: MCASP interface clock divided by 64 0x7: MCASP interface clock divided by 128 0x8: MCASP interface clock divided by 256 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " XMIN ,0x0 to 0xFF: Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If XCNT is less than XMIN after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " XMAX ,0x0 to 0xFF: Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If the current counter value is greater than XMAX after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " XCNT ,Transmit clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 transmit high-frequency master clock (mcaspi_ahclkx) signals, and stores the count in XCNT until the next measurement is taken" group.byte 0xCC++0x3 line.long 0x0 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x0 0. " XDATDMA ,Transmit data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD0++0x3 line.long 0x0 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x0 0. " ENABLE ,One-shot clock adjust enable. Not supported. Bit field must always be written as 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x104++0x3 line.long 0x0 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x108++0x3 line.long 0x0 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x10C++0x3 line.long 0x0 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x110++0x3 line.long 0x0 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x114++0x3 line.long 0x0 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x118++0x3 line.long 0x0 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x11C++0x3 line.long 0x0 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x120++0x3 line.long 0x0 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x124++0x3 line.long 0x0 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x128++0x3 line.long 0x0 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x12C++0x3 line.long 0x0 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x130++0x3 line.long 0x0 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x134++0x3 line.long 0x0 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x138++0x3 line.long 0x0 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x13C++0x3 line.long 0x0 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x140++0x3 line.long 0x0 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x144++0x3 line.long 0x0 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x148++0x3 line.long 0x0 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x14C++0x3 line.long 0x0 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x150++0x3 line.long 0x0 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x154++0x3 line.long 0x0 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x158++0x3 line.long 0x0 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x15C++0x3 line.long 0x0 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x180++0x3 line.long 0x0 "MCASP_XRSRCTLn_0,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "MCASP_XRSRCTLn_1,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "MCASP_XRSRCTLn_2,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "MCASP_XRSRCTLn_3,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x204++0x3 line.long 0x0 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x208++0x3 line.long 0x0 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x20C++0x3 line.long 0x0 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x280++0x3 line.long 0x0 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x284++0x3 line.long 0x0 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x288++0x3 line.long 0x0 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x28C++0x3 line.long 0x0 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" width 0x0B tree.end tree "MCASP4_CFG" base ad:0x4846C000 width 18. group.byte 0x0++0x3 line.long 0x0 "MCASP_PID,Peripheral identification register" bitfld.long 0x0 0.--5. " REVMINOR ,Minor revision number." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Non-custom. Indicates a special version for a given device." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " REVMAJOR ,Major revision number." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNCTION ,MCASP. Indicates a software-compatible module family." bitfld.long 0x0 28.--29. " RESV ,Reserved." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,Scheme. Distinguishes between old scheme and current." "0,1,2,3" group.byte 0x4++0x3 line.long 0x0 "PWRIDLESYSCONFIG,Power idle module configuration register." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode - default state 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 2.--5. " OTHER ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO." "0,1" group.byte 0x14++0x3 line.long 0x0 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin." bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output." "0,1" group.byte 0x18++0x3 line.long 0x0 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times, and may be read back at all times. The value held by is not affected by writing to and . However, the data value in is driven out onto the MCASP pin only if the corresponding bit in is set to 1 (GPIO function) and the corresponding bit in is set to 1 (output)." bitfld.long 0x0 0. " AXR0 ,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1." "0,1" bitfld.long 0x0 28. " AFSX ,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "0,1" bitfld.long 0x0 30. " AHCLKR ,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1." "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins. allows reading the actual value of the pin, regardless of the state of and ." bitfld.long 0x0 0. " AXR0 ,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)." "0,1" bitfld.long 0x0 1. " AXR1 ,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)." "0,1" bitfld.long 0x0 3. " AXR3 ,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)." "0,1" bitfld.long 0x0 5. " AXR5 ,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)." "0,1" bitfld.long 0x0 7. " AXR7 ,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)." "0,1" bitfld.long 0x0 9. " AXR9 ,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)." "0,1" bitfld.long 0x0 11. " AXR11 ,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)." "0,1" bitfld.long 0x0 13. " AXR13 ,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)." "0,1" bitfld.long 0x0 15. " AXR15 ,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)." "0,1" bitfld.long 0x0 28. " AFSX ,Logic level on AFSX pin (device level: mcaspi_fsx signal)." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Logic level on AFSR pin (device level: mcaspi_fsr signal)." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only. Writing a 1 to the bit sets the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic high on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x20++0x3 line.long 0x0 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only. Writing a 1 to the bit clears the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic low on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x44++0x3 line.long 0x0 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections. The bit fields in are synchronized and latched by the transmitter and receiver corresponding clocks - mcaspi_aclkx clock ( bits [12:8] ) and mcaspi_aclkr ( bits [4:0] ), respectively. Before programming , ensure that the serial clocks are running. If the corresponding external serial clocks - mcaspi_aclkx and mcaspi_aclkr, are not yet running, select the internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL and ACLKRCTL before programming the . Also, after programming any bits in , do not proceed until reading back from and verifying that the bits in are latched." bitfld.long 0x0 0. " RCLKRST ,Receive clock divider reset enable bit." "0,1" bitfld.long 0x0 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit." "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed." "0,1" bitfld.long 0x0 3. " RSMRST ,Receive state machine reset enable bit." "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,Transmit clock divider reset enable bit" "0,1" bitfld.long 0x0 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,Transmit serializer clear enable bit. By clearing and then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the next active time slot, an underrun occurs." "0,1" bitfld.long 0x0 11. " XSMRST ,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1, the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot. ." "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Transmit frame-sync generator reset enable bit" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode. Note that loopback is NOT supported if MCASP is configured in DIT mode." bitfld.long 0x0 0. " DLBEN ,Loop back mode enable bit." "0,1" bitfld.long 0x0 1. " ORD ,Loopback order bit when loopback mode is enabled (DLBEN = 1)." "0,1" textline " " bitfld.long 0x0 2.--3. " MODE ,Loopback generator mode bits.0x2, 0x3: Reserved enum=RESERVED ." "0,1,2,3" bitfld.long 0x0 4. " IOLBEN ,If DLBEN=0b1, the IOLBEN bit selects between and loopback modes. IOLBEN bit value is irrelevant, If DLBEN=0b0." "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "MCASP_TXDITCTL,Transmit DIT mode control register, controls DIT operations of the MCASP" bitfld.long 0x0 0. " DITEN ,DIT mode enable bit" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " VA ,Valid bit for even time slots (DIT left subframe)." "0,1" bitfld.long 0x0 3. " VB ,Valid bit for odd time slots (DIT right subframe)." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "MCASP_GBLCTLR,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12). Reads return GBLCTL" bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU." hexmask.long 0x0 0.--31. 1. " RMASK_31_0 ,Receive data mask enable bit." group.byte 0x68++0x3 line.long 0x0 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format." bitfld.long 0x0 0.--2. " RROT ,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RBUSEL ,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " RSSZ ,Receive slot size.0x0 - 0x2 : Reserved enum=RSVD ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " RPBIT ,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits. This field only applies when RPAD = 2h.0x01 - 0x1F: Pad with value of the bit positioned within the range RBUFn[31:1]. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " RRVRS ,Receive serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " RDATDLY ,Receive Frame sync delay of AXR[n]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)." bitfld.long 0x0 0. " FSRP ,Receive frame sync polarity select bit." "0,1" bitfld.long 0x0 1. " FSRM ,Receive frame sync generation select bit." "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " FRWID ,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " RMOD ,Receive frame sync mode select bits.0x3 - 0x20: 3-slot TDM to 32-slot TDM mode . 0x21 - 0x17F: Reserved . 0x181 - 0x1FF: Reserved ." textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator." bitfld.long 0x0 0.--4. " CLKRDIV ,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0.0x2 - 0x1F: Divide-by-3 to divide-by-32 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKRM ,Receive bit clock source bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " CLKRP ,Receive bitstream clock polarity select bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKRADJ ,CLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0.If CLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR.0x2 - 0xFFF: Divide-by-3 to divide-by-4096 ." bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKRM ,High Freq. RCV clock Source" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKRADJ ,HCLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active." hexmask.long 0x0 0.--31. 1. " RTDMS_31_0 ,Receiver mode during TDM time slot n." group.byte 0x7C++0x3 line.long 0x0 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates RINT." bitfld.long 0x0 0. " ROVRN ,Receiver overrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " RDMAERR ,Receive DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " RDATA ,Receive data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " RSTAFRM ,Receive start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number." bitfld.long 0x0 0. " ROVRN ,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync (AFSR) occurs before it is expected. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 3. " RTDMSLOT ,Returns the LSB of RSLOT. Allows a single read ofMCASP_RXSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 5. " RDATA ,Receive data ready flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " RSTAFRM ,Receive start of frame flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 7. " RDMAERR ,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the DMA port in a given time slot than were programmed as receivers. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 8. " RERR ,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame." hexmask.long.word 0x0 0.--8. 1. " RSLOTCNT ,0x0 - 0x17F: Current receive time slot count. Legal values: 0 to 383 (17Fh). TDM function is not supported for > 32 time slots. However, TDM time slot counter may count to 383 when used to receive a DIR block (transferred over TDM format)." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." bitfld.long 0x0 0.--3. " RPS ,Receive clock check prescaler value.0x9 - 0xF: Reserved enum=DIVBY8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " RMIN ,0x00 - 0xFF: Receive clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If RCNT is less than RMIN after counting 32 AHCLKR signals, RCKFAIL in RSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " RMAX ,0x00-0xFF: Receive clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If the current counter value is greater than RMAX after counting 32 AHCLKR signals, RCKFAIL inMCASP_RXSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " RCNT ,0x0 - 0xFF: Receive clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 receive high-frequency master clock (AHCLKR) signals, and stores the count in RCNT until the next measurement is taken." group.byte 0x8C++0x3 line.long 0x0 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x0 0. " RDATDMA ,Receive data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MCASP_GBLCTLX,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12.). Reads return GBLCTL." bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLKR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" hexmask.long 0x0 0.--31. 1. " XMASK_31_0 ,Transmit data mask enable bit" group.byte 0xA8++0x3 line.long 0x0 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x0 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " XBUSEL ,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " XSSZ ,Transmit slot size0x0 - 0x2 : Reserved enum=RSV8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " XPBIT ,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting. This field only applies when XPAD = 0x2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " XRVRS ,Transmit serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " XDATDLY ,Transmit sync bit delay" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xAC++0x3 line.long 0x0 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)." bitfld.long 0x0 0. " FSXP ,Transmit frame-sync polarity select bit" "0,1" bitfld.long 0x0 1. " FSXM ,Transmit frame-sync generation select bit" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4. " FXWID ,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " XMOD ,Transmit frame-sync mode select bits 0x0: Burst mode 0x1: Reserved 0x2: 2-slot TDM mode () 0x3 - 0x20: 3-slot TDM to 32-slot TDM mode 0x21 - 0x17F: Reserved 0x180: 384-slot DIT mode All other: Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator." bitfld.long 0x0 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits, determine the divide-down ratio from AHCLKX to ACLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0x1F: Divide-by-3 to divide-by-32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKXM ,Transmit bit clock source bit" "0,1" textline " " bitfld.long 0x0 6. " ASYNC ,Transmit operation asynchronous enable bit" "0,1" bitfld.long 0x0 7. " CLKXP ,Transmit bitstream clock polarity select bit." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKXADJ ,CLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If CLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB4++0x3 line.long 0x0 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0xFFF: Divide-by-3 to divide-by-4096" bitfld.long 0x0 12.--13. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKXM ,Transmit high-frequency clock source bit" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKXADJ ,HCLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB8++0x3 line.long 0x0 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)." hexmask.long 0x0 0.--31. 1. " XTDMS_31_0 ,Transmitter mode during TDM time slot n (n = 0..31)" group.byte 0xBC++0x3 line.long 0x0 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates XINT." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " XDMAERR ,Transmit DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " XSTAFRM ,Transmit start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the MCASP logic has priority and the flag remains set. This also causes the generation of a new interrupt request." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF[n] to XRSR[n], but XBUF[n] has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT) if this bit and XUNDRN inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT) if this bit and XSYNCERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt (XINT) if this bit and XCKFAIL inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 3. " XTDMSLOT ,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot flag. XLAST, along with XDATA, are set if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT) if this bit and XLAST inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data ready flag. Causes a transmit interrupt (XINT) if this bit and XDATA inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " XSTAFRM ,Transmit start of frame flag. Causes a transmit interrupt (XINT) if this bit and XSTAFRM inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" bitfld.long 0x0 7. " XDMAERR ,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more words to the DATA port of the MCASP in a given time slot than it should. Causes a transmit interrupt (XINT) if this bit and XDMAERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 8. " XERR ,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x0 0.--8. 1. " XSLOTCNT ,Current transmit time slot count. the value of this register is 0b0101111111 (0x17f) during reset and 0 after reset." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit." bitfld.long 0x0 0.--3. " XPS ,Transmit clock check prescaler value 0x0: MCASP interface clock divided by 1 0x1: MCASP interface clock divided by 2 0x2: MCASP interface clock divided by 4 0x3: MCASP interface clock divided by 8 0x4: MCASP interface clock divided by 16 0x5: MCASP interface clock divided by 32 0x6: MCASP interface clock divided by 64 0x7: MCASP interface clock divided by 128 0x8: MCASP interface clock divided by 256 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " XMIN ,0x0 to 0xFF: Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If XCNT is less than XMIN after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " XMAX ,0x0 to 0xFF: Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If the current counter value is greater than XMAX after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " XCNT ,Transmit clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 transmit high-frequency master clock (mcaspi_ahclkx) signals, and stores the count in XCNT until the next measurement is taken" group.byte 0xCC++0x3 line.long 0x0 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x0 0. " XDATDMA ,Transmit data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD0++0x3 line.long 0x0 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x0 0. " ENABLE ,One-shot clock adjust enable. Not supported. Bit field must always be written as 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x104++0x3 line.long 0x0 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x108++0x3 line.long 0x0 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x10C++0x3 line.long 0x0 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x110++0x3 line.long 0x0 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x114++0x3 line.long 0x0 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x118++0x3 line.long 0x0 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x11C++0x3 line.long 0x0 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x120++0x3 line.long 0x0 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x124++0x3 line.long 0x0 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x128++0x3 line.long 0x0 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x12C++0x3 line.long 0x0 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x130++0x3 line.long 0x0 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x134++0x3 line.long 0x0 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x138++0x3 line.long 0x0 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x13C++0x3 line.long 0x0 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x140++0x3 line.long 0x0 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x144++0x3 line.long 0x0 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x148++0x3 line.long 0x0 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x14C++0x3 line.long 0x0 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x150++0x3 line.long 0x0 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x154++0x3 line.long 0x0 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x158++0x3 line.long 0x0 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x15C++0x3 line.long 0x0 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x180++0x3 line.long 0x0 "MCASP_XRSRCTLn_0,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "MCASP_XRSRCTLn_1,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "MCASP_XRSRCTLn_2,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "MCASP_XRSRCTLn_3,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x204++0x3 line.long 0x0 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x208++0x3 line.long 0x0 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x20C++0x3 line.long 0x0 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x280++0x3 line.long 0x0 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x284++0x3 line.long 0x0 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x288++0x3 line.long 0x0 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x28C++0x3 line.long 0x0 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" width 0x0B tree.end tree "MCASP5_CFG" base ad:0x48470000 width 18. group.byte 0x0++0x3 line.long 0x0 "MCASP_PID,Peripheral identification register" bitfld.long 0x0 0.--5. " REVMINOR ,Minor revision number." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Non-custom. Indicates a special version for a given device." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " REVMAJOR ,Major revision number." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNCTION ,MCASP. Indicates a software-compatible module family." bitfld.long 0x0 28.--29. " RESV ,Reserved." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,Scheme. Distinguishes between old scheme and current." "0,1,2,3" group.byte 0x4++0x3 line.long 0x0 "PWRIDLESYSCONFIG,Power idle module configuration register." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode - default state 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 2.--5. " OTHER ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO." "0,1" group.byte 0x14++0x3 line.long 0x0 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin." bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output." "0,1" group.byte 0x18++0x3 line.long 0x0 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times, and may be read back at all times. The value held by is not affected by writing to and . However, the data value in is driven out onto the MCASP pin only if the corresponding bit in is set to 1 (GPIO function) and the corresponding bit in is set to 1 (output)." bitfld.long 0x0 0. " AXR0 ,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1." "0,1" bitfld.long 0x0 28. " AFSX ,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "0,1" bitfld.long 0x0 30. " AHCLKR ,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1." "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins. allows reading the actual value of the pin, regardless of the state of and ." bitfld.long 0x0 0. " AXR0 ,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)." "0,1" bitfld.long 0x0 1. " AXR1 ,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)." "0,1" bitfld.long 0x0 3. " AXR3 ,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)." "0,1" bitfld.long 0x0 5. " AXR5 ,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)." "0,1" bitfld.long 0x0 7. " AXR7 ,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)." "0,1" bitfld.long 0x0 9. " AXR9 ,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)." "0,1" bitfld.long 0x0 11. " AXR11 ,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)." "0,1" bitfld.long 0x0 13. " AXR13 ,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)." "0,1" bitfld.long 0x0 15. " AXR15 ,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)." "0,1" bitfld.long 0x0 28. " AFSX ,Logic level on AFSX pin (device level: mcaspi_fsx signal)." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Logic level on AFSR pin (device level: mcaspi_fsr signal)." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only. Writing a 1 to the bit sets the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic high on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x20++0x3 line.long 0x0 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only. Writing a 1 to the bit clears the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic low on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x44++0x3 line.long 0x0 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections. The bit fields in are synchronized and latched by the transmitter and receiver corresponding clocks - mcaspi_aclkx clock ( bits [12:8] ) and mcaspi_aclkr ( bits [4:0] ), respectively. Before programming , ensure that the serial clocks are running. If the corresponding external serial clocks - mcaspi_aclkx and mcaspi_aclkr, are not yet running, select the internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL and ACLKRCTL before programming the . Also, after programming any bits in , do not proceed until reading back from and verifying that the bits in are latched." bitfld.long 0x0 0. " RCLKRST ,Receive clock divider reset enable bit." "0,1" bitfld.long 0x0 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit." "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed." "0,1" bitfld.long 0x0 3. " RSMRST ,Receive state machine reset enable bit." "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,Transmit clock divider reset enable bit" "0,1" bitfld.long 0x0 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,Transmit serializer clear enable bit. By clearing and then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the next active time slot, an underrun occurs." "0,1" bitfld.long 0x0 11. " XSMRST ,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1, the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot. ." "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Transmit frame-sync generator reset enable bit" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode. Note that loopback is NOT supported if MCASP is configured in DIT mode." bitfld.long 0x0 0. " DLBEN ,Loop back mode enable bit." "0,1" bitfld.long 0x0 1. " ORD ,Loopback order bit when loopback mode is enabled (DLBEN = 1)." "0,1" textline " " bitfld.long 0x0 2.--3. " MODE ,Loopback generator mode bits.0x2, 0x3: Reserved enum=RESERVED ." "0,1,2,3" bitfld.long 0x0 4. " IOLBEN ,If DLBEN=0b1, the IOLBEN bit selects between and loopback modes. IOLBEN bit value is irrelevant, If DLBEN=0b0." "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "MCASP_TXDITCTL,Transmit DIT mode control register, controls DIT operations of the MCASP" bitfld.long 0x0 0. " DITEN ,DIT mode enable bit" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " VA ,Valid bit for even time slots (DIT left subframe)." "0,1" bitfld.long 0x0 3. " VB ,Valid bit for odd time slots (DIT right subframe)." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "MCASP_GBLCTLR,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12). Reads return GBLCTL" bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU." hexmask.long 0x0 0.--31. 1. " RMASK_31_0 ,Receive data mask enable bit." group.byte 0x68++0x3 line.long 0x0 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format." bitfld.long 0x0 0.--2. " RROT ,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RBUSEL ,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " RSSZ ,Receive slot size.0x0 - 0x2 : Reserved enum=RSVD ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " RPBIT ,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits. This field only applies when RPAD = 2h.0x01 - 0x1F: Pad with value of the bit positioned within the range RBUFn[31:1]. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " RRVRS ,Receive serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " RDATDLY ,Receive Frame sync delay of AXR[n]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)." bitfld.long 0x0 0. " FSRP ,Receive frame sync polarity select bit." "0,1" bitfld.long 0x0 1. " FSRM ,Receive frame sync generation select bit." "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " FRWID ,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " RMOD ,Receive frame sync mode select bits.0x3 - 0x20: 3-slot TDM to 32-slot TDM mode . 0x21 - 0x17F: Reserved . 0x181 - 0x1FF: Reserved ." textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator." bitfld.long 0x0 0.--4. " CLKRDIV ,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0.0x2 - 0x1F: Divide-by-3 to divide-by-32 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKRM ,Receive bit clock source bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " CLKRP ,Receive bitstream clock polarity select bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKRADJ ,CLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0.If CLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR.0x2 - 0xFFF: Divide-by-3 to divide-by-4096 ." bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKRM ,High Freq. RCV clock Source" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKRADJ ,HCLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active." hexmask.long 0x0 0.--31. 1. " RTDMS_31_0 ,Receiver mode during TDM time slot n." group.byte 0x7C++0x3 line.long 0x0 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates RINT." bitfld.long 0x0 0. " ROVRN ,Receiver overrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " RDMAERR ,Receive DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " RDATA ,Receive data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " RSTAFRM ,Receive start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number." bitfld.long 0x0 0. " ROVRN ,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync (AFSR) occurs before it is expected. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 3. " RTDMSLOT ,Returns the LSB of RSLOT. Allows a single read ofMCASP_RXSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 5. " RDATA ,Receive data ready flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " RSTAFRM ,Receive start of frame flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 7. " RDMAERR ,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the DMA port in a given time slot than were programmed as receivers. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 8. " RERR ,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame." hexmask.long.word 0x0 0.--8. 1. " RSLOTCNT ,0x0 - 0x17F: Current receive time slot count. Legal values: 0 to 383 (17Fh). TDM function is not supported for > 32 time slots. However, TDM time slot counter may count to 383 when used to receive a DIR block (transferred over TDM format)." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." bitfld.long 0x0 0.--3. " RPS ,Receive clock check prescaler value.0x9 - 0xF: Reserved enum=DIVBY8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " RMIN ,0x00 - 0xFF: Receive clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If RCNT is less than RMIN after counting 32 AHCLKR signals, RCKFAIL in RSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " RMAX ,0x00-0xFF: Receive clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If the current counter value is greater than RMAX after counting 32 AHCLKR signals, RCKFAIL inMCASP_RXSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " RCNT ,0x0 - 0xFF: Receive clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 receive high-frequency master clock (AHCLKR) signals, and stores the count in RCNT until the next measurement is taken." group.byte 0x8C++0x3 line.long 0x0 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x0 0. " RDATDMA ,Receive data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MCASP_GBLCTLX,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12.). Reads return GBLCTL." bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLKR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" hexmask.long 0x0 0.--31. 1. " XMASK_31_0 ,Transmit data mask enable bit" group.byte 0xA8++0x3 line.long 0x0 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x0 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " XBUSEL ,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " XSSZ ,Transmit slot size0x0 - 0x2 : Reserved enum=RSV8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " XPBIT ,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting. This field only applies when XPAD = 0x2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " XRVRS ,Transmit serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " XDATDLY ,Transmit sync bit delay" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xAC++0x3 line.long 0x0 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)." bitfld.long 0x0 0. " FSXP ,Transmit frame-sync polarity select bit" "0,1" bitfld.long 0x0 1. " FSXM ,Transmit frame-sync generation select bit" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4. " FXWID ,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " XMOD ,Transmit frame-sync mode select bits 0x0: Burst mode 0x1: Reserved 0x2: 2-slot TDM mode () 0x3 - 0x20: 3-slot TDM to 32-slot TDM mode 0x21 - 0x17F: Reserved 0x180: 384-slot DIT mode All other: Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator." bitfld.long 0x0 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits, determine the divide-down ratio from AHCLKX to ACLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0x1F: Divide-by-3 to divide-by-32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKXM ,Transmit bit clock source bit" "0,1" textline " " bitfld.long 0x0 6. " ASYNC ,Transmit operation asynchronous enable bit" "0,1" bitfld.long 0x0 7. " CLKXP ,Transmit bitstream clock polarity select bit." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKXADJ ,CLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If CLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB4++0x3 line.long 0x0 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0xFFF: Divide-by-3 to divide-by-4096" bitfld.long 0x0 12.--13. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKXM ,Transmit high-frequency clock source bit" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKXADJ ,HCLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB8++0x3 line.long 0x0 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)." hexmask.long 0x0 0.--31. 1. " XTDMS_31_0 ,Transmitter mode during TDM time slot n (n = 0..31)" group.byte 0xBC++0x3 line.long 0x0 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates XINT." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " XDMAERR ,Transmit DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " XSTAFRM ,Transmit start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the MCASP logic has priority and the flag remains set. This also causes the generation of a new interrupt request." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF[n] to XRSR[n], but XBUF[n] has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT) if this bit and XUNDRN inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT) if this bit and XSYNCERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt (XINT) if this bit and XCKFAIL inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 3. " XTDMSLOT ,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot flag. XLAST, along with XDATA, are set if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT) if this bit and XLAST inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data ready flag. Causes a transmit interrupt (XINT) if this bit and XDATA inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " XSTAFRM ,Transmit start of frame flag. Causes a transmit interrupt (XINT) if this bit and XSTAFRM inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" bitfld.long 0x0 7. " XDMAERR ,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more words to the DATA port of the MCASP in a given time slot than it should. Causes a transmit interrupt (XINT) if this bit and XDMAERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 8. " XERR ,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x0 0.--8. 1. " XSLOTCNT ,Current transmit time slot count. the value of this register is 0b0101111111 (0x17f) during reset and 0 after reset." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit." bitfld.long 0x0 0.--3. " XPS ,Transmit clock check prescaler value 0x0: MCASP interface clock divided by 1 0x1: MCASP interface clock divided by 2 0x2: MCASP interface clock divided by 4 0x3: MCASP interface clock divided by 8 0x4: MCASP interface clock divided by 16 0x5: MCASP interface clock divided by 32 0x6: MCASP interface clock divided by 64 0x7: MCASP interface clock divided by 128 0x8: MCASP interface clock divided by 256 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " XMIN ,0x0 to 0xFF: Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If XCNT is less than XMIN after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " XMAX ,0x0 to 0xFF: Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If the current counter value is greater than XMAX after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " XCNT ,Transmit clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 transmit high-frequency master clock (mcaspi_ahclkx) signals, and stores the count in XCNT until the next measurement is taken" group.byte 0xCC++0x3 line.long 0x0 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x0 0. " XDATDMA ,Transmit data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD0++0x3 line.long 0x0 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x0 0. " ENABLE ,One-shot clock adjust enable. Not supported. Bit field must always be written as 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x104++0x3 line.long 0x0 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x108++0x3 line.long 0x0 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x10C++0x3 line.long 0x0 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x110++0x3 line.long 0x0 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x114++0x3 line.long 0x0 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x118++0x3 line.long 0x0 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x11C++0x3 line.long 0x0 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x120++0x3 line.long 0x0 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x124++0x3 line.long 0x0 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x128++0x3 line.long 0x0 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x12C++0x3 line.long 0x0 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x130++0x3 line.long 0x0 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x134++0x3 line.long 0x0 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x138++0x3 line.long 0x0 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x13C++0x3 line.long 0x0 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x140++0x3 line.long 0x0 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x144++0x3 line.long 0x0 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x148++0x3 line.long 0x0 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x14C++0x3 line.long 0x0 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x150++0x3 line.long 0x0 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x154++0x3 line.long 0x0 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x158++0x3 line.long 0x0 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x15C++0x3 line.long 0x0 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x180++0x3 line.long 0x0 "MCASP_XRSRCTLn_0,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "MCASP_XRSRCTLn_1,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "MCASP_XRSRCTLn_2,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "MCASP_XRSRCTLn_3,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x204++0x3 line.long 0x0 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x208++0x3 line.long 0x0 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x20C++0x3 line.long 0x0 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x280++0x3 line.long 0x0 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x284++0x3 line.long 0x0 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x288++0x3 line.long 0x0 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x28C++0x3 line.long 0x0 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" width 0x0B tree.end tree "MCASP6_CFG" base ad:0x48474000 width 18. group.byte 0x0++0x3 line.long 0x0 "MCASP_PID,Peripheral identification register" bitfld.long 0x0 0.--5. " REVMINOR ,Minor revision number." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Non-custom. Indicates a special version for a given device." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " REVMAJOR ,Major revision number." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNCTION ,MCASP. Indicates a software-compatible module family." bitfld.long 0x0 28.--29. " RESV ,Reserved." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,Scheme. Distinguishes between old scheme and current." "0,1,2,3" group.byte 0x4++0x3 line.long 0x0 "PWRIDLESYSCONFIG,Power idle module configuration register." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode - default state 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 2.--5. " OTHER ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO." "0,1" group.byte 0x14++0x3 line.long 0x0 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin." bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output." "0,1" group.byte 0x18++0x3 line.long 0x0 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times, and may be read back at all times. The value held by is not affected by writing to and . However, the data value in is driven out onto the MCASP pin only if the corresponding bit in is set to 1 (GPIO function) and the corresponding bit in is set to 1 (output)." bitfld.long 0x0 0. " AXR0 ,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1." "0,1" bitfld.long 0x0 28. " AFSX ,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "0,1" bitfld.long 0x0 30. " AHCLKR ,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1." "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins. allows reading the actual value of the pin, regardless of the state of and ." bitfld.long 0x0 0. " AXR0 ,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)." "0,1" bitfld.long 0x0 1. " AXR1 ,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)." "0,1" bitfld.long 0x0 3. " AXR3 ,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)." "0,1" bitfld.long 0x0 5. " AXR5 ,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)." "0,1" bitfld.long 0x0 7. " AXR7 ,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)." "0,1" bitfld.long 0x0 9. " AXR9 ,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)." "0,1" bitfld.long 0x0 11. " AXR11 ,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)." "0,1" bitfld.long 0x0 13. " AXR13 ,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)." "0,1" bitfld.long 0x0 15. " AXR15 ,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)." "0,1" bitfld.long 0x0 28. " AFSX ,Logic level on AFSX pin (device level: mcaspi_fsx signal)." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Logic level on AFSR pin (device level: mcaspi_fsr signal)." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only. Writing a 1 to the bit sets the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic high on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x20++0x3 line.long 0x0 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only. Writing a 1 to the bit clears the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic low on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x44++0x3 line.long 0x0 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections. The bit fields in are synchronized and latched by the transmitter and receiver corresponding clocks - mcaspi_aclkx clock ( bits [12:8] ) and mcaspi_aclkr ( bits [4:0] ), respectively. Before programming , ensure that the serial clocks are running. If the corresponding external serial clocks - mcaspi_aclkx and mcaspi_aclkr, are not yet running, select the internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL and ACLKRCTL before programming the . Also, after programming any bits in , do not proceed until reading back from and verifying that the bits in are latched." bitfld.long 0x0 0. " RCLKRST ,Receive clock divider reset enable bit." "0,1" bitfld.long 0x0 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit." "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed." "0,1" bitfld.long 0x0 3. " RSMRST ,Receive state machine reset enable bit." "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,Transmit clock divider reset enable bit" "0,1" bitfld.long 0x0 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,Transmit serializer clear enable bit. By clearing and then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the next active time slot, an underrun occurs." "0,1" bitfld.long 0x0 11. " XSMRST ,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1, the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot. ." "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Transmit frame-sync generator reset enable bit" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode. Note that loopback is NOT supported if MCASP is configured in DIT mode." bitfld.long 0x0 0. " DLBEN ,Loop back mode enable bit." "0,1" bitfld.long 0x0 1. " ORD ,Loopback order bit when loopback mode is enabled (DLBEN = 1)." "0,1" textline " " bitfld.long 0x0 2.--3. " MODE ,Loopback generator mode bits.0x2, 0x3: Reserved enum=RESERVED ." "0,1,2,3" bitfld.long 0x0 4. " IOLBEN ,If DLBEN=0b1, the IOLBEN bit selects between and loopback modes. IOLBEN bit value is irrelevant, If DLBEN=0b0." "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "MCASP_TXDITCTL,Transmit DIT mode control register, controls DIT operations of the MCASP" bitfld.long 0x0 0. " DITEN ,DIT mode enable bit" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " VA ,Valid bit for even time slots (DIT left subframe)." "0,1" bitfld.long 0x0 3. " VB ,Valid bit for odd time slots (DIT right subframe)." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "MCASP_GBLCTLR,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12). Reads return GBLCTL" bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU." hexmask.long 0x0 0.--31. 1. " RMASK_31_0 ,Receive data mask enable bit." group.byte 0x68++0x3 line.long 0x0 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format." bitfld.long 0x0 0.--2. " RROT ,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RBUSEL ,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " RSSZ ,Receive slot size.0x0 - 0x2 : Reserved enum=RSVD ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " RPBIT ,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits. This field only applies when RPAD = 2h.0x01 - 0x1F: Pad with value of the bit positioned within the range RBUFn[31:1]. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " RRVRS ,Receive serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " RDATDLY ,Receive Frame sync delay of AXR[n]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)." bitfld.long 0x0 0. " FSRP ,Receive frame sync polarity select bit." "0,1" bitfld.long 0x0 1. " FSRM ,Receive frame sync generation select bit." "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " FRWID ,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " RMOD ,Receive frame sync mode select bits.0x3 - 0x20: 3-slot TDM to 32-slot TDM mode . 0x21 - 0x17F: Reserved . 0x181 - 0x1FF: Reserved ." textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator." bitfld.long 0x0 0.--4. " CLKRDIV ,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0.0x2 - 0x1F: Divide-by-3 to divide-by-32 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKRM ,Receive bit clock source bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " CLKRP ,Receive bitstream clock polarity select bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKRADJ ,CLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0.If CLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR.0x2 - 0xFFF: Divide-by-3 to divide-by-4096 ." bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKRM ,High Freq. RCV clock Source" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKRADJ ,HCLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active." hexmask.long 0x0 0.--31. 1. " RTDMS_31_0 ,Receiver mode during TDM time slot n." group.byte 0x7C++0x3 line.long 0x0 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates RINT." bitfld.long 0x0 0. " ROVRN ,Receiver overrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " RDMAERR ,Receive DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " RDATA ,Receive data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " RSTAFRM ,Receive start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number." bitfld.long 0x0 0. " ROVRN ,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync (AFSR) occurs before it is expected. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 3. " RTDMSLOT ,Returns the LSB of RSLOT. Allows a single read ofMCASP_RXSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 5. " RDATA ,Receive data ready flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " RSTAFRM ,Receive start of frame flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 7. " RDMAERR ,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the DMA port in a given time slot than were programmed as receivers. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 8. " RERR ,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame." hexmask.long.word 0x0 0.--8. 1. " RSLOTCNT ,0x0 - 0x17F: Current receive time slot count. Legal values: 0 to 383 (17Fh). TDM function is not supported for > 32 time slots. However, TDM time slot counter may count to 383 when used to receive a DIR block (transferred over TDM format)." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." bitfld.long 0x0 0.--3. " RPS ,Receive clock check prescaler value.0x9 - 0xF: Reserved enum=DIVBY8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " RMIN ,0x00 - 0xFF: Receive clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If RCNT is less than RMIN after counting 32 AHCLKR signals, RCKFAIL in RSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " RMAX ,0x00-0xFF: Receive clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If the current counter value is greater than RMAX after counting 32 AHCLKR signals, RCKFAIL inMCASP_RXSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " RCNT ,0x0 - 0xFF: Receive clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 receive high-frequency master clock (AHCLKR) signals, and stores the count in RCNT until the next measurement is taken." group.byte 0x8C++0x3 line.long 0x0 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x0 0. " RDATDMA ,Receive data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MCASP_GBLCTLX,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12.). Reads return GBLCTL." bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLKR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" hexmask.long 0x0 0.--31. 1. " XMASK_31_0 ,Transmit data mask enable bit" group.byte 0xA8++0x3 line.long 0x0 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x0 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " XBUSEL ,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " XSSZ ,Transmit slot size0x0 - 0x2 : Reserved enum=RSV8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " XPBIT ,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting. This field only applies when XPAD = 0x2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " XRVRS ,Transmit serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " XDATDLY ,Transmit sync bit delay" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xAC++0x3 line.long 0x0 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)." bitfld.long 0x0 0. " FSXP ,Transmit frame-sync polarity select bit" "0,1" bitfld.long 0x0 1. " FSXM ,Transmit frame-sync generation select bit" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4. " FXWID ,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " XMOD ,Transmit frame-sync mode select bits 0x0: Burst mode 0x1: Reserved 0x2: 2-slot TDM mode () 0x3 - 0x20: 3-slot TDM to 32-slot TDM mode 0x21 - 0x17F: Reserved 0x180: 384-slot DIT mode All other: Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator." bitfld.long 0x0 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits, determine the divide-down ratio from AHCLKX to ACLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0x1F: Divide-by-3 to divide-by-32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKXM ,Transmit bit clock source bit" "0,1" textline " " bitfld.long 0x0 6. " ASYNC ,Transmit operation asynchronous enable bit" "0,1" bitfld.long 0x0 7. " CLKXP ,Transmit bitstream clock polarity select bit." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKXADJ ,CLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If CLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB4++0x3 line.long 0x0 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0xFFF: Divide-by-3 to divide-by-4096" bitfld.long 0x0 12.--13. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKXM ,Transmit high-frequency clock source bit" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKXADJ ,HCLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB8++0x3 line.long 0x0 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)." hexmask.long 0x0 0.--31. 1. " XTDMS_31_0 ,Transmitter mode during TDM time slot n (n = 0..31)" group.byte 0xBC++0x3 line.long 0x0 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates XINT." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " XDMAERR ,Transmit DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " XSTAFRM ,Transmit start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the MCASP logic has priority and the flag remains set. This also causes the generation of a new interrupt request." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF[n] to XRSR[n], but XBUF[n] has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT) if this bit and XUNDRN inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT) if this bit and XSYNCERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt (XINT) if this bit and XCKFAIL inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 3. " XTDMSLOT ,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot flag. XLAST, along with XDATA, are set if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT) if this bit and XLAST inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data ready flag. Causes a transmit interrupt (XINT) if this bit and XDATA inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " XSTAFRM ,Transmit start of frame flag. Causes a transmit interrupt (XINT) if this bit and XSTAFRM inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" bitfld.long 0x0 7. " XDMAERR ,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more words to the DATA port of the MCASP in a given time slot than it should. Causes a transmit interrupt (XINT) if this bit and XDMAERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 8. " XERR ,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x0 0.--8. 1. " XSLOTCNT ,Current transmit time slot count. the value of this register is 0b0101111111 (0x17f) during reset and 0 after reset." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit." bitfld.long 0x0 0.--3. " XPS ,Transmit clock check prescaler value 0x0: MCASP interface clock divided by 1 0x1: MCASP interface clock divided by 2 0x2: MCASP interface clock divided by 4 0x3: MCASP interface clock divided by 8 0x4: MCASP interface clock divided by 16 0x5: MCASP interface clock divided by 32 0x6: MCASP interface clock divided by 64 0x7: MCASP interface clock divided by 128 0x8: MCASP interface clock divided by 256 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " XMIN ,0x0 to 0xFF: Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If XCNT is less than XMIN after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " XMAX ,0x0 to 0xFF: Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If the current counter value is greater than XMAX after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " XCNT ,Transmit clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 transmit high-frequency master clock (mcaspi_ahclkx) signals, and stores the count in XCNT until the next measurement is taken" group.byte 0xCC++0x3 line.long 0x0 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x0 0. " XDATDMA ,Transmit data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD0++0x3 line.long 0x0 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x0 0. " ENABLE ,One-shot clock adjust enable. Not supported. Bit field must always be written as 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x104++0x3 line.long 0x0 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x108++0x3 line.long 0x0 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x10C++0x3 line.long 0x0 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x110++0x3 line.long 0x0 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x114++0x3 line.long 0x0 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x118++0x3 line.long 0x0 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x11C++0x3 line.long 0x0 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x120++0x3 line.long 0x0 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x124++0x3 line.long 0x0 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x128++0x3 line.long 0x0 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x12C++0x3 line.long 0x0 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x130++0x3 line.long 0x0 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x134++0x3 line.long 0x0 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x138++0x3 line.long 0x0 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x13C++0x3 line.long 0x0 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x140++0x3 line.long 0x0 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x144++0x3 line.long 0x0 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x148++0x3 line.long 0x0 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x14C++0x3 line.long 0x0 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x150++0x3 line.long 0x0 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x154++0x3 line.long 0x0 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x158++0x3 line.long 0x0 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x15C++0x3 line.long 0x0 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x180++0x3 line.long 0x0 "MCASP_XRSRCTLn_0,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "MCASP_XRSRCTLn_1,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "MCASP_XRSRCTLn_2,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "MCASP_XRSRCTLn_3,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x204++0x3 line.long 0x0 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x208++0x3 line.long 0x0 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x20C++0x3 line.long 0x0 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x280++0x3 line.long 0x0 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x284++0x3 line.long 0x0 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x288++0x3 line.long 0x0 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x28C++0x3 line.long 0x0 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" width 0x0B tree.end tree "MCASP7_CFG" base ad:0x48478000 width 18. group.byte 0x0++0x3 line.long 0x0 "MCASP_PID,Peripheral identification register" bitfld.long 0x0 0.--5. " REVMINOR ,Minor revision number." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Non-custom. Indicates a special version for a given device." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " REVMAJOR ,Major revision number." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNCTION ,MCASP. Indicates a software-compatible module family." bitfld.long 0x0 28.--29. " RESV ,Reserved." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,Scheme. Distinguishes between old scheme and current." "0,1,2,3" group.byte 0x4++0x3 line.long 0x0 "PWRIDLESYSCONFIG,Power idle module configuration register." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode - default state 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 2.--5. " OTHER ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO." "0,1" group.byte 0x14++0x3 line.long 0x0 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin." bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output." "0,1" group.byte 0x18++0x3 line.long 0x0 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times, and may be read back at all times. The value held by is not affected by writing to and . However, the data value in is driven out onto the MCASP pin only if the corresponding bit in is set to 1 (GPIO function) and the corresponding bit in is set to 1 (output)." bitfld.long 0x0 0. " AXR0 ,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1." "0,1" bitfld.long 0x0 28. " AFSX ,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "0,1" bitfld.long 0x0 30. " AHCLKR ,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1." "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins. allows reading the actual value of the pin, regardless of the state of and ." bitfld.long 0x0 0. " AXR0 ,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)." "0,1" bitfld.long 0x0 1. " AXR1 ,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)." "0,1" bitfld.long 0x0 3. " AXR3 ,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)." "0,1" bitfld.long 0x0 5. " AXR5 ,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)." "0,1" bitfld.long 0x0 7. " AXR7 ,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)." "0,1" bitfld.long 0x0 9. " AXR9 ,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)." "0,1" bitfld.long 0x0 11. " AXR11 ,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)." "0,1" bitfld.long 0x0 13. " AXR13 ,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)." "0,1" bitfld.long 0x0 15. " AXR15 ,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)." "0,1" bitfld.long 0x0 28. " AFSX ,Logic level on AFSX pin (device level: mcaspi_fsx signal)." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Logic level on AFSR pin (device level: mcaspi_fsr signal)." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only. Writing a 1 to the bit sets the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic high on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x20++0x3 line.long 0x0 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only. Writing a 1 to the bit clears the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic low on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x44++0x3 line.long 0x0 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections. The bit fields in are synchronized and latched by the transmitter and receiver corresponding clocks - mcaspi_aclkx clock ( bits [12:8] ) and mcaspi_aclkr ( bits [4:0] ), respectively. Before programming , ensure that the serial clocks are running. If the corresponding external serial clocks - mcaspi_aclkx and mcaspi_aclkr, are not yet running, select the internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL and ACLKRCTL before programming the . Also, after programming any bits in , do not proceed until reading back from and verifying that the bits in are latched." bitfld.long 0x0 0. " RCLKRST ,Receive clock divider reset enable bit." "0,1" bitfld.long 0x0 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit." "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed." "0,1" bitfld.long 0x0 3. " RSMRST ,Receive state machine reset enable bit." "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,Transmit clock divider reset enable bit" "0,1" bitfld.long 0x0 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,Transmit serializer clear enable bit. By clearing and then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the next active time slot, an underrun occurs." "0,1" bitfld.long 0x0 11. " XSMRST ,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1, the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot. ." "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Transmit frame-sync generator reset enable bit" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode. Note that loopback is NOT supported if MCASP is configured in DIT mode." bitfld.long 0x0 0. " DLBEN ,Loop back mode enable bit." "0,1" bitfld.long 0x0 1. " ORD ,Loopback order bit when loopback mode is enabled (DLBEN = 1)." "0,1" textline " " bitfld.long 0x0 2.--3. " MODE ,Loopback generator mode bits.0x2, 0x3: Reserved enum=RESERVED ." "0,1,2,3" bitfld.long 0x0 4. " IOLBEN ,If DLBEN=0b1, the IOLBEN bit selects between and loopback modes. IOLBEN bit value is irrelevant, If DLBEN=0b0." "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "MCASP_TXDITCTL,Transmit DIT mode control register, controls DIT operations of the MCASP" bitfld.long 0x0 0. " DITEN ,DIT mode enable bit" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " VA ,Valid bit for even time slots (DIT left subframe)." "0,1" bitfld.long 0x0 3. " VB ,Valid bit for odd time slots (DIT right subframe)." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "MCASP_GBLCTLR,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12). Reads return GBLCTL" bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU." hexmask.long 0x0 0.--31. 1. " RMASK_31_0 ,Receive data mask enable bit." group.byte 0x68++0x3 line.long 0x0 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format." bitfld.long 0x0 0.--2. " RROT ,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RBUSEL ,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " RSSZ ,Receive slot size.0x0 - 0x2 : Reserved enum=RSVD ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " RPBIT ,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits. This field only applies when RPAD = 2h.0x01 - 0x1F: Pad with value of the bit positioned within the range RBUFn[31:1]. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " RRVRS ,Receive serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " RDATDLY ,Receive Frame sync delay of AXR[n]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)." bitfld.long 0x0 0. " FSRP ,Receive frame sync polarity select bit." "0,1" bitfld.long 0x0 1. " FSRM ,Receive frame sync generation select bit." "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " FRWID ,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " RMOD ,Receive frame sync mode select bits.0x3 - 0x20: 3-slot TDM to 32-slot TDM mode . 0x21 - 0x17F: Reserved . 0x181 - 0x1FF: Reserved ." textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator." bitfld.long 0x0 0.--4. " CLKRDIV ,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0.0x2 - 0x1F: Divide-by-3 to divide-by-32 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKRM ,Receive bit clock source bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " CLKRP ,Receive bitstream clock polarity select bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKRADJ ,CLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0.If CLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR.0x2 - 0xFFF: Divide-by-3 to divide-by-4096 ." bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKRM ,High Freq. RCV clock Source" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKRADJ ,HCLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active." hexmask.long 0x0 0.--31. 1. " RTDMS_31_0 ,Receiver mode during TDM time slot n." group.byte 0x7C++0x3 line.long 0x0 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates RINT." bitfld.long 0x0 0. " ROVRN ,Receiver overrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " RDMAERR ,Receive DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " RDATA ,Receive data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " RSTAFRM ,Receive start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number." bitfld.long 0x0 0. " ROVRN ,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync (AFSR) occurs before it is expected. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 3. " RTDMSLOT ,Returns the LSB of RSLOT. Allows a single read ofMCASP_RXSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 5. " RDATA ,Receive data ready flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " RSTAFRM ,Receive start of frame flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 7. " RDMAERR ,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the DMA port in a given time slot than were programmed as receivers. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 8. " RERR ,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame." hexmask.long.word 0x0 0.--8. 1. " RSLOTCNT ,0x0 - 0x17F: Current receive time slot count. Legal values: 0 to 383 (17Fh). TDM function is not supported for > 32 time slots. However, TDM time slot counter may count to 383 when used to receive a DIR block (transferred over TDM format)." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." bitfld.long 0x0 0.--3. " RPS ,Receive clock check prescaler value.0x9 - 0xF: Reserved enum=DIVBY8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " RMIN ,0x00 - 0xFF: Receive clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If RCNT is less than RMIN after counting 32 AHCLKR signals, RCKFAIL in RSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " RMAX ,0x00-0xFF: Receive clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If the current counter value is greater than RMAX after counting 32 AHCLKR signals, RCKFAIL inMCASP_RXSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " RCNT ,0x0 - 0xFF: Receive clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 receive high-frequency master clock (AHCLKR) signals, and stores the count in RCNT until the next measurement is taken." group.byte 0x8C++0x3 line.long 0x0 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x0 0. " RDATDMA ,Receive data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MCASP_GBLCTLX,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12.). Reads return GBLCTL." bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLKR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" hexmask.long 0x0 0.--31. 1. " XMASK_31_0 ,Transmit data mask enable bit" group.byte 0xA8++0x3 line.long 0x0 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x0 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " XBUSEL ,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " XSSZ ,Transmit slot size0x0 - 0x2 : Reserved enum=RSV8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " XPBIT ,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting. This field only applies when XPAD = 0x2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " XRVRS ,Transmit serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " XDATDLY ,Transmit sync bit delay" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xAC++0x3 line.long 0x0 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)." bitfld.long 0x0 0. " FSXP ,Transmit frame-sync polarity select bit" "0,1" bitfld.long 0x0 1. " FSXM ,Transmit frame-sync generation select bit" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4. " FXWID ,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " XMOD ,Transmit frame-sync mode select bits 0x0: Burst mode 0x1: Reserved 0x2: 2-slot TDM mode () 0x3 - 0x20: 3-slot TDM to 32-slot TDM mode 0x21 - 0x17F: Reserved 0x180: 384-slot DIT mode All other: Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator." bitfld.long 0x0 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits, determine the divide-down ratio from AHCLKX to ACLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0x1F: Divide-by-3 to divide-by-32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKXM ,Transmit bit clock source bit" "0,1" textline " " bitfld.long 0x0 6. " ASYNC ,Transmit operation asynchronous enable bit" "0,1" bitfld.long 0x0 7. " CLKXP ,Transmit bitstream clock polarity select bit." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKXADJ ,CLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If CLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB4++0x3 line.long 0x0 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0xFFF: Divide-by-3 to divide-by-4096" bitfld.long 0x0 12.--13. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKXM ,Transmit high-frequency clock source bit" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKXADJ ,HCLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB8++0x3 line.long 0x0 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)." hexmask.long 0x0 0.--31. 1. " XTDMS_31_0 ,Transmitter mode during TDM time slot n (n = 0..31)" group.byte 0xBC++0x3 line.long 0x0 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates XINT." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " XDMAERR ,Transmit DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " XSTAFRM ,Transmit start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the MCASP logic has priority and the flag remains set. This also causes the generation of a new interrupt request." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF[n] to XRSR[n], but XBUF[n] has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT) if this bit and XUNDRN inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT) if this bit and XSYNCERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt (XINT) if this bit and XCKFAIL inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 3. " XTDMSLOT ,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot flag. XLAST, along with XDATA, are set if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT) if this bit and XLAST inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data ready flag. Causes a transmit interrupt (XINT) if this bit and XDATA inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " XSTAFRM ,Transmit start of frame flag. Causes a transmit interrupt (XINT) if this bit and XSTAFRM inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" bitfld.long 0x0 7. " XDMAERR ,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more words to the DATA port of the MCASP in a given time slot than it should. Causes a transmit interrupt (XINT) if this bit and XDMAERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 8. " XERR ,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x0 0.--8. 1. " XSLOTCNT ,Current transmit time slot count. the value of this register is 0b0101111111 (0x17f) during reset and 0 after reset." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit." bitfld.long 0x0 0.--3. " XPS ,Transmit clock check prescaler value 0x0: MCASP interface clock divided by 1 0x1: MCASP interface clock divided by 2 0x2: MCASP interface clock divided by 4 0x3: MCASP interface clock divided by 8 0x4: MCASP interface clock divided by 16 0x5: MCASP interface clock divided by 32 0x6: MCASP interface clock divided by 64 0x7: MCASP interface clock divided by 128 0x8: MCASP interface clock divided by 256 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " XMIN ,0x0 to 0xFF: Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If XCNT is less than XMIN after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " XMAX ,0x0 to 0xFF: Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If the current counter value is greater than XMAX after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " XCNT ,Transmit clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 transmit high-frequency master clock (mcaspi_ahclkx) signals, and stores the count in XCNT until the next measurement is taken" group.byte 0xCC++0x3 line.long 0x0 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x0 0. " XDATDMA ,Transmit data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD0++0x3 line.long 0x0 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x0 0. " ENABLE ,One-shot clock adjust enable. Not supported. Bit field must always be written as 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x104++0x3 line.long 0x0 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x108++0x3 line.long 0x0 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x10C++0x3 line.long 0x0 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x110++0x3 line.long 0x0 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x114++0x3 line.long 0x0 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x118++0x3 line.long 0x0 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x11C++0x3 line.long 0x0 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x120++0x3 line.long 0x0 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x124++0x3 line.long 0x0 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x128++0x3 line.long 0x0 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x12C++0x3 line.long 0x0 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x130++0x3 line.long 0x0 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x134++0x3 line.long 0x0 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x138++0x3 line.long 0x0 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x13C++0x3 line.long 0x0 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x140++0x3 line.long 0x0 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x144++0x3 line.long 0x0 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x148++0x3 line.long 0x0 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x14C++0x3 line.long 0x0 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x150++0x3 line.long 0x0 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x154++0x3 line.long 0x0 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x158++0x3 line.long 0x0 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x15C++0x3 line.long 0x0 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x180++0x3 line.long 0x0 "MCASP_XRSRCTLn_0,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "MCASP_XRSRCTLn_1,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "MCASP_XRSRCTLn_2,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "MCASP_XRSRCTLn_3,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x204++0x3 line.long 0x0 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x208++0x3 line.long 0x0 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x20C++0x3 line.long 0x0 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x280++0x3 line.long 0x0 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x284++0x3 line.long 0x0 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x288++0x3 line.long 0x0 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x28C++0x3 line.long 0x0 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" width 0x0B tree.end tree "MCASP8_CFG" base ad:0x4847C000 width 18. group.byte 0x0++0x3 line.long 0x0 "MCASP_PID,Peripheral identification register" bitfld.long 0x0 0.--5. " REVMINOR ,Minor revision number." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Non-custom. Indicates a special version for a given device." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " REVMAJOR ,Major revision number." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL version." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNCTION ,MCASP. Indicates a software-compatible module family." bitfld.long 0x0 28.--29. " RESV ,Reserved." "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,Scheme. Distinguishes between old scheme and current." "0,1,2,3" group.byte 0x4++0x3 line.long 0x0 "PWRIDLESYSCONFIG,Power idle module configuration register." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0: Force-idle mode 0x1: No-idle mode 0x2: Smart-idle mode - default state 0x3: Reserved" "0,1,2,3" bitfld.long 0x0 2.--5. " OTHER ,Reserved for future expansion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "MCASP_PFUNC,Specifies the function of the pins as either a MCASP pin or a GPIO pin" bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as MCASP or GPIO." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as MCASP or GPIO." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as MCASP or GPIO." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as MCASP or GPIO." "0,1" group.byte 0x14++0x3 line.long 0x0 "MCASP_PDIR,Pin direction register - specifies the direction of the MCASP pins as either an input or an output pin." bitfld.long 0x0 0. " AXR0 ,Determines if AXR0 pin (device level: mcaspi_axr[0] signal) functions as an input or output." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines if AXR1 pin (device level: mcaspi_axr[1] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines if AXR2 pin (device level: mcaspi_axr[2] signal) functions as an input or output." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines if AXR3 pin (device level: mcaspi_axr[3] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines if AXR4 pin (device level: mcaspi_axr[4] signal) functions as an input or output." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines if AXR5 pin (device level: mcaspi_axr[5] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines if AXR6 pin (device level: mcaspi_axr[6] signal) functions as an input or output." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines if AXR7 pin (device level: mcaspi_axr[7] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines if AXR8 pin (device level: mcaspi_axr[8] signal) functions as an input or output." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines if AXR9 pin (device level: mcaspi_axr[9] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines if AXR10 pin (device level: mcaspi_axr[10] signal) functions as an input or output." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines if AXR11 pin (device level: mcaspi_axr[11] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines if AXR12 pin (device level: mcaspi_axr[12] signal) functions as an input or output." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines if AXR13 pin (device level: mcaspi_axr[13] signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines if AXR14 pin (device level: mcaspi_axr[14] signal) functions as an input or output." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines if AXR15 pin (device level: mcaspi_axr[15] signal) functions as an input or output." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines if ACLKX pin (device level: mcaspi_aclkx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines if AHCLKX pin (device level: mcaspi_ahclkx signal) functions as an input or output." "0,1" bitfld.long 0x0 28. " AFSX ,Determines if AFSX pin (device level: mcaspi_fsx signal) functions as an input or output." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines if ACLKR pin (device level: mcaspi_aclkr signal) functions as an input or output." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines if AFSR pin (device level: mcaspi_fsr signal) functions as an input or output." "0,1" group.byte 0x18++0x3 line.long 0x0 "MCASP_PDOUT,Pin data output register - holds a value for data out at all times, and may be read back at all times. The value held by is not affected by writing to and . However, the data value in is driven out onto the MCASP pin only if the corresponding bit in is set to 1 (GPIO function) and the corresponding bit in is set to 1 (output)." bitfld.long 0x0 0. " AXR0 ,Determines drive on AXR0 output pin when the correspondingMCASP_PFUNC[0] and MCASP_PDIR[0] bits are set to 1." "0,1" bitfld.long 0x0 1. " AXR1 ,Determines drive on AXR1 output pin when the correspondingMCASP_PFUNC[1] and MCASP_PDIR[1] bits are set to 1." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Determines drive on AXR2 output pin when the correspondingMCASP_PFUNC[2] and MCASP_PDIR[2] bits are set to 1." "0,1" bitfld.long 0x0 3. " AXR3 ,Determines drive on AXR3 output pin when the correspondingMCASP_PFUNC[3] and MCASP_PDIR[3] bits are set to 1." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Determines drive on AXR4 output pin when the correspondingMCASP_PFUNC[4] and MCASP_PDIR[4] bits are set to 1." "0,1" bitfld.long 0x0 5. " AXR5 ,Determines drive on AXR5 output pin when the correspondingMCASP_PFUNC[5] and MCASP_PDIR[5] bits are set to 1." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Determines drive on AXR6 output pin when the correspondingMCASP_PFUNC[6] and MCASP_PDIR[6] bits are set to 1." "0,1" bitfld.long 0x0 7. " AXR7 ,Determines drive on AXR7 output pin when the correspondingMCASP_PFUNC[7] and MCASP_PDIR[7] bits are set to 1." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Determines drive on AXR8 output pin when the correspondingMCASP_PFUNC[8] and MCASP_PDIR[8] bits are set to 1." "0,1" bitfld.long 0x0 9. " AXR9 ,Determines drive on AXR9 output pin when the correspondingMCASP_PFUNC[9] and MCASP_PDIR[9] bits are set to 1." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Determines drive on AXR10 output pin when the correspondingMCASP_PFUNC[10] and MCASP_PDIR[10] bits are set to 1." "0,1" bitfld.long 0x0 11. " AXR11 ,Determines drive on AXR11 output pin when the correspondingMCASP_PFUNC[11] and MCASP_PDIR[11] bits are set to 1." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Determines drive on AXR12 output pin when the correspondingMCASP_PFUNC[12] and MCASP_PDIR[12] bits are set to 1." "0,1" bitfld.long 0x0 13. " AXR13 ,Determines drive on AXR13 output pin when the correspondingMCASP_PFUNC[13] and MCASP_PDIR[13] bits are set to 1." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Determines drive on AXR14 output pin when the correspondingMCASP_PFUNC[14] and MCASP_PDIR[14] bits are set to 1." "0,1" bitfld.long 0x0 15. " AXR15 ,Determines drive on AXR15 output pin when the correspondingMCASP_PFUNC[15] and MCASP_PDIR[15] bits are set to 1." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Determines drive on ACLKX output pin when the correspondingMCASP_PFUNC[26] and MCASP_PDIR[26] bits are set to 1" "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Determines drive on AHCLKX output pin when the correspondingMCASP_PFUNC[27] and MCASP_PDIR[27] bits are set to 1." "0,1" bitfld.long 0x0 28. " AFSX ,Determines drive on AFSX output pin when the correspondingMCASP_PFUNC[28] and MCASP_PDIR[28] bits are set to 1." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Determines drive on ACLKR output pin when the correspondingMCASP_PFUNC[29] and MCASP_PDIR[29] bits are set to 1" "0,1" bitfld.long 0x0 30. " AHCLKR ,Determines drive on AHCLKR output pin when the correspondingMCASP_PFUNC[30] and MCASP_PDIR[30] bits are set to 1." "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Determines drive on AFSR output pin when the correspondingMCASP_PFUNC[31] and MCASP_PDIR[31] bits are set to 1." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDIN,Pin data input register - holds the state of all the MCASP pins. allows reading the actual value of the pin, regardless of the state of and ." bitfld.long 0x0 0. " AXR0 ,Logic level on AXR0 pin (device level: mcaspi_axr[0] signal)." "0,1" bitfld.long 0x0 1. " AXR1 ,Logic level on AXR1 pin (device level: mcaspi_axr[1] signal)." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Logic level on AXR2 pin (device level: mcaspi_axr[2] signal)." "0,1" bitfld.long 0x0 3. " AXR3 ,Logic level on AXR3 pin (device level: mcaspi_axr[3] signal)." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Logic level on AXR4 pin (device level: mcaspi_axr[4] signal)." "0,1" bitfld.long 0x0 5. " AXR5 ,Logic level on AXR5 pin (device level: mcaspi_axr[5] signal)." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Logic level on AXR6 pin (device level: mcaspi_axr[6] signal)." "0,1" bitfld.long 0x0 7. " AXR7 ,Logic level on AXR7 pin (device level: mcaspi_axr[7] signal)." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Logic level on AXR8 pin (device level: mcaspi_axr[8] signal)." "0,1" bitfld.long 0x0 9. " AXR9 ,Logic level on AXR9 pin (device level: mcaspi_axr[9] signal)." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Logic level on AXR10 pin (device level: mcaspi_axr[10] signal)." "0,1" bitfld.long 0x0 11. " AXR11 ,Logic level on AXR11 pin (device level: mcaspi_axr[11] signal)." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Logic level on AXR12 pin (device level: mcaspi_axr[12] signal)." "0,1" bitfld.long 0x0 13. " AXR13 ,Logic level on AXR13 pin (device level: mcaspi_axr[13] signal)." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Logic level on AXR14 pin (device level: mcaspi_axr[14] signal)." "0,1" bitfld.long 0x0 15. " AXR15 ,Logic level on AXR15 pin (device level: mcaspi_axr[15] signal)." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Logic level on ACLKX pin (device level: mcaspi_aclkx signal)." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Logic level on AHCLKX pin (device level: mcaspi_ahclkx signal)." "0,1" bitfld.long 0x0 28. " AFSX ,Logic level on AFSX pin (device level: mcaspi_fsx signal)." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Logic level on ACLKR pin (device level: mcaspi_aclkr signal)." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Logic level on AFSR pin (device level: mcaspi_fsr signal)." "0,1" group.byte 0x1C++0x3 line.long 0x0 "MCASP_PDSET,The pin data set register is an alias of the pin data output register () for writes only. Writing a 1 to the bit sets the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic high on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x20++0x3 line.long 0x0 "MCASP_PDCLR,The pin data clear register is an alias of the pin data output register () for writes only. Writing a 1 to the bit clears the corresponding bit in and, if = 1 (GPIO function) and = 1 (output), drives a logic low on the pin." bitfld.long 0x0 0. " AXR0 ,Allows the AXR0 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 1. " AXR1 ,Allows the AXR1 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 2. " AXR2 ,Allows the AXR2 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 3. " AXR3 ,Allows the AXR3 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 4. " AXR4 ,Allows the AXR4 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 5. " AXR5 ,Allows the AXR5 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 6. " AXR6 ,Allows the AXR6 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 7. " AXR7 ,Allows the AXR7 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 8. " AXR8 ,Allows the AXR8 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 9. " AXR9 ,Allows the AXR9 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 10. " AXR10 ,Allows the AXR10 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 11. " AXR11 ,Allows the AXR11 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 12. " AXR12 ,Allows the AXR12 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 13. " AXR13 ,Allows the AXR13 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 14. " AXR14 ,Allows the AXR14 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 15. " AXR15 ,Allows the AXR15 bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " hexmask.long.word 0x0 16.--25. 1. " RESERVED ,Reserved" bitfld.long 0x0 26. " ACLKX ,Allows the corresponding ACLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 27. " AHCLKX ,Allows the corresponding AHCLKX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 28. " AFSX ,Allows the corresponding AFSX bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" textline " " bitfld.long 0x0 29. " ACLKR ,Allows the corresponding ACLKR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" bitfld.long 0x0 30. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 31. " AFSR ,Allows the corresponding AFSR bit inMCASP_PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port." "0,1" group.byte 0x44++0x3 line.long 0x0 "MCASP_GBLCTL,Global transmit control register - provides initialization of the transmit and receive sections. The bit fields in are synchronized and latched by the transmitter and receiver corresponding clocks - mcaspi_aclkx clock ( bits [12:8] ) and mcaspi_aclkr ( bits [4:0] ), respectively. Before programming , ensure that the serial clocks are running. If the corresponding external serial clocks - mcaspi_aclkx and mcaspi_aclkr, are not yet running, select the internal serial clock source in AHCLKXCTL, AHCLKRCTL, ACLKXCTL and ACLKRCTL before programming the . Also, after programming any bits in , do not proceed until reading back from and verifying that the bits in are latched." bitfld.long 0x0 0. " RCLKRST ,Receive clock divider reset enable bit." "0,1" bitfld.long 0x0 1. " RHCLKRST ,Receive high-frequency clock divider reset enable bit." "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,Receive serializer clear enable bit. By clearing then setting this bit, the receive buffer is flushed." "0,1" bitfld.long 0x0 3. " RSMRST ,Receive state machine reset enable bit." "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Receive frame sync generator reset enable bit." "0,1" bitfld.long 0x0 5.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,Transmit clock divider reset enable bit" "0,1" bitfld.long 0x0 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable bit" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,Transmit serializer clear enable bit. By clearing and then setting this bit, the transmit buffer is flushed to an empty state (XDATA = 1). If XSMRST = 1, XSRCLR = 1, XDATA = 1, and XBUF is not loaded with new data before the start of the next active time slot, an underrun occurs." "0,1" bitfld.long 0x0 11. " XSMRST ,Transmit state-machine reset enable bitAXR[n] pin state : If[n] = 0 and [n] = 1, the corresponding serializer [n] drives the AXR[n] pin to the state specified for inactive time slot. ." "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Transmit frame-sync generator reset enable bit" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ,Reserved" group.byte 0x48++0x3 line.long 0x0 "MCASP_AMUTE,Mute control register - Controls the MCASP mute output pin - AMUTE (device level - not implemented)" hexmask.long 0x0 0.--31. 1. " RESERVED ,Reserved" group.byte 0x4C++0x3 line.long 0x0 "MCASP_LBCTL,The digital loopback control register () controls the internal (MCASP module)- level and chip-level loopback settings of the MCASP in TDM mode. Note that loopback is NOT supported if MCASP is configured in DIT mode." bitfld.long 0x0 0. " DLBEN ,Loop back mode enable bit." "0,1" bitfld.long 0x0 1. " ORD ,Loopback order bit when loopback mode is enabled (DLBEN = 1)." "0,1" textline " " bitfld.long 0x0 2.--3. " MODE ,Loopback generator mode bits.0x2, 0x3: Reserved enum=RESERVED ." "0,1,2,3" bitfld.long 0x0 4. " IOLBEN ,If DLBEN=0b1, the IOLBEN bit selects between and loopback modes. IOLBEN bit value is irrelevant, If DLBEN=0b0." "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x50++0x3 line.long 0x0 "MCASP_TXDITCTL,Transmit DIT mode control register, controls DIT operations of the MCASP" bitfld.long 0x0 0. " DITEN ,DIT mode enable bit" "0,1" bitfld.long 0x0 1. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 2. " VA ,Valid bit for even time slots (DIT left subframe)." "0,1" bitfld.long 0x0 3. " VB ,Valid bit for odd time slots (DIT right subframe)." "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x60++0x3 line.long 0x0 "MCASP_GBLCTLR,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12). Reads return GBLCTL" bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "MCASP_RXMASK,The receive format unit bit mask register () determines which bits of the received data are masked off and padded with a known value before being read by the CPU." hexmask.long 0x0 0.--31. 1. " RMASK_31_0 ,Receive data mask enable bit." group.byte 0x68++0x3 line.long 0x0 "MCASP_RXFMT,The receive bit stream format register () configures the receive data format." bitfld.long 0x0 0.--2. " RROT ,Right-rotation value for receive rotate right format unit." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RBUSEL ,Selects whether reads from serializer buffer RBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " RSSZ ,Receive slot size.0x0 - 0x2 : Reserved enum=RSVD ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " RPBIT ,RPBIT value determines which bit (as read by the CPU from RBUF[n]) is used to pad the extra bits. This field only applies when RPAD = 2h.0x01 - 0x1F: Pad with value of the bit positioned within the range RBUFn[31:1]. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word. This field only applies to bits when RMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " RRVRS ,Receive serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " RDATDLY ,Receive Frame sync delay of AXR[n]" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "MCASP_RXFMCTL,The receive frame sync control register () configures the receive frame sync (AFSR)." bitfld.long 0x0 0. " FSRP ,Receive frame sync polarity select bit." "0,1" bitfld.long 0x0 1. " FSRM ,Receive frame sync generation select bit." "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " FRWID ,Receive frame sync width select bit indicates the width of the receive frame sync (AFSR) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " RMOD ,Receive frame sync mode select bits.0x3 - 0x20: 3-slot TDM to 32-slot TDM mode . 0x21 - 0x17F: Reserved . 0x181 - 0x1FF: Reserved ." textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "MCASP_ACLKRCTL,The receive clock control register () configures the receive bit clock (ACLKR) and the receive clock generator." bitfld.long 0x0 0.--4. " CLKRDIV ,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0.0x2 - 0x1F: Divide-by-3 to divide-by-32 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKRM ,Receive bit clock source bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " CLKRP ,Receive bitstream clock polarity select bit. Note that this bitfield does not have any effect, ifMCASP_ACLKXCTL[6] ASYNC = 0" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKRADJ ,CLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0.If CLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "MCASP_AHCLKRCTL,The receive high-frequency clock control register () configures the receive high-frequency master clock (AHCLKR) and the receive clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR.0x2 - 0xFFF: Divide-by-3 to divide-by-4096 ." bitfld.long 0x0 12.--13. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKRM ,High Freq. RCV clock Source" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKRADJ ,HCLKRDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKRDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x78++0x3 line.long 0x0 "MCASP_RXTDM,The receive TDM time slot register () specifies which TDM time slot the receiver is active." hexmask.long 0x0 0.--31. 1. " RTDMS_31_0 ,Receiver mode during TDM time slot n." group.byte 0x7C++0x3 line.long 0x0 "MCASP_EVTCTLR,Receiver Interrupt control register - controls generation of the MCASP receive interrupt (RINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates RINT." bitfld.long 0x0 0. " ROVRN ,Receiver overrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " RDMAERR ,Receive DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " RDATA ,Receive data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " RSTAFRM ,Receive start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x80++0x3 line.long 0x0 "MCASP_RXSTAT,The receiver status register () provides the receiver status and receive TDM time slot number." bitfld.long 0x0 0. " ROVRN ,Receiver overrun flag. ROVRN is set when the receive serializer is instructed to transfer data from XRSR to RBUF, but the former data in RBUF has not yet been read by the CPU or DMA. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 1. " RSYNCERR ,Unexpected receive frame sync flag. RSYNCERR is set when a new receive frame sync (AFSR) occurs before it is expected. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 2. " RCKFAIL ,Receive clock failure flag. RCKFAIL is set when the receive clock failure detection circuit reports an error. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 3. " RTDMSLOT ,Returns the LSB of RSLOT. Allows a single read ofMCASP_RXSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " RLAST ,Receive last slot flag. RLAST is set along with RDATA, if the current slot is the last slot in a frame. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 5. " RDATA ,Receive data ready flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 6. " RSTAFRM ,Receive start of frame flag. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" bitfld.long 0x0 7. " RDMAERR ,Receive DMA error flag. RDMAERR is set when the CPU or DMA reads more serializers through the DMA port in a given time slot than were programmed as receivers. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect." "0,1" textline " " bitfld.long 0x0 8. " RERR ,RERR bit always returns a logic-OR of: ROVRN | RSYNCERR | RCKFAIL | RDMAERR Allows a single bit to be checked to determine if a receiver error has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "MCASP_RXTDMSLOT,The current receive TDM time slot register () indicates the current time slot for the receive data frame." hexmask.long.word 0x0 0.--8. 1. " RSLOTCNT ,0x0 - 0x17F: Current receive time slot count. Legal values: 0 to 383 (17Fh). TDM function is not supported for > 32 time slots. However, TDM time slot counter may count to 383 when used to receive a DIR block (transferred over TDM format)." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "MCASP_RXCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit." bitfld.long 0x0 0.--3. " RPS ,Receive clock check prescaler value.0x9 - 0xF: Reserved enum=DIVBY8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " RMIN ,0x00 - 0xFF: Receive clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If RCNT is less than RMIN after counting 32 AHCLKR signals, RCKFAIL in RSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " RMAX ,0x00-0xFF: Receive clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 receive high-frequency master clock (AHCLKR) signals have been received. If the current counter value is greater than RMAX after counting 32 AHCLKR signals, RCKFAIL inMCASP_RXSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " RCNT ,0x0 - 0xFF: Receive clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 receive high-frequency master clock (AHCLKR) signals, and stores the count in RCNT until the next measurement is taken." group.byte 0x8C++0x3 line.long 0x0 "MCASP_REVTCTL,Receiver DMA event control register" bitfld.long 0x0 0. " RDATDMA ,Receive data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xA0++0x3 line.long 0x0 "MCASP_GBLCTLX,Alias of GBLCTL. When writing to this register, only the TRANSMIT bits of GBLCTL are affected (This means GBLCTL bits 8,9,10,11,12.). Reads return GBLCTL." bitfld.long 0x0 0. " RCLKRST ,RCV clock divder reset" "0,1" bitfld.long 0x0 1. " RHCLKRST ,RCV High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 2. " RSRCLKR ,RCV serializer clear" "0,1" bitfld.long 0x0 3. " RSMRST ,RCV state machine reset" "0,1" textline " " bitfld.long 0x0 4. " RFRST ,Frame sync generator reset" "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " XCLKRST ,XMT clock divder reset" "0,1" bitfld.long 0x0 9. " XHCLKRST ,XMT High Freq. clk Divider" "0,1" textline " " bitfld.long 0x0 10. " XSRCLR ,XMT serializer clear" "0,1" bitfld.long 0x0 11. " XSMRST ,XMT state machine reset" "0,1" textline " " bitfld.long 0x0 12. " XFRST ,Frame sync generator reset" "0,1" hexmask.long.tbyte 0x0 13.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "MCASP_TXMASK,Transmit format unit bit mask register - Determines which bits of the transmitted data are masked off before being shifted out the MCASP" hexmask.long 0x0 0.--31. 1. " XMASK_31_0 ,Transmit data mask enable bit" group.byte 0xA8++0x3 line.long 0x0 "MCASP_TXFMT,Transmit bitstream format register - configures the transmit data format" bitfld.long 0x0 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " XBUSEL ,Selects whether writes to the serializer buffer XBUF[n] originate from the peripheral configuration CFG port or the DATA port." "0,1" textline " " bitfld.long 0x0 4.--7. " XSSZ ,Transmit slot size0x0 - 0x2 : Reserved enum=RSV8 ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--12. " XPBIT ,XPBIT value determines which bit (as written by the CPU or DMA to XBUF[n]) is used to pad the extra bits before shifting. This field only applies when XPAD = 0x2." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to word defined by XMASK. This field only applies to bits when XMASK[n] = 0." "0,1,2,3" bitfld.long 0x0 15. " XRVRS ,Transmit serial bitstream order" "0,1" textline " " bitfld.long 0x0 16.--17. " XDATDLY ,Transmit sync bit delay" "0,1,2,3" hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reserved" group.byte 0xAC++0x3 line.long 0x0 "MCASP_TXFMCTL,Transmit frame-sync control register - configures the transmit frame sync (mcaspi_fsx)." bitfld.long 0x0 0. " FSXP ,Transmit frame-sync polarity select bit" "0,1" bitfld.long 0x0 1. " FSXM ,Transmit frame-sync generation select bit" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 4. " FXWID ,The transmit frame-sync width select bit indicates the width of the transmit frame sync (mcaspi_fsx) during its active period." "0,1" textline " " bitfld.long 0x0 5.--6. " RESERVED ,Reserved" "0,1,2,3" hexmask.long.word 0x0 7.--15. 1. " XMOD ,Transmit frame-sync mode select bits 0x0: Burst mode 0x1: Reserved 0x2: 2-slot TDM mode () 0x3 - 0x20: 3-slot TDM to 32-slot TDM mode 0x21 - 0x17F: Reserved 0x180: 384-slot DIT mode All other: Reserved" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "MCASP_ACLKXCTL,Transmit clock control register - Configures the transmit bit clock (mcaspi_aclkx) and the transmit clock generator." bitfld.long 0x0 0.--4. " CLKXDIV ,Transmit bit clock divide ratio bits, determine the divide-down ratio from AHCLKX to ACLKX. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0x1F: Divide-by-3 to divide-by-32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " CLKXM ,Transmit bit clock source bit" "0,1" textline " " bitfld.long 0x0 6. " ASYNC ,Transmit operation asynchronous enable bit" "0,1" bitfld.long 0x0 7. " CLKXP ,Transmit bitstream clock polarity select bit." "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--17. " CLKXADJ ,CLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If CLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" textline " " bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" textline " " bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB4++0x3 line.long 0x0 "MCASP_AHCLKXCTL,High-frequency transmit clock control register - Configures the transmit high-frequency master clock (mcaspi_ahclkx) and the transmit clock generator." hexmask.long.word 0x0 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to mcaspi_ahclkx. 0x0: Divide-by-1 0x1: Divide-by-2 0x2 to 0xFFF: Divide-by-3 to divide-by-4096" bitfld.long 0x0 12.--13. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select bit." "0,1" bitfld.long 0x0 15. " HCLKXM ,Transmit high-frequency clock source bit" "0,1" textline " " bitfld.long 0x0 16.--17. " HCLKXADJ ,HCLKXDIV one-shot adjustment. Not supported. Bit field must always be written as 0x0. If HCLKXDIV is set such that there are m input clocks per one output clock, then for one output cycle:00 = (m+0) input clocks per output clock, i.e. no adjustment . 01 = (m-1) input clocks per output clock . 10 = (m+1) input clocks per output clock . 11 = (m+0) input clocks per output clock, i.e. no adjustment . NOTE: writes to these bits are ineffective if CLKADJEN:ENABLE bit is set to 0b. These bits are ALWAYS read back as zero. ." "0,1,2,3" bitfld.long 0x0 18. " ADJBUSY ,Status: one-shot adjustment in progress? Not supported." "0,1" textline " " bitfld.long 0x0 19. " DIVBUSY ,Status: divide ratio change in progress? Not supported." "0,1" bitfld.long 0x0 20. " BUSY ,Status: logical OR of DIVBUSY, ADJBUSY. Not supported." "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ,Reserved" group.byte 0xB8++0x3 line.long 0x0 "MCASP_TXTDM,Transmit TDM slot 0-31 register - TDM time slot counter range is to 384 slots (to support SPDIF blocks of 384 subframes)." hexmask.long 0x0 0.--31. 1. " XTDMS_31_0 ,Transmitter mode during TDM time slot n (n = 0..31)" group.byte 0xBC++0x3 line.long 0x0 "MCASP_EVTCTLX,Transmitter Interrupt control register - controls generation of the MCASP transmit interrupt (XINT). When the register bit(s) is set to 1, the occurrence of the enabled MCASP condition(s) generates XINT." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun interrupt enable bit" "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync interrupt enable bit" "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure interrupt enable bit" "0,1" bitfld.long 0x0 3. " XDMAERR ,Transmit DMA error interrupt enable bit" "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot interrupt enable bit" "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data-ready interrupt enable bit" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 7. " XSTAFRM ,Transmit start of frame interrupt enable bit" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC0++0x3 line.long 0x0 "MCASP_TXSTAT,Transmitter status register - If the MCASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear it, the MCASP logic has priority and the flag remains set. This also causes the generation of a new interrupt request." bitfld.long 0x0 0. " XUNDRN ,Transmitter underrun flag. XUNDRN is set when the transmit serializer is instructed to transfer data from XBUF[n] to XRSR[n], but XBUF[n] has not yet been serviced with new data since the last transfer. Causes a transmit interrupt (XINT) if this bit and XUNDRN inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 1. " XSYNCERR ,Unexpected transmit frame-sync flag. XSYNCERR is set when a new transmit frame sync (AFSX) occurs before it is expected. Causes a transmit interrupt (XINT) if this bit and XSYNCERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 2. " XCKFAIL ,Transmit clock failure flag. XCKFAIL is set when the transmit clock failure detection circuit reports an error. Causes a transmit interrupt (XINT) if this bit and XCKFAIL inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 3. " XTDMSLOT ,Returns the LSB of XSLOT. Allows a single read of XSTAT to determine whether the current TDM time slot is even or odd." "0,1" textline " " bitfld.long 0x0 4. " XLAST ,Transmit last slot flag. XLAST, along with XDATA, are set if the current slot is the last slot in a frame. Causes a transmit interrupt (XINT) if this bit and XLAST inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect." "0,1" bitfld.long 0x0 5. " XDATA ,Transmit data ready flag. Causes a transmit interrupt (XINT) if this bit and XDATA inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to iit. Writing a 0 has no effect" "0,1" textline " " bitfld.long 0x0 6. " XSTAFRM ,Transmit start of frame flag. Causes a transmit interrupt (XINT) if this bit and XSTAFRM inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" bitfld.long 0x0 7. " XDMAERR ,Transmit DMA error flag. XDMAERR is set when the CPU or DMA writes more words to the DATA port of the MCASP in a given time slot than it should. Causes a transmit interrupt (XINT) if this bit and XDMAERR inMCASP_EVTCTLX are set. This bit is cleared by writing a 1 to it. Writing a 0 has no effect." "0,1" textline " " bitfld.long 0x0 8. " XERR ,XERR bit always returns a logic-OR of: XUNDRN | XSYNCERR | XCKFAIL | XDMAERR. Allows a single bit to be checked to determine if a transmitter error interrupt has occurred." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "MCASP_TXTDMSLOT,Current transmit TDM time slot register" hexmask.long.word 0x0 0.--8. 1. " XSLOTCNT ,Current transmit time slot count. the value of this register is 0b0101111111 (0x17f) during reset and 0 after reset." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC8++0x3 line.long 0x0 "MCASP_TXCLKCHK,Transmit clock check control register - configures the transmit clock failure detection circuit." bitfld.long 0x0 0.--3. " XPS ,Transmit clock check prescaler value 0x0: MCASP interface clock divided by 1 0x1: MCASP interface clock divided by 2 0x2: MCASP interface clock divided by 4 0x3: MCASP interface clock divided by 8 0x4: MCASP interface clock divided by 16 0x5: MCASP interface clock divided by 32 0x6: MCASP interface clock divided by 64 0x7: MCASP interface clock divided by 128 0x8: MCASP interface clock divided by 256 0x9 to 0xF: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 8.--15. 1. " XMIN ,0x0 to 0xFF: Transmit clock minimum boundary. This 8-bit unsigned value sets the minimum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If XCNT is less than XMIN after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." hexmask.long.byte 0x0 16.--23. 1. " XMAX ,0x0 to 0xFF: Transmit clock maximum boundary. This 8-bit unsigned value sets the maximum allowed boundary for the clock check counter after 32 transmit high-frequency master clock (mcaspi_ahclkx) signals have been received. If the current counter value is greater than XMAX after counting 32 AHCLKX signals, XCKFAIL in XSTAT is set. The comparison is performed using unsigned arithmetic." textline " " hexmask.long.byte 0x0 24.--31. 1. " XCNT ,Transmit clock count value (from previous measurement). The clock circuit continually counts the number of interface clocks for every 32 transmit high-frequency master clock (mcaspi_ahclkx) signals, and stores the count in XCNT until the next measurement is taken" group.byte 0xCC++0x3 line.long 0x0 "MCASP_XEVTCTL,Transmitter DMA event control register" bitfld.long 0x0 0. " XDATDMA ,Transmit data DMA request enable bit." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0xD0++0x3 line.long 0x0 "MCASP_CLKADJEN,One-Shot Clock Adjustment Enable" bitfld.long 0x0 0. " ENABLE ,One-shot clock adjust enable. Not supported. Bit field must always be written as 0x0." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "MCASP_DITCSRAi_0,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x104++0x3 line.long 0x0 "MCASP_DITCSRAi_1,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x108++0x3 line.long 0x0 "MCASP_DITCSRAi_2,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x10C++0x3 line.long 0x0 "MCASP_DITCSRAi_3,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x110++0x3 line.long 0x0 "MCASP_DITCSRAi_4,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x114++0x3 line.long 0x0 "MCASP_DITCSRAi_5,DIT left channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRAi ,Left (even TDM slot ) channel status" group.byte 0x118++0x3 line.long 0x0 "MCASP_DITCSRBi_0,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x11C++0x3 line.long 0x0 "MCASP_DITCSRBi_1,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x120++0x3 line.long 0x0 "MCASP_DITCSRBi_2,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x124++0x3 line.long 0x0 "MCASP_DITCSRBi_3,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x128++0x3 line.long 0x0 "MCASP_DITCSRBi_4,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x12C++0x3 line.long 0x0 "MCASP_DITCSRBi_5,DIT right channel status register - All six 32-bit registers (i = 0 to 5) can store 192 bits of channel status data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register file before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITCSRBi ,Right (odd TDM slot ) channel status" group.byte 0x130++0x3 line.long 0x0 "MCASP_DITUDRAi_0,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x134++0x3 line.long 0x0 "MCASP_DITUDRAi_1,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x138++0x3 line.long 0x0 "MCASP_DITUDRAi_2,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x13C++0x3 line.long 0x0 "MCASP_DITUDRAi_3,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x140++0x3 line.long 0x0 "MCASP_DITUDRAi_4,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x144++0x3 line.long 0x0 "MCASP_DITUDRAi_5,DIT left channel user data register - provides the user data of each left channel (even TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRAi ,Left (even TDM slot ) user data" group.byte 0x148++0x3 line.long 0x0 "MCASP_DITUDRBi_0,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x14C++0x3 line.long 0x0 "MCASP_DITUDRBi_1,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x150++0x3 line.long 0x0 "MCASP_DITUDRBi_2,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x154++0x3 line.long 0x0 "MCASP_DITUDRBi_3,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x158++0x3 line.long 0x0 "MCASP_DITUDRBi_4,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x15C++0x3 line.long 0x0 "MCASP_DITUDRBi_5,DIT right user data register - provides the user data of each right channel (odd TDM time slot). All six 32-bit registers (i = 0 to 5) can store 192 bits of user data for a complete block of transmission. The DIT reuses the same data for the next block. Make sure to update the register before a different set of data needs to be sent." hexmask.long 0x0 0.--31. 1. " DITUDRBi ,Right (odd TDM slot ) user data" group.byte 0x180++0x3 line.long 0x0 "MCASP_XRSRCTLn_0,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x184++0x3 line.long 0x0 "MCASP_XRSRCTLn_1,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x188++0x3 line.long 0x0 "MCASP_XRSRCTLn_2,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x18C++0x3 line.long 0x0 "MCASP_XRSRCTLn_3,Serializer n control register." bitfld.long 0x0 0.--1. " SRMOD ,Serializer mode bit" "0,1,2,3" bitfld.long 0x0 2.--3. " DISMOD ,Serializer pin drive mode bit. Drive on pin when in inactive TDM slot of transmit mode or when serializer is inactive. This field only applies if the pin is configured as a MCASP pin (PFUNC = 0)." "0,1,2,3" textline " " bitfld.long 0x0 4. " XRDY ,Transmit buffer ready bit. XRDY indicates the current transmit buffer state. Always reads 0 when programmed as a receiver or as inactive. If SRMOD bit is set to transmit (1h), XRDY switches from 0 to 1 when XSRCLR in GBLCTL is switched from 0 to 1 to indicate an empty transmitter. XRDY remains set until XSRCLR is forced to 0, data is written to the corresponding transmit buffer, or SRMOD bit is changed to receive (2h) or inactive (0)." "0,1" bitfld.long 0x0 5. " RRDY ,Receive buffer ready bit. RRDY indicates the current receive buffer state. Always reads 0 when programmed as a transmitter or as inactive. If SRMOD bit is set to receive (2h), RRDY switches from 0 to 1 whenever data is transferred from XRSRn to RBUFn." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x200++0x3 line.long 0x0 "MCASP_TXBUFn_0,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x204++0x3 line.long 0x0 "MCASP_TXBUFn_1,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x208++0x3 line.long 0x0 "MCASP_TXBUFn_2,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x20C++0x3 line.long 0x0 "MCASP_TXBUFn_3,Transmit buffer n - The transmit buffer for the serializer n holds data from the transmit format unit." hexmask.long 0x0 0.--31. 1. " XBUFn ,Transmit buffer n" group.byte 0x280++0x3 line.long 0x0 "MCASP_RXBUFn_0,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x284++0x3 line.long 0x0 "MCASP_RXBUFn_1,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x288++0x3 line.long 0x0 "MCASP_RXBUFn_2,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" group.byte 0x28C++0x3 line.long 0x0 "MCASP_RXBUFn_3,Receive buffer n - The receive buffer for the serializer n holds data before the data goes to the receive format unit." hexmask.long 0x0 0.--31. 1. " RBUFn ,Receive Buffer n" width 0x0B tree.end tree "MCASP1_AFIFO" base ad:0x48461000 width 10. group.byte 0x0++0x3 line.long 0x0 "WFIFOCTL,The Write FIFO control register. The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " WNUMDMA ,Write word count (32-bit words). On the transmit DMA event from McASP the WNUMDMA word will be transferred from DMA engine to McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the write FIFO.0x3 - 0x10: 3 to 16 words. . 0x11 - 0xFF: Reserved. ." hexmask.long.byte 0x0 8.--15. 1. " WNUMEVT ,Write word count (32-bit) to generate TX event to host. When Write FIFO has word space for more or equal to this value then transmit event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." textline " " bitfld.long 0x0 16. " WENA ,Write FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "WFIFOSTS,The Write FIFO status register." hexmask.long.byte 0x0 0.--7. 1. " WLVL ,Write level (read-only). Number of 32-bit words currently in write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "RFIFOCTL,The Read FIFO control register. The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " RNUMDMA ,Read word count (32-bit words). On receive DMA event from McASP, the DMA engine will read specified number of words from McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the read FIFO.0x3 - 0x10: 3-16 words . 0x11 - 0xFF: Reserved ." hexmask.long.byte 0x0 8.--15. 1. " RNUMEVT ,Read word count (32-bit) to generate RX event to host. When Read FIFO has number of word available which is more or equal to this value then receive event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved ." textline " " bitfld.long 0x0 16. " RENA ,Read FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0 0.--7. 1. " RLVL ,Read level (read-only). Number of 32-bit words currently in read FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCASP2_AFIFO" base ad:0x48465000 width 10. group.byte 0x0++0x3 line.long 0x0 "WFIFOCTL,The Write FIFO control register. The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " WNUMDMA ,Write word count (32-bit words). On the transmit DMA event from McASP the WNUMDMA word will be transferred from DMA engine to McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the write FIFO.0x3 - 0x10: 3 to 16 words. . 0x11 - 0xFF: Reserved. ." hexmask.long.byte 0x0 8.--15. 1. " WNUMEVT ,Write word count (32-bit) to generate TX event to host. When Write FIFO has word space for more or equal to this value then transmit event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." textline " " bitfld.long 0x0 16. " WENA ,Write FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "WFIFOSTS,The Write FIFO status register." hexmask.long.byte 0x0 0.--7. 1. " WLVL ,Write level (read-only). Number of 32-bit words currently in write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "RFIFOCTL,The Read FIFO control register. The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " RNUMDMA ,Read word count (32-bit words). On receive DMA event from McASP, the DMA engine will read specified number of words from McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the read FIFO.0x3 - 0x10: 3-16 words . 0x11 - 0xFF: Reserved ." hexmask.long.byte 0x0 8.--15. 1. " RNUMEVT ,Read word count (32-bit) to generate RX event to host. When Read FIFO has number of word available which is more or equal to this value then receive event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved ." textline " " bitfld.long 0x0 16. " RENA ,Read FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0 0.--7. 1. " RLVL ,Read level (read-only). Number of 32-bit words currently in read FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCASP3_AFIFO" base ad:0x48469000 width 10. group.byte 0x0++0x3 line.long 0x0 "WFIFOCTL,The Write FIFO control register. The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " WNUMDMA ,Write word count (32-bit words). On the transmit DMA event from McASP the WNUMDMA word will be transferred from DMA engine to McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the write FIFO.0x3 - 0x10: 3 to 16 words. . 0x11 - 0xFF: Reserved. ." hexmask.long.byte 0x0 8.--15. 1. " WNUMEVT ,Write word count (32-bit) to generate TX event to host. When Write FIFO has word space for more or equal to this value then transmit event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." textline " " bitfld.long 0x0 16. " WENA ,Write FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "WFIFOSTS,The Write FIFO status register." hexmask.long.byte 0x0 0.--7. 1. " WLVL ,Write level (read-only). Number of 32-bit words currently in write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "RFIFOCTL,The Read FIFO control register. The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " RNUMDMA ,Read word count (32-bit words). On receive DMA event from McASP, the DMA engine will read specified number of words from McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the read FIFO.0x3 - 0x10: 3-16 words . 0x11 - 0xFF: Reserved ." hexmask.long.byte 0x0 8.--15. 1. " RNUMEVT ,Read word count (32-bit) to generate RX event to host. When Read FIFO has number of word available which is more or equal to this value then receive event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved ." textline " " bitfld.long 0x0 16. " RENA ,Read FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0 0.--7. 1. " RLVL ,Read level (read-only). Number of 32-bit words currently in read FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCASP4_AFIFO" base ad:0x4846D000 width 10. group.byte 0x0++0x3 line.long 0x0 "WFIFOCTL,The Write FIFO control register. The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " WNUMDMA ,Write word count (32-bit words). On the transmit DMA event from McASP the WNUMDMA word will be transferred from DMA engine to McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the write FIFO.0x3 - 0x10: 3 to 16 words. . 0x11 - 0xFF: Reserved. ." hexmask.long.byte 0x0 8.--15. 1. " WNUMEVT ,Write word count (32-bit) to generate TX event to host. When Write FIFO has word space for more or equal to this value then transmit event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." textline " " bitfld.long 0x0 16. " WENA ,Write FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "WFIFOSTS,The Write FIFO status register." hexmask.long.byte 0x0 0.--7. 1. " WLVL ,Write level (read-only). Number of 32-bit words currently in write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "RFIFOCTL,The Read FIFO control register. The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " RNUMDMA ,Read word count (32-bit words). On receive DMA event from McASP, the DMA engine will read specified number of words from McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the read FIFO.0x3 - 0x10: 3-16 words . 0x11 - 0xFF: Reserved ." hexmask.long.byte 0x0 8.--15. 1. " RNUMEVT ,Read word count (32-bit) to generate RX event to host. When Read FIFO has number of word available which is more or equal to this value then receive event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved ." textline " " bitfld.long 0x0 16. " RENA ,Read FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0 0.--7. 1. " RLVL ,Read level (read-only). Number of 32-bit words currently in read FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCASP5_AFIFO" base ad:0x48471000 width 10. group.byte 0x0++0x3 line.long 0x0 "WFIFOCTL,The Write FIFO control register. The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " WNUMDMA ,Write word count (32-bit words). On the transmit DMA event from McASP the WNUMDMA word will be transferred from DMA engine to McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the write FIFO.0x3 - 0x10: 3 to 16 words. . 0x11 - 0xFF: Reserved. ." hexmask.long.byte 0x0 8.--15. 1. " WNUMEVT ,Write word count (32-bit) to generate TX event to host. When Write FIFO has word space for more or equal to this value then transmit event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." textline " " bitfld.long 0x0 16. " WENA ,Write FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "WFIFOSTS,The Write FIFO status register." hexmask.long.byte 0x0 0.--7. 1. " WLVL ,Write level (read-only). Number of 32-bit words currently in write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "RFIFOCTL,The Read FIFO control register. The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " RNUMDMA ,Read word count (32-bit words). On receive DMA event from McASP, the DMA engine will read specified number of words from McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the read FIFO.0x3 - 0x10: 3-16 words . 0x11 - 0xFF: Reserved ." hexmask.long.byte 0x0 8.--15. 1. " RNUMEVT ,Read word count (32-bit) to generate RX event to host. When Read FIFO has number of word available which is more or equal to this value then receive event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved ." textline " " bitfld.long 0x0 16. " RENA ,Read FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0 0.--7. 1. " RLVL ,Read level (read-only). Number of 32-bit words currently in read FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCASP6_AFIFO" base ad:0x48475000 width 10. group.byte 0x0++0x3 line.long 0x0 "WFIFOCTL,The Write FIFO control register. The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " WNUMDMA ,Write word count (32-bit words). On the transmit DMA event from McASP the WNUMDMA word will be transferred from DMA engine to McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the write FIFO.0x3 - 0x10: 3 to 16 words. . 0x11 - 0xFF: Reserved. ." hexmask.long.byte 0x0 8.--15. 1. " WNUMEVT ,Write word count (32-bit) to generate TX event to host. When Write FIFO has word space for more or equal to this value then transmit event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." textline " " bitfld.long 0x0 16. " WENA ,Write FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "WFIFOSTS,The Write FIFO status register." hexmask.long.byte 0x0 0.--7. 1. " WLVL ,Write level (read-only). Number of 32-bit words currently in write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "RFIFOCTL,The Read FIFO control register. The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " RNUMDMA ,Read word count (32-bit words). On receive DMA event from McASP, the DMA engine will read specified number of words from McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the read FIFO.0x3 - 0x10: 3-16 words . 0x11 - 0xFF: Reserved ." hexmask.long.byte 0x0 8.--15. 1. " RNUMEVT ,Read word count (32-bit) to generate RX event to host. When Read FIFO has number of word available which is more or equal to this value then receive event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved ." textline " " bitfld.long 0x0 16. " RENA ,Read FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0 0.--7. 1. " RLVL ,Read level (read-only). Number of 32-bit words currently in read FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCASP7_AFIFO" base ad:0x48479000 width 10. group.byte 0x0++0x3 line.long 0x0 "WFIFOCTL,The Write FIFO control register. The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " WNUMDMA ,Write word count (32-bit words). On the transmit DMA event from McASP the WNUMDMA word will be transferred from DMA engine to McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the write FIFO.0x3 - 0x10: 3 to 16 words. . 0x11 - 0xFF: Reserved. ." hexmask.long.byte 0x0 8.--15. 1. " WNUMEVT ,Write word count (32-bit) to generate TX event to host. When Write FIFO has word space for more or equal to this value then transmit event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." textline " " bitfld.long 0x0 16. " WENA ,Write FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "WFIFOSTS,The Write FIFO status register." hexmask.long.byte 0x0 0.--7. 1. " WLVL ,Write level (read-only). Number of 32-bit words currently in write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "RFIFOCTL,The Read FIFO control register. The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " RNUMDMA ,Read word count (32-bit words). On receive DMA event from McASP, the DMA engine will read specified number of words from McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the read FIFO.0x3 - 0x10: 3-16 words . 0x11 - 0xFF: Reserved ." hexmask.long.byte 0x0 8.--15. 1. " RNUMEVT ,Read word count (32-bit) to generate RX event to host. When Read FIFO has number of word available which is more or equal to this value then receive event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved ." textline " " bitfld.long 0x0 16. " RENA ,Read FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0 0.--7. 1. " RLVL ,Read level (read-only). Number of 32-bit words currently in read FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MCASP8_AFIFO" base ad:0x4847D000 width 10. group.byte 0x0++0x3 line.long 0x0 "WFIFOCTL,The Write FIFO control register. The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO. If the Write FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " WNUMDMA ,Write word count (32-bit words). On the transmit DMA event from McASP the WNUMDMA word will be transferred from DMA engine to McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the write FIFO.0x3 - 0x10: 3 to 16 words. . 0x11 - 0xFF: Reserved. ." hexmask.long.byte 0x0 8.--15. 1. " WNUMEVT ,Write word count (32-bit) to generate TX event to host. When Write FIFO has word space for more or equal to this value then transmit event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." textline " " bitfld.long 0x0 16. " WENA ,Write FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "WFIFOSTS,The Write FIFO status register." hexmask.long.byte 0x0 0.--7. 1. " WLVL ,Write level (read-only). Number of 32-bit words currently in write FIFO.0x3 - 0x40: 3 to 64 words currently in write FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "RFIFOCTL,The Read FIFO control register. The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO. If the Read FIFO is to be enabled, it must be enabled prior to taking the McASP out of reset." hexmask.long.byte 0x0 0.--7. 1. " RNUMDMA ,Read word count (32-bit words). On receive DMA event from McASP, the DMA engine will read specified number of words from McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the read FIFO.0x3 - 0x10: 3-16 words . 0x11 - 0xFF: Reserved ." hexmask.long.byte 0x0 8.--15. 1. " RNUMEVT ,Read word count (32-bit) to generate RX event to host. When Read FIFO has number of word available which is more or equal to this value then receive event will be generated to host/DMA. This value must be set prior to enabling the write FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved ." textline " " bitfld.long 0x0 16. " RENA ,Read FIFO enable bit." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "RFIFOSTS,The Read FIFO status register" hexmask.long.byte 0x0 0.--7. 1. " RLVL ,Read level (read-only). Number of 32-bit words currently in read FIFO.0x3 - 0x40: 3 to 64 words currently in read FIFO. . 0x41 - 0xFF: Reserved. ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "DWC_ahsata" base ad:0x4A140000 width 16. group.byte 0x0++0x3 line.long 0x0 "SATA_CAP,Capabilities register: Basic capabilities of the SATA AHCI core. Some fields can be written once after reset, read-only." bitfld.long 0x0 0.--4. " NP ,Number of ports: ports supported by the SATA controller, minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " SXS ,Supports external SATA" "0,1" textline " " bitfld.long 0x0 6. " EMS ,Enclosure management supported" "0,1" bitfld.long 0x0 7. " CCCS ,Command completion coalescing supported" "0,1" textline " " bitfld.long 0x0 8.--12. " NCS ,Number of command slots: slots supported by the SATA controller, minus 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13. " PSC ,PARTIAL state capable Support of transitions to the interface PARTIAL power management state" "0,1" textline " " bitfld.long 0x0 14. " SSC ,SLUMBER state capable Support of transitions to the interface SLUMBER power management state" "0,1" bitfld.long 0x0 15. " PMD ,PIO Multiple DRQ Support of multiple DRQ block data transfers for the PIO command protocol" "0,1" textline " " bitfld.long 0x0 16. " FBSS ,FIS-based switching supported Support of PM FIS-based switching." "0,1" bitfld.long 0x0 17. " SPM ,Supports PM (Port Multiplier) SATA controller supports command-based switching PM on any port." "0,1" textline " " bitfld.long 0x0 18. " SAM ,Supports AHCI mode only SATA controller supports AHCI mode only and does not support legacy, task file-based register interface." "0,1" bitfld.long 0x0 19. " SNZO ,Supports Non-zero DMA offsets" "0,1" textline " " bitfld.long 0x0 20.--23. " ISS ,Interface speed support Maximum speed the HBA can support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " SCLO ,Supports command list override Supports the SATA_PxCMD.CLO bit functionality for enumeration of PM devices" "0,1" textline " " bitfld.long 0x0 25. " SAL ,Supports Activity LED" "0,1" bitfld.long 0x0 26. " SALP ,Supports aggressive link power management" "0,1" textline " " bitfld.long 0x0 27. " SSS ,Supports staggered spin-up Controller can support this feature through SATA_PxCMD.SUD Writable once after power up, read-only afterward" "0,1" bitfld.long 0x0 28. " SMPS ,Supports mechanical presence switch Support of a mechanical presence switch for hot plug operation, depending on integration Writable once after power up, read-only afterward" "0,1" textline " " bitfld.long 0x0 29. " SSNTF ,Supports SNotification register Controller supports SATA_PxSNTF (SNotification) register and its associated functionality." "0,1" bitfld.long 0x0 30. " SNCQ ,Supports NCQ (Native Command Queuing) Controller supports SATA NCQ by handling DMA setup FIS natively." "0,1" textline " " bitfld.long 0x0 31. " S64A ,Supports 64-bit addressing" "0,1" group.byte 0x4++0x3 line.long 0x0 "SATA_GHC,Global HBA control" bitfld.long 0x0 0. " HR ,HBA reset Global reset control" "0,1" bitfld.long 0x0 1. " IE ,Interrupt enable Global enable of SATA controller interrupts. Reset on global reset (SATA_GHC.HR = 1)." "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ," bitfld.long 0x0 31. " AE ,AHCI enable Always set because SATA controller supports AHCI mode only, as indicated by the SATA_CAP.SAM = 1" "0,1" group.byte 0x8++0x3 line.long 0x0 "SATA_IS,Interrupt status Indicates which port has a pending interrupt" bitfld.long 0x0 0. " IPS ,Interrupt pending status. Bit-significant field. Bits are set by ports that have interrupt events pending in the SATA_PxIS bits and enabled in SATA_PxIE. Set bits are cleared by software writing 1 to them." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "SATA_PI,Ports implemented Indicates which ports are exposed by the SATA controller and available for use" bitfld.long 0x0 0. " PI ,Ports implemented. Bit-significant field. Writable once after power up, read-only afterward. If a bit is set (1), the corresponding port is available; else (0) it is not. Only bits 0 to SATA_CAP.NP can be set to 1. At least one bit must be set to 1." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "SATA_VS,AHCI version supported: 1.3 WARNING: Controller complies fully with AHCI version 1.10 and also complies with AHCI version 1.3 except for FIS-based switching, which is not currently supported." hexmask.long.word 0x0 0.--15. 1. " MNR ,Minor Version Number: 3.00" hexmask.long.word 0x0 16.--31. 1. " MJR ,Major Version Number: 1" group.byte 0x14++0x3 line.long 0x0 "SATA_CCC_CTL,CCC (Command Completion Coalescing) control Used to configure the CCC feature for the SATA controller Reset on global reset" bitfld.long 0x0 0. " EN ,Enable CCC enable" "0,1" bitfld.long 0x0 1.--2. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 3.--7. " INT ,Interrupt Number of the interrupt used by the CCC feature, using the number of ports configured for the core When a CCC interrupt occurs, the SATA_IS.IPS[INT] bit is set to 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 8.--15. 1. " CC ,Command completions Number of command completions necessary to cause a CCC interrupt Loaded prior to enabling CCC, becomes read-only when SATA_CCC_CTL.EN = 10x1 - 0xFF: specifies the number of commands upon which completion a CCC interrupt is generated. The number of commands to complete before interrupt is triggered are selectable within the range ( 1 - 255 ) commands. enum=count1 ." textline " " hexmask.long.word 0x0 16.--31. 1. " TV ,Time-out value. Specifies the CCC time-out value in 1-ms intervals Loaded prior to enabling CCC; becomes read-only when SATA_CCC_CTL.EN = 10x1 - 0xFFFF: timeout slectable between within the range (1 - 65535 ) ms. enum=1 ." group.byte 0x18++0x3 line.long 0x0 "SATA_CCC_PORTS,CCC ports Specifies the ports that are coalesced as part of the CCC feature when .EN = 1 Reset on global reset" bitfld.long 0x0 0. " PRT ,Ports Bit-significant field Set a bit to 1 to make the corresponding port part of the CCC feature. Bits set to 1 in this register have the same bit set to 1 in register PI." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "SATA_CAP2,Extended capabilities" bitfld.long 0x0 0. " BOH ,BIOS/OS Handoff" "0,1" bitfld.long 0x0 1. " NVMP ,NVMHCI present" "0,1" textline " " bitfld.long 0x0 2. " APST ,Automatic PARTIAL to SLUMBER transitions" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "SATA_BISTAFR,Built-In, Self-Test (BIST) Activate FIS Register Reset on global reset or port reset" hexmask.long.byte 0x0 0.--7. 1. " PD ,Pattern definition Pattern definition field of the received BIST Activate FIS - bits [23:16] of the first DWORD. Puts the SATA controller in one of the listed BIST modes" hexmask.long.byte 0x0 8.--15. 1. " NCP ,Noncompliant pattern Least significant byte of the received BIST Activate FIS second DWORD (bits [7:0]). This value defines the required pattern for far-end transmit-only mode (SATA_BISTAFR.PD =0x80 or 0xA0). If none of the listed values is decoded, the simultaneous switching pattern is transmitted by default." textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "SATA_BISTCR,BIST control register Reset on global reset or port reset" bitfld.long 0x0 0.--3. " PATTERN ,Pattern Defines one of the listed SATA-compliant patterns for far-end retimed/ far-end analog/ near-end analog initiator modes, or noncompliant patterns for transmit-only responder mode when initiated by software writing to the SATA_BISTCR.TXO bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " PV ,Pattern version Selects either short or long version of the SSOP, HTDP, LTDP, LFSCP, COMP pattern" "0,1" textline " " bitfld.long 0x0 5. " FLIP ,Flip disparity Change disparity of the current test pattern to the opposite each time its state is changed by software." "0,1" bitfld.long 0x0 6. " ERREN ,Error enable Allow or filter (disable) PHY internal errors outside the FIS boundary to set corresponding SATA_PxSERR bits" "0,1" textline " " bitfld.long 0x0 7. " RESERVED ," "0,1" bitfld.long 0x0 8. " LLC_SCRAM ,Link layer control, scrambler In normal mode, the function can be changed only during port reset (SATA_PxSCTL.DET = 0x1). Hardwarecleared (enabled) when the port enters a responder far-end transmit BIST mode with scrambling enabled (SATA_BISTAFR.PD = 0x80)." "0,1" textline " " bitfld.long 0x0 9. " LLC_DESCRAM ,Link layer control, descrambler In normal mode, the function can be changed only during port reset (SATA_PxSCTL.DET = 0x1)." "0,1" bitfld.long 0x0 10. " LLC_RPD ,Link layer control, repeat primitive drop In normal mode, the function can be changed only during port reset (SATA_PxSCTL.DET = 0x1)." "0,1" textline " " bitfld.long 0x0 11. " RESERVED ,Only write 0 into this reserved field to avoid undefined results." "0,1" bitfld.long 0x0 12. " SDFE ,Signal detect feature enable Not affected by global reset or port reset" "0,1" textline " " bitfld.long 0x0 13. " ERRLOSSEN ,Always keep this bit at default value." "0,1" bitfld.long 0x0 14. " RESERVED ," "0,1" textline " " bitfld.long 0x0 15. " LLB ,Lab Loopback Mode Masks out phy_sig_det from the OOB detector in BIST Loopback Mode. To exit BIST Loopback mode, clear the register bit then issue COMRESET / receive COMINIT." "0,1" bitfld.long 0x0 16. " NEALB ,Near-end analog loopback This mode should be initiated in the PARTIAL or SLUMBER power state or with the device disconnected from the port PHY (link NOCOMM state). BIST Activate FIS is not sent to the device in this mode." "0,1" textline " " bitfld.long 0x0 17. " CNTCLR ,Counter clear Clears BIST error count registers" "0,1" bitfld.long 0x0 18. " TXO ,Transmit only" "0,1" textline " " bitfld.long 0x0 19. " RESERVED ," "0,1" bitfld.long 0x0 20. " FERLB ,Far-end retimed loopback" "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "SATA_BISTFCTR,BIST frame-information-structure CounT register Received BIST FIS count in the loopback initiator far-end retimed, far-end analog, and near-end analog modes. Updated each time a new BIST FIS is received. Reset by global reset, port reset (COMRESET), or by writing 1 to .CNTCLR Does not roll over and freezes when the FFFF_FFFFh value is reached. It takes approximately 65 hours of continuous BIST operation to reach this value." hexmask.long 0x0 0.--31. 1. " COUNT ,BIST FIS Count" group.byte 0xAC++0x3 line.long 0x0 "SATA_BISTSR,BIST status register Errors detected in the received BIST FIS in the loopback initiator far-end retimed, far-end analog, and near-end analog modes Updated each time a new BIST FIS is received Reset on global reset, port reset (COMRESET), or by writing 1 to .CNTCLR" hexmask.long.word 0x0 0.--15. 1. " FRAMERR ,Frame error count. New value is added to the old value each time a new BIST frame with a CRC error is received. Does not roll over and freezes at FFFFh" hexmask.long.byte 0x0 16.--23. 1. " BRSTERR ,Burst error count. Accumulated each time a burst error condition is detected: DWORD error is detected in the received frame and 1.5 seconds (27,000 frames) passed since the previous burst error was detected. Value does not roll over and freezes at FFh." textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xB0++0x3 line.long 0x0 "SATA_BISTDECR,BIST double-word error count register Number of DWORD errors detected in the received BIST frame in the loopback initiator far-end retimed, far-end analog, and near-end analog modes Updated each time a new BIST frame is received, when the parameter BIST_MODE = DWORD. Reset on global reset, port reset (COMRESET), or by writing 1 to .CNTCLR." hexmask.long 0x0 0.--31. 1. " DWERR ,DWORD error count. New value is added to the old value each time a new BIST frame is received. The DWERR value does not roll over, and freezes when it exceeds 0xFFFF_F000." group.byte 0xBC++0x3 line.long 0x0 "SATA_OOBR,OOB (Out Of Band Register) register Controls the link layer OOB detection counters" hexmask.long.byte 0x0 0.--7. 1. " CIMAX,COMINIT_MAX ,COMINIT_MAX, in OOB rx clock cycles Read-only when SATA_OOBR.WE=0" hexmask.long.byte 0x0 8.--15. 1. " CIMIN,COMINIT_MIN ,COMINIT_MIN, in OOB rx clock cycles Read-only when SATA_OOBR.WE = 0" textline " " hexmask.long.byte 0x0 16.--23. 1. " CWMAX,COMWAKE_MAX ,COMWAKE_MAX, in OOB rx clock cycles Read-only when SATA_OOBR.WE = 0" hexmask.long.byte 0x0 24.--30. 1. " CWMIN,COMWAKE_MIN ,COMWAKE_MIN, in OOB rx clock cycles Read-only when SATA_OOBR.WE = 0" textline " " bitfld.long 0x0 31. " WE ,WRITE_ENABLE" "0,1" group.byte 0xE0++0x3 line.long 0x0 "SATA_TIMER1MS,Timer 1 ms Configuration to generate the 1-ms tick for the CCC logic Must be initialized before using the CCC feature Reset on power up, not affected by global reset" hexmask.long.tbyte 0x0 0.--19. 1. " TIMV ,OCP bus clock frequency in kHz (for example, reset value is 100,000 = 100 MHz)" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0xE8++0x3 line.long 0x0 "SATA_GPARAM1R,Global parameters register 1 Hardware configuration of the DWC AHCI SATA core" bitfld.long 0x0 0.--2. " M_HDATA ,Master Data Bus Width" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. " S_HDATA ,Slave Data Bus Width" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 6. " M_HADDR ,Master address bus width" "0,1" bitfld.long 0x0 7. " S_HADDR ,Slave address bus width" "0,1" textline " " bitfld.long 0x0 8.--9. " AHB_ENDIAN ,Endianness of master and slave" "0,1,2,3" bitfld.long 0x0 10. " RETURN_ERR ,Error response on illegal access" "0,1" textline " " bitfld.long 0x0 11.--12. " PHY_TYPE ,PHY interface type0x2, 0x3: Reserved enum=config ." "0,1,2,3" bitfld.long 0x0 13. " BIST_M ,BIST loopback checking depth" "0,1" textline " " bitfld.long 0x0 14. " LATCH_M ,Test mode lock-up latches" "0,1" bitfld.long 0x0 15.--20. " PHY_STAT ,PHY status width (in bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 21.--26. " PHY_CTRL ,PHY control width (in bits)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 27. " PHY_RST ,PHY reset mode" "0,1" textline " " bitfld.long 0x0 28.--29. " PHY_DATA ,PHY data width (in 8- or 10-bit characters)" "0,1,2,3" bitfld.long 0x0 30. " RX_BUFFER ,RX data buffer implemented" "0,1" textline " " bitfld.long 0x0 31. " ALIGN_M ,RX data alignment" "0,1" group.byte 0xEC++0x3 line.long 0x0 "SATA_GPARAM2R,Global parameters register 2 Hardware configuration of the DWC AHCI SATA core, continued" hexmask.long.word 0x0 0.--8. 1. " RXOOB_CLK ,RX OOB clock frequency, in MHz" bitfld.long 0x0 9. " TX_OOB_M ,TX OOB mode: sequence generation implemented" "0,1" textline " " bitfld.long 0x0 10. " RX_OOB_M ,RX OOB mode: sequence generation implemented" "0,1" bitfld.long 0x0 11. " RXOOB_CLK_M ,RX OOB clocking mode:" "0,1" textline " " bitfld.long 0x0 12. " ENCODE_M ,8b/10b Encoding/decoding implemented in core" "0,1" bitfld.long 0x0 13. " DEV_MP ,Mechanical presence switch implemented in core" "0,1" textline " " bitfld.long 0x0 14. " DEV_CP ,Cold presence detection implemented in core" "0,1" hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "SATA_PPARAMR,Port parameter register Hardware configuration of the DWC AHCI SATA core port selected by .PSEL" bitfld.long 0x0 0.--3. " RXFIFO_DEPTH ,Rx FIFO Depth, in dwords (log2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " TXFIFO_DEPTH ,Tx FIFO Depth, in dwords (log2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " RX_MEM_S ,RX FIFO memory selection:" "0,1" bitfld.long 0x0 9. " RX_MEM_M ,RX FIFO memory mode:" "0,1" textline " " bitfld.long 0x0 10. " TX_MEM_S ,TX FIFO memory selection:" "0,1" bitfld.long 0x0 11. " TX_MEM_M ,TX FIFO memory mode:" "0,1" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0xF4++0x3 line.long 0x0 "SATA_TESTR,Test register Puts the SATA controller slave interface in a test mode and selects a port for BIST operation" bitfld.long 0x0 0. " TEST_IF ,Test interface" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " PSEL ,Port select: Selects the port for BIST operation" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 19.--31. 1. " RESERVED ," group.byte 0xF8++0x3 line.long 0x0 "SATA_VERSIONR,Version register" hexmask.long 0x0 0.--31. 1. " VERSION ,Version of DWC SATA controller, ASCII. See." group.byte 0xFC++0x3 line.long 0x0 "SATA_IDR,ID register, containing the 32-bit Highlander (HL) revision." hexmask.long 0x0 0.--31. 1. " REVISION ,See." group.byte 0x100++0x3 line.long 0x0 "SATA_PxCLB,Port command List base address 32-bit base physical address for the command list for this port. Used when fetching commands to execute. The structure pointed to by this address range is 1 KiB in length." hexmask.long.word 0x0 0.--9. 1. " ZERO ,Always 0 as address is 1 KiB-aligned" hexmask.long.tbyte 0x0 10.--31. 1. " CLB ,Command list base address (bits 31:10)" group.byte 0x104++0x3 line.long 0x0 "SATA_PxCLBU,Port Command List Base Upper address Upper half of the 64-bit base physical address for the command list for this Port. Used when fetching commands to execute. Remains all 0 when in 32-bit mode. Reserved & read-only when CAP.S64A=0" hexmask.long 0x0 0.--31. 1. " CLBU ,Command List Base Upper Address (bits 63:32)" group.byte 0x108++0x3 line.long 0x0 "SATA_PxFB,Port Frame-information-structure Base address 32-bit base physical address for received FISes for this port. The structure pointed to by this address range is 256 bytes in length." hexmask.long.byte 0x0 0.--7. 1. " ZERO ,Always 0 as address is 256-bytes aligned" hexmask.long.tbyte 0x0 8.--31. 1. " FB ,FIS base address (bits 31:8)" group.byte 0x10C++0x3 line.long 0x0 "SATA_PxFBU,FIS Base Upper Address Upper half of the 64-bit base physical address for received FISes for this port. Remains all 0 with a 32-bit SW driver. Reserved & read-only when CAP.S64A=0" hexmask.long 0x0 0.--31. 1. " FBU ,FIS Base Upper Address (bits 63:32)" group.byte 0x110++0x3 line.long 0x0 "SATA_PxIS,Port interrupt status Bits are set by internal conditions and cleared (when possible) by writing 1 to them. Reset on global reset." bitfld.long 0x0 0. " DHRS ,Device to host register FIS interrupt A D2H register FIS is received with the I bit set and copied into system memory." "0,1" bitfld.long 0x0 1. " PSS ,PIO setup FIS interrupt A PIO Setup FIS is received with the I bit set, copied into system memory, and the data related to the FIS is transferred. Note: This bit is set even when the data transfer resulted in an error." "0,1" textline " " bitfld.long 0x0 2. " DSS ,DMA setup FIS interrupt A DMA Setup FIS is received with the I bit set and copied into system memory." "0,1" bitfld.long 0x0 3. " SDBS ,Set device bits interrupt A Set Device Bits FIS is received with the I bit set and copied into system memory." "0,1" textline " " bitfld.long 0x0 4. " UFS ,Unknown FIS interrupt An unknown FIS was received and has been copied into system memory. Cleared to 0 by the software clearing the SATA_PxSERR.DIAG_F bit to 0. Note: The UFS bit does not directly reflect the SATA_PxSERR.DIAG_F bit. SATA_PxSERR.DIAG_F bit is set immediately when an unknown FIS is detected, whereas the UFS bit is set when that FIS is posted to memory. The software should wait to act on an unknown FIS until the UFS bit is set to 1 or the two bits may become out of sync." "0,1" bitfld.long 0x0 5. " DPS ,Descriptor processed A PRD with the I bit set has transferred all of its data. Note. This is an opportunistic interrupt and must not be used to definitively indicate the end of a transfer. Two PRD interrupts could occur close enough together that the second interrupt is missed when the first PRD interrupt is cleared." "0,1" textline " " bitfld.long 0x0 6. " PCS ,Port connect change status This bit reflects the state of the SATA_PxSERR.DIAG_X bit. Cleared only when SATA_PxSERR.DIAG_X is cleared" "0,1" bitfld.long 0x0 7. " DMPS ,Device mechanical presence status Set when the pX_mp_switch input changes its state as a result of a mechanical switch attached to this port opening or closing Valid only when SATA_CAP.SMPS and SATA_PxCMD.MPSP are set" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " PRCS ,PhyRdy change status Reflects the state of SATA_PxSERR.DIAG_N To clear this bit, clear the SATA_PxSERR.DIAG_N bit to 0." "0,1" textline " " bitfld.long 0x0 23. " IPMS ,Incorrect PM status FIS received from a device in which the PM field did not match what was expected May be set during enumeration of devices on a PM due to the normal PM enumeration process Must be used only after enumeration is complete on the PM" "0,1" bitfld.long 0x0 24. " OFS ,Overflow status Set when command list overflow is detected during read or write operation when the software builds command table that has fever total bytes than the transaction given to the device. Port DMA transitions to a fatal state until the software clears SATA_PxCMD.ST bit or resets the interface by way of port reset or global reset." "0,1" textline " " bitfld.long 0x0 25. " RESERVED ," "0,1" bitfld.long 0x0 26. " INFS ,Interface nonfatal error status Set when any of the following conditions is detected: 1) One or more of the following errors are detected during nondata FIS transfer: - 10b to 8b decode error (SATA_PxSERR.DIAG_B) - Protocol (SATA_PxSERR.ERR_P) - CRC (SATA_PxSERR.DIAG_C) - Handshake (SATA_PxSERR.DIAG_H) - PHY not ready (SATA_PxSERR.ERR_C) 2) Command list underflow during read operation (that is, DMA read) when the software builds a command table that has more total bytes than the transaction given to the device. In both cases port operation continues normally. When an error is detected during nondata FIS transmission, this FIS is retransmitted continuously until it succeeds, or until the software times out and resets the interface." "0,1" textline " " bitfld.long 0x0 27. " IFS ,Interface fatal error status This bit is set when any of the following conditions is detected: 1) SYNC escape is received from the device during H2D register or data FIS transmission. 2) One or more of the following errors are detected during data FIS transfer: - 10B to 8B Decode Error (SATA_PxSERR.DIAG_B) - Protocol (SATA_PxSERR.ERR_P) - CRC (SATA_PxSERR.DIAG_C) - Handshake (SATA_PxSERR.DIAG_H) - PHY not ready (SATA_PxSERR.ERR_C) 3) Unknown FIS is received with good CRC, but the length exceeds 64 bytes. 4) PRD table byte count is 0. 5) DMA setup FIS is received with a TAG corresponding to inactive (SATA_PxSACT bit is cleared) command slot. Port DMA transitions to a fatal state until the software clears SATA_PxCMD.ST bit or resets the interface by way of port reset or global reset." "0,1" bitfld.long 0x0 28. " HBDS ,Host bus data error status This bit is always cleared to 0." "0,1" textline " " bitfld.long 0x0 29. " HBFS ,Host bus fatal error status Set when master (DMA) detects an ERROR response from the slave" "0,1" bitfld.long 0x0 30. " TFES ,Task file error status Set whenever the SATA_PxTFD.STS register is updated by the device and the error bit (bit 0) is set." "0,1" textline " " bitfld.long 0x0 31. " CPDS ,Cold port detect status Set when the pX_cp_det input changes its state due to the insertion or removal of a device Valid only if the port supports cold presence detection as indicated by the SATA_PxCMD.CPD bit set to 1." "0,1" group.byte 0x114++0x3 line.long 0x0 "SATA_PxIE,Port interrupt enable Enables and disables the reporting of the corresponding interrupt to system software When a bit is set (1), .IE = 1, and the corresponding interrupt condition in is active, then the SATA controller interrupt output is asserted. When a bit is cleared (0), interrupt sources are still reflected in the status registers. Reset on global reset" bitfld.long 0x0 0. " DHRE ,Device to host register FIS interrupt enable" "0,1" bitfld.long 0x0 1. " PSE ,PIO setup FIS interrupt enable" "0,1" textline " " bitfld.long 0x0 2. " DSE ,DMA setup FIS interrupt enable" "0,1" bitfld.long 0x0 3. " SDBE ,Set device bits interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " UFE ,Unknown FIS interrupt enable" "0,1" bitfld.long 0x0 5. " DPE ,Descriptor processed interrupt enable" "0,1" textline " " bitfld.long 0x0 6. " PCE ,Port connect change enable" "0,1" bitfld.long 0x0 7. " DMPE ,Device mechanical presence enable" "0,1" textline " " hexmask.long.word 0x0 8.--21. 1. " RESERVED ," bitfld.long 0x0 22. " PRCE ,PhyRdy change enable" "0,1" textline " " bitfld.long 0x0 23. " IPME ,Incorrect PM enable" "0,1" bitfld.long 0x0 24. " OFE ,Overflow enable" "0,1" textline " " bitfld.long 0x0 25. " RESERVED ," "0,1" bitfld.long 0x0 26. " INFE ,Interface non fatal error enable" "0,1" textline " " bitfld.long 0x0 27. " IFE ,Interface fatal error enable" "0,1" bitfld.long 0x0 28. " HBDE ,Host bus data error enable" "0,1" textline " " bitfld.long 0x0 29. " HBFE ,Host bus fatal error enable" "0,1" bitfld.long 0x0 30. " TFEE ,Task file error enable" "0,1" textline " " bitfld.long 0x0 31. " CPDE ,Cold port detect enable" "0,1" group.byte 0x118++0x3 line.long 0x0 "SATA_PxCMD,Port command" bitfld.long 0x0 0. " ST ,Start" "0,1" bitfld.long 0x0 1. " SUD ,Spin-up device Writable if SATA_CAP.SSS = 1 (staggered spin-up supported), else read-only 1. Read-only-0 on power-up until SATA_CAP.SSS bit is written with the required value." "0,1" textline " " bitfld.long 0x0 2. " POD ,Power-on device Writable if SATA_PxCMD.CPD = 1 (cold presence detection enabled), otherwise read-only -1." "0,1" bitfld.long 0x0 3. " CLO ,Command list override" "0,1" textline " " bitfld.long 0x0 4. " FRE ,FIS receive enable Must not be set until SATA_PxFB / SATA_PxFBU is programmed with a valid pointer to the FIS receive area Base can be moved after clearing FRE and waiting for FR to clear to 0." "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--12. " CCS ,Current command slot This field is valid when SATA_PxCMD.ST is set to 1 and is set to the command slot value of the command currently issued by the port. When SATA_PxCMD.ST transitions from 1 to 0, this field is reset to 0x00. After SATA_PxCMD.ST transitions from 0 to 1, the highest priority slot to issue from next is command slot 0. After the first command is issued, the highest priority slot to issue from next is SATA_PxCMD.CCS + 1. For example, after the port issues its first command, if CCS = 0x00 and SATA_PxCI is set to 0x3, the next command issued is from command slot 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 13. " MPSS ,Mechanical presence switch state Reports the state of a mechanical presence switch attached to this port as indicated by the pX_mp_switch input state (assuming SATA_CAP.SMPS = 1 and SATA_PxCMD.MPSP = 1) Cleared to 0 when SATA_CAP.SMPS = 0" "0,1" textline " " bitfld.long 0x0 14. " FR ,FIS receive running For details, see Section 10.3.2 of the AHCI specification." "0,1" bitfld.long 0x0 15. " CR ,Command list running For details, see the AHCI state-machine in Section 5.3.2 of the AHCI specification." "0,1" textline " " bitfld.long 0x0 16. " CPS ,Cold presence state Reports whether a device is currently detected on this port as indicated by the pX_cp_det input state (assuming SATA_PxCMD.CPD = 1)." "0,1" bitfld.long 0x0 17. " PMA ,PM attached Software is responsible for detecting the presence of a PM. There is no autodetection." "0,1" textline " " bitfld.long 0x0 18. " HPCP ,Hot plug capable port Writable once after power up, read-only afterward" "0,1" bitfld.long 0x0 19. " MPSP ,Mechanical presence switch attached to port Writable once after power up, read-only afterward" "0,1" textline " " bitfld.long 0x0 20. " CPD ,Cold presence detect Writable once after power up, read-only afterward" "0,1" bitfld.long 0x0 21. " ESP ,External SATA port Writable once after power up, read-only afterward" "0,1" textline " " bitfld.long 0x0 22. " FBSCP ,FIS-based Switching Capable Port May only be set to ?1? if CAP.SPM = CAP.FBSS = 1 (not the case). Writable once after power up, read-only afterwards." "0,1" bitfld.long 0x0 23. " APSTE ,Auto PARTIAL to SLUMBER transition enable" "0,1" textline " " bitfld.long 0x0 24. " ATAPI ,Device is ATAPI Used by the port to determine whether or not to assert pX_act_led output when commands are active." "0,1" bitfld.long 0x0 25. " DLAE ,Drive LED on ATAPI enable" "0,1" textline " " bitfld.long 0x0 26. " ALPE ,Aggressive link power management enable" "0,1" bitfld.long 0x0 27. " ASP ,Aggressive SLUMBER/PARTIAL" "0,1" textline " " bitfld.long 0x0 28.--31. " ICC ,Interface communication control Control of power management states of the interface If the link layer is in the L_IDLE state, writes cause the port to request a transition to a given interface state. If the link layer is not in the L_IDLE state, writes have no effect. When a nonreserved, non-0 (No-Op) value is written, the core performs the action and clears the field back to 0 (Idle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x120++0x3 line.long 0x0 "SATA_PxTFD,Port Task File Data: copies specific fields of the task file when FISes are received" bitfld.long 0x0 0. " STS_ERR ,Status, error Latest copy of the 8-bit task file status register, bit 0 STS_ERR = Error during the transfer" "0,1" bitfld.long 0x0 1.--2. " STS_CS ,Status, command-specific Latest copy of the 8-bit task file status register, bits 2:1" "0,1,2,3" textline " " bitfld.long 0x0 3. " STS_DRQ ,Status, data request Latest copy of the 8-bit task file status register, bit 3 STS_DRQ = Data transfer is requested" "0,1" bitfld.long 0x0 4.--6. " STS_CS2 ,Status, command-specific Latest copy of the 8-bit task file status register, bits 6:4" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " STS_BSY ,Status, busy Latest copy of the 8-bit task file status register, bit 7 STS_BSY = Interface is busy" "0,1" hexmask.long.byte 0x0 8.--15. 1. " ERR ,Err: Latest copy of the task file error register" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "SATA_PxSIG,Port signature: Signature received from a device on the first D2H register FIS. Updated once after a reset sequence." hexmask.long.byte 0x0 0.--7. 1. " SIG_SCR,Signature ,Signature, sector count register" hexmask.long.byte 0x0 8.--15. 1. " SIG_LBAL,Signature ,Signature, LBA low (sector number) register" textline " " hexmask.long.byte 0x0 16.--23. 1. " SIG_LBAM,Signature ,Signature, LBA mid (cylinder low) register" hexmask.long.byte 0x0 24.--31. 1. " SIG_LBAH,Signature ,Signature, LBA high (cylinder high) register" group.byte 0x128++0x3 line.long 0x0 "SATA_PxSSTS,Port SATA status Current state of the interface and host, updated continuously and asynchronously. When the port transmits a COMRESET to the device, this register is updated to its reset values (that is, global reset, port reset, or COMINIT from the device)." bitfld.long 0x0 0.--3. " DET ,Device detection: Interface device detection and PHY state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPD ,Current interface speed: Negotiated interface communication speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " IPM ,Interface power management: Current interface state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x12C++0x3 line.long 0x0 "SATA_PxSCTL,Port SATA control Control of SATA interface capabilities. Writes to this register result in action taken by the port PHY interface. Reads from the register return the last value written to it. Reset on global reset. Wait for at least seven periods of the slower clock (OCP or parallel serdes clock) between writes, due to the internal clock domain crossing between the transport (OCP) and link (serdes I/F) layers." bitfld.long 0x0 0.--3. " DET ,Device detection initialization: Controls the HBA device detection and interface initialization. Can be modified only when SATA_PxCMD.ST = 0. Must have a value of 0x0 when SATA_PxCMD.ST = 1. MSB is always 1'b0 (not writable), as for all unreserved field values." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " SPD ,Speed allowed: Highest allowable speed of the interface The two MSBs are always 2'b00 (not writable), as for all unreserved field values." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " IPM ,Interface power management transitions allowed: Indicates which power states the HBA is allowed to transition to. If an interface power management state is disabled, the HBA is not allowed to initiate that state and the HBA must PMNAK_P any request from the device to enter that state. The two MSBs are always 2'b00 (not writable), as for all unreserved field values." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " SPM ,Select power management: This field is not used by the AHCI." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " PMP ,PM port: This field is not used by the AHCI." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "SATA_PxSERR,Port SATA error Detected interface errors accumulated since the last time it cleared. When set, indicates that the corresponding error condition became true one or more times since the last time cleared. Write 1 to a bit to clear it. Cleared by global reset or port reset (COMRESET)." bitfld.long 0x0 0. " ERR_I ,Recovered data integrity error: Any of the following conditions are set during non-data FIS transfer: - ERR_P (Protocol) - DIAG_C (CRC) - DIAG_H (Handshake) - ERR_C (PHY Ready negation)" "0,1" bitfld.long 0x0 1. " ERR_M ,Recovered communication error: PHY Ready condition is detected after interface initialization, but not after transition from PARTIAL or SLUMBER power management state to ACTIVE state." "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " ERR_T ,Nonrecovered transient data integrity error: Any of the following conditions are set during data FIS transfer: - ERR_P (Protocol) - DIAG_C (CRC) - DIAG_H (Handshake) - ERR_C (PHY Ready negation)" "0,1" textline " " bitfld.long 0x0 9. " ERR_C ,Nonrecovered persistent communication error: PHY Ready signal is negated due to loss of communication with the device or problems with the interface, but not after transition from ACTIVE to PARTIAL or SLUMBER power management state." "0,1" bitfld.long 0x0 10. " ERR_P ,Protocol error: Any of the following conditions: - Transport state transition error (DIAG_T) - Link sequence error (DIAG_S) - RxFIFO overflow - Link bad end error (WTRM instead of EOF received)" "0,1" textline " " bitfld.long 0x0 11. " ERR_E ,Internal error: One or more errors detected on the master (DMA) or the slave (MMR access) interfaces." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DIAG_N ,PhyRdy change: Indicates that the PHY Ready signal changed state. Reflected inSATA_PxIS.PRCS." "0,1" bitfld.long 0x0 17. " DIAG_I ,PHY internal error: Internal error detected by the PHY. Note: If the PHY does not support any errors, this bit is never set." "0,1" textline " " bitfld.long 0x0 18. " DIAG_W ,Comm wake: Comm wake signal detected by the PHY." "0,1" bitfld.long 0x0 19. " DIAG_B ,10bit-to-8bit decode error: Errors detected by the 10b8b decoder. Note: Set only when an error is detected on the received FIS data word. Not set when an error is detected on the primitive, regardless of whether it is inside or outside the FIS." "0,1" textline " " bitfld.long 0x0 20. " DIAG_D ,Disparity error: Not used by AHCI, always 0." "0,1" bitfld.long 0x0 21. " DIAG_C ,CRC error: One ore more CRC errors detected by the link layer during FIS reception." "0,1" textline " " bitfld.long 0x0 22. " DIAG_H ,Handshake error: One or more R-ERRp received in response to frame transmission. May be the result of a CRC error detected by the device, a disparity or 8b/10b decoding error, or other error condition leading to a negative handshake on a transmitted frame." "0,1" bitfld.long 0x0 23. " DIAG_S ,Link sequence error: One or more Link state machine error conditions encountered, including device doing SYNC escape during FIS transmission." "0,1" textline " " bitfld.long 0x0 24. " DIAG_T ,Transport state transition error: Transport Layer protocol violation detected." "0,1" bitfld.long 0x0 25. " DIAG_F ,Unknown FIS type: One or more FISes were received by the transport layer with good CRC, but had a type field that was not recognized/known and the length was = 64 bytes. Note: If the unknown FIS length exceeds 64 bytes, DIAG_F is not set and DIAG_T is set instead." "0,1" textline " " bitfld.long 0x0 26. " DIAG_X ,Exchanged: PHY COMINIT signal detected. Reflected inSATA_PxIS.PCS." "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x134++0x3 line.long 0x0 "SATA_PxSACT,Port SATA active (SActive): Indicates which command slots contain commands." hexmask.long 0x0 0.--31. 1. " DS ,Device status: Field is bit-significant. Each bit corresponds to the TAG and command slot of a native queued command, where bit 0 corresponds to TAG 0 and command slot 0. Set by Software prior to issuing a native queued command for a particular command slot. Prior to writingSATA_PxCI[TAG] to 1, software sets DS[TAG] to 1 to indicate that a command with that TAG is outstanding. The device clears bits by sending a set device bits FIS to the port. The port clears bits in this field that are set to 1 in the SActive field of the set device bits FIS. The port only clears bits that correspond to native queued commands completed successfully. Write only when SATA_PxCMD.ST bit is set to 1. Cleared when SATA_PxCMD.ST is written from 1 to 0. Not cleared by a port reset (COMRESET) or a software reset." group.byte 0x138++0x3 line.long 0x0 "SATA_PxCI,Port command issue: Indicates that a command is constructed and may be carried out." hexmask.long 0x0 0.--31. 1. " CI ,Commands issue: Field is bit-significant. Each bit corresponds to a command slot, where bit 0 corresponds to command slot 0. This field is set by software to indicate to the port that a command is built in system memory for a command slot and may be sent to the device. When the port receives a FIS that clears the BSY, DRQ, and ERR bits for the command, it clears the corresponding bit in this register for that command slot. Bits in this field can only be set to 1 by software whenSATA_PxCMD.ST is set to 1. Also cleared when SATA_PxCMD.ST is written from 1 to 0 by software." group.byte 0x13C++0x3 line.long 0x0 "SATA_PxSNTF,Port SATA notification: Used to determine if asynchronous notification events have occurred for directly connected devices and devices connected to a PM." hexmask.long.word 0x0 0.--15. 1. " PMN ,PM notify: Indicates whether a particular device with the corresponding PM port number issued a set device bits FIS to the SATA controller Port with the notification bit set: - PM Port 0h sets bit 0. - PM Port 0h sets bit 1. - etc. Write 1 to a bit to clear it. Reset on global reset but not on port reset (COMRESET) or software reset." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x170++0x3 line.long 0x0 "SATA_PxDMACR,Port DMA control register. Not AHCI-standard. Writable only when.ST = 0. Attempts to write a field value less than the minimum or more than the maximum cause the field to be set to the minimum or the maximum. Reset on global reset and port reset (COMRESET)" bitfld.long 0x0 0.--3. " TXTS ,Transmit transaction size: DMA transaction size for transmit operations (system bus read, device write)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RXTS ,Receive transaction size: DMA transaction size for receive operations (system bus write, device read)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," width 0x0B tree.end tree "SATAMAC_wrapper" base ad:0x4A141100 width 16. group.byte 0x0++0x3 line.long 0x0 "SATA_SYSCONFIG,This register controls the idle and standby modes of Highlander 08 modules." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, the target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,Configuration of the local initiator-state management mode. By definition, the initiator can generate a read/write transaction as long as it is out of STANDBY state." "0,1,2,3" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " OVERRIDE0 ,Override for clock stopping. Normally the functional clock can be stopped only if the link is put into PARTIAL or SLUMBER power state. However, if there is no device attached (such as in a removable media situation) or the device is not started, the user can stop the functional clocks but not be able to enter a low-power state. In this case, software can set the OVERRIDE bit to 1, removing the requirement for a low-power state WARNING: If there is a device attached, the OVERRIDE bit is used, and the functional clock is stopped when the link is not in a low-power state it ruins the link and causes undetermined behavior. A port reset or full SATASS reset might be required to recover." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "SATA_CDRLOCK,Programmable delay for CDR lock indication" hexmask.long.word 0x0 0.--11. 1. " CDR_LOCK_DELAY ,CDR lock delay, in parallel (10-bit) serdes interface clock cycles. Parallel clock is 300 MHz (3.3 ns period) for SATA-3GT/s, 150 MHz (6.7 ns) for SATA-1.5GT/s." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS1_EP_CFG_PCIe" base ad:0x20000000 width 46. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x0 0.--15. 1. " VENDORID ,Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " DEVICEID ,Device ID (CS)" group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x0 0. " IO_SPACE_EN ,IO Space Enable" "0,1" bitfld.long 0x0 1. " MEM_SPACE_EN ,Memory Space Enable" "0,1" textline " " bitfld.long 0x0 2. " BUSMASTER_EN ,Bus Master Enable" "0,1" bitfld.long 0x0 3. " SPEC_CYCLE_EN ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 4. " MEMWR_INVA ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 5. " VGA_SNOOP ,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 6. " PARITYERRRESP ,Parity Error Response" "0,1" bitfld.long 0x0 7. " IDSEL_CTRL ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 8. " SERR_EN ,SERR Enable" "0,1" bitfld.long 0x0 9. " FAST_BBEN ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 10. " INTX_ASSER_DIS ,INTx Assertion Disable" "0,1" hexmask.long.byte 0x0 11.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " INTX_STATUS ,INTx Status" "0,1" bitfld.long 0x0 20. " CAP_LIST ,Capabilities List Hardwired to 1" "0,1" textline " " bitfld.long 0x0 21. " C66MHZ_CAP ,66MHz Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 23. " FAST_B2B ,Back to Back Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 24. " MASTERDATA_PARERR ,Master Data Parity Error" "0,1" textline " " bitfld.long 0x0 25.--26. " DEVSEL_TIME ,DevSel Timing, Harsdwired to 0 for PCIExpress" "0,1,2,3" bitfld.long 0x0 27. " SIGNAL_TRGTABORT ,Signaled Target Abort" "0,1" textline " " bitfld.long 0x0 28. " RCVD_TRGTABORT ,Received Target Abort" "0,1" bitfld.long 0x0 29. " RCVD_MASTERABORT ,Received Master Abort" "0,1" textline " " bitfld.long 0x0 30. " SIGNAL_SYSERR ,Signaled System Error" "0,1" bitfld.long 0x0 31. " DETECT_PARERR ,Detected Parity Error" "0,1" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x0 0.--7. 1. " REVID ,Revision ID (CS)" hexmask.long.byte 0x0 8.--15. 1. " PROG_IF_CODE ,Programming Interface Code (CS)" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBCLS_CD ,Sub Class Code (CS)" hexmask.long.byte 0x0 24.--31. 1. " BASE_CLS_CD ,Base Class Code (CS)" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BIST_HEAD_LAT_CACH,BIST, Header Type, Latency Timer, Cache Line Size" hexmask.long.byte 0x0 0.--7. 1. " CACH_LN_SZE ,Cache Line Size, No impact on write, write is allowed only for legacy purpose" hexmask.long.byte 0x0 8.--15. 1. " MSTR_LAT_TIM ,Master Latency Timer, Not Applicable for PCIe hence hardwired to 0" textline " " hexmask.long.byte 0x0 16.--22. 1. " HEAD_TYP ,Header Type 0x0 = EP header 0x1 = RC header" bitfld.long 0x0 23. " MFD ,MultiFunction Device" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " BIST ,BIST" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask" group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR1,Base Address Register 1 If BAR0.AS = 64-bit: upper half of BAR0 base address If BAR0.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask." group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR3,Base Address Register 3 If BAR2.AS = 64-bit: upper half of BAR2 base address If BAR2.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.byte 0x0 4.--11. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.tbyte 0x0 12.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask." group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR5,Base Address Register 5 If BAR4.AS = 64-bit: upper half of BAR4 base address If BAR4.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_CARDBUS_CIS_POINTER,PCIECTRL_EP_PCIEWIRE_CARDBUS_CIS_POINTER" hexmask.long 0x0 0.--31. 1. " CARDBUS_CIS_PTR_N ,Cardbus CIS pointer (CS)" group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_SUBID_SUBVENDORID,PCIECTRL_EP_PCIEWIRE_SUBID_SUBVENDORID" hexmask.long.word 0x0 0.--15. 1. " SUBSYS_VENDOR_ID_N ,Subsystem Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " SUBSYS_DEV_ID_N ,Subsystem ID (CS)" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" bitfld.long 0x0 0. " EXROM_EN ,Expansion ROM Enable" "0,1" hexmask.long.word 0x0 1.--10. 1. " RESERVED ," textline " " bitfld.long 0x0 11.--15. " EXROM_ADDRESS_RO ,Expansion ROM address, masked." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--31. 1. " EXROM_ADDRESS ,Expansion ROM address, unmasked (that is, programmable)." group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_CAPPTR,CapPtr" hexmask.long.byte 0x0 0.--7. 1. " CAPTR ,First Capability Pointer (CS)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_INTERRUPT,Int Pin and line" hexmask.long.byte 0x0 0.--7. 1. " INT_LIN ,Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. " INT_PIN ,Interrupt Pin (CS)" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_PM_CAP,Power Management Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PM_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--18. " PMC_VER ,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " PME_CLK ,PME Clock, hardwired to 0 (CS)" "0,1" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21. " DSI ,Device Specific Initialization (CS)" "0,1" textline " " bitfld.long 0x0 22.--24. " AUX_CUR ,AUX Current (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 25. " D1_SP ,D1 Support (CS)" "0,1" textline " " bitfld.long 0x0 26. " D2_SP ,D2 Support (CS)" "0,1" bitfld.long 0x0 27.--31. " PME_SP ,PME Support (CS); Power states from which PME messages can be sent (active hi, one bit per state) Bit 0: from D0 Bit 1: from D1 Bit 2: from D2 Bit 3: from D3hot Bit 4: from D3cold (if Vaux present)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_PM_CSR,Power Management Control and Status Register" bitfld.long 0x0 0.--1. " PWR_STATE ,Device Power State" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " NSR ,No Soft Reset (CS)" "0,1" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PME_EN ,PME Enable (Sticky bit)" "0,1" bitfld.long 0x0 9.--12. " DATA_SEL ,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 13.--14. " DATA_SCALE ,Data Scale (not supported)" "0,1,2,3" bitfld.long 0x0 15. " PME_STATUS ,PME Status (Sticky bit)" "0,1" textline " " bitfld.long 0x0 16.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " B2B3_SP ,B2/B3 Support, hardwired to 0" "0,1" textline " " bitfld.long 0x0 23. " BP_CCE ,Bus Power/Clock Control Enable, hardwired to 0" "0,1" hexmask.long.byte 0x0 24.--31. 1. " DATA1 ,Data register for additional information (not supported)" group.byte 0x70++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_PCIE_CAP,PCIE cap structure" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PCIE_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--19. " PCIE_VER ,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " DEV_TYPE ,Device/Port Type Value depends on assigned type 0x0 = PCIe endpoint 0x1 = Legacy PCIe endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SLOT ,Slot Implemented Must be 0 for an endpoint" "0,1" bitfld.long 0x0 25.--29. " IM_NUM ,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x74++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x0 0.--2. " MAX_PAYLOAD_SIZE ,Maximum Payload Size (CS) Read 0x1 = 256 Byte" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " PHANTOMFUNC ,Phantom Function Support, not SUPPORTED (CS)" "0,1,2,3" textline " " bitfld.long 0x0 5. " EXTTAGFIELD_SUPPORT ,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" bitfld.long 0x0 6.--8. " DEFAULT_EP_L0S_ACCPT_LATENCY ,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " DEFAULT_EP_L1_ACCPT_LATENCY ,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " UNDEFINED ,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ROLEBASED_ERRRPT ,Role Based Error Reporting (CS)" "0,1" bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 18.--25. 1. " CAPT_SLOW_PWRLIMIT_VALUE ,Captured Slow Power Limit Value (CS)" bitfld.long 0x0 26.--27. " CAPT_SLOW_PWRLIMIT_SCALE ,Captured Slow Power Scale Value (CS)" "0,1,2,3" textline " " bitfld.long 0x0 28. " FLR_EN ,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x78++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_DEV_CAS,PCIE Device Control and Status" bitfld.long 0x0 0. " COR_RE ,Correctable Error Reporting Enable" "0,1" bitfld.long 0x0 1. " NFT_RE ,Non-Fatal Error Reporting Enable" "0,1" textline " " bitfld.long 0x0 2. " FT_RE ,Fatal Error Reporting Enable" "0,1" bitfld.long 0x0 3. " UR_RE ,Unsupported Request Reporting Enable" "0,1" textline " " bitfld.long 0x0 4. " EN_RO ,Enable Relaxed Ordering" "0,1" bitfld.long 0x0 5.--7. " MPS ,Max_Payload_Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " EXTAG_EN ,Extended Tag Field Enable" "0,1" bitfld.long 0x0 9. " PHFUN_EN ,Phantom Function Enable" "0,1" textline " " bitfld.long 0x0 10. " AUXPM_EN ,AUX Power PM Enable" "0,1" bitfld.long 0x0 11. " NOSNP_EN ,Enable No Snoop" "0,1" textline " " bitfld.long 0x0 12.--14. " MRRS ,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " INIT_FLR ,Reserved" "0,1" textline " " bitfld.long 0x0 16. " COR_DET ,Correctable Error Detected" "0,1" bitfld.long 0x0 17. " NFT_DET ,Non-Fatal Error Detected" "0,1" textline " " bitfld.long 0x0 18. " FT_DET ,Fatal Error Detected" "0,1" bitfld.long 0x0 19. " UR_DET ,Unsupported Request Detected" "0,1" textline " " bitfld.long 0x0 20. " AUXP_DET ,Aux Power Detected" "0,1" bitfld.long 0x0 21. " TRANS_PEND ,Transaction Pending" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_LNK_CAP,PCIE Link Capabilities" bitfld.long 0x0 0.--3. " MAX_LINK_SPEEDS ,Supported Max Link Speed (CS) 0x1 = 2.5 GT/s (Gen1) 0x2 = 5 GT/s (Gen2) 0x4 = 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--9. " MAX_LINK_WIDTH ,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 10.--11. " AS_LINK_PM_SUPPORT ,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0 12.--14. " L0S_EXIT_LAT ,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " L1_EXIT_LAT ,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18. " CLK_PWR_MGMT ,Clock Power Management (CS)" "0,1" textline " " bitfld.long 0x0 19. " UNSUP ,Unsupported, Surprise Down Error Reporting Capable, Hardwired to 0" "0,1" bitfld.long 0x0 20. " DLL_ACTRPT_CAP ,Data Link Layer Active Reporting Capable" "0,1" textline " " bitfld.long 0x0 21. " LNK_BW_not_CAP ,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0 22. " ASPM_OPT_COMP ,ASPM Optionality Compliance (CS)" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" hexmask.long.byte 0x0 24.--31. 1. " PORT_NUM ,Port Number (CS)" group.byte 0x80++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x0 0.--1. " ASPM_CTRL ,Active State Link PM Control 0x0: DISABLED 0x1: L0S_ENABLED 0x2: L1_ENABLED 0x3: L0S_AND_L1_ENABLED" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " RCB ,Read Completion Boundary (CS) 0x0 = 64 Byte 0x1 = 128 Byte" "0,1" bitfld.long 0x0 4. " LINK_DIS ,Link Disable" "0,1" textline " " bitfld.long 0x0 5. " RETRAIN_LINK ,Retrain Link" "0,1" bitfld.long 0x0 6. " COM_CLK_CFG ,Common Clock Configuration" "0,1" textline " " bitfld.long 0x0 7. " EXT_SYN ,Extended Synch" "0,1" bitfld.long 0x0 8. " EN_CPM ,Enable Clock Power Management" "0,1" textline " " bitfld.long 0x0 9. " HAWD ,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x0 10. " LBMIE ,Link Bandwidth Management Interrupt Enable" "0,1" textline " " bitfld.long 0x0 11. " LABIE ,Link Autonomous Bandwidth Interrupt Enable." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " LINK_SPEED ,Link Speed UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " NEG_LW ,Negotiated Link Width UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 26. " UNDEF ,Undefined" "0,1" bitfld.long 0x0 27. " LINK_TRAIN ,LINK training" "0,1" textline " " bitfld.long 0x0 28. " SLOT_CLK_CONFIG ,Slot Clock Configuration (CS)" "0,1" bitfld.long 0x0 29. " DLL_ACT ,Data Link Layer Active" "0,1" textline " " bitfld.long 0x0 30. " LBW_STATUS ,Link Bandwidth Management Status" "0,1" bitfld.long 0x0 31. " LAB_STATUS ,Link Autonomous Bandwidth Status" "0,1" group.byte 0x94++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_RNG_SUPPORTED ,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS_SUPPORTED ,Completion Timeout Disable Supported" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOR_SP ,AtomicOp Routing Supported" "0,1" textline " " bitfld.long 0x0 7. " AOC32_SP ,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x0 8. " AOC64_SP ,64-bit AtomicOp Completer Supported" "0,1" textline " " bitfld.long 0x0 9. " CASC128_SP ,128-bit CAS Completer Supported" "0,1" bitfld.long 0x0 10. " NOROPR ,No RO-enabled PR-PR Passing" "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " TPHC_SP ,TPH Completer Supported" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_VALUE ,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS ,Completion Timeout Disable" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOP_REQ_EN ,AtomicOp Requester Enable" "0,1" textline " " bitfld.long 0x0 7. " AOP_EG_BLK ,AtomicOp Egress Blocking" "0,1" bitfld.long 0x0 8. " IDO_REQ_EN ,IDO Request Enable" "0,1" textline " " bitfld.long 0x0 9. " IDO_CPL_EN ,IDO Completion Enable" "0,1" bitfld.long 0x0 10. " LTR_EN ,LTR Mechanism Enable" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13.--14. " OBFF_EN ,OBFF Enable" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long.byte 0x0 1.--7. 1. " SP_LS_VEC ,Supported Link Speeds Vector" textline " " bitfld.long 0x0 8. " CROSSLINK_SP ,Crosslink Supported" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0 0.--3. " TRGT_LINK_SPEED ,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENTR_COMPL ,Enter Compliance" "0,1" textline " " bitfld.long 0x0 5. " HW_AUTO_SP_DIS ,Hardware Autonomous Speed Disable" "0,1" bitfld.long 0x0 6. " SEL_DEEMP ,Selectable De-emphasize" "0,1" textline " " bitfld.long 0x0 7.--9. " TX_MARGIN ,Transmit Margin" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. " ENT_MOD_COMPL ,Enter Modified Compliance" "0,1" textline " " bitfld.long 0x0 11. " COMPL_SOS ,Compliance SOS" "0,1" bitfld.long 0x0 12.--15. " COMPL_PRST_DEEPH ,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DEEMPH_LEVEL ,Current De-emphasis Level" "0,1" bitfld.long 0x0 17. " EQ_COMPLETE ,Equalization Complete, Gen3 Only" "0,1" textline " " bitfld.long 0x0 18. " EQ_PH1 ,Equalization Ph1 Success, Gen3 Only" "0,1" bitfld.long 0x0 19. " EQ_PH2 ,Equalization Ph2 Success, Gen3 Only" "0,1" textline " " bitfld.long 0x0 20. " EQ_PH3 ,Equalization Ph3 Success, Gen3 Only" "0,1" bitfld.long 0x0 21. " LINK_EQ_REQ ,Link Equilization Request" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS2_EP_CFG_PCIe" base ad:0x30000000 width 46. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x0 0.--15. 1. " VENDORID ,Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " DEVICEID ,Device ID (CS)" group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x0 0. " IO_SPACE_EN ,IO Space Enable" "0,1" bitfld.long 0x0 1. " MEM_SPACE_EN ,Memory Space Enable" "0,1" textline " " bitfld.long 0x0 2. " BUSMASTER_EN ,Bus Master Enable" "0,1" bitfld.long 0x0 3. " SPEC_CYCLE_EN ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 4. " MEMWR_INVA ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 5. " VGA_SNOOP ,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 6. " PARITYERRRESP ,Parity Error Response" "0,1" bitfld.long 0x0 7. " IDSEL_CTRL ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 8. " SERR_EN ,SERR Enable" "0,1" bitfld.long 0x0 9. " FAST_BBEN ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 10. " INTX_ASSER_DIS ,INTx Assertion Disable" "0,1" hexmask.long.byte 0x0 11.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " INTX_STATUS ,INTx Status" "0,1" bitfld.long 0x0 20. " CAP_LIST ,Capabilities List Hardwired to 1" "0,1" textline " " bitfld.long 0x0 21. " C66MHZ_CAP ,66MHz Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 23. " FAST_B2B ,Back to Back Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 24. " MASTERDATA_PARERR ,Master Data Parity Error" "0,1" textline " " bitfld.long 0x0 25.--26. " DEVSEL_TIME ,DevSel Timing, Harsdwired to 0 for PCIExpress" "0,1,2,3" bitfld.long 0x0 27. " SIGNAL_TRGTABORT ,Signaled Target Abort" "0,1" textline " " bitfld.long 0x0 28. " RCVD_TRGTABORT ,Received Target Abort" "0,1" bitfld.long 0x0 29. " RCVD_MASTERABORT ,Received Master Abort" "0,1" textline " " bitfld.long 0x0 30. " SIGNAL_SYSERR ,Signaled System Error" "0,1" bitfld.long 0x0 31. " DETECT_PARERR ,Detected Parity Error" "0,1" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x0 0.--7. 1. " REVID ,Revision ID (CS)" hexmask.long.byte 0x0 8.--15. 1. " PROG_IF_CODE ,Programming Interface Code (CS)" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBCLS_CD ,Sub Class Code (CS)" hexmask.long.byte 0x0 24.--31. 1. " BASE_CLS_CD ,Base Class Code (CS)" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BIST_HEAD_LAT_CACH,BIST, Header Type, Latency Timer, Cache Line Size" hexmask.long.byte 0x0 0.--7. 1. " CACH_LN_SZE ,Cache Line Size, No impact on write, write is allowed only for legacy purpose" hexmask.long.byte 0x0 8.--15. 1. " MSTR_LAT_TIM ,Master Latency Timer, Not Applicable for PCIe hence hardwired to 0" textline " " hexmask.long.byte 0x0 16.--22. 1. " HEAD_TYP ,Header Type 0x0 = EP header 0x1 = RC header" bitfld.long 0x0 23. " MFD ,MultiFunction Device" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " BIST ,BIST" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask" group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR1,Base Address Register 1 If BAR0.AS = 64-bit: upper half of BAR0 base address If BAR0.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask." group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR3,Base Address Register 3 If BAR2.AS = 64-bit: upper half of BAR2 base address If BAR2.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.byte 0x0 4.--11. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.tbyte 0x0 12.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask." group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_BAR5,Base Address Register 5 If BAR4.AS = 64-bit: upper half of BAR4 base address If BAR4.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0 = BAR type is Memory 0x1 = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_CARDBUS_CIS_POINTER,PCIECTRL_EP_PCIEWIRE_CARDBUS_CIS_POINTER" hexmask.long 0x0 0.--31. 1. " CARDBUS_CIS_PTR_N ,Cardbus CIS pointer (CS)" group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_SUBID_SUBVENDORID,PCIECTRL_EP_PCIEWIRE_SUBID_SUBVENDORID" hexmask.long.word 0x0 0.--15. 1. " SUBSYS_VENDOR_ID_N ,Subsystem Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " SUBSYS_DEV_ID_N ,Subsystem ID (CS)" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" bitfld.long 0x0 0. " EXROM_EN ,Expansion ROM Enable" "0,1" hexmask.long.word 0x0 1.--10. 1. " RESERVED ," textline " " bitfld.long 0x0 11.--15. " EXROM_ADDRESS_RO ,Expansion ROM address, masked." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--31. 1. " EXROM_ADDRESS ,Expansion ROM address, unmasked (that is, programmable)." group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_CAPPTR,CapPtr" hexmask.long.byte 0x0 0.--7. 1. " CAPTR ,First Capability Pointer (CS)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_INTERRUPT,Int Pin and line" hexmask.long.byte 0x0 0.--7. 1. " INT_LIN ,Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. " INT_PIN ,Interrupt Pin (CS)" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_PM_CAP,Power Management Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PM_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--18. " PMC_VER ,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " PME_CLK ,PME Clock, hardwired to 0 (CS)" "0,1" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21. " DSI ,Device Specific Initialization (CS)" "0,1" textline " " bitfld.long 0x0 22.--24. " AUX_CUR ,AUX Current (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 25. " D1_SP ,D1 Support (CS)" "0,1" textline " " bitfld.long 0x0 26. " D2_SP ,D2 Support (CS)" "0,1" bitfld.long 0x0 27.--31. " PME_SP ,PME Support (CS); Power states from which PME messages can be sent (active hi, one bit per state) Bit 0: from D0 Bit 1: from D1 Bit 2: from D2 Bit 3: from D3hot Bit 4: from D3cold (if Vaux present)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_PM_CSR,Power Management Control and Status Register" bitfld.long 0x0 0.--1. " PWR_STATE ,Device Power State" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " NSR ,No Soft Reset (CS)" "0,1" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PME_EN ,PME Enable (Sticky bit)" "0,1" bitfld.long 0x0 9.--12. " DATA_SEL ,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 13.--14. " DATA_SCALE ,Data Scale (not supported)" "0,1,2,3" bitfld.long 0x0 15. " PME_STATUS ,PME Status (Sticky bit)" "0,1" textline " " bitfld.long 0x0 16.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " B2B3_SP ,B2/B3 Support, hardwired to 0" "0,1" textline " " bitfld.long 0x0 23. " BP_CCE ,Bus Power/Clock Control Enable, hardwired to 0" "0,1" hexmask.long.byte 0x0 24.--31. 1. " DATA1 ,Data register for additional information (not supported)" group.byte 0x70++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_PCIE_CAP,PCIE cap structure" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PCIE_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--19. " PCIE_VER ,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " DEV_TYPE ,Device/Port Type Value depends on assigned type 0x0 = PCIe endpoint 0x1 = Legacy PCIe endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SLOT ,Slot Implemented Must be 0 for an endpoint" "0,1" bitfld.long 0x0 25.--29. " IM_NUM ,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x74++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x0 0.--2. " MAX_PAYLOAD_SIZE ,Maximum Payload Size (CS) Read 0x1 = 256 Byte" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " PHANTOMFUNC ,Phantom Function Support, not SUPPORTED (CS)" "0,1,2,3" textline " " bitfld.long 0x0 5. " EXTTAGFIELD_SUPPORT ,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" bitfld.long 0x0 6.--8. " DEFAULT_EP_L0S_ACCPT_LATENCY ,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " DEFAULT_EP_L1_ACCPT_LATENCY ,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " UNDEFINED ,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ROLEBASED_ERRRPT ,Role Based Error Reporting (CS)" "0,1" bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 18.--25. 1. " CAPT_SLOW_PWRLIMIT_VALUE ,Captured Slow Power Limit Value (CS)" bitfld.long 0x0 26.--27. " CAPT_SLOW_PWRLIMIT_SCALE ,Captured Slow Power Scale Value (CS)" "0,1,2,3" textline " " bitfld.long 0x0 28. " FLR_EN ,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x78++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_DEV_CAS,PCIE Device Control and Status" bitfld.long 0x0 0. " COR_RE ,Correctable Error Reporting Enable" "0,1" bitfld.long 0x0 1. " NFT_RE ,Non-Fatal Error Reporting Enable" "0,1" textline " " bitfld.long 0x0 2. " FT_RE ,Fatal Error Reporting Enable" "0,1" bitfld.long 0x0 3. " UR_RE ,Unsupported Request Reporting Enable" "0,1" textline " " bitfld.long 0x0 4. " EN_RO ,Enable Relaxed Ordering" "0,1" bitfld.long 0x0 5.--7. " MPS ,Max_Payload_Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " EXTAG_EN ,Extended Tag Field Enable" "0,1" bitfld.long 0x0 9. " PHFUN_EN ,Phantom Function Enable" "0,1" textline " " bitfld.long 0x0 10. " AUXPM_EN ,AUX Power PM Enable" "0,1" bitfld.long 0x0 11. " NOSNP_EN ,Enable No Snoop" "0,1" textline " " bitfld.long 0x0 12.--14. " MRRS ,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " INIT_FLR ,Reserved" "0,1" textline " " bitfld.long 0x0 16. " COR_DET ,Correctable Error Detected" "0,1" bitfld.long 0x0 17. " NFT_DET ,Non-Fatal Error Detected" "0,1" textline " " bitfld.long 0x0 18. " FT_DET ,Fatal Error Detected" "0,1" bitfld.long 0x0 19. " UR_DET ,Unsupported Request Detected" "0,1" textline " " bitfld.long 0x0 20. " AUXP_DET ,Aux Power Detected" "0,1" bitfld.long 0x0 21. " TRANS_PEND ,Transaction Pending" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_LNK_CAP,PCIE Link Capabilities" bitfld.long 0x0 0.--3. " MAX_LINK_SPEEDS ,Supported Max Link Speed (CS) 0x1 = 2.5 GT/s (Gen1) 0x2 = 5 GT/s (Gen2) 0x4 = 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--9. " MAX_LINK_WIDTH ,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 10.--11. " AS_LINK_PM_SUPPORT ,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0 12.--14. " L0S_EXIT_LAT ,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " L1_EXIT_LAT ,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18. " CLK_PWR_MGMT ,Clock Power Management (CS)" "0,1" textline " " bitfld.long 0x0 19. " UNSUP ,Unsupported, Surprise Down Error Reporting Capable, Hardwired to 0" "0,1" bitfld.long 0x0 20. " DLL_ACTRPT_CAP ,Data Link Layer Active Reporting Capable" "0,1" textline " " bitfld.long 0x0 21. " LNK_BW_not_CAP ,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0 22. " ASPM_OPT_COMP ,ASPM Optionality Compliance (CS)" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" hexmask.long.byte 0x0 24.--31. 1. " PORT_NUM ,Port Number (CS)" group.byte 0x80++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x0 0.--1. " ASPM_CTRL ,Active State Link PM Control 0x0: DISABLED 0x1: L0S_ENABLED 0x2: L1_ENABLED 0x3: L0S_AND_L1_ENABLED" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " RCB ,Read Completion Boundary (CS) 0x0 = 64 Byte 0x1 = 128 Byte" "0,1" bitfld.long 0x0 4. " LINK_DIS ,Link Disable" "0,1" textline " " bitfld.long 0x0 5. " RETRAIN_LINK ,Retrain Link" "0,1" bitfld.long 0x0 6. " COM_CLK_CFG ,Common Clock Configuration" "0,1" textline " " bitfld.long 0x0 7. " EXT_SYN ,Extended Synch" "0,1" bitfld.long 0x0 8. " EN_CPM ,Enable Clock Power Management" "0,1" textline " " bitfld.long 0x0 9. " HAWD ,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x0 10. " LBMIE ,Link Bandwidth Management Interrupt Enable" "0,1" textline " " bitfld.long 0x0 11. " LABIE ,Link Autonomous Bandwidth Interrupt Enable." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " LINK_SPEED ,Link Speed UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " NEG_LW ,Negotiated Link Width UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 26. " UNDEF ,Undefined" "0,1" bitfld.long 0x0 27. " LINK_TRAIN ,LINK training" "0,1" textline " " bitfld.long 0x0 28. " SLOT_CLK_CONFIG ,Slot Clock Configuration (CS)" "0,1" bitfld.long 0x0 29. " DLL_ACT ,Data Link Layer Active" "0,1" textline " " bitfld.long 0x0 30. " LBW_STATUS ,Link Bandwidth Management Status" "0,1" bitfld.long 0x0 31. " LAB_STATUS ,Link Autonomous Bandwidth Status" "0,1" group.byte 0x94++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_RNG_SUPPORTED ,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS_SUPPORTED ,Completion Timeout Disable Supported" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOR_SP ,AtomicOp Routing Supported" "0,1" textline " " bitfld.long 0x0 7. " AOC32_SP ,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x0 8. " AOC64_SP ,64-bit AtomicOp Completer Supported" "0,1" textline " " bitfld.long 0x0 9. " CASC128_SP ,128-bit CAS Completer Supported" "0,1" bitfld.long 0x0 10. " NOROPR ,No RO-enabled PR-PR Passing" "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " TPHC_SP ,TPH Completer Supported" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_VALUE ,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS ,Completion Timeout Disable" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOP_REQ_EN ,AtomicOp Requester Enable" "0,1" textline " " bitfld.long 0x0 7. " AOP_EG_BLK ,AtomicOp Egress Blocking" "0,1" bitfld.long 0x0 8. " IDO_REQ_EN ,IDO Request Enable" "0,1" textline " " bitfld.long 0x0 9. " IDO_CPL_EN ,IDO Completion Enable" "0,1" bitfld.long 0x0 10. " LTR_EN ,LTR Mechanism Enable" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13.--14. " OBFF_EN ,OBFF Enable" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long.byte 0x0 1.--7. 1. " SP_LS_VEC ,Supported Link Speeds Vector" textline " " bitfld.long 0x0 8. " CROSSLINK_SP ,Crosslink Supported" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PCIECTRL_EP_PCIEWIRE_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0 0.--3. " TRGT_LINK_SPEED ,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENTR_COMPL ,Enter Compliance" "0,1" textline " " bitfld.long 0x0 5. " HW_AUTO_SP_DIS ,Hardware Autonomous Speed Disable" "0,1" bitfld.long 0x0 6. " SEL_DEEMP ,Selectable De-emphasize" "0,1" textline " " bitfld.long 0x0 7.--9. " TX_MARGIN ,Transmit Margin" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. " ENT_MOD_COMPL ,Enter Modified Compliance" "0,1" textline " " bitfld.long 0x0 11. " COMPL_SOS ,Compliance SOS" "0,1" bitfld.long 0x0 12.--15. " COMPL_PRST_DEEPH ,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DEEMPH_LEVEL ,Current De-emphasis Level" "0,1" bitfld.long 0x0 17. " EQ_COMPLETE ,Equalization Complete, Gen3 Only" "0,1" textline " " bitfld.long 0x0 18. " EQ_PH1 ,Equalization Ph1 Success, Gen3 Only" "0,1" bitfld.long 0x0 19. " EQ_PH2 ,Equalization Ph2 Success, Gen3 Only" "0,1" textline " " bitfld.long 0x0 20. " EQ_PH3 ,Equalization Ph3 Success, Gen3 Only" "0,1" bitfld.long 0x0 21. " LINK_EQ_REQ ,Link Equilization Request" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS1_EP_CFG_DBICS2" base ad:0x51001000 width 44. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x0 0.--15. 1. " VENDORID ,Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " DEVICEID ,Device ID (CS)" group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x0 0. " IO_SPACE_EN ,IO Space Enable" "0,1" bitfld.long 0x0 1. " MEM_SPACE_EN ,Memory Space Enable" "0,1" textline " " bitfld.long 0x0 2. " BUSMASTER_EN ,Bus Master Enable" "0,1" bitfld.long 0x0 3. " SPEC_CYCLE_EN ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 4. " MEMWR_INVA ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 5. " VGA_SNOOP ,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 6. " PARITYERRRESP ,Parity Error Response" "0,1" bitfld.long 0x0 7. " IDSEL_CTRL ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 8. " SERR_EN ,SERR Enable" "0,1" bitfld.long 0x0 9. " FAST_BBEN ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 10. " INTX_ASSER_DIS ,INTx Assertion Disable" "0,1" hexmask.long.byte 0x0 11.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " INTX_STATUS ,INTx Status" "0,1" bitfld.long 0x0 20. " CAP_LIST ,Capabilities List Hardwired to 1" "0,1" textline " " bitfld.long 0x0 21. " C66MHZ_CAP ,66MHz Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 23. " FAST_B2B ,Back to Back Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 24. " MASTERDATA_PARERR ,Master Data Parity Error" "0,1" textline " " bitfld.long 0x0 25.--26. " DEVSEL_TIME ,DevSel Timing, Harsdwired to 0 for PCIExpress" "0,1,2,3" bitfld.long 0x0 27. " SIGNAL_TRGTABORT ,Signaled Target Abort" "0,1" textline " " bitfld.long 0x0 28. " RCVD_TRGTABORT ,Received Target Abort" "0,1" bitfld.long 0x0 29. " RCVD_MASTERABORT ,Received Master Abort" "0,1" textline " " bitfld.long 0x0 30. " SIGNAL_SYSERR ,Signaled System Error" "0,1" bitfld.long 0x0 31. " DETECT_PARERR ,Detected Parity Error" "0,1" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x0 0.--7. 1. " REVID ,Revision ID (CS)" hexmask.long.byte 0x0 8.--15. 1. " PROG_IF_CODE ,Programming Interface Code (CS)" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBCLS_CD ,Sub Class Code (CS)" hexmask.long.byte 0x0 24.--31. 1. " BASE_CLS_CD ,Base Class Code (CS)" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BIST_HEAD_LAT_CACH,BIST, Header Type, Latency Timer, Cache Line Size" hexmask.long.byte 0x0 0.--7. 1. " CACH_LN_SZE ,Cache Line Size, No impact on write, write is allowed only for legacy purpose" hexmask.long.byte 0x0 8.--15. 1. " MSTR_LAT_TIM ,Master Latency Timer, Not Applicable for PCIe hence hardwired to 0" textline " " hexmask.long.byte 0x0 16.--22. 1. " HEAD_TYP ,Header Type 0x0 = EP header 0x1 = RC header" bitfld.long 0x0 23. " MFD ,MultiFunction Device" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " BIST ,BIST" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR1_MASK,Base Address Register 1 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode, contains the upper bits of BAR0 mask." bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR2_MASK,Base Address Register 2 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR3_MASK,Base Address Register 3 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR2 is in 64-bit mode, contains the upper bits of BAR2 mask." bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR4_MASK,Base Address Register 4 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR5_MASK,Base Address Register 5 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR4 is in 64-bit mode, contains the upper bits of BAR4 mask." bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_CARDBUS_CIS_POINTER,PCIECTRL_EP_DBICS2_CARDBUS_CIS_POINTER" hexmask.long 0x0 0.--31. 1. " CARDBUS_CIS_PTR_N ,Cardbus CIS pointer (CS)" group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_SUBID_SUBVENDORID,PCIECTRL_EP_DBICS2_SUBID_SUBVENDORID" hexmask.long.word 0x0 0.--15. 1. " SUBSYS_VENDOR_ID_N ,Subsystem Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " SUBSYS_DEV_ID_N ,Subsystem ID (CS)" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" bitfld.long 0x0 0. " EXROM_EN ,Expansion ROM Enable" "0,1" hexmask.long.word 0x0 1.--10. 1. " RESERVED ," textline " " bitfld.long 0x0 11.--15. " EXROM_ADDRESS_RO ,Expansion ROM address, masked." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--31. 1. " EXROM_ADDRESS ,Expansion ROM address, unmasked (ie programmable)" group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x0 0.--7. 1. " CAPTR ,First Capability Pointer (CS)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_INTERRUPT,Int Pin and line" hexmask.long.byte 0x0 0.--7. 1. " INT_LIN ,Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. " INT_PIN ,Interrupt Pin (CS)" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_PM_CAP,Power Management Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PM_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--18. " PMC_VER ,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " PME_CLK ,PME Clock, hardwired to 0 (CS)" "0,1" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21. " DSI ,Device Specific Initialization (CS)" "0,1" textline " " bitfld.long 0x0 22.--24. " AUX_CUR ,AUX Current (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 25. " D1_SP ,D1 Support (CS)" "0,1" textline " " bitfld.long 0x0 26. " D2_SP ,D2 Support (CS)" "0,1" bitfld.long 0x0 27.--31. " PME_SP ,PME Support (CS); Power states from which PME messages can be sent (active hi, one bit per state) Bit 0: from D0 Bit 1: from D1 Bit 2: from D2 Bit 3: from D3hot Bit 4: from D3cold (if Vaux present)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_PM_CSR,Power Management Control and Status Register" bitfld.long 0x0 0.--1. " PWR_STATE ,Device Power State" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " NSR ,No Soft Reset (CS)" "0,1" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PME_EN ,PME Enable (Sticky bit)" "0,1" bitfld.long 0x0 9.--12. " DATA_SEL ,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 13.--14. " DATA_SCALE ,Data Scale (not supported)" "0,1,2,3" bitfld.long 0x0 15. " PME_STATUS ,PME Status (Sticky bit)" "0,1" textline " " bitfld.long 0x0 16.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " B2B3_SP ,B2/B3 Support, hardwired to 0" "0,1" textline " " bitfld.long 0x0 23. " BP_CCE ,Bus Power/Clock Control Enable, hardwired to 0" "0,1" hexmask.long.byte 0x0 24.--31. 1. " DATA1 ,Data register for additional information (not supported)" group.byte 0x70++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_PCIE_CAP,PCIE cap structure" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PCIE_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--19. " PCIE_VER ,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " DEV_TYPE ,Device/Port Type Value depends on assigned type 0x0 = PCIe endpoint 0x1 = Legacy PCIe endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SLOT ,Slot Implemented Must be 0 for an endpoint" "0,1" bitfld.long 0x0 25.--29. " IM_NUM ,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x74++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x0 0.--2. " MAX_PAYLOAD_SIZE ,Maximum Payload Size (CS) Read 0x1 = 256 Byte" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " PHANTOMFUNC ,Phantom Function Support, not SUPPORTED (CS)" "0,1,2,3" textline " " bitfld.long 0x0 5. " EXTTAGFIELD_SUPPORT ,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" bitfld.long 0x0 6.--8. " DEFAULT_EP_L0S_ACCPT_LATENCY ,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " DEFAULT_EP_L1_ACCPT_LATENCY ,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " UNDEFINED ,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ROLEBASED_ERRRPT ,Role Based Error Reporting (CS)" "0,1" bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 18.--25. 1. " CAPT_SLOW_PWRLIMIT_VALUE ,Captured Slow Power Limit Value (CS)" bitfld.long 0x0 26.--27. " CAPT_SLOW_PWRLIMIT_SCALE ,Captured Slow Power Scale Value (CS)" "0,1,2,3" textline " " bitfld.long 0x0 28. " FLR_EN ,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x78++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_DEV_CAS,PCIE Device Control and Status" bitfld.long 0x0 0. " COR_RE ,Correctable Error Reporting Enable" "0,1" bitfld.long 0x0 1. " NFT_RE ,Non-Fatal Error Reporting Enable" "0,1" textline " " bitfld.long 0x0 2. " FT_RE ,Fatal Error Reporting Enable" "0,1" bitfld.long 0x0 3. " UR_RE ,Unsupported Request Reporting Enable" "0,1" textline " " bitfld.long 0x0 4. " EN_RO ,Enable Relaxed Ordering" "0,1" bitfld.long 0x0 5.--7. " MPS ,Max_Payload_Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " EXTAG_EN ,Extended Tag Field Enable" "0,1" bitfld.long 0x0 9. " PHFUN_EN ,Phantom Function Enable" "0,1" textline " " bitfld.long 0x0 10. " AUXPM_EN ,AUX Power PM Enable" "0,1" bitfld.long 0x0 11. " NOSNP_EN ,Enable No Snoop" "0,1" textline " " bitfld.long 0x0 12.--14. " MRRS ,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " INIT_FLR ,Reserved" "0,1" textline " " bitfld.long 0x0 16. " COR_DET ,Correctable Error Detected" "0,1" bitfld.long 0x0 17. " NFT_DET ,Non-Fatal Error Detected" "0,1" textline " " bitfld.long 0x0 18. " FT_DET ,Fatal Error Detected" "0,1" bitfld.long 0x0 19. " UR_DET ,Unsupported Request Detected" "0,1" textline " " bitfld.long 0x0 20. " AUXP_DET ,Aux Power Detected" "0,1" bitfld.long 0x0 21. " TRANS_PEND ,Transaction Pending" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_LNK_CAP,PCIE Link Capabilities" bitfld.long 0x0 0.--3. " MAX_LINK_SPEEDS ,Supported Max Link Speed (CS) 0x1(R) = 2.5 GT/s (Gen1) 0x2(R) = 5 GT/s (Gen2) 0x4(R) = 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--9. " MAX_LINK_WIDTH ,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 10.--11. " AS_LINK_PM_SUPPORT ,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0 12.--14. " L0S_EXIT_LAT ,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " L1_EXIT_LAT ,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18. " CLK_PWR_MGMT ,Clock Power Management (CS)" "0,1" textline " " bitfld.long 0x0 19. " UNSUP ,Unsupported, Surprise Down Error Reporting Capable, Hardwired to 0" "0,1" bitfld.long 0x0 20. " DLL_ACTRPT_CAP ,Data Link Layer Active Reporting Capable" "0,1" textline " " bitfld.long 0x0 21. " LNK_BW_not_CAP ,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0 22. " ASPM_OPT_COMP ,ASPM Optionality Compliance (CS)" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" hexmask.long.byte 0x0 24.--31. 1. " PORT_NUM ,Port Number (CS)" group.byte 0x80++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x0 0.--1. " ASPM_CTRL ,Active State Link PM Control 0x0: DISABLED 0x1: L0S_ENABLED 0x2: L1_ENABLED 0x3: L0S_AND_L1_ENABLED" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " RCB ,Read Completion Boundary (CS) Read 0x0 = 64 Byte Read 0x1 = 128 Byte" "0,1" bitfld.long 0x0 4. " LINK_DIS ,Link Disable" "0,1" textline " " bitfld.long 0x0 5. " RETRAIN_LINK ,Retrain Link" "0,1" bitfld.long 0x0 6. " COM_CLK_CFG ,Common Clock Configuration" "0,1" textline " " bitfld.long 0x0 7. " EXT_SYN ,Extended Synch" "0,1" bitfld.long 0x0 8. " EN_CPM ,Enable Clock Power Management" "0,1" textline " " bitfld.long 0x0 9. " HAWD ,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x0 10. " LBMIE ,Link Bandwidth Management Interrupt Enable" "0,1" textline " " bitfld.long 0x0 11. " LABIE ,Link Autonomous Bandwidth Interrupt Enable." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " LINK_SPEED ,Link Speed UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " NEG_LW ,Negotiated Link Width UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 26. " UNDEF ,Undefined" "0,1" bitfld.long 0x0 27. " LINK_TRAIN ,LINK training" "0,1" textline " " bitfld.long 0x0 28. " SLOT_CLK_CONFIG ,Slot Clock Configuration (CS)" "0,1" bitfld.long 0x0 29. " DLL_ACT ,Data Link Layer Active" "0,1" textline " " bitfld.long 0x0 30. " LBW_STATUS ,Link Bandwidth Management Status" "0,1" bitfld.long 0x0 31. " LAB_STATUS ,Link Autonomous Bandwidth Status" "0,1" group.byte 0x94++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_RNG_SUPPORTED ,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS_SUPPORTED ,Completion Timeout Disable Supported" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOR_SP ,AtomicOp Routing Supported" "0,1" textline " " bitfld.long 0x0 7. " AOC32_SP ,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x0 8. " AOC64_SP ,64-bit AtomicOp Completer Supported" "0,1" textline " " bitfld.long 0x0 9. " CASC128_SP ,128-bit CAS Completer Supported" "0,1" bitfld.long 0x0 10. " NOROPR ,No RO-enabled PR-PR Passing" "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " TPHC_SP ,TPH Completer Supported" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_VALUE ,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS ,Completion Timeout Disable" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOP_REQ_EN ,AtomicOp Requester Enable" "0,1" textline " " bitfld.long 0x0 7. " AOP_EG_BLK ,AtomicOp Egress Blocking" "0,1" bitfld.long 0x0 8. " IDO_REQ_EN ,IDO Request Enable" "0,1" textline " " bitfld.long 0x0 9. " IDO_CPL_EN ,IDO Completion Enable" "0,1" bitfld.long 0x0 10. " LTR_EN ,LTR Mechanism Enable" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13.--14. " OBFF_EN ,OBFF Enable" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long.byte 0x0 1.--7. 1. " SP_LS_VEC ,Supported Link Speeds Vector" textline " " bitfld.long 0x0 8. " CROSSLINK_SP ,Crosslink Supported" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0 0.--3. " TRGT_LINK_SPEED ,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENTR_COMPL ,Enter Compliance" "0,1" textline " " bitfld.long 0x0 5. " HW_AUTO_SP_DIS ,Hardware Autonomous Speed Disable" "0,1" bitfld.long 0x0 6. " SEL_DEEMP ,Selectable De-emphasize" "0,1" textline " " bitfld.long 0x0 7.--9. " TX_MARGIN ,Transmit Margin" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. " ENT_MOD_COMPL ,Enter Modified Compliance" "0,1" textline " " bitfld.long 0x0 11. " COMPL_SOS ,Compliance SOS" "0,1" bitfld.long 0x0 12.--15. " COMPL_PRST_DEEPH ,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DEEMPH_LEVEL ,Current De-emphasis Level" "0,1" bitfld.long 0x0 17. " EQ_COMPLETE ,Equalization Complete, Gen3 Only" "0,1" textline " " bitfld.long 0x0 18. " EQ_PH1 ,Equalization Ph1 Success, Gen3 Only" "0,1" bitfld.long 0x0 19. " EQ_PH2 ,Equalization Ph2 Success, Gen3 Only" "0,1" textline " " bitfld.long 0x0 20. " EQ_PH3 ,Equalization Ph3 Success, Gen3 Only" "0,1" bitfld.long 0x0 21. " LINK_EQ_REQ ,Link Equilization Request" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS2_EP_CFG_DBICS2" base ad:0x51801000 width 44. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x0 0.--15. 1. " VENDORID ,Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " DEVICEID ,Device ID (CS)" group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x0 0. " IO_SPACE_EN ,IO Space Enable" "0,1" bitfld.long 0x0 1. " MEM_SPACE_EN ,Memory Space Enable" "0,1" textline " " bitfld.long 0x0 2. " BUSMASTER_EN ,Bus Master Enable" "0,1" bitfld.long 0x0 3. " SPEC_CYCLE_EN ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 4. " MEMWR_INVA ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 5. " VGA_SNOOP ,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 6. " PARITYERRRESP ,Parity Error Response" "0,1" bitfld.long 0x0 7. " IDSEL_CTRL ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 8. " SERR_EN ,SERR Enable" "0,1" bitfld.long 0x0 9. " FAST_BBEN ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 10. " INTX_ASSER_DIS ,INTx Assertion Disable" "0,1" hexmask.long.byte 0x0 11.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " INTX_STATUS ,INTx Status" "0,1" bitfld.long 0x0 20. " CAP_LIST ,Capabilities List Hardwired to 1" "0,1" textline " " bitfld.long 0x0 21. " C66MHZ_CAP ,66MHz Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 23. " FAST_B2B ,Back to Back Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 24. " MASTERDATA_PARERR ,Master Data Parity Error" "0,1" textline " " bitfld.long 0x0 25.--26. " DEVSEL_TIME ,DevSel Timing, Harsdwired to 0 for PCIExpress" "0,1,2,3" bitfld.long 0x0 27. " SIGNAL_TRGTABORT ,Signaled Target Abort" "0,1" textline " " bitfld.long 0x0 28. " RCVD_TRGTABORT ,Received Target Abort" "0,1" bitfld.long 0x0 29. " RCVD_MASTERABORT ,Received Master Abort" "0,1" textline " " bitfld.long 0x0 30. " SIGNAL_SYSERR ,Signaled System Error" "0,1" bitfld.long 0x0 31. " DETECT_PARERR ,Detected Parity Error" "0,1" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x0 0.--7. 1. " REVID ,Revision ID (CS)" hexmask.long.byte 0x0 8.--15. 1. " PROG_IF_CODE ,Programming Interface Code (CS)" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBCLS_CD ,Sub Class Code (CS)" hexmask.long.byte 0x0 24.--31. 1. " BASE_CLS_CD ,Base Class Code (CS)" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BIST_HEAD_LAT_CACH,BIST, Header Type, Latency Timer, Cache Line Size" hexmask.long.byte 0x0 0.--7. 1. " CACH_LN_SZE ,Cache Line Size, No impact on write, write is allowed only for legacy purpose" hexmask.long.byte 0x0 8.--15. 1. " MSTR_LAT_TIM ,Master Latency Timer, Not Applicable for PCIe hence hardwired to 0" textline " " hexmask.long.byte 0x0 16.--22. 1. " HEAD_TYP ,Header Type 0x0 = EP header 0x1 = RC header" bitfld.long 0x0 23. " MFD ,MultiFunction Device" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " BIST ,BIST" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR1_MASK,Base Address Register 1 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode, contains the upper bits of BAR0 mask." bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR2_MASK,Base Address Register 2 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR3_MASK,Base Address Register 3 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR2 is in 64-bit mode, contains the upper bits of BAR2 mask." bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR4_MASK,Base Address Register 4 Mask (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR" bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_BAR5_MASK,Base Address Register 5 (CS2 mode only) Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR4 is in 64-bit mode, contains the upper bits of BAR4 mask." bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_CARDBUS_CIS_POINTER,PCIECTRL_EP_DBICS2_CARDBUS_CIS_POINTER" hexmask.long 0x0 0.--31. 1. " CARDBUS_CIS_PTR_N ,Cardbus CIS pointer (CS)" group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_SUBID_SUBVENDORID,PCIECTRL_EP_DBICS2_SUBID_SUBVENDORID" hexmask.long.word 0x0 0.--15. 1. " SUBSYS_VENDOR_ID_N ,Subsystem Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " SUBSYS_DEV_ID_N ,Subsystem ID (CS)" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" bitfld.long 0x0 0. " EXROM_EN ,Expansion ROM Enable" "0,1" hexmask.long.word 0x0 1.--10. 1. " RESERVED ," textline " " bitfld.long 0x0 11.--15. " EXROM_ADDRESS_RO ,Expansion ROM address, masked." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--31. 1. " EXROM_ADDRESS ,Expansion ROM address, unmasked (ie programmable)" group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x0 0.--7. 1. " CAPTR ,First Capability Pointer (CS)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_INTERRUPT,Int Pin and line" hexmask.long.byte 0x0 0.--7. 1. " INT_LIN ,Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. " INT_PIN ,Interrupt Pin (CS)" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_PM_CAP,Power Management Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PM_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--18. " PMC_VER ,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " PME_CLK ,PME Clock, hardwired to 0 (CS)" "0,1" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21. " DSI ,Device Specific Initialization (CS)" "0,1" textline " " bitfld.long 0x0 22.--24. " AUX_CUR ,AUX Current (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 25. " D1_SP ,D1 Support (CS)" "0,1" textline " " bitfld.long 0x0 26. " D2_SP ,D2 Support (CS)" "0,1" bitfld.long 0x0 27.--31. " PME_SP ,PME Support (CS); Power states from which PME messages can be sent (active hi, one bit per state) Bit 0: from D0 Bit 1: from D1 Bit 2: from D2 Bit 3: from D3hot Bit 4: from D3cold (if Vaux present)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_PM_CSR,Power Management Control and Status Register" bitfld.long 0x0 0.--1. " PWR_STATE ,Device Power State" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " NSR ,No Soft Reset (CS)" "0,1" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PME_EN ,PME Enable (Sticky bit)" "0,1" bitfld.long 0x0 9.--12. " DATA_SEL ,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 13.--14. " DATA_SCALE ,Data Scale (not supported)" "0,1,2,3" bitfld.long 0x0 15. " PME_STATUS ,PME Status (Sticky bit)" "0,1" textline " " bitfld.long 0x0 16.--21. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " B2B3_SP ,B2/B3 Support, hardwired to 0" "0,1" textline " " bitfld.long 0x0 23. " BP_CCE ,Bus Power/Clock Control Enable, hardwired to 0" "0,1" hexmask.long.byte 0x0 24.--31. 1. " DATA1 ,Data register for additional information (not supported)" group.byte 0x70++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_PCIE_CAP,PCIE cap structure" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PCIE_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--19. " PCIE_VER ,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " DEV_TYPE ,Device/Port Type Value depends on assigned type 0x0 = PCIe endpoint 0x1 = Legacy PCIe endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SLOT ,Slot Implemented Must be 0 for an endpoint" "0,1" bitfld.long 0x0 25.--29. " IM_NUM ,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x74++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x0 0.--2. " MAX_PAYLOAD_SIZE ,Maximum Payload Size (CS) Read 0x1 = 256 Byte" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " PHANTOMFUNC ,Phantom Function Support, not SUPPORTED (CS)" "0,1,2,3" textline " " bitfld.long 0x0 5. " EXTTAGFIELD_SUPPORT ,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" bitfld.long 0x0 6.--8. " DEFAULT_EP_L0S_ACCPT_LATENCY ,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " DEFAULT_EP_L1_ACCPT_LATENCY ,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " UNDEFINED ,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ROLEBASED_ERRRPT ,Role Based Error Reporting (CS)" "0,1" bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 18.--25. 1. " CAPT_SLOW_PWRLIMIT_VALUE ,Captured Slow Power Limit Value (CS)" bitfld.long 0x0 26.--27. " CAPT_SLOW_PWRLIMIT_SCALE ,Captured Slow Power Scale Value (CS)" "0,1,2,3" textline " " bitfld.long 0x0 28. " FLR_EN ,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x78++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_DEV_CAS,PCIE Device Control and Status" bitfld.long 0x0 0. " COR_RE ,Correctable Error Reporting Enable" "0,1" bitfld.long 0x0 1. " NFT_RE ,Non-Fatal Error Reporting Enable" "0,1" textline " " bitfld.long 0x0 2. " FT_RE ,Fatal Error Reporting Enable" "0,1" bitfld.long 0x0 3. " UR_RE ,Unsupported Request Reporting Enable" "0,1" textline " " bitfld.long 0x0 4. " EN_RO ,Enable Relaxed Ordering" "0,1" bitfld.long 0x0 5.--7. " MPS ,Max_Payload_Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " EXTAG_EN ,Extended Tag Field Enable" "0,1" bitfld.long 0x0 9. " PHFUN_EN ,Phantom Function Enable" "0,1" textline " " bitfld.long 0x0 10. " AUXPM_EN ,AUX Power PM Enable" "0,1" bitfld.long 0x0 11. " NOSNP_EN ,Enable No Snoop" "0,1" textline " " bitfld.long 0x0 12.--14. " MRRS ,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " INIT_FLR ,Reserved" "0,1" textline " " bitfld.long 0x0 16. " COR_DET ,Correctable Error Detected" "0,1" bitfld.long 0x0 17. " NFT_DET ,Non-Fatal Error Detected" "0,1" textline " " bitfld.long 0x0 18. " FT_DET ,Fatal Error Detected" "0,1" bitfld.long 0x0 19. " UR_DET ,Unsupported Request Detected" "0,1" textline " " bitfld.long 0x0 20. " AUXP_DET ,Aux Power Detected" "0,1" bitfld.long 0x0 21. " TRANS_PEND ,Transaction Pending" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_LNK_CAP,PCIE Link Capabilities" bitfld.long 0x0 0.--3. " MAX_LINK_SPEEDS ,Supported Max Link Speed (CS) 0x1(R) = 2.5 GT/s (Gen1) 0x2(R) = 5 GT/s (Gen2) 0x4(R) = 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--9. " MAX_LINK_WIDTH ,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 10.--11. " AS_LINK_PM_SUPPORT ,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0 12.--14. " L0S_EXIT_LAT ,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " L1_EXIT_LAT ,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18. " CLK_PWR_MGMT ,Clock Power Management (CS)" "0,1" textline " " bitfld.long 0x0 19. " UNSUP ,Unsupported, Surprise Down Error Reporting Capable, Hardwired to 0" "0,1" bitfld.long 0x0 20. " DLL_ACTRPT_CAP ,Data Link Layer Active Reporting Capable" "0,1" textline " " bitfld.long 0x0 21. " LNK_BW_not_CAP ,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0 22. " ASPM_OPT_COMP ,ASPM Optionality Compliance (CS)" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" hexmask.long.byte 0x0 24.--31. 1. " PORT_NUM ,Port Number (CS)" group.byte 0x80++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x0 0.--1. " ASPM_CTRL ,Active State Link PM Control 0x0: DISABLED 0x1: L0S_ENABLED 0x2: L1_ENABLED 0x3: L0S_AND_L1_ENABLED" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " RCB ,Read Completion Boundary (CS) Read 0x0 = 64 Byte Read 0x1 = 128 Byte" "0,1" bitfld.long 0x0 4. " LINK_DIS ,Link Disable" "0,1" textline " " bitfld.long 0x0 5. " RETRAIN_LINK ,Retrain Link" "0,1" bitfld.long 0x0 6. " COM_CLK_CFG ,Common Clock Configuration" "0,1" textline " " bitfld.long 0x0 7. " EXT_SYN ,Extended Synch" "0,1" bitfld.long 0x0 8. " EN_CPM ,Enable Clock Power Management" "0,1" textline " " bitfld.long 0x0 9. " HAWD ,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x0 10. " LBMIE ,Link Bandwidth Management Interrupt Enable" "0,1" textline " " bitfld.long 0x0 11. " LABIE ,Link Autonomous Bandwidth Interrupt Enable." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " LINK_SPEED ,Link Speed UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " NEG_LW ,Negotiated Link Width UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 26. " UNDEF ,Undefined" "0,1" bitfld.long 0x0 27. " LINK_TRAIN ,LINK training" "0,1" textline " " bitfld.long 0x0 28. " SLOT_CLK_CONFIG ,Slot Clock Configuration (CS)" "0,1" bitfld.long 0x0 29. " DLL_ACT ,Data Link Layer Active" "0,1" textline " " bitfld.long 0x0 30. " LBW_STATUS ,Link Bandwidth Management Status" "0,1" bitfld.long 0x0 31. " LAB_STATUS ,Link Autonomous Bandwidth Status" "0,1" group.byte 0x94++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_RNG_SUPPORTED ,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS_SUPPORTED ,Completion Timeout Disable Supported" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOR_SP ,AtomicOp Routing Supported" "0,1" textline " " bitfld.long 0x0 7. " AOC32_SP ,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x0 8. " AOC64_SP ,64-bit AtomicOp Completer Supported" "0,1" textline " " bitfld.long 0x0 9. " CASC128_SP ,128-bit CAS Completer Supported" "0,1" bitfld.long 0x0 10. " NOROPR ,No RO-enabled PR-PR Passing" "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " TPHC_SP ,TPH Completer Supported" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_VALUE ,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS ,Completion Timeout Disable" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOP_REQ_EN ,AtomicOp Requester Enable" "0,1" textline " " bitfld.long 0x0 7. " AOP_EG_BLK ,AtomicOp Egress Blocking" "0,1" bitfld.long 0x0 8. " IDO_REQ_EN ,IDO Request Enable" "0,1" textline " " bitfld.long 0x0 9. " IDO_CPL_EN ,IDO Completion Enable" "0,1" bitfld.long 0x0 10. " LTR_EN ,LTR Mechanism Enable" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13.--14. " OBFF_EN ,OBFF Enable" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long.byte 0x0 1.--7. 1. " SP_LS_VEC ,Supported Link Speeds Vector" textline " " bitfld.long 0x0 8. " CROSSLINK_SP ,Crosslink Supported" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PCIECTRL_EP_DBICS2_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0 0.--3. " TRGT_LINK_SPEED ,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENTR_COMPL ,Enter Compliance" "0,1" textline " " bitfld.long 0x0 5. " HW_AUTO_SP_DIS ,Hardware Autonomous Speed Disable" "0,1" bitfld.long 0x0 6. " SEL_DEEMP ,Selectable De-emphasize" "0,1" textline " " bitfld.long 0x0 7.--9. " TX_MARGIN ,Transmit Margin" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. " ENT_MOD_COMPL ,Enter Modified Compliance" "0,1" textline " " bitfld.long 0x0 11. " COMPL_SOS ,Compliance SOS" "0,1" bitfld.long 0x0 12.--15. " COMPL_PRST_DEEPH ,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DEEMPH_LEVEL ,Current De-emphasis Level" "0,1" bitfld.long 0x0 17. " EQ_COMPLETE ,Equalization Complete, Gen3 Only" "0,1" textline " " bitfld.long 0x0 18. " EQ_PH1 ,Equalization Ph1 Success, Gen3 Only" "0,1" bitfld.long 0x0 19. " EQ_PH2 ,Equalization Ph2 Success, Gen3 Only" "0,1" textline " " bitfld.long 0x0 20. " EQ_PH3 ,Equalization Ph3 Success, Gen3 Only" "0,1" bitfld.long 0x0 21. " LINK_EQ_REQ ,Link Equilization Request" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS1_TI_CONF" base ad:0x51002000 width 37. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_TI_CONF_REVISION,IP Revision Identifier" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_TI_CONF_SYSCONFIG,Controls various parameters of the master and slave interfaces." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,PM mode of local target (slave); Target shall be capable of handling read/write transaction as long as it is out of IDLE state. 0x0: Force-idle mode = local target's idle state follows (acknowledges) the system's idle requests unconditionally, regardless of the IP module's internal requirements. 0x1: No-idle mode = local target never enters idle state. 0x2: Smart-idle mode = local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. Module shall not generate (IRQ- or DMA-request-related) wakeup events. 0x3: Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,PM mode of local initiator (master); Initiator may generate read/write transaction as long as it is out of STANDBY state. 0x0: Force-standby mode = Initiator is unconditionally placed in standby state. 0x1: No-standby mode = initiator is unconditionally placed out of standby state. 0x2: Smart-standby mode = initiator's standby state depends on internal conditions, that is, the module's functional requirements. Asynchronous wakeup events cannot be generated. 0x3: Smart-Standby, wakeup-capable mode = initiator's standby state depends on internal conditions, ie the module's functional requirements. Asynchronous wakeup events can be generated." "0,1,2,3" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCOHERENT_EN ,Allows the no-snoop (NS) attribute of inbound PCIe TLPs to be passed to SoC system bus (AXI) master as a 'coherent' inband flag." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if an new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0.--3. " LINE_NUMBER ,Write the IRQ line number to apply software EOI to it. Write 0x0: software EOI on main interrupt line Read 0x0: Read always returns zeros Write 0x1: software EOI on message-signalled (MSI) interrupt line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MAIN,Raw status of 'main' interrupt requests; Set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug (regular status also gets set)." bitfld.long 0x0 0. " ERR_SYS ,System Error IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 1. " ERR_FATAL ,Fatal Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 2. " ERR_NONFATAL ,Non-Fatal Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 3. " ERR_COR ,Correctable Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 4. " ERR_AXI ,AXI tag lookup fatal Error IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 5. " ERR_ECRC ,ECRC Error IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8. " PME_TURN_OFF ,Power Management Event Turn-Off message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 9. " PME_TO_ACK ,Power Management Event Turn-Off Ack message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 10. " PM_PME ,PM Power Management Event message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 11. " LINK_REQ_RST ,Link Request Reset IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 12. " LINK_UP_EVT ,Link-up state change IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 13. " CFG_BME_EVT ,CFG 'Bus Master Enable' change IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 14. " CFG_MSE_EVT ,CFG 'Memory Space Enable' change IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQSTATUS_MAIN,Regular status of 'main' interrupt requests; Set only when enabled. Write 1 to clear after interrupt has been serviced (raw status also gets cleared)." bitfld.long 0x0 0. " ERR_SYS ,System Error IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 1. " ERR_FATAL ,Fatal Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 2. " ERR_NONFATAL ,Non-Fatal Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 3. " ERR_COR ,Correctable Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 4. " ERR_AXI ,AXI tag lookup fatal Error IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 5. " ERR_ECRC ,ECRC Error IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8. " PME_TURN_OFF ,Power Management Event Turn-Off message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 9. " PME_TO_ACK ,Power Management Event Turn-Off Ack message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 10. " PM_PME ,PM Power Management Event message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 11. " LINK_REQ_RST ,Link Request Reset IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 12. " LINK_UP_EVT ,Link-up state change IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 13. " CFG_BME_EVT ,CFG 'Bus Master Enable' change IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 14. " CFG_MSE_EVT ,CFG 'Memory Space Enable' change IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQENABLE_SET_MAIN,Enable of 'main' interrupt requests; Write 1 to set (ie to enable interrupt). Readout is the same as corresponding _CLR register." bitfld.long 0x0 0. " ERR_SYS_EN ,System Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 1. " ERR_FATAL_EN ,Fatal Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 2. " ERR_NONFATAL_EN ,Non-Fatal Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 3. " ERR_COR_EN ,Correctable Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 4. " ERR_AXI_EN ,AXI tag lookup fatal Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 5. " ERR_ECRC_EN ,ECRC Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8. " PME_TURN_OFF_EN ,Power Management Event Turn-Off message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 9. " PME_TO_ACK_EN ,Power Management Event Turn-Off Ack message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 10. " PM_PME_EN ,PM Power Management Event message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 11. " LINK_REQ_RST_EN ,Link Request Reset IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 12. " LINK_UP_EVT_EN ,Link-up state change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 13. " CFG_BME_EVT_EN ,CFG 'Bus Master Enable' change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 14. " CFG_MSE_EVT_EN ,CFG 'Memory Space Enable' change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQENABLE_CLR_MAIN,Enable of 'main' interrupt requests; Write 1 to clear (ie to disable interrupt). Readout is the same as corresponding _SET register." bitfld.long 0x0 0. " ERR_SYS_EN ,System Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 1. " ERR_FATAL_EN ,Fatal Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 2. " ERR_NONFATAL_EN ,Non-Fatal Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 3. " ERR_COR_EN ,Correctable Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 4. " ERR_AXI_EN ,AXI tag lookup fatal Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 5. " ERR_ECRC_EN ,ECRC Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8. " PME_TURN_OFF_EN ,Power Management Event Turn-Off message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 9. " PME_TO_ACK_EN ,Power Management Event Turn-Off Ack message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 10. " PM_PME_EN ,PM Power Management Event message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 11. " LINK_REQ_RST_EN ,Link Request Reset IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 12. " LINK_UP_EVT_EN ,Link-up state change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 13. " CFG_BME_EVT_EN ,CFG 'Bus Master Enable' change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 14. " CFG_MSE_EVT_EN ,CFG 'Memory Space Enable' change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MSI,Raw status of legacy and MSI interrupt requests; Set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug (regular status also gets set)." bitfld.long 0x0 0. " INTA ,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only. Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 1. " INTB ,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only. Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 2. " INTC ,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only. Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 3. " INTD ,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only. Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 4. " MSI ,Message Signaled Interrupt IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQSTATUS_MSI,Regular status of legacy and MSI interrupt requests; Set only when enabled. Write 1 to clear after interrupt has been serviced (raw status also gets cleared). HW-generated events are self-clearing." bitfld.long 0x0 0. " INTA ,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only. Typically set AND cleared by the remote EP, without local software intervention. Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any. Read 1: IRQ event pending" "0,1" bitfld.long 0x0 1. " INTB ,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only. Typically set AND cleared by the remote EP, without local software intervention. Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any. Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 2. " INTC ,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only. Typically set AND cleared by the remote EP, without local software intervention. Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any. Read 1: IRQ event pending" "0,1" bitfld.long 0x0 3. " INTD ,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only. Typically set AND cleared by the remote EP, without local software intervention. Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any. Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 4. " MSI ,Message Signaled Interrupt IRQ status. Cleared by clearing all vectors in the MSI controller (PL) registers Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any. Read 1: IRQ event pending" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQENABLE_SET_MSI,Enable of legacy and MSI interrupt requests; Write 1 to set (ie to enable interrupt). Readout is the same as corresponding _CLR register." bitfld.long 0x0 0. " INTA_EN ,INTA IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 1. " INTB_EN ,INTB IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 2. " INTC_EN ,INTC IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 3. " INTD_EN ,INTD IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 4. " MSI_EN ,Message Signaled Interrupt IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQENABLE_CLR_MSI,Enable of legacy and MSI interrupt requests; Write 1 to clear (ie to disable interrupt). Readout is the same as corresponding _SET register." bitfld.long 0x0 0. " INTA_EN ,INTA IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 1. " INTB_EN ,INTB IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 2. " INTC_EN ,INTC IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 3. " INTD_EN ,INTD IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 4. " MSI_EN ,Message Signaled Interrupt IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "PCIECTRL_TI_CONF_DEVICE_TYPE,Sets the Dual-Mode device's type" bitfld.long 0x0 0.--3. " TYPE ,PCIe device type including the contents of the PCI config space (Type-0 for EP, Type-1 for RC); Apply fundamental reset after change; Do not change during core operation; 0x0: PCIe endpoint (EP) 0x1: Legacy PCIe endpoint (LEG_EP) 0x4: Root Complex (RC) Other values: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "PCIECTRL_TI_CONF_DEVICE_CMD,Device command (startup control and status); WARNING: cleared by all reset conditions, including fundamental reset" bitfld.long 0x0 0. " LTSSM_EN ,LTSSM enable: start the PCI link (This bit is CLEARED BY FUNDAMENTAL RESET)" "0,1" bitfld.long 0x0 1. " APP_REQ_RETRY_EN ,Application Request Retry Enable (This bit is CLEARED BY FUNDAMENTAL RESET)" "0,1" textline " " bitfld.long 0x0 2.--7. " LTSSM_STATE ,LTSSM state /substate, implementation-specific, for debug Read 0x00: DETECT_QUIET Read 0x01: DETECT_ACT Read 0x02: POLL_ACTIVE Read 0x03: POLL_COMPLIANCE Read 0x04: POLL_CONFIG Read 0x05: PRE_DETECT_QUIET Read 0x06: DETECT_WAIT Read 0x07: CFG_LINKWD_START Read 0x08: CFG_LINKWD_ACEPT Read 0x09: CFG_LANENUM_WAIT Read 0x0A: CFG_LANENUM_ACEPT Read 0x0B: CFG_COMPLETE Read 0x0C: CFG_IDLE Read 0x0D: RCVRY_LOCK Read 0x0E: RCVRY_SPEED Read 0x0F: RCVRY_RCVRCFG Read 0x10: RCVRY_IDLE Read 0x11: L0 Read 0x12: L0S Read 0x13: L123_SEND_EIDLE Read 0x14: L1_IDLE Read 0x15: L2_IDLE Read 0x16: L2_WAKE Read 0x17: DISABLED_ENTRY Read 0x18: DISABLED_IDLE Read 0x19: DISABLED Read 0x1A: LPBK_ENTRY Read 0x1B: LPBK_ACTIVE Read 0x1C: LPBK_EXIT Read 0x1D: LPBK_EXIT_TIMEOUT Read 0x1E: HOT_RESET_ENTRY Read 0x1F: HOT_RESET Read 0x20: RCVRY_EQ0 Read 0x21: RCVRY_EQ1 Read 0x22: RCVRY_EQ2 Read 0x23: RCVRY_EQ3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--20. " DEV_NUM ,PCIe device number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 21.--28. 1. " BUS_NUM ,PCIe bus number" textline " " bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x108++0x3 line.long 0x0 "PCIECTRL_TI_CONF_PM_CTRL,Power Management Control" bitfld.long 0x0 0. " PME_TURN_OFF ,Transmits PME_Turn_Off message downstream (RC mode only); Eventually sends all links of hierarchy domain to L2L/3_ready" "0,1" bitfld.long 0x0 1. " PM_PME ,Transmits PM_PME wakeup message (EP mode only)" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " L23_READY ,Indicates system readiness for the link to enter L2/L3 ready state (EP mode only); Allows the transmission of PM_Enter_L23 following PM_Turn_OFF/PME_TO_Ack handshake. Self-cleared upon transition to L2/L3." "0,1" textline " " bitfld.long 0x0 9. " REQ_ENTR_L1 ,Request to transition to L1 state" "0,1" bitfld.long 0x0 10. " REQ_EXIT_L1 ,Request to exit L1 state (to L0)" "0,1" textline " " bitfld.long 0x0 11. " AUX_PWR_DET ,Auxilliary Power Detection; Status of Vaux detection for the PCIe controller; Determines transition to L2 vs L3 upon Vmain turn-off." "0,1" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "PCIECTRL_TI_CONF_PHY_CS,Physical Layer Control and Status" bitfld.long 0x0 0. " REVERSE_LANES ,Manual lane reversal control, allowing lane 0 and lane 1 to be swapped by default; Both Tx and Rx are reversed; Polarity of the individual lane is unchanged" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " LINK_UP ,Link status, from LTSSM" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "PCIECTRL_TI_CONF_INTX_ASSERT,Legacy INTx ASSERT message control, with 'x' in (A,B,C,D) set by the 'Interrupt Pin' field. Write 1 to send message, read to get the status; EP mode only" bitfld.long 0x0 0. " ASSERT_F0 ,INTx ASSERT for function 0 Write 0: No action Read 0: INTx is inactive (has been deasserted) Write 1: Transmit INTx ASSERT to RC Read 1: INTx is active (has been asserted)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x128++0x3 line.long 0x0 "PCIECTRL_TI_CONF_INTX_DEASSERT,Legacy INTx DEASSERT message control, with 'x' in (A,B,C,D) set by the 'Interrupt Pin' field. Write 1 to send message, read to get the status; EP mode only" bitfld.long 0x0 0. " DEASSERT_F0 ,INTx DEASSERT for function 0 Write 0: No action Read 0: INTx is inactive (has been deasserted) Write 1: Transmit INTx DEASSERT to RC Read 1: INTx is active (has been asserted)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x12C++0x3 line.long 0x0 "PCIECTRL_TI_CONF_MSI_XMT,MSI transmitter (EP mode); Specifies parameters of MSI, together with MSI capability descriptor already configured by remote RC." bitfld.long 0x0 0. " MSI_REQ_GRANT ,MSI transmit request (and grant status) Write 0: No Action Read 0: MSI transmission request pending Read 1: No MSI request pending (last request granted) Write 1: Request MSI transmission" "0,1" bitfld.long 0x0 1.--3. " MSI_FUNC_NUM ,Function number for transmitted MSI; Always 0 for single-function EP" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " MSI_TC ,Traffic class (TC) for transmitted MSI" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7.--11. " MSI_VECTOR ,Vector number for transmitted MSI (as allowed by RC at enumeration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x140++0x3 line.long 0x0 "PCIECTRL_TI_CONF_DEBUG_CFG,Configuration of debug_data output and register (observability)" bitfld.long 0x0 0.--5. " SEL ,Debug_data mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x144++0x3 line.long 0x0 "PCIECTRL_TI_CONF_DEBUG_DATA,Debug data vector, depending on DEBUG_CFG.sel value" hexmask.long 0x0 0.--31. 1. " DEBUG ," group.byte 0x148++0x3 line.long 0x0 "PCIECTRL_TI_CONF_DIAG_CTRL,Diagnostic control" bitfld.long 0x0 0. " INV_LCRC ,Corrupts LSB of LCRC in the next packet, then self-clears. Read 0: No CRC corruption pending Read 1: CRC corruption pending Write 1: Request CRC corruption" "0,1" bitfld.long 0x0 1. " INV_ECRC ,Corrupt LSB of ECRC in the next packet, then self-clears. Read 0: No CRC corruption pending Read 1: CRC corruption pending Write 1: Request CRC corruption" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,software must always keep this bit at its default value - 0." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS2_TI_CONF" base ad:0x51802000 width 37. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_TI_CONF_REVISION,IP Revision Identifier" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_TI_CONF_SYSCONFIG,Controls various parameters of the master and slave interfaces." bitfld.long 0x0 0.--1. " RESERVED ," "0,1,2,3" bitfld.long 0x0 2.--3. " IDLEMODE ,PM mode of local target (slave); Target shall be capable of handling read/write transaction as long as it is out of IDLE state. 0x0: Force-idle mode = local target's idle state follows (acknowledges) the system's idle requests unconditionally, regardless of the IP module's internal requirements. 0x1: No-idle mode = local target never enters idle state. 0x2: Smart-idle mode = local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. Module shall not generate (IRQ- or DMA-request-related) wakeup events. 0x3: Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " STANDBYMODE ,PM mode of local initiator (master); Initiator may generate read/write transaction as long as it is out of STANDBY state. 0x0: Force-standby mode = Initiator is unconditionally placed in standby state. 0x1: No-standby mode = initiator is unconditionally placed out of standby state. 0x2: Smart-standby mode = initiator's standby state depends on internal conditions, that is, the module's functional requirements. Asynchronous wakeup events cannot be generated. 0x3: Smart-Standby, wakeup-capable mode = initiator's standby state depends on internal conditions, ie the module's functional requirements. Asynchronous wakeup events can be generated." "0,1,2,3" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " MCOHERENT_EN ,Allows the no-snoop (NS) attribute of inbound PCIe TLPs to be passed to SoC system bus (AXI) master as a 'coherent' inband flag." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQ_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if an new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0.--3. " LINE_NUMBER ,Write the IRQ line number to apply software EOI to it. Write 0x0: software EOI on main interrupt line Read 0x0: Read always returns zeros Write 0x1: software EOI on message-signalled (MSI) interrupt line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MAIN,Raw status of 'main' interrupt requests; Set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug (regular status also gets set)." bitfld.long 0x0 0. " ERR_SYS ,System Error IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 1. " ERR_FATAL ,Fatal Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 2. " ERR_NONFATAL ,Non-Fatal Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 3. " ERR_COR ,Correctable Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 4. " ERR_AXI ,AXI tag lookup fatal Error IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 5. " ERR_ECRC ,ECRC Error IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8. " PME_TURN_OFF ,Power Management Event Turn-Off message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 9. " PME_TO_ACK ,Power Management Event Turn-Off Ack message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 10. " PM_PME ,PM Power Management Event message received IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 11. " LINK_REQ_RST ,Link Request Reset IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 12. " LINK_UP_EVT ,Link-up state change IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 13. " CFG_BME_EVT ,CFG 'Bus Master Enable' change IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 14. " CFG_MSE_EVT ,CFG 'Memory Space Enable' change IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQSTATUS_MAIN,Regular status of 'main' interrupt requests; Set only when enabled. Write 1 to clear after interrupt has been serviced (raw status also gets cleared)." bitfld.long 0x0 0. " ERR_SYS ,System Error IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 1. " ERR_FATAL ,Fatal Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 2. " ERR_NONFATAL ,Non-Fatal Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 3. " ERR_COR ,Correctable Error message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 4. " ERR_AXI ,AXI tag lookup fatal Error IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 5. " ERR_ECRC ,ECRC Error IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8. " PME_TURN_OFF ,Power Management Event Turn-Off message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 9. " PME_TO_ACK ,Power Management Event Turn-Off Ack message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 10. " PM_PME ,PM Power Management Event message received IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 11. " LINK_REQ_RST ,Link Request Reset IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 12. " LINK_UP_EVT ,Link-up state change IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 13. " CFG_BME_EVT ,CFG 'Bus Master Enable' change IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" bitfld.long 0x0 14. " CFG_MSE_EVT ,CFG 'Memory Space Enable' change IRQ status Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any Read 1: IRQ event pending" "0,1" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQENABLE_SET_MAIN,Enable of 'main' interrupt requests; Write 1 to set (ie to enable interrupt). Readout is the same as corresponding _CLR register." bitfld.long 0x0 0. " ERR_SYS_EN ,System Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 1. " ERR_FATAL_EN ,Fatal Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 2. " ERR_NONFATAL_EN ,Non-Fatal Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 3. " ERR_COR_EN ,Correctable Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 4. " ERR_AXI_EN ,AXI tag lookup fatal Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 5. " ERR_ECRC_EN ,ECRC Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8. " PME_TURN_OFF_EN ,Power Management Event Turn-Off message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 9. " PME_TO_ACK_EN ,Power Management Event Turn-Off Ack message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 10. " PM_PME_EN ,PM Power Management Event message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 11. " LINK_REQ_RST_EN ,Link Request Reset IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 12. " LINK_UP_EVT_EN ,Link-up state change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 13. " CFG_BME_EVT_EN ,CFG 'Bus Master Enable' change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 14. " CFG_MSE_EVT_EN ,CFG 'Memory Space Enable' change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQENABLE_CLR_MAIN,Enable of 'main' interrupt requests; Write 1 to clear (ie to disable interrupt). Readout is the same as corresponding _SET register." bitfld.long 0x0 0. " ERR_SYS_EN ,System Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 1. " ERR_FATAL_EN ,Fatal Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 2. " ERR_NONFATAL_EN ,Non-Fatal Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 3. " ERR_COR_EN ,Correctable Error message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 4. " ERR_AXI_EN ,AXI tag lookup fatal Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 5. " ERR_ECRC_EN ,ECRC Error IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" bitfld.long 0x0 8. " PME_TURN_OFF_EN ,Power Management Event Turn-Off message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 9. " PME_TO_ACK_EN ,Power Management Event Turn-Off Ack message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 10. " PM_PME_EN ,PM Power Management Event message received IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 11. " LINK_REQ_RST_EN ,Link Request Reset IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 12. " LINK_UP_EVT_EN ,Link-up state change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 13. " CFG_BME_EVT_EN ,CFG 'Bus Master Enable' change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 14. " CFG_MSE_EVT_EN ,CFG 'Memory Space Enable' change IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQSTATUS_RAW_MSI,Raw status of legacy and MSI interrupt requests; Set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug (regular status also gets set)." bitfld.long 0x0 0. " INTA ,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only. Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 1. " INTB ,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only. Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 2. " INTC ,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only. Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" bitfld.long 0x0 3. " INTD ,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only. Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 4. " MSI ,Message Signaled Interrupt IRQ status Write 0: No action Read 0: No event pending Write 1: Trigger IRQ event by software Read 1: IRQ event pending" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQSTATUS_MSI,Regular status of legacy and MSI interrupt requests; Set only when enabled. Write 1 to clear after interrupt has been serviced (raw status also gets cleared). HW-generated events are self-clearing." bitfld.long 0x0 0. " INTA ,INTA IRQ status (Legacy PCIe message interrupt A); RC mode only. Typically set AND cleared by the remote EP, without local software intervention. Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any. Read 1: IRQ event pending" "0,1" bitfld.long 0x0 1. " INTB ,INTB IRQ status (Legacy PCIe message interrupt B); RC mode only. Typically set AND cleared by the remote EP, without local software intervention. Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any. Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 2. " INTC ,INTC IRQ status (Legacy PCIe message interrupt C); RC mode only. Typically set AND cleared by the remote EP, without local software intervention. Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any. Read 1: IRQ event pending" "0,1" bitfld.long 0x0 3. " INTD ,INTD IRQ status (Legacy PCIe message interrupt D); RC mode only. Typically set AND cleared by the remote EP, without local software intervention. Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any. Read 1: IRQ event pending" "0,1" textline " " bitfld.long 0x0 4. " MSI ,Message Signaled Interrupt IRQ status. Cleared by clearing all vectors in the MSI controller (PL) registers Write 0: No action Read 0: No event pending Write 1: Clear pending event, if any. Read 1: IRQ event pending" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQENABLE_SET_MSI,Enable of legacy and MSI interrupt requests; Write 1 to set (ie to enable interrupt). Readout is the same as corresponding _CLR register." bitfld.long 0x0 0. " INTA_EN ,INTA IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 1. " INTB_EN ,INTB IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 2. " INTC_EN ,INTC IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 3. " INTD_EN ,INTD IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 4. " MSI_EN ,Message Signaled Interrupt IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Set IRQ enable (that is, enable event) Read 1: IRQ event is enabled" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_TI_CONF_IRQENABLE_CLR_MSI,Enable of legacy and MSI interrupt requests; Write 1 to clear (ie to disable interrupt). Readout is the same as corresponding _SET register." bitfld.long 0x0 0. " INTA_EN ,INTA IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 1. " INTB_EN ,INTB IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 2. " INTC_EN ,INTC IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" bitfld.long 0x0 3. " INTD_EN ,INTD IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" textline " " bitfld.long 0x0 4. " MSI_EN ,Message Signaled Interrupt IRQ enable Write 0: No action Read 0: IRQ event is disabled Write 1: Clear IRQ enable (that is, disable event) Read 1: IRQ event is enabled" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "PCIECTRL_TI_CONF_DEVICE_TYPE,Sets the Dual-Mode device's type" bitfld.long 0x0 0.--3. " TYPE ,PCIe device type including the contents of the PCI config space (Type-0 for EP, Type-1 for RC); Apply fundamental reset after change; Do not change during core operation; 0x0: PCIe endpoint (EP) 0x1: Legacy PCIe endpoint (LEG_EP) 0x4: Root Complex (RC) Other values: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "PCIECTRL_TI_CONF_DEVICE_CMD,Device command (startup control and status); WARNING: cleared by all reset conditions, including fundamental reset" bitfld.long 0x0 0. " LTSSM_EN ,LTSSM enable: start the PCI link (This bit is CLEARED BY FUNDAMENTAL RESET)" "0,1" bitfld.long 0x0 1. " APP_REQ_RETRY_EN ,Application Request Retry Enable (This bit is CLEARED BY FUNDAMENTAL RESET)" "0,1" textline " " bitfld.long 0x0 2.--7. " LTSSM_STATE ,LTSSM state /substate, implementation-specific, for debug Read 0x00: DETECT_QUIET Read 0x01: DETECT_ACT Read 0x02: POLL_ACTIVE Read 0x03: POLL_COMPLIANCE Read 0x04: POLL_CONFIG Read 0x05: PRE_DETECT_QUIET Read 0x06: DETECT_WAIT Read 0x07: CFG_LINKWD_START Read 0x08: CFG_LINKWD_ACEPT Read 0x09: CFG_LANENUM_WAIT Read 0x0A: CFG_LANENUM_ACEPT Read 0x0B: CFG_COMPLETE Read 0x0C: CFG_IDLE Read 0x0D: RCVRY_LOCK Read 0x0E: RCVRY_SPEED Read 0x0F: RCVRY_RCVRCFG Read 0x10: RCVRY_IDLE Read 0x11: L0 Read 0x12: L0S Read 0x13: L123_SEND_EIDLE Read 0x14: L1_IDLE Read 0x15: L2_IDLE Read 0x16: L2_WAKE Read 0x17: DISABLED_ENTRY Read 0x18: DISABLED_IDLE Read 0x19: DISABLED Read 0x1A: LPBK_ENTRY Read 0x1B: LPBK_ACTIVE Read 0x1C: LPBK_EXIT Read 0x1D: LPBK_EXIT_TIMEOUT Read 0x1E: HOT_RESET_ENTRY Read 0x1F: HOT_RESET Read 0x20: RCVRY_EQ0 Read 0x21: RCVRY_EQ1 Read 0x22: RCVRY_EQ2 Read 0x23: RCVRY_EQ3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--20. " DEV_NUM ,PCIe device number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 21.--28. 1. " BUS_NUM ,PCIe bus number" textline " " bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" group.byte 0x108++0x3 line.long 0x0 "PCIECTRL_TI_CONF_PM_CTRL,Power Management Control" bitfld.long 0x0 0. " PME_TURN_OFF ,Transmits PME_Turn_Off message downstream (RC mode only); Eventually sends all links of hierarchy domain to L2L/3_ready" "0,1" bitfld.long 0x0 1. " PM_PME ,Transmits PM_PME wakeup message (EP mode only)" "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " L23_READY ,Indicates system readiness for the link to enter L2/L3 ready state (EP mode only); Allows the transmission of PM_Enter_L23 following PM_Turn_OFF/PME_TO_Ack handshake. Self-cleared upon transition to L2/L3." "0,1" textline " " bitfld.long 0x0 9. " REQ_ENTR_L1 ,Request to transition to L1 state" "0,1" bitfld.long 0x0 10. " REQ_EXIT_L1 ,Request to exit L1 state (to L0)" "0,1" textline " " bitfld.long 0x0 11. " AUX_PWR_DET ,Auxilliary Power Detection; Status of Vaux detection for the PCIe controller; Determines transition to L2 vs L3 upon Vmain turn-off." "0,1" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "PCIECTRL_TI_CONF_PHY_CS,Physical Layer Control and Status" bitfld.long 0x0 0. " REVERSE_LANES ,Manual lane reversal control, allowing lane 0 and lane 1 to be swapped by default; Both Tx and Rx are reversed; Polarity of the individual lane is unchanged" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " LINK_UP ,Link status, from LTSSM" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "PCIECTRL_TI_CONF_INTX_ASSERT,Legacy INTx ASSERT message control, with 'x' in (A,B,C,D) set by the 'Interrupt Pin' field. Write 1 to send message, read to get the status; EP mode only" bitfld.long 0x0 0. " ASSERT_F0 ,INTx ASSERT for function 0 Write 0: No action Read 0: INTx is inactive (has been deasserted) Write 1: Transmit INTx ASSERT to RC Read 1: INTx is active (has been asserted)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x128++0x3 line.long 0x0 "PCIECTRL_TI_CONF_INTX_DEASSERT,Legacy INTx DEASSERT message control, with 'x' in (A,B,C,D) set by the 'Interrupt Pin' field. Write 1 to send message, read to get the status; EP mode only" bitfld.long 0x0 0. " DEASSERT_F0 ,INTx DEASSERT for function 0 Write 0: No action Read 0: INTx is inactive (has been deasserted) Write 1: Transmit INTx DEASSERT to RC Read 1: INTx is active (has been asserted)" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x12C++0x3 line.long 0x0 "PCIECTRL_TI_CONF_MSI_XMT,MSI transmitter (EP mode); Specifies parameters of MSI, together with MSI capability descriptor already configured by remote RC." bitfld.long 0x0 0. " MSI_REQ_GRANT ,MSI transmit request (and grant status) Write 0: No Action Read 0: MSI transmission request pending Read 1: No MSI request pending (last request granted) Write 1: Request MSI transmission" "0,1" bitfld.long 0x0 1.--3. " MSI_FUNC_NUM ,Function number for transmitted MSI; Always 0 for single-function EP" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--6. " MSI_TC ,Traffic class (TC) for transmitted MSI" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7.--11. " MSI_VECTOR ,Vector number for transmitted MSI (as allowed by RC at enumeration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x140++0x3 line.long 0x0 "PCIECTRL_TI_CONF_DEBUG_CFG,Configuration of debug_data output and register (observability)" bitfld.long 0x0 0.--5. " SEL ,Debug_data mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x144++0x3 line.long 0x0 "PCIECTRL_TI_CONF_DEBUG_DATA,Debug data vector, depending on DEBUG_CFG.sel value" hexmask.long 0x0 0.--31. 1. " DEBUG ," group.byte 0x148++0x3 line.long 0x0 "PCIECTRL_TI_CONF_DIAG_CTRL,Diagnostic control" bitfld.long 0x0 0. " INV_LCRC ,Corrupts LSB of LCRC in the next packet, then self-clears. Read 0: No CRC corruption pending Read 1: CRC corruption pending Write 1: Request CRC corruption" "0,1" bitfld.long 0x0 1. " INV_ECRC ,Corrupt LSB of ECRC in the next packet, then self-clears. Read 0: No CRC corruption pending Read 1: CRC corruption pending Write 1: Request CRC corruption" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,software must always keep this bit at its default value - 0." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS1_RC_CFG_DBICS2" base ad:0x51001000 width 47. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x0 0.--15. 1. " VENDORID ,Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " DEVICEID ,Device ID (CS)" group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x0 0. " IO_SPACE_EN ,IO Space Enable (ISE)" "0,1" bitfld.long 0x0 1. " MEM_SPACE_EN ,Memory Space Enable (MSE)" "0,1" textline " " bitfld.long 0x0 2. " BUSMASTER_EN ,Bus Master Enable (BME)" "0,1" bitfld.long 0x0 3. " SPEC_CYCLE_EN ,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 4. " MEMWR_INVA ,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 5. " VGA_SNOOP ,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 6. " PARITYERRRESP ,Parity Error Response" "0,1" bitfld.long 0x0 7. " IDSEL_CTRL ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 8. " SERR_EN ,SERR Enable" "0,1" bitfld.long 0x0 9. " FAST_BBEN ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 10. " INTX_ASSER_DIS ,INTx Assertion Disable" "0,1" hexmask.long.byte 0x0 11.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " INTX_STATUS ,INTx Status" "0,1" bitfld.long 0x0 20. " CAP_LIST ,Capabilities List Hardwired to 1" "0,1" textline " " bitfld.long 0x0 21. " C66MHZ_CAP ,66MHz Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 23. " FAST_B2B ,Back to Back Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 24. " MASTERDATA_PARERR ,Master Data Parity Error" "0,1" textline " " bitfld.long 0x0 25.--26. " DEVSEL_TIME ,DevSel Timing, Harsdwired to 0 for PCIExpress" "0,1,2,3" bitfld.long 0x0 27. " SIGNAL_TRGTABORT ,Signaled Target Abort" "0,1" textline " " bitfld.long 0x0 28. " RCVD_TRGTABORT ,Received Target Abort" "0,1" bitfld.long 0x0 29. " RCVD_MASTERABORT ,Received Master Abort" "0,1" textline " " bitfld.long 0x0 30. " SIGNAL_SYSERR ,Signaled System Error" "0,1" bitfld.long 0x0 31. " DETECT_PARERR ,Detected Parity Error" "0,1" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x0 0.--7. 1. " REVID ,Revision ID (CS)" hexmask.long.byte 0x0 8.--15. 1. " PROG_IF_CODE ,Programming Interface Code (CS)" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBCLS_CD ,Sub Class Code (CS)" hexmask.long.byte 0x0 24.--31. 1. " BASE_CLS_CD ,Base Class Code (CS)" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_BIST_HEAD_LAT_CACH,BIST, Header Type, Latency Timer, Cache Line Size" hexmask.long.byte 0x0 0.--7. 1. " CACH_LN_SZE ,Cache Line Size, No impact on write, write is allowed only for legacy purpose" hexmask.long.byte 0x0 8.--15. 1. " MSTR_LAT_TIM ,Master Latency Timer, Not Applicable for PCIe hence hardwired to 0" textline " " hexmask.long.byte 0x0 16.--22. 1. " HEAD_TYP ,Header Type" bitfld.long 0x0 23. " MFD ,MultiFunction Device" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " BIST ,BIST" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR Reads like in CS mode" bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_BAR1_MASK,Base Address Register 1 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode, contains the upper bits of BAR0 mask Reads like in CS mode" bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x0 0.--7. 1. " PRIM_BUS_NUM ,Primary Bus Number" hexmask.long.byte 0x0 8.--15. 1. " SEC_BUS_NUM ,Secondary Bus Number" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBORD_BUS_NUM ,Subordinate Bus Number" hexmask.long.byte 0x0 24.--31. 1. " SEC_LAT_TIMER ,Secondary Latency Timer, Not Applicable for PCI Express hence hardwired to 0" group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_IOBASE_LIMIT_SEC_STATUS,IO Base,Limit and Secondary Status Register" bitfld.long 0x0 0. " IODECODE_32_0 ,32 or 16 Bit IO Space (CS)" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--7. " IO_SPACE_BASE ,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " IODECODE_32 ,32 or 16 Bit IO Space" "0,1" textline " " bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--15. " IO_SPACE_LIMIT ,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21. " C66MHZ_CAPA ,66MHz Capable, Not Applicable for PCI Express hence hardwired to 0" "0,1" textline " " bitfld.long 0x0 22. " RESERVED ," "0,1" bitfld.long 0x0 23. " FAST_B2B_CAP ,Fast Back to Back Capable, Not Applicable for PCI Express hence hardwired to 0" "0,1" textline " " bitfld.long 0x0 24. " MSTR_DATA_PRTY_ERR ,Mastered Data Parity Error" "0,1" bitfld.long 0x0 25.--26. " DEVSEL_TIMING ,DEVSEL Timing, Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" textline " " bitfld.long 0x0 27. " SGNLD_TRGT_ABORT ,Signaled Target Error" "0,1" bitfld.long 0x0 28. " RCVD_TRGT_ABORT ,Received Target Error" "0,1" textline " " bitfld.long 0x0 29. " RCVD_MSTR_ABORT ,Received Master Abort" "0,1" bitfld.long 0x0 30. " RCVD_SYS_ERR ,Received System Error" "0,1" textline " " bitfld.long 0x0 31. " DET_PAR_ERR ,Detected Parity Error" "0,1" group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_MEM_BASE_LIMIT,Memory Base and Limit Register" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " MEM_BASE_ADDR ,Memory Base Address" textline " " bitfld.long 0x0 16.--19. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " MEM_LIMIT_ADDR ,Memory Limit Address" group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" bitfld.long 0x0 0. " MEMDECODE_64_0 ,64-Bit Memory Addressing" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 4.--15. 1. " UPPPREF_MEM_ADDR ,Upper 12 bits of 32-bit Prefetchable Memory start Address" bitfld.long 0x0 16. " MEMDECODE_64 ,64-Bit Memory Addressing" "0,1" textline " " bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 20.--31. 1. " PREF_MEM_ADDR ,Upper 12 bits of 32-bit Prefetchable Memory End Address" group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" hexmask.long 0x0 0.--31. 1. " ADDRUPP ,Upper 32 Bits of Base Address of Prefetachable Memory Space, Used only if 64 Bit Prefetachable Addresing is enabled" group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" hexmask.long 0x0 0.--31. 1. " ADDRUPP_LIMIT ,Upper 32 Bits of Limit Address of Prefetachable Memory Space, Used only if 64 Bit Prefetachable Addresing is enabled" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x0 0.--15. 1. " UPP16_IOBASE ,Upper 16 IO Base Address" hexmask.long.word 0x0 16.--31. 1. " UPP16_IOLIMIT ,Upper 16 IO Limit Address" group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x0 0.--7. 1. " CAPTR ,First Capability Pointer (CS)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" bitfld.long 0x0 0. " EXP_ROM_EN ,Expansion ROM Enable" "0,1" hexmask.long.word 0x0 1.--10. 1. " RESERVED ," textline " " bitfld.long 0x0 11.--15. " EXROM_ADDRESS_RO ,Expansion ROM address, masked." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--31. 1. " EXROM_ADDRESS ,Expansion ROM address, unmasked (ie programmable)" group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_BRIDGE_INT,Bridge Control and Int Pin and line" hexmask.long.byte 0x0 0.--7. 1. " INT_LIN ,Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. " INT_PIN ,Interrupt Pin (CS)" textline " " bitfld.long 0x0 16. " PERR_RESP_EN ,Parity Error Response Enable" "0,1" bitfld.long 0x0 17. " SERR_EN ,SERR Enable" "0,1" textline " " bitfld.long 0x0 18. " ISA_EN ,ISA Enable" "0,1" bitfld.long 0x0 19. " VGA_EN ,VGA Enable" "0,1" textline " " bitfld.long 0x0 20. " VGA_16B_DEC ,VGA 16-Bit Decode" "0,1" bitfld.long 0x0 21. " MST_ABT_MOD ,Master Abort Mode" "0,1" textline " " bitfld.long 0x0 22. " SEC_BUS_RST ,Secondary Bus Reset (initiate hot reset)" "0,1" bitfld.long 0x0 23. " FAST_B2B_EN ,Fast Back-to-Back Transactions Enable" "0,1" textline " " bitfld.long 0x0 24. " PRI_DT ,Primary Discard Timer" "0,1" bitfld.long 0x0 25. " SEC_DT ,Secondary Discard Timer" "0,1" textline " " bitfld.long 0x0 26. " DT_STS ,Discard Timer Status" "0,1" bitfld.long 0x0 27. " DT_SERR_EN ,Discard Timer SERR Enable Status" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x70++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_PCIE_CAP,PCI Express Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PCIE_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--19. " PCIE_VER ,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " DEV_TYPE ,Device/Port Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SLOT ,Slot Implemented (CS)" "0,1" bitfld.long 0x0 25.--29. " IM_NUM ,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x74++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x0 0.--2. " MAX_PAYLOAD_SIZE ,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " PHANTOMFUNC ,Phantom Function Support, not SUPPORTED (CS)" "0,1,2,3" textline " " bitfld.long 0x0 5. " EXTTAGFIELD_SUPPORT ,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x0 6.--8. " DEFAULT_EP_L0S_ACCPT_LATENCY ,Endpoint L0s Acceptable Latency; Must be 0 for RC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " DEFAULT_EP_L1_ACCPT_LATENCY ,Endpoint L1 Acceptable Latency; Must be 0 for RC." "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " UNDEFINED ,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ROLEBASED_ERRRPT ,Role Based Error Reporting (CS)" "0,1" bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 18.--25. 1. " CAPT_SLOW_PWRLIMIT_VALUE ,Captured Slow Power Limit Value, for Upstream Port Only (CS)" bitfld.long 0x0 26.--27. " CAPT_SLOW_PWRLIMIT_SCALE ,Captured Slow Power Scale Value, for Upstream Port Only (CS)" "0,1,2,3" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x78++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_DEV_CAS,PCIE Device Control and Status" bitfld.long 0x0 0. " COR_RE ,Correctable Error Reporting Enable" "0,1" bitfld.long 0x0 1. " NFT_RE ,Non-Fatal Error Reporting Enable" "0,1" textline " " bitfld.long 0x0 2. " FT_RE ,Fatal Error Reporting Enable" "0,1" bitfld.long 0x0 3. " UR_RE ,Unsupported Request Reporting Enable" "0,1" textline " " bitfld.long 0x0 4. " EN_RO ,Enable Relaxed Ordering" "0,1" bitfld.long 0x0 5.--7. " MPS ,Max_Payload_Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " EXTAG_EN ,Extended Tag Field Enable" "0,1" bitfld.long 0x0 9. " PHFUN_EN ,Phantom Function Enable" "0,1" textline " " bitfld.long 0x0 10. " AUXPM_EN ,AUX Power PM Enable (Sticky bit)" "0,1" bitfld.long 0x0 11. " NOSNP_EN ,Enable No Snoop" "0,1" textline " " bitfld.long 0x0 12.--14. " MRRS ,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " INIT_FLR ,Reserved" "0,1" textline " " bitfld.long 0x0 16. " COR_DET ,Correctable Error Detected" "0,1" bitfld.long 0x0 17. " NFT_DET ,Non-Fatal Error Detected" "0,1" textline " " bitfld.long 0x0 18. " FT_DET ,Fatal Error Detected" "0,1" bitfld.long 0x0 19. " UR_DET ,Unsupported Request Detected" "0,1" textline " " bitfld.long 0x0 20. " AUXP_DET ,Aux Power Detected" "0,1" bitfld.long 0x0 21. " TRANS_PEND ,Transaction Pending" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_LNK_CAP,PCIE Link Capabilities" bitfld.long 0x0 0.--3. " MAX_LINK_SPEEDS ,Supported Max Link Speed (CS) Read 0x1: 2.5 GT/s (Gen1) Read 0x2: 5 GT/s (Gen2) Read 0x3: 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--9. " MAX_LINK_WIDTH ,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 10.--11. " AS_LINK_PM_SUPPORT ,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0 12.--14. " COMM_L0S_EXIT_LAT ,Common-clock-mode L0s Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " COMM_L1_EXIT_LAT ,Common-clock-mode L1 Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18. " CLK_PWR_MGMT ,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" textline " " bitfld.long 0x0 19. " UNSUP ,Unsupported, Surprise Down Error Reporting Capable, Hardwired to 0" "0,1" bitfld.long 0x0 20. " DLL_ACTRPT_CAP ,Data Link Layer Active Reporting Capable" "0,1" textline " " bitfld.long 0x0 21. " LNK_BW_not_CAP ,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0 22. " ASPM_OPT_COMP ,ASPM Optionality Compliance (CS)" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" hexmask.long.byte 0x0 24.--31. 1. " PORT_NUM ,Port Number (CS)" group.byte 0x80++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x0 0.--1. " ASPM_CTRL ,Active State Link PM Control 0x0: DISABLED 0x1: L0S_ENABLED 0x2: L1_ENABLED 0x3: L0S_AND_L1_ENABLED" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " RCB ,Read Completion Boundary (CS)" "0,1" bitfld.long 0x0 4. " LINK_DIS ,Link Disable" "0,1" textline " " bitfld.long 0x0 5. " RETRAIN_LINK ,Retrain Link" "0,1" bitfld.long 0x0 6. " COM_CLK_CFG ,Common Clock Configuration" "0,1" textline " " bitfld.long 0x0 7. " EXT_SYN ,Extended Synch" "0,1" bitfld.long 0x0 8. " EN_CPM ,Enable Clock Power Management" "0,1" textline " " bitfld.long 0x0 9. " HAWD ,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x0 10. " LBMIE ,Link Bandwidth Management Interrupt Enable" "0,1" textline " " bitfld.long 0x0 11. " LABIE ,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " LINK_SPEED ,Link Speed; UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " NEG_LW ,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 26. " UNDEF ,Undefined" "0,1" bitfld.long 0x0 27. " LINK_TRAIN ,LINK training" "0,1" textline " " bitfld.long 0x0 28. " SLOT_CLK_CONFIG ,Slot Clock Configuration (CS)" "0,1" bitfld.long 0x0 29. " DLL_ACT ,Data Link Layer Active" "0,1" textline " " bitfld.long 0x0 30. " LBW_STATUS ,Link Bandwidth Management Status" "0,1" bitfld.long 0x0 31. " LAB_STATUS ,Link Autonomous Bandwidth Status" "0,1" group.byte 0x84++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_SLOT_CAP,Slot Capabilities Register" bitfld.long 0x0 0. " ABP ,Attention Button Present (CS)" "0,1" bitfld.long 0x0 1. " PCP ,Power Controller Present (CS)" "0,1" textline " " bitfld.long 0x0 2. " MRLSP ,MRL Sensor Present (CS)" "0,1" bitfld.long 0x0 3. " AIP ,Attention Indicator Present (CS)" "0,1" textline " " bitfld.long 0x0 4. " PIP ,Power Indicator Present (CS)" "0,1" bitfld.long 0x0 5. " HPS ,Hot-Plug Surprise (CS)" "0,1" textline " " bitfld.long 0x0 6. " HPC ,Hot-Plug Capable (CS)" "0,1" hexmask.long.byte 0x0 7.--14. 1. " SPLV ,Slot Power Limit Value (CS)" textline " " bitfld.long 0x0 15.--16. " SPLS ,Slot Power Limit Scale (CS)" "0,1,2,3" bitfld.long 0x0 17. " EIP ,Electromechanical Interlock Present (CS)" "0,1" textline " " bitfld.long 0x0 18. " NCCS ,No Command Complete Support (CS)" "0,1" hexmask.long.word 0x0 19.--31. 1. " PSN ,Physical Slot Number (CS)" group.byte 0x88++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x0 0. " ABP_EN ,Attention Button Pressed Enable" "0,1" bitfld.long 0x0 1. " PFD_EN ,Power Fault Detected Enable" "0,1" textline " " bitfld.long 0x0 2. " MRLSC_EN ,MRL Sensor Changed Enable" "0,1" bitfld.long 0x0 3. " PDC_EN ,Presence Detect Changed Enable" "0,1" textline " " bitfld.long 0x0 4. " CCI_EN ,Command Completed Interrupt Enable" "0,1" bitfld.long 0x0 5. " HPI_EN ,Hot-Plug Interrupt Enable" "0,1" textline " " bitfld.long 0x0 6.--7. " AIC ,Attention Indicator Control" "0,1,2,3" bitfld.long 0x0 8.--9. " PIC ,Power Indicator Control" "0,1,2,3" textline " " bitfld.long 0x0 10. " PCC ,Power Controller Control" "0,1" bitfld.long 0x0 11. " EIC ,Electromechanical Interlock Control" "0,1" textline " " bitfld.long 0x0 12. " DSC_EN ,Data Link Layer State Changed Enable" "0,1" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " ABP ,Attention Button Pressed" "0,1" bitfld.long 0x0 17. " PFD ,Power Fault Detected" "0,1" textline " " bitfld.long 0x0 18. " MRCSC ,MRL Sensor Changed" "0,1" bitfld.long 0x0 19. " PDC ,Presence Detect Changed" "0,1" textline " " bitfld.long 0x0 20. " CC ,Command Completed" "0,1" bitfld.long 0x0 21. " MRLSS ,MRL Sensor State" "0,1" textline " " bitfld.long 0x0 22. " PDS ,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" bitfld.long 0x0 23. " EIS ,Electromechanical Interlock Status" "0,1" textline " " bitfld.long 0x0 24. " DSC ,Data Link Layer State Changed" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_ROOT_CAC,Root Control and Capability Register" bitfld.long 0x0 0. " SECE_EN ,System Error on Correctable Error Enable" "0,1" bitfld.long 0x0 1. " SENE_EN ,System Error on Non-fatal Error Enable" "0,1" textline " " bitfld.long 0x0 2. " SEFE_EN ,System Error on Fatal Error Enable" "0,1" bitfld.long 0x0 3. " PMEI_EN ,PME Interrupt Enable" "0,1" textline " " bitfld.long 0x0 4. " CRSSV_EN ,CRS Software Visibility Enable" "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " CRSSV ,CRS Software Visibility" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_ROOT_STS,Root Status Register" hexmask.long.word 0x0 0.--15. 1. " PME_RID ,PME Requester ID" bitfld.long 0x0 16. " PME_STS ,PME Status (Sticky bit)" "0,1" textline " " bitfld.long 0x0 17. " PME_PND ,PME Pending" "0,1" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_RNG_SUPPORTED ,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS_SUPPORTED ,Completion Timeout Disable Supported" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOR_SP ,AtomicOp Routing Supported" "0,1" textline " " bitfld.long 0x0 7. " AOC32_SP ,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x0 8. " AOC64_SP ,64-bit AtomicOp Completer Supported" "0,1" textline " " bitfld.long 0x0 9. " CASC128_SP ,128-bit CAS Completer Supported" "0,1" bitfld.long 0x0 10. " NOROPR ,No RO-enabled PR-PR Passing" "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " TPHC_SP ,TPH Completer Supported" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_VALUE ,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS ,Completion Timeout Disable" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOP_REQ_EN ,AtomicOp Requester Enable" "0,1" textline " " bitfld.long 0x0 7. " AOP_EG_BLK ,AtomicOp Egress Blocking" "0,1" bitfld.long 0x0 8. " IDO_REQ_EN ,IDO Request Enable" "0,1" textline " " bitfld.long 0x0 9. " IDO_CPL_EN ,IDO Completion Enable" "0,1" bitfld.long 0x0 10. " LTR_EN ,LTR Mechanism Enable" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13.--14. " OBFF_EN ,OBFF Enable" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long.byte 0x0 1.--7. 1. " SP_LS_VEC ,Supported Link Speeds Vector" textline " " bitfld.long 0x0 8. " CROSSLINK_SP ,Crosslink Supported" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x0 0.--3. " TRGT_LINK_SPEED ,Target Link Speed: Read 0x1: 2.5 GT/s (Gen1) Read 0x2: 5 GT/s (Gen2) Read 0x3: 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENTR_COMPL ,Enter Compliance" "0,1" textline " " bitfld.long 0x0 5. " HW_AUTO_SP_DIS ,Hardware Autonomous Speed Disable" "0,1" bitfld.long 0x0 6. " SEL_DEEMP ,Selectable De-emphasis (CS)" "0,1" textline " " bitfld.long 0x0 7.--9. " TX_MARGIN ,Transmit Margin" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. " ENT_MOD_COMPL ,Enter Modified Compliance" "0,1" textline " " bitfld.long 0x0 11. " COMPL_SOS ,Compliance SOS" "0,1" bitfld.long 0x0 12.--15. " COMPL_PRST_DEEPH ,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DEEMPH_LEVEL ,Current De-emphasis Level" "0,1" bitfld.long 0x0 17. " EQ_COMPLETE ,Equalization Complete, Gen3 Only" "0,1" textline " " bitfld.long 0x0 18. " EQ_PH1 ,Equalization Ph1 Success, Gen3 Only" "0,1" bitfld.long 0x0 19. " EQ_PH2 ,Equalization Ph2 Success, Gen3 Only" "0,1" textline " " bitfld.long 0x0 20. " EQ_PH3 ,Equalization Ph3 Success, Gen3 Only" "0,1" bitfld.long 0x0 21. " LINK_EQ_REQ ,Link Equilization Request" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS2_RC_CFG_DBICS2" base ad:0x51801000 width 47. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x0 0.--15. 1. " VENDORID ,Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " DEVICEID ,Device ID (CS)" group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x0 0. " IO_SPACE_EN ,IO Space Enable (ISE)" "0,1" bitfld.long 0x0 1. " MEM_SPACE_EN ,Memory Space Enable (MSE)" "0,1" textline " " bitfld.long 0x0 2. " BUSMASTER_EN ,Bus Master Enable (BME)" "0,1" bitfld.long 0x0 3. " SPEC_CYCLE_EN ,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 4. " MEMWR_INVA ,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 5. " VGA_SNOOP ,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 6. " PARITYERRRESP ,Parity Error Response" "0,1" bitfld.long 0x0 7. " IDSEL_CTRL ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 8. " SERR_EN ,SERR Enable" "0,1" bitfld.long 0x0 9. " FAST_BBEN ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 10. " INTX_ASSER_DIS ,INTx Assertion Disable" "0,1" hexmask.long.byte 0x0 11.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " INTX_STATUS ,INTx Status" "0,1" bitfld.long 0x0 20. " CAP_LIST ,Capabilities List Hardwired to 1" "0,1" textline " " bitfld.long 0x0 21. " C66MHZ_CAP ,66MHz Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 23. " FAST_B2B ,Back to Back Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 24. " MASTERDATA_PARERR ,Master Data Parity Error" "0,1" textline " " bitfld.long 0x0 25.--26. " DEVSEL_TIME ,DevSel Timing, Harsdwired to 0 for PCIExpress" "0,1,2,3" bitfld.long 0x0 27. " SIGNAL_TRGTABORT ,Signaled Target Abort" "0,1" textline " " bitfld.long 0x0 28. " RCVD_TRGTABORT ,Received Target Abort" "0,1" bitfld.long 0x0 29. " RCVD_MASTERABORT ,Received Master Abort" "0,1" textline " " bitfld.long 0x0 30. " SIGNAL_SYSERR ,Signaled System Error" "0,1" bitfld.long 0x0 31. " DETECT_PARERR ,Detected Parity Error" "0,1" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x0 0.--7. 1. " REVID ,Revision ID (CS)" hexmask.long.byte 0x0 8.--15. 1. " PROG_IF_CODE ,Programming Interface Code (CS)" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBCLS_CD ,Sub Class Code (CS)" hexmask.long.byte 0x0 24.--31. 1. " BASE_CLS_CD ,Base Class Code (CS)" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_BIST_HEAD_LAT_CACH,BIST, Header Type, Latency Timer, Cache Line Size" hexmask.long.byte 0x0 0.--7. 1. " CACH_LN_SZE ,Cache Line Size, No impact on write, write is allowed only for legacy purpose" hexmask.long.byte 0x0 8.--15. 1. " MSTR_LAT_TIM ,Master Latency Timer, Not Applicable for PCIe hence hardwired to 0" textline " " hexmask.long.byte 0x0 16.--22. 1. " HEAD_TYP ,Header Type" bitfld.long 0x0 23. " MFD ,MultiFunction Device" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " BIST ,BIST" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_BAR0_MASK,Base Address Register 0 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR Reads like in CS mode" bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_BAR1_MASK,Base Address Register 1 Mask (CS2 mode only) Write 1 to BAR[0] to enable the BAR Write ones to BAR[M-1:1] for a 2**M byte BAR If BAR0 is in 64-bit mode, contains the upper bits of BAR0 mask Reads like in CS mode" bitfld.long 0x0 0. " BAR_ENABLED ,BAR enabled (CS2 only)" "0,1" hexmask.long 0x0 1.--31. 1. " BAR_MASK ,Write 1 to unmask/0 to mask the BAR address bit (CS2 only)" group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x0 0.--7. 1. " PRIM_BUS_NUM ,Primary Bus Number" hexmask.long.byte 0x0 8.--15. 1. " SEC_BUS_NUM ,Secondary Bus Number" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBORD_BUS_NUM ,Subordinate Bus Number" hexmask.long.byte 0x0 24.--31. 1. " SEC_LAT_TIMER ,Secondary Latency Timer, Not Applicable for PCI Express hence hardwired to 0" group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_IOBASE_LIMIT_SEC_STATUS,IO Base,Limit and Secondary Status Register" bitfld.long 0x0 0. " IODECODE_32_0 ,32 or 16 Bit IO Space (CS)" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--7. " IO_SPACE_BASE ,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " IODECODE_32 ,32 or 16 Bit IO Space" "0,1" textline " " bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--15. " IO_SPACE_LIMIT ,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21. " C66MHZ_CAPA ,66MHz Capable, Not Applicable for PCI Express hence hardwired to 0" "0,1" textline " " bitfld.long 0x0 22. " RESERVED ," "0,1" bitfld.long 0x0 23. " FAST_B2B_CAP ,Fast Back to Back Capable, Not Applicable for PCI Express hence hardwired to 0" "0,1" textline " " bitfld.long 0x0 24. " MSTR_DATA_PRTY_ERR ,Mastered Data Parity Error" "0,1" bitfld.long 0x0 25.--26. " DEVSEL_TIMING ,DEVSEL Timing, Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" textline " " bitfld.long 0x0 27. " SGNLD_TRGT_ABORT ,Signaled Target Error" "0,1" bitfld.long 0x0 28. " RCVD_TRGT_ABORT ,Received Target Error" "0,1" textline " " bitfld.long 0x0 29. " RCVD_MSTR_ABORT ,Received Master Abort" "0,1" bitfld.long 0x0 30. " RCVD_SYS_ERR ,Received System Error" "0,1" textline " " bitfld.long 0x0 31. " DET_PAR_ERR ,Detected Parity Error" "0,1" group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_MEM_BASE_LIMIT,Memory Base and Limit Register" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " MEM_BASE_ADDR ,Memory Base Address" textline " " bitfld.long 0x0 16.--19. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " MEM_LIMIT_ADDR ,Memory Limit Address" group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" bitfld.long 0x0 0. " MEMDECODE_64_0 ,64-Bit Memory Addressing" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 4.--15. 1. " UPPPREF_MEM_ADDR ,Upper 12 bits of 32-bit Prefetchable Memory start Address" bitfld.long 0x0 16. " MEMDECODE_64 ,64-Bit Memory Addressing" "0,1" textline " " bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 20.--31. 1. " PREF_MEM_ADDR ,Upper 12 bits of 32-bit Prefetchable Memory End Address" group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" hexmask.long 0x0 0.--31. 1. " ADDRUPP ,Upper 32 Bits of Base Address of Prefetachable Memory Space, Used only if 64 Bit Prefetachable Addresing is enabled" group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" hexmask.long 0x0 0.--31. 1. " ADDRUPP_LIMIT ,Upper 32 Bits of Limit Address of Prefetachable Memory Space, Used only if 64 Bit Prefetachable Addresing is enabled" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x0 0.--15. 1. " UPP16_IOBASE ,Upper 16 IO Base Address" hexmask.long.word 0x0 16.--31. 1. " UPP16_IOLIMIT ,Upper 16 IO Limit Address" group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_CAPPTR,CapPtr" hexmask.long.byte 0x0 0.--7. 1. " CAPTR ,First Capability Pointer (CS)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" bitfld.long 0x0 0. " EXP_ROM_EN ,Expansion ROM Enable" "0,1" hexmask.long.word 0x0 1.--10. 1. " RESERVED ," textline " " bitfld.long 0x0 11.--15. " EXROM_ADDRESS_RO ,Expansion ROM address, masked." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--31. 1. " EXROM_ADDRESS ,Expansion ROM address, unmasked (ie programmable)" group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_BRIDGE_INT,Bridge Control and Int Pin and line" hexmask.long.byte 0x0 0.--7. 1. " INT_LIN ,Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. " INT_PIN ,Interrupt Pin (CS)" textline " " bitfld.long 0x0 16. " PERR_RESP_EN ,Parity Error Response Enable" "0,1" bitfld.long 0x0 17. " SERR_EN ,SERR Enable" "0,1" textline " " bitfld.long 0x0 18. " ISA_EN ,ISA Enable" "0,1" bitfld.long 0x0 19. " VGA_EN ,VGA Enable" "0,1" textline " " bitfld.long 0x0 20. " VGA_16B_DEC ,VGA 16-Bit Decode" "0,1" bitfld.long 0x0 21. " MST_ABT_MOD ,Master Abort Mode" "0,1" textline " " bitfld.long 0x0 22. " SEC_BUS_RST ,Secondary Bus Reset (initiate hot reset)" "0,1" bitfld.long 0x0 23. " FAST_B2B_EN ,Fast Back-to-Back Transactions Enable" "0,1" textline " " bitfld.long 0x0 24. " PRI_DT ,Primary Discard Timer" "0,1" bitfld.long 0x0 25. " SEC_DT ,Secondary Discard Timer" "0,1" textline " " bitfld.long 0x0 26. " DT_STS ,Discard Timer Status" "0,1" bitfld.long 0x0 27. " DT_SERR_EN ,Discard Timer SERR Enable Status" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x70++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_PCIE_CAP,PCI Express Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PCIE_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--19. " PCIE_VER ,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " DEV_TYPE ,Device/Port Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SLOT ,Slot Implemented (CS)" "0,1" bitfld.long 0x0 25.--29. " IM_NUM ,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x74++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x0 0.--2. " MAX_PAYLOAD_SIZE ,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " PHANTOMFUNC ,Phantom Function Support, not SUPPORTED (CS)" "0,1,2,3" textline " " bitfld.long 0x0 5. " EXTTAGFIELD_SUPPORT ,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x0 6.--8. " DEFAULT_EP_L0S_ACCPT_LATENCY ,Endpoint L0s Acceptable Latency; Must be 0 for RC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " DEFAULT_EP_L1_ACCPT_LATENCY ,Endpoint L1 Acceptable Latency; Must be 0 for RC." "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " UNDEFINED ,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ROLEBASED_ERRRPT ,Role Based Error Reporting (CS)" "0,1" bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 18.--25. 1. " CAPT_SLOW_PWRLIMIT_VALUE ,Captured Slow Power Limit Value, for Upstream Port Only (CS)" bitfld.long 0x0 26.--27. " CAPT_SLOW_PWRLIMIT_SCALE ,Captured Slow Power Scale Value, for Upstream Port Only (CS)" "0,1,2,3" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x78++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_DEV_CAS,PCIE Device Control and Status" bitfld.long 0x0 0. " COR_RE ,Correctable Error Reporting Enable" "0,1" bitfld.long 0x0 1. " NFT_RE ,Non-Fatal Error Reporting Enable" "0,1" textline " " bitfld.long 0x0 2. " FT_RE ,Fatal Error Reporting Enable" "0,1" bitfld.long 0x0 3. " UR_RE ,Unsupported Request Reporting Enable" "0,1" textline " " bitfld.long 0x0 4. " EN_RO ,Enable Relaxed Ordering" "0,1" bitfld.long 0x0 5.--7. " MPS ,Max_Payload_Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " EXTAG_EN ,Extended Tag Field Enable" "0,1" bitfld.long 0x0 9. " PHFUN_EN ,Phantom Function Enable" "0,1" textline " " bitfld.long 0x0 10. " AUXPM_EN ,AUX Power PM Enable (Sticky bit)" "0,1" bitfld.long 0x0 11. " NOSNP_EN ,Enable No Snoop" "0,1" textline " " bitfld.long 0x0 12.--14. " MRRS ,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " INIT_FLR ,Reserved" "0,1" textline " " bitfld.long 0x0 16. " COR_DET ,Correctable Error Detected" "0,1" bitfld.long 0x0 17. " NFT_DET ,Non-Fatal Error Detected" "0,1" textline " " bitfld.long 0x0 18. " FT_DET ,Fatal Error Detected" "0,1" bitfld.long 0x0 19. " UR_DET ,Unsupported Request Detected" "0,1" textline " " bitfld.long 0x0 20. " AUXP_DET ,Aux Power Detected" "0,1" bitfld.long 0x0 21. " TRANS_PEND ,Transaction Pending" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_LNK_CAP,PCIE Link Capabilities" bitfld.long 0x0 0.--3. " MAX_LINK_SPEEDS ,Supported Max Link Speed (CS) Read 0x1: 2.5 GT/s (Gen1) Read 0x2: 5 GT/s (Gen2) Read 0x3: 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--9. " MAX_LINK_WIDTH ,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 10.--11. " AS_LINK_PM_SUPPORT ,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0 12.--14. " COMM_L0S_EXIT_LAT ,Common-clock-mode L0s Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " COMM_L1_EXIT_LAT ,Common-clock-mode L1 Exit Latency (CS2) Compare CS" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18. " CLK_PWR_MGMT ,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" textline " " bitfld.long 0x0 19. " UNSUP ,Unsupported, Surprise Down Error Reporting Capable, Hardwired to 0" "0,1" bitfld.long 0x0 20. " DLL_ACTRPT_CAP ,Data Link Layer Active Reporting Capable" "0,1" textline " " bitfld.long 0x0 21. " LNK_BW_not_CAP ,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0 22. " ASPM_OPT_COMP ,ASPM Optionality Compliance (CS)" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" hexmask.long.byte 0x0 24.--31. 1. " PORT_NUM ,Port Number (CS)" group.byte 0x80++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x0 0.--1. " ASPM_CTRL ,Active State Link PM Control 0x0: DISABLED 0x1: L0S_ENABLED 0x2: L1_ENABLED 0x3: L0S_AND_L1_ENABLED" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " RCB ,Read Completion Boundary (CS)" "0,1" bitfld.long 0x0 4. " LINK_DIS ,Link Disable" "0,1" textline " " bitfld.long 0x0 5. " RETRAIN_LINK ,Retrain Link" "0,1" bitfld.long 0x0 6. " COM_CLK_CFG ,Common Clock Configuration" "0,1" textline " " bitfld.long 0x0 7. " EXT_SYN ,Extended Synch" "0,1" bitfld.long 0x0 8. " EN_CPM ,Enable Clock Power Management" "0,1" textline " " bitfld.long 0x0 9. " HAWD ,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x0 10. " LBMIE ,Link Bandwidth Management Interrupt Enable" "0,1" textline " " bitfld.long 0x0 11. " LABIE ,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " LINK_SPEED ,Link Speed; UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " NEG_LW ,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 26. " UNDEF ,Undefined" "0,1" bitfld.long 0x0 27. " LINK_TRAIN ,LINK training" "0,1" textline " " bitfld.long 0x0 28. " SLOT_CLK_CONFIG ,Slot Clock Configuration (CS)" "0,1" bitfld.long 0x0 29. " DLL_ACT ,Data Link Layer Active" "0,1" textline " " bitfld.long 0x0 30. " LBW_STATUS ,Link Bandwidth Management Status" "0,1" bitfld.long 0x0 31. " LAB_STATUS ,Link Autonomous Bandwidth Status" "0,1" group.byte 0x84++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_SLOT_CAP,Slot Capabilities Register" bitfld.long 0x0 0. " ABP ,Attention Button Present (CS)" "0,1" bitfld.long 0x0 1. " PCP ,Power Controller Present (CS)" "0,1" textline " " bitfld.long 0x0 2. " MRLSP ,MRL Sensor Present (CS)" "0,1" bitfld.long 0x0 3. " AIP ,Attention Indicator Present (CS)" "0,1" textline " " bitfld.long 0x0 4. " PIP ,Power Indicator Present (CS)" "0,1" bitfld.long 0x0 5. " HPS ,Hot-Plug Surprise (CS)" "0,1" textline " " bitfld.long 0x0 6. " HPC ,Hot-Plug Capable (CS)" "0,1" hexmask.long.byte 0x0 7.--14. 1. " SPLV ,Slot Power Limit Value (CS)" textline " " bitfld.long 0x0 15.--16. " SPLS ,Slot Power Limit Scale (CS)" "0,1,2,3" bitfld.long 0x0 17. " EIP ,Electromechanical Interlock Present (CS)" "0,1" textline " " bitfld.long 0x0 18. " NCCS ,No Command Complete Support (CS)" "0,1" hexmask.long.word 0x0 19.--31. 1. " PSN ,Physical Slot Number (CS)" group.byte 0x88++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x0 0. " ABP_EN ,Attention Button Pressed Enable" "0,1" bitfld.long 0x0 1. " PFD_EN ,Power Fault Detected Enable" "0,1" textline " " bitfld.long 0x0 2. " MRLSC_EN ,MRL Sensor Changed Enable" "0,1" bitfld.long 0x0 3. " PDC_EN ,Presence Detect Changed Enable" "0,1" textline " " bitfld.long 0x0 4. " CCI_EN ,Command Completed Interrupt Enable" "0,1" bitfld.long 0x0 5. " HPI_EN ,Hot-Plug Interrupt Enable" "0,1" textline " " bitfld.long 0x0 6.--7. " AIC ,Attention Indicator Control" "0,1,2,3" bitfld.long 0x0 8.--9. " PIC ,Power Indicator Control" "0,1,2,3" textline " " bitfld.long 0x0 10. " PCC ,Power Controller Control" "0,1" bitfld.long 0x0 11. " EIC ,Electromechanical Interlock Control" "0,1" textline " " bitfld.long 0x0 12. " DSC_EN ,Data Link Layer State Changed Enable" "0,1" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " ABP ,Attention Button Pressed" "0,1" bitfld.long 0x0 17. " PFD ,Power Fault Detected" "0,1" textline " " bitfld.long 0x0 18. " MRCSC ,MRL Sensor Changed" "0,1" bitfld.long 0x0 19. " PDC ,Presence Detect Changed" "0,1" textline " " bitfld.long 0x0 20. " CC ,Command Completed" "0,1" bitfld.long 0x0 21. " MRLSS ,MRL Sensor State" "0,1" textline " " bitfld.long 0x0 22. " PDS ,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" bitfld.long 0x0 23. " EIS ,Electromechanical Interlock Status" "0,1" textline " " bitfld.long 0x0 24. " DSC ,Data Link Layer State Changed" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_ROOT_CAC,Root Control and Capability Register" bitfld.long 0x0 0. " SECE_EN ,System Error on Correctable Error Enable" "0,1" bitfld.long 0x0 1. " SENE_EN ,System Error on Non-fatal Error Enable" "0,1" textline " " bitfld.long 0x0 2. " SEFE_EN ,System Error on Fatal Error Enable" "0,1" bitfld.long 0x0 3. " PMEI_EN ,PME Interrupt Enable" "0,1" textline " " bitfld.long 0x0 4. " CRSSV_EN ,CRS Software Visibility Enable" "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " CRSSV ,CRS Software Visibility" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_ROOT_STS,Root Status Register" hexmask.long.word 0x0 0.--15. 1. " PME_RID ,PME Requester ID" bitfld.long 0x0 16. " PME_STS ,PME Status (Sticky bit)" "0,1" textline " " bitfld.long 0x0 17. " PME_PND ,PME Pending" "0,1" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_RNG_SUPPORTED ,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS_SUPPORTED ,Completion Timeout Disable Supported" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOR_SP ,AtomicOp Routing Supported" "0,1" textline " " bitfld.long 0x0 7. " AOC32_SP ,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x0 8. " AOC64_SP ,64-bit AtomicOp Completer Supported" "0,1" textline " " bitfld.long 0x0 9. " CASC128_SP ,128-bit CAS Completer Supported" "0,1" bitfld.long 0x0 10. " NOROPR ,No RO-enabled PR-PR Passing" "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " TPHC_SP ,TPH Completer Supported" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_VALUE ,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS ,Completion Timeout Disable" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOP_REQ_EN ,AtomicOp Requester Enable" "0,1" textline " " bitfld.long 0x0 7. " AOP_EG_BLK ,AtomicOp Egress Blocking" "0,1" bitfld.long 0x0 8. " IDO_REQ_EN ,IDO Request Enable" "0,1" textline " " bitfld.long 0x0 9. " IDO_CPL_EN ,IDO Completion Enable" "0,1" bitfld.long 0x0 10. " LTR_EN ,LTR Mechanism Enable" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13.--14. " OBFF_EN ,OBFF Enable" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long.byte 0x0 1.--7. 1. " SP_LS_VEC ,Supported Link Speeds Vector" textline " " bitfld.long 0x0 8. " CROSSLINK_SP ,Crosslink Supported" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PCIECTRL_RC_DBICS2_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x0 0.--3. " TRGT_LINK_SPEED ,Target Link Speed: Read 0x1: 2.5 GT/s (Gen1) Read 0x2: 5 GT/s (Gen2) Read 0x3: 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENTR_COMPL ,Enter Compliance" "0,1" textline " " bitfld.long 0x0 5. " HW_AUTO_SP_DIS ,Hardware Autonomous Speed Disable" "0,1" bitfld.long 0x0 6. " SEL_DEEMP ,Selectable De-emphasis (CS)" "0,1" textline " " bitfld.long 0x0 7.--9. " TX_MARGIN ,Transmit Margin" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. " ENT_MOD_COMPL ,Enter Modified Compliance" "0,1" textline " " bitfld.long 0x0 11. " COMPL_SOS ,Compliance SOS" "0,1" bitfld.long 0x0 12.--15. " COMPL_PRST_DEEPH ,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DEEMPH_LEVEL ,Current De-emphasis Level" "0,1" bitfld.long 0x0 17. " EQ_COMPLETE ,Equalization Complete, Gen3 Only" "0,1" textline " " bitfld.long 0x0 18. " EQ_PH1 ,Equalization Ph1 Success, Gen3 Only" "0,1" bitfld.long 0x0 19. " EQ_PH2 ,Equalization Ph2 Success, Gen3 Only" "0,1" textline " " bitfld.long 0x0 20. " EQ_PH3 ,Equalization Ph3 Success, Gen3 Only" "0,1" bitfld.long 0x0 21. " LINK_EQ_REQ ,Link Equilization Request" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS1_RC_CFG_DBICS" base ad:0x51000000 width 46. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x0 0.--15. 1. " VENDORID ,Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " DEVICEID ,Device ID (CS)" group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x0 0. " IO_SPACE_EN ,IO Space Enable (ISE)" "0,1" bitfld.long 0x0 1. " MEM_SPACE_EN ,Memory Space Enable (MSE)" "0,1" textline " " bitfld.long 0x0 2. " BUSMASTER_EN ,Bus Master Enable (BME)" "0,1" bitfld.long 0x0 3. " SPEC_CYCLE_EN ,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 4. " MEMWR_INVA ,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 5. " VGA_SNOOP ,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 6. " PARITYERRRESP ,Parity Error Response" "0,1" bitfld.long 0x0 7. " IDSEL_CTRL ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 8. " SERR_EN ,SERR Enable" "0,1" bitfld.long 0x0 9. " FAST_BBEN ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 10. " INTX_ASSER_DIS ,INTx Assertion Disable" "0,1" hexmask.long.byte 0x0 11.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " INTX_STATUS ,INTx Status" "0,1" bitfld.long 0x0 20. " CAP_LIST ,Capabilities List Hardwired to 1" "0,1" textline " " bitfld.long 0x0 21. " C66MHZ_CAP ,66MHz Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 23. " FAST_B2B ,Back to Back Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 24. " MASTERDATA_PARERR ,Master Data Parity Error" "0,1" textline " " bitfld.long 0x0 25.--26. " DEVSEL_TIME ,DevSel Timing, Harsdwired to 0 for PCIExpress" "0,1,2,3" bitfld.long 0x0 27. " SIGNAL_TRGTABORT ,Signaled Target Abort" "0,1" textline " " bitfld.long 0x0 28. " RCVD_TRGTABORT ,Received Target Abort" "0,1" bitfld.long 0x0 29. " RCVD_MASTERABORT ,Received Master Abort" "0,1" textline " " bitfld.long 0x0 30. " SIGNAL_SYSERR ,Signaled System Error" "0,1" bitfld.long 0x0 31. " DETECT_PARERR ,Detected Parity Error" "0,1" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x0 0.--7. 1. " REVID ,Revision ID (CS)" hexmask.long.byte 0x0 8.--15. 1. " PROG_IF_CODE ,Programming Interface Code (CS)" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBCLS_CD ,Sub Class Code (CS)" hexmask.long.byte 0x0 24.--31. 1. " BASE_CLS_CD ,Base Class Code (CS)" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_BIST_HEAD_LAT_CACH,BIST, Header Type, Latency Timer, Cache Line Size" hexmask.long.byte 0x0 0.--7. 1. " CACH_LN_SZE ,Cache Line Size, No impact on write, write is allowed only for legacy purpose" hexmask.long.byte 0x0 8.--15. 1. " MSTR_LAT_TIM ,Master Latency Timer, Not Applicable for PCIe hence hardwired to 0" textline " " hexmask.long.byte 0x0 16.--22. 1. " HEAD_TYP ,Header Type" bitfld.long 0x0 23. " MFD ,MultiFunction Device" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " BIST ,BIST" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS)" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LS Bit of I/O addressRead 0x0 = 32 bit enum=_32BIT . Read 0x2 = 64 bit enum=_64BIT ." "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask.NOTE: The RO and RW division between bits 19 and 20 is based on the assumption that BAR mask is 20 bits (1MB)." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask.NOTE: The RO and RW division between bits 19 and 20 is based on the assumption that BAR mask is 20 bits (1MB)." group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_BAR1,Base Address Register 1 If BAR0.AS = 64-bit: upper half of BAR0 base address If BAR0.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS)" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O addressRead 0x0 = 32 bit enum=_32BIT . Read 0x2 = 64 bit enum=_64BIT ." "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask.NOTE: The RO and RW division between bits 19 and 20 is based on the assumption that BAR mask is 20 bits (1MB)." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask.NOTE: The RO and RW division between bits 19 and 20 is based on the assumption that BAR mask is 20 bits (1MB)." group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x0 0.--7. 1. " PRIM_BUS_NUM ,Primary Bus Number" hexmask.long.byte 0x0 8.--15. 1. " SEC_BUS_NUM ,Secondary Bus Number" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBORD_BUS_NUM ,Subordinate Bus Number" hexmask.long.byte 0x0 24.--31. 1. " SEC_LAT_TIMER ,Secondary Latency Timer, Not Applicable for PCI Express hence hardwired to 0" group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_IOBASE_LIMIT_SEC_STATUS,IO Base,Limit and Secondary Status Register" bitfld.long 0x0 0. " IODECODE_32_0 ,32 or 16 Bit IO Space (CS)" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--7. " IO_SPACE_BASE ,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " IODECODE_32 ,32 or 16 Bit IO Space" "0,1" textline " " bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--15. " IO_SPACE_LIMIT ,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21. " C66MHZ_CAPA ,66MHz Capable, Not Applicable for PCI Express hence hardwired to 0" "0,1" textline " " bitfld.long 0x0 22. " RESERVED ," "0,1" bitfld.long 0x0 23. " FAST_B2B_CAP ,Fast Back to Back Capable, Not Applicable for PCI Express hence hardwired to 0" "0,1" textline " " bitfld.long 0x0 24. " MSTR_DATA_PRTY_ERR ,Mastered Data Parity Error" "0,1" bitfld.long 0x0 25.--26. " DEVSEL_TIMING ,DEVSEL Timing, Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" textline " " bitfld.long 0x0 27. " SGNLD_TRGT_ABORT ,Signaled Target Error" "0,1" bitfld.long 0x0 28. " RCVD_TRGT_ABORT ,Received Target Error" "0,1" textline " " bitfld.long 0x0 29. " RCVD_MSTR_ABORT ,Received Master Abort" "0,1" bitfld.long 0x0 30. " RCVD_SYS_ERR ,Received System Error" "0,1" textline " " bitfld.long 0x0 31. " DET_PAR_ERR ,Detected Parity Error" "0,1" group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_MEM_BASE_LIMIT,Memory Base and Limit Register" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " MEM_BASE_ADDR ,Memory Base Address" textline " " bitfld.long 0x0 16.--19. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " MEM_LIMIT_ADDR ,Memory Limit Address" group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" bitfld.long 0x0 0. " MEMDECODE_64_0 ,64-Bit Memory Addressing" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 4.--15. 1. " UPPPREF_MEM_ADDR ,Upper 12 bits of 32-bit Prefetchable Memory start Address" bitfld.long 0x0 16. " MEMDECODE_64 ,64-Bit Memory Addressing" "0,1" textline " " bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 20.--31. 1. " PREF_MEM_ADDR ,Upper 12 bits of 32-bit Prefetchable Memory End Address" group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" hexmask.long 0x0 0.--31. 1. " ADDRUPP ,Upper 32 Bits of Base Address of Prefetachable Memory Space, Used only if 64 Bit Prefetachable Addresing is enabled" group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" hexmask.long 0x0 0.--31. 1. " ADDRUPP_LIMIT ,Upper 32 Bits of Limit Address of Prefetachable Memory Space, Used only if 64 Bit Prefetachable Addresing is enabled" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x0 0.--15. 1. " UPP16_IOBASE ,Upper 16 IO Base Address" hexmask.long.word 0x0 16.--31. 1. " UPP16_IOLIMIT ,Upper 16 IO Limit Address" group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x0 0.--7. 1. " CAPTR ,First Capability Pointer (CS)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" bitfld.long 0x0 0. " EXP_ROM_EN ,Expansion ROM Enable" "0,1" hexmask.long.word 0x0 1.--10. 1. " RESERVED ," textline " " bitfld.long 0x0 11.--15. " EXROM_ADDRESS_RO ,Expansion ROM address, masked." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--31. 1. " EXROM_ADDRESS ,Expansion ROM address, unmasked (ie programmable)" group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_BRIDGE_INT,Bridge Control and Int Pin and line" hexmask.long.byte 0x0 0.--7. 1. " INT_LIN ,Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. " INT_PIN ,Interrupt Pin (CS)" textline " " bitfld.long 0x0 16. " PERR_RESP_EN ,Parity Error Response Enable" "0,1" bitfld.long 0x0 17. " SERR_EN ,SERR Enable" "0,1" textline " " bitfld.long 0x0 18. " ISA_EN ,ISA Enable" "0,1" bitfld.long 0x0 19. " VGA_EN ,VGA Enable" "0,1" textline " " bitfld.long 0x0 20. " VGA_16B_DEC ,VGA 16-Bit Decode" "0,1" bitfld.long 0x0 21. " MST_ABT_MOD ,Master Abort Mode" "0,1" textline " " bitfld.long 0x0 22. " SEC_BUS_RST ,Secondary Bus Reset (initiate hot reset)" "0,1" bitfld.long 0x0 23. " FAST_B2B_EN ,Fast Back-to-Back Transactions Enable" "0,1" textline " " bitfld.long 0x0 24. " PRI_DT ,Primary Discard Timer" "0,1" bitfld.long 0x0 25. " SEC_DT ,Secondary Discard Timer" "0,1" textline " " bitfld.long 0x0 26. " DT_STS ,Discard Timer Status" "0,1" bitfld.long 0x0 27. " DT_SERR_EN ,Discard Timer SERR Enable Status" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x70++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_PCIE_CAP,PCI Express Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PCIE_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--19. " PCIE_VER ,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " DEV_TYPE ,Device/Port Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SLOT ,Slot Implemented (CS)" "0,1" bitfld.long 0x0 25.--29. " IM_NUM ,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x74++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x0 0.--2. " MAX_PAYLOAD_SIZE ,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " PHANTOMFUNC ,Phantom Function Support, not SUPPORTED (CS)" "0,1,2,3" textline " " bitfld.long 0x0 5. " EXTTAGFIELD_SUPPORT ,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x0 6.--8. " DEFAULT_EP_L0S_ACCPT_LATENCY ,Endpoint L0s Acceptable Latency; Must be 0 for RC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " DEFAULT_EP_L1_ACCPT_LATENCY ,Endpoint L1 Acceptable Latency; Must be 0 for RC." "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " UNDEFINED ,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ROLEBASED_ERRRPT ,Role Based Error Reporting (CS)" "0,1" bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 18.--25. 1. " CAPT_SLOW_PWRLIMIT_VALUE ,Captured Slow Power Limit Value, for Upstream Port Only (CS)" bitfld.long 0x0 26.--27. " CAPT_SLOW_PWRLIMIT_SCALE ,Captured Slow Power Scale Value, for Upstream Port Only (CS)" "0,1,2,3" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x78++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_DEV_CAS,PCIE Device Control and Status" bitfld.long 0x0 0. " COR_RE ,Correctable Error Reporting Enable" "0,1" bitfld.long 0x0 1. " NFT_RE ,Non-Fatal Error Reporting Enable" "0,1" textline " " bitfld.long 0x0 2. " FT_RE ,Fatal Error Reporting Enable" "0,1" bitfld.long 0x0 3. " UR_RE ,Unsupported Request Reporting Enable" "0,1" textline " " bitfld.long 0x0 4. " EN_RO ,Enable Relaxed Ordering" "0,1" bitfld.long 0x0 5.--7. " MPS ,Max_Payload_Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " EXTAG_EN ,Extended Tag Field Enable" "0,1" bitfld.long 0x0 9. " PHFUN_EN ,Phantom Function Enable" "0,1" textline " " bitfld.long 0x0 10. " AUXPM_EN ,AUX Power PM Enable (Sticky bit)" "0,1" bitfld.long 0x0 11. " NOSNP_EN ,Enable No Snoop" "0,1" textline " " bitfld.long 0x0 12.--14. " MRRS ,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " INIT_FLR ,Reserved" "0,1" textline " " bitfld.long 0x0 16. " COR_DET ,Correctable Error Detected" "0,1" bitfld.long 0x0 17. " NFT_DET ,Non-Fatal Error Detected" "0,1" textline " " bitfld.long 0x0 18. " FT_DET ,Fatal Error Detected" "0,1" bitfld.long 0x0 19. " UR_DET ,Unsupported Request Detected" "0,1" textline " " bitfld.long 0x0 20. " AUXP_DET ,Aux Power Detected" "0,1" bitfld.long 0x0 21. " TRANS_PEND ,Transaction Pending" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_LNK_CAP,PCIE Link Capabilities" bitfld.long 0x0 0.--3. " MAX_LINK_SPEEDS ,Supported Max Link Speed (CS) Read 0x1: 2.5 GT/s (Gen1) Read 0x2: 5 GT/s (Gen2) Read 0x3: 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--9. " MAX_LINK_WIDTH ,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 10.--11. " AS_LINK_PM_SUPPORT ,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0 12.--14. " L0S_EXIT_LAT ,L0s Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " L1_EXIT_LAT ,L1 Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18. " CLK_PWR_MGMT ,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" textline " " bitfld.long 0x0 19. " UNSUP ,Unsupported, Surprise Down Error Reporting Capable, Hardwired to 0" "0,1" bitfld.long 0x0 20. " DLL_ACTRPT_CAP ,Data Link Layer Active Reporting Capable" "0,1" textline " " bitfld.long 0x0 21. " LNK_BW_not_CAP ,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0 22. " ASPM_OPT_COMP ,ASPM Optionality Compliance (CS)" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" hexmask.long.byte 0x0 24.--31. 1. " PORT_NUM ,Port Number (CS)" group.byte 0x80++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x0 0.--1. " ASPM_CTRL ,Active State Link PM Control 0x0: DISABLED 0x1: L0S_ENABLED 0x2: L1_ENABLED 0x3: L0S_AND_L1_ENABLED" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " RCB ,Read Completion Boundary (CS)" "0,1" bitfld.long 0x0 4. " LINK_DIS ,Link Disable" "0,1" textline " " bitfld.long 0x0 5. " RETRAIN_LINK ,Retrain Link" "0,1" bitfld.long 0x0 6. " COM_CLK_CFG ,Common Clock Configuration" "0,1" textline " " bitfld.long 0x0 7. " EXT_SYN ,Extended Synch" "0,1" bitfld.long 0x0 8. " EN_CPM ,Enable Clock Power Management" "0,1" textline " " bitfld.long 0x0 9. " HAWD ,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x0 10. " LBMIE ,Link Bandwidth Management Interrupt Enable" "0,1" textline " " bitfld.long 0x0 11. " LABIE ,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " LINK_SPEED ,Link Speed; UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " NEG_LW ,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 26. " UNDEF ,Undefined" "0,1" bitfld.long 0x0 27. " LINK_TRAIN ,LINK training" "0,1" textline " " bitfld.long 0x0 28. " SLOT_CLK_CONFIG ,Slot Clock Configuration (CS)" "0,1" bitfld.long 0x0 29. " DLL_ACT ,Data Link Layer Active" "0,1" textline " " bitfld.long 0x0 30. " LBW_STATUS ,Link Bandwidth Management Status" "0,1" bitfld.long 0x0 31. " LAB_STATUS ,Link Autonomous Bandwidth Status" "0,1" group.byte 0x84++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_SLOT_CAP,Slot Capabilities Register" bitfld.long 0x0 0. " ABP ,Attention Button Present (CS)" "0,1" bitfld.long 0x0 1. " PCP ,Power Controller Present (CS)" "0,1" textline " " bitfld.long 0x0 2. " MRLSP ,MRL Sensor Present (CS)" "0,1" bitfld.long 0x0 3. " AIP ,Attention Indicator Present (CS)" "0,1" textline " " bitfld.long 0x0 4. " PIP ,Power Indicator Present (CS)" "0,1" bitfld.long 0x0 5. " HPS ,Hot-Plug Surprise (CS)" "0,1" textline " " bitfld.long 0x0 6. " HPC ,Hot-Plug Capable (CS)" "0,1" hexmask.long.byte 0x0 7.--14. 1. " SPLV ,Slot Power Limit Value (CS)" textline " " bitfld.long 0x0 15.--16. " SPLS ,Slot Power Limit Scale (CS)" "0,1,2,3" bitfld.long 0x0 17. " EIP ,Electromechanical Interlock Present (CS)" "0,1" textline " " bitfld.long 0x0 18. " NCCS ,No Command Complete Support (CS)" "0,1" hexmask.long.word 0x0 19.--31. 1. " PSN ,Physical Slot Number (CS)" group.byte 0x88++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x0 0. " ABP_EN ,Attention Button Pressed Enable" "0,1" bitfld.long 0x0 1. " PFD_EN ,Power Fault Detected Enable" "0,1" textline " " bitfld.long 0x0 2. " MRLSC_EN ,MRL Sensor Changed Enable" "0,1" bitfld.long 0x0 3. " PDC_EN ,Presence Detect Changed Enable" "0,1" textline " " bitfld.long 0x0 4. " CCI_EN ,Command Completed Interrupt Enable" "0,1" bitfld.long 0x0 5. " HPI_EN ,Hot-Plug Interrupt Enable" "0,1" textline " " bitfld.long 0x0 6.--7. " AIC ,Attention Indicator Control" "0,1,2,3" bitfld.long 0x0 8.--9. " PIC ,Power Indicator Control" "0,1,2,3" textline " " bitfld.long 0x0 10. " PCC ,Power Controller Control" "0,1" bitfld.long 0x0 11. " EIC ,Electromechanical Interlock Control" "0,1" textline " " bitfld.long 0x0 12. " DSC_EN ,Data Link Layer State Changed Enable" "0,1" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " ABP ,Attention Button Pressed" "0,1" bitfld.long 0x0 17. " PFD ,Power Fault Detected" "0,1" textline " " bitfld.long 0x0 18. " MRCSC ,MRL Sensor Changed" "0,1" bitfld.long 0x0 19. " PDC ,Presence Detect Changed" "0,1" textline " " bitfld.long 0x0 20. " CC ,Command Completed" "0,1" bitfld.long 0x0 21. " MRLSS ,MRL Sensor State" "0,1" textline " " bitfld.long 0x0 22. " PDS ,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" bitfld.long 0x0 23. " EIS ,Electromechanical Interlock Status" "0,1" textline " " bitfld.long 0x0 24. " DSC ,Data Link Layer State Changed" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_ROOT_CAC,Root Control and Capability Register" bitfld.long 0x0 0. " SECE_EN ,System Error on Correctable Error Enable" "0,1" bitfld.long 0x0 1. " SENE_EN ,System Error on Non-fatal Error Enable" "0,1" textline " " bitfld.long 0x0 2. " SEFE_EN ,System Error on Fatal Error Enable" "0,1" bitfld.long 0x0 3. " PMEI_EN ,PME Interrupt Enable" "0,1" textline " " bitfld.long 0x0 4. " CRSSV_EN ,CRS Software Visibility Enable" "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " CRSSV ,CRS Software Visibility" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_ROOT_STS,Root Status Register" hexmask.long.word 0x0 0.--15. 1. " PME_RID ,PME Requester ID" bitfld.long 0x0 16. " PME_STS ,PME Status (Sticky bit)" "0,1" textline " " bitfld.long 0x0 17. " PME_PND ,PME Pending" "0,1" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_RNG_SUPPORTED ,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS_SUPPORTED ,Completion Timeout Disable Supported" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOR_SP ,AtomicOp Routing Supported" "0,1" textline " " bitfld.long 0x0 7. " AOC32_SP ,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x0 8. " AOC64_SP ,64-bit AtomicOp Completer Supported" "0,1" textline " " bitfld.long 0x0 9. " CASC128_SP ,128-bit CAS Completer Supported" "0,1" bitfld.long 0x0 10. " NOROPR ,No RO-enabled PR-PR Passing" "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " TPHC_SP ,TPH Completer Supported" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_VALUE ,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS ,Completion Timeout Disable" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOP_REQ_EN ,AtomicOp Requester Enable" "0,1" textline " " bitfld.long 0x0 7. " AOP_EG_BLK ,AtomicOp Egress Blocking" "0,1" bitfld.long 0x0 8. " IDO_REQ_EN ,IDO Request Enable" "0,1" textline " " bitfld.long 0x0 9. " IDO_CPL_EN ,IDO Completion Enable" "0,1" bitfld.long 0x0 10. " LTR_EN ,LTR Mechanism Enable" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13.--14. " OBFF_EN ,OBFF Enable" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long.byte 0x0 1.--7. 1. " SP_LS_VEC ,Supported Link Speeds Vector" textline " " bitfld.long 0x0 8. " CROSSLINK_SP ,Crosslink Supported" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x0 0.--3. " TRGT_LINK_SPEED ,Target Link Speed Read 0x1: 2.5 GT/s (Gen1) Read 0x2: 5 GT/s (Gen2) Read 0x3: 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENTR_COMPL ,Enter Compliance" "0,1" textline " " bitfld.long 0x0 5. " HW_AUTO_SP_DIS ,Hardware Autonomous Speed Disable" "0,1" bitfld.long 0x0 6. " SEL_DEEMP ,Selectable De-emphasis (CS)" "0,1" textline " " bitfld.long 0x0 7.--9. " TX_MARGIN ,Transmit Margin" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. " ENT_MOD_COMPL ,Enter Modified Compliance" "0,1" textline " " bitfld.long 0x0 11. " COMPL_SOS ,Compliance SOS" "0,1" bitfld.long 0x0 12.--15. " COMPL_PRST_DEEPH ,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DEEMPH_LEVEL ,Current De-emphasis Level" "0,1" bitfld.long 0x0 17. " EQ_COMPLETE ,Equalization Complete, Gen3 Only" "0,1" textline " " bitfld.long 0x0 18. " EQ_PH1 ,Equalization Ph1 Success, Gen3 Only" "0,1" bitfld.long 0x0 19. " EQ_PH2 ,Equalization Ph2 Success, Gen3 Only" "0,1" textline " " bitfld.long 0x0 20. " EQ_PH3 ,Equalization Ph3 Success, Gen3 Only" "0,1" bitfld.long 0x0 21. " LINK_EQ_REQ ,Link Equilization Request" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS2_RC_CFG_DBICS" base ad:0x51800000 width 46. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x0 0.--15. 1. " VENDORID ,Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " DEVICEID ,Device ID (CS)" group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x0 0. " IO_SPACE_EN ,IO Space Enable (ISE)" "0,1" bitfld.long 0x0 1. " MEM_SPACE_EN ,Memory Space Enable (MSE)" "0,1" textline " " bitfld.long 0x0 2. " BUSMASTER_EN ,Bus Master Enable (BME)" "0,1" bitfld.long 0x0 3. " SPEC_CYCLE_EN ,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 4. " MEMWR_INVA ,Not Applicable for PCI Express; Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 5. " VGA_SNOOP ,Not Applicable forPCI Express; Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 6. " PARITYERRRESP ,Parity Error Response" "0,1" bitfld.long 0x0 7. " IDSEL_CTRL ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 8. " SERR_EN ,SERR Enable" "0,1" bitfld.long 0x0 9. " FAST_BBEN ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 10. " INTX_ASSER_DIS ,INTx Assertion Disable" "0,1" hexmask.long.byte 0x0 11.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " INTX_STATUS ,INTx Status" "0,1" bitfld.long 0x0 20. " CAP_LIST ,Capabilities List Hardwired to 1" "0,1" textline " " bitfld.long 0x0 21. " C66MHZ_CAP ,66MHz Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 23. " FAST_B2B ,Back to Back Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 24. " MASTERDATA_PARERR ,Master Data Parity Error" "0,1" textline " " bitfld.long 0x0 25.--26. " DEVSEL_TIME ,DevSel Timing, Harsdwired to 0 for PCIExpress" "0,1,2,3" bitfld.long 0x0 27. " SIGNAL_TRGTABORT ,Signaled Target Abort" "0,1" textline " " bitfld.long 0x0 28. " RCVD_TRGTABORT ,Received Target Abort" "0,1" bitfld.long 0x0 29. " RCVD_MASTERABORT ,Received Master Abort" "0,1" textline " " bitfld.long 0x0 30. " SIGNAL_SYSERR ,Signaled System Error" "0,1" bitfld.long 0x0 31. " DETECT_PARERR ,Detected Parity Error" "0,1" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x0 0.--7. 1. " REVID ,Revision ID (CS)" hexmask.long.byte 0x0 8.--15. 1. " PROG_IF_CODE ,Programming Interface Code (CS)" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBCLS_CD ,Sub Class Code (CS)" hexmask.long.byte 0x0 24.--31. 1. " BASE_CLS_CD ,Base Class Code (CS)" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_BIST_HEAD_LAT_CACH,BIST, Header Type, Latency Timer, Cache Line Size" hexmask.long.byte 0x0 0.--7. 1. " CACH_LN_SZE ,Cache Line Size, No impact on write, write is allowed only for legacy purpose" hexmask.long.byte 0x0 8.--15. 1. " MSTR_LAT_TIM ,Master Latency Timer, Not Applicable for PCIe hence hardwired to 0" textline " " hexmask.long.byte 0x0 16.--22. 1. " HEAD_TYP ,Header Type" bitfld.long 0x0 23. " MFD ,MultiFunction Device" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " BIST ,BIST" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS)" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LS Bit of I/O addressRead 0x0 = 32 bit enum=_32BIT . Read 0x2 = 64 bit enum=_64BIT ." "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask.NOTE: The RO and RW division between bits 19 and 20 is based on the assumption that BAR mask is 20 bits (1MB)." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask.NOTE: The RO and RW division between bits 19 and 20 is based on the assumption that BAR mask is 20 bits (1MB)." group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_BAR1,Base Address Register 1 If BAR0.AS = 64-bit: upper half of BAR0 base address If BAR0.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS)" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O addressRead 0x0 = 32 bit enum=_32BIT . Read 0x2 = 64 bit enum=_64BIT ." "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask.NOTE: The RO and RW division between bits 19 and 20 is based on the assumption that BAR mask is 20 bits (1MB)." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask.NOTE: The RO and RW division between bits 19 and 20 is based on the assumption that BAR mask is 20 bits (1MB)." group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_BUS_NUM_REG,Bus Number Registers" hexmask.long.byte 0x0 0.--7. 1. " PRIM_BUS_NUM ,Primary Bus Number" hexmask.long.byte 0x0 8.--15. 1. " SEC_BUS_NUM ,Secondary Bus Number" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBORD_BUS_NUM ,Subordinate Bus Number" hexmask.long.byte 0x0 24.--31. 1. " SEC_LAT_TIMER ,Secondary Latency Timer, Not Applicable for PCI Express hence hardwired to 0" group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_IOBASE_LIMIT_SEC_STATUS,IO Base,Limit and Secondary Status Register" bitfld.long 0x0 0. " IODECODE_32_0 ,32 or 16 Bit IO Space (CS)" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--7. " IO_SPACE_BASE ,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " IODECODE_32 ,32 or 16 Bit IO Space" "0,1" textline " " bitfld.long 0x0 9.--11. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--15. " IO_SPACE_LIMIT ,IO_Space_Limit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--20. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 21. " C66MHZ_CAPA ,66MHz Capable, Not Applicable for PCI Express hence hardwired to 0" "0,1" textline " " bitfld.long 0x0 22. " RESERVED ," "0,1" bitfld.long 0x0 23. " FAST_B2B_CAP ,Fast Back to Back Capable, Not Applicable for PCI Express hence hardwired to 0" "0,1" textline " " bitfld.long 0x0 24. " MSTR_DATA_PRTY_ERR ,Mastered Data Parity Error" "0,1" bitfld.long 0x0 25.--26. " DEVSEL_TIMING ,DEVSEL Timing, Not Applicable for PCI Express hence hardwired to 0" "0,1,2,3" textline " " bitfld.long 0x0 27. " SGNLD_TRGT_ABORT ,Signaled Target Error" "0,1" bitfld.long 0x0 28. " RCVD_TRGT_ABORT ,Received Target Error" "0,1" textline " " bitfld.long 0x0 29. " RCVD_MSTR_ABORT ,Received Master Abort" "0,1" bitfld.long 0x0 30. " RCVD_SYS_ERR ,Received System Error" "0,1" textline " " bitfld.long 0x0 31. " DET_PAR_ERR ,Detected Parity Error" "0,1" group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_MEM_BASE_LIMIT,Memory Base and Limit Register" bitfld.long 0x0 0.--3. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 4.--15. 1. " MEM_BASE_ADDR ,Memory Base Address" textline " " bitfld.long 0x0 16.--19. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " MEM_LIMIT_ADDR ,Memory Limit Address" group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_PREF_MEM_BASE_LIMIT,Prefetchable Memory Base and Limit Register" bitfld.long 0x0 0. " MEMDECODE_64_0 ,64-Bit Memory Addressing" "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x0 4.--15. 1. " UPPPREF_MEM_ADDR ,Upper 12 bits of 32-bit Prefetchable Memory start Address" bitfld.long 0x0 16. " MEMDECODE_64 ,64-Bit Memory Addressing" "0,1" textline " " bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 20.--31. 1. " PREF_MEM_ADDR ,Upper 12 bits of 32-bit Prefetchable Memory End Address" group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_BASEADDR,Upper 32 Bit Prefetachable Base Address Register" hexmask.long 0x0 0.--31. 1. " ADDRUPP ,Upper 32 Bits of Base Address of Prefetachable Memory Space, Used only if 64 Bit Prefetachable Addresing is enabled" group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_UPPER_32BIT_PREF_LIMITADDR,Upper 32 Bit Prefetachable Limit Address Register" hexmask.long 0x0 0.--31. 1. " ADDRUPP_LIMIT ,Upper 32 Bits of Limit Address of Prefetachable Memory Space, Used only if 64 Bit Prefetachable Addresing is enabled" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_IO_BASE_LIMIT,IO Base and Limit Register" hexmask.long.word 0x0 0.--15. 1. " UPP16_IOBASE ,Upper 16 IO Base Address" hexmask.long.word 0x0 16.--31. 1. " UPP16_IOLIMIT ,Upper 16 IO Limit Address" group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x0 0.--7. 1. " CAPTR ,First Capability Pointer (CS)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" bitfld.long 0x0 0. " EXP_ROM_EN ,Expansion ROM Enable" "0,1" hexmask.long.word 0x0 1.--10. 1. " RESERVED ," textline " " bitfld.long 0x0 11.--15. " EXROM_ADDRESS_RO ,Expansion ROM address, masked." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--31. 1. " EXROM_ADDRESS ,Expansion ROM address, unmasked (ie programmable)" group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_BRIDGE_INT,Bridge Control and Int Pin and line" hexmask.long.byte 0x0 0.--7. 1. " INT_LIN ,Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. " INT_PIN ,Interrupt Pin (CS)" textline " " bitfld.long 0x0 16. " PERR_RESP_EN ,Parity Error Response Enable" "0,1" bitfld.long 0x0 17. " SERR_EN ,SERR Enable" "0,1" textline " " bitfld.long 0x0 18. " ISA_EN ,ISA Enable" "0,1" bitfld.long 0x0 19. " VGA_EN ,VGA Enable" "0,1" textline " " bitfld.long 0x0 20. " VGA_16B_DEC ,VGA 16-Bit Decode" "0,1" bitfld.long 0x0 21. " MST_ABT_MOD ,Master Abort Mode" "0,1" textline " " bitfld.long 0x0 22. " SEC_BUS_RST ,Secondary Bus Reset (initiate hot reset)" "0,1" bitfld.long 0x0 23. " FAST_B2B_EN ,Fast Back-to-Back Transactions Enable" "0,1" textline " " bitfld.long 0x0 24. " PRI_DT ,Primary Discard Timer" "0,1" bitfld.long 0x0 25. " SEC_DT ,Secondary Discard Timer" "0,1" textline " " bitfld.long 0x0 26. " DT_STS ,Discard Timer Status" "0,1" bitfld.long 0x0 27. " DT_SERR_EN ,Discard Timer SERR Enable Status" "0,1" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x70++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_PCIE_CAP,PCI Express Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PCIE_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--19. " PCIE_VER ,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " DEV_TYPE ,Device/Port Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SLOT ,Slot Implemented (CS)" "0,1" bitfld.long 0x0 25.--29. " IM_NUM ,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x74++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x0 0.--2. " MAX_PAYLOAD_SIZE ,Maximum Payload Size (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " PHANTOMFUNC ,Phantom Function Support, not SUPPORTED (CS)" "0,1,2,3" textline " " bitfld.long 0x0 5. " EXTTAGFIELD_SUPPORT ,Extended Tag Field Support (CS)" "0,1" bitfld.long 0x0 6.--8. " DEFAULT_EP_L0S_ACCPT_LATENCY ,Endpoint L0s Acceptable Latency; Must be 0 for RC." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " DEFAULT_EP_L1_ACCPT_LATENCY ,Endpoint L1 Acceptable Latency; Must be 0 for RC." "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " UNDEFINED ,Undefined from PCIe 1.1 onwards" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ROLEBASED_ERRRPT ,Role Based Error Reporting (CS)" "0,1" bitfld.long 0x0 16.--17. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 18.--25. 1. " CAPT_SLOW_PWRLIMIT_VALUE ,Captured Slow Power Limit Value, for Upstream Port Only (CS)" bitfld.long 0x0 26.--27. " CAPT_SLOW_PWRLIMIT_SCALE ,Captured Slow Power Scale Value, for Upstream Port Only (CS)" "0,1,2,3" textline " " bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x78++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_DEV_CAS,PCIE Device Control and Status" bitfld.long 0x0 0. " COR_RE ,Correctable Error Reporting Enable" "0,1" bitfld.long 0x0 1. " NFT_RE ,Non-Fatal Error Reporting Enable" "0,1" textline " " bitfld.long 0x0 2. " FT_RE ,Fatal Error Reporting Enable" "0,1" bitfld.long 0x0 3. " UR_RE ,Unsupported Request Reporting Enable" "0,1" textline " " bitfld.long 0x0 4. " EN_RO ,Enable Relaxed Ordering" "0,1" bitfld.long 0x0 5.--7. " MPS ,Max_Payload_Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " EXTAG_EN ,Extended Tag Field Enable" "0,1" bitfld.long 0x0 9. " PHFUN_EN ,Phantom Function Enable" "0,1" textline " " bitfld.long 0x0 10. " AUXPM_EN ,AUX Power PM Enable (Sticky bit)" "0,1" bitfld.long 0x0 11. " NOSNP_EN ,Enable No Snoop" "0,1" textline " " bitfld.long 0x0 12.--14. " MRRS ,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " INIT_FLR ,Reserved" "0,1" textline " " bitfld.long 0x0 16. " COR_DET ,Correctable Error Detected" "0,1" bitfld.long 0x0 17. " NFT_DET ,Non-Fatal Error Detected" "0,1" textline " " bitfld.long 0x0 18. " FT_DET ,Fatal Error Detected" "0,1" bitfld.long 0x0 19. " UR_DET ,Unsupported Request Detected" "0,1" textline " " bitfld.long 0x0 20. " AUXP_DET ,Aux Power Detected" "0,1" bitfld.long 0x0 21. " TRANS_PEND ,Transaction Pending" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x7C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_LNK_CAP,PCIE Link Capabilities" bitfld.long 0x0 0.--3. " MAX_LINK_SPEEDS ,Supported Max Link Speed (CS) Read 0x1: 2.5 GT/s (Gen1) Read 0x2: 5 GT/s (Gen2) Read 0x3: 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--9. " MAX_LINK_WIDTH ,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 10.--11. " AS_LINK_PM_SUPPORT ,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0 12.--14. " L0S_EXIT_LAT ,L0s Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " L1_EXIT_LAT ,L1 Exit Latency (CS) Compare CS2" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18. " CLK_PWR_MGMT ,Clock Power Management; Hardwired to 0 for DS port (RC); (CS)" "0,1" textline " " bitfld.long 0x0 19. " UNSUP ,Unsupported, Surprise Down Error Reporting Capable, Hardwired to 0" "0,1" bitfld.long 0x0 20. " DLL_ACTRPT_CAP ,Data Link Layer Active Reporting Capable" "0,1" textline " " bitfld.long 0x0 21. " LNK_BW_not_CAP ,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0 22. " ASPM_OPT_COMP ,ASPM Optionality Compliance (CS)" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" hexmask.long.byte 0x0 24.--31. 1. " PORT_NUM ,Port Number (CS)" group.byte 0x80++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x0 0.--1. " ASPM_CTRL ,Active State Link PM Control 0x0: DISABLED 0x1: L0S_ENABLED 0x2: L1_ENABLED 0x3: L0S_AND_L1_ENABLED" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " RCB ,Read Completion Boundary (CS)" "0,1" bitfld.long 0x0 4. " LINK_DIS ,Link Disable" "0,1" textline " " bitfld.long 0x0 5. " RETRAIN_LINK ,Retrain Link" "0,1" bitfld.long 0x0 6. " COM_CLK_CFG ,Common Clock Configuration" "0,1" textline " " bitfld.long 0x0 7. " EXT_SYN ,Extended Synch" "0,1" bitfld.long 0x0 8. " EN_CPM ,Enable Clock Power Management" "0,1" textline " " bitfld.long 0x0 9. " HAWD ,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x0 10. " LBMIE ,Link Bandwidth Management Interrupt Enable" "0,1" textline " " bitfld.long 0x0 11. " LABIE ,Link Autonomous Bandwidth Interrupt Enable" "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " LINK_SPEED ,Link Speed; UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " NEG_LW ,Negotiated Link Width; UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 26. " UNDEF ,Undefined" "0,1" bitfld.long 0x0 27. " LINK_TRAIN ,LINK training" "0,1" textline " " bitfld.long 0x0 28. " SLOT_CLK_CONFIG ,Slot Clock Configuration (CS)" "0,1" bitfld.long 0x0 29. " DLL_ACT ,Data Link Layer Active" "0,1" textline " " bitfld.long 0x0 30. " LBW_STATUS ,Link Bandwidth Management Status" "0,1" bitfld.long 0x0 31. " LAB_STATUS ,Link Autonomous Bandwidth Status" "0,1" group.byte 0x84++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_SLOT_CAP,Slot Capabilities Register" bitfld.long 0x0 0. " ABP ,Attention Button Present (CS)" "0,1" bitfld.long 0x0 1. " PCP ,Power Controller Present (CS)" "0,1" textline " " bitfld.long 0x0 2. " MRLSP ,MRL Sensor Present (CS)" "0,1" bitfld.long 0x0 3. " AIP ,Attention Indicator Present (CS)" "0,1" textline " " bitfld.long 0x0 4. " PIP ,Power Indicator Present (CS)" "0,1" bitfld.long 0x0 5. " HPS ,Hot-Plug Surprise (CS)" "0,1" textline " " bitfld.long 0x0 6. " HPC ,Hot-Plug Capable (CS)" "0,1" hexmask.long.byte 0x0 7.--14. 1. " SPLV ,Slot Power Limit Value (CS)" textline " " bitfld.long 0x0 15.--16. " SPLS ,Slot Power Limit Scale (CS)" "0,1,2,3" bitfld.long 0x0 17. " EIP ,Electromechanical Interlock Present (CS)" "0,1" textline " " bitfld.long 0x0 18. " NCCS ,No Command Complete Support (CS)" "0,1" hexmask.long.word 0x0 19.--31. 1. " PSN ,Physical Slot Number (CS)" group.byte 0x88++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_SLOT_CAS,Slot Control and Status Register" bitfld.long 0x0 0. " ABP_EN ,Attention Button Pressed Enable" "0,1" bitfld.long 0x0 1. " PFD_EN ,Power Fault Detected Enable" "0,1" textline " " bitfld.long 0x0 2. " MRLSC_EN ,MRL Sensor Changed Enable" "0,1" bitfld.long 0x0 3. " PDC_EN ,Presence Detect Changed Enable" "0,1" textline " " bitfld.long 0x0 4. " CCI_EN ,Command Completed Interrupt Enable" "0,1" bitfld.long 0x0 5. " HPI_EN ,Hot-Plug Interrupt Enable" "0,1" textline " " bitfld.long 0x0 6.--7. " AIC ,Attention Indicator Control" "0,1,2,3" bitfld.long 0x0 8.--9. " PIC ,Power Indicator Control" "0,1,2,3" textline " " bitfld.long 0x0 10. " PCC ,Power Controller Control" "0,1" bitfld.long 0x0 11. " EIC ,Electromechanical Interlock Control" "0,1" textline " " bitfld.long 0x0 12. " DSC_EN ,Data Link Layer State Changed Enable" "0,1" bitfld.long 0x0 13.--15. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16. " ABP ,Attention Button Pressed" "0,1" bitfld.long 0x0 17. " PFD ,Power Fault Detected" "0,1" textline " " bitfld.long 0x0 18. " MRCSC ,MRL Sensor Changed" "0,1" bitfld.long 0x0 19. " PDC ,Presence Detect Changed" "0,1" textline " " bitfld.long 0x0 20. " CC ,Command Completed" "0,1" bitfld.long 0x0 21. " MRLSS ,MRL Sensor State" "0,1" textline " " bitfld.long 0x0 22. " PDS ,Presence Detect State NO PRESENCE DETECTION IMPLEMENTED: TIED TO 1" "0,1" bitfld.long 0x0 23. " EIS ,Electromechanical Interlock Status" "0,1" textline " " bitfld.long 0x0 24. " DSC ,Data Link Layer State Changed" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_ROOT_CAC,Root Control and Capability Register" bitfld.long 0x0 0. " SECE_EN ,System Error on Correctable Error Enable" "0,1" bitfld.long 0x0 1. " SENE_EN ,System Error on Non-fatal Error Enable" "0,1" textline " " bitfld.long 0x0 2. " SEFE_EN ,System Error on Fatal Error Enable" "0,1" bitfld.long 0x0 3. " PMEI_EN ,PME Interrupt Enable" "0,1" textline " " bitfld.long 0x0 4. " CRSSV_EN ,CRS Software Visibility Enable" "0,1" hexmask.long.word 0x0 5.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " CRSSV ,CRS Software Visibility" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_ROOT_STS,Root Status Register" hexmask.long.word 0x0 0.--15. 1. " PME_RID ,PME Requester ID" bitfld.long 0x0 16. " PME_STS ,PME Status (Sticky bit)" "0,1" textline " " bitfld.long 0x0 17. " PME_PND ,PME Pending" "0,1" hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x94++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_RNG_SUPPORTED ,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS_SUPPORTED ,Completion Timeout Disable Supported" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOR_SP ,AtomicOp Routing Supported" "0,1" textline " " bitfld.long 0x0 7. " AOC32_SP ,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x0 8. " AOC64_SP ,64-bit AtomicOp Completer Supported" "0,1" textline " " bitfld.long 0x0 9. " CASC128_SP ,128-bit CAS Completer Supported" "0,1" bitfld.long 0x0 10. " NOROPR ,No RO-enabled PR-PR Passing" "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " TPHC_SP ,TPH Completer Supported" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_VALUE ,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS ,Completion Timeout Disable" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOP_REQ_EN ,AtomicOp Requester Enable" "0,1" textline " " bitfld.long 0x0 7. " AOP_EG_BLK ,AtomicOp Egress Blocking" "0,1" bitfld.long 0x0 8. " IDO_REQ_EN ,IDO Request Enable" "0,1" textline " " bitfld.long 0x0 9. " IDO_CPL_EN ,IDO Completion Enable" "0,1" bitfld.long 0x0 10. " LTR_EN ,LTR Mechanism Enable" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13.--14. " OBFF_EN ,OBFF Enable" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long.byte 0x0 1.--7. 1. " SP_LS_VEC ,Supported Link Speeds Vector" textline " " bitfld.long 0x0 8. " CROSSLINK_SP ,Crosslink Supported" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PCIECTRL_RC_DBICS_LNK_CAS_2,Link Control and Status 2 Register (Sticky)" bitfld.long 0x0 0.--3. " TRGT_LINK_SPEED ,Target Link Speed Read 0x1: 2.5 GT/s (Gen1) Read 0x2: 5 GT/s (Gen2) Read 0x3: 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENTR_COMPL ,Enter Compliance" "0,1" textline " " bitfld.long 0x0 5. " HW_AUTO_SP_DIS ,Hardware Autonomous Speed Disable" "0,1" bitfld.long 0x0 6. " SEL_DEEMP ,Selectable De-emphasis (CS)" "0,1" textline " " bitfld.long 0x0 7.--9. " TX_MARGIN ,Transmit Margin" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. " ENT_MOD_COMPL ,Enter Modified Compliance" "0,1" textline " " bitfld.long 0x0 11. " COMPL_SOS ,Compliance SOS" "0,1" bitfld.long 0x0 12.--15. " COMPL_PRST_DEEPH ,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DEEMPH_LEVEL ,Current De-emphasis Level" "0,1" bitfld.long 0x0 17. " EQ_COMPLETE ,Equalization Complete, Gen3 Only" "0,1" textline " " bitfld.long 0x0 18. " EQ_PH1 ,Equalization Ph1 Success, Gen3 Only" "0,1" bitfld.long 0x0 19. " EQ_PH2 ,Equalization Ph2 Success, Gen3 Only" "0,1" textline " " bitfld.long 0x0 20. " EQ_PH3 ,Equalization Ph3 Success, Gen3 Only" "0,1" bitfld.long 0x0 21. " LINK_EQ_REQ ,Link Equilization Request" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS1_EP_CFG_DBICS" base ad:0x51000000 width 43. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x0 0.--15. 1. " VENDORID ,Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " DEVICEID ,Device ID (CS)" group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x0 0. " IO_SPACE_EN ,IO Space Enable" "0,1" bitfld.long 0x0 1. " MEM_SPACE_EN ,Memory Space Enable" "0,1" textline " " bitfld.long 0x0 2. " BUSMASTER_EN ,Bus Master Enable" "0,1" bitfld.long 0x0 3. " SPEC_CYCLE_EN ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 4. " MEMWR_INVA ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 5. " VGA_SNOOP ,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 6. " PARITYERRRESP ,Parity Error Response" "0,1" bitfld.long 0x0 7. " IDSEL_CTRL ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 8. " SERR_EN ,SERR Enable" "0,1" bitfld.long 0x0 9. " FAST_BBEN ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 10. " INTX_ASSER_DIS ,INTx Assertion Disable" "0,1" hexmask.long.byte 0x0 11.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " INTX_STATUS ,INTx Status" "0,1" bitfld.long 0x0 20. " CAP_LIST ,Capabilities List Hardwired to 1" "0,1" textline " " bitfld.long 0x0 21. " C66MHZ_CAP ,66MHz Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 23. " FAST_B2B ,Back to Back Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 24. " MASTERDATA_PARERR ,Master Data Parity Error" "0,1" textline " " bitfld.long 0x0 25.--26. " DEVSEL_TIME ,DevSel Timing, Harsdwired to 0 for PCIExpress" "0,1,2,3" bitfld.long 0x0 27. " SIGNAL_TRGTABORT ,Signaled Target Abort" "0,1" textline " " bitfld.long 0x0 28. " RCVD_TRGTABORT ,Received Target Abort" "0,1" bitfld.long 0x0 29. " RCVD_MASTERABORT ,Received Master Abort" "0,1" textline " " bitfld.long 0x0 30. " SIGNAL_SYSERR ,Signaled System Error" "0,1" bitfld.long 0x0 31. " DETECT_PARERR ,Detected Parity Error" "0,1" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x0 0.--7. 1. " REVID ,Revision ID (CS)" hexmask.long.byte 0x0 8.--15. 1. " PROG_IF_CODE ,Programming Interface Code (CS)" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBCLS_CD ,Sub Class Code (CS)" hexmask.long.byte 0x0 24.--31. 1. " BASE_CLS_CD ,Base Class Code (CS)" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BIST_HEAD_LAT_CACH,BIST, Header Type, Latency Timer, Cache Line Size" hexmask.long.byte 0x0 0.--7. 1. " CACH_LN_SZE ,Cache Line Size, No impact on write, write is allowed only for legacy purpose" hexmask.long.byte 0x0 8.--15. 1. " MSTR_LAT_TIM ,Master Latency Timer, Not Applicable for PCIe hence hardwired to 0" textline " " hexmask.long.byte 0x0 16.--22. 1. " HEAD_TYP ,Header Type 0x0 = EP header 0x1 = RC header" bitfld.long 0x0 23. " MFD ,MultiFunction Device" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " BIST ,BIST" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask." group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR1,Base Address Register 1 If BAR0.AS = 64-bit: upper half of BAR0 base address If BAR0.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask." group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR3,Base Address Register 3 If BAR2.AS = 64-bit: upper half of BAR2 base address If BAR2.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.byte 0x0 4.--11. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.tbyte 0x0 12.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask." group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR5,Base Address Register 5 If BAR4.AS = 64-bit: upper half of BAR4 base address If BAR4.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_CARDBUS_CIS_POINTER,PCIECTRL_EP_DBICS_CARDBUS_CIS_POINTER" hexmask.long 0x0 0.--31. 1. " CARDBUS_CIS_PTR_N ,Cardbus CIS pointer (CS)" group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_SUBID_SUBVENDORID,PCIECTRL_EP_DBICS_SUBID_SUBVENDORID" hexmask.long.word 0x0 0.--15. 1. " SUBSYS_VENDOR_ID_N ,Subsystem Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " SUBSYS_DEV_ID_N ,Subsystem ID (CS)" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" bitfld.long 0x0 0. " EXROM_EN ,Expansion ROM Enable" "0,1" hexmask.long.word 0x0 1.--10. 1. " RESERVED ," textline " " bitfld.long 0x0 11.--15. " EXROM_ADDRESS_RO ,Expansion ROM address, masked." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--31. 1. " EXROM_ADDRESS ,Expansion ROM address, unmasked (ie programmable)" group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x0 0.--7. 1. " CAPTR ,First Capability Pointer (CS)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_INTERRUPT,Int Pin and line" hexmask.long.byte 0x0 0.--7. 1. " INT_LIN ,Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. " INT_PIN ,Interrupt Pin (CS)" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_PM_CAP,Power Management Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PM_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--18. " PMC_VER ,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " PME_CLK ,PME Clock, hardwired to 0 (CS)" "0,1" textline " " bitfld.long 0x0 20. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 21. " DSI ,Device Specific Initialization (CS)" "0,1" textline " " bitfld.long 0x0 22.--24. " AUX_CUR ,AUX Current (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 25. " D1_SP ,D1 Support (CS)" "0,1" textline " " bitfld.long 0x0 26. " D2_SP ,D2 Support (CS)" "0,1" bitfld.long 0x0 27.--31. " PME_SP ,PME Support (CS); Power states from which PME messages can be sent (active hi, one bit per state) Bit 0: from D0 Bit 1: from D1 Bit 2: from D2 Bit 3: from D3hot Bit 4: from D3cold (if Vaux present)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_PM_CSR,Power Management Control and Status Register" bitfld.long 0x0 0.--1. " PM_STATE ,Power Management Control and Status Register" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 3. " NSR ,No Soft Reset (CS)" "0,1" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PME_EN ,PME Enable (Sticky bit)" "0,1" bitfld.long 0x0 9.--12. " DATA_SEL ,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 13.--14. " DATA_SCALE ,Data Scale (not supported)" "0,1,2,3" bitfld.long 0x0 15. " PME_STATUS ,PME Status (Sticky bit)" "0,1" textline " " bitfld.long 0x0 16.--21. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " B2B3_SP ,B2/B3 Support, hardwired to 0" "0,1" textline " " bitfld.long 0x0 23. " BP_CCE ,Bus Power/Clock Control Enable, hardwired to 0" "0,1" hexmask.long.byte 0x0 24.--31. 1. " DATA1 ,Data register for additional information (not supported)" group.byte 0x50++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_MSI_CAP,Message Signaled Interrupt Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,MSI Capability ID Read 0x05 MSI" hexmask.long.byte 0x0 8.--15. 1. " MSI_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16. " MSI_EN ,MSI Enable" "0,1" bitfld.long 0x0 17.--19. " MMC ,Multiple Message Capable (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20.--22. " MME ,Multiple Message Enable" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " MSI_64_EN ,64-bit Address Capable (CS)" "0,1" textline " " bitfld.long 0x0 24. " PVM_EN ,MSI Per Vector Masking (PVM) supported" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_MSI_ADD_L32,PCIe memory space address of MSI write TLP request, lower 32 bits." bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " ADDR ,Lower 32-bit address (DWORD aligned)" group.byte 0x58++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_MSI_ADD_U32,PCIe memory space address of MSI write TLP request, upper 32 bits (used if MSI_64_EN = 1)." hexmask.long 0x0 0.--31. 1. " ADDR ,Upper 32-bit address" group.byte 0x5C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_MSI_DATA,Data of MSI write TLP request (modified for multiple vectors)" hexmask.long.word 0x0 0.--15. 1. " DATA ,MSI data" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x70++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_PCIE_CAP,PCIE cap structure" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PCIE_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--19. " PCIE_VER ,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " DEV_TYPE ,Device/Port Type Value depends on assigned type 0x0 = PCIe endpoint 0x1 = Legacy PCIe endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SLOT ,Slot Implemented Must be 0 for an endpoint" "0,1" bitfld.long 0x0 25.--29. " IM_NUM ,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 30.--31. " RESERVED ,Reserved" "0,1,2,3" group.byte 0x74++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x0 0.--2. " MAX_PAYLOAD_SIZE ,Maximum Payload Size (CS) Read 0x1 = 256 Byte" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " PHANTOMFUNC ,Phantom Function Support, not SUPPORTED (CS)" "0,1,2,3" textline " " bitfld.long 0x0 5. " EXTTAGFIELD_SUPPORT ,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" bitfld.long 0x0 6.--8. " DEFAULT_EP_L0S_ACCPT_LATENCY ,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " DEFAULT_EP_L1_ACCPT_LATENCY ,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " UNDEFINED ,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ROLEBASED_ERRRPT ,Role Based Error Reporting (CS)" "0,1" bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" textline " " hexmask.long.byte 0x0 18.--25. 1. " CAPT_SLOW_PWRLIMIT_VALUE ,Captured Slow Power Limit Value (CS)" bitfld.long 0x0 26.--27. " CAPT_SLOW_PWRLIMIT_SCALE ,Captured Slow Power Scale Value (CS)" "0,1,2,3" textline " " bitfld.long 0x0 28. " FLR_EN ,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x78++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_DEV_CAS,PCIE Device Control and Status" bitfld.long 0x0 0. " COR_RE ,Correctable Error Reporting Enable" "0,1" bitfld.long 0x0 1. " NFT_RE ,Non-Fatal Error Reporting Enable" "0,1" textline " " bitfld.long 0x0 2. " FT_RE ,Fatal Error Reporting Enable" "0,1" bitfld.long 0x0 3. " UR_RE ,Unsupported Request Reporting Enable" "0,1" textline " " bitfld.long 0x0 4. " EN_RO ,Enable Relaxed Ordering" "0,1" bitfld.long 0x0 5.--7. " MPS ,Max_Payload_Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " EXTAG_EN ,Extended Tag Field Enable" "0,1" bitfld.long 0x0 9. " PHFUN_EN ,Phantom Function Enable" "0,1" textline " " bitfld.long 0x0 10. " AUXPM_EN ,AUX Power PM Enable" "0,1" bitfld.long 0x0 11. " NOSNP_EN ,Enable No Snoop" "0,1" textline " " bitfld.long 0x0 12.--14. " MRRS ,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " INIT_FLR ,Reserved" "0,1" textline " " bitfld.long 0x0 16. " COR_DET ,Correctable Error Detected" "0,1" bitfld.long 0x0 17. " NFT_DET ,Non-Fatal Error Detected" "0,1" textline " " bitfld.long 0x0 18. " FT_DET ,Fatal Error Detected" "0,1" bitfld.long 0x0 19. " UR_DET ,Unsupported Request Detected" "0,1" textline " " bitfld.long 0x0 20. " AUXP_DET ,Aux Power Detected" "0,1" bitfld.long 0x0 21. " TRANS_PEND ,Transaction Pending" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x7C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_LNK_CAP,PCIE Link Capabilities" bitfld.long 0x0 0.--3. " MAX_LINK_SPEEDS ,Supported Max Link Speed (CS) 0x1(R) = 2.5 GT/s (Gen1) 0x2(R) = 5 GT/s (Gen2) 0x4(R) = 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--9. " MAX_LINK_WIDTH ,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 10.--11. " AS_LINK_PM_SUPPORT ,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0 12.--14. " L0S_EXIT_LAT ,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " L1_EXIT_LAT ,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18. " CLK_PWR_MGMT ,Clock Power Management (CS)" "0,1" textline " " bitfld.long 0x0 19. " UNSUP ,Unsupported, Surprise Down Error Reporting Capable, Hardwired to 0" "0,1" bitfld.long 0x0 20. " DLL_ACTRPT_CAP ,Data Link Layer Active Reporting Capable" "0,1" textline " " bitfld.long 0x0 21. " LNK_BW_not_CAP ,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0 22. " ASPM_OPT_COMP ,ASPM Optionality Compliance (CS)" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" hexmask.long.byte 0x0 24.--31. 1. " PORT_NUM ,Port Number (CS)" group.byte 0x80++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x0 0.--1. " ASPM_CTRL ,Active State Link PM Control 0x0: DISABLED 0x1: L0S_ENABLED 0x2: L1_ENABLED 0x3: L0S_AND_L1_ENABLED" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " RCB ,Read Completion Boundary (CS) 0x0 = 64 Byte 0x1 = 128 Byte" "0,1" bitfld.long 0x0 4. " LINK_DIS ,Link Disable" "0,1" textline " " bitfld.long 0x0 5. " RETRAIN_LINK ,Retrain Link" "0,1" bitfld.long 0x0 6. " COM_CLK_CFG ,Common Clock Configuration" "0,1" textline " " bitfld.long 0x0 7. " EXT_SYN ,Extended Synch" "0,1" bitfld.long 0x0 8. " EN_CPM ,Enable Clock Power Management" "0,1" textline " " bitfld.long 0x0 9. " HAWD ,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x0 10. " LBMIE ,Link Bandwidth Management Interrupt Enable" "0,1" textline " " bitfld.long 0x0 11. " LABIE ,Link Autonomous Bandwidth Interrupt Enable." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " LINK_SPEED ,Link Speed UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " NEG_LW ,Negotiated Link Width UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 26. " UNDEF ,Undefined" "0,1" bitfld.long 0x0 27. " LINK_TRAIN ,LINK training" "0,1" textline " " bitfld.long 0x0 28. " SLOT_CLK_CONFIG ,Slot Clock Configuration (CS)" "0,1" bitfld.long 0x0 29. " DLL_ACT ,Data Link Layer Active" "0,1" textline " " bitfld.long 0x0 30. " LBW_STATUS ,Link Bandwidth Management Status" "0,1" bitfld.long 0x0 31. " LAB_STATUS ,Link Autonomous Bandwidth Status" "0,1" group.byte 0x94++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_RNG_SUPPORTED ,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS_SUPPORTED ,Completion Timeout Disable Supported" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOR_SP ,AtomicOp Routing Supported" "0,1" textline " " bitfld.long 0x0 7. " AOC32_SP ,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x0 8. " AOC64_SP ,64-bit AtomicOp Completer Supported" "0,1" textline " " bitfld.long 0x0 9. " CASC128_SP ,128-bit CAS Completer Supported" "0,1" bitfld.long 0x0 10. " NOROPR ,No RO-enabled PR-PR Passing" "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " TPHC_SP ,TPH Completer Supported" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_VALUE ,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS ,Completion Timeout Disable" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOP_REQ_EN ,AtomicOp Requester Enable" "0,1" textline " " bitfld.long 0x0 7. " AOP_EG_BLK ,AtomicOp Egress Blocking" "0,1" bitfld.long 0x0 8. " IDO_REQ_EN ,IDO Request Enable" "0,1" textline " " bitfld.long 0x0 9. " IDO_CPL_EN ,IDO Completion Enable" "0,1" bitfld.long 0x0 10. " LTR_EN ,LTR Mechanism Enable" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13.--14. " OBFF_EN ,OBFF Enable" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long.byte 0x0 1.--7. 1. " SP_LS_VEC ,Supported Link Speeds Vector" textline " " bitfld.long 0x0 8. " CROSSLINK_SP ,Crosslink Supported" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0 0.--3. " TRGT_LINK_SPEED ,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENTR_COMPL ,Enter Compliance" "0,1" textline " " bitfld.long 0x0 5. " HW_AUTO_SP_DIS ,Hardware Autonomous Speed Disable" "0,1" bitfld.long 0x0 6. " SEL_DEEMP ,Selectable De-emphasize" "0,1" textline " " bitfld.long 0x0 7.--9. " TX_MARGIN ,Transmit Margin" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. " ENT_MOD_COMPL ,Enter Modified Compliance" "0,1" textline " " bitfld.long 0x0 11. " COMPL_SOS ,Compliance SOS" "0,1" bitfld.long 0x0 12.--15. " COMPL_PRST_DEEPH ,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DEEMPH_LEVEL ,Current De-emphasis Level" "0,1" bitfld.long 0x0 17. " EQ_COMPLETE ,Equalization Complete, Gen3 Only" "0,1" textline " " bitfld.long 0x0 18. " EQ_PH1 ,Equalization Ph1 Success, Gen3 Only" "0,1" bitfld.long 0x0 19. " EQ_PH2 ,Equalization Ph2 Success, Gen3 Only" "0,1" textline " " bitfld.long 0x0 20. " EQ_PH3 ,Equalization Ph3 Success, Gen3 Only" "0,1" bitfld.long 0x0 21. " LINK_EQ_REQ ,Link Equilization Request" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS2_EP_CFG_DBICS" base ad:0x51800000 width 43. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_DEVICE_VENDORID,Device and Vendor ID" hexmask.long.word 0x0 0.--15. 1. " VENDORID ,Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " DEVICEID ,Device ID (CS)" group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_STATUS_COMMAND_REGISTER,Status and Command registers" bitfld.long 0x0 0. " IO_SPACE_EN ,IO Space Enable" "0,1" bitfld.long 0x0 1. " MEM_SPACE_EN ,Memory Space Enable" "0,1" textline " " bitfld.long 0x0 2. " BUSMASTER_EN ,Bus Master Enable" "0,1" bitfld.long 0x0 3. " SPEC_CYCLE_EN ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 4. " MEMWR_INVA ,Not Applicable for PCI Express Bit hardwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 5. " VGA_SNOOP ,Not Applicable forPCI Express Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 6. " PARITYERRRESP ,Parity Error Response" "0,1" bitfld.long 0x0 7. " IDSEL_CTRL ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 8. " SERR_EN ,SERR Enable" "0,1" bitfld.long 0x0 9. " FAST_BBEN ,Bit hardwired to 0 for PCIExpress" "0,1" textline " " bitfld.long 0x0 10. " INTX_ASSER_DIS ,INTx Assertion Disable" "0,1" hexmask.long.byte 0x0 11.--18. 1. " RESERVED ," textline " " bitfld.long 0x0 19. " INTX_STATUS ,INTx Status" "0,1" bitfld.long 0x0 20. " CAP_LIST ,Capabilities List Hardwired to 1" "0,1" textline " " bitfld.long 0x0 21. " C66MHZ_CAP ,66MHz Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 22. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 23. " FAST_B2B ,Back to Back Capable, Harsdwired to 0 for PCIExpress" "0,1" bitfld.long 0x0 24. " MASTERDATA_PARERR ,Master Data Parity Error" "0,1" textline " " bitfld.long 0x0 25.--26. " DEVSEL_TIME ,DevSel Timing, Harsdwired to 0 for PCIExpress" "0,1,2,3" bitfld.long 0x0 27. " SIGNAL_TRGTABORT ,Signaled Target Abort" "0,1" textline " " bitfld.long 0x0 28. " RCVD_TRGTABORT ,Received Target Abort" "0,1" bitfld.long 0x0 29. " RCVD_MASTERABORT ,Received Master Abort" "0,1" textline " " bitfld.long 0x0 30. " SIGNAL_SYSERR ,Signaled System Error" "0,1" bitfld.long 0x0 31. " DETECT_PARERR ,Detected Parity Error" "0,1" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_CLASSCODE_REVISIONID,Class code and Revision ID" hexmask.long.byte 0x0 0.--7. 1. " REVID ,Revision ID (CS)" hexmask.long.byte 0x0 8.--15. 1. " PROG_IF_CODE ,Programming Interface Code (CS)" textline " " hexmask.long.byte 0x0 16.--23. 1. " SUBCLS_CD ,Sub Class Code (CS)" hexmask.long.byte 0x0 24.--31. 1. " BASE_CLS_CD ,Base Class Code (CS)" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BIST_HEAD_LAT_CACH,BIST, Header Type, Latency Timer, Cache Line Size" hexmask.long.byte 0x0 0.--7. 1. " CACH_LN_SZE ,Cache Line Size, No impact on write, write is allowed only for legacy purpose" hexmask.long.byte 0x0 8.--15. 1. " MSTR_LAT_TIM ,Master Latency Timer, Not Applicable for PCIe hence hardwired to 0" textline " " hexmask.long.byte 0x0 16.--22. 1. " HEAD_TYP ,Header Type 0x0 = EP header 0x1 = RC header" bitfld.long 0x0 23. " MFD ,MultiFunction Device" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " BIST ,BIST" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR0,Base Address Register 0 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask." group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR1,Base Address Register 1 If BAR0.AS = 64-bit: upper half of BAR0 base address If BAR0.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR2,Base Address Register 2 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask." group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR3,Base Address Register 3 If BAR2.AS = 64-bit: upper half of BAR2 base address If BAR2.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR4,Base Address Register 4 Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.byte 0x0 4.--11. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Masked LSBs, as set by BAR mask." textline " " hexmask.long.tbyte 0x0 12.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, upper base address bits are in BAR above). Unmasked MSBs, as set by BAR mask." group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_BAR5,Base Address Register 5 If BAR4.AS = 64-bit: upper half of BAR4 base address If BAR4.AS = 32-bit: independent 32-bit BAR Bit #0 is also a WO BAR enable (CS2) BAR Mask is writable (CS2)" bitfld.long 0x0 0. " SPACE_INDICATOR ,BAR I/O vs memory space indicator (CS) 0x0(R) = BAR type is Memory 0x1(R) = BAR type is I/O" "0,1" bitfld.long 0x0 1.--2. " AS ,MEM BAR: Address Size (CS) I/O BAR: bit 0 is always 0, bit 1 is LSBit of I/O address Read 0x0 = 32 Bit Read 0x2 = 64 Bit" "0,1,2,3" textline " " bitfld.long 0x0 3. " PREFETCHABLE ,MEM BAR: Prefetchable (CS) I/O BAR: bit 1 is part of I/O address" "0,1" hexmask.long.word 0x0 4.--19. 1. " BASE_ADDR_RO ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Masked LSBs, as set by BAR mask." textline " " hexmask.long.word 0x0 20.--31. 1. " BASE_ADDR_RW ,Base address bits (for a 64-bit BAR, lower base address bits are in BAR below). Unmasked MSBs, as set by BAR mask." group.byte 0x28++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_CARDBUS_CIS_POINTER,PCIECTRL_EP_DBICS_CARDBUS_CIS_POINTER" hexmask.long 0x0 0.--31. 1. " CARDBUS_CIS_PTR_N ,Cardbus CIS pointer (CS)" group.byte 0x2C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_SUBID_SUBVENDORID,PCIECTRL_EP_DBICS_SUBID_SUBVENDORID" hexmask.long.word 0x0 0.--15. 1. " SUBSYS_VENDOR_ID_N ,Subsystem Vendor ID (CS)" hexmask.long.word 0x0 16.--31. 1. " SUBSYS_DEV_ID_N ,Subsystem ID (CS)" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_EXPANSION_ROM_BAR,Expansion ROM Base Address Register" bitfld.long 0x0 0. " EXROM_EN ,Expansion ROM Enable" "0,1" hexmask.long.word 0x0 1.--10. 1. " RESERVED ," textline " " bitfld.long 0x0 11.--15. " EXROM_ADDRESS_RO ,Expansion ROM address, masked." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 16.--31. 1. " EXROM_ADDRESS ,Expansion ROM address, unmasked (ie programmable)" group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_CAPPTR,CapPtr" hexmask.long.byte 0x0 0.--7. 1. " CAPTR ,First Capability Pointer (CS)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_INTERRUPT,Int Pin and line" hexmask.long.byte 0x0 0.--7. 1. " INT_LIN ,Interrupt Line" hexmask.long.byte 0x0 8.--15. 1. " INT_PIN ,Interrupt Pin (CS)" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_PM_CAP,Power Management Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PM_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--18. " PMC_VER ,Power Management specification version (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " PME_CLK ,PME Clock, hardwired to 0 (CS)" "0,1" textline " " bitfld.long 0x0 20. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 21. " DSI ,Device Specific Initialization (CS)" "0,1" textline " " bitfld.long 0x0 22.--24. " AUX_CUR ,AUX Current (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 25. " D1_SP ,D1 Support (CS)" "0,1" textline " " bitfld.long 0x0 26. " D2_SP ,D2 Support (CS)" "0,1" bitfld.long 0x0 27.--31. " PME_SP ,PME Support (CS); Power states from which PME messages can be sent (active hi, one bit per state) Bit 0: from D0 Bit 1: from D1 Bit 2: from D2 Bit 3: from D3hot Bit 4: from D3cold (if Vaux present)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x44++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_PM_CSR,Power Management Control and Status Register" bitfld.long 0x0 0.--1. " PM_STATE ,Power Management Control and Status Register" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 3. " NSR ,No Soft Reset (CS)" "0,1" bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8. " PME_EN ,PME Enable (Sticky bit)" "0,1" bitfld.long 0x0 9.--12. " DATA_SEL ,Data Select (not supported)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 13.--14. " DATA_SCALE ,Data Scale (not supported)" "0,1,2,3" bitfld.long 0x0 15. " PME_STATUS ,PME Status (Sticky bit)" "0,1" textline " " bitfld.long 0x0 16.--21. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22. " B2B3_SP ,B2/B3 Support, hardwired to 0" "0,1" textline " " bitfld.long 0x0 23. " BP_CCE ,Bus Power/Clock Control Enable, hardwired to 0" "0,1" hexmask.long.byte 0x0 24.--31. 1. " DATA1 ,Data register for additional information (not supported)" group.byte 0x50++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_MSI_CAP,Message Signaled Interrupt Capability structure header" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,MSI Capability ID Read 0x05 MSI" hexmask.long.byte 0x0 8.--15. 1. " MSI_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16. " MSI_EN ,MSI Enable" "0,1" bitfld.long 0x0 17.--19. " MMC ,Multiple Message Capable (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20.--22. " MME ,Multiple Message Enable" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " MSI_64_EN ,64-bit Address Capable (CS)" "0,1" textline " " bitfld.long 0x0 24. " PVM_EN ,MSI Per Vector Masking (PVM) supported" "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ,Reserved" group.byte 0x54++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_MSI_ADD_L32,PCIe memory space address of MSI write TLP request, lower 32 bits." bitfld.long 0x0 0.--1. " RESERVED ,Reserved" "0,1,2,3" hexmask.long 0x0 2.--31. 1. " ADDR ,Lower 32-bit address (DWORD aligned)" group.byte 0x58++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_MSI_ADD_U32,PCIe memory space address of MSI write TLP request, upper 32 bits (used if MSI_64_EN = 1)." hexmask.long 0x0 0.--31. 1. " ADDR ,Upper 32-bit address" group.byte 0x5C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_MSI_DATA,Data of MSI write TLP request (modified for multiple vectors)" hexmask.long.word 0x0 0.--15. 1. " DATA ,MSI data" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x70++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_PCIE_CAP,PCIE cap structure" hexmask.long.byte 0x0 0.--7. 1. " CAP_ID ,Capability ID" hexmask.long.byte 0x0 8.--15. 1. " PCIE_NX_PTR ,Next Capability Pointer (CS)" textline " " bitfld.long 0x0 16.--19. " PCIE_VER ,PCI Express Capability Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " DEV_TYPE ,Device/Port Type Value depends on assigned type 0x0 = PCIe endpoint 0x1 = Legacy PCIe endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SLOT ,Slot Implemented Must be 0 for an endpoint" "0,1" bitfld.long 0x0 25.--29. " IM_NUM ,Interrupt Message Number (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 30.--31. " RESERVED ,Reserved" "0,1,2,3" group.byte 0x74++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_DEV_CAP,PCIE Device Capabilities" bitfld.long 0x0 0.--2. " MAX_PAYLOAD_SIZE ,Maximum Payload Size (CS) Read 0x1 = 256 Byte" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--4. " PHANTOMFUNC ,Phantom Function Support, not SUPPORTED (CS)" "0,1,2,3" textline " " bitfld.long 0x0 5. " EXTTAGFIELD_SUPPORT ,Value derived from DEFAULT_EXT_TAG_FIELD_SUPPORTED" "0,1" bitfld.long 0x0 6.--8. " DEFAULT_EP_L0S_ACCPT_LATENCY ,Endpoint L0s Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " DEFAULT_EP_L1_ACCPT_LATENCY ,Endpoint L1 Acceptable Latency (CS)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " UNDEFINED ,Undefined from PCIe 1.1 onwards (CS)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " ROLEBASED_ERRRPT ,Role Based Error Reporting (CS)" "0,1" bitfld.long 0x0 16.--17. " RESERVED ,Reserved" "0,1,2,3" textline " " hexmask.long.byte 0x0 18.--25. 1. " CAPT_SLOW_PWRLIMIT_VALUE ,Captured Slow Power Limit Value (CS)" bitfld.long 0x0 26.--27. " CAPT_SLOW_PWRLIMIT_SCALE ,Captured Slow Power Scale Value (CS)" "0,1,2,3" textline " " bitfld.long 0x0 28. " FLR_EN ,Function Level Reset Capability (CS)" "0,1" bitfld.long 0x0 29.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" group.byte 0x78++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_DEV_CAS,PCIE Device Control and Status" bitfld.long 0x0 0. " COR_RE ,Correctable Error Reporting Enable" "0,1" bitfld.long 0x0 1. " NFT_RE ,Non-Fatal Error Reporting Enable" "0,1" textline " " bitfld.long 0x0 2. " FT_RE ,Fatal Error Reporting Enable" "0,1" bitfld.long 0x0 3. " UR_RE ,Unsupported Request Reporting Enable" "0,1" textline " " bitfld.long 0x0 4. " EN_RO ,Enable Relaxed Ordering" "0,1" bitfld.long 0x0 5.--7. " MPS ,Max_Payload_Size" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " EXTAG_EN ,Extended Tag Field Enable" "0,1" bitfld.long 0x0 9. " PHFUN_EN ,Phantom Function Enable" "0,1" textline " " bitfld.long 0x0 10. " AUXPM_EN ,AUX Power PM Enable" "0,1" bitfld.long 0x0 11. " NOSNP_EN ,Enable No Snoop" "0,1" textline " " bitfld.long 0x0 12.--14. " MRRS ,Max_Read_Request_Size" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " INIT_FLR ,Reserved" "0,1" textline " " bitfld.long 0x0 16. " COR_DET ,Correctable Error Detected" "0,1" bitfld.long 0x0 17. " NFT_DET ,Non-Fatal Error Detected" "0,1" textline " " bitfld.long 0x0 18. " FT_DET ,Fatal Error Detected" "0,1" bitfld.long 0x0 19. " UR_DET ,Unsupported Request Detected" "0,1" textline " " bitfld.long 0x0 20. " AUXP_DET ,Aux Power Detected" "0,1" bitfld.long 0x0 21. " TRANS_PEND ,Transaction Pending" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ,Reserved" group.byte 0x7C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_LNK_CAP,PCIE Link Capabilities" bitfld.long 0x0 0.--3. " MAX_LINK_SPEEDS ,Supported Max Link Speed (CS) 0x1(R) = 2.5 GT/s (Gen1) 0x2(R) = 5 GT/s (Gen2) 0x4(R) = 8 GT/s (Gen3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--9. " MAX_LINK_WIDTH ,Max Link Width (lanes) (CS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 10.--11. " AS_LINK_PM_SUPPORT ,Active State Link PM (ASPM) Support (CS)" "0,1,2,3" bitfld.long 0x0 12.--14. " L0S_EXIT_LAT ,L0s Exit Latency (CS2)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " L1_EXIT_LAT ,L1 Exit Latency (CS2)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18. " CLK_PWR_MGMT ,Clock Power Management (CS)" "0,1" textline " " bitfld.long 0x0 19. " UNSUP ,Unsupported, Surprise Down Error Reporting Capable, Hardwired to 0" "0,1" bitfld.long 0x0 20. " DLL_ACTRPT_CAP ,Data Link Layer Active Reporting Capable" "0,1" textline " " bitfld.long 0x0 21. " LNK_BW_not_CAP ,Link Bandwidth Notification Capability (CS)" "0,1" bitfld.long 0x0 22. " ASPM_OPT_COMP ,ASPM Optionality Compliance (CS)" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" hexmask.long.byte 0x0 24.--31. 1. " PORT_NUM ,Port Number (CS)" group.byte 0x80++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_LNK_CAS,PCIE Link Control and Status" bitfld.long 0x0 0.--1. " ASPM_CTRL ,Active State Link PM Control 0x0: DISABLED 0x1: L0S_ENABLED 0x2: L1_ENABLED 0x3: L0S_AND_L1_ENABLED" "0,1,2,3" bitfld.long 0x0 2. " RESERVED ," "0,1" textline " " bitfld.long 0x0 3. " RCB ,Read Completion Boundary (CS) 0x0 = 64 Byte 0x1 = 128 Byte" "0,1" bitfld.long 0x0 4. " LINK_DIS ,Link Disable" "0,1" textline " " bitfld.long 0x0 5. " RETRAIN_LINK ,Retrain Link" "0,1" bitfld.long 0x0 6. " COM_CLK_CFG ,Common Clock Configuration" "0,1" textline " " bitfld.long 0x0 7. " EXT_SYN ,Extended Synch" "0,1" bitfld.long 0x0 8. " EN_CPM ,Enable Clock Power Management" "0,1" textline " " bitfld.long 0x0 9. " HAWD ,Hardware Autonomous Width Disable" "0,1" bitfld.long 0x0 10. " LBMIE ,Link Bandwidth Management Interrupt Enable" "0,1" textline " " bitfld.long 0x0 11. " LABIE ,Link Autonomous Bandwidth Interrupt Enable." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " LINK_SPEED ,Link Speed UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " NEG_LW ,Negotiated Link Width UNDEFINED UNTIL LINK IS UP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 26. " UNDEF ,Undefined" "0,1" bitfld.long 0x0 27. " LINK_TRAIN ,LINK training" "0,1" textline " " bitfld.long 0x0 28. " SLOT_CLK_CONFIG ,Slot Clock Configuration (CS)" "0,1" bitfld.long 0x0 29. " DLL_ACT ,Data Link Layer Active" "0,1" textline " " bitfld.long 0x0 30. " LBW_STATUS ,Link Bandwidth Management Status" "0,1" bitfld.long 0x0 31. " LAB_STATUS ,Link Autonomous Bandwidth Status" "0,1" group.byte 0x94++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_DEV_CAP_2,Device Capabilities 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_RNG_SUPPORTED ,Completion Timeout Ranges Supported" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS_SUPPORTED ,Completion Timeout Disable Supported" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOR_SP ,AtomicOp Routing Supported" "0,1" textline " " bitfld.long 0x0 7. " AOC32_SP ,32-bit AtomicOp Completer Supported" "0,1" bitfld.long 0x0 8. " AOC64_SP ,64-bit AtomicOp Completer Supported" "0,1" textline " " bitfld.long 0x0 9. " CASC128_SP ,128-bit CAS Completer Supported" "0,1" bitfld.long 0x0 10. " NOROPR ,No RO-enabled PR-PR Passing" "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--13. " TPHC_SP ,TPH Completer Supported" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x98++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_DEV_CAS_2,Device Control 2 Register" bitfld.long 0x0 0.--3. " CPL_TIMEOUT_VALUE ,Completion Timeout Values" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " CPL_TIMEOUT_DIS ,Completion Timeout Disable" "0,1" textline " " bitfld.long 0x0 5. " ARI_FWD_SP ,ARI Forwarding Supported" "0,1" bitfld.long 0x0 6. " AOP_REQ_EN ,AtomicOp Requester Enable" "0,1" textline " " bitfld.long 0x0 7. " AOP_EG_BLK ,AtomicOp Egress Blocking" "0,1" bitfld.long 0x0 8. " IDO_REQ_EN ,IDO Request Enable" "0,1" textline " " bitfld.long 0x0 9. " IDO_CPL_EN ,IDO Completion Enable" "0,1" bitfld.long 0x0 10. " LTR_EN ,LTR Mechanism Enable" "0,1" textline " " bitfld.long 0x0 11.--12. " RESERVED ," "0,1,2,3" bitfld.long 0x0 13.--14. " OBFF_EN ,OBFF Enable" "0,1,2,3" textline " " hexmask.long.tbyte 0x0 15.--31. 1. " RESERVED ," group.byte 0x9C++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_LNK_CAP_2,PCIE Link Capabilities 2 Register" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long.byte 0x0 1.--7. 1. " SP_LS_VEC ,Supported Link Speeds Vector" textline " " bitfld.long 0x0 8. " CROSSLINK_SP ,Crosslink Supported" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "PCIECTRL_EP_DBICS_LNK_CAS_2,Link Control and Status 2 Register" bitfld.long 0x0 0.--3. " TRGT_LINK_SPEED ,Target Link Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4. " ENTR_COMPL ,Enter Compliance" "0,1" textline " " bitfld.long 0x0 5. " HW_AUTO_SP_DIS ,Hardware Autonomous Speed Disable" "0,1" bitfld.long 0x0 6. " SEL_DEEMP ,Selectable De-emphasize" "0,1" textline " " bitfld.long 0x0 7.--9. " TX_MARGIN ,Transmit Margin" "0,1,2,3,4,5,6,7" bitfld.long 0x0 10. " ENT_MOD_COMPL ,Enter Modified Compliance" "0,1" textline " " bitfld.long 0x0 11. " COMPL_SOS ,Compliance SOS" "0,1" bitfld.long 0x0 12.--15. " COMPL_PRST_DEEPH ,Compliance Pre-set/ De-emphasis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " DEEMPH_LEVEL ,Current De-emphasis Level" "0,1" bitfld.long 0x0 17. " EQ_COMPLETE ,Equalization Complete, Gen3 Only" "0,1" textline " " bitfld.long 0x0 18. " EQ_PH1 ,Equalization Ph1 Success, Gen3 Only" "0,1" bitfld.long 0x0 19. " EQ_PH2 ,Equalization Ph2 Success, Gen3 Only" "0,1" textline " " bitfld.long 0x0 20. " EQ_PH3 ,Equalization Ph3 Success, Gen3 Only" "0,1" bitfld.long 0x0 21. " LINK_EQ_REQ ,Link Equilization Request" "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," width 0x0B tree.end tree "PCIe_SS1_PL_CONF" base ad:0x51000700 width 37. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_PL_LAT_REL_TIM,Ack Latency and Replay Timer Register" hexmask.long.word 0x0 0.--15. 1. " ACK_LATENCY_TIME_LIMIT ,The Ack/Nak latency timer expires when it reaches this limit; The default value depends on number of bytes (NB) per cycle, which is defined by the maximum core base frequency of the device PCIe core, corresponding to 250 MHz for PCIe-Gen2 (5 Gbps) operation. The default is then updated based on the Negotiated Link Width and Max_Payload_Size. Note: If operating at 5 Gb/s, then the rounded-up value of an additional (51 /CX_NB) cycles is added, where CX_NB correspond to the number of PCIEPCS 8-bit input symbols per single 16-bit lane, that is, CX_NB=2. This means at 5Gbps, 26 extra cycles should be considered for the acknowledge latency time limit. This is for additional internal processing for received TLPs and transmitted DLLPs." hexmask.long.word 0x0 16.--31. 1. " REPLAY_TIME_LIMIT ,The replay timer expires when it reaches this limit; The core initiates a replay upon reception of a Nak or when the replay timer expires; The default value depends on number of bytes (NB) per cycle, which is defined by the maximum core base frequency of the device PCIe core, corresponding to 250 MHz for PCIe-Gen2 (5 Gbps) operation. The default is then updated based on the Negotiated Link Width and Max_Payload_Size; Note: If operating at 5 Gb/s, then the rounded-up value of an additional (153/CX_NB) cycles is added, where CX_NB correspond to the number of PCIEPCS 8-bit input symbols per single 16-bit lane, that is, CX_NB=2. This means at 5Gbps, 77 extra cycles should be considered for the replay time limit. This is for additional internal processing for received TLPs and transmitted DLLPs." group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_PL_VENDOR_SPECIFIC_DLLP,Vendor Specific DLLP Register" hexmask.long 0x0 0.--31. 1. " VEN_DLLP_REG ,To send custom DLLP, write 8-bit DLLP Type and 24-bits of Payload data, then set PT_LNK_CTRL_R[0]" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_PL_PT_LNK_R,Port Force Link Register" hexmask.long.byte 0x0 0.--7. 1. " LINK_NUM ,Link Number; Not used for Endpoint" bitfld.long 0x0 8.--11. " FORCED_LTSSM_STATE ,LTSSM state forced by setting Force_Link (bit 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " FORCE_LINK ,Forces the LTSSM state and the Link command specified in this register; Self-clearing" "0,1" textline " " bitfld.long 0x0 16.--21. " FORCED_LINK_COMMAND ,Link command transmitted by setting Force_Link (bit 15);" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 24.--31. 1. " LOW_POWER_ENTR_CNT ,The Power Management state will wait for this many clock cycles for the associated completion of a CfgWr to D-state register to go low-power; This register is intended for applications that do not let the core handle a completion for configuration request to the PMCSCR register; Note: Only used in the DM core (in EP mode), EP core, and the Upstream Port of a Switch" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_PL_ACK_FREQ_ASPM,Ack Frequency and L0-L1 ASPM Control Register (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " ACK_FREQ ,Ack Frequency; Number of pending ACKs accumulated before sending an ACK DLLP" hexmask.long.byte 0x0 8.--15. 1. " N_FTS ,Number of Fast Training Sequence (FTS) ordered sets to be transmitted when exiting L0s to L0; The maximum that can be requested is 255; Value 0 is not supported, and may cause LTSSM to go into Recovery upon L0s exit" textline " " hexmask.long.byte 0x0 16.--23. 1. " COMMOM_CLK_N_FTS ,Alternative N_FTS value, for common clock mode" bitfld.long 0x0 24.--26. " L0S_ENTR_LAT ,L0s Entrance Latency; Values correspond to: 0b000: 1 us 0b001: 2 us 0b010: 3 us 0b011: 4 us 0b100: 5 us 0b101: 6 us 0b110: 7 us 0b111: 7 us (alternate encoding)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--29. " L1_ENTR_LAT ,L1 Entrance Latency 0x0: 1 uS 0x1: 2 uS 0x2: 4 uS 0x3: 8 uS 0x4: 16 uS 0x5: 32 uS 0x6: 64 uS 0x7: 64 uS (alternate encoding)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30. " L1_ENTR_WO_L0S ,Enter ASPM L1 without receive in L0s; Allow core to enter ASPM L1 even when link partner did not go to L0s (receive is not in L0s); When not set, core goes to ASPM L1 only after idle period during which both receive and transmit are in L0s" "0,1" textline " " bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_PL_PT_LNK_CTRL_R,Port Link Control Register (Sticky)" bitfld.long 0x0 0. " VEN_DLLP_REQ ,Vendor Specific DLLP transmit Request" "0,1" bitfld.long 0x0 1. " SCRAMBLE_DIS ,Scramble Disable" "0,1" textline " " bitfld.long 0x0 2. " LB_EN ,Loopback Enable" "0,1" bitfld.long 0x0 3. " RESET_ASSERT ,Reset Assert" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5. " DL_EN ,DLL Link Enable" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " FAST_LINK ,Fast Link Mode" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--21. " LINK_MODE ,Link Mode Enable; Write 1 to bit N to enable (2**N)-lane mode 0x01: _1x 0x03: _2x 0x07: _4x" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 22. " CROSSLINK_EN ,Crosslink Enable" "0,1" bitfld.long 0x0 23. " CROSSLINK_ACT ,Crosslink Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_PL_LN_SKW_R,Lane Skew Register (Sticky)" hexmask.long.tbyte 0x0 0.--23. 1. " LANE_SKEW ,Insert Lane Skew for Transmit" bitfld.long 0x0 24. " FC_DIS ,Flow Control Disable" "0,1" textline " " bitfld.long 0x0 25. " ACKNAK_DIS ,Ack/Nak Disable" "0,1" bitfld.long 0x0 26.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 31. " DIS_L2L_SKEW ,Disable Lane-to-Lane Deskew" "0,1" group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_PL_SYMB_N_R,Timer Control and Symbol Number Register (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " MAX_FUNC ,Configuration Requests targeted at function numbers above this value will be returned with UR (unsupported request)." bitfld.long 0x0 8.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 14.--18. " REPLAY_ADJ ,Timer Modifier for Replay Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 19.--23. " ACK_LATENCY_INC ,Timer Modifier for Ack/Nak Latency Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_PL_SYMB_T_R,Symbol Timer Register and Filter Mask Register 1 (Sticky)" hexmask.long.word 0x0 0.--10. 1. " SKP_INT ,SKP Interval Value minus one, PIPE clock cycles. (1 PIPE cycle = 2 symbols in 16-bit-per-lane PIPE)" bitfld.long 0x0 11.--14. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " DIS_FC_TIM ,Disable FC Watchdog Timer" "0,1" hexmask.long.word 0x0 16.--31. 1. " FLT_MSK_1 ,Mask RADM Filtering and Error Handling Rules: Mask 1" group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_PL_FL_MSK_R2,Filter Mask Register 2 (Sticky)" hexmask.long 0x0 0.--31. 1. " FLT_MSK_2 ,Mask RADM Filtering and Error Handling Rules: Mask 2" group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_PL_OBNP_SUBREQ_CTRL,AXI Multiple Outbound Decomposed NP SubRequests Control Register (Sticky)" bitfld.long 0x0 0. " EN_OBNP_SUBREQ ,Enable AXI Multiple Outbound Decomposed NP Sub-Requests." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_PL_TR_P_STS_R,Transmit Posted FC Credit Status Register (Sticky)" hexmask.long.word 0x0 0.--11. 1. " PD_CRDT ,Transmit Posted Data FC Credits" hexmask.long.byte 0x0 12.--19. 1. " PH_CRDT ,Transmit Posted Header FC Credits" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_PL_TR_NP_STS_R,Transmit Non-Posted FC Credit Status Register (Sticky)" hexmask.long.word 0x0 0.--11. 1. " NPD_CRDT ,Transmit Non-Posted Data FC Credits" hexmask.long.byte 0x0 12.--19. 1. " NPH_CRDT ,Transmit Non-Posted Header FC Credits" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "PCIECTRL_PL_TR_C_STS_R,Transmit Completion FC Credit Status Register (Sticky)" hexmask.long.word 0x0 0.--11. 1. " CPLD_CRDT ,Transmit Completion Data FC Credits" hexmask.long.byte 0x0 12.--19. 1. " CPLH_CRDT ,Transmit Completion Header FC Credits" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_PL_Q_STS_R,Queue Status Register (Sticky)" bitfld.long 0x0 0. " CRDT_not_RTRN ,Received TLP FC Credits Not Returned" "0,1" bitfld.long 0x0 1. " RTYB_not_EMPTY ,Transmit Retry Buffer Not Empty" "0,1" textline " " bitfld.long 0x0 2. " RCVQ_not_EMPTY ,Received Queue Not Empty" "0,1" hexmask.long.word 0x0 3.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--28. 1. " FC_LATENCY_OVR ,FC Latency Timer Override Value" bitfld.long 0x0 29.--30. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 31. " FC_LATENCY_OVR_EN ,FC Latency Timer Override Enable" "0,1" group.byte 0x40++0x3 line.long 0x0 "PCIECTRL_PL_VC_TR_A_R1,VC Transmit Arbitration Register 1 (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " WRR_VC0 ,WRR Weight for VC0" hexmask.long.byte 0x0 8.--15. 1. " WRR_VC1 ,WRR Weight for VC1" textline " " hexmask.long.byte 0x0 16.--23. 1. " WRR_VC2 ,WRR Weight for VC2" hexmask.long.byte 0x0 24.--31. 1. " WRR_VC3 ,WRR Weight for VC3" group.byte 0x44++0x3 line.long 0x0 "PCIECTRL_PL_VC_TR_A_R2,VC Transmit Arbitration Register 2 (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " WRR_VC4 ,WRR Weight for VC4" hexmask.long.byte 0x0 8.--15. 1. " WRR_VC5 ,WRR Weight for VC5" textline " " hexmask.long.byte 0x0 16.--23. 1. " WRR_VC6 ,WRR Weight for VC6" hexmask.long.byte 0x0 24.--31. 1. " WRR_VC7 ,WRR Weight for VC7" group.byte 0x48++0x3 line.long 0x0 "PCIECTRL_PL_VC0_PR_Q_C,VC0 Posted Receive Queue Control (Sticky)" hexmask.long.word 0x0 0.--11. 1. " P_DCRD ,VC0 Posted Data Credits" hexmask.long.byte 0x0 12.--19. 1. " P_HCRD ,VC0 Posted Header Credits" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21.--23. " P_QMODE ,VC0 Poster TLP Queue Mode Read 0x1: STORE_AND_FORWARD Read 0x2: CUT_THROUGH Read 0x4: BYPASS Others: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--29. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 30. " ORDERING_RULES ,VC0 TLP Type Ordering Rules" "0,1" textline " " bitfld.long 0x0 31. " STRICT_VC_PRIORITY ,VC Ordering for Receive Queues" "0,1" group.byte 0x4C++0x3 line.long 0x0 "PCIECTRL_PL_VC0_NPR_Q_C,VC0 Non-Posted Receive Queue Control (Sticky)" hexmask.long.word 0x0 0.--11. 1. " NP_DCRD ,VC0 Non-Posted Data Credits" hexmask.long.byte 0x0 12.--19. 1. " NP_HCRD ,VC0 Non-Posted Header Credits" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21.--23. " NP_QMODE ,VC0 Non-Poster TLP Queue Mode Read 0x1: STORE_AND_FORWARD Read 0x2: CUT_THROUGH Read 0x4: BYPASS Others: Reserved" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "PCIECTRL_PL_VC0_CR_Q_C,VC0 Completion Receive Queue Control (Sticky)" hexmask.long.word 0x0 0.--11. 1. " CPL_DCRD ,VC0 Completion Data Credits" hexmask.long.byte 0x0 12.--19. 1. " CPL_HCRD ,VC0 Completion Header Credits" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21.--23. " CPL_QMODE ,VC0 Completion TLP Queue Mode Read 0x1: STORE_AND_FORWARD Read 0x2: CUT_THROUGH Read 0x4: BYPASS" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "PCIECTRL_PL_WIDTH_SPEED_CTL,Link Width and Speed Change Control Register (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " CFG_Gen2_N_FTS ,Number of Fast Training Sequences" hexmask.long.word 0x0 8.--16. 1. " CFG_LANE_EN ,Predetermined Number of Lanes" textline " " bitfld.long 0x0 17. " CFG_DIRECTED_SPEED_CHANGE ,Directed Speed Change" "0,1" bitfld.long 0x0 18. " CFG_PHY_TXSWING ,Config PHY Tx Swing" "0,1" textline " " bitfld.long 0x0 19. " CFG_TX_COMPLIANCE_RCV ,Config Tx Compliance Receive Bit" "0,1" bitfld.long 0x0 20. " CFG_UP_SEL_DEEMPH ,Used to set the de-emphasis level for Upstream Ports" "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "PCIECTRL_PL_PHY_STS_R,PHY Status Register (Sticky)" hexmask.long 0x0 0.--31. 1. " PHY_STS ,PHY Status" group.byte 0x114++0x3 line.long 0x0 "PCIECTRL_PL_PHY_CTRL_R,PHY Control Register (Sticky)" hexmask.long 0x0 0.--31. 1. " PHY_CTRL ,PHY Control" group.byte 0x120++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_ADDRESS,MSI Controller Address Register (RC-mode MSI receiver)" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_ADDRESS ," group.byte 0x124++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_UPPER_ADDRESS,MSI Controller Upper Address Register (RC-mode MSI receiver)" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_UPPER_ADDRESS ," group.byte 0x128++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_0,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x134++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_1,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x140++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_2,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x14C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_3,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x158++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_4,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x164++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_5,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x170++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_6,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x17C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_7,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x12C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_0,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x138++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_1,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x144++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_2,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x150++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_3,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x15C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_4,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x168++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_5,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x174++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_6,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x180++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_7,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x130++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_0,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x13C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_1,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x148++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_2,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x154++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_3,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x160++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_4,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x16C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_5,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x178++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_6,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x184++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_7,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x188++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_GPIO,MSI Controller General Purpose IO Register (RC-mode MSI receiver)" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_GPIO ," group.byte 0x1B8++0x3 line.long 0x0 "PCIECTRL_PL_PIPE_LOOPBACK,PIPE loopback control register (Sticky)" hexmask.long 0x0 0.--30. 1. " RESERVED ," bitfld.long 0x0 31. " LOOPBACK_EN ,PIPE Loopback Enable" "0,1" group.byte 0x1BC++0x3 line.long 0x0 "PCIECTRL_PL_DBI_RO_WR_EN,DIF Read-Only register Write Enable (Sticky)" bitfld.long 0x0 0. " CX_DBI_RO_WR_EN ,Control the writability over DIF of certain configuration fields that are RO over the PCIe wire" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x1D0++0x3 line.long 0x0 "PCIECTRL_PL_AXIS_SLV_ERR_RESP,AXI Slave Error Response Register (Sticky)" bitfld.long 0x0 0. " SLAVE_ERR_MAP ,Global Slave Error Response Mapping" "0,1" bitfld.long 0x0 1. " DBI_ERR_MAP ,DIF Slave Error Response Mapping" "0,1" textline " " bitfld.long 0x0 2. " NO_VID_ERR_MAP ,Vendor ID Non-existent Slave Error Response Mapping" "0,1" bitfld.long 0x0 3. " RESET_TIMEOUT_ERR_MAP ,Graceful Reset and Link Timeout Slave Error Response Mapping" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x1D4++0x3 line.long 0x0 "PCIECTRL_PL_AXIS_SLV_TIMEOUT,Link Down AXI Slave Timeout Register (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " TIMEOUT_VALUE ,Timeout Value (ms)" bitfld.long 0x0 8. " FLUSH_EN ,Enable flush" "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x200++0x3 line.long 0x0 "PCIECTRL_PL_IATU_INDEX,iATU Viewport Register: makes the registers of the corresponding iATU region accessible." bitfld.long 0x0 0.--3. " REGION_INDEX ,Outbound region, from 0 to 15. Inbound region, from 0 to 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " REGION_DIRECTION ," "0,1" group.byte 0x204++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_CTRL_1,iATU Region Control 1 Register" bitfld.long 0x0 0.--4. " TYPE ,Outbound: TYPE applied to outgoing TLP with matching addess Inbound: TYPE-match criteria" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " TC ,Outbound: TC applied to outgoing TLP with matching addess Inbound: TC-match criteria (if TC_match_enable=1)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " TD ,Outbound: TD applied to outgoing TLP with matching addess Inbound: TD-match criteria (if TD_match_enable=1)" "0,1" bitfld.long 0x0 9.--10. " ATTR ,Outbound: ATTR applied to outgoing TLP with matching addess Inbound: ATTR-match criteria (if ATTR_match_enable=1)" "0,1,2,3" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 16.--17. " AT ,Outbound: AT applied to outgoing TLP with matching addess Inbound: AT-match criteria for matching TLP (if AT_match_enable=1)" "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" bitfld.long 0x0 20.--24. " FUNCTION_NUMBER ,Outbound: F.N; applied to outgoing TLP (RID) with matching addess Inbound: F.N.-match criteria for incoming TLP (if Function_Number_match_enable=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_CTRL_2,iATU Region Control 2 Register" hexmask.long.byte 0x0 0.--7. 1. " MESSAGECODE ,Outbound: MessageCode applied to outgoing message TLP with matching addess Inbound: MessageCode-match criteria for infoming message TLP (if Message_Code_match_enable=1)" bitfld.long 0x0 8.--10. " BAR_NUMBER ,BAR number for mayching with incoming MEM, I/O TLP (if Match_Mode = 1) 0x0: BAR0 0x1: BAR1 0x2: BAR2 0x3: BAR3 0x4: BAR4 0x5: BAR5 0x6: ROM" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14. " TC_MATCH_ENABLE ,Enable TC match criteria on inbound TLP" "0,1" textline " " bitfld.long 0x0 15. " TD_MATCH_ENABLE ,Enable TD match criteria on inbound TLP" "0,1" bitfld.long 0x0 16. " ATTR_MATCH_ENABLE ,Enable ATTR match criteria on inbound TLP" "0,1" textline " " bitfld.long 0x0 17. " RESERVED ," "0,1" bitfld.long 0x0 18. " AT_MATCH_ENABLE ,Enable AT match criteria on inbound TLP ATS not SUPPORTED: DO not USE" "0,1" textline " " bitfld.long 0x0 19. " FUNCTION_NUMBER_MATCH_ENABLE ,Outbound: Function Number Translation Bypass Inbound: Enable Function Number match criteria" "0,1" bitfld.long 0x0 20. " VIRTUAL_FUNCTION_NUMBER_MATCH_ENABLE ,VIRTUAL FUNCTIONS not IMPLEMENTED: not USED" "0,1" textline " " bitfld.long 0x0 21. " MESSAGE_CODE_MATCH_ENABLE ,Enable MessageCode match criteria on inbound TLP" "0,1" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24.--25. " RESPONSE_CODE ,Override HW-generated completion status when responding inbound TLP 0x0: No override, use HW-generated CS 0x1: Unsupported Request: CS= 3'b001 0x2: Completer Abort: CS= 3'b100" "0,1,2,3" bitfld.long 0x0 26. " RESERVED ," "0,1" textline " " bitfld.long 0x0 27. " FUZZY_TYPE_MATCH_MODE ,Outbound: DMA Bypass Mode Inbound: Relax matching on inbound TLP TYPE: CfgRd0 == CfgRd1 CfgWr0 == CfgWr1 MRd == MRdLk routing field of Msg/MsgD ignored" "0,1" bitfld.long 0x0 28. " CFG_SHIFT_MODE ,Enable the shifting of CFG CID (BDF), incoming and outgoing TLP; CFG get mapped to a contiguous 2**28 = 256 MByte address space Untranslated CID = CFG_DW#3[31:16] Shifted CID = CFG_DW#3[27:12]" "0,1" textline " " bitfld.long 0x0 29. " INVERT_MODE ,Redefine match criteria as outside the defined range (instead of inside)" "0,1" bitfld.long 0x0 30. " MATCH_MODE ,Sets inbound TLP match mode, depending on TYPE" "0,1" textline " " bitfld.long 0x0 31. " REGION_ENABLE ,Enable AT for this region" "0,1" group.byte 0x20C++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_LOWER_BASE,iATU Region Lower Base Address Register (2**12 = 4kbyte - aligned)" hexmask.long.word 0x0 0.--11. 1. " ZERO ," hexmask.long.tbyte 0x0 12.--31. 1. " IATU_REG_LOWER_BASE ," group.byte 0x210++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_UPPER_BASE,iATU Region Upper Base Address Register" hexmask.long 0x0 0.--31. 1. " IATU_REG_UPPER_BASE ," group.byte 0x214++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_LIMIT,iATU Region Limit Address Register" hexmask.long.word 0x0 0.--11. 1. " ONES ," hexmask.long.tbyte 0x0 12.--31. 1. " IATU_REG_LIMIT ," group.byte 0x218++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_LOWER_TARGET,iATU Region Lower Target Address Register (2**12 = 4kbyte - aligned)" hexmask.long.word 0x0 0.--11. 1. " ZERO ," hexmask.long.tbyte 0x0 12.--31. 1. " IATU_REG_LOWER_TARGET ," group.byte 0x21C++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_UPPER_TARGET,iATU Region Upper Target Address Register" hexmask.long 0x0 0.--31. 1. " IATU_REG_UPPER_TARGET ," group.byte 0x220++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_CTRL_3,iATU Region Control 3 Register; VIRTUAL FUNCTIONS not IMPLEMENTED: not USED" hexmask.long 0x0 0.--31. 1. " IATU_REG_CTRL_3 ," width 0x0B tree.end tree "PCIe_SS2_PL_CONF" base ad:0x51800700 width 37. group.byte 0x0++0x3 line.long 0x0 "PCIECTRL_PL_LAT_REL_TIM,Ack Latency and Replay Timer Register" hexmask.long.word 0x0 0.--15. 1. " ACK_LATENCY_TIME_LIMIT ,The Ack/Nak latency timer expires when it reaches this limit; The default value depends on number of bytes (NB) per cycle, which is defined by the maximum core base frequency of the device PCIe core, corresponding to 250 MHz for PCIe-Gen2 (5 Gbps) operation. The default is then updated based on the Negotiated Link Width and Max_Payload_Size. Note: If operating at 5 Gb/s, then the rounded-up value of an additional (51 /CX_NB) cycles is added, where CX_NB correspond to the number of PCIEPCS 8-bit input symbols per single 16-bit lane, that is, CX_NB=2. This means at 5Gbps, 26 extra cycles should be considered for the acknowledge latency time limit. This is for additional internal processing for received TLPs and transmitted DLLPs." hexmask.long.word 0x0 16.--31. 1. " REPLAY_TIME_LIMIT ,The replay timer expires when it reaches this limit; The core initiates a replay upon reception of a Nak or when the replay timer expires; The default value depends on number of bytes (NB) per cycle, which is defined by the maximum core base frequency of the device PCIe core, corresponding to 250 MHz for PCIe-Gen2 (5 Gbps) operation. The default is then updated based on the Negotiated Link Width and Max_Payload_Size; Note: If operating at 5 Gb/s, then the rounded-up value of an additional (153/CX_NB) cycles is added, where CX_NB correspond to the number of PCIEPCS 8-bit input symbols per single 16-bit lane, that is, CX_NB=2. This means at 5Gbps, 77 extra cycles should be considered for the replay time limit. This is for additional internal processing for received TLPs and transmitted DLLPs." group.byte 0x4++0x3 line.long 0x0 "PCIECTRL_PL_VENDOR_SPECIFIC_DLLP,Vendor Specific DLLP Register" hexmask.long 0x0 0.--31. 1. " VEN_DLLP_REG ,To send custom DLLP, write 8-bit DLLP Type and 24-bits of Payload data, then set PT_LNK_CTRL_R[0]" group.byte 0x8++0x3 line.long 0x0 "PCIECTRL_PL_PT_LNK_R,Port Force Link Register" hexmask.long.byte 0x0 0.--7. 1. " LINK_NUM ,Link Number; Not used for Endpoint" bitfld.long 0x0 8.--11. " FORCED_LTSSM_STATE ,LTSSM state forced by setting Force_Link (bit 15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " FORCE_LINK ,Forces the LTSSM state and the Link command specified in this register; Self-clearing" "0,1" textline " " bitfld.long 0x0 16.--21. " FORCED_LINK_COMMAND ,Link command transmitted by setting Force_Link (bit 15);" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " hexmask.long.byte 0x0 24.--31. 1. " LOW_POWER_ENTR_CNT ,The Power Management state will wait for this many clock cycles for the associated completion of a CfgWr to D-state register to go low-power; This register is intended for applications that do not let the core handle a completion for configuration request to the PMCSCR register; Note: Only used in the DM core (in EP mode), EP core, and the Upstream Port of a Switch" group.byte 0xC++0x3 line.long 0x0 "PCIECTRL_PL_ACK_FREQ_ASPM,Ack Frequency and L0-L1 ASPM Control Register (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " ACK_FREQ ,Ack Frequency; Number of pending ACKs accumulated before sending an ACK DLLP" hexmask.long.byte 0x0 8.--15. 1. " N_FTS ,Number of Fast Training Sequence (FTS) ordered sets to be transmitted when exiting L0s to L0; The maximum that can be requested is 255; Value 0 is not supported, and may cause LTSSM to go into Recovery upon L0s exit" textline " " hexmask.long.byte 0x0 16.--23. 1. " COMMOM_CLK_N_FTS ,Alternative N_FTS value, for common clock mode" bitfld.long 0x0 24.--26. " L0S_ENTR_LAT ,L0s Entrance Latency; Values correspond to: 0b000: 1 us 0b001: 2 us 0b010: 3 us 0b011: 4 us 0b100: 5 us 0b101: 6 us 0b110: 7 us 0b111: 7 us (alternate encoding)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 27.--29. " L1_ENTR_LAT ,L1 Entrance Latency 0x0: 1 uS 0x1: 2 uS 0x2: 4 uS 0x3: 8 uS 0x4: 16 uS 0x5: 32 uS 0x6: 64 uS 0x7: 64 uS (alternate encoding)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 30. " L1_ENTR_WO_L0S ,Enter ASPM L1 without receive in L0s; Allow core to enter ASPM L1 even when link partner did not go to L0s (receive is not in L0s); When not set, core goes to ASPM L1 only after idle period during which both receive and transmit are in L0s" "0,1" textline " " bitfld.long 0x0 31. " RESERVED ,Reserved" "0,1" group.byte 0x10++0x3 line.long 0x0 "PCIECTRL_PL_PT_LNK_CTRL_R,Port Link Control Register (Sticky)" bitfld.long 0x0 0. " VEN_DLLP_REQ ,Vendor Specific DLLP transmit Request" "0,1" bitfld.long 0x0 1. " SCRAMBLE_DIS ,Scramble Disable" "0,1" textline " " bitfld.long 0x0 2. " LB_EN ,Loopback Enable" "0,1" bitfld.long 0x0 3. " RESET_ASSERT ,Reset Assert" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ," "0,1" bitfld.long 0x0 5. " DL_EN ,DLL Link Enable" "0,1" textline " " bitfld.long 0x0 6. " RESERVED ," "0,1" bitfld.long 0x0 7. " FAST_LINK ,Fast Link Mode" "0,1" textline " " hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," bitfld.long 0x0 16.--21. " LINK_MODE ,Link Mode Enable; Write 1 to bit N to enable (2**N)-lane mode 0x01: _1x 0x03: _2x 0x07: _4x" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 22. " CROSSLINK_EN ,Crosslink Enable" "0,1" bitfld.long 0x0 23. " CROSSLINK_ACT ,Crosslink Active" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "PCIECTRL_PL_LN_SKW_R,Lane Skew Register (Sticky)" hexmask.long.tbyte 0x0 0.--23. 1. " LANE_SKEW ,Insert Lane Skew for Transmit" bitfld.long 0x0 24. " FC_DIS ,Flow Control Disable" "0,1" textline " " bitfld.long 0x0 25. " ACKNAK_DIS ,Ack/Nak Disable" "0,1" bitfld.long 0x0 26.--30. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 31. " DIS_L2L_SKEW ,Disable Lane-to-Lane Deskew" "0,1" group.byte 0x18++0x3 line.long 0x0 "PCIECTRL_PL_SYMB_N_R,Timer Control and Symbol Number Register (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " MAX_FUNC ,Configuration Requests targeted at function numbers above this value will be returned with UR (unsupported request)." bitfld.long 0x0 8.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 14.--18. " REPLAY_ADJ ,Timer Modifier for Replay Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 19.--23. " ACK_LATENCY_INC ,Timer Modifier for Ack/Nak Latency Timer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PCIECTRL_PL_SYMB_T_R,Symbol Timer Register and Filter Mask Register 1 (Sticky)" hexmask.long.word 0x0 0.--10. 1. " SKP_INT ,SKP Interval Value minus one, PIPE clock cycles. (1 PIPE cycle = 2 symbols in 16-bit-per-lane PIPE)" bitfld.long 0x0 11.--14. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " DIS_FC_TIM ,Disable FC Watchdog Timer" "0,1" hexmask.long.word 0x0 16.--31. 1. " FLT_MSK_1 ,Mask RADM Filtering and Error Handling Rules: Mask 1" group.byte 0x20++0x3 line.long 0x0 "PCIECTRL_PL_FL_MSK_R2,Filter Mask Register 2 (Sticky)" hexmask.long 0x0 0.--31. 1. " FLT_MSK_2 ,Mask RADM Filtering and Error Handling Rules: Mask 2" group.byte 0x24++0x3 line.long 0x0 "PCIECTRL_PL_OBNP_SUBREQ_CTRL,AXI Multiple Outbound Decomposed NP SubRequests Control Register (Sticky)" bitfld.long 0x0 0. " EN_OBNP_SUBREQ ,Enable AXI Multiple Outbound Decomposed NP Sub-Requests." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x30++0x3 line.long 0x0 "PCIECTRL_PL_TR_P_STS_R,Transmit Posted FC Credit Status Register (Sticky)" hexmask.long.word 0x0 0.--11. 1. " PD_CRDT ,Transmit Posted Data FC Credits" hexmask.long.byte 0x0 12.--19. 1. " PH_CRDT ,Transmit Posted Header FC Credits" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "PCIECTRL_PL_TR_NP_STS_R,Transmit Non-Posted FC Credit Status Register (Sticky)" hexmask.long.word 0x0 0.--11. 1. " NPD_CRDT ,Transmit Non-Posted Data FC Credits" hexmask.long.byte 0x0 12.--19. 1. " NPH_CRDT ,Transmit Non-Posted Header FC Credits" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x38++0x3 line.long 0x0 "PCIECTRL_PL_TR_C_STS_R,Transmit Completion FC Credit Status Register (Sticky)" hexmask.long.word 0x0 0.--11. 1. " CPLD_CRDT ,Transmit Completion Data FC Credits" hexmask.long.byte 0x0 12.--19. 1. " CPLH_CRDT ,Transmit Completion Header FC Credits" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,Reserved" group.byte 0x3C++0x3 line.long 0x0 "PCIECTRL_PL_Q_STS_R,Queue Status Register (Sticky)" bitfld.long 0x0 0. " CRDT_not_RTRN ,Received TLP FC Credits Not Returned" "0,1" bitfld.long 0x0 1. " RTYB_not_EMPTY ,Transmit Retry Buffer Not Empty" "0,1" textline " " bitfld.long 0x0 2. " RCVQ_not_EMPTY ,Received Queue Not Empty" "0,1" hexmask.long.word 0x0 3.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--28. 1. " FC_LATENCY_OVR ,FC Latency Timer Override Value" bitfld.long 0x0 29.--30. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 31. " FC_LATENCY_OVR_EN ,FC Latency Timer Override Enable" "0,1" group.byte 0x40++0x3 line.long 0x0 "PCIECTRL_PL_VC_TR_A_R1,VC Transmit Arbitration Register 1 (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " WRR_VC0 ,WRR Weight for VC0" hexmask.long.byte 0x0 8.--15. 1. " WRR_VC1 ,WRR Weight for VC1" textline " " hexmask.long.byte 0x0 16.--23. 1. " WRR_VC2 ,WRR Weight for VC2" hexmask.long.byte 0x0 24.--31. 1. " WRR_VC3 ,WRR Weight for VC3" group.byte 0x44++0x3 line.long 0x0 "PCIECTRL_PL_VC_TR_A_R2,VC Transmit Arbitration Register 2 (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " WRR_VC4 ,WRR Weight for VC4" hexmask.long.byte 0x0 8.--15. 1. " WRR_VC5 ,WRR Weight for VC5" textline " " hexmask.long.byte 0x0 16.--23. 1. " WRR_VC6 ,WRR Weight for VC6" hexmask.long.byte 0x0 24.--31. 1. " WRR_VC7 ,WRR Weight for VC7" group.byte 0x48++0x3 line.long 0x0 "PCIECTRL_PL_VC0_PR_Q_C,VC0 Posted Receive Queue Control (Sticky)" hexmask.long.word 0x0 0.--11. 1. " P_DCRD ,VC0 Posted Data Credits" hexmask.long.byte 0x0 12.--19. 1. " P_HCRD ,VC0 Posted Header Credits" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21.--23. " P_QMODE ,VC0 Poster TLP Queue Mode Read 0x1: STORE_AND_FORWARD Read 0x2: CUT_THROUGH Read 0x4: BYPASS Others: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 24.--29. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 30. " ORDERING_RULES ,VC0 TLP Type Ordering Rules" "0,1" textline " " bitfld.long 0x0 31. " STRICT_VC_PRIORITY ,VC Ordering for Receive Queues" "0,1" group.byte 0x4C++0x3 line.long 0x0 "PCIECTRL_PL_VC0_NPR_Q_C,VC0 Non-Posted Receive Queue Control (Sticky)" hexmask.long.word 0x0 0.--11. 1. " NP_DCRD ,VC0 Non-Posted Data Credits" hexmask.long.byte 0x0 12.--19. 1. " NP_HCRD ,VC0 Non-Posted Header Credits" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21.--23. " NP_QMODE ,VC0 Non-Poster TLP Queue Mode Read 0x1: STORE_AND_FORWARD Read 0x2: CUT_THROUGH Read 0x4: BYPASS Others: Reserved" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "PCIECTRL_PL_VC0_CR_Q_C,VC0 Completion Receive Queue Control (Sticky)" hexmask.long.word 0x0 0.--11. 1. " CPL_DCRD ,VC0 Completion Data Credits" hexmask.long.byte 0x0 12.--19. 1. " CPL_HCRD ,VC0 Completion Header Credits" textline " " bitfld.long 0x0 20. " RESERVED ," "0,1" bitfld.long 0x0 21.--23. " CPL_QMODE ,VC0 Completion TLP Queue Mode Read 0x1: STORE_AND_FORWARD Read 0x2: CUT_THROUGH Read 0x4: BYPASS" "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "PCIECTRL_PL_WIDTH_SPEED_CTL,Link Width and Speed Change Control Register (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " CFG_Gen2_N_FTS ,Number of Fast Training Sequences" hexmask.long.word 0x0 8.--16. 1. " CFG_LANE_EN ,Predetermined Number of Lanes" textline " " bitfld.long 0x0 17. " CFG_DIRECTED_SPEED_CHANGE ,Directed Speed Change" "0,1" bitfld.long 0x0 18. " CFG_PHY_TXSWING ,Config PHY Tx Swing" "0,1" textline " " bitfld.long 0x0 19. " CFG_TX_COMPLIANCE_RCV ,Config Tx Compliance Receive Bit" "0,1" bitfld.long 0x0 20. " CFG_UP_SEL_DEEMPH ,Used to set the de-emphasis level for Upstream Ports" "0,1" textline " " hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "PCIECTRL_PL_PHY_STS_R,PHY Status Register (Sticky)" hexmask.long 0x0 0.--31. 1. " PHY_STS ,PHY Status" group.byte 0x114++0x3 line.long 0x0 "PCIECTRL_PL_PHY_CTRL_R,PHY Control Register (Sticky)" hexmask.long 0x0 0.--31. 1. " PHY_CTRL ,PHY Control" group.byte 0x120++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_ADDRESS,MSI Controller Address Register (RC-mode MSI receiver)" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_ADDRESS ," group.byte 0x124++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_UPPER_ADDRESS,MSI Controller Upper Address Register (RC-mode MSI receiver)" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_UPPER_ADDRESS ," group.byte 0x128++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_0,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x134++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_1,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x140++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_2,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x14C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_3,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x158++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_4,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x164++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_5,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x170++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_6,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x17C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_ENABLE_N_7,MSI Controller Interrupt #N Enable Register (RC-mode MSI receiver) with N = MSI data [7:5] and ENABLE[i] = enable MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_ENABLE ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x12C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_0,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x138++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_1,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x144++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_2,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x150++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_3,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x15C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_4,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x168++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_5,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x174++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_6,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x180++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_MASK_N_7,MSI Controller Interrupt #N Mask Register (RC-mode MSI receiver) with N = MSI data [7:5] and MASK[i] = mask of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_MASK ,Status of a masked bit (vector) triggers no IRQ to MPU when set." group.byte 0x130++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_0,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x13C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_1,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x148++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_2,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x154++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_3,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x160++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_4,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x16C++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_5,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x178++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_6,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x184++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_INT_STATUS_N_7,MSI Controller Interrupt #N Status Register (RC-mode MSI receiver) with N = MSI data [7:5] and STATUS[i] = status of MSI vector #i, with i = MSI data [4:0]" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_INT_STATUS ,Status of an enabled bit (vectors) is set upon incoming MSI." group.byte 0x188++0x3 line.long 0x0 "PCIECTRL_PL_MSI_CTRL_GPIO,MSI Controller General Purpose IO Register (RC-mode MSI receiver)" hexmask.long 0x0 0.--31. 1. " MSI_CTRL_GPIO ," group.byte 0x1B8++0x3 line.long 0x0 "PCIECTRL_PL_PIPE_LOOPBACK,PIPE loopback control register (Sticky)" hexmask.long 0x0 0.--30. 1. " RESERVED ," bitfld.long 0x0 31. " LOOPBACK_EN ,PIPE Loopback Enable" "0,1" group.byte 0x1BC++0x3 line.long 0x0 "PCIECTRL_PL_DBI_RO_WR_EN,DIF Read-Only register Write Enable (Sticky)" bitfld.long 0x0 0. " CX_DBI_RO_WR_EN ,Control the writability over DIF of certain configuration fields that are RO over the PCIe wire" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x1D0++0x3 line.long 0x0 "PCIECTRL_PL_AXIS_SLV_ERR_RESP,AXI Slave Error Response Register (Sticky)" bitfld.long 0x0 0. " SLAVE_ERR_MAP ,Global Slave Error Response Mapping" "0,1" bitfld.long 0x0 1. " DBI_ERR_MAP ,DIF Slave Error Response Mapping" "0,1" textline " " bitfld.long 0x0 2. " NO_VID_ERR_MAP ,Vendor ID Non-existent Slave Error Response Mapping" "0,1" bitfld.long 0x0 3. " RESET_TIMEOUT_ERR_MAP ,Graceful Reset and Link Timeout Slave Error Response Mapping" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x1D4++0x3 line.long 0x0 "PCIECTRL_PL_AXIS_SLV_TIMEOUT,Link Down AXI Slave Timeout Register (Sticky)" hexmask.long.byte 0x0 0.--7. 1. " TIMEOUT_VALUE ,Timeout Value (ms)" bitfld.long 0x0 8. " FLUSH_EN ,Enable flush" "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x200++0x3 line.long 0x0 "PCIECTRL_PL_IATU_INDEX,iATU Viewport Register: makes the registers of the corresponding iATU region accessible." bitfld.long 0x0 0.--3. " REGION_INDEX ,Outbound region, from 0 to 15. Inbound region, from 0 to 3." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " REGION_DIRECTION ," "0,1" group.byte 0x204++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_CTRL_1,iATU Region Control 1 Register" bitfld.long 0x0 0.--4. " TYPE ,Outbound: TYPE applied to outgoing TLP with matching addess Inbound: TYPE-match criteria" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " TC ,Outbound: TC applied to outgoing TLP with matching addess Inbound: TC-match criteria (if TC_match_enable=1)" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " TD ,Outbound: TD applied to outgoing TLP with matching addess Inbound: TD-match criteria (if TD_match_enable=1)" "0,1" bitfld.long 0x0 9.--10. " ATTR ,Outbound: ATTR applied to outgoing TLP with matching addess Inbound: ATTR-match criteria (if ATTR_match_enable=1)" "0,1,2,3" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 16.--17. " AT ,Outbound: AT applied to outgoing TLP with matching addess Inbound: AT-match criteria for matching TLP (if AT_match_enable=1)" "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" bitfld.long 0x0 20.--24. " FUNCTION_NUMBER ,Outbound: F.N; applied to outgoing TLP (RID) with matching addess Inbound: F.N.-match criteria for incoming TLP (if Function_Number_match_enable=1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_CTRL_2,iATU Region Control 2 Register" hexmask.long.byte 0x0 0.--7. 1. " MESSAGECODE ,Outbound: MessageCode applied to outgoing message TLP with matching addess Inbound: MessageCode-match criteria for infoming message TLP (if Message_Code_match_enable=1)" bitfld.long 0x0 8.--10. " BAR_NUMBER ,BAR number for mayching with incoming MEM, I/O TLP (if Match_Mode = 1) 0x0: BAR0 0x1: BAR1 0x2: BAR2 0x3: BAR3 0x4: BAR4 0x5: BAR5 0x6: ROM" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14. " TC_MATCH_ENABLE ,Enable TC match criteria on inbound TLP" "0,1" textline " " bitfld.long 0x0 15. " TD_MATCH_ENABLE ,Enable TD match criteria on inbound TLP" "0,1" bitfld.long 0x0 16. " ATTR_MATCH_ENABLE ,Enable ATTR match criteria on inbound TLP" "0,1" textline " " bitfld.long 0x0 17. " RESERVED ," "0,1" bitfld.long 0x0 18. " AT_MATCH_ENABLE ,Enable AT match criteria on inbound TLP ATS not SUPPORTED: DO not USE" "0,1" textline " " bitfld.long 0x0 19. " FUNCTION_NUMBER_MATCH_ENABLE ,Outbound: Function Number Translation Bypass Inbound: Enable Function Number match criteria" "0,1" bitfld.long 0x0 20. " VIRTUAL_FUNCTION_NUMBER_MATCH_ENABLE ,VIRTUAL FUNCTIONS not IMPLEMENTED: not USED" "0,1" textline " " bitfld.long 0x0 21. " MESSAGE_CODE_MATCH_ENABLE ,Enable MessageCode match criteria on inbound TLP" "0,1" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24.--25. " RESPONSE_CODE ,Override HW-generated completion status when responding inbound TLP 0x0: No override, use HW-generated CS 0x1: Unsupported Request: CS= 3'b001 0x2: Completer Abort: CS= 3'b100" "0,1,2,3" bitfld.long 0x0 26. " RESERVED ," "0,1" textline " " bitfld.long 0x0 27. " FUZZY_TYPE_MATCH_MODE ,Outbound: DMA Bypass Mode Inbound: Relax matching on inbound TLP TYPE: CfgRd0 == CfgRd1 CfgWr0 == CfgWr1 MRd == MRdLk routing field of Msg/MsgD ignored" "0,1" bitfld.long 0x0 28. " CFG_SHIFT_MODE ,Enable the shifting of CFG CID (BDF), incoming and outgoing TLP; CFG get mapped to a contiguous 2**28 = 256 MByte address space Untranslated CID = CFG_DW#3[31:16] Shifted CID = CFG_DW#3[27:12]" "0,1" textline " " bitfld.long 0x0 29. " INVERT_MODE ,Redefine match criteria as outside the defined range (instead of inside)" "0,1" bitfld.long 0x0 30. " MATCH_MODE ,Sets inbound TLP match mode, depending on TYPE" "0,1" textline " " bitfld.long 0x0 31. " REGION_ENABLE ,Enable AT for this region" "0,1" group.byte 0x20C++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_LOWER_BASE,iATU Region Lower Base Address Register (2**12 = 4kbyte - aligned)" hexmask.long.word 0x0 0.--11. 1. " ZERO ," hexmask.long.tbyte 0x0 12.--31. 1. " IATU_REG_LOWER_BASE ," group.byte 0x210++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_UPPER_BASE,iATU Region Upper Base Address Register" hexmask.long 0x0 0.--31. 1. " IATU_REG_UPPER_BASE ," group.byte 0x214++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_LIMIT,iATU Region Limit Address Register" hexmask.long.word 0x0 0.--11. 1. " ONES ," hexmask.long.tbyte 0x0 12.--31. 1. " IATU_REG_LIMIT ," group.byte 0x218++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_LOWER_TARGET,iATU Region Lower Target Address Register (2**12 = 4kbyte - aligned)" hexmask.long.word 0x0 0.--11. 1. " ZERO ," hexmask.long.tbyte 0x0 12.--31. 1. " IATU_REG_LOWER_TARGET ," group.byte 0x21C++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_UPPER_TARGET,iATU Region Upper Target Address Register" hexmask.long 0x0 0.--31. 1. " IATU_REG_UPPER_TARGET ," group.byte 0x220++0x3 line.long 0x0 "PCIECTRL_PL_IATU_REG_CTRL_3,iATU Region Control 3 Register; VIRTUAL FUNCTIONS not IMPLEMENTED: not USED" hexmask.long 0x0 0.--31. 1. " IATU_REG_CTRL_3 ," width 0x0B tree.end tree "DCAN2" base ad:0x48480000 width 15. group.byte 0x0++0x3 line.long 0x0 "DCAN_CTL,DCAN control register NOTE: The Bus-Off recovery sequence (refer to CAN specification) cannot be shortened by setting or resetting INIT bit. If the module goes Bus-Off, it will automatically set the INIT bit and stop all bus activities. When the INIT bit is cleared by the application again, the module will then wait for 129 occurrences of Bus Idle (129 W 11 consecutive recessive bits) before resuming normal operation. At the end of the bus-off recovery sequence, the error counters will be reset. After the INIT bit is reset, each time when a sequence of 11 recessive bits is monitored, a Bit0 error code is written to , enabling the software to check whether the CAN bus is stuck at dominant or continuously disturbed, and to monitor the proceeding of the bus-off recovery sequence." bitfld.long 0x0 0. " INIT ,Initialization" "0,1" bitfld.long 0x0 1. " IE0 ,Interrupt line 0 enable" "0,1" textline " " bitfld.long 0x0 2. " SIE ,Status change interrupt enable" "0,1" bitfld.long 0x0 3. " EIE ,Error interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,This bit is always read as 0. Writes have no effect." "0,1" bitfld.long 0x0 5. " DAR ,Disable automatic retransmission" "0,1" textline " " bitfld.long 0x0 6. " CCE ,Configuration change enable" "0,1" bitfld.long 0x0 7. " TEST ,Test mode enable" "0,1" textline " " bitfld.long 0x0 8. " IDS ,Interruption debug support enable" "0,1" bitfld.long 0x0 9. " ABO ,Auto-Bus-On enable" "0,1" textline " " bitfld.long 0x0 10.--13. " PMD ,Parityon/offOthers: function enabled ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 14. " RESERVED ,This bit is always read as 0. Writes have no effect." "0,1" textline " " bitfld.long 0x0 15. " SWR ,Software reset enable. Note: To execute software reset, the following procedure is necessary:" "0,1" bitfld.long 0x0 16. " INITDBG ,Internal init state while debug access" "0,1" textline " " bitfld.long 0x0 17. " IE1 ,Interrupt line 1 enable" "0,1" bitfld.long 0x0 18. " DE1 ,Enable DMA request line for IF1. Note: A pending DMA request for IF1 remains active until first access to one of the IF1 registers." "0,1" textline " " bitfld.long 0x0 19. " DE2 ,Enable DMA request line for IF2. Note: A pending DMA request for IF2 remains active until first access to one of the IF2 registers." "0,1" bitfld.long 0x0 20. " DE3 ,Enable DMA request line for IF3. Note: A pending DMA request for IF3 remains active until first access to one of the IF3 registers." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. " PDR ,Request for local low power-down mode" "0,1" textline " " bitfld.long 0x0 25. " WUBA ,Automatic wake up on bus activity when in local power-down mode. Note: The CAN message, which initiates the bus activity, cannot be received. This means that the first message received in power down and automatic wake-up mode, will be lost." "0,1" bitfld.long 0x0 26.--31. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x4++0x3 line.long 0x0 "DCAN_ES,Error and Status Register Interrupts are generated by bits PER, BOFF and EWARN (if EIE bit in is 1) and by bits WAKEUPPND, RXOK, TXOK, and LEC (if SIE bit in is 1). A change of bit EPASS will not generate an interrupt. Reading the clears the WAKEUPPND, PER, RXOK and TXOK bits and set the LEC to value '7.' Additionally, the status interrupt value (0x8000) in the will be replaced by the next lower priority interrupt value. For debug support, the auto clear functionality of (clear of status flags by read) is disabled when in debug/suspend mode." bitfld.long 0x0 0.--2. " LEC ,Last error code. The LEC field indicates the type of the last error on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " TXOK ,Transmitted a message successfully. This bit will be reset ifDCAN_ES register is read. ." "0,1" textline " " bitfld.long 0x0 4. " RXOK ,Received a message successfully. This bit will be reset ifDCAN_ES register is read. ." "0,1" bitfld.long 0x0 5. " EPASS ,Error passive state" "0,1" textline " " bitfld.long 0x0 6. " EWARN ,Warning state" "0,1" bitfld.long 0x0 7. " BOFF ,Bus-Off state" "0,1" textline " " bitfld.long 0x0 8. " PER ,Parity error detected. This bit will be reset ifDCAN_ES register is read." "0,1" bitfld.long 0x0 9. " WAKEUPPND ,Wake up pending. This bit can be used by the software to identify the DCAN as the source to wake up the system. This bit will be reset ifDCAN_ES is read. ." "0,1" textline " " bitfld.long 0x0 10. " PDA ,Local power-down mode acknowledge" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x8++0x3 line.long 0x0 "DCAN_ERRC,Error Counter Register" hexmask.long.byte 0x0 0.--7. 1. " TEC ,Transmit error counter. Actual state of the transmit error counter" hexmask.long.byte 0x0 8.--14. 1. " REC ,Receive error counter. Actual state of the receive error counter" textline " " bitfld.long 0x0 15. " RP ,Receive error passive" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0xC++0x3 line.long 0x0 "DCAN_BTR,Bit timing register This register is only writable if CCE and INIT bits in the are set. The CAN bit time may be programmed in the range of 8 to 25 time quanta The CAN time quantum may be programmed in the range of 1 to 1024 CAN_CLK periods." bitfld.long 0x0 0.--5. " BRP ,Baud rate prescalerValue by which the CAN_CLK frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. . Valid programmed values are 0 to 63. . The actual BRP value interpreted for the bit timing will be the programmed BRP value + 1. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " SJW ,Synchronization Jump WidthValid programmed values are 0 to 3. . The actual SJW value interpreted for the synchronization will be the programmed SJW value + 1. ." "0,1,2,3" textline " " bitfld.long 0x0 8.--11. " TSEG1 ,Time segment before the sample pointValid programmed values are 1 to15. . The actual TSeg1 value interpreted for the bit timing will be the programmed TSeg1 value + 1. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--14. " TSEG2 ,Time segment after the sample pointValid programmed values are 0 to 7. . The actual TSeg2 value which is interpreted for the bit timing will be the programmed TSeg2 value + 1. ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1" bitfld.long 0x0 16.--19. " BRPE ,Baud rate prescaler extension.Valid programmed values are 0 to 15. . By programming BRPE the baud rate prescaler can be extended to values up to 1024. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x10++0x3 line.long 0x0 "DCAN_INT,Interrupt register" hexmask.long.word 0x0 0.--15. 1. " INT0ID ,Interrupt Identifier (the number here indicates the source of the interrupt)0x0001-0x0080: Number of message object which caused the interrupt. . 0x0081-0x7FFF: Unused . 0x8001-0xFFFF: Unused . If several interrupts are pending,DCAN_INTwill point to the pending interrupt with the highest priority. The INT0 interrupt line remains active until INT0ID reaches value 0 (the cause of the interrupt is reset) or until IE0 is cleared. . The Status interrupt has the highest priority. Among the message interrupts, the message object's interrupt priority decreases with increasing message number. ." hexmask.long.byte 0x0 16.--23. 1. " INT1ID ,Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)0x01-0x80: Number of message object which caused the interrupt. . 0x81-0xFF: Unused . If several interrupts are pending, will point to the pending interrupt with the highest priority. The INT1 interrupt line remains active until INT1ID reaches value 0 (the cause of the interrupt is reset) or until IE1 is cleared. . A message interrupt is cleared by clearing the message object's IntPnd bit. . Among the message interrupts, the message object's interrupt priority decreases with increasing message number. ." textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x14++0x3 line.long 0x0 "DCAN_TEST,Test Register For all test modes, the TEST bit in control register needs to be set to 1. If TEST bit is set, the RDA, EXL, TX1, TX0, LBACK and SILENT bits are writable. Bit RX monitors the state of pin CAN_RX and therefore is only readable. All test register functions are disabled when TEST bit is cleared." bitfld.long 0x0 0.--2. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " SILENT ,Silent mode" "0,1" textline " " bitfld.long 0x0 4. " LBACK ,Loopback mode. When the internal loop-back mode is active (bit LBACK is set), bit EXL will be ignored." "0,1" bitfld.long 0x0 5.--6. " TX ,Control of CAN_TX pin. Setting Tx[1:0] other than '00' will disturb message transfer." "0,1,2,3" textline " " bitfld.long 0x0 7. " RX ,Receive pin. Monitors the actual value of the CAN_RX pin" "0,1" bitfld.long 0x0 8. " EXL ,External loopback mode. When the internal loop-back mode is active (bit LBACK is set), bit EXL will be ignored." "0,1" textline " " bitfld.long 0x0 9. " RDA ,RAM direct access enable" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x1C++0x3 line.long 0x0 "DCAN_PERR,Parity Error Code Register If a parity error is detected, the PER flag will be set in the . This bit is not reset by the parity check mechanism; it must be reset by reading . In addition to the PER flag, the parity error code register will indicate the memory area where the parity error has been detected (message number and word number). If more than one word with a parity error was detected, the highest word number with a parity error will be displayed. After a parity error has been detected, the register will hold the last error code until power is removed." hexmask.long.byte 0x0 0.--7. 1. " MESSAGE_NUMBER ,Message object number where parity error has been detected (0x01-0x80)" bitfld.long 0x0 8.--10. " WORD_NUMBER ,Word number where parity error has been detectedRDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode). ." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x20++0x3 line.long 0x0 "DCAN_REL,Core revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,DCAN core revision number" group.byte 0x80++0x3 line.long 0x0 "DCAN_ABOTR,Auto-Bus-On Time Register On write access to the while Auto-Bus-On timer is running, the Auto-Bus-On procedure will be aborted. During Debug/Suspend mode, running Auto-Bus-On timer will be paused." hexmask.long 0x0 0.--31. 1. " ABO_TIME ,Number of OCP clock cycles before a Bus-Off recovery sequence is started by clearing the INIT bit. This function has to be enabled by setting bit ABO inDCAN_CTL. The Auto-Bus-On timer is realized by a 32-bit counter which starts to count down to zero when the module goes Bus-Off. The counter will be reloaded with the preload value of the DCAN_ABOTR after this phase." group.byte 0x84++0x3 line.long 0x0 "DCAN_TXRQ_X,Transmission Request X Register The software can detect if one or more bits in the different transmission request registers are set. Each register bit represents a group of eight message objects. If at least one of the TxRqst bits of these message objects are set, the corresponding bit in the transmission request X register will be set." bitfld.long 0x0 0.--1. " TXRQSTREG1 ,Transmission request bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 2.--3. " TXRQSTREG2 ,Transmission request bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " TXRQSTREG3 ,Transmission request bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 6.--7. " TXRQSTREG4 ,Transmission request bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " TXRQSTREG5 ,Transmission request bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 10.--11. " TXRQSTREG6 ,Transmission request bits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " TXRQSTREG7 ,Transmission request bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 14.--15. " TXRQSTREG8 ,Transmission request bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x88++0x3 line.long 0x0 "DCAN_TXRQ12,Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " TXRQS ,Transmission request bits (for 1-32 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done." group.byte 0x8C++0x3 line.long 0x0 "DCAN_TXRQ34,Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " TXRQS ,Transmission request bits (for 33-64 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done." group.byte 0x90++0x3 line.long 0x0 "DCAN_TXRQ56,Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " TXRQS ,Transmission request bits (for 65-96 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done." group.byte 0x94++0x3 line.long 0x0 "DCAN_TXRQ78,Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " TXRQS ,Transmission request bits (for 97-128 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done." group.byte 0x98++0x3 line.long 0x0 "DCAN_NWDAT_X,New Data X Register With the new data X register, the software can detect if one or more bits in the different new data registers are set. Each register bit represents a group of eight message objects. If at least on of the NewDat bits of these message objects are set, the corresponding bit in the new data X register will be set" bitfld.long 0x0 0.--1. " NEWDATREG1 ,New data bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 2.--3. " NEWDATREG2 ,New data bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " NEWDATREG3 ,New data bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 6.--7. " NEWDATREG4 ,New data bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " NEWDATREG5 ,New data bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 10.--11. " NEWDATREG6 ,New data bits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " NEWDATREG7 ,New data bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 14.--15. " NEWDATREG8 ,New data bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x9C++0x3 line.long 0x0 "DCAN_NWDAT12,New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " NEWDAT ,New Data Bits (for 1-32 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object." group.byte 0xA0++0x3 line.long 0x0 "DCAN_NWDAT34,New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " NEWDAT ,New Data Bits (for 33-64 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object." group.byte 0xA4++0x3 line.long 0x0 "DCAN_NWDAT56,New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " NEWDAT ,New Data Bits (for 65-96 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object." group.byte 0xA8++0x3 line.long 0x0 "DCAN_NWDAT78,New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " NEWDAT ,New Data Bits (for 97-128 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object." group.byte 0xAC++0x3 line.long 0x0 "DCAN_INTPND_X,Interrupt Pending X Register With the interrupt pending X register, the software can detect if one or more bits in the different interrupt pending registers are set. Each bit of this register represents a group of eight message objects. If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the interrupt pending X register will be set." bitfld.long 0x0 0.--1. " INTPNDREG1 ,Interrupt Pending bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 2.--3. " INTPNDREG2 ,Interrupt Pending bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " INTPNDREG3 ,Interrupt Pending bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 6.--7. " INTPNDREG4 ,Interrupt Pending bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " INTPNDREG5 ,Interrupt Pending bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 10.--11. " INTPNDREG6 ,Interrupt Pendingbits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " INTPNDREG7 ,Interrupt Pending bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 14.--15. " INTPNDREG8 ,Interrupt Pending bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "DCAN_INTPND12,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission." hexmask.long 0x0 0.--31. 1. " INTPND ,Interrupt Pending Bits (for 1-32 message objects)" group.byte 0xB4++0x3 line.long 0x0 "DCAN_INTPND34,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission." hexmask.long 0x0 0.--31. 1. " INTPND ,Interrupt Pending Bits (for 33-64 message objects)" group.byte 0xB8++0x3 line.long 0x0 "DCAN_INTPND56,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission." hexmask.long 0x0 0.--31. 1. " INTPND ,Interrupt Pending Bits (for 65-96 message objects)" group.byte 0xBC++0x3 line.long 0x0 "DCAN_INTPND78,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission." hexmask.long 0x0 0.--31. 1. " INTPND ,Interrupt Pending Bits (for 97-128 message objects)" group.byte 0xC0++0x3 line.long 0x0 "DCAN_MSGVAL_X,Message Valid X Register With the message valid X register, the software can detect if one or more bits in the different message valid registers are set. Each bit of this register represents a group of eight message objects. If at least one of the MsgVal bits of these message objects are set, the corresponding bit in the message valid X register will be set." bitfld.long 0x0 0.--1. " MSGVALREG1 ,Message valid bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 2.--3. " MSGVALREG2 ,Message valid bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " MSGVALREG3 ,Message valid bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 6.--7. " MSGVALREG4 ,Message valid bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " MSGVALREG5 ,Message valid bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 10.--11. " MSGVALREG6 ,Message valid bits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " MSGVALREG7 ,Message valid bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 14.--15. " MSGVALREG8 ,Message valid bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "DCAN_MSGVAL12,Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission" hexmask.long 0x0 0.--31. 1. " MSGVAL ,Message valid Bits (for 1-32 message objects)" group.byte 0xC8++0x3 line.long 0x0 "DCAN_MSGVAL34,Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission" hexmask.long 0x0 0.--31. 1. " MSGVAL ,Message valid Bits (for 33-64 message objects)" group.byte 0xCC++0x3 line.long 0x0 "DCAN_MSGVAL56,Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission" hexmask.long 0x0 0.--31. 1. " MSGVAL ,Message valid Bits (for 65-96 message objects)" group.byte 0xD0++0x3 line.long 0x0 "DCAN_MSGVAL78,Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission" hexmask.long 0x0 0.--31. 1. " MSGVAL ,Message valid Bits (for 97-128 message objects)" group.byte 0xD8++0x3 line.long 0x0 "DCAN_INTMUX12,Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in . The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp. INT1ID flags in the register." hexmask.long 0x0 0.--31. 1. " INTMUX ,Multiplexes IntPnd value to either INT0 or INT1 interrupt lines (bit 0 -> last implemented message object) ( bits 1:31 -> 1-31 message objects)" group.byte 0xDC++0x3 line.long 0x0 "DCAN_INTMUX34,Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN control register. The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp INT1ID flags in the register." hexmask.long 0x0 0.--31. 1. " INTMUX ,Multiplexes IntPnd value to either INT0 or INT1 interrupt lines ( bits 0:31 -> 32-63 message objects)" group.byte 0xE0++0x3 line.long 0x0 "DCAN_INTMUX56,Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN control register. The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp INT1ID flags in the register." hexmask.long 0x0 0.--31. 1. " INTMUX ,Multiplexes IntPnd value to either INT0 or INT1 interrupt lines ( bits 0:31 -> 64-95 message objects)" group.byte 0xE4++0x3 line.long 0x0 "DCAN_INTMUX78,Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN control register. The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp INT1ID flags in the register." hexmask.long 0x0 0.--31. 1. " INTMUX ,Multiplexes IntPnd value to either INT0 or INT1 interrupt lines ( bits 0:31 -> 96-127 message objects)" group.byte 0x100++0x3 line.long 0x0 "DCAN_IF1CMD,IF1 Command Register The IF1 Command Register () configure and initiate the transfer between the IF1 register set and the message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the software writes the message number to bits [7:0] MESSAGE_NUMBER. With this write operation, the BUSY bit is automatically set to 1 to indicate that a transfer is in progress. After 4 to 14 OCP clock cycles, the transfer between the interface register and the message RAM will be completed and the BUSY bit is cleared. The maximum number of cycles is needed when the message transfer concurs with a CAN message transmission, acceptance filtering, or message storage. If the software writes to both / consecutively (request of a second transfer while first transfer is still in progress), the second transfer will start after the first one has been completed. While BUSY bit is one, IF1/IF2 register sets are write protected. For debug support, the auto clear functionality of the IF1/IF2 command registers (clear of DMAACTIVE flag by r/w) is disabled during Debug/Suspend mode. If an invalid Message Number is written to bits [7:0] MESSAGE_NUMBER, the message handler may access an implemented (valid) message object instead." hexmask.long.byte 0x0 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers . 0x81-0xFF: Invalid message numbers ." bitfld.long 0x0 8.--13. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 updateThe DMA request remains active until the first read or write to one of the IF1 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one. . Note: Due to the auto reset feature of the DMAACTIVE bit, this bit has to be set for each subsequent DMA cycle separately. ." "0,1" bitfld.long 0x0 15. " BUSY ,Busy flagThis bit is set to one after the message number has been written to bits [7:0] MESSAGE_NUMBER. IF1 register set will be write protected. The bit is cleared after read/write action has been finished. ." "0,1" textline " " bitfld.long 0x0 16. " DATA_B ,Access Data Bytes 4-7Note: The duration of the message transfer is independent of the number of bytes to be transferred. ." "0,1" bitfld.long 0x0 17. " DATA_A ,Access Data Bytes 0-3Note: The duration of the message transfer is independent of the number of bytes to be transferred. ." "0,1" textline " " bitfld.long 0x0 18. " TXRQST_NEWDAT ,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register, the TxRqst/NewDat bits in the message object will be set to one independent of the values in. . Note: A read access to a message object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the always reflect the status before resetting them. ." "0,1" bitfld.long 0x0 19. " CLRINTPND ,Clear interrupt pending bit" "0,1" textline " " bitfld.long 0x0 20. " CONTROL ,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set, the TXRQST/ NEWDAT bits in the will be ignored. ." "0,1" bitfld.long 0x0 21. " ARB ,Access arbitration bits" "0,1" textline " " bitfld.long 0x0 22. " MASK ,Access mask bits" "0,1" bitfld.long 0x0 23. " WR_RD ,Write/Read" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x104++0x3 line.long 0x0 "DCAN_IF1MSK,IF1 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long 0x0 0.--28. 1. " MSK ,Identifier Mask" bitfld.long 0x0 29. " RESERVED ,This bit is always read as 1. Writes have no effect." "0,1" textline " " bitfld.long 0x0 30. " MDIR ,Mask Message Direction" "0,1" bitfld.long 0x0 31. " MXTD ,Mask Extended IdentifierWhen 11-bit (standard) identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered. ." "0,1" group.byte 0x108++0x3 line.long 0x0 "DCAN_IF1ARB,IF1 arbitration register The Arbitration bits ID[28:0], XTD, and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0], MXTD, and MDIR) for acceptance filtering of incoming messages. A received message is stored into the valid message object with matching identifier and Direction = receive (data frame) or Direction = transmit (remote frame). Extended frames can be stored only in message objects with XTD = 1, standard frames in message objects with XTD = 0. If a received message (data frame or remote frame) matches more than one valid message objects, it is stored into the one with the lowest message number. The bits of the IF1/IF2 arbitration registers mirror the arbitration bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long 0x0 0.--28. 1. " ID ,Message identifierID[28:0]: 29-bit identifier (extended frame) . ID[28:18]: 11-bit identifier (standard frame) ." bitfld.long 0x0 29. " DIR ,Message direction" "0,1" textline " " bitfld.long 0x0 30. " XTD ,Extended identifier" "0,1" bitfld.long 0x0 31. " MSGVAL ,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the. This bit must also be reset if the messages object is no longer required. ." "0,1" group.byte 0x10C++0x3 line.long 0x0 "DCAN_IF1MCTL,IF1 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects While BUSY bit of / register is one, IF1/IF2 register set is write protected." bitfld.long 0x0 0.--3. " DLC ,Data length code0-8: Data frame has 0-8 data bytes. . 9-15 Data frame has 8 data bytes. . Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " EOB ,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to 1. ." "0,1" bitfld.long 0x0 8. " TXRQST ,Transmit request" "0,1" textline " " bitfld.long 0x0 9. " RMTEN ,Remote enable" "0,1" bitfld.long 0x0 10. " RXIE ,Receive interrupt enable" "0,1" textline " " bitfld.long 0x0 11. " TXIE ,Transmit interrupt enable" "0,1" bitfld.long 0x0 12. " UMASK ,Use acceptance maskIf the UMASK bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one. ." "0,1" textline " " bitfld.long 0x0 13. " INTPND ,Interrupt pending" "0,1" bitfld.long 0x0 14. " MSGLST ,Message lost (only valid for message objects with direction = receive)" "0,1" textline " " bitfld.long 0x0 15. " NEWDAT ,New data" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x110++0x3 line.long 0x0 "DCAN_IF1DATA,IF1 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long.byte 0x0 0.--7. 1. " DATA_0 ,Data byte 0" hexmask.long.byte 0x0 8.--15. 1. " DATA_1 ,Data byte 1" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_2 ,Data byte 2" hexmask.long.byte 0x0 24.--31. 1. " DATA_3 ,Data byte 3" group.byte 0x114++0x3 line.long 0x0 "DCAN_IF1DATB,IF1 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long.byte 0x0 0.--7. 1. " DATA_4 ,Data byte 4" hexmask.long.byte 0x0 8.--15. 1. " DATA_5 ,Data byte 5" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_6 ,Data byte 6" hexmask.long.byte 0x0 24.--31. 1. " DATA_7 ,Data byte 7" group.byte 0x120++0x3 line.long 0x0 "DCAN_IF2CMD,IF2 Command Register The IF2 Command Register () configure and initiate the transfer between the IF2 register set and the message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the software writes the message number to bits [7:0] MESSAGE_NUMBER. With this write operation, the BUSY bit is automatically set to 1 to indicate that a transfer is in progress. After 4 to 14 OCP clock cycles, the transfer between the interface register and the message RAM will be completed and the BUSY bit is cleared. The maximum number of cycles is needed when the message transfer concurs with a CAN message transmission, acceptance filtering, or message storage. If the software writes to both / consecutively (request of a second transfer while first transfer is still in progress), the second transfer will start after the first one has been completed. While BUSY bit is one, IF1/IF2 register sets are write protected. For debug support, the auto clear functionality of the IF1/IF2 command registers (clear of DMAACTIVE flag by r/w) is disabled during Debug/Suspend mode. If an invalid Message Number is written to bits [7:0] MESSAGE_NUMBER, the message handler may access an implemented (valid) message object instead." hexmask.long.byte 0x0 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers . 0x81-0xFF: Invalid message numbers ." bitfld.long 0x0 8.--13. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF2 updateThe DMA request remains active until the first read or write to one of the IF2 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one. . Note: Due to the auto reset feature of the DMAACTIVE bit, this bit has to be set for each subsequent DMA cycle separately. ." "0,1" bitfld.long 0x0 15. " BUSY ,Busy flagThis bit is set to one after the message number has been written to bits [7:0] MESSAGE_NUMBER. IF2 register set will be write protected. The bit is cleared after read/write action has been finished. ." "0,1" textline " " bitfld.long 0x0 16. " DATA_B ,Access Data Bytes 4-7Note: The duration of the message transfer is independent of the number of bytes to be transferred. ." "0,1" bitfld.long 0x0 17. " DATA_A ,Access Data Bytes 0-3Note: The duration of the message transfer is independent of the number of bytes to be transferred. ." "0,1" textline " " bitfld.long 0x0 18. " TXRQST_NEWDAT ,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register, the TxRqst/NewDat bits in the message object will be set to one independent of the values in/. . Note: A read access to a message object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the/ always reflect the status before resetting them. ." "0,1" bitfld.long 0x0 19. " CLRINTPND ,Clear interrupt pending bit" "0,1" textline " " bitfld.long 0x0 20. " CONTROL ,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set, the TXRQST/ NEWDAT bits in the/ will be ignored. ." "0,1" bitfld.long 0x0 21. " ARB ,Access arbitration bits" "0,1" textline " " bitfld.long 0x0 22. " MASK ,Access mask bits" "0,1" bitfld.long 0x0 23. " WR_RD ,Write/Read" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x124++0x3 line.long 0x0 "DCAN_IF2MSK,IF2 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long 0x0 0.--28. 1. " MSK ,Identifier Mask" bitfld.long 0x0 29. " RESERVED ,This bit is always read as 1. Writes have no effect." "0,1" textline " " bitfld.long 0x0 30. " MDIR ,Mask Message Direction" "0,1" bitfld.long 0x0 31. " MXTD ,Mask Extended IdentifierWhen 11-bit (standard) identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered. ." "0,1" group.byte 0x128++0x3 line.long 0x0 "DCAN_IF2ARB,IF2 arbitration register The Arbitration bits ID[28:0], XTD, and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0], MXTD, and MDIR) for acceptance filtering of incoming messages. A received message is stored into the valid message object with matching identifier and Direction = receive (data frame) or Direction = transmit (remote frame). Extended frames can be stored only in message objects with Xtd = 1, standard frames in message objects with Xtd = 0. If a received message (data frame or remote frame) matches more than one valid message objects, it is stored into the one with the lowest message number. The bits of the IF1/IF2 arbitration registers mirror the arbitration bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long 0x0 0.--28. 1. " ID ,Message identifierID[28:0]: 29-bit identifier (extended frame) . ID[28:18]: 11-bit identifier (standard frame) ." bitfld.long 0x0 29. " DIR ,Message direction" "0,1" textline " " bitfld.long 0x0 30. " XTD ,Extended identifier" "0,1" bitfld.long 0x0 31. " MSGVAL ,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the. This bit must also be reset if the messages object is no longer required. ." "0,1" group.byte 0x12C++0x3 line.long 0x0 "DCAN_IF2MCTL,IF2 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects While BUSY bit of / register is one, IF1/IF2 register set is write protected." bitfld.long 0x0 0.--3. " DLC ,Data length code0-8: Data frame has 0-8 data bytes. . 9-15 Data frame has 8 data bytes. . Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " EOB ,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one. ." "0,1" bitfld.long 0x0 8. " TXRQST ,Transmit request" "0,1" textline " " bitfld.long 0x0 9. " RMTEN ,Remote enable" "0,1" bitfld.long 0x0 10. " RXIE ,Receive interrupt enable" "0,1" textline " " bitfld.long 0x0 11. " TXIE ,Transmit interrupt enable" "0,1" bitfld.long 0x0 12. " UMASK ,Use acceptance maskIf the UMask bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one. ." "0,1" textline " " bitfld.long 0x0 13. " INTPND ,Interrupt pending" "0,1" bitfld.long 0x0 14. " MSGLST ,Message lost (only valid for message objects with direction = receive)" "0,1" textline " " bitfld.long 0x0 15. " NEWDAT ,New data" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x130++0x3 line.long 0x0 "DCAN_IF2DATA,IF2 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long.byte 0x0 0.--7. 1. " DATA_0 ,Data byte 0" hexmask.long.byte 0x0 8.--15. 1. " DATA_1 ,Data byte 1" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_2 ,Data byte 2" hexmask.long.byte 0x0 24.--31. 1. " DATA_3 ,Data byte 3" group.byte 0x134++0x3 line.long 0x0 "DCAN_IF2DATB,IF2 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long.byte 0x0 0.--7. 1. " DATA_4 ,Data byte 4" hexmask.long.byte 0x0 8.--15. 1. " DATA_5 ,Data byte 5" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_6 ,Data byte 6" hexmask.long.byte 0x0 24.--31. 1. " DATA_7 ,Data byte 7" group.byte 0x140++0x3 line.long 0x0 "DCAN_IF3OBS,IF3 Observation Register The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from message RAM by software (Additional information can be found in NOTE: If IF3 Update Enable is used and no Observation flag is set, the corresponding message objects will be copied to IF3 without activating the DMA request line and without waiting for DMA read accesses. A write access to this register aborts a pending DMA cycle by resetting the DMA line and enables updating of IF3 interface register set with new data. To avoid data inconsistency, the DMA controller should be disabled before reconfiguring IF3 observation register. The status of the current read-cycle can be observed via status flags (Bits [12:8])." bitfld.long 0x0 0. " MASK ,Mask data read observation" "0,1" bitfld.long 0x0 1. " ARB ,Arbitration data read observation" "0,1" textline " " bitfld.long 0x0 2. " CTRL ,Ctrl read observation" "0,1" bitfld.long 0x0 3. " DATAA ,Data A read observation" "0,1" textline " " bitfld.long 0x0 4. " DATAB ,Data B read observation" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " IF3_SM ,IF3 Status of Mask data read access" "0,1" bitfld.long 0x0 9. " IF3_SA ,IF3 Status of Arbitration data read access" "0,1" textline " " bitfld.long 0x0 10. " IF3_SC ,IF3 Status of control bits read access" "0,1" bitfld.long 0x0 11. " IF3_SDA ,IF3 Status of Data A read access" "0,1" textline " " bitfld.long 0x0 12. " IF3_SDB ,IF3 Status of Data B read access" "0,1" bitfld.long 0x0 13.--14. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3" textline " " bitfld.long 0x0 15. " IF3_UPD ,IF3 Update Data" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x144++0x3 line.long 0x0 "DCAN_IF3MSK,IF3 Mask Register" hexmask.long 0x0 0.--28. 1. " MSK ,Identifier Mask" bitfld.long 0x0 29. " RESERVED ,These bits are always read as 1. Writes have no effect." "0,1" textline " " bitfld.long 0x0 30. " MDIR ,Mask Message Direction" "0,1" bitfld.long 0x0 31. " MXTD ,Mask Extended IdentifierWhen 11-bit (standard) identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered. ." "0,1" group.byte 0x148++0x3 line.long 0x0 "DCAN_IF3ARB,IF3 Arbitration Register" hexmask.long 0x0 0.--28. 1. " ID ,Message IdentifierID[28:0]: 29-bit Identifier (extended frame) . ID[28:18]: 11-bit Identifier (standard frame) ." bitfld.long 0x0 29. " DIR ,Message Direction" "0,1" textline " " bitfld.long 0x0 30. " XTD ,Extended Identifier" "0,1" bitfld.long 0x0 31. " MSGVAL ,Message ValidThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the. This bit must also be reset before the identifier ID[28:0], the control bits Xtd, Dir or DLC[3:0] are modified, or if the messages object is no longer required. ." "0,1" group.byte 0x14C++0x3 line.long 0x0 "DCAN_IF3MCTL,IF3 Message Control Register" bitfld.long 0x0 0.--3. " DLC ,Data Length Code0-8: Data frame has 0-8 data bits. . 9-15: Data frame has 8 data bytes. . Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " EOB ,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one. ." "0,1" bitfld.long 0x0 8. " TXRQST ,Transmit Request" "0,1" textline " " bitfld.long 0x0 9. " RMTEN ,Remote enable" "0,1" bitfld.long 0x0 10. " RXIE ,Receive Interrupt enable" "0,1" textline " " bitfld.long 0x0 11. " TXIE ,Transmit Interrupt enable" "0,1" bitfld.long 0x0 12. " UMASK ,Use Acceptance MaskIf the UMASK bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one. ." "0,1" textline " " bitfld.long 0x0 13. " INTPND ,Interrupt Pending" "0,1" bitfld.long 0x0 14. " MSGLST ,Message Lost (only valid for message objects with direction = receive)" "0,1" textline " " bitfld.long 0x0 15. " NEWDAT ,New Data" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x150++0x3 line.long 0x0 "DCAN_IF3DATA,IF3 Data A The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first." hexmask.long.byte 0x0 0.--7. 1. " DATA_0 ,Data byte 0" hexmask.long.byte 0x0 8.--15. 1. " DATA_1 ,Data byte 1" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_2 ,Data byte 2" hexmask.long.byte 0x0 24.--31. 1. " DATA_3 ,Data byte 3" group.byte 0x154++0x3 line.long 0x0 "DCAN_IF3DATB,IF3 Data B The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first." hexmask.long.byte 0x0 0.--7. 1. " DATA_4 ,Data byte 4" hexmask.long.byte 0x0 8.--15. 1. " DATA_5 ,Data byte 5" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_6 ,Data byte 6" hexmask.long.byte 0x0 24.--31. 1. " DATA_7 ,Data byte 7" group.byte 0x160++0x3 line.long 0x0 "DCAN_IF3UPD12,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects." hexmask.long 0x0 0.--31. 1. " IF3UPDEN ,IF3 Update Enabled (for 1-32 message objects)" group.byte 0x164++0x3 line.long 0x0 "DCAN_IF3UPD34,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects." hexmask.long 0x0 0.--31. 1. " IF3UPDEN ,IF3 Update Enabled (for 33-64 message objects)" group.byte 0x168++0x3 line.long 0x0 "DCAN_IF3UPD56,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects." hexmask.long 0x0 0.--31. 1. " IF3UPDEN ,IF3 Update Enabled (for 65-96 message objects)" group.byte 0x16C++0x3 line.long 0x0 "DCAN_IF3UPD78,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects." hexmask.long 0x0 0.--31. 1. " IF3UPDEN ,IF3 Update Enabled (for 97-128 message objects)" group.byte 0x1E0++0x3 line.long 0x0 "DCAN_TIOC,TX I/O Control Register The CAN_TX pin of the DCAN module can be used as general purpose IO pin if CAN function is not needed. The values of the IO control registers are only writable if INIT bit of the is set to 1." bitfld.long 0x0 0. " IN ,CAN_TX data inNote: When CAN_TX pin is connected to a CAN transceiver, an external pullup resistor has to be used to ensure that the CAN bus will not be disturbed (e.g. while reset of the DCAN module). ." "0,1" bitfld.long 0x0 1. " OUT ,CAN_TX data out write. This bit is only active when CAN_TX pin is configured to be in GIO mode (FUNC = 0) and configured to be an output pin (DIR = 1). The value of this bit indicates the value to be output to the CAN_TX pin.Forced to 1 if INIT bit of is reset. ." "0,1" textline " " bitfld.long 0x0 2. " DIR ,CAN_TX data direction. This bit controls the direction of the CAN_TX pin when it is configured to be in GIO mode only (FUNC=0)Forced to '1' if INIT bit of is reset. ." "0,1" bitfld.long 0x0 3. " FUNC ,CAN_TX function. This bit changes the function of the CAN_TX pinForced to Tx output of the CAN core, if INIT bit of is reset. ." "0,1" textline " " hexmask.long.word 0x0 4.--15. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." bitfld.long 0x0 16. " OD ,CAN_TX open drain enable. This bit is only active when CAN_TX is configured to be in GIO mode (FUNC=0).Forced to '0' if INIT bit of is reset. ." "0,1" textline " " bitfld.long 0x0 17. " PD ,CAN_TX pull disable. This bit is only active when CAN_TX is configured to be an input." "0,1" bitfld.long 0x0 18. " PU ,CAN_TX pull up/pull down select. This bit is only active when CAN_TX is configured to be an input." "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x1E4++0x3 line.long 0x0 "DCAN_RIOC,RX I/O Control Register The CAN_RX pin of the DCAN_module can be used as general purpose IO pin if CAN function is not needed. The values of the IO control registers are only writable if INIT bit of the is set to 1." bitfld.long 0x0 0. " IN ,CAN_RX data in ." "0,1" bitfld.long 0x0 1. " OUT ,CAN_RX data out write. This bit is only active when CAN_RX pin is configured to be in GIO mode (FUNC = 0) and configured to be an output pin (DIR = 1). The value of this bit indicates the value to be output to the CAN_RX pin. ." "0,1" textline " " bitfld.long 0x0 2. " DIR ,CAN_RX data direction. This bit controls the direction of the CAN_RX pin when it is configured to be in GIO mode only (FUNC=0)Forced to '0' if INIT bit is reset. ." "0,1" bitfld.long 0x0 3. " FUNC ,CAN_RX function. This bit changes the function of the CAN_RX pinForced to '1' if INIT bit of is reset. ." "0,1" textline " " hexmask.long.word 0x0 4.--15. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." bitfld.long 0x0 16. " OD ,CAN_RX open drain enable. This bit is only active when CAN_RX is configured to be in GIO mode (FUNC=0).Forced to '0' if INIT bit of is reset. ." "0,1" textline " " bitfld.long 0x0 17. " PD ,CAN_RX pull disable. This bit is only active when CAN_TX is configured to be an input." "0,1" bitfld.long 0x0 18. " PU ,CAN_RX pull up/pull down select. This bit is only active when CAN_RX is configured to be an input." "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." width 0x0B tree.end tree "DCAN1" base ad:0x4AE3C000 width 15. group.byte 0x0++0x3 line.long 0x0 "DCAN_CTL,DCAN control register NOTE: The Bus-Off recovery sequence (refer to CAN specification) cannot be shortened by setting or resetting INIT bit. If the module goes Bus-Off, it will automatically set the INIT bit and stop all bus activities. When the INIT bit is cleared by the application again, the module will then wait for 129 occurrences of Bus Idle (129 W 11 consecutive recessive bits) before resuming normal operation. At the end of the bus-off recovery sequence, the error counters will be reset. After the INIT bit is reset, each time when a sequence of 11 recessive bits is monitored, a Bit0 error code is written to , enabling the software to check whether the CAN bus is stuck at dominant or continuously disturbed, and to monitor the proceeding of the bus-off recovery sequence." bitfld.long 0x0 0. " INIT ,Initialization" "0,1" bitfld.long 0x0 1. " IE0 ,Interrupt line 0 enable" "0,1" textline " " bitfld.long 0x0 2. " SIE ,Status change interrupt enable" "0,1" bitfld.long 0x0 3. " EIE ,Error interrupt enable" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,This bit is always read as 0. Writes have no effect." "0,1" bitfld.long 0x0 5. " DAR ,Disable automatic retransmission" "0,1" textline " " bitfld.long 0x0 6. " CCE ,Configuration change enable" "0,1" bitfld.long 0x0 7. " TEST ,Test mode enable" "0,1" textline " " bitfld.long 0x0 8. " IDS ,Interruption debug support enable" "0,1" bitfld.long 0x0 9. " ABO ,Auto-Bus-On enable" "0,1" textline " " bitfld.long 0x0 10.--13. " PMD ,Parityon/offOthers: function enabled ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 14. " RESERVED ,This bit is always read as 0. Writes have no effect." "0,1" textline " " bitfld.long 0x0 15. " SWR ,Software reset enable. Note: To execute software reset, the following procedure is necessary:" "0,1" bitfld.long 0x0 16. " INITDBG ,Internal init state while debug access" "0,1" textline " " bitfld.long 0x0 17. " IE1 ,Interrupt line 1 enable" "0,1" bitfld.long 0x0 18. " DE1 ,Enable DMA request line for IF1. Note: A pending DMA request for IF1 remains active until first access to one of the IF1 registers." "0,1" textline " " bitfld.long 0x0 19. " DE2 ,Enable DMA request line for IF2. Note: A pending DMA request for IF2 remains active until first access to one of the IF2 registers." "0,1" bitfld.long 0x0 20. " DE3 ,Enable DMA request line for IF3. Note: A pending DMA request for IF3 remains active until first access to one of the IF3 registers." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. " PDR ,Request for local low power-down mode" "0,1" textline " " bitfld.long 0x0 25. " WUBA ,Automatic wake up on bus activity when in local power-down mode. Note: The CAN message, which initiates the bus activity, cannot be received. This means that the first message received in power down and automatic wake-up mode, will be lost." "0,1" bitfld.long 0x0 26.--31. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x4++0x3 line.long 0x0 "DCAN_ES,Error and Status Register Interrupts are generated by bits PER, BOFF and EWARN (if EIE bit in is 1) and by bits WAKEUPPND, RXOK, TXOK, and LEC (if SIE bit in is 1). A change of bit EPASS will not generate an interrupt. Reading the clears the WAKEUPPND, PER, RXOK and TXOK bits and set the LEC to value '7.' Additionally, the status interrupt value (0x8000) in the will be replaced by the next lower priority interrupt value. For debug support, the auto clear functionality of (clear of status flags by read) is disabled when in debug/suspend mode." bitfld.long 0x0 0.--2. " LEC ,Last error code. The LEC field indicates the type of the last error on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " TXOK ,Transmitted a message successfully. This bit will be reset ifDCAN_ES register is read. ." "0,1" textline " " bitfld.long 0x0 4. " RXOK ,Received a message successfully. This bit will be reset ifDCAN_ES register is read. ." "0,1" bitfld.long 0x0 5. " EPASS ,Error passive state" "0,1" textline " " bitfld.long 0x0 6. " EWARN ,Warning state" "0,1" bitfld.long 0x0 7. " BOFF ,Bus-Off state" "0,1" textline " " bitfld.long 0x0 8. " PER ,Parity error detected. This bit will be reset ifDCAN_ES register is read." "0,1" bitfld.long 0x0 9. " WAKEUPPND ,Wake up pending. This bit can be used by the software to identify the DCAN as the source to wake up the system. This bit will be reset ifDCAN_ES is read. ." "0,1" textline " " bitfld.long 0x0 10. " PDA ,Local power-down mode acknowledge" "0,1" hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x8++0x3 line.long 0x0 "DCAN_ERRC,Error Counter Register" hexmask.long.byte 0x0 0.--7. 1. " TEC ,Transmit error counter. Actual state of the transmit error counter" hexmask.long.byte 0x0 8.--14. 1. " REC ,Receive error counter. Actual state of the receive error counter" textline " " bitfld.long 0x0 15. " RP ,Receive error passive" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0xC++0x3 line.long 0x0 "DCAN_BTR,Bit timing register This register is only writable if CCE and INIT bits in the are set. The CAN bit time may be programmed in the range of 8 to 25 time quanta The CAN time quantum may be programmed in the range of 1 to 1024 CAN_CLK periods." bitfld.long 0x0 0.--5. " BRP ,Baud rate prescalerValue by which the CAN_CLK frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. . Valid programmed values are 0 to 63. . The actual BRP value interpreted for the bit timing will be the programmed BRP value + 1. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " SJW ,Synchronization Jump WidthValid programmed values are 0 to 3. . The actual SJW value interpreted for the synchronization will be the programmed SJW value + 1. ." "0,1,2,3" textline " " bitfld.long 0x0 8.--11. " TSEG1 ,Time segment before the sample pointValid programmed values are 1 to15. . The actual TSeg1 value interpreted for the bit timing will be the programmed TSeg1 value + 1. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--14. " TSEG2 ,Time segment after the sample pointValid programmed values are 0 to 7. . The actual TSeg2 value which is interpreted for the bit timing will be the programmed TSeg2 value + 1. ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1" bitfld.long 0x0 16.--19. " BRPE ,Baud rate prescaler extension.Valid programmed values are 0 to 15. . By programming BRPE the baud rate prescaler can be extended to values up to 1024. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x10++0x3 line.long 0x0 "DCAN_INT,Interrupt register" hexmask.long.word 0x0 0.--15. 1. " INT0ID ,Interrupt Identifier (the number here indicates the source of the interrupt)0x0001-0x0080: Number of message object which caused the interrupt. . 0x0081-0x7FFF: Unused . 0x8001-0xFFFF: Unused . If several interrupts are pending,DCAN_INTwill point to the pending interrupt with the highest priority. The INT0 interrupt line remains active until INT0ID reaches value 0 (the cause of the interrupt is reset) or until IE0 is cleared. . The Status interrupt has the highest priority. Among the message interrupts, the message object's interrupt priority decreases with increasing message number. ." hexmask.long.byte 0x0 16.--23. 1. " INT1ID ,Interrupt 1 Identifier (indicates the message object with the highest pending interrupt)0x01-0x80: Number of message object which caused the interrupt. . 0x81-0xFF: Unused . If several interrupts are pending, will point to the pending interrupt with the highest priority. The INT1 interrupt line remains active until INT1ID reaches value 0 (the cause of the interrupt is reset) or until IE1 is cleared. . A message interrupt is cleared by clearing the message object's IntPnd bit. . Among the message interrupts, the message object's interrupt priority decreases with increasing message number. ." textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x14++0x3 line.long 0x0 "DCAN_TEST,Test Register For all test modes, the TEST bit in control register needs to be set to 1. If TEST bit is set, the RDA, EXL, TX1, TX0, LBACK and SILENT bits are writable. Bit RX monitors the state of pin CAN_RX and therefore is only readable. All test register functions are disabled when TEST bit is cleared." bitfld.long 0x0 0.--2. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " SILENT ,Silent mode" "0,1" textline " " bitfld.long 0x0 4. " LBACK ,Loopback mode. When the internal loop-back mode is active (bit LBACK is set), bit EXL will be ignored." "0,1" bitfld.long 0x0 5.--6. " TX ,Control of CAN_TX pin. Setting Tx[1:0] other than '00' will disturb message transfer." "0,1,2,3" textline " " bitfld.long 0x0 7. " RX ,Receive pin. Monitors the actual value of the CAN_RX pin" "0,1" bitfld.long 0x0 8. " EXL ,External loopback mode. When the internal loop-back mode is active (bit LBACK is set), bit EXL will be ignored." "0,1" textline " " bitfld.long 0x0 9. " RDA ,RAM direct access enable" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x1C++0x3 line.long 0x0 "DCAN_PERR,Parity Error Code Register If a parity error is detected, the PER flag will be set in the . This bit is not reset by the parity check mechanism; it must be reset by reading . In addition to the PER flag, the parity error code register will indicate the memory area where the parity error has been detected (message number and word number). If more than one word with a parity error was detected, the highest word number with a parity error will be displayed. After a parity error has been detected, the register will hold the last error code until power is removed." hexmask.long.byte 0x0 0.--7. 1. " MESSAGE_NUMBER ,Message object number where parity error has been detected (0x01-0x80)" bitfld.long 0x0 8.--10. " WORD_NUMBER ,Word number where parity error has been detectedRDA word number (1 to 5) of the message object (according to the message RAM representation in RDA mode). ." "0,1,2,3,4,5,6,7" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x20++0x3 line.long 0x0 "DCAN_REL,Core revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,DCAN core revision number" group.byte 0x80++0x3 line.long 0x0 "DCAN_ABOTR,Auto-Bus-On Time Register On write access to the while Auto-Bus-On timer is running, the Auto-Bus-On procedure will be aborted. During Debug/Suspend mode, running Auto-Bus-On timer will be paused." hexmask.long 0x0 0.--31. 1. " ABO_TIME ,Number of OCP clock cycles before a Bus-Off recovery sequence is started by clearing the INIT bit. This function has to be enabled by setting bit ABO inDCAN_CTL. The Auto-Bus-On timer is realized by a 32-bit counter which starts to count down to zero when the module goes Bus-Off. The counter will be reloaded with the preload value of the DCAN_ABOTR after this phase." group.byte 0x84++0x3 line.long 0x0 "DCAN_TXRQ_X,Transmission Request X Register The software can detect if one or more bits in the different transmission request registers are set. Each register bit represents a group of eight message objects. If at least one of the TxRqst bits of these message objects are set, the corresponding bit in the transmission request X register will be set." bitfld.long 0x0 0.--1. " TXRQSTREG1 ,Transmission request bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 2.--3. " TXRQSTREG2 ,Transmission request bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " TXRQSTREG3 ,Transmission request bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 6.--7. " TXRQSTREG4 ,Transmission request bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " TXRQSTREG5 ,Transmission request bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 10.--11. " TXRQSTREG6 ,Transmission request bits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " TXRQSTREG7 ,Transmission request bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 14.--15. " TXRQSTREG8 ,Transmission request bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,RESERVED" group.byte 0x88++0x3 line.long 0x0 "DCAN_TXRQ12,Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " TXRQS ,Transmission request bits (for 1-32 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done." group.byte 0x8C++0x3 line.long 0x0 "DCAN_TXRQ34,Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " TXRQS ,Transmission request bits (for 33-64 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done." group.byte 0x90++0x3 line.long 0x0 "DCAN_TXRQ56,Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " TXRQS ,Transmission request bits (for 65-96 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done." group.byte 0x94++0x3 line.long 0x0 "DCAN_TXRQ78,Transmission Request Register This register holds the TxRqst bits of the implemented message objects. By reading out these bits, the software can check for pending transmission requests. The TxRqst bit in a specific message object can be set/reset by the software via the IF1/IF2 message interface registers, or by the message handler after reception of a remote frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " TXRQS ,Transmission request bits (for 97-128 message objects) 0: No transmission has been requested for this message object. 1: The transmission of this message object is requested and is not yet done." group.byte 0x98++0x3 line.long 0x0 "DCAN_NWDAT_X,New Data X Register With the new data X register, the software can detect if one or more bits in the different new data registers are set. Each register bit represents a group of eight message objects. If at least on of the NewDat bits of these message objects are set, the corresponding bit in the new data X register will be set" bitfld.long 0x0 0.--1. " NEWDATREG1 ,New data bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 2.--3. " NEWDATREG2 ,New data bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " NEWDATREG3 ,New data bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 6.--7. " NEWDATREG4 ,New data bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " NEWDATREG5 ,New data bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 10.--11. " NEWDATREG6 ,New data bits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " NEWDATREG7 ,New data bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 14.--15. " NEWDATREG8 ,New data bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x9C++0x3 line.long 0x0 "DCAN_NWDAT12,New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " NEWDAT ,New Data Bits (for 1-32 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object." group.byte 0xA0++0x3 line.long 0x0 "DCAN_NWDAT34,New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " NEWDAT ,New Data Bits (for 33-64 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object." group.byte 0xA4++0x3 line.long 0x0 "DCAN_NWDAT56,New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " NEWDAT ,New Data Bits (for 65-96 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object." group.byte 0xA8++0x3 line.long 0x0 "DCAN_NWDAT78,New Data Register This register hold the NewDat bits of the implemented message objects. By reading out these bits, the software can check for new data in the message objects. The NewDat bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after reception of a data frame or after a successful transmission." hexmask.long 0x0 0.--31. 1. " NEWDAT ,New Data Bits (for 97-128 message objects) 0: No new data has been written into the data portion of this message object by the Message Handler since the last time when this flag was cleared by the software. 1: The Message Handler or the software has written new data into the data portion of this message object." group.byte 0xAC++0x3 line.long 0x0 "DCAN_INTPND_X,Interrupt Pending X Register With the interrupt pending X register, the software can detect if one or more bits in the different interrupt pending registers are set. Each bit of this register represents a group of eight message objects. If at least one of the IntPnd bits of these message objects are set, the corresponding bit in the interrupt pending X register will be set." bitfld.long 0x0 0.--1. " INTPNDREG1 ,Interrupt Pending bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 2.--3. " INTPNDREG2 ,Interrupt Pending bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " INTPNDREG3 ,Interrupt Pending bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 6.--7. " INTPNDREG4 ,Interrupt Pending bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " INTPNDREG5 ,Interrupt Pending bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 10.--11. " INTPNDREG6 ,Interrupt Pendingbits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " INTPNDREG7 ,Interrupt Pending bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 14.--15. " INTPNDREG8 ,Interrupt Pending bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xB0++0x3 line.long 0x0 "DCAN_INTPND12,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission." hexmask.long 0x0 0.--31. 1. " INTPND ,Interrupt Pending Bits (for 1-32 message objects)" group.byte 0xB4++0x3 line.long 0x0 "DCAN_INTPND34,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission." hexmask.long 0x0 0.--31. 1. " INTPND ,Interrupt Pending Bits (for 33-64 message objects)" group.byte 0xB8++0x3 line.long 0x0 "DCAN_INTPND56,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission." hexmask.long 0x0 0.--31. 1. " INTPND ,Interrupt Pending Bits (for 65-96 message objects)" group.byte 0xBC++0x3 line.long 0x0 "DCAN_INTPND78,Interrupt Pending Register This register holds the IntPnd bits of the implemented message objects. By reading out these bits, the software can check for pending interrupts in the message objects. The IntPnd bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission." hexmask.long 0x0 0.--31. 1. " INTPND ,Interrupt Pending Bits (for 97-128 message objects)" group.byte 0xC0++0x3 line.long 0x0 "DCAN_MSGVAL_X,Message Valid X Register With the message valid X register, the software can detect if one or more bits in the different message valid registers are set. Each bit of this register represents a group of eight message objects. If at least one of the MsgVal bits of these message objects are set, the corresponding bit in the message valid X register will be set." bitfld.long 0x0 0.--1. " MSGVALREG1 ,Message valid bits (aggregate for 1-16 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 2.--3. " MSGVALREG2 ,Message valid bits (aggregate for 17-32 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " MSGVALREG3 ,Message valid bits (aggregate for 33-48 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 6.--7. " MSGVALREG4 ,Message valid bits (aggregate for 49-64 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " MSGVALREG5 ,Message valid bits (aggregate for 65-80 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 10.--11. " MSGVALREG6 ,Message valid bits (aggregate for 81-96 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " MSGVALREG7 ,Message valid bits (aggregate for 97-112 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" bitfld.long 0x0 14.--15. " MSGVALREG8 ,Message valid bits (aggregate for 113-128 message objects). Lower bit represents first 8 message objects. Higher bit represents second 8 message objects." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0xC4++0x3 line.long 0x0 "DCAN_MSGVAL12,Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission" hexmask.long 0x0 0.--31. 1. " MSGVAL ,Message valid Bits (for 1-32 message objects)" group.byte 0xC8++0x3 line.long 0x0 "DCAN_MSGVAL34,Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission" hexmask.long 0x0 0.--31. 1. " MSGVAL ,Message valid Bits (for 33-64 message objects)" group.byte 0xCC++0x3 line.long 0x0 "DCAN_MSGVAL56,Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission" hexmask.long 0x0 0.--31. 1. " MSGVAL ,Message valid Bits (for 65-96 message objects)" group.byte 0xD0++0x3 line.long 0x0 "DCAN_MSGVAL78,Message Valid Register These registers hold the MsgVal bits of the implemented message objects. By reading out these bits, the software can check which message objects are valid. The MsgVal bit of a specific message object can be set/reset by the software via the IF1/IF2 interface register sets, or by the message handler after a reception or a successful transmission" hexmask.long 0x0 0.--31. 1. " MSGVAL ,Message valid Bits (for 97-128 message objects)" group.byte 0xD8++0x3 line.long 0x0 "DCAN_INTMUX12,Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in . The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp. INT1ID flags in the register." hexmask.long 0x0 0.--31. 1. " INTMUX ,Multiplexes IntPnd value to either INT0 or INT1 interrupt lines (bit 0 -> last implemented message object) ( bits 1:31 -> 1-31 message objects)" group.byte 0xDC++0x3 line.long 0x0 "DCAN_INTMUX34,Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN control register. The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp INT1ID flags in the register." hexmask.long 0x0 0.--31. 1. " INTMUX ,Multiplexes IntPnd value to either INT0 or INT1 interrupt lines ( bits 0:31 -> 32-63 message objects)" group.byte 0xE0++0x3 line.long 0x0 "DCAN_INTMUX56,Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN control register. The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp INT1ID flags in the register." hexmask.long 0x0 0.--31. 1. " INTMUX ,Multiplexes IntPnd value to either INT0 or INT1 interrupt lines ( bits 0:31 -> 64-95 message objects)" group.byte 0xE4++0x3 line.long 0x0 "DCAN_INTMUX78,Interrupt Multiplexer Register The IntMux flag determine for each message object, which of the two interrupt lines (INT0 or INT1) will be asserted when the IntPnd of this message object is set. Both interrupt lines can be globally enabled or disabled by setting or clearing IE0 and IE1 bits in CAN control register. The IntPnd bit of a specific message object can be set or reset by the software via the IF1/IF2 interface register sets, or by message handler after reception or successful transmission of a frame. This will also affect the INT0ID resp INT1ID flags in the register." hexmask.long 0x0 0.--31. 1. " INTMUX ,Multiplexes IntPnd value to either INT0 or INT1 interrupt lines ( bits 0:31 -> 96-127 message objects)" group.byte 0x100++0x3 line.long 0x0 "DCAN_IF1CMD,IF1 Command Register The IF1 Command Register () configure and initiate the transfer between the IF1 register set and the message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the software writes the message number to bits [7:0] MESSAGE_NUMBER. With this write operation, the BUSY bit is automatically set to 1 to indicate that a transfer is in progress. After 4 to 14 OCP clock cycles, the transfer between the interface register and the message RAM will be completed and the BUSY bit is cleared. The maximum number of cycles is needed when the message transfer concurs with a CAN message transmission, acceptance filtering, or message storage. If the software writes to both / consecutively (request of a second transfer while first transfer is still in progress), the second transfer will start after the first one has been completed. While BUSY bit is one, IF1/IF2 register sets are write protected. For debug support, the auto clear functionality of the IF1/IF2 command registers (clear of DMAACTIVE flag by r/w) is disabled during Debug/Suspend mode. If an invalid Message Number is written to bits [7:0] MESSAGE_NUMBER, the message handler may access an implemented (valid) message object instead." hexmask.long.byte 0x0 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers . 0x81-0xFF: Invalid message numbers ." bitfld.long 0x0 8.--13. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF1 updateThe DMA request remains active until the first read or write to one of the IF1 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one. . Note: Due to the auto reset feature of the DMAACTIVE bit, this bit has to be set for each subsequent DMA cycle separately. ." "0,1" bitfld.long 0x0 15. " BUSY ,Busy flagThis bit is set to one after the message number has been written to bits [7:0] MESSAGE_NUMBER. IF1 register set will be write protected. The bit is cleared after read/write action has been finished. ." "0,1" textline " " bitfld.long 0x0 16. " DATA_B ,Access Data Bytes 4-7Note: The duration of the message transfer is independent of the number of bytes to be transferred. ." "0,1" bitfld.long 0x0 17. " DATA_A ,Access Data Bytes 0-3Note: The duration of the message transfer is independent of the number of bytes to be transferred. ." "0,1" textline " " bitfld.long 0x0 18. " TXRQST_NEWDAT ,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register, the TxRqst/NewDat bits in the message object will be set to one independent of the values in. . Note: A read access to a message object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the always reflect the status before resetting them. ." "0,1" bitfld.long 0x0 19. " CLRINTPND ,Clear interrupt pending bit" "0,1" textline " " bitfld.long 0x0 20. " CONTROL ,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set, the TXRQST/ NEWDAT bits in the will be ignored. ." "0,1" bitfld.long 0x0 21. " ARB ,Access arbitration bits" "0,1" textline " " bitfld.long 0x0 22. " MASK ,Access mask bits" "0,1" bitfld.long 0x0 23. " WR_RD ,Write/Read" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x104++0x3 line.long 0x0 "DCAN_IF1MSK,IF1 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long 0x0 0.--28. 1. " MSK ,Identifier Mask" bitfld.long 0x0 29. " RESERVED ,This bit is always read as 1. Writes have no effect." "0,1" textline " " bitfld.long 0x0 30. " MDIR ,Mask Message Direction" "0,1" bitfld.long 0x0 31. " MXTD ,Mask Extended IdentifierWhen 11-bit (standard) identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered. ." "0,1" group.byte 0x108++0x3 line.long 0x0 "DCAN_IF1ARB,IF1 arbitration register The Arbitration bits ID[28:0], XTD, and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0], MXTD, and MDIR) for acceptance filtering of incoming messages. A received message is stored into the valid message object with matching identifier and Direction = receive (data frame) or Direction = transmit (remote frame). Extended frames can be stored only in message objects with XTD = 1, standard frames in message objects with XTD = 0. If a received message (data frame or remote frame) matches more than one valid message objects, it is stored into the one with the lowest message number. The bits of the IF1/IF2 arbitration registers mirror the arbitration bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long 0x0 0.--28. 1. " ID ,Message identifierID[28:0]: 29-bit identifier (extended frame) . ID[28:18]: 11-bit identifier (standard frame) ." bitfld.long 0x0 29. " DIR ,Message direction" "0,1" textline " " bitfld.long 0x0 30. " XTD ,Extended identifier" "0,1" bitfld.long 0x0 31. " MSGVAL ,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the. This bit must also be reset if the messages object is no longer required. ." "0,1" group.byte 0x10C++0x3 line.long 0x0 "DCAN_IF1MCTL,IF1 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects While BUSY bit of / register is one, IF1/IF2 register set is write protected." bitfld.long 0x0 0.--3. " DLC ,Data length code0-8: Data frame has 0-8 data bytes. . 9-15 Data frame has 8 data bytes. . Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " EOB ,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to 1. ." "0,1" bitfld.long 0x0 8. " TXRQST ,Transmit request" "0,1" textline " " bitfld.long 0x0 9. " RMTEN ,Remote enable" "0,1" bitfld.long 0x0 10. " RXIE ,Receive interrupt enable" "0,1" textline " " bitfld.long 0x0 11. " TXIE ,Transmit interrupt enable" "0,1" bitfld.long 0x0 12. " UMASK ,Use acceptance maskIf the UMASK bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one. ." "0,1" textline " " bitfld.long 0x0 13. " INTPND ,Interrupt pending" "0,1" bitfld.long 0x0 14. " MSGLST ,Message lost (only valid for message objects with direction = receive)" "0,1" textline " " bitfld.long 0x0 15. " NEWDAT ,New data" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x110++0x3 line.long 0x0 "DCAN_IF1DATA,IF1 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long.byte 0x0 0.--7. 1. " DATA_0 ,Data byte 0" hexmask.long.byte 0x0 8.--15. 1. " DATA_1 ,Data byte 1" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_2 ,Data byte 2" hexmask.long.byte 0x0 24.--31. 1. " DATA_3 ,Data byte 3" group.byte 0x114++0x3 line.long 0x0 "DCAN_IF1DATB,IF1 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long.byte 0x0 0.--7. 1. " DATA_4 ,Data byte 4" hexmask.long.byte 0x0 8.--15. 1. " DATA_5 ,Data byte 5" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_6 ,Data byte 6" hexmask.long.byte 0x0 24.--31. 1. " DATA_7 ,Data byte 7" group.byte 0x120++0x3 line.long 0x0 "DCAN_IF2CMD,IF2 Command Register The IF2 Command Register () configure and initiate the transfer between the IF2 register set and the message RAM. It is configurable which portions of the message object should be transferred. A transfer is started when the software writes the message number to bits [7:0] MESSAGE_NUMBER. With this write operation, the BUSY bit is automatically set to 1 to indicate that a transfer is in progress. After 4 to 14 OCP clock cycles, the transfer between the interface register and the message RAM will be completed and the BUSY bit is cleared. The maximum number of cycles is needed when the message transfer concurs with a CAN message transmission, acceptance filtering, or message storage. If the software writes to both / consecutively (request of a second transfer while first transfer is still in progress), the second transfer will start after the first one has been completed. While BUSY bit is one, IF1/IF2 register sets are write protected. For debug support, the auto clear functionality of the IF1/IF2 command registers (clear of DMAACTIVE flag by r/w) is disabled during Debug/Suspend mode. If an invalid Message Number is written to bits [7:0] MESSAGE_NUMBER, the message handler may access an implemented (valid) message object instead." hexmask.long.byte 0x0 0.--7. 1. " MESSAGE_NUMBER ,Number of message object in message RAM which is used for data transfer0x01-0x80: Valid message numbers . 0x81-0xFF: Invalid message numbers ." bitfld.long 0x0 8.--13. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 14. " DMAACTIVE ,Activation of DMA feature for subsequent internal IF2 updateThe DMA request remains active until the first read or write to one of the IF2 registers; an exception is a write to MESSAGE_NUMBER when DMAACTIVE is one. . Note: Due to the auto reset feature of the DMAACTIVE bit, this bit has to be set for each subsequent DMA cycle separately. ." "0,1" bitfld.long 0x0 15. " BUSY ,Busy flagThis bit is set to one after the message number has been written to bits [7:0] MESSAGE_NUMBER. IF2 register set will be write protected. The bit is cleared after read/write action has been finished. ." "0,1" textline " " bitfld.long 0x0 16. " DATA_B ,Access Data Bytes 4-7Note: The duration of the message transfer is independent of the number of bytes to be transferred. ." "0,1" bitfld.long 0x0 17. " DATA_A ,Access Data Bytes 0-3Note: The duration of the message transfer is independent of the number of bytes to be transferred. ." "0,1" textline " " bitfld.long 0x0 18. " TXRQST_NEWDAT ,Access transmission request bitNote: If a CAN transmission is requested by setting TXRQST_NEWDAT in this register, the TxRqst/NewDat bits in the message object will be set to one independent of the values in/. . Note: A read access to a message object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the/ always reflect the status before resetting them. ." "0,1" bitfld.long 0x0 19. " CLRINTPND ,Clear interrupt pending bit" "0,1" textline " " bitfld.long 0x0 20. " CONTROL ,Access control bitsIf the TXRQST_NEWDAT bit in this register(Bit [18]) is set, the TXRQST/ NEWDAT bits in the/ will be ignored. ." "0,1" bitfld.long 0x0 21. " ARB ,Access arbitration bits" "0,1" textline " " bitfld.long 0x0 22. " MASK ,Access mask bits" "0,1" bitfld.long 0x0 23. " WR_RD ,Write/Read" "0,1" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x124++0x3 line.long 0x0 "DCAN_IF2MSK,IF2 Mask Register The bits of the IF1/IF2 mask registers mirror the mask bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long 0x0 0.--28. 1. " MSK ,Identifier Mask" bitfld.long 0x0 29. " RESERVED ,This bit is always read as 1. Writes have no effect." "0,1" textline " " bitfld.long 0x0 30. " MDIR ,Mask Message Direction" "0,1" bitfld.long 0x0 31. " MXTD ,Mask Extended IdentifierWhen 11-bit (standard) identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered. ." "0,1" group.byte 0x128++0x3 line.long 0x0 "DCAN_IF2ARB,IF2 arbitration register The Arbitration bits ID[28:0], XTD, and DIR are used to define the identifier and type of outgoing messages and (together with the mask bits MSK[28:0], MXTD, and MDIR) for acceptance filtering of incoming messages. A received message is stored into the valid message object with matching identifier and Direction = receive (data frame) or Direction = transmit (remote frame). Extended frames can be stored only in message objects with Xtd = 1, standard frames in message objects with Xtd = 0. If a received message (data frame or remote frame) matches more than one valid message objects, it is stored into the one with the lowest message number. The bits of the IF1/IF2 arbitration registers mirror the arbitration bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long 0x0 0.--28. 1. " ID ,Message identifierID[28:0]: 29-bit identifier (extended frame) . ID[28:18]: 11-bit identifier (standard frame) ." bitfld.long 0x0 29. " DIR ,Message direction" "0,1" textline " " bitfld.long 0x0 30. " XTD ,Extended identifier" "0,1" bitfld.long 0x0 31. " MSGVAL ,Message validThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the. This bit must also be reset if the messages object is no longer required. ." "0,1" group.byte 0x12C++0x3 line.long 0x0 "DCAN_IF2MCTL,IF2 Message Control Register The bits of the IF1/IF2 message control registers mirror the message control bits of a message object. The function of the relevant message objects bits is described in Structure of Message Objects While BUSY bit of / register is one, IF1/IF2 register set is write protected." bitfld.long 0x0 0.--3. " DLC ,Data length code0-8: Data frame has 0-8 data bytes. . 9-15 Data frame has 8 data bytes. . Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " EOB ,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one. ." "0,1" bitfld.long 0x0 8. " TXRQST ,Transmit request" "0,1" textline " " bitfld.long 0x0 9. " RMTEN ,Remote enable" "0,1" bitfld.long 0x0 10. " RXIE ,Receive interrupt enable" "0,1" textline " " bitfld.long 0x0 11. " TXIE ,Transmit interrupt enable" "0,1" bitfld.long 0x0 12. " UMASK ,Use acceptance maskIf the UMask bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one. ." "0,1" textline " " bitfld.long 0x0 13. " INTPND ,Interrupt pending" "0,1" bitfld.long 0x0 14. " MSGLST ,Message lost (only valid for message objects with direction = receive)" "0,1" textline " " bitfld.long 0x0 15. " NEWDAT ,New data" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x130++0x3 line.long 0x0 "DCAN_IF2DATA,IF2 Data A Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long.byte 0x0 0.--7. 1. " DATA_0 ,Data byte 0" hexmask.long.byte 0x0 8.--15. 1. " DATA_1 ,Data byte 1" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_2 ,Data byte 2" hexmask.long.byte 0x0 24.--31. 1. " DATA_3 ,Data byte 3" group.byte 0x134++0x3 line.long 0x0 "DCAN_IF2DATB,IF2 Data B Register The data bytes of CAN messages are stored in the IF1/IF2 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first. While BUSY bit of / register is one, IF1/IF2 register set is write protected." hexmask.long.byte 0x0 0.--7. 1. " DATA_4 ,Data byte 4" hexmask.long.byte 0x0 8.--15. 1. " DATA_5 ,Data byte 5" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_6 ,Data byte 6" hexmask.long.byte 0x0 24.--31. 1. " DATA_7 ,Data byte 7" group.byte 0x140++0x3 line.long 0x0 "DCAN_IF3OBS,IF3 Observation Register The IF3 register set can automatically be updated with received message objects without the need to initiate the transfer from message RAM by software (Additional information can be found in NOTE: If IF3 Update Enable is used and no Observation flag is set, the corresponding message objects will be copied to IF3 without activating the DMA request line and without waiting for DMA read accesses. A write access to this register aborts a pending DMA cycle by resetting the DMA line and enables updating of IF3 interface register set with new data. To avoid data inconsistency, the DMA controller should be disabled before reconfiguring IF3 observation register. The status of the current read-cycle can be observed via status flags (Bits [12:8])." bitfld.long 0x0 0. " MASK ,Mask data read observation" "0,1" bitfld.long 0x0 1. " ARB ,Arbitration data read observation" "0,1" textline " " bitfld.long 0x0 2. " CTRL ,Ctrl read observation" "0,1" bitfld.long 0x0 3. " DATAA ,Data A read observation" "0,1" textline " " bitfld.long 0x0 4. " DATAB ,Data B read observation" "0,1" bitfld.long 0x0 5.--7. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " IF3_SM ,IF3 Status of Mask data read access" "0,1" bitfld.long 0x0 9. " IF3_SA ,IF3 Status of Arbitration data read access" "0,1" textline " " bitfld.long 0x0 10. " IF3_SC ,IF3 Status of control bits read access" "0,1" bitfld.long 0x0 11. " IF3_SDA ,IF3 Status of Data A read access" "0,1" textline " " bitfld.long 0x0 12. " IF3_SDB ,IF3 Status of Data B read access" "0,1" bitfld.long 0x0 13.--14. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3" textline " " bitfld.long 0x0 15. " IF3_UPD ,IF3 Update Data" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x144++0x3 line.long 0x0 "DCAN_IF3MSK,IF3 Mask Register" hexmask.long 0x0 0.--28. 1. " MSK ,Identifier Mask" bitfld.long 0x0 29. " RESERVED ,These bits are always read as 1. Writes have no effect." "0,1" textline " " bitfld.long 0x0 30. " MDIR ,Mask Message Direction" "0,1" bitfld.long 0x0 31. " MXTD ,Mask Extended IdentifierWhen 11-bit (standard) identifiers are used for a message object, the identifiers of received data frames are written into bits ID[28:18]. For acceptance filtering, only these bits together with mask bits Msk[28:18] are considered. ." "0,1" group.byte 0x148++0x3 line.long 0x0 "DCAN_IF3ARB,IF3 Arbitration Register" hexmask.long 0x0 0.--28. 1. " ID ,Message IdentifierID[28:0]: 29-bit Identifier (extended frame) . ID[28:18]: 11-bit Identifier (standard frame) ." bitfld.long 0x0 29. " DIR ,Message Direction" "0,1" textline " " bitfld.long 0x0 30. " XTD ,Extended Identifier" "0,1" bitfld.long 0x0 31. " MSGVAL ,Message ValidThe software should reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit INIT in the. This bit must also be reset before the identifier ID[28:0], the control bits Xtd, Dir or DLC[3:0] are modified, or if the messages object is no longer required. ." "0,1" group.byte 0x14C++0x3 line.long 0x0 "DCAN_IF3MCTL,IF3 Message Control Register" bitfld.long 0x0 0.--3. " DLC ,Data Length Code0-8: Data frame has 0-8 data bits. . 9-15: Data frame has 8 data bytes. . Note: The data length code of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the message handler stores a data frame, it will write the DLC to the value given by the received message. ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " RESERVED ,These bits are always read as 0. Writes have no effect." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " EOB ,End of BlockNote: This bit is used to concatenate multiple message objects to build a FIFO Buffer. For single message objects (not belonging to a FIFO Buffer), this bit must always be set to one. ." "0,1" bitfld.long 0x0 8. " TXRQST ,Transmit Request" "0,1" textline " " bitfld.long 0x0 9. " RMTEN ,Remote enable" "0,1" bitfld.long 0x0 10. " RXIE ,Receive Interrupt enable" "0,1" textline " " bitfld.long 0x0 11. " TXIE ,Transmit Interrupt enable" "0,1" bitfld.long 0x0 12. " UMASK ,Use Acceptance MaskIf the UMASK bit is set to one, the message object's mask bits have to be programmed during initialization of the message object before MsgVal is set to one. ." "0,1" textline " " bitfld.long 0x0 13. " INTPND ,Interrupt Pending" "0,1" bitfld.long 0x0 14. " MSGLST ,Message Lost (only valid for message objects with direction = receive)" "0,1" textline " " bitfld.long 0x0 15. " NEWDAT ,New Data" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x150++0x3 line.long 0x0 "DCAN_IF3DATA,IF3 Data A The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first." hexmask.long.byte 0x0 0.--7. 1. " DATA_0 ,Data byte 0" hexmask.long.byte 0x0 8.--15. 1. " DATA_1 ,Data byte 1" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_2 ,Data byte 2" hexmask.long.byte 0x0 24.--31. 1. " DATA_3 ,Data byte 3" group.byte 0x154++0x3 line.long 0x0 "DCAN_IF3DATB,IF3 Data B The data bytes of CAN messages are stored in the IF3 registers in the following order: In a CAN data frame, Data 0 is the first, and Data 7 is the last byte to be transmitted or received. In CAN's serial bit stream, the MSB of each byte will be transmitted first." hexmask.long.byte 0x0 0.--7. 1. " DATA_4 ,Data byte 4" hexmask.long.byte 0x0 8.--15. 1. " DATA_5 ,Data byte 5" textline " " hexmask.long.byte 0x0 16.--23. 1. " DATA_6 ,Data byte 6" hexmask.long.byte 0x0 24.--31. 1. " DATA_7 ,Data byte 7" group.byte 0x160++0x3 line.long 0x0 "DCAN_IF3UPD12,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects." hexmask.long 0x0 0.--31. 1. " IF3UPDEN ,IF3 Update Enabled (for 1-32 message objects)" group.byte 0x164++0x3 line.long 0x0 "DCAN_IF3UPD34,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects." hexmask.long 0x0 0.--31. 1. " IF3UPDEN ,IF3 Update Enabled (for 33-64 message objects)" group.byte 0x168++0x3 line.long 0x0 "DCAN_IF3UPD56,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects." hexmask.long 0x0 0.--31. 1. " IF3UPDEN ,IF3 Update Enabled (for 65-96 message objects)" group.byte 0x16C++0x3 line.long 0x0 "DCAN_IF3UPD78,Update Enable Register The automatic update functionality of the IF3 register set can be configured for each message object. A message object is enabled for automatic IF3 update, if the dedicated IF3UPDEN flag is set. This means that an active NewDat flag of this message object (e.g due to reception of a CAN frame) will trigger an automatic copy of the whole message object to IF3 register set NOTE: IF3 Update enable should not be set for transmit objects." hexmask.long 0x0 0.--31. 1. " IF3UPDEN ,IF3 Update Enabled (for 97-128 message objects)" group.byte 0x1E0++0x3 line.long 0x0 "DCAN_TIOC,TX I/O Control Register The CAN_TX pin of the DCAN module can be used as general purpose IO pin if CAN function is not needed. The values of the IO control registers are only writable if INIT bit of the is set to 1." bitfld.long 0x0 0. " IN ,CAN_TX data inNote: When CAN_TX pin is connected to a CAN transceiver, an external pullup resistor has to be used to ensure that the CAN bus will not be disturbed (e.g. while reset of the DCAN module). ." "0,1" bitfld.long 0x0 1. " OUT ,CAN_TX data out write. This bit is only active when CAN_TX pin is configured to be in GIO mode (FUNC = 0) and configured to be an output pin (DIR = 1). The value of this bit indicates the value to be output to the CAN_TX pin.Forced to 1 if INIT bit of is reset. ." "0,1" textline " " bitfld.long 0x0 2. " DIR ,CAN_TX data direction. This bit controls the direction of the CAN_TX pin when it is configured to be in GIO mode only (FUNC=0)Forced to '1' if INIT bit of is reset. ." "0,1" bitfld.long 0x0 3. " FUNC ,CAN_TX function. This bit changes the function of the CAN_TX pinForced to Tx output of the CAN core, if INIT bit of is reset. ." "0,1" textline " " hexmask.long.word 0x0 4.--15. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." bitfld.long 0x0 16. " OD ,CAN_TX open drain enable. This bit is only active when CAN_TX is configured to be in GIO mode (FUNC=0).Forced to '0' if INIT bit of is reset. ." "0,1" textline " " bitfld.long 0x0 17. " PD ,CAN_TX pull disable. This bit is only active when CAN_TX is configured to be an input." "0,1" bitfld.long 0x0 18. " PU ,CAN_TX pull up/pull down select. This bit is only active when CAN_TX is configured to be an input." "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." group.byte 0x1E4++0x3 line.long 0x0 "DCAN_RIOC,RX I/O Control Register The CAN_RX pin of the DCAN_module can be used as general purpose IO pin if CAN function is not needed. The values of the IO control registers are only writable if INIT bit of the is set to 1." bitfld.long 0x0 0. " IN ,CAN_RX data in ." "0,1" bitfld.long 0x0 1. " OUT ,CAN_RX data out write. This bit is only active when CAN_RX pin is configured to be in GIO mode (FUNC = 0) and configured to be an output pin (DIR = 1). The value of this bit indicates the value to be output to the CAN_RX pin. ." "0,1" textline " " bitfld.long 0x0 2. " DIR ,CAN_RX data direction. This bit controls the direction of the CAN_RX pin when it is configured to be in GIO mode only (FUNC=0)Forced to '0' if INIT bit is reset. ." "0,1" bitfld.long 0x0 3. " FUNC ,CAN_RX function. This bit changes the function of the CAN_RX pinForced to '1' if INIT bit of is reset. ." "0,1" textline " " hexmask.long.word 0x0 4.--15. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." bitfld.long 0x0 16. " OD ,CAN_RX open drain enable. This bit is only active when CAN_RX is configured to be in GIO mode (FUNC=0).Forced to '0' if INIT bit of is reset. ." "0,1" textline " " bitfld.long 0x0 17. " PD ,CAN_RX pull disable. This bit is only active when CAN_TX is configured to be an input." "0,1" bitfld.long 0x0 18. " PU ,CAN_RX pull up/pull down select. This bit is only active when CAN_RX is configured to be an input." "0,1" textline " " hexmask.long.word 0x0 19.--31. 1. " RESERVED ,These bits are always read as 0. Writes have no effect." width 0x0B tree.end tree "SPF1" base ad:0x48485C00 width 19. group.byte 0x0++0x3 line.long 0x0 "SPF_IDVER,SPF revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,SPF revision value" group.byte 0x4++0x3 line.long 0x0 "SPF_STATUS,Status register" bitfld.long 0x0 0. " SPF_BUSY ,SPF is Busy/Idle, Busy Packet processing or logging in progress." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "SPF_CONTROL,SPF control register" bitfld.long 0x0 0. " SPF_ENABLE ,SPF Enable. This bit must be set to enable any operation in SPF. The SPF instruction memory can only be accessed by host processor when the spf_enable is deasserted. Once spf_enable is set, writing a zero to this bit will only take effect when spf_busy signal is low. This ensures that spf stops only on packet boundaries." "0,1" bitfld.long 0x0 1. " SPF_DROP ,SPF Drop Enable. This bit must be set to activate packet drops." "0,1" textline " " bitfld.long 0x0 2. " SPF_EXT_BYPASS ,SPF Extractor Bypass Enable. The extractor will not provide any offset information to rule engine if this bit is set. The rule engine must load each of the base registers it intends to use to determine if the packet should be discarded." "0,1" bitfld.long 0x0 3. " SPF_RULE_LOG ,SPF Rule Engine Log Enable. Setting this bit will allow SPF to log data from rule engine. The default is log data from extractor." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SPF_LOG_EN ,SPF Log Enable. Setting this bit will allow SPF to log information about dropped packets to memory." "0,1" textline " " bitfld.long 0x0 9. " SPF_LOGOW_EN ,SPF Log Overwrite Enable. Setting this bit will cause SPF to overwrite previously logged data whether or not software has updated the software_working_pointer. Overwriting only occurs if there is new data but no space to write it in the space indicated by log_start_address and log_end_address." "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "SPF_DROPCOUNT,Drop Count Register" hexmask.long.tbyte 0x0 0.--23. 1. " SPF_DROPCNT ,SPF Drop counter indicates the number of packets dropped so far. This counter does not roll over and must be cleared by writing 0x00FFFFFF." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "SPF_SWRESET,Software Reset Register" bitfld.long 0x0 0. " SPF_SWRST ,SPF Software reset bit can be set to initiate a software reset. It stays high until the reset has not completed, this reset clears all registers to default value." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "SPF_PRESCALE,Rate Limit Prescale Register" hexmask.long.tbyte 0x0 0.--19. 1. " SPF_PRESCALE ,The MAIN clock is divided by this value for use in Rate Limiters. It is used to create rolling time intervals for use in rate limiting feature." hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "SPF_RATELIMi_0,Rate Limit Register" hexmask.long.byte 0x0 0.--7. 1. " SPF_RATELIM ,SPF Rate Limit Register. The number of packets corresponding to a filter that will be allowed per unit time interval. The filters are programmed in the rule engine and time interval is determined by theSPF_PRESCALE register." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "SPF_RATELIMi_1,Rate Limit Register" hexmask.long.byte 0x0 0.--7. 1. " SPF_RATELIM ,SPF Rate Limit Register. The number of packets corresponding to a filter that will be allowed per unit time interval. The filters are programmed in the rule engine and time interval is determined by theSPF_PRESCALE register." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "SPF_RATELIMi_2,Rate Limit Register" hexmask.long.byte 0x0 0.--7. 1. " SPF_RATELIM ,SPF Rate Limit Register. The number of packets corresponding to a filter that will be allowed per unit time interval. The filters are programmed in the rule engine and time interval is determined by theSPF_PRESCALE register." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "SPF_RATELIMi_3,Rate Limit Register" hexmask.long.byte 0x0 0.--7. 1. " SPF_RATELIM ,SPF Rate Limit Register. The number of packets corresponding to a filter that will be allowed per unit time interval. The filters are programmed in the rule engine and time interval is determined by theSPF_PRESCALE register." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "SPF_CONSTj_0,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x20++0x3 line.long 0x0 "SPF_CONSTj_1,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x24++0x3 line.long 0x0 "SPF_CONSTj_2,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x28++0x3 line.long 0x0 "SPF_CONSTj_3,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x2C++0x3 line.long 0x0 "SPF_CONSTj_4,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x30++0x3 line.long 0x0 "SPF_CONSTj_5,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x34++0x3 line.long 0x0 "SPF_CONSTj_6,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x38++0x3 line.long 0x0 "SPF_CONSTj_7,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x50++0x3 line.long 0x0 "SPF_INSTRW2,Instruction Word 2 Register" hexmask.long.word 0x0 0.--13. 1. " SPF_INSTR_W2 ,SPF Rule Engine Instruction Word [75:64] is read from or written to this field." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "SPF_INSTRW1,Instruction Word 1 Register" hexmask.long 0x0 0.--31. 1. " SPF_INSTR_W1 ,SPF Rule Engine Instruction Word [63:32] is read from or written to this field." group.byte 0x58++0x3 line.long 0x0 "SPF_INSTRW0,Instruction Word 0 Register" hexmask.long 0x0 0.--31. 1. " SPF_INSTR_W0 ,SPF Rule Engine Instruction Word [31:0] is read from or written to this field." group.byte 0x5C++0x3 line.long 0x0 "SPF_INSTR_CTL,Instruction Control Register" bitfld.long 0x0 0.--5. " SPF_INSTR_PTR ,The address in the instruction memory that is to be accessed." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.tbyte 0x0 6.--29. 1. " RESERVED ," textline " " bitfld.long 0x0 30. " SPF_INSTR_REN ,SPF Read enable bit specifies whether a read operation is to be performed. This bit is set to perform a read and read data is available in the SPF_INSTR_W2, SPF_INSTR_W1 and SPF_INSTR_W0 registers once read operation has completed. This bit is always read as zero." "0,1" bitfld.long 0x0 31. " SPF_INSTR_WEN ,SPF Write enable bit specifies whether a write operation is to be performed. To read or write instructions, spf processing must be stopped. When the rule engine is processing instructions, the instruction memory cannot be accessed. This bit is set to perform a write and the data in the SPF_INSTR_W2, SPF_INSTR_W1 and SPF_INSTR_W0 registers is written to the instruction RAM at address specified in the SPF_INSTR_PTR field. This bit is always read as zero." "0,1" group.byte 0x60++0x3 line.long 0x0 "SPF_LOG_BEGIN,Log Begin Address Register" hexmask.long 0x0 0.--31. 1. " SPF_LOG_BEGIN ,SPF starts to write log data to memory starting from address given in this field." group.byte 0x64++0x3 line.long 0x0 "SPF_LOG_END,Log End Address Register" hexmask.long 0x0 0.--31. 1. " SPF_LOG_END ,This register along withSPF_LOG_BEGIN register defines the memory range for writing log data, the range(SPF_LOG_END SPF_LOG_BEGIN) should be multiple of 4 words(32 bits), as this is a look ahead register therefore the value progammed should be next word address. (i.e. last word address + 4)." group.byte 0x68++0x3 line.long 0x0 "SPF_LOG_HWPTR,Log Hardware Pointer Register" hexmask.long 0x0 0.--31. 1. " SPF_LOG_HWPTR ,This register indicated the address of next location in memory that the SPF will log information to." group.byte 0x6C++0x3 line.long 0x0 "SPF_LOG_SWPTR,Log Software Pointer Register" hexmask.long 0x0 0.--31. 1. " SPF_LOG_SWPTR ,This register specifies the address where software shall do next read, software must inform SPF about memory roll over by writingSPF_LOG_END into this register." group.byte 0x70++0x3 line.long 0x0 "SPF_LOG_MAP0,Filter Code Map Register 0" hexmask.long.byte 0x0 0.--7. 1. " SPF_LOGMAP0 ,Mapping of drop code 0 to log threshold 0" hexmask.long.byte 0x0 8.--15. 1. " SPF_LOGMAP1 ,Mapping of drop code 1 to log threshold 1" textline " " hexmask.long.byte 0x0 16.--23. 1. " SPF_LOGMAP2 ,Mapping of drop code 2 to log threshold 2" hexmask.long.byte 0x0 24.--31. 1. " SPF_LOGMAP3 ,Mapping of drop code 3 to log threshold 3" group.byte 0x74++0x3 line.long 0x0 "SPF_LOG_MAP1,Filter Code Map Register 1" hexmask.long.byte 0x0 0.--7. 1. " SPF_LOGMAP4 ,Mapping of drop code 4 to log threshold 4" hexmask.long.byte 0x0 8.--15. 1. " SPF_LOGMAP5 ,Mapping of drop code 5 to log threshold 5" textline " " hexmask.long.byte 0x0 16.--23. 1. " SPF_LOGMAP6 ,Mapping of drop code 6 to log threshold 6" hexmask.long.byte 0x0 24.--31. 1. " SPF_LOGMAP7 ,Mapping of drop code 7 to log threshold 7" group.byte 0x78++0x3 line.long 0x0 "SPF_LOG_THRESHk_0,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x7C++0x3 line.long 0x0 "SPF_LOG_THRESHk_1,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x80++0x3 line.long 0x0 "SPF_LOG_THRESHk_2,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x84++0x3 line.long 0x0 "SPF_LOG_THRESHk_3,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x88++0x3 line.long 0x0 "SPF_LOG_THRESHk_4,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x8C++0x3 line.long 0x0 "SPF_LOG_THRESHk_5,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x90++0x3 line.long 0x0 "SPF_LOG_THRESHk_6,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x94++0x3 line.long 0x0 "SPF_LOG_THRESHk_7,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x98++0x3 line.long 0x0 "SPF_LOG_THRESHk_8,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x9C++0x3 line.long 0x0 "SPF_INTCNT,Interrupt Frequency Control Register" bitfld.long 0x0 0.--4. " SPF_INTCNT ,Number of time thresholds must be met before a drop interrupt is triggered." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "SPF_INT_RAW,Raw Interrupt Status register" bitfld.long 0x0 0. " SPF_INT_RAW ,Status of Raw interrupt signal" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "SPF_INT_MASKED,Interrupt Status register" bitfld.long 0x0 0. " SPF_INT_MASKED ,Status of interrupt signal with mask" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "SPF_MASK_SET,Interrupt Mask Set Register" bitfld.long 0x0 0. " SPF_MASKSET ,Write a 1 to this bit to enable the interrupt." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xAC++0x3 line.long 0x0 "SPF_MASK_CLR,Interrupt Mask Clear Register" bitfld.long 0x0 0. " SPF_MASKCLR ,Write a 1 to this bit to disable the interrupt." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "SPF2" base ad:0x48485E00 width 19. group.byte 0x0++0x3 line.long 0x0 "SPF_IDVER,SPF revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,SPF revision value" group.byte 0x4++0x3 line.long 0x0 "SPF_STATUS,Status register" bitfld.long 0x0 0. " SPF_BUSY ,SPF is Busy/Idle, Busy Packet processing or logging in progress." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "SPF_CONTROL,SPF control register" bitfld.long 0x0 0. " SPF_ENABLE ,SPF Enable. This bit must be set to enable any operation in SPF. The SPF instruction memory can only be accessed by host processor when the spf_enable is deasserted. Once spf_enable is set, writing a zero to this bit will only take effect when spf_busy signal is low. This ensures that spf stops only on packet boundaries." "0,1" bitfld.long 0x0 1. " SPF_DROP ,SPF Drop Enable. This bit must be set to activate packet drops." "0,1" textline " " bitfld.long 0x0 2. " SPF_EXT_BYPASS ,SPF Extractor Bypass Enable. The extractor will not provide any offset information to rule engine if this bit is set. The rule engine must load each of the base registers it intends to use to determine if the packet should be discarded." "0,1" bitfld.long 0x0 3. " SPF_RULE_LOG ,SPF Rule Engine Log Enable. Setting this bit will allow SPF to log data from rule engine. The default is log data from extractor." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SPF_LOG_EN ,SPF Log Enable. Setting this bit will allow SPF to log information about dropped packets to memory." "0,1" textline " " bitfld.long 0x0 9. " SPF_LOGOW_EN ,SPF Log Overwrite Enable. Setting this bit will cause SPF to overwrite previously logged data whether or not software has updated the software_working_pointer. Overwriting only occurs if there is new data but no space to write it in the space indicated by log_start_address and log_end_address." "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "SPF_DROPCOUNT,Drop Count Register" hexmask.long.tbyte 0x0 0.--23. 1. " SPF_DROPCNT ,SPF Drop counter indicates the number of packets dropped so far. This counter does not roll over and must be cleared by writing 0x00FFFFFF." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "SPF_SWRESET,Software Reset Register" bitfld.long 0x0 0. " SPF_SWRST ,SPF Software reset bit can be set to initiate a software reset. It stays high until the reset has not completed, this reset clears all registers to default value." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "SPF_PRESCALE,Rate Limit Prescale Register" hexmask.long.tbyte 0x0 0.--19. 1. " SPF_PRESCALE ,The MAIN clock is divided by this value for use in Rate Limiters. It is used to create rolling time intervals for use in rate limiting feature." hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "SPF_RATELIMi_0,Rate Limit Register" hexmask.long.byte 0x0 0.--7. 1. " SPF_RATELIM ,SPF Rate Limit Register. The number of packets corresponding to a filter that will be allowed per unit time interval. The filters are programmed in the rule engine and time interval is determined by theSPF_PRESCALE register." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "SPF_RATELIMi_1,Rate Limit Register" hexmask.long.byte 0x0 0.--7. 1. " SPF_RATELIM ,SPF Rate Limit Register. The number of packets corresponding to a filter that will be allowed per unit time interval. The filters are programmed in the rule engine and time interval is determined by theSPF_PRESCALE register." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "SPF_RATELIMi_2,Rate Limit Register" hexmask.long.byte 0x0 0.--7. 1. " SPF_RATELIM ,SPF Rate Limit Register. The number of packets corresponding to a filter that will be allowed per unit time interval. The filters are programmed in the rule engine and time interval is determined by theSPF_PRESCALE register." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "SPF_RATELIMi_3,Rate Limit Register" hexmask.long.byte 0x0 0.--7. 1. " SPF_RATELIM ,SPF Rate Limit Register. The number of packets corresponding to a filter that will be allowed per unit time interval. The filters are programmed in the rule engine and time interval is determined by theSPF_PRESCALE register." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "SPF_CONSTj_0,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x20++0x3 line.long 0x0 "SPF_CONSTj_1,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x24++0x3 line.long 0x0 "SPF_CONSTj_2,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x28++0x3 line.long 0x0 "SPF_CONSTj_3,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x2C++0x3 line.long 0x0 "SPF_CONSTj_4,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x30++0x3 line.long 0x0 "SPF_CONSTj_5,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x34++0x3 line.long 0x0 "SPF_CONSTj_6,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x38++0x3 line.long 0x0 "SPF_CONSTj_7,Constant Register" hexmask.long 0x0 0.--31. 1. " SPF_CONST ,SPF Constant Register. The contents of this register are used as input to any instruction that references it." group.byte 0x50++0x3 line.long 0x0 "SPF_INSTRW2,Instruction Word 2 Register" hexmask.long.word 0x0 0.--13. 1. " SPF_INSTR_W2 ,SPF Rule Engine Instruction Word [75:64] is read from or written to this field." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "SPF_INSTRW1,Instruction Word 1 Register" hexmask.long 0x0 0.--31. 1. " SPF_INSTR_W1 ,SPF Rule Engine Instruction Word [63:32] is read from or written to this field." group.byte 0x58++0x3 line.long 0x0 "SPF_INSTRW0,Instruction Word 0 Register" hexmask.long 0x0 0.--31. 1. " SPF_INSTR_W0 ,SPF Rule Engine Instruction Word [31:0] is read from or written to this field." group.byte 0x5C++0x3 line.long 0x0 "SPF_INSTR_CTL,Instruction Control Register" bitfld.long 0x0 0.--5. " SPF_INSTR_PTR ,The address in the instruction memory that is to be accessed." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.tbyte 0x0 6.--29. 1. " RESERVED ," textline " " bitfld.long 0x0 30. " SPF_INSTR_REN ,SPF Read enable bit specifies whether a read operation is to be performed. This bit is set to perform a read and read data is available in the SPF_INSTR_W2, SPF_INSTR_W1 and SPF_INSTR_W0 registers once read operation has completed. This bit is always read as zero." "0,1" bitfld.long 0x0 31. " SPF_INSTR_WEN ,SPF Write enable bit specifies whether a write operation is to be performed. To read or write instructions, spf processing must be stopped. When the rule engine is processing instructions, the instruction memory cannot be accessed. This bit is set to perform a write and the data in the SPF_INSTR_W2, SPF_INSTR_W1 and SPF_INSTR_W0 registers is written to the instruction RAM at address specified in the SPF_INSTR_PTR field. This bit is always read as zero." "0,1" group.byte 0x60++0x3 line.long 0x0 "SPF_LOG_BEGIN,Log Begin Address Register" hexmask.long 0x0 0.--31. 1. " SPF_LOG_BEGIN ,SPF starts to write log data to memory starting from address given in this field." group.byte 0x64++0x3 line.long 0x0 "SPF_LOG_END,Log End Address Register" hexmask.long 0x0 0.--31. 1. " SPF_LOG_END ,This register along withSPF_LOG_BEGIN register defines the memory range for writing log data, the range(SPF_LOG_END SPF_LOG_BEGIN) should be multiple of 4 words(32 bits), as this is a look ahead register therefore the value progammed should be next word address. (i.e. last word address + 4)." group.byte 0x68++0x3 line.long 0x0 "SPF_LOG_HWPTR,Log Hardware Pointer Register" hexmask.long 0x0 0.--31. 1. " SPF_LOG_HWPTR ,This register indicated the address of next location in memory that the SPF will log information to." group.byte 0x6C++0x3 line.long 0x0 "SPF_LOG_SWPTR,Log Software Pointer Register" hexmask.long 0x0 0.--31. 1. " SPF_LOG_SWPTR ,This register specifies the address where software shall do next read, software must inform SPF about memory roll over by writingSPF_LOG_END into this register." group.byte 0x70++0x3 line.long 0x0 "SPF_LOG_MAP0,Filter Code Map Register 0" hexmask.long.byte 0x0 0.--7. 1. " SPF_LOGMAP0 ,Mapping of drop code 0 to log threshold 0" hexmask.long.byte 0x0 8.--15. 1. " SPF_LOGMAP1 ,Mapping of drop code 1 to log threshold 1" textline " " hexmask.long.byte 0x0 16.--23. 1. " SPF_LOGMAP2 ,Mapping of drop code 2 to log threshold 2" hexmask.long.byte 0x0 24.--31. 1. " SPF_LOGMAP3 ,Mapping of drop code 3 to log threshold 3" group.byte 0x74++0x3 line.long 0x0 "SPF_LOG_MAP1,Filter Code Map Register 1" hexmask.long.byte 0x0 0.--7. 1. " SPF_LOGMAP4 ,Mapping of drop code 4 to log threshold 4" hexmask.long.byte 0x0 8.--15. 1. " SPF_LOGMAP5 ,Mapping of drop code 5 to log threshold 5" textline " " hexmask.long.byte 0x0 16.--23. 1. " SPF_LOGMAP6 ,Mapping of drop code 6 to log threshold 6" hexmask.long.byte 0x0 24.--31. 1. " SPF_LOGMAP7 ,Mapping of drop code 7 to log threshold 7" group.byte 0x78++0x3 line.long 0x0 "SPF_LOG_THRESHk_0,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x7C++0x3 line.long 0x0 "SPF_LOG_THRESHk_1,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x80++0x3 line.long 0x0 "SPF_LOG_THRESHk_2,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x84++0x3 line.long 0x0 "SPF_LOG_THRESHk_3,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x88++0x3 line.long 0x0 "SPF_LOG_THRESHk_4,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x8C++0x3 line.long 0x0 "SPF_LOG_THRESHk_5,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x90++0x3 line.long 0x0 "SPF_LOG_THRESHk_6,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x94++0x3 line.long 0x0 "SPF_LOG_THRESHk_7,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x98++0x3 line.long 0x0 "SPF_LOG_THRESHk_8,Log Threshold and Count Register" hexmask.long.word 0x0 0.--15. 1. " SPF_THRESH ,Number of packets to be dropped before logging starts" hexmask.long.word 0x0 16.--31. 1. " SPF_COUNT ,Number of packets dropped for drop code k (8 is default)" group.byte 0x9C++0x3 line.long 0x0 "SPF_INTCNT,Interrupt Frequency Control Register" bitfld.long 0x0 0.--4. " SPF_INTCNT ,Number of time thresholds must be met before a drop interrupt is triggered." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "SPF_INT_RAW,Raw Interrupt Status register" bitfld.long 0x0 0. " SPF_INT_RAW ,Status of Raw interrupt signal" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "SPF_INT_MASKED,Interrupt Status register" bitfld.long 0x0 0. " SPF_INT_MASKED ,Status of interrupt signal with mask" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "SPF_MASK_SET,Interrupt Mask Set Register" bitfld.long 0x0 0. " SPF_MASKSET ,Write a 1 to this bit to enable the interrupt." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xAC++0x3 line.long 0x0 "SPF_MASK_CLR,Interrupt Mask Clear Register" bitfld.long 0x0 0. " SPF_MASKCLR ,Write a 1 to this bit to disable the interrupt." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," width 0x0B tree.end tree "MDIO" base ad:0x48485000 width 21. group.byte 0x0++0x3 line.long 0x0 "MDIO_VER,MDIO Revision" hexmask.long 0x0 0.--31. 1. " REVISION ,MDIO revision value" group.byte 0x4++0x3 line.long 0x0 "MDIO_CONTROL,MDIO Control register" hexmask.long.word 0x0 0.--15. 1. " CLKDIV ,Clock divider. This field specifies the division ratio between ICLK and the frequency of MDCLK. MDCLK is disabled when CLKDIV is set to 0. MDCLK frequency = ICLK frequency/(CLKDIV+1)." bitfld.long 0x0 16. " RESERVED ," "0,1" textline " " bitfld.long 0x0 17. " INTTESTENB ,Interrupt test enable. This bit can be set to 1 to enable the host to set the USERINT and LINKINT bits for test purposes. 0: Interrupt bits are not set. 1: Enables the host to set the USERINT and LINKINT bits for test purposes." "0,1" bitfld.long 0x0 18. " FAULTENB ,Fault detect enable. This bit has to be set to 1 to enable the physical layer fault detection. 0: Disables the physical layer fault detection. 1: Enables the physical layer fault detection." "0,1" textline " " bitfld.long 0x0 19. " FAULT ,Fault indicator. This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them. This indicates a physical layer fault and the module state machine is reset. Writing a 1 to it clears this bit. 0: No failure. 1: Physical layer fault; the MDIO state machine is reset." "0,1" bitfld.long 0x0 20. " PREAMBLE ,Preamble disable. 0: Standard MDIO preamble is used. 1: Disables this device from sending MDIO frame preambles." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel. This field specifies the highest user access channel that is available in the module and is currently set to 1. This implies that theMDIO_USERACCESS1 register is the highest available user access channel." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 29. " RESERVED ," "0,1" bitfld.long 0x0 30. " ENABLE ,Enable control. If the MDIO state machine is active at the time it is disabled, it will complete the current operation before halting and setting the IDLE bit. If using byte access, the ENABLE bit has to be the last bit written in this register. 0: Disables the MDIO state machine. 1: Enable the MDIO state machine." "0,1" textline " " bitfld.long 0x0 31. " IDLE ,MDIO state machine IDLE. Set to 1 when the state machine is in the idle state. 0: State machine is not in idle state. 1: State machine is in idle state." "0,1" group.byte 0x8++0x3 line.long 0x0 "MDIO_ALIVE,PHY Alive Status Register" hexmask.long 0x0 0.--31. 1. " ALIVE ,MDIO alive. Each of the 32 bits of this register is set if the most recent access to the PHY with address corresponding to the register bit number was acknowledged by the PHY, the bit is reset if the PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause the corresponding alive bit to be updated. The alive bits are only meant to be used to give an indication of the presence or not of a PHY with the corresponding address. Writing a 1 to any bit will clear it, writing a 0 has no effect." group.byte 0xC++0x3 line.long 0x0 "MDIO_LINK,PHY Link Status" hexmask.long 0x0 0.--31. 1. " LINK ,MDIO link state. This register is updated after a read of the Generic Status Register of a PHY. The bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge the read transaction. Writes to the register have no effect. In addition, the status of the two PHYs specified in the MDIO_USERPHYSEL registers can be determined using the MLINK input pins (NOT PINNED OUT). This is determined by the LINKSEL bit in the MDIO_USERPHYSEL register." group.byte 0x10++0x3 line.long 0x0 "MDIO_LINKINTRAW,MDIO_LINKINTRAW" bitfld.long 0x0 0.--1. " LINKINTRAW ,MDIO link change event, raw value." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "MDIO_LINKINTMASKED,MDIO Link Status Change Interrupt Register" bitfld.long 0x0 0.--1. " LINKINTMASKED ,MDIO link change interrupt, masked value. When asserted 1, a bit indicates that there was an MDIO link change event (i.e. change in the MDIO Link register) corresponding to the PHY address in the MDIO_USERPHYSEL register and the corresponding LINKINTENB bit was set. LINKINTMASKED[0] and LINKINTMASKED[1] correspond toMDIO_USERPHYSEL0 and MDIO_USERPHYSEL1, respectively. Writing a 1 will clear the interrupt and writing 0 has no effect. If the INTTESTENB bit in the MDIO_CONTROL register is set, the host may set the LINKINT bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "MDIO_USERINTRAW,MDIO User Command Complete Interrupt" bitfld.long 0x0 0.--1. " USERINTRAW ,Raw value of MDIO user command complete event for theMDIO_USERACCESS1 and MDIO_USERACCESS0 register, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIO_USERACCESS register has completed. Writing a 1 will clear the event and writing 0 has no effect. If the INTTESTENB bit in the MDIO_CONTROL register is set, the host may set the USERINTRAW bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "MDIO_USERINTMASKED,MDIO User Command Complete Interrupt" bitfld.long 0x0 0.--1. " USERINTMASKED ,Masked value of MDIO user command complete interrupt for theMDIO_USERACCESS1 and MDIO_USERACCESS0 register, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIO_USERACCESS register has completed and the corresponding USERINTMASKSET bit is set to 1. Writing a 1 will clear the interrupt and writing 0 has no effect. If the INTTESTENB bit in the MDIO_CONTROL register is set, the host may set the USERINTMASKED bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "MDIO_USERINTMASKSET,MDIO User Command Complete Interrupt Mask Set" bitfld.long 0x0 0.--1. " USERINTMASKSET ,MDIO user interrupt mask set for USERINTMASKED[1:0], respectively. Writing a bit to 1 will enable MDIO user command complete interrupts for that particular MDIO_USERACCESS register. MDIO user interrupt for a particular MDIO_USERACCESS register is disabled if the corresponding bit is 0. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "MDIO_USERINTMASKCLR,MDIO User Command Complete Interrupt Mask Clear" bitfld.long 0x0 0.--1. " USERINTMASKCLEAR ,MDIO user command complete interrupt mask clear for USERINTMASKED[1:0], respectively. Writing a bit to 1 will disable further user command complete interrupts for that particular MDIO_USERACCESS register. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "MDIO_USERACCESS0,MDIO_User_Access" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. Specifies the PHY to be accesses for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. Specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to theMDIO_USERACCESS0 register are blocked when the GO bit is 1. If byte access is being used, the GO bit should be written last." "0,1" group.byte 0x84++0x3 line.long 0x0 "MDIO_USERPHYSEL0,MDIO User PHY Select" bitfld.long 0x0 0.--4. " PHYADDRMON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINTENB ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in PHYADDRMON. Link change interrupts are disabled if this bit is set to 0. 0: Link change interrupts are disabled. 1: Link change status interrupts for PHY address specified in PHYADDRMON bits are enabled." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin (NOT PINNED OUT). Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "MDIO_USERACCESS1,MDIO User Access" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. Specifies the PHY to be accesses for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. Specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to theMDIO_USERACCESS1 register are blocked when the GO bit is 1. If byte access is being used, the GO bit should be written last." "0,1" group.byte 0x8C++0x3 line.long 0x0 "MDIO_USERPHYSEL1,MDIO User PHY Select" bitfld.long 0x0 0.--4. " PHYADDRMON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINTENB ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in PHYADDRMON. Link change interrupts are disabled if this bit is set to 0. 0: Link change interrupts are disabled. 1: Link change status interrupts for PHY address specified in PHYADDRMON bits are enabled." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin (NOT PINNED OUT). Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," width 0x0B tree.end tree "STATS" base ad:0x48484900 width 30. group.byte 0x0++0x3 line.long 0x0 "GOOD_RX_FRAMES,The total number of good frames received on the port. A good frame is defined to be: - Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Had a length of 64 to [13:0] RX_MAXLEN bytes inclusive - Had no CRC error, alignment error or code error. See the and statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x4++0x3 line.long 0x0 "BROADCAST_RX_FRAMES,The total number of good broadcast frames received on the port. A good broadcast frame is defined to be: - Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF - Had a length of [13:0] RX_MAXLEN bytes inclusive - Had no CRC error, alignment error or code error. See the and statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x8++0x3 line.long 0x0 "MULTICAST_RX_FRAMES,The total number of good multicast frames received on the port. A good multicast frame is defined to be: - Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF - Had a length of [13:0] RX_MAXLEN bytes inclusive - Had no CRC error, alignment error or code error. See the and statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0xC++0x3 line.long 0x0 "PAUSE_RX_FRAMES,The total number of IEEE 802.3X pause frames received by the port (whether acted upon or not). Such a frame: - Contained any unicast, broadcast, or multicast address - Contained the length/type field value 88.08 (hex) and the opcode 0x0001 - Was of length 64 to [13:0] RX_MAXLEN bytes inclusive - Had no CRC error, alignment error or code error - Pause-frames had been enabled on the port ([4] TX_FLOW_EN = 1). The port could have been in either half or full-duplex mode. See the and statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x10++0x3 line.long 0x0 "RX_CRC_ERRORS,The total number of frames received on the port that experienced a CRC error. Such a frame: - Was any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Was of length 64 to [13:0] RX_MAXLEN bytes inclusive - Had no code/align error, - Had a CRC error Overruns have no effect upon this statistic. A CRC error is defined to be: - A frame containing an even number of nibbles - Failing the Frame Check Sequence test" hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x14++0x3 line.long 0x0 "RX_ALIGN_CODE_ERRORS,The total number of frames received on the port that experienced an alignment error or code error. Such a frame: - Was any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Was of length 64 to [13:0] RX_MAXLEN bytes inclusive - Had either an alignment error or a code error Overruns have no effect upon this statistic. An alignment error is defined to be: - A frame containing an odd number of nibbles - Failing the Frame Check Sequence test if the final nibble is ignored A code error is defined to be a frame which has been discarded because the port's MRXER pin driven with a one for at least one bit-time's duration at any point during the frame's reception. Note: RFC 1757 etherStatsCRCAlignErrors Ref. 1.5 can be calculated by summing and ." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x18++0x3 line.long 0x0 "OVERSIZE_RX_FRAMES,The total number of oversized frames received on the port. An oversized frame is defined to be: - Was any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Was greater than [13:0] RX_MAXLEN in bytes - Had no CRC error, alignment error or code error See the and statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x1C++0x3 line.long 0x0 "RX_JABBERS,The total number of jabber frames received on the port. A jabber frame: - Was any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Was greater than [13:0] RX_MAXLEN in bytes - Had no CRC error, alignment error or code error See the and statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x20++0x3 line.long 0x0 "UNDERSIZE_RX_FRAMES,The total number of undersized frames received on the port. An undersized frame is defined to be: - Was any data frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Was greater than [13:0] RX_MAXLEN in bytes - Had no CRC error, alignment error or code error See the and statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x24++0x3 line.long 0x0 "RX_FRAGMENTS,The total number of frame fragments received on the port. A frame fragment is defined to be: - Any data frame (address matching does not matter) - Less than 64 bytes long - Having a CRC error, an alignment error, or a code error - Not the result of a collision caused by half duplex, collision based flow control See the and statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x30++0x3 line.long 0x0 "RX_OCTETS,The total number of bytes in all good frames received on the port. A good frame is defined to be: - Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Of length 64 to [13:0] RX_MAXLEN bytes inclusive - Had no CRC error, alignment error or code error See the and statistic descriptions for definitions of alignment, code and CRC errors. Overruns have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x34++0x3 line.long 0x0 "GOOD_TX_FRAMES,The total number of good frames received on the port. A good frame is defined to be: - Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Any length - Had no late or excessive collisions, no carrier loss and no underrun" hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x38++0x3 line.long 0x0 "BROADCAST_TX_FRAMES,The total number of good broadcast frames received on the port. A good broadcast frame is defined to be: - Any data or MAC control frame which was destined for only address 0xFFFFFFFFFFFF - Any length - Had no late or excessive collisions, no carrier loss and no underrun" hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x3C++0x3 line.long 0x0 "MULTICAST_TX_FRAMES,The total number of good multicast frames received on the port. A good multicast frame is defined to be: - Any data or MAC control frame which was destined for any multicast address other than 0xFFFFFFFFFFFF - Any length - Had no late or excessive collisions, no carrier loss and no underrun" hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x40++0x3 line.long 0x0 "PAUSE_TX_FRAMES,This statistic indicates the number of IEEE 802.3X pause frames transmitted by the port. Pause frames cannot underrun or contain a CRC error because they are created in the transmitting MAC, so these error conditions have no effect upon the statistic. Pause frames sent by software will not be included in this count. Since pause frames are only transmitted in full duplex carrier loss and collisions have no effect upon this statistic. Transmitted pause frames are always 64 byte multicast frames so will appear in the and statistics." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x44++0x3 line.long 0x0 "DEFERRED_TX_FRAMES,The total number of frames transmitted on the port that first experienced deferment. Such a frame: - Was any data or MAC control frame destined for any unicast, broadcast or multicast address - Was any size - Had no carrier loss and no underrun - Experienced no collisions before being successfully transmitted - Found the medium busy when transmission was first attempted, so had to wait. CRC errors have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x48++0x3 line.long 0x0 "COLLISIONS,This statistic records the total number of times that the port experienced a collision. Collisions occur under two circumstances. 1. When a transmit data or MAC control frame: - Was destined for any unicast, broadcast or multicast address - Was any size - Had no carrier loss and no underrun - Experienced a collision. A jam sequence is sent for every non-late collision, so this statistic will increment on each occasion if a frame experiences multiple collisions (and increments on late collisions) CRC errors have no effect upon this statistic. 2. When the port is in half-duplex mode, flow control is active, and a frame reception begins." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x4C++0x3 line.long 0x0 "SINGLE_COLLISION_TX_FRAMES,The total number of frames transmitted on the port that experienced exactly one collision. Such a frame: - Was any data or MAC control frame destined for any unicast, broadcast or multicast address - Was any size - Had no carrier loss and no underrun - Experienced one collision before successful transmission. The collision was not late. CRC errors have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x50++0x3 line.long 0x0 "MULTIPLE_COLLISION_TX_FRAMES,The total number of frames transmitted on the port that experienced multiple collisions. Such a frame: - Was any data or MAC control frame destined for any unicast, broadcast or multicast address - Was any size - Had no carrier loss and no underrun - Experienced 2 to 15 collisions before being successfully transmitted. None of the collisions were late. CRC errors have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x54++0x3 line.long 0x0 "EXCESSIVE_COLLISIONS,The total number of frames for which transmission was abandoned due to excessive collisions. Such a frame: - Was any data or MAC control frame destined for any unicast, broadcast or multicast address - Was any size - Had no carrier loss and no underrun - Experienced 16 collisions before abandoning all attempts at transmitting the frame. None of the collisions were late. CRC errors have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x58++0x3 line.long 0x0 "LATE_COLLISIONS,The total number of frames on the port for which transmission was abandoned because they experienced a late collision. Such a frame: - Was any data or MAC control frame destined for any unicast, broadcast or multicast address - Was any size - Experienced a collision later than 512 bit-times into the transmission. There may have been up to 15 previous (non-late) collisions which had previously required the transmission to be re-attempted. The Late Collisions statistic dominates over the single, multiple and excessive Collisions statistics - if a late collision occurs the frame will not be counted in any of these other three statistics. CRC errors have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x5C++0x3 line.long 0x0 "TX_UNDERRUN,There should be no transmitted frames that experience underrun." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x60++0x3 line.long 0x0 "CARRIER_SENSE_ERRORS,The total number of frames received on the port that had a CPDMA middle of frame (MOF) overrun. MOF overrun frame is defined to be: - Was any data or MAC control frame destined for any unicast, broadcast or multicast address - Was any size - The carrier sense condition was lost or never asserted when transmitting the frame (the frame is not retransmitted). This is a transmit only statistic. Carrier Sense is a don't care for received frames. Transmit frames with carrier sense errors are sent until completion and are not aborted. CRC errors have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x64++0x3 line.long 0x0 "TX_OCTETS,The total number of bytes in all good frames transmitted on the port. A good frame is defined to be: - Any data or MAC control frame which was destined for any unicast, broadcast or multicast address - Was any size - Had no late or excessive collisions, no carrier loss and no underrun." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x68++0x3 line.long 0x0 "RX_TX_64_OCTET_FRAMES,The total number of 64-byte frames received and transmitted on the port. Such a frame is defined to be: - Any data or MAC control frame which was destined for any unicast, broadcast or multicast address - Did not experience late collisions, excessive collisions, or carrier sense error - Was exactly 64 bytes long. (If the frame was being transmitted and experienced carrier loss that resulted in a frame of this size being transmitted, then the frame will be recorded in this statistic). CRC errors, code/align errors and overruns do not affect the recording of frames in this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x6C++0x3 line.long 0x0 "RX_TX_65_127_OCTET_FRAMES,The total number of frames of size 65 to 127 bytes received and transmitted on the port. Such a frame is defined to be: - Any data or MAC control frame which was destined for any unicast, broadcast or multicast address - Did not experience late collisions, excessive collisions, or carrier sense error - Was 65 to 127 bytes long CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x70++0x3 line.long 0x0 "RX_TX_128_255_OCTET_FRAMES,The total number of frames of size 128 to 255 bytes received and transmitted on the port. Such a frame is defined to be: - Any data or MAC control frame which was destined for any unicast, broadcast or multicast address - Did not experience late collisions, excessive collisions, or carrier sense error - Was 128 to 255 bytes long CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x74++0x3 line.long 0x0 "RX_TX_256_511_OCTET_FRAMES,The total number of frames of size 256 to 511 bytes received and transmitted on the port. Such a frame is defined to be: - Any data or MAC control frame which was destined for any unicast, broadcast or multicast address - Did not experience late collisions, excessive collisions, or carrier sense error - Was 256 to 511 bytes long CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x78++0x3 line.long 0x0 "RX_TX_512_1023_OCTET_FRAMES,The total number of frames of size 512 to 1023 bytes received and transmitted on the port. Such a frame is defined to be: - Any data or MAC control frame which was destined for any unicast, broadcast or multicast address - Did not experience late collisions, excessive collisions, or carrier sense error - Was 512 to 1023 bytes long CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x7C++0x3 line.long 0x0 "RX_TX_1024_UP_OCTET_FRAMES,The total number of frames of size 1024 to[13:0] RX_MAXLEN bytes for receive or 1024 up for transmit on the port. Such a frame is defined to be: - Any data or MAC control frame which was destined for any unicast, broadcast or multicast address - Did not experience late collisions, excessive collisions, or carrier sense error - Was 1024 to [13:0] RX_MAXLEN bytes long on receive, or any size on transmit CRC errors, code/align errors, underruns and overruns do not affect the recording of frames in this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x80++0x3 line.long 0x0 "NET_OCTETS,The total number of bytes of frame data received and transmitted on the port. Each frame counted: - was any data or MAC control frame destined for any unicast, broadcast or multicast address (address match does not matter) - Any length (including less than 64 bytes and greater than [13:0] RX_MAXLEN bytes) Also counted in this statistic is: - Every byte transmitted before a carrier- loss was experienced - Every byte transmitted before each collision was experienced, (i.e. multiple retries are counted each time) - Every byte received if the port is in half-duplex mode until a jam sequence was transmitted to initiate flow control. (The jam sequence was not counted to prevent double-counting) Error conditions such as alignment errors, CRC errors, code errors, overruns and underruns do not affect the recording of bytes by this statistic. The objective of this statistic is to give a reasonable indication of ethernet utilization" hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x84++0x3 line.long 0x0 "RX_START_OF_FRAME_OVERRUNS,The total number of frames received on the port that had a CPDMA start of frame (SOF) overrun or were dropped by due to FIFO resource limitations, or were dropped by the SPF. SOF overrun frame is defined to be: - Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Any length (including less than 64 bytes and greater than [13:0] RX_MAXLEN bytes) - The CPDMA had a start of frame overrun or the packet was dropped due to FIFO resource limitations" hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x88++0x3 line.long 0x0 "RX_MIDDLE_OF_FRAME_OVERRUNS,The total number of frames received on the port that had a CPDMA middle of frame (MOF) overrun. MOF overrun frame is defined to be: - Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Any length (including less than 64 bytes and greater than [13:0] RX_MAXLEN bytes) - The CPDMA had a middle of frame overrun" hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" group.byte 0x8C++0x3 line.long 0x0 "RX_DMA_OVERRUNS,The total number of frames received on the port that had either a DMA start of frame (SOF) overrun or a DMA MOF overrun. An Rx DMA overrun frame is defined to be: - Any data or MAC control frame which matched a unicast, broadcast or multicast address, or matched due to promiscuous mode - Any length (including less than 64 bytes and greater than [13:0] RX_MAXLEN bytes) - The CPGMAC_SL was unable to receive it because it did not have the DMA buffer resources to receive it (zero head descriptor pointer at the start or during the middle of the frame reception) CRC errors, alignment errors and code errors have no effect upon this statistic." hexmask.long 0x0 0.--31. 1. " VALUE ,Statistic value" width 0x0B tree.end tree "SS" base ad:0x48484000 width 19. group.byte 0x0++0x3 line.long 0x0 "CPSW_ID_VER,CPSW_3G ID version register" hexmask.long 0x0 0.--31. 1. " REVISION ,CPSW_3G Revision Value" group.byte 0x4++0x3 line.long 0x0 "CPSW_CONTROL,Switch control register" bitfld.long 0x0 0. " FIFO_LOOPBACK ,FIFO Loopback Mode 0 - Loopback is disabled 1 - FIFO Loopback mode enabled. Each packet received is turned around and sent out on the same port's transmit path. Port 2 receive is fixed on channel zero. The RXSOFOVERRUN statistic will increment for every packet sent in FIFO loopback mode." "0,1" bitfld.long 0x0 1. " VLAN_AWARE ,VLAN Aware Mode: 0 - CPSW_3G is in the VLAN unaware mode. 1 - CPSW_3G is in the VLAN aware mode." "0,1" textline " " bitfld.long 0x0 2. " RX_VLAN_ENCAP ,Port 0 VLAN Encapsulation (egress): 0 - Port 0 receive packets (from CPSW_3G) are not VLAN encapsulated. 1 - Port 0 receive packets (from CPSW_3G) are VLAN encapsulated." "0,1" bitfld.long 0x0 3. " DLR_EN ,DLR enable 0 - DLR is disabled. DLR packets will not be moved to queue priority 3 and will not be separated out onto dlr_cpdma_ch. 1 - DLR is disabled. DLR packets be moved to destination port transmit queue priority 3 and will be separated out onto dlr_cpdma_ch when packet is to egress on port 0." "0,1" textline " " bitfld.long 0x0 4. " EEE_EN ,EEE (Energy Efficient Ethernet) enable 0  EEE is disabled. 1  EEE is enabled" "0,1" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "CPSW_SOFT_RESET,Soft reset register" bitfld.long 0x0 0. " SOFT_RESET ,Software reset - Writing a one to this bit causes the 3G logic (INT, REGS, CPPI, and SPF modules) to be reset. After writing a one to this bit, it may be polled to determine if the reset has occurred. If a one is read, the reset has not yet occurred. If a zero is read then reset has occurred." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "CPSW_STAT_PORT_EN,Statistics port enable register" bitfld.long 0x0 0. " P0_STAT_EN ,Port 0 Statistics Enable 0 - Port 0 statistics are not enabled 1 - Port 0 statistics are enabled. FIFO overruns (SOFOVERRUNS) are the only port 0 statistics that are enabled to be kept." "0,1" bitfld.long 0x0 1. " P1_STAT_EN ,Port 1 (GMII1 and Port 1 FIFO) Statistics Enable 0 - Port 1 statistics are not enabled. 1 - Port 1 statistics are enabled." "0,1" textline " " bitfld.long 0x0 2. " P2_STAT_EN ,Port 2 (GMII2 and Port 2 FIFO) Statistics Enable 0 - Port 2 statistics are not enabled. 1 - Port 2 statistics are enabled." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "CPSW_PTYPE,Transmit priority type register" bitfld.long 0x0 0.--4. " ESC_PRI_LD_VAL ,Escalate Priority Load Value When a port is in escalate priority, this is the number of higher priority packets sent before the next lower priority is allowed to send a packet. Escalate priority allows lower priority packets to be sent at a fixed rate relative to the next higher priority." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8. " P0_PTYPE_ESC ,Port 0 Priority Type Escalate - 0 - Port 0 priority type fixed 1 - Port 0 priority type escalate Escalate should not be used with queue shaping." "0,1" bitfld.long 0x0 9. " P1_PTYPE_ESC ,Port 1 Priority Type Escalate - 0 - Port 1 priority type fixed 1 - Port 1 priority type escalate Escalate should not be used with queue shaping." "0,1" textline " " bitfld.long 0x0 10. " P2_PTYPE_ESC ,Port 2 Priority Type Escalate - 0 - Port 2 priority type fixed 1 - Port 2 priority type escalate Escalate should not be used with queue shaping." "0,1" bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16. " P1_PRI1_SHAPE_EN ,Port 1 Queue Priority 1 Transmit Shape Enable- If there are three shaping queues all three bits should be set." "0,1" bitfld.long 0x0 17. " P1_PRI2_SHAPE_EN ,Port 1 Queue Priority 2 Transmit Shape Enable- If there are two shaping queues then they must be priorities 3 and 2." "0,1" textline " " bitfld.long 0x0 18. " P1_PRI3_SHAPE_EN ,Port 1 Queue Priority 3 Transmit Shape Enable - If there is only one shaping queue then it must be priority 3." "0,1" bitfld.long 0x0 19. " P2_PRI1_SHAPE_EN ,Port 2 Queue Priority 1 Transmit Shape Enable - If there are three shaping queues all three bits should be set." "0,1" textline " " bitfld.long 0x0 20. " P2_PRI2_SHAPE_EN ,Port 2 Queue Priority 2 Transmit Shape Enable - If there are two shaping queues then they must be priorities 3 and 2." "0,1" bitfld.long 0x0 21. " P2_PRI3_SHAPE_EN ,Port 2 Queue Priority 3 Transmit Shape Enable - If there is only one shaping queue then it must be priority 3." "0,1" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "CPSW_SOFT_IDLE,Software idle" bitfld.long 0x0 0. " SOFT_IDLE ,Software Idle - Setting this bit causes the switch fabric to stop forwarding packets at the next start of packet." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "CPSW_THRU_RATE,Throughput rate" bitfld.long 0x0 0.--3. " CPDMA_THRU_RATE ,CPDMA Switch FIFO receive through rate. This register value is the maximum throughput of the CPDMA host port to the crossbar SCR. The default is one 8-byte word for every 3 MAIN_CLK periods maximum." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0 4.--11. 1. " RESERVED ," textline " " bitfld.long 0x0 12.--15. " SL_RX_THRU_RATE ,CPGMAC_SL Switch FIFO receive through rate. This register value is the maximum throughput of the ethernet ports to the crossbar SCR. The default is one 8-byte word for every 3 MAIN_CLK periods maximum." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "CPSW_GAP_THRESH,CPGMAC_SL short gap threshold" bitfld.long 0x0 0.--4. " GAP_THRESH ,CPGMAC_SL Short Gap Threshold - This is the CPGMAC_SL associated FIFO transmit block usage value for triggering TX_SHORT_GAP." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CPSW_TX_START_WDS,Transmit start words" hexmask.long.word 0x0 0.--10. 1. " TX_START_WDS ,FIFO Packet Transmit (egress) Start Words. This value is the number of required packet words in the transmit FIFO before the packet egress will begin. This value is non-zero to preclude underrun. Decimal 32 is the recommended value. It should not be increased unnecessairly to prevent adding to the switch latency." hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "CPSW_FLOW_CONTROL,Flow control" bitfld.long 0x0 0. " P0_FLOW_EN ,Port 0 Receive flow control enable" "0,1" bitfld.long 0x0 1. " P1_FLOW_EN ,Port 1 Receive flow control enable" "0,1" textline " " bitfld.long 0x0 2. " P2_FLOW_EN ,Port 2 Receive flow control enable" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "CPSW_VLAN_LTYPE,LTYPE1 and LTYPE 2 Register" hexmask.long.word 0x0 0.--15. 1. " VLAN_LTYPE1 ,Time Sync VLAN LTYPE1 This VLAN LTYPE value is used for tx and rx. This is the outer VLAN if both are present." hexmask.long.word 0x0 16.--31. 1. " VLAN_LTYPE2 ,Time Sync VLAN LTYPE2 This VLAN LTYPE value is used for tx and rx. This is the inner VLAN if both are present." group.byte 0x2C++0x3 line.long 0x0 "CPSW_TS_LTYPE,VLAN_LTYPE1 and VLAN_LTYPE2 Register" hexmask.long.word 0x0 0.--15. 1. " TS_LTYPE1 ,Time Sync LTYPE1 This is an ethertype value to match for tx and rx time sync packets." hexmask.long.word 0x0 16.--31. 1. " TS_LTYPE2 ,Time Sync LTYPE2 This is an Ethertype value to match for tx and rx time sync packets." group.byte 0x30++0x3 line.long 0x0 "CPSW_DLR_LTYPE,DLR LTYPE register" hexmask.long.word 0x0 0.--15. 1. " DLR_LTYPE ,DLR LTYPE. This is the ethertype value to match for DLR packets." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "CPSW_EEE_PRESCALE,EEE Pre-scale Counter Load Value Register" hexmask.long.word 0x0 0.--11. 1. " EEE_PRESCALE ,Energy Efficient Ethernet Pre-scale count load value  This value is loaded into the EEE pre-scale counter each time the pre-scale count decrements to zero. The EEE counters are enabled to decrement each time the pre-scale counter reaches zero (and the EEE counters are enabled to count time). If this value is zero then the EEE counters decrement on every clock. If this value is 0x001 then the counters decrement on every other clock (and so on)." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," width 0x0B tree.end tree "STATERAM" base ad:0x48484A00 width 9. group.byte 0x0++0x3 line.long 0x0 "TX0_HDP,CPDMA_STATERAM TX channel 0 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " TX_HDP ,TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x4++0x3 line.long 0x0 "TX1_HDP,CPDMA_STATERAM TX channel 1 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " TX_HDP ,TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x8++0x3 line.long 0x0 "TX2_HDP,CPDMA_STATERAM TX channel 2 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " TX_HDP ,TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0xC++0x3 line.long 0x0 "TX3_HDP,CPDMA_STATERAM TX channel 3 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " TX_HDP ,TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x10++0x3 line.long 0x0 "TX4_HDP,CPDMA_STATERAM TX channel 4 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " TX_HDP ,TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x14++0x3 line.long 0x0 "TX5_HDP,CPDMA_STATERAM TX channel 5 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " TX_HDP ,TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x18++0x3 line.long 0x0 "TX6_HDP,CPDMA_STATERAM TX channel 6 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " TX_HDP ,TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x1C++0x3 line.long 0x0 "TX7_HDP,CPDMA_STATERAM TX channel 7 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " TX_HDP ,TX Channel (0..7) DMA Head Descriptor Pointer - Writing a TX DMA Buffer Descriptor address to a head pointer location initiates TX DMA operations in the queue for the selected channel. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x20++0x3 line.long 0x0 "RX0_HDP,CPDMA_STATERAM RX 0 channel 0 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " RX_HDP ,RX DMA Head Descriptor Pointer - Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x24++0x3 line.long 0x0 "RX1_HDP,CPDMA_STATERAM RX 1 channel 1 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " RX_HDP ,RX DMA Head Descriptor Pointer - Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x28++0x3 line.long 0x0 "RX2_HDP,CPDMA_STATERAM RX 2 channel 2 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " RX_HDP ,RX DMA Head Descriptor Pointer - Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x2C++0x3 line.long 0x0 "RX3_HDP,CPDMA_STATERAM RX 3 channel 3 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " RX_HDP ,RX DMA Head Descriptor Pointer - Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x30++0x3 line.long 0x0 "RX4_HDP,CPDMA_STATERAM RX 4 channel 4 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " RX_HDP ,RX DMA Head Descriptor Pointer - Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x34++0x3 line.long 0x0 "RX5_HDP,CPDMA_STATERAM RX 5 channel 5 head descriptor pointer" hexmask.long 0x0 0.--31. 1. " RX_HDP ,RX DMA Head Descriptor Pointer - Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x38++0x3 line.long 0x0 "RX6_HDP,CPDMA_STATERAM RX 6 channel 6 head desc pointer" hexmask.long 0x0 0.--31. 1. " RX_HDP ,RX DMA Head Descriptor Pointer - Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x3C++0x3 line.long 0x0 "RX7_HDP,CPDMA_STATERAM RX 7 channel 7 head desc pointer" hexmask.long 0x0 0.--31. 1. " RX_HDP ,RX DMA Head Descriptor Pointer - Writing an RX DMA Buffer Descriptor address to this location allows RX DMA operations in the selected channel when a channel frame is received. Writing to these locations when they are non-zero is an error (except at reset). Host software must initialize these locations to zero on reset." group.byte 0x40++0x3 line.long 0x0 "TX0_CP,CPDMA_STATERAM TX channel 0 completion pointer register" hexmask.long 0x0 0.--31. 1. " TX_CP ,Tx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted." group.byte 0x44++0x3 line.long 0x0 "TX1_CP,CPDMA_STATERAM TX channel 1 completion pointer register" hexmask.long 0x0 0.--31. 1. " TX_CP ,Tx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted." group.byte 0x48++0x3 line.long 0x0 "TX2_CP,CPDMA_STATERAM TX channel 2 completion pointer register" hexmask.long 0x0 0.--31. 1. " TX_CP ,Tx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted." group.byte 0x4C++0x3 line.long 0x0 "TX3_CP,CPDMA_STATERAM TX channel 3 completion pointer register" hexmask.long 0x0 0.--31. 1. " TX_CP ,Tx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted." group.byte 0x50++0x3 line.long 0x0 "TX4_CP,CPDMA_STATERAM TX channel 4 completion pointer register" hexmask.long 0x0 0.--31. 1. " TX_CP ,Tx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted." group.byte 0x54++0x3 line.long 0x0 "TX5_CP,CPDMA_STATERAM TX channel 5 completion pointer register" hexmask.long 0x0 0.--31. 1. " TX_CP ,Tx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted." group.byte 0x58++0x3 line.long 0x0 "TX6_CP,CPDMA_STATERAM TX channel 6 completion pointer register" hexmask.long 0x0 0.--31. 1. " TX_CP ,Tx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted." group.byte 0x5C++0x3 line.long 0x0 "TX7_CP,CPDMA_STATERAM TX channel 7 completion pointer register" hexmask.long 0x0 0.--31. 1. " TX_CP ,Tx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted." group.byte 0x60++0x3 line.long 0x0 "RX0_CP,CPDMA_STATERAM RX channel 0 completion pointer register" hexmask.long 0x0 0.--31. 1. " RX_CP ,Rx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted. Note: The value read is the completion pointer (interrupt acknowledge) value that was written by the CPDMA DMA controller (port). The value written to this register by the host is compared with the value that the port wrote to determine if the interrupt should remain asserted. The value written is not actually stored in the location. The interrupt is deasserted if the two values are equal." group.byte 0x64++0x3 line.long 0x0 "RX1_CP,CPDMA_STATERAM RX channel 1 completion pointer register" hexmask.long 0x0 0.--31. 1. " RX_CP ,Rx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted. Note: The value read is the completion pointer (interrupt acknowledge) value that was written by the CPDMA DMA controller (port). The value written to this register by the host is compared with the value that the port wrote to determine if the interrupt should remain asserted. The value written is not actually stored in the location. The interrupt is deasserted if the two values are equal." group.byte 0x68++0x3 line.long 0x0 "RX2_CP,CPDMA_STATERAM RX channel 2 completion pointer register" hexmask.long 0x0 0.--31. 1. " RX_CP ,Rx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted. Note: The value read is the completion pointer (interrupt acknowledge) value that was written by the CPDMA DMA controller (port). The value written to this register by the host is compared with the value that the port wrote to determine if the interrupt should remain asserted. The value written is not actually stored in the location. The interrupt is deasserted if the two values are equal." group.byte 0x6C++0x3 line.long 0x0 "RX3_CP,CPDMA_STATERAM RX channel 3 completion pointer register" hexmask.long 0x0 0.--31. 1. " RX_CP ,Rx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted. Note: The value read is the completion pointer (interrupt acknowledge) value that was written by the CPDMA DMA controller (port). The value written to this register by the host is compared with the value that the port wrote to determine if the interrupt should remain asserted. The value written is not actually stored in the location. The interrupt is deasserted if the two values are equal." group.byte 0x70++0x3 line.long 0x0 "RX4_CP,CPDMA_STATERAM RX channel 4 completion pointer register" hexmask.long 0x0 0.--31. 1. " RX_CP ,Rx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted. Note: The value read is the completion pointer (interrupt acknowledge) value that was written by the CPDMA DMA controller (port). The value written to this register by the host is compared with the value that the port wrote to determine if the interrupt should remain asserted. The value written is not actually stored in the location. The interrupt is deasserted if the two values are equal." group.byte 0x74++0x3 line.long 0x0 "RX5_CP,CPDMA_STATERAM RX channel 5 completion pointer register" hexmask.long 0x0 0.--31. 1. " RX_CP ,Rx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted. Note: The value read is the completion pointer (interrupt acknowledge) value that was written by the CPDMA DMA controller (port). The value written to this register by the host is compared with the value that the port wrote to determine if the interrupt should remain asserted. The value written is not actually stored in the location. The interrupt is deasserted if the two values are equal." group.byte 0x78++0x3 line.long 0x0 "RX6_CP,CPDMA_STATERAM RX channel 6 completion pointer register" hexmask.long 0x0 0.--31. 1. " RX_CP ,Rx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted. Note: The value read is the completion pointer (interrupt acknowledge) value that was written by the CPDMA DMA controller (port). The value written to this register by the host is compared with the value that the port wrote to determine if the interrupt should remain asserted. The value written is not actually stored in the location. The interrupt is deasserted if the two values are equal." group.byte 0x7C++0x3 line.long 0x0 "RX7_CP,CPDMA_STATERAM RX channel 7 completion pointer register" hexmask.long 0x0 0.--31. 1. " RX_CP ,Rx Completion Pointer Register - This register is written by the host with the buffer descriptor address for the last buffer processed by the host during interrupt processing. The port uses the value written to determine if the interrupt should be deasserted. Note: The value read is the completion pointer (interrupt acknowledge) value that was written by the CPDMA DMA controller (port). The value written to this register by the host is compared with the value that the port wrote to determine if the interrupt should remain asserted. The value written is not actually stored in the location. The interrupt is deasserted if the two values are equal." width 0x0B tree.end tree "CPTS" base ad:0x48484C00 width 21. group.byte 0x0++0x3 line.long 0x0 "CPTS_IDVER,CPTS revision" hexmask.long 0x0 0.--31. 1. " REVISION ,CPTS revision value" group.byte 0x4++0x3 line.long 0x0 "CPTS_CONTROL,Time sync control register" bitfld.long 0x0 0. " CPTS_EN ,Time Sync Enable - When disabled (cleared to zero), the RCLK domain is held in reset. 0 - Time Sync Disabled 1 - Time Sync Enabled" "0,1" bitfld.long 0x0 1. " INT_TEST ,Interrupt Test - When set, this bit allows the raw interrupt to be written to facilitate interrupt test." "0,1" textline " " bitfld.long 0x0 2.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 8. " HW1_TS_PUSH_EN ,Hardware push 1 enable" "0,1" textline " " bitfld.long 0x0 9. " HW2_TS_PUSH_EN ,Hardware push 2 enable" "0,1" bitfld.long 0x0 10. " HW3_TS_PUSH_EN ,Hardware push 3 enable" "0,1" textline " " bitfld.long 0x0 11. " HW4_TS_PUSH_EN ,Hardware push 4 enable" "0,1" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "CPTS_TS_PUSH,Time stamp event push register" bitfld.long 0x0 0. " TS_PUSH ,Time stamp event push - When a logic high is written to this bit a time stamp event is pushed onto the event FIFO. The time stamp value is the time of the write of this register, not the time of the event read. The time stamp value can then be read on interrupt via the event registers. Software should not push a second time stamp event onto the event FIFO until the first time stamp value has been read from the event FIFO (there should be only one time stamp event in the event FIFO at any given time). This bit is write only and always reads zero." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "CPTS_TS_LOAD_VAL,Time stamp load value register" hexmask.long 0x0 0.--31. 1. " TS_LOAD_VAL ,Time Stamp Load Value - Writing theCPTS_TS_LOAD_EN[0] TS_LOAD_EN bit causes the value contained in this register to be written into the time stamp. The time stamp value is read by initiating a time stamp push event, not by reading this register. When reading this register, the value read is not the time stamp, but is the value that was last written to this register." group.byte 0x14++0x3 line.long 0x0 "CPTS_TS_LOAD_EN,Time stamp load enable register" bitfld.long 0x0 0. " TS_LOAD_EN ,Time Stamp Load - Writing a one to this bit enables the time stamp value to be written via theCPTS_TS_LOAD_VAL register. This feature is included for test purposes. This bit is write only." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CPTS_INTSTAT_RAW,Time sync interrupt status raw register" bitfld.long 0x0 0. " TS_PEND_RAW ,TS_PEND_RAW int read (before enable). Writable whenCPTS_CONTROL[1] INT_TEST = 1. A one in this bit indicates that there is one or more events in the event FIFO." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "CPTS_INTSTAT_MASKED,Time sync interrupt status masked register" bitfld.long 0x0 0. " TS_PEND ,TS_PEND masked interrupt read (after enable)." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "CPTS_INT_ENABLE,Time sync interrupt enable register" bitfld.long 0x0 0. " TS_PEND_EN ,TS_PEND masked interrupt enable." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "CPTS_EVENT_POP,Event interrupt pop register" bitfld.long 0x0 0. " EVENT_POP ,Event Pop - When a logic high is written to this bit an event is popped off the event FIFO. The event FIFO pop occurs as part of the interrupt process after the event has been read in theCPTS_EVENT_LOW and CPTS_EVENT_HIGH registers. Popping an event discards the event and causes the next event, if any, to be moved to the top of the FIFO ready to be read by software on interrupt." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "CPTS_EVENT_LOW,Lower 32-bits of the event value" hexmask.long 0x0 0.--31. 1. " TIME_STAMP ,Time Stamp - The timestamp is valid for transmit, receive, and time stamp push event types. The timestamp value is not valid for counter roll event types." group.byte 0x38++0x3 line.long 0x0 "CPTS_EVENT_HIGH,Upper 32-bits of the event value" hexmask.long.word 0x0 0.--15. 1. " SEQUENCE_ID ,Sequence ID - The 16-bit sequence id is the value that was contained in an ethernet transmit or receivetime sync packet. This field is valid only for ethernet transmit or receive events." bitfld.long 0x0 16.--19. " MESSAGE_TYPE ,Message type - The message type value that was contained in an ethernet transmit or receive time sync packet. This field is valid only for ethernet transmit or receive events." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 20.--23. " EVENT_TYPE ,Time Sync Event Type 0x0 - Time Stamp Push Event 0x1 - Time Stamp Rollover Event 0x2 - Time Stamp Half Rollover Event 0x3 - Hardware Time Stamp Push Event 0x4 - Ethernet Receive Event 0x5 - Ethernet Transmit Event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24.--28. " PORT_NUMBER ,Port Number - indicates the port number of an ethernet event or the hardware push pin number (1 to 4)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 29.--31. " RESERVED ," "0,1,2,3,4,5,6,7" width 0x0B tree.end tree "ALE" base ad:0x48484D00 width 18. group.byte 0x0++0x3 line.long 0x0 "ALE_IDVER,ADDRESS LOOKUP ENGINE revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,ALE Revision Value" group.byte 0x8++0x3 line.long 0x0 "ALE_CONTROL,Address lookup engine control register" bitfld.long 0x0 0. " ENABLE_RATE_LIMIT ,Enable Broadcast and Multicast Rate Limit 0 - Broadcast/Multicast rates not limited 1 - Broadcast/Multicast packet reception limited to the port control register rate limit fields." "0,1" bitfld.long 0x0 1. " ENABLE_AUTH_MODE ,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software. There are no learned address in authorization mode and the packet will be dropped if the source address is not found (and the destination address is not a multicast address with the super table entry bit set). 0 - The ALE is not in MAC authorization mode 1 - The ALE is in MAC authorization mode" "0,1" textline " " bitfld.long 0x0 2. " VLAN_AWARE ,ALE VLAN Aware - Determines what is done if VLAN not found. 0 - Flood if VLAN not found 1 - Drop packet if VLAN not found" "0,1" bitfld.long 0x0 3. " RATE_LIMIT_TX ,Rate Limit Transmit mode - 0 - Broadcast and multicast rate limit counters are received port based 1 - Broadcast and multicast rate limit counters are transmit port based." "0,1" textline " " bitfld.long 0x0 4. " BYPASS ,ALE Bypass - When set, all packets received on ports 0 and 1 are sent to the host (only to the host)." "0,1" bitfld.long 0x0 5. " ENABLE_OUI_DENY ,Enable OUI Deny Mode - When set this bit indicates that a packet with a non OUI table entry matching source address will be dropped to the host unless the destination address matches a multicast table entry with the super bit set." "0,1" textline " " bitfld.long 0x0 6. " EN_VID0_MODE ,Enable VLAN ID = 0 Mode 0 - Process the packet with VID = PORT_VLAN[11:0]. 1 - Process the packet with VID = 0." "0,1" bitfld.long 0x0 7. " LEARN_NO_VID ,Learn No VID - 0 - VID is learned with the source address 1 - VID is not learned with the source address (source address is not tied to VID)." "0,1" textline " " bitfld.long 0x0 8. " EN_P0_UNI_FLOOD ,Enable Port 0 (Host Port) unicast flood 0 - do not flood unknown unicast packets to host port (p0) 1 - flood unknown unicast packets to host port (p0)" "0,1" hexmask.long.tbyte 0x0 9.--28. 1. " RESERVED ," textline " " bitfld.long 0x0 29. " AGE_OUT_NOW ,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit. This bit is cleared when the age out process has completed. This bit may be read. The age out process takes 4096 clocks best case (no ale packet processing during ageout) and 66550 clocks absolute worst case." "0,1" bitfld.long 0x0 30. " CLEAR_TABLE ,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero. Software must perform a clear table operation as part of the ALE setup/configuration process. Setting this bit causes all ALE accesses to be held up for 64 clocks while the clear is performed. Access to all ALE registers will be blocked (wait states) until the 64 clocks have completed. This bit cannot be read as one because the read is blocked until the clear table is completed at which time this bit is cleared to zero." "0,1" textline " " bitfld.long 0x0 31. " ENABLE_ALE ,Enable ALE - 0 - Drop all packets 1 - Enable ALE packet processing" "0,1" group.byte 0x10++0x3 line.long 0x0 "ALE_PRESCALE,Address lookup engine prescale register" hexmask.long.tbyte 0x0 0.--19. 1. " PRESCALE ,ALE Prescale Register - The input clock is divided by this value for use in the multicast/broadcast rate limiters. The minimum operating value is 0x10. The prescaler is off when the value is zero." hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "ALE_UNKNOWN_VLAN,Address lookup engine unknown vlan register" bitfld.long 0x0 0.--5. " UNKNOWN_VLAN_MEMBER_LIST ,Unknown VLAN Member List" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8.--13. " UNKNOWN_MCAST_FLOOD_MASK ,Unknown VLAN Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--21. " UNKNOWN_REG_MCAST_FLOOD_MASK ,Unknown VLAN Registered Multicast Flood Mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24.--29. " UNKNOWN_FORCE_UNTAGGED_EGRESS ,Unknown VLAN Force Untagged Egress." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x20++0x3 line.long 0x0 "ALE_TBLCTL,Address lookup engine table control" hexmask.long.word 0x0 0.--9. 1. " ENTRY_POINTER ,Table Entry Pointer - The entry_pointer contains the table entry value that will be read/written with accesses to the table word registers." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " WRITE_RDZ ,Write Bit - This bit is always read as zero. Writing a 1 to this bit causes the three table word register values to be written to the entry_pointer location in the address table. Writing a 0 to this bit causes the three table word register values to be loaded from the entry_pointer location in the address table so that they may be subsequently read. A read of any ALE address location will be stalled until the read or write has completed." "0,1" group.byte 0x34++0x3 line.long 0x0 "ALE_TBLW2,Address lookup engine table word 2 register" hexmask.long.byte 0x0 0.--7. 1. " ENTRY71_64 ,Table entry bits 71:64" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "ALE_TBLW1,Address lookup engine table word 1 register" hexmask.long 0x0 0.--31. 1. " ENTRY63_32 ,Table entry bits 63:32" group.byte 0x3C++0x3 line.long 0x0 "ALE_TBLW0,Address lookup engine table word 0 register" hexmask.long 0x0 0.--31. 1. " ENTRY31_0 ,Table entry bits 31:0" group.byte 0x40++0x3 line.long 0x0 "ALE_PORTCTL0,Address lookup engine port 0 control register" bitfld.long 0x0 0.--1. " PORT_STATE ,Port State 0x0 - Disabled 0x1 - Blocked 0x2 - Learn 0x3 - Forward" "0,1,2,3" bitfld.long 0x0 2. " DROP_UNTAGGED ,Drop Untagged Packets - Drop non-VLAN tagged ingress packets." "0,1" textline " " bitfld.long 0x0 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check - If VLAN not found then drop the packet. Packets with an unknown (default) VLAN will be dropped." "0,1" bitfld.long 0x0 4. " NO_LEARN ,No Learn Mode - When set the port is disabled from learning an address." "0,1" textline " " bitfld.long 0x0 5. " NO_SA_UPDATE ,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry." "0,1" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Multicast rate limiting is enabled by a non-zero value in this field." hexmask.long.byte 0x0 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Broadcast rate limiting is enabled by a non-zero value in this field" group.byte 0x44++0x3 line.long 0x0 "ALE_PORTCTL1,Address lookup engine port 1 control register" bitfld.long 0x0 0.--1. " PORT_STATE ,Port State 0x0 - Disabled 0x1 - Blocked 0x2 - Learn 0x3 - Forward" "0,1,2,3" bitfld.long 0x0 2. " DROP_UNTAGGED ,Drop Untagged Packets - Drop non-VLAN tagged ingress packets." "0,1" textline " " bitfld.long 0x0 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check - If VLAN not found then drop the packet. Packets with an unknown (default) VLAN will be dropped." "0,1" bitfld.long 0x0 4. " NO_LEARN ,No Learn Mode - When set the port is disabled from learning an address." "0,1" textline " " bitfld.long 0x0 5. " NO_SA_UPDATE ,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry." "0,1" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Multicast rate limiting is enabled by a non-zero value in this field." hexmask.long.byte 0x0 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Broadcast rate limiting is enabled by a non-zero value in this field" group.byte 0x48++0x3 line.long 0x0 "ALE_PORTCTL2,Address lookup engine port 2 control register" bitfld.long 0x0 0.--1. " PORT_STATE ,Port State 0x0 - Disabled 0x1 - Blocked 0x2 - Learn 0x3 - Forward" "0,1,2,3" bitfld.long 0x0 2. " DROP_UNTAGGED ,Drop Untagged Packets - Drop non-VLAN tagged ingress packets." "0,1" textline " " bitfld.long 0x0 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check - If VLAN not found then drop the packet. Packets with an unknown (default) VLAN will be dropped." "0,1" bitfld.long 0x0 4. " NO_LEARN ,No Learn Mode - When set the port is disabled from learning an address." "0,1" textline " " bitfld.long 0x0 5. " NO_SA_UPDATE ,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry." "0,1" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Multicast rate limiting is enabled by a non-zero value in this field." hexmask.long.byte 0x0 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Broadcast rate limiting is enabled by a non-zero value in this field" group.byte 0x4C++0x3 line.long 0x0 "ALE_PORTCTL3,Address lookup engine port 3 control register" bitfld.long 0x0 0.--1. " PORT_STATE ,Port State 0x0 - Disabled 0x1 - Blocked 0x2 - Learn 0x3 - Forward" "0,1,2,3" bitfld.long 0x0 2. " DROP_UNTAGGED ,Drop Untagged Packets - Drop non-VLAN tagged ingress packets." "0,1" textline " " bitfld.long 0x0 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check - If VLAN not found then drop the packet. Packets with an unknown (default) VLAN will be dropped." "0,1" bitfld.long 0x0 4. " NO_LEARN ,No Learn Mode - When set the port is disabled from learning an address." "0,1" textline " " bitfld.long 0x0 5. " NO_SA_UPDATE ,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry." "0,1" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Multicast rate limiting is enabled by a non-zero value in this field." hexmask.long.byte 0x0 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Broadcast rate limiting is enabled by a non-zero value in this field" group.byte 0x50++0x3 line.long 0x0 "ALE_PORTCTL4,Address lookup engine port 4 control register" bitfld.long 0x0 0.--1. " PORT_STATE ,Port State 0x0 - Disabled 0x1 - Blocked 0x2 - Learn 0x3 - Forward" "0,1,2,3" bitfld.long 0x0 2. " DROP_UNTAGGED ,Drop Untagged Packets - Drop non-VLAN tagged ingress packets." "0,1" textline " " bitfld.long 0x0 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check - If VLAN not found then drop the packet. Packets with an unknown (default) VLAN will be dropped." "0,1" bitfld.long 0x0 4. " NO_LEARN ,No Learn Mode - When set the port is disabled from learning an address." "0,1" textline " " bitfld.long 0x0 5. " NO_SA_UPDATE ,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry." "0,1" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Multicast rate limiting is enabled by a non-zero value in this field." hexmask.long.byte 0x0 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Broadcast rate limiting is enabled by a non-zero value in this field" group.byte 0x54++0x3 line.long 0x0 "ALE_PORTCTL5,Address lookup engine port 5 control register" bitfld.long 0x0 0.--1. " PORT_STATE ,Port State 0x0 - Disabled 0x1 - Blocked 0x2 - Learn 0x3 - Forward" "0,1,2,3" bitfld.long 0x0 2. " DROP_UNTAGGED ,Drop Untagged Packets - Drop non-VLAN tagged ingress packets." "0,1" textline " " bitfld.long 0x0 3. " VID_INGRESS_CHECK ,VLAN ID Ingress Check - If VLAN not found then drop the packet. Packets with an unknown (default) VLAN will be dropped." "0,1" bitfld.long 0x0 4. " NO_LEARN ,No Learn Mode - When set the port is disabled from learning an address." "0,1" textline " " bitfld.long 0x0 5. " NO_SA_UPDATE ,No Souce Address Update - When set the port is disabled from updating the source port number in an ALE table entry." "0,1" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " MCAST_LIMIT ,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Multicast rate limiting is enabled by a non-zero value in this field." hexmask.long.byte 0x0 24.--31. 1. " BCAST_LIMIT ,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter. The port counters are decremented with each packet received or transmitted depending on whether the mode is transmit or receive. If the counters decrement to zero, then further packets are rate limited until the next prescale pulse. Broadcast rate limiting is enabled by a non-zero value in this field" width 0x0B tree.end tree "SL1" base ad:0x48484D80 width 15. group.byte 0x0++0x3 line.long 0x0 "SL_IDVER,CPGMAC_SL revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,CPGMAC_SL revision Value" group.byte 0x4++0x3 line.long 0x0 "SL_MACCONTROL,CPGMAC_SL MAC control register" bitfld.long 0x0 0. " FULLDUPLEX ,Full Duplex mode - Gigabit mode forces fullduplex mode regardless of whether the FULLDUPLEX bit is set or not. The FULLDUPLEX_OUT output is the value of this register bit 0 - half duplex mode 1 - full duplex mode" "0,1" bitfld.long 0x0 1. " LOOPBACK ,Loop Back Mode - Loopback mode forces internal fullduplex mode regardless of whether the FULLDUPLEX bit is set or not. The LOOPBACK bit should be changed only when GMII_EN is deasserted. 0 - Not looped back 1 - Loop Back Mode enabled" "0,1" textline " " bitfld.long 0x0 2. " MTEST ,Manufacturing Test mode - This bit must be set to allow writes to theSL_BOFFTEST and SL_RX_PAUSE/SL_TX_PAUSE registers." "0,1" bitfld.long 0x0 3. " RX_FLOW_EN ,Receive Flow Control Enable - 0 - Receive Flow Control Disabled Half-duplex mode - No flow control generated collisions are sent. Full-duplex mode - No outgoing pause frames are sent. 1 - Receive Flow Control Enabled Half-duplex mode - Collisions are initiated when receive flow control is triggered. Full-duplex mode - Outgoing pause frames are sent when receive flow control is triggered." "0,1" textline " " bitfld.long 0x0 4. " TX_FLOW_EN ,Transmit Flow Control Enable - Determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode regardless of this bit setting. The RX_MBP_Enable bits determine whether or not received pause frames are transferred to memory. 0 - Transmit Flow Control Disabled. Full-duplex mode - Incoming pause frames are not acted upon. 1 - Transmit Flow Control Enabled . Full-duplex mode - Incoming pause frames are acted upon." "0,1" bitfld.long 0x0 5. " GMII_EN ,GMII Enable - 0 - GMII RX and TX held in reset. 1 - GMII RX and TX released from reset." "0,1" textline " " bitfld.long 0x0 6. " TX_PACE ,Transmit Pacing Enable 0 - Transmit Pacing Disabled 1 - Transmit Pacing Enabled" "0,1" bitfld.long 0x0 7. " GIG ,Gigabit Mode - 0 - 10/100 mode 1 - Gigabit mode (full duplex only) The GIG_OUT output is the value of this bit." "0,1" textline " " bitfld.long 0x0 8.--9. " RESERVED ," "0,1,2,3" bitfld.long 0x0 10. " TX_SHORT_GAP_EN ,Transmit Short Gap Enable 0 - Transmit with a short IPG is disabled 1 - Transmit with a short IPG (when TX_SHORT_GAP input is asserted) is enabled." "0,1" textline " " bitfld.long 0x0 11. " CMD_IDLE ,Command Idle 0 - Idle not commanded 1 - Idle Commanded (read IDLE in SL_MACSTATUS)" "0,1" bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " IFCTL_A ,Interface Control A 0 - 10Mbps operation 1 - 100Mbps operation" "0,1" bitfld.long 0x0 16. " IFCTL_B ,Interface Control B (NOT FUNCTIONAL) 0 - 10Mbps operation 1 - 100Mbps operation" "0,1" textline " " bitfld.long 0x0 17. " GIG_FORCE ,Gigabit Mode Force - This bit is used to force the CPGMAC_SL into gigabit mode if the input GMII_MTCLK has been stopped by the PHY." "0,1" bitfld.long 0x0 18. " EXT_EN ,Control Enable - Enables the fullduplex and gigabit mode to be selected from the FULLDUPLEX_IN and GIG_IN input signals and not from the FULLDUPLEX and GIG bits in this register. The FULLDUPLEX_MODE bit reflects the actual fullduplex mode selected 0 - Use this setting for RMII/GMII mode . 1 - Use this setting for RGMII mode" "0,1" textline " " bitfld.long 0x0 19.--20. " RESERVED ," "0,1,2,3" bitfld.long 0x0 21. " TX_SHORT_GAP_LIM_EN ,Transmit Short Gap Limit Enable When set this bit limits the number of short gap packets transmitted to 100ppm. Each time a short gap packet is sent, a counter is loaded with 10,000 and decremented on each wireside clock. Another short gap packet will not be sent out until the counter decrements to zero. This mode is included to preclude the host from filling up the FIFO and sending every packet out with short gap which would violate the maximum number of packets per second allowed." "0,1" textline " " bitfld.long 0x0 22. " RX_CEF_EN ,RX Copy Error Frames Enable - Enables frames containing errors to be transferred to memory. The appropriate error bit will be set in the frame receive footer. Frames containing errors will be filtered when RX_CEF _EN is not set. 0 - Frames containing errors are filtered. 1 - Frames containing errors are transferred to memory." "0,1" bitfld.long 0x0 23. " RX_CSF_EN ,RX Copy Short Frames Enable - Enables frames or fragments shorter than 64 bytes to be copied to memory. Frames transferred to memory due to RX_CSF_EN will have the fragment or undersized bit set in their receive footer. Fragments are short frames that contain CRC/align/code errors and undersized are short frames without errors. 0 - Short frames are filtered 1 - Short frames are transferred to memory." "0,1" textline " " bitfld.long 0x0 24. " RX_CMF_EN ,RX Copy MAC Control Frames Enable - Enables MAC control frames to be transferred to memory. MAC control frames are normally acted upon (if enabled), but not copied to memory. MAC control frames that are pause frames will be acted upon if enabled in theSL_MACCONTROL register, regardless of the value of RX_CMF_EN. Frames transferred to memory due to RX_CMF_EN will have the control bit set in their EOP buffer descriptor. 0 - MAC control frames are filtered (but acted upon if enabled). 1 - MAC control frames are transferred to memory." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "SL_MACSTATUS,CPGMAC_SL MAC status register" bitfld.long 0x0 0. " TX_FLOW_ACT ,Transmit Flow Control Active - When asserted, this bit indicates that the pause time period is being observed for a received pause frame. No new transmissions will begin while this bit is asserted except for the transmission of pause frames. Any transmission in progress when this bit is asserted will complete." "0,1" bitfld.long 0x0 1. " RX_FLOW_ACT ,Receive Flow Control Active - When asserted, indicates that receive flow control is enabled and triggered." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ," "0,1" bitfld.long 0x0 3. " EXT_FULLDUPLEX ,External Fullduplex - This is the value of the EXT_FULLDUPLEX input bit." "0,1" textline " " bitfld.long 0x0 4. " EXT_GIG ,External GIG - This is the value of the EXT_GIG input bit." "0,1" hexmask.long 0x0 5.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " IDLE ,CPGMAC_SL IDLE - The CPGMAC_SL is in the idle state (valid after an idle command) 0 - The CPGMAC_SL is not in the idle state. 1 - The CPGMAC_SL is in the idle state." "0,1" group.byte 0xC++0x3 line.long 0x0 "SL_SOFT_RESET,CPGMAC_SL soft reset register" bitfld.long 0x0 0. " SOFT_RESET ,Software reset - Writing a one to this bit causes the CPGMAC_SL logic to be reset. After writing a one to this bit, it may be polled to determine if the reset has occurred. If a one is read, the reset has not yet occurred. If a zero is read then reset has occurred." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "SL_RX_MAXLEN,CPGMAC_SL RX Maximum length register" hexmask.long.word 0x0 0.--13. 1. " RX_MAXLEN ,RX Maximum Frame Length - This field determines the maximum length of a received frame. The reset value is 1518 (dec). Frames with byte counts greater than rx_maxlen are long frames. Long frames with no errors are oversized frames. Long frames with CRC, code, or alignment error are jabber frames. The maximum value is 16,383." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "SL_BOFFTEST,CPGMAC_SL backoff test register" hexmask.long.word 0x0 0.--9. 1. " TX_BACKOFF ,Backoff Count - This field allows the current value of the backoff counter to be observed for test purposes. This field is loaded automatically according to the backoff algorithm, and is decremented by one for each slot time after the collision." bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--15. " COLL_COUNT ,Collision Count - The number of collisions the current frame has experienced." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 16.--25. 1. " RNDNUM ,Backoff Random Number Generator - This field allows the Backoff Random Number Generator to be read (or written in test mode only). This field can be written only when mtest has previously been set. Reading this field returns the generator's current value. The value is reset to zero and begins counting on the clock after the deassertion of reset." textline " " bitfld.long 0x0 26.--30. " PACEVAL ,Pacing Register Current Value. A non-zero value in this field indicates that transmit pacing is active. A transmit frame collision or deferral causes PACEVAL to loaded with decimal 31, good frame transmissions (with no collisions or deferrals) cause PACEVAL to be decremented down to zero. When PACEVAL is nonzero, the transmitter delays 4 IPGs between new frame transmissions after each successfully transmitted frame that had no deferrals or collisions. Transmit pacing helps reduce 'capture' effects improving overall network bandwidth." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x18++0x3 line.long 0x0 "SL_RX_PAUSE,CPGMAC_SL receive pause timer register" hexmask.long.word 0x0 0.--15. 1. " RX_PAUSETIMER ,RX Pause Timer Value - This field allows the contents of the receive pause timer to be observed (and written in test mode). The receive pause timer is loaded with 0xFF00 when the CPGMAC_SL sends an outgoing pause frame (with pause time of 0xFFFF). The receive pause timer is decremented at slot time intervals. If the receive pause timer decrements to zero, then another outgoing pause frame will be sent and the load/decrement process will be repeated." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "SL_TX_PAUSE,CPGMAC_SL transmit pause timer register" hexmask.long.word 0x0 0.--15. 1. " TX_PAUSETIMER ,TX Pause Timer Value - This field allows the contents of the transmit pause timer to be observed (and written in test mode). The transmit pause timer is loaded by a received (incoming) pause frame, and then decremented, at slottime intervals, down to zero at which time CPGMAC_SL transmit frames are again enabled." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "SL_EMCONTROL,CPGMAC_SL emulation control register" bitfld.long 0x0 0. " FREE ,Emulation Free Bit. Emulation free bit. This bit is used in conjunction with SOFT bit to determine the emulation suspend mode." "0,1" bitfld.long 0x0 1. " SOFT ,Emulation Soft Bit. Emulation soft bit. This bit is used in conjunction with FREE bit to determine the emulation suspend mode. This bit has no effect if FREE = 1." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "SL_RX_PRI_MAP,CPGMAC_SL RX packet priority to header priority mapping register" bitfld.long 0x0 0.--2. " PRI0 ,Priority 0 - A packet priority of 0x0 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI1 ,Priority 1 - A packet priority of 0x1 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI2 ,Priority 2 - A packet priority of 0x2 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI3 ,Priority 3 - A packet priority of 0x3 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI4 ,Priority 4 - A packet priority of 0x4 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI5 ,Priority 5 - A packet priority of 0x5 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI6 ,Priority 6 - A packet priority of 0x6 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI7 ,Priority 7 - A packet priority of 0x7 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x28++0x3 line.long 0x0 "SL_TX_GAP,Transmit inter-packet gap register" hexmask.long.word 0x0 0.--8. 1. " TX_GAP ,Transmit Inter-Packet Gap" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "SL2" base ad:0x48484DC0 width 15. group.byte 0x0++0x3 line.long 0x0 "SL_IDVER,CPGMAC_SL revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,CPGMAC_SL revision Value" group.byte 0x4++0x3 line.long 0x0 "SL_MACCONTROL,CPGMAC_SL MAC control register" bitfld.long 0x0 0. " FULLDUPLEX ,Full Duplex mode - Gigabit mode forces fullduplex mode regardless of whether the FULLDUPLEX bit is set or not. The FULLDUPLEX_OUT output is the value of this register bit 0 - half duplex mode 1 - full duplex mode" "0,1" bitfld.long 0x0 1. " LOOPBACK ,Loop Back Mode - Loopback mode forces internal fullduplex mode regardless of whether the FULLDUPLEX bit is set or not. The LOOPBACK bit should be changed only when GMII_EN is deasserted. 0 - Not looped back 1 - Loop Back Mode enabled" "0,1" textline " " bitfld.long 0x0 2. " MTEST ,Manufacturing Test mode - This bit must be set to allow writes to theSL_BOFFTEST and SL_RX_PAUSE/SL_TX_PAUSE registers." "0,1" bitfld.long 0x0 3. " RX_FLOW_EN ,Receive Flow Control Enable - 0 - Receive Flow Control Disabled Half-duplex mode - No flow control generated collisions are sent. Full-duplex mode - No outgoing pause frames are sent. 1 - Receive Flow Control Enabled Half-duplex mode - Collisions are initiated when receive flow control is triggered. Full-duplex mode - Outgoing pause frames are sent when receive flow control is triggered." "0,1" textline " " bitfld.long 0x0 4. " TX_FLOW_EN ,Transmit Flow Control Enable - Determines if incoming pause frames are acted upon in full-duplex mode. Incoming pause frames are not acted upon in half-duplex mode regardless of this bit setting. The RX_MBP_Enable bits determine whether or not received pause frames are transferred to memory. 0 - Transmit Flow Control Disabled. Full-duplex mode - Incoming pause frames are not acted upon. 1 - Transmit Flow Control Enabled . Full-duplex mode - Incoming pause frames are acted upon." "0,1" bitfld.long 0x0 5. " GMII_EN ,GMII Enable - 0 - GMII RX and TX held in reset. 1 - GMII RX and TX released from reset." "0,1" textline " " bitfld.long 0x0 6. " TX_PACE ,Transmit Pacing Enable 0 - Transmit Pacing Disabled 1 - Transmit Pacing Enabled" "0,1" bitfld.long 0x0 7. " GIG ,Gigabit Mode - 0 - 10/100 mode 1 - Gigabit mode (full duplex only) The GIG_OUT output is the value of this bit." "0,1" textline " " bitfld.long 0x0 8.--9. " RESERVED ," "0,1,2,3" bitfld.long 0x0 10. " TX_SHORT_GAP_EN ,Transmit Short Gap Enable 0 - Transmit with a short IPG is disabled 1 - Transmit with a short IPG (when TX_SHORT_GAP input is asserted) is enabled." "0,1" textline " " bitfld.long 0x0 11. " CMD_IDLE ,Command Idle 0 - Idle not commanded 1 - Idle Commanded (read IDLE in SL_MACSTATUS)" "0,1" bitfld.long 0x0 12.--14. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15. " IFCTL_A ,Interface Control A 0 - 10Mbps operation 1 - 100Mbps operation" "0,1" bitfld.long 0x0 16. " IFCTL_B ,Interface Control B (NOT FUNCTIONAL) 0 - 10Mbps operation 1 - 100Mbps operation" "0,1" textline " " bitfld.long 0x0 17. " GIG_FORCE ,Gigabit Mode Force - This bit is used to force the CPGMAC_SL into gigabit mode if the input GMII_MTCLK has been stopped by the PHY." "0,1" bitfld.long 0x0 18. " EXT_EN ,Control Enable - Enables the fullduplex and gigabit mode to be selected from the FULLDUPLEX_IN and GIG_IN input signals and not from the FULLDUPLEX and GIG bits in this register. The FULLDUPLEX_MODE bit reflects the actual fullduplex mode selected 0 - Use this setting for RMII/GMII mode . 1 - Use this setting for RGMII mode" "0,1" textline " " bitfld.long 0x0 19.--20. " RESERVED ," "0,1,2,3" bitfld.long 0x0 21. " TX_SHORT_GAP_LIM_EN ,Transmit Short Gap Limit Enable When set this bit limits the number of short gap packets transmitted to 100ppm. Each time a short gap packet is sent, a counter is loaded with 10,000 and decremented on each wireside clock. Another short gap packet will not be sent out until the counter decrements to zero. This mode is included to preclude the host from filling up the FIFO and sending every packet out with short gap which would violate the maximum number of packets per second allowed." "0,1" textline " " bitfld.long 0x0 22. " RX_CEF_EN ,RX Copy Error Frames Enable - Enables frames containing errors to be transferred to memory. The appropriate error bit will be set in the frame receive footer. Frames containing errors will be filtered when RX_CEF _EN is not set. 0 - Frames containing errors are filtered. 1 - Frames containing errors are transferred to memory." "0,1" bitfld.long 0x0 23. " RX_CSF_EN ,RX Copy Short Frames Enable - Enables frames or fragments shorter than 64 bytes to be copied to memory. Frames transferred to memory due to RX_CSF_EN will have the fragment or undersized bit set in their receive footer. Fragments are short frames that contain CRC/align/code errors and undersized are short frames without errors. 0 - Short frames are filtered 1 - Short frames are transferred to memory." "0,1" textline " " bitfld.long 0x0 24. " RX_CMF_EN ,RX Copy MAC Control Frames Enable - Enables MAC control frames to be transferred to memory. MAC control frames are normally acted upon (if enabled), but not copied to memory. MAC control frames that are pause frames will be acted upon if enabled in theSL_MACCONTROL register, regardless of the value of RX_CMF_EN. Frames transferred to memory due to RX_CMF_EN will have the control bit set in their EOP buffer descriptor. 0 - MAC control frames are filtered (but acted upon if enabled). 1 - MAC control frames are transferred to memory." "0,1" hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "SL_MACSTATUS,CPGMAC_SL MAC status register" bitfld.long 0x0 0. " TX_FLOW_ACT ,Transmit Flow Control Active - When asserted, this bit indicates that the pause time period is being observed for a received pause frame. No new transmissions will begin while this bit is asserted except for the transmission of pause frames. Any transmission in progress when this bit is asserted will complete." "0,1" bitfld.long 0x0 1. " RX_FLOW_ACT ,Receive Flow Control Active - When asserted, indicates that receive flow control is enabled and triggered." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ," "0,1" bitfld.long 0x0 3. " EXT_FULLDUPLEX ,External Fullduplex - This is the value of the EXT_FULLDUPLEX input bit." "0,1" textline " " bitfld.long 0x0 4. " EXT_GIG ,External GIG - This is the value of the EXT_GIG input bit." "0,1" hexmask.long 0x0 5.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " IDLE ,CPGMAC_SL IDLE - The CPGMAC_SL is in the idle state (valid after an idle command) 0 - The CPGMAC_SL is not in the idle state. 1 - The CPGMAC_SL is in the idle state." "0,1" group.byte 0xC++0x3 line.long 0x0 "SL_SOFT_RESET,CPGMAC_SL soft reset register" bitfld.long 0x0 0. " SOFT_RESET ,Software reset - Writing a one to this bit causes the CPGMAC_SL logic to be reset. After writing a one to this bit, it may be polled to determine if the reset has occurred. If a one is read, the reset has not yet occurred. If a zero is read then reset has occurred." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "SL_RX_MAXLEN,CPGMAC_SL RX Maximum length register" hexmask.long.word 0x0 0.--13. 1. " RX_MAXLEN ,RX Maximum Frame Length - This field determines the maximum length of a received frame. The reset value is 1518 (dec). Frames with byte counts greater than rx_maxlen are long frames. Long frames with no errors are oversized frames. Long frames with CRC, code, or alignment error are jabber frames. The maximum value is 16,383." hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "SL_BOFFTEST,CPGMAC_SL backoff test register" hexmask.long.word 0x0 0.--9. 1. " TX_BACKOFF ,Backoff Count - This field allows the current value of the backoff counter to be observed for test purposes. This field is loaded automatically according to the backoff algorithm, and is decremented by one for each slot time after the collision." bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--15. " COLL_COUNT ,Collision Count - The number of collisions the current frame has experienced." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 16.--25. 1. " RNDNUM ,Backoff Random Number Generator - This field allows the Backoff Random Number Generator to be read (or written in test mode only). This field can be written only when mtest has previously been set. Reading this field returns the generator's current value. The value is reset to zero and begins counting on the clock after the deassertion of reset." textline " " bitfld.long 0x0 26.--30. " PACEVAL ,Pacing Register Current Value. A non-zero value in this field indicates that transmit pacing is active. A transmit frame collision or deferral causes PACEVAL to loaded with decimal 31, good frame transmissions (with no collisions or deferrals) cause PACEVAL to be decremented down to zero. When PACEVAL is nonzero, the transmitter delays 4 IPGs between new frame transmissions after each successfully transmitted frame that had no deferrals or collisions. Transmit pacing helps reduce 'capture' effects improving overall network bandwidth." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x18++0x3 line.long 0x0 "SL_RX_PAUSE,CPGMAC_SL receive pause timer register" hexmask.long.word 0x0 0.--15. 1. " RX_PAUSETIMER ,RX Pause Timer Value - This field allows the contents of the receive pause timer to be observed (and written in test mode). The receive pause timer is loaded with 0xFF00 when the CPGMAC_SL sends an outgoing pause frame (with pause time of 0xFFFF). The receive pause timer is decremented at slot time intervals. If the receive pause timer decrements to zero, then another outgoing pause frame will be sent and the load/decrement process will be repeated." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "SL_TX_PAUSE,CPGMAC_SL transmit pause timer register" hexmask.long.word 0x0 0.--15. 1. " TX_PAUSETIMER ,TX Pause Timer Value - This field allows the contents of the transmit pause timer to be observed (and written in test mode). The transmit pause timer is loaded by a received (incoming) pause frame, and then decremented, at slottime intervals, down to zero at which time CPGMAC_SL transmit frames are again enabled." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "SL_EMCONTROL,CPGMAC_SL emulation control register" bitfld.long 0x0 0. " FREE ,Emulation Free Bit. Emulation free bit. This bit is used in conjunction with SOFT bit to determine the emulation suspend mode." "0,1" bitfld.long 0x0 1. " SOFT ,Emulation Soft Bit. Emulation soft bit. This bit is used in conjunction with FREE bit to determine the emulation suspend mode. This bit has no effect if FREE = 1." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "SL_RX_PRI_MAP,CPGMAC_SL RX packet priority to header priority mapping register" bitfld.long 0x0 0.--2. " PRI0 ,Priority 0 - A packet priority of 0x0 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI1 ,Priority 1 - A packet priority of 0x1 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI2 ,Priority 2 - A packet priority of 0x2 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI3 ,Priority 3 - A packet priority of 0x3 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI4 ,Priority 4 - A packet priority of 0x4 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI5 ,Priority 5 - A packet priority of 0x5 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI6 ,Priority 6 - A packet priority of 0x6 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI7 ,Priority 7 - A packet priority of 0x7 is mapped (changed) to this value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x28++0x3 line.long 0x0 "SL_TX_GAP,Transmit inter-packet gap register" hexmask.long.word 0x0 0.--8. 1. " TX_GAP ,Transmit Inter-Packet Gap" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "WR" base ad:0x48485200 width 22. group.byte 0x0++0x3 line.long 0x0 "WR_IDVER,Subsystem wrapper revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,Wrapper revision value" group.byte 0x4++0x3 line.long 0x0 "WR_SOFT_RESET,Subsystem soft reset register" bitfld.long 0x0 0. " SOFT_RESET ,Software reset - Writing a one to this bit causes the CPGMACSS_R logic to be reset (INT, REGS, CPPI). Software reset occurs on the clock following the register bit write." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "WR_CONTROL,Subsystem control register" bitfld.long 0x0 0.--1. " MMR_IDLEMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of IDLE state." "0,1,2,3" bitfld.long 0x0 2.--3. " MMR_STDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state." "0,1,2,3" textline " " bitfld.long 0x0 4.--7. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SS_EEE_EN ,Subsystem Energy Efficient Ethernet enable 0: EEE disabled 1: EEE enabled" "0,1" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "WR_INT_CONTROL,Subsystem interrupt control" hexmask.long.word 0x0 0.--11. 1. " INT_PRESCALE ,Interrupt Counter Prescaler - The number of MAIN_CLK periods in 4us." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--21. " INT_PACE_EN ,Interrupt Pacing Enable INT_PACE_EN[0]  Enables RX_PULSE Pacing (0 is pacing bypass) INT_PACE_EN[1]  Enables TX_PULSE Pacing (0 is pacing bypass)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x0 22.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " INT_TEST ,Interrupt Test - Test bit to the interrupt pacing blocks" "0,1" group.byte 0x10++0x3 line.long 0x0 "WR_C0_RX_THRESH_EN,Subsystem core 0 receive threshold int enable register" hexmask.long.byte 0x0 0.--7. 1. " C0_RX_THRESH_EN ,Core 0 Receive Threshold Enable - Each bit in this register corresponds to the bit in the receive threshold interrupt that is enabled to generate an interrupt on RX_THRESH_PULSE." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "WR_C0_RX_EN,Subsystem core 0 receive interrupt enable register" hexmask.long.byte 0x0 0.--7. 1. " C0_RX_EN ,Core 0 Receive Enable - Each bit in this register corresponds to the bit in the rx interrupt that is enabled to generate an interrupt on RX_PULSE." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "WR_C0_TX_EN,Subsystem core 0 transmit interrupt enable register" hexmask.long.byte 0x0 0.--7. 1. " C0_TX_EN ,Core 0 Transmit Enable - Each bit in this register corresponds to the bit in the tx interrupt that is enabled to generate an interrupt on TX_PULSE." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "WR_C0_MISC_EN,Subsystem core 0 misc interrupt enable register" bitfld.long 0x0 0.--4. " C0_MISC_EN ,Core 0 Misc Enable - Each bit in this register corresponds to the miscellaneous interrupt (SPF2_PEND, SPF1_PEND, EVNT_PEND, STAT_PEND, HOST_PEND, MDIO_LINKINT, MDIO_USERINT) that is enabled to generate an interrupt on MISC_PULSE." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "WR_C0_RX_THRESH_STAT,Subsystem core 0 rx threshold masked int status register" hexmask.long.byte 0x0 0.--7. 1. " C0_RX_THRESH_STAT ,Core 0 Receive Threshold Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the receive threshold interrupt that is enabled and generating an interrupt on RX_THRESH_PULSE." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "WR_C0_RX_STAT,Subsystem core 0 rx interrupt masked int status register" hexmask.long.byte 0x0 0.--7. 1. " C0_RX_STAT ,Core 0 Receive Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the Rx interrupt that is enabled and generating an interrupt on RX_PULSE." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "WR_C0_TX_STAT,Subsystem core 0 tx interrupt masked int status register" hexmask.long.byte 0x0 0.--7. 1. " C0_TX_STAT ,Core 0 Transmit Masked Interrupt Status - Each bit in this read only register corresponds to the bit in the Tx interrupt that is enabled and generating an interrupt on TX_PULSE ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "WR_C0_MISC_STAT,Subsystem core 0 misc interrupt masked int status register" bitfld.long 0x0 0.--4. " C0_MISC_STAT ,Core 0 Misc Masked Interrupt Status - Each bit in this register corresponds to the miscellaneous interrupt (SPF2_PEND, SPF1_PEND, EVNT_PEND, STAT_PEND, HOST_PEND, MDIO_LINKINT, MDIO_USERINT) that is enabled and generating an interrupt on MISC_PULSE ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x70++0x3 line.long 0x0 "WR_C0_RX_IMAX,Subsystem core 0 receive interrupts per millisecond" bitfld.long 0x0 0.--5. " C0_RX_IMAX ,Core 0 Receive Interrupts per Millisecond - The maximum number of interrupts per millisecond generated on RX_PULSE if pacing is enabled for this interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x74++0x3 line.long 0x0 "WR_C0_TX_IMAX,Subsystem core 0 transmit interrupts per millisecond" bitfld.long 0x0 0.--5. " C0_TX_IMAX ,Core 0 Transmit Interrupts per Millisecond - The maximum number of interrupts per millisecond generated on TX_PULSE if pacing is enabled for this interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "WR_RGMII_CTL,RGMII control signal register" bitfld.long 0x0 0. " RGMII1_LINK ,RGMII1 Link Indicator - This is the CPRGMII link output signal 0 - RGMII1 link is down 1 - RGMII1 link is up" "0,1" bitfld.long 0x0 1.--2. " RGMII1_SPEED ,RGMII1 Speed - This is the CPRGMII speed output signal 0x0 - 10Mbps mode 0x1 - 100Mbps mode 0x2 - 1000Mbps (gig) mode 0x3 - reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " RGMII1_FULLDUPLEX ,RGMII1 Fullduplex - This is the CPRGMII fullduplex output signal. 0 - Half-duplex mode 1 - Full-duplex mode" "0,1" bitfld.long 0x0 4. " RGMII2_LINK ,RGMII2 Link Indicator - This is the CPRGMII link output signal 0 - RGMII2 link is down 1 - RGMII2 link is up" "0,1" textline " " bitfld.long 0x0 5.--6. " RGMII2_SPEED ,RGMII2 Speed - This is the CPRGMII speed output signal 0x0 - 10Mbps mode 0x1 - 100Mbps mode 0x2 - 1000Mbps (gig) mode 0x3 - reserved" "0,1,2,3" bitfld.long 0x0 7. " RGMII2_FULLDUPLEX ,RGMII 2 Fullduplex - This is the CPRGMII fullduplex output signal. 0 - Half-duplex mode 1 - Full-duplex mode" "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "WR_STATUS,Subsystem Status register" bitfld.long 0x0 0. " EEE_CLKSTOP_ACK ,CPSW_3G Clockstop Acknowledge  When asserted the subsystem gated clock is not turned on due to the CPSW_3G." "0,1" bitfld.long 0x0 1. " SPF1_CLKSTOP_ACK ,SPF1 Clockstop Acknowledge  When asserted the subsystem gated clock is not turned on due to SPF1." "0,1" textline " " bitfld.long 0x0 2. " SPF2_CLKSTOP_ACK ,SPF2 Clockstop Acknowledge  When asserted the subsystem gated clock is not turned on due to SPF2." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," width 0x0B tree.end tree "CPDMA" base ad:0x48484800 width 26. group.byte 0x0++0x3 line.long 0x0 "CPDMA_TX_IDVER,CPDMA_REGS TX revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,CPDMA TX Revision Value" group.byte 0x4++0x3 line.long 0x0 "CPDMA_TX_CONTROL,CPDMA_REGS TX control register" bitfld.long 0x0 0. " TX_EN ,TX Enable 0 - Disabled 1 - Enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "CPDMA_TX_TEARDOWN,CPDMA_REGS TX teardown register" bitfld.long 0x0 0.--2. " TX_TDN_CH ,Tx Teardown Channel - Transmit channel teardown is commanded by writing the encoded value of the transmit channel to be torn down. The teardown register is read as zero." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " TX_TDN_RDY ,Tx Teardown Ready - read as zero, but is always assumed to be one (unused)." "0,1" group.byte 0x10++0x3 line.long 0x0 "CPDMA_RX_IDVER,CPDMA_REGS RX revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,RX Revision Value" group.byte 0x14++0x3 line.long 0x0 "CPDMA_RX_CONTROL,CPDMA_REGS RX control register" bitfld.long 0x0 0. " RX_EN ,RX DMA Enable 0 - Disabled 1 - Enabled" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "CPDMA_RX_TEARDOWN,CPDMA_REGS RX teardown register" bitfld.long 0x0 0.--2. " RX_TDN_CH ,Rx Teardown Channel -Receive channel teardown is commanded by writing the encoded value of the receive channel to be torn down. The teardown register is read as zero." "0,1,2,3,4,5,6,7" hexmask.long 0x0 3.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " RX_TDN_RDY ,Teardown Ready - read as zero, but is always assumed to be one (unused)." "0,1" group.byte 0x1C++0x3 line.long 0x0 "CPDMA_SOFT_RESET,CPDMA_REGS soft reset register" bitfld.long 0x0 0. " SOFT_RESET ,Software reset - Writing a one to this bit causes the CPDMA logic to be reset. Software reset occurs when the RX and TX DMA Controllers are in an idle state to avoid locking up the VBUSP bus. After writing a one to this bit, it may be polled to determine if the reset has occurred. If a one is read, the reset has not yet occurred. If a zero is read then reset has occurred." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "CPDMA_DMACONTROL,CPDMA_REGS CPDMA control register" bitfld.long 0x0 0. " TX_PTYPE ,Transmit Queue Priority Type 0 - The queue uses a round robin scheme to select the next channel for transmission. 1 - The queue uses a fixed (channel 7 highest priority) priority scheme to select the next channel for transmission" "0,1" bitfld.long 0x0 1. " RX_OWNERSHIP ,Receive Ownership Write Bit Value. 0 - The CPDMA writes the receive ownership bit to zero at the end of packet processing as specified in CPPI 3.0. 1 - The CPDMA writes the receive ownership bit to one at the end of packet processing. Users who do not use the ownership mechanism can use this mode to preclude the necessity of software having to set this bit each time the buffer descriptor is used." "0,1" textline " " bitfld.long 0x0 2. " RX_OFFLEN_BLOCK ,Receive Offset/Length word write block. 0 - Do not block the DMA writes to the receive buffer descriptor offset/buffer length word. The offset/buffer length word is written as specified in CPPI 3.0. 1 - Block all CPDMA DMA controller writes to the receive buffer descriptor offset/buffer length words during CPPI packet processing. when this bit is set, the CPDMA will never write the third word to any receive buffer descriptor." "0,1" bitfld.long 0x0 3. " CMD_IDLE ,Command Idle 0 - Idle not commanded 1 - Idle Commanded (read IDLE in CPDMA_DMASTATUS)" "0,1" textline " " bitfld.long 0x0 4. " RX_CEF ,RX Copy Error Frames Enable - Enables DMA overrun frames to be transferred to memory (up to the point of overrun). The overrun error bit will be set in the frame EOP buffer descriptor. Overrun frame data will be filtered when RX_CEF is not set. Frames coming from the receive FIFO with other error bits set are not effected by this bit. 0 - Frames containing overrun errors are filtered. 1 - Frames containing overrun errors are transferred to memory." "0,1" bitfld.long 0x0 5.--7. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " hexmask.long.byte 0x0 8.--15. 1. " TX_RLIM ,Transmit Rate Limit Channel Bus 00000000 - no rate-limited channels 10000000 - channel 7 is rate-limited 11000000 - channels 7 downto 6 are rate-limited 11100000 - channels 7 downto 5 are rate-limited 11110000 - channels 7 downto 4 are rate-limited 11111000 - channels 7 downto 3 are rate-limited 11111100 - channels 7 downto 2 are rate-limited 11111110 - channels 7 downto 1 are rate-limited 11111111 - channels 7 downto 0 are rate-limited all others invalid - this bus must be set MSB towards LSB. TX_PTYPE must be set if any TX_RLIM bit is set for fixed priority." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "CPDMA_DMASTATUS,CPDMA_REGS CPDMA status register" hexmask.long.byte 0x0 0.--7. 1. " RESERVED ," bitfld.long 0x0 8.--10. " RX_ERR_CH ,RX Host Error Channel - This field indicates which RX channel the host error occurred on. This field is cleared to zero on a host read." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RX_HOST_ERR_CODE ,RX Host Error Code - This field is set to indicate CPDMA detected RX DMA related host errors. The host should read this field after a HOST_ERR_INT to determine the error. Host error Interrupts require hardware reset in order to recover. 0x0 - No error 0x1 - reserved 0x2 - Ownership bit not set in input buffer. 0x3 - reserved 0x4 - Zero Buffer Pointer. 0x5 - Zero buffer length on non-SOP descriptor 0x6 - SOP buffer length not greater than offset 0x7 - 1xF - reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--18. " TX_ERR_CH ,TX Host Error Channel - This field indicates which TX channel (if applicable) the host error occurred on. This field is cleared to zero on a host read." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--23. " TX_HOST_ERR_CODE ,TX Host Error Code - This field is set to indicate CPDMA detected TX DMA related host errors. The host should read this field after a HOST_ERR_INT to determine the error. Host error Interrupts require hardware reset in order to recover. A zero packet length is an error, but it is not detected. 0x0 - No error 0x1 - SOP error. 0x2 - Ownership bit not set in SOP buffer. 0x3 - Zero Next Buffer Descriptor Pointer Without EOP 0x4 - Zero Buffer Pointer. 0x5 - Zero Buffer Length 0x6 - Packet Length Error (sum of buffers is less than packet length) 0x7 - 1xF - reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0 24.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " IDLE ,Idle Status Bit - Indicates when set that the CPDMA is not transferring a packet on transmit or receive." "0,1" group.byte 0x28++0x3 line.long 0x0 "CPDMA_RX_BUFFER_OFFSET,CPDMA_REGS receive buffer offset" hexmask.long.word 0x0 0.--15. 1. " RX_BUFFER_OFFSET ,Receive Buffer Offset Value - The RX_BUFFER_OFFSET will be written by the port into each frame SOP buffer descriptor buffer_offset field. The frame data will begin after the rx_buffer_offset value of bytes. A value of 0x0000 indicates that there are no unused bytes at the beginning of the data and that valid data begins on the first byte of the buffer. A value of 0x000F (decimal 15) indicates that the first 15 bytes of the buffer are to be ignored by the port and that valid buffer data starts on byte 16 of the buffer. This value is used for all channels." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "CPDMA_EMCONTROL,CPDMA_REGS emulation control" bitfld.long 0x0 0. " FREE ,Emulation Free Bit" "0,1" bitfld.long 0x0 1. " SOFT ,Emulation Soft Bit" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "CPDMA_TX_PRI0_RATE,CPDMA_REGS transmit (ingress) priority 0 rate" hexmask.long.word 0x0 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " hexmask.long.word 0x0 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x34++0x3 line.long 0x0 "CPDMA_TX_PRI1_RATE,CPDMA_REGS transmit (ingress) priority 1 rate" hexmask.long.word 0x0 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " hexmask.long.word 0x0 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x38++0x3 line.long 0x0 "CPDMA_TX_PRI2_RATE,CPDMA_REGS transmit (ingress) priority 2 rate" hexmask.long.word 0x0 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " hexmask.long.word 0x0 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x3C++0x3 line.long 0x0 "CPDMA_TX_PRI3_RATE,CPDMA_REGS transmit (ingress) priority 3 rate" hexmask.long.word 0x0 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " hexmask.long.word 0x0 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x40++0x3 line.long 0x0 "CPDMA_TX_PRI4_RATE,CPDMA_REGS transmit (ingress) priority 4 rate" hexmask.long.word 0x0 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " hexmask.long.word 0x0 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x44++0x3 line.long 0x0 "CPDMA_TX_PRI5_RATE,CPDMA_REGS transmit (ingress) priority 5 rate" hexmask.long.word 0x0 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " hexmask.long.word 0x0 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x48++0x3 line.long 0x0 "CPDMA_TX_PRI6_RATE,CPDMA_REGS TRANSMIT (INGRESS) PRIORITY 6 RATE" hexmask.long.word 0x0 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " hexmask.long.word 0x0 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x4C++0x3 line.long 0x0 "CPDMA_TX_PRI7_RATE,CPDMA_REGS transmit (ingress) priority 7 rate" hexmask.long.word 0x0 0.--13. 1. " PRIN_SEND_CNT ,Priority ( 7:0) send count" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " hexmask.long.word 0x0 16.--29. 1. " PRIN_IDLE_CNT ,Priority ( 7:0) idle count" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x80++0x3 line.long 0x0 "CPDMA_TX_INTSTAT_RAW,CPDMA_INT TX interrupt status register (raw value)" bitfld.long 0x0 0. " TX0_PEND ,TX0_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 1. " TX1_PEND ,TX1_PEND raw int read (before mask)." "0,1" textline " " bitfld.long 0x0 2. " TX2_PEND ,TX2_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 3. " TX3_PEND ,TX3_PEND raw int read (before mask)." "0,1" textline " " bitfld.long 0x0 4. " TX4_PEND ,TX4_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 5. " TX5_PEND ,TX5_PEND raw int read (before mask)." "0,1" textline " " bitfld.long 0x0 6. " TX6_PEND ,TX6_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 7. " TX7_PEND ,TX7_PEND raw int read (before mask)." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x84++0x3 line.long 0x0 "CPDMA_TX_INTSTAT_MASKED,CPDMA_INT TX interrupt status register (masked value)" bitfld.long 0x0 0. " TX0_PEND ,TX0_PEND masked interrupt read." "0,1" bitfld.long 0x0 1. " TX1_PEND ,TX1_PEND masked interrupt read." "0,1" textline " " bitfld.long 0x0 2. " TX2_PEND ,TX2_PEND masked interrupt read." "0,1" bitfld.long 0x0 3. " TX3_PEND ,TX3_PEND masked interrupt read." "0,1" textline " " bitfld.long 0x0 4. " TX4_PEND ,TX4_PEND masked interrupt read." "0,1" bitfld.long 0x0 5. " TX5_PEND ,TX5_PEND masked interrupt read." "0,1" textline " " bitfld.long 0x0 6. " TX6_PEND ,TX6_PEND masked interrupt read." "0,1" bitfld.long 0x0 7. " TX7_PEND ,TX7_PEND masked interrupt read." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "CPDMA_TX_INTMASK_SET,CPDMA_INT TX interrupt mask set register" bitfld.long 0x0 0. " TX0_MASK ,TX Channel 0 Mask - Write one to enable interrupt." "0,1" bitfld.long 0x0 1. " TX1_MASK ,TX Channel 1 Mask - Write one to enable interrupt." "0,1" textline " " bitfld.long 0x0 2. " TX2_MASK ,TX Channel 2 Mask - Write one to enable interrupt." "0,1" bitfld.long 0x0 3. " TX3_MASK ,TX Channel 3 Mask - Write one to enable interrupt." "0,1" textline " " bitfld.long 0x0 4. " TX4_MASK ,TX Channel 4 Mask - Write one to enable interrupt." "0,1" bitfld.long 0x0 5. " TX5_MASK ,TX Channel 5 Mask - Write one to enable interrupt." "0,1" textline " " bitfld.long 0x0 6. " TX6_MASK ,TX Channel 6 Mask - Write one to enable interrupt." "0,1" bitfld.long 0x0 7. " TX7_MASK ,TX Channel 7 Mask - Write one to enable interrupt." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x8C++0x3 line.long 0x0 "CPDMA_TX_INTMASK_CLEAR,CPDMA_INT TX Interrupt mask clear register" bitfld.long 0x0 0. " TX0_MASK ,TX Channel 0 Mask - Write one to disable interrupt." "0,1" bitfld.long 0x0 1. " TX1_MASK ,TX Channel 1 Mask - Write one to disable interrupt." "0,1" textline " " bitfld.long 0x0 2. " TX2_MASK ,TX Channel 2 Mask - Write one to disable interrupt." "0,1" bitfld.long 0x0 3. " TX3_MASK ,TX Channel 3 Mask - Write one to disable interrupt." "0,1" textline " " bitfld.long 0x0 4. " TX4_MASK ,TX Channel 4 Mask - Write one to disable interrupt." "0,1" bitfld.long 0x0 5. " TX5_MASK ,TX Channel 5 Mask - Write one to disable interrupt." "0,1" textline " " bitfld.long 0x0 6. " TX6_MASK ,TX Channel 6 Mask - Write one to disable interrupt." "0,1" bitfld.long 0x0 7. " TX7_MASK ,TX Channel 7 Mask - Write one to disable interrupt." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x90++0x3 line.long 0x0 "CPDMA_IN_VECTOR,CPDMA_INT input vector (read only)" hexmask.long 0x0 0.--31. 1. " DMA_IN_VECTOR ,DMA Input Vector - The value of DMA_IN_VECTOR is reset to zero, but will change to the IN_VECTOR bus value one clock after reset is deasserted. Thereafter, this value will change to a new IN_VECTOR value one clock after the IN_VECTOR value changes." group.byte 0x94++0x3 line.long 0x0 "CPDMA_EOI_VECTOR,CPDMA_INT end of interrupt vector" bitfld.long 0x0 0.--4. " DMA_EOI_VECTOR ,DMA End of Interrupt Vector - The EOI_VECTOR( 4:0) pins reflect the value written to this location one MAIN_CLK cycle after a write to this location. The EOI_WR signal is asserted for a single clock cycle after a latency of two MAIN_CLK cycles when a write is performed to this location." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0xA0++0x3 line.long 0x0 "CPDMA_RX_INTSTAT_RAW,CPDMA_INT RX Interrupt status register (raw value)" bitfld.long 0x0 0. " RX0_PEND ,RX0_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 1. " RX1_PEND ,RX1_PEND raw int read (before mask)." "0,1" textline " " bitfld.long 0x0 2. " RX2_PEND ,RX2_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 3. " RX3_PEND ,RX3_PEND raw int read (before mask)." "0,1" textline " " bitfld.long 0x0 4. " RX4_PEND ,RX4_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 5. " RX5_PEND ,RX5_PEND raw int read (before mask)." "0,1" textline " " bitfld.long 0x0 6. " RX6_PEND ,RX6_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 7. " RX7_PEND ,RX7_PEND raw int read (before mask)." "0,1" textline " " bitfld.long 0x0 8. " RX0_THRESH_PEND ,RX0_THRESH_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 9. " RX1_THRESH_PEND ,RX1_THRESH_PEND raw int read (before mask)." "0,1" textline " " bitfld.long 0x0 10. " RX2_THRESH_PEND ,RX2_THRESH_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 11. " RX3_THRESH_PEND ,RX3_THRESH_PEND raw int read (before mask)." "0,1" textline " " bitfld.long 0x0 12. " RX4_THRESH_PEND ,RX4_THRESH_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 13. " RX5_THRESH_PEND ,RX5_THRESH_PEND raw int read (before mask)." "0,1" textline " " bitfld.long 0x0 14. " RX6_THRESH_PEND ,RX6_THRESH_PEND raw int read (before mask)." "0,1" bitfld.long 0x0 15. " RX7_THRESH_PEND ,RX7_THRESH_PEND raw int read (before mask)." "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xA4++0x3 line.long 0x0 "CPDMA_RX_INTSTAT_MASKED,CPDMA_INT RX interrupt status register (masked value)" bitfld.long 0x0 0. " RX0_PEND ,RX0_PEND masked int read." "0,1" bitfld.long 0x0 1. " RX1_PEND ,RX1_PEND masked int read." "0,1" textline " " bitfld.long 0x0 2. " RX2_PEND ,RX2_PEND masked int read." "0,1" bitfld.long 0x0 3. " RX3_PEND ,RX3_PEND masked int read." "0,1" textline " " bitfld.long 0x0 4. " RX4_PEND ,RX4_PEND masked int read." "0,1" bitfld.long 0x0 5. " RX5_PEND ,RX5_PEND masked int read." "0,1" textline " " bitfld.long 0x0 6. " RX6_PEND ,RX6_PEND masked int read." "0,1" bitfld.long 0x0 7. " RX7_PEND ,RX7_PEND masked int read." "0,1" textline " " bitfld.long 0x0 8. " RX0_THRESH_PEND ,RX0_THRESH_PEND masked int read." "0,1" bitfld.long 0x0 9. " RX1_THRESH_PEND ,RX1_THRESH_PEND masked int read." "0,1" textline " " bitfld.long 0x0 10. " RX2_THRESH_PEND ,RX2_THRESH_PEND masked int read." "0,1" bitfld.long 0x0 11. " RX3_THRESH_PEND ,RX3_THRESH_PEND masked int read." "0,1" textline " " bitfld.long 0x0 12. " RX4_THRESH_PEND ,RX4_THRESH_PEND masked int read." "0,1" bitfld.long 0x0 13. " RX5_THRESH_PEND ,RX5_THRESH_PEND masked int read." "0,1" textline " " bitfld.long 0x0 14. " RX6_THRESH_PEND ,RX6_THRESH_PEND masked int read." "0,1" bitfld.long 0x0 15. " RX7_THRESH_PEND ,RX7_THRESH_PEND masked int read." "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xA8++0x3 line.long 0x0 "CPDMA_RX_INTMASK_SET,CPDMA_INT RX interrupt mask set register" bitfld.long 0x0 0. " RX0_PEND_MASK ,RX Channel 0 Pending Int. Mask - Write one to enable Int." "0,1" bitfld.long 0x0 1. " RX1_PEND_MASK ,RX Channel 1 Pending Int. Mask - Write one to enable Int." "0,1" textline " " bitfld.long 0x0 2. " RX2_PEND_MASK ,RX Channel 2 Pending Int. Mask - Write one to enable Int." "0,1" bitfld.long 0x0 3. " RX3_PEND_MASK ,RX Channel 3 Pending Int. Mask - Write one to enable Int." "0,1" textline " " bitfld.long 0x0 4. " RX4_PEND_MASK ,RX Channel 4 Pending Int. Mask - Write one to enable Int." "0,1" bitfld.long 0x0 5. " RX5_PEND_MASK ,RX Channel 5 Pending Int. Mask - Write one to enable Int." "0,1" textline " " bitfld.long 0x0 6. " RX6_PEND_MASK ,RX Channel 6 Pending Int. Mask - Write one to enable Int." "0,1" bitfld.long 0x0 7. " RX7_PEND_MASK ,RX Channel 7 Pending Int. Mask - Write one to enable Int." "0,1" textline " " bitfld.long 0x0 8. " RX0_THRESH_PEND_MASK ,RX Channel 0 Threshold Pending Int. Mask - Write one to enable Int." "0,1" bitfld.long 0x0 9. " RX1_THRESH_PEND_MASK ,RX Channel 1 Threshold Pending Int. Mask - Write one to enable Int." "0,1" textline " " bitfld.long 0x0 10. " RX2_THRESH_PEND_MASK ,RX Channel 2 Threshold Pending Int. Mask - Write one to enable Int." "0,1" bitfld.long 0x0 11. " RX3_THRESH_PEND_MASK ,RX Channel 3 Threshold Pending Int. Mask - Write one to enable Int." "0,1" textline " " bitfld.long 0x0 12. " RX4_THRESH_PEND_MASK ,RX Channel 4 Threshold Pending Int. Mask - Write one to enable Int." "0,1" bitfld.long 0x0 13. " RX5_THRESH_PEND_MASK ,RX Channel 5 Threshold Pending Int. Mask - Write one to enable Int." "0,1" textline " " bitfld.long 0x0 14. " RX6_THRESH_PEND_MASK ,RX Channel 6 Threshold Pending Int. Mask - Write one to enable Int." "0,1" bitfld.long 0x0 15. " RX7_THRESH_PEND_MASK ,RX Channel 7 Threshold Pending Int. Mask - Write one to enable Int." "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xAC++0x3 line.long 0x0 "CPDMA_RX_INTMASK_CLEAR,CPDMA_INT RX interrupt mask clear register" bitfld.long 0x0 0. " RX0_PEND_MASK ,RX Channel 0 Pending Int. Mask - Write one to disable Int." "0,1" bitfld.long 0x0 1. " RX1_PEND_MASK ,RX Channel 1 Pending Int. Mask - Write one to disable Int." "0,1" textline " " bitfld.long 0x0 2. " RX2_PEND_MASK ,RX Channel 2 Pending Int. Mask - Write one to disable Int." "0,1" bitfld.long 0x0 3. " RX3_PEND_MASK ,RX Channel 3 Pending Int. Mask - Write one to disable Int." "0,1" textline " " bitfld.long 0x0 4. " RX4_PEND_MASK ,RX Channel 4 Pending Int. Mask - Write one to disable Int." "0,1" bitfld.long 0x0 5. " RX5_PEND_MASK ,RX Channel 5 Pending Int. Mask - Write one to disable Int." "0,1" textline " " bitfld.long 0x0 6. " RX6_PEND_MASK ,RX Channel 6 Pending Int. Mask - Write one to disable Int." "0,1" bitfld.long 0x0 7. " RX7_PEND_MASK ,RX Channel 7 Pending Int. Mask - Write one to disable Int." "0,1" textline " " bitfld.long 0x0 8. " RX0_THRESH_PEND_MASK ,RX Channel 0 Threshold Pending Int. Mask - Write one to disable Int." "0,1" bitfld.long 0x0 9. " RX1_THRESH_PEND_MASK ,RX Channel 1 Threshold Pending Int. Mask - Write one to disable Int." "0,1" textline " " bitfld.long 0x0 10. " RX2_THRESH_PEND_MASK ,RX Channel 2 Threshold Pending Int. Mask - Write one to disable Int." "0,1" bitfld.long 0x0 11. " RX3_THRESH_PEND_MASK ,RX Channel 3 Threshold Pending Int. Mask - Write one to disable Int." "0,1" textline " " bitfld.long 0x0 12. " RX4_THRESH_PEND_MASK ,RX Channel 4 Threshold Pending Int. Mask - Write one to disable Int." "0,1" bitfld.long 0x0 13. " RX5_THRESH_PEND_MASK ,RX Channel 5 Threshold Pending Int. Mask - Write one to disable Int." "0,1" textline " " bitfld.long 0x0 14. " RX6_THRESH_PEND_MASK ,RX Channel 6 Threshold Pending Int. Mask - Write one to disable Int." "0,1" bitfld.long 0x0 15. " RX7_THRESH_PEND_MASK ,RX Channel 7 Threshold Pending Int. Mask - Write one to disable Int." "0,1" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xB0++0x3 line.long 0x0 "CPDMA_DMA_INTSTAT_RAW,CPDMA_INT DMA interrupt status register (raw value)" bitfld.long 0x0 0. " STAT_PEND ,Statistics Pending Interrupt - raw int read (before mask)." "0,1" bitfld.long 0x0 1. " HOST_PEND ,Host Pending Interrupt - raw int read (before mask)." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0xB4++0x3 line.long 0x0 "CPDMA_DMA_INTSTAT_MASKED,CPDMA_INT DMA interrupt status register (masked value)" bitfld.long 0x0 0. " STAT_PEND ,Statistics Pending Interrupt - masked interrupt read." "0,1" bitfld.long 0x0 1. " HOST_PEND ,Host Pending Interrupt - masked interrupt read." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0xB8++0x3 line.long 0x0 "CPDMA_DMA_INTMASK_SET,CPDMA_INT DMA interrupt mask set register" bitfld.long 0x0 0. " STAT_INT_MASK ,Statistics Interrupt Mask - Write one to enable interrupt." "0,1" bitfld.long 0x0 1. " HOST_ERR_INT_MASK ,Host Error Interrupt Mask - Write one to enable interrupt." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0xBC++0x3 line.long 0x0 "CPDMA_DMA_INTMASK_CLEAR,CPDMA_INT DMA interrupt mask clear register" bitfld.long 0x0 0. " STAT_INT_MASK ,Statistics Interrupt Mask - Write one to disable interrupt." "0,1" bitfld.long 0x0 1. " HOST_ERR_INT_MASK ,Host Error Interrupt Mask - Write one to disable interrupt." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0xC0++0x3 line.long 0x0 "CPDMA_RX0_PENDTHRESH,CPDMA_INT receive threshold pending register channel 0" hexmask.long.byte 0x0 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0xC4++0x3 line.long 0x0 "CPDMA_RX1_PENDTHRESH,CPDMA_INT receive threshold pending register channel 1" hexmask.long.byte 0x0 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0xC8++0x3 line.long 0x0 "CPDMA_RX2_PENDTHRESH,CPDMA_INT receive threshold pending register channel 2" hexmask.long.byte 0x0 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0xCC++0x3 line.long 0x0 "CPDMA_RX3_PENDTHRESH,CPDMA_INT receive threshold pending register channel 3" hexmask.long.byte 0x0 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0xD0++0x3 line.long 0x0 "CPDMA_RX4_PENDTHRESH,CPDMA_INT receive threshold pending register channel 4" hexmask.long.byte 0x0 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0xD4++0x3 line.long 0x0 "CPDMA_RX5_PENDTHRESH,CPDMA_INT receive threshold pending register channel 5" hexmask.long.byte 0x0 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0xD8++0x3 line.long 0x0 "CPDMA_RX6_PENDTHRESH,CPDMA_INT receive threshold pending register channel 6" hexmask.long.byte 0x0 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0xDC++0x3 line.long 0x0 "CPDMA_RX7_PENDTHRESH,CPDMA_INT receive threshold pending register channel 7" hexmask.long.byte 0x0 0.--7. 1. " RX_PENDTHRESH ,Rx Flow Threshold - This field contains the threshold value for issuing receive threshold pending interrupts (when enabled)." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0xE0++0x3 line.long 0x0 "CPDMA_RX0_FREEBUFFER,CPDMA_INT receive free buffer register channel 0" hexmask.long.word 0x0 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count - This field contains the count of free buffers available. TheCPDMA_RX0_PENDTHRESH[7:0] RX_PENDTHRESH value is compared with this field to determine if the receive threshold pending interrupt should be asseted (if enabled). This is a write to increment field. This field rolls over to zero on overflow. If receive threshold pending interrupts are used, the host must initialize this field to the number of available buffers (one register per channel). The port decrements (by the number of buffers in the received frame) the associated channel register for each received frame. This is a write to increment field. The host must write this field with the number of buffers that have been freed due to host processing." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xE4++0x3 line.long 0x0 "CPDMA_RX1_FREEBUFFER,CPDMA_INT receive free buffer register channel 1" hexmask.long.word 0x0 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count - This field contains the count of free buffers available. TheCPDMA_RX1_PENDTHRESH[7:0] RX_PENDTHRESH value is compared with this field to determine if the receive threshold pending interrupt should be asseted (if enabled). This is a write to increment field. This field rolls over to zero on overflow. If receive threshold pending interrupts are used, the host must initialize this field to the number of available buffers (one register per channel). The port decrements (by the number of buffers in the received frame) the associated channel register for each received frame. This is a write to increment field. The host must write this field with the number of buffers that have been freed due to host processing." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xE8++0x3 line.long 0x0 "CPDMA_RX2_FREEBUFFER,CPDMA_INT receive free buffer register channel 2" hexmask.long.word 0x0 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count - This field contains the count of free buffers available. TheCPDMA_RX2_PENDTHRESH[7:0] RX_PENDTHRESH value is compared with this field to determine if the receive threshold pending interrupt should be asseted (if enabled). This is a write to increment field. This field rolls over to zero on overflow. If receive threshold pending interrupts are used, the host must initialize this field to the number of available buffers (one register per channel). The port decrements (by the number of buffers in the received frame) the associated channel register for each received frame. This is a write to increment field. The host must write this field with the number of buffers that have been freed due to host processing." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xEC++0x3 line.long 0x0 "CPDMA_RX3_FREEBUFFER,CPDMA_INT receive free buffer register channel 3" hexmask.long.word 0x0 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count - This field contains the count of free buffers available. TheCPDMA_RX3_PENDTHRESH[7:0] RX_PENDTHRESH value is compared with this field to determine if the receive threshold pending interrupt should be asseted (if enabled). This is a write to increment field. This field rolls over to zero on overflow. If receive threshold pending interrupts are used, the host must initialize this field to the number of available buffers (one register per channel). The port decrements (by the number of buffers in the received frame) the associated channel register for each received frame. This is a write to increment field. The host must write this field with the number of buffers that have been freed due to host processing." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xF0++0x3 line.long 0x0 "CPDMA_RX4_FREEBUFFER,CPDMA_INT receive free buffer register channel 4" hexmask.long.word 0x0 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count - This field contains the count of free buffers available. TheCPDMA_RX4_PENDTHRESH[7:0] RX_PENDTHRESH value is compared with this field to determine if the receive threshold pending interrupt should be asseted (if enabled). This is a write to increment field. This field rolls over to zero on overflow. If receive threshold pending interrupts are used, the host must initialize this field to the number of available buffers (one register per channel). The port decrements (by the number of buffers in the received frame) the associated channel register for each received frame. This is a write to increment field. The host must write this field with the number of buffers that have been freed due to host processing." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xF4++0x3 line.long 0x0 "CPDMA_RX5_FREEBUFFER,CPDMA_INT receive free buffer register channel 5" hexmask.long.word 0x0 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count - This field contains the count of free buffers available. TheCPDMA_RX5_PENDTHRESH[7:0] RX_PENDTHRESH value is compared with this field to determine if the receive threshold pending interrupt should be asseted (if enabled). This is a write to increment field. This field rolls over to zero on overflow. If receive threshold pending interrupts are used, the host must initialize this field to the number of available buffers (one register per channel). The port decrements (by the number of buffers in the received frame) the associated channel register for each received frame. This is a write to increment field. The host must write this field with the number of buffers that have been freed due to host processing." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xF8++0x3 line.long 0x0 "CPDMA_RX6_FREEBUFFER,CPDMA_INT receive free buffer register channel 6" hexmask.long.word 0x0 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count - This field contains the count of free buffers available. TheCPDMA_RX6_PENDTHRESH[7:0] RX_PENDTHRESH value is compared with this field to determine if the receive threshold pending interrupt should be asseted (if enabled). This is a write to increment field. This field rolls over to zero on overflow. If receive threshold pending interrupts are used, the host must initialize this field to the number of available buffers (one register per channel). The port decrements (by the number of buffers in the received frame) the associated channel register for each received frame. This is a write to increment field. The host must write this field with the number of buffers that have been freed due to host processing." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0xFC++0x3 line.long 0x0 "CPDMA_RX7_FREEBUFFER,CPDMA_INT receive free buffer register channel 7" hexmask.long.word 0x0 0.--15. 1. " RX_FREEBUFFER ,Rx Free Buffer Count - This field contains the count of free buffers available. TheCPDMA_RX7_PENDTHRESH[7:0] RX_PENDTHRESH value is compared with this field to determine if the receive threshold pending interrupt should be asseted (if enabled). This is a write to increment field. This field rolls over to zero on overflow. If receive threshold pending interrupts are used, the host must initialize this field to the number of available buffers (one register per channel). The port decrements (by the number of buffers in the received frame) the associated channel register for each received frame. This is a write to increment field. The host must write this field with the number of buffers that have been freed due to host processing." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," width 0x0B tree.end tree "PORT" base ad:0x48484100 width 21. group.byte 0x0++0x3 line.long 0x0 "P0_CONTROL,CPSW PORT 0 control register" hexmask.long.word 0x0 0.--15. 1. " RESERVED ," bitfld.long 0x0 16. " P0_DSCP_PRI_EN ,Port 0 DSCP Priority Enable 0 - DSCP priority disabled 1 - DSCP priority enabled. All non-tagged IPV4 packets have their received packet priority determined by mapping the 6 TOS bits through the port DSCP priority mapping registers." "0,1" textline " " bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. " P0_VLAN_LTYPE1_EN ,Port 0 VLAN LTYPE 1 enable 0 - disabled 1 - enabled" "0,1" textline " " bitfld.long 0x0 21. " P0_VLAN_LTYPE2_EN ,Port 0 VLAN LTYPE 2 enable 0 - disabled 1 - enabled" "0,1" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24. " P0_PASS_PRI_TAGGED ,Port 0 Pass Priority Tagged 0 - Priority tagged packets have the zero VID replaced with the input port P0_PORT_VLAN [11:0] 1 - Priority tagged packets are processed unchanged." "0,1" bitfld.long 0x0 25.--27. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 28.--30. " P0_DLR_CPDMA_CH ,Port 0 DLR CPDMA Channel This field indicates the CPDMA channel that DLR packets will be received on." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x8++0x3 line.long 0x0 "P0_MAX_BLKS,CPSW PORT 0 maximum FIFO blocks register" bitfld.long 0x0 0.--3. " P0_RX_MAX_BLKS ,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue. 0x4 is the recommended value. 0x3 is the minimum value P0_RX_MAX_BLKS and 0x6 is the maximum value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " P0_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues. 0x10 is the recommended value of P0_TX_MAX_BLKS. Port 0 should remain in flow control mode. 0xE is the minimum value P0_TX_MAX_BLKS." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "P0_BLK_CNT,CPSW PORT 0 FIFO block usage count (read only)" bitfld.long 0x0 0.--3. " P0_RX_BLK_CNT ,Port 0 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " P0_TX_BLK_CNT ,Port 0 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "P0_TX_IN_CTL,CPSW PORT 0 transmit FIFO control" hexmask.long.word 0x0 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--15. " TX_BLKS_REM ,Transmit FIFO Input Blocks to subtract in dual MAC mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select 00 - Normal priority mode 01 - Dual MAC mode 10 - Rate Limit mode 11 - reserved Note that Dual MAC mode is not compatible with escalation or shaping because dual MAC mode forces round robin priority on FIFO egress. Rate-limiting and shaping are still available for Port 1 and Port 2 when Port 0 is set in dual MAC mode." "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" bitfld.long 0x0 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "P0_PORT_VLAN,CPSW PORT 0 VLAN register" hexmask.long.word 0x0 0.--11. 1. " PORT_VID ,Port VLAN ID" bitfld.long 0x0 12. " PORT_CFI ,Port CFI bit" "0,1" textline " " bitfld.long 0x0 13.--15. " PORT_PRI ,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "P0_TX_PRI_MAP,CPSW PORT 0 TX header priority to switch priority mapping register" bitfld.long 0x0 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x1C++0x3 line.long 0x0 "P0_CPDMA_TX_PRI_MAP,CPSW CPDMA TX (PORT 0 RX) packet priority to header priority" bitfld.long 0x0 0.--2. " PRI0 ,Priority 0 - A packet pri of 0x0 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI1 ,Priority 1 - A packet pri of 0x1 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI2 ,Priority 2 - A packet pri of 0x2 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI3 ,Priority 3 - A packet pri of 0x3 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI4 ,Priority 4 - A packet pri of 0x4 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI5 ,Priority 5 - A packet pri of 0x5 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI6 ,Priority 6 - A packet pri of 0x6 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI7 ,Priority 7 - A packet pri of 0x7 is mapped (changed) to this header packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x20++0x3 line.long 0x0 "P0_CPDMA_RX_CH_MAP,CPSW CPDMA RX (PORT 0 TX) switch priority to DMA channel" bitfld.long 0x0 0.--2. " P1_PRI0 ,Port 1 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " P1_PRI1 ,Port 1 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " P1_PRI2 ,Port 1 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " P1_PRI3 ,Port 1 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " P2_PRI0 ,Port 2 Priority 0 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " P2_PRI1 ,Port 2 Priority 1 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " P2_PRI2 ,Port 2 Priority 2 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " P2_PRI3 ,Port 2 Priority 3 packets go to this CPDMA Rx Channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x30++0x3 line.long 0x0 "P0_RX_DSCP_PRI_MAP0,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 0" bitfld.long 0x0 0.--2. " PRI0 ,Priority 0 - A packet TOS of 0d0 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI1 ,Priority 1 - A packet TOS of 0d1 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI2 ,Priority 2 - A packet TOS of 0d2 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI3 ,Priority 3 - A packet TOS of 0d3 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI4 ,Priority 4 - A packet TOS of 0d4 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI5 ,Priority 5 - A packet TOS of 0d5 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI6 ,Priority 6 - A packet TOS of 0d6 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI7 ,Priority 7 - A packet TOS of 0d7 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x34++0x3 line.long 0x0 "P0_RX_DSCP_PRI_MAP1,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 1" bitfld.long 0x0 0.--2. " PRI8 ,Priority 8 - A packet TOS of 0d8 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI9 ,Priority 9 - A packet TOS of 0d9 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI10 ,Priority 10 - A packet TOS of 0d10 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI11 ,Priority 11 - A packet TOS of 0d11 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI12 ,Priority 12 - A packet TOS of 0d12 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI13 ,Priority 13 - A packet TOS of 0d13 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI14 ,Priority 14 - A packet TOS of 0d14 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI15 ,Priority 15 - A packet TOS of 0d15 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x38++0x3 line.long 0x0 "P0_RX_DSCP_PRI_MAP2,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 2" bitfld.long 0x0 0.--2. " PRI16 ,Priority 16 - A packet TOS of 0d16 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI17 ,Priority 17 - A packet TOS of 0d17 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI18 ,Priority 18 - A packet TOS of 0d18 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI19 ,Priority 19 - A packet TOS of 0d19 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI20 ,Priority 20 - A packet TOS of 0d20 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI21 ,Priority 21 - A packet TOS of 0d21 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI22 ,Priority 22 - A packet TOS of 0d22 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI23 ,Priority 23 - A packet TOS of 0d23 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x3C++0x3 line.long 0x0 "P0_RX_DSCP_PRI_MAP3,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 3" bitfld.long 0x0 0.--2. " PRI24 ,Priority 24 - A packet TOS of 0d24 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI25 ,Priority 25 - A packet TOS of 0d25 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI26 ,Priority 26 - A packet TOS of 0d26 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI27 ,Priority 27 - A packet TOS of 0d27 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI28 ,Priority 28 - A packet TOS of 0d28 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI29 ,Priority 29 - A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI30 ,Priority 30 - A packet TOS of 0d30 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI31 ,Priority 31 - A packet TOS of 0d31 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x40++0x3 line.long 0x0 "P0_RX_DSCP_PRI_MAP4,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 4" bitfld.long 0x0 0.--2. " PRI32 ,Priority 32 - A packet TOS of 0d32 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI33 ,Priority 33 - A packet TOS of 0d33 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI34 ,Priority 34 - A packet TOS of 0d34 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI35 ,Priority 35 - A packet TOS of 0d35 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI36 ,Priority 36 - A packet TOS of 0d36 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI37 ,Priority 37 - A packet TOS of 0d37 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI38 ,Priority 38 - A packet TOS of 0d38 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI39 ,Priority 39 - A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x44++0x3 line.long 0x0 "P0_RX_DSCP_PRI_MAP5,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 5" bitfld.long 0x0 0.--2. " PRI40 ,Priority 40 - A packet TOS of 0d40 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI41 ,Priority 41 - A packet TOS of 0d41 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI42 ,Priority 42 - A packet TOS of 0d42 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI43 ,Priority 43 - A packet TOS of 0d43 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI44 ,Priority 44 - A packet TOS of 0d44 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI45 ,Priority 45 - A packet TOS of 0d45 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI46 ,Priority 46 - A packet TOS of 0d46 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI47 ,Priority 47 - A packet TOS of 0d47 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x48++0x3 line.long 0x0 "P0_RX_DSCP_PRI_MAP6,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 6" bitfld.long 0x0 0.--2. " PRI48 ,Priority 48 - A packet TOS of 0d48 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI49 ,Priority 49 - A packet TOS of 0d49 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI50 ,Priority 50 - A packet TOS of 0d50 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI51 ,Priority 51 - A packet TOS of 0d51 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI52 ,Priority 52 - A packet TOS of 0d52 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI53 ,Priority 53 - A packet TOS of 0d53 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI54 ,Priority 54 - A packet TOS of 0d54 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI55 ,Priority 55 - A packet TOS of 0d55 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x4C++0x3 line.long 0x0 "P0_RX_DSCP_PRI_MAP7,CPSW PORT 0 RX DSCP priority to RX packet mapping reg 7" bitfld.long 0x0 0.--2. " PRI56 ,Priority 56 - A packet TOS of 0d56 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI57 ,Priority 57 - A packet TOS of 0d57 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI58 ,Priority 58 - A packet TOS of 0d58 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI59 ,Priority 59 - A packet TOS of 0d59 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI60 ,Priority 60 - A packet TOS of 0d60 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI61 ,Priority 61 - A packet TOS of 0d61 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI62 ,Priority 62 - A packet TOS of 0d62 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI63 ,Priority 63 - A packet TOS of 0d63 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x50++0x3 line.long 0x0 "P0_IDLE2LPI,Port 0 EEE Idle to LPI Counter Load Value Register" hexmask.long.tbyte 0x0 0.--19. 1. " P0_IDLE2LPI ,Port 0 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted, this value is loaded into the port 0 idle to LPI counter on each clock that the port 0 transmit is not idle. Port 0 enters the transmit LPI state when this counter decrements to zero. This counter decrements each time the EEE prescale counter decrements to zero." hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "P0_LPI2WAKE,Port 0 EEE LPI to Wake Counter Load Value Register" hexmask.long.tbyte 0x0 0.--19. 1. " P0_LPI2WAKE ,Port 0 EEE LPI to wake counter load value  When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted, this value is loaded into the port 0 LPI to wake counter. Transmit packet operations may begin (resume) when the LPI to wake count decrements to zero (on the pre-scale count). This is the time that the CPDMA transmit must wait before transmit (switch ingress) packet operations begin (resume after wakeup)." hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x100++0x3 line.long 0x0 "P1_CONTROL,CPSW PORT 1 control register" bitfld.long 0x0 0. " P1_TS_RX_EN ,Port 1 Time Sync Receive Enable 0 - Port 1 Receive Time Sync disabled 1 - Port 1 Receive Time Sync enabled" "0,1" bitfld.long 0x0 1. " P1_TS_TX_EN ,Port 1 Time Sync Transmit Enable 0 - disabled 1 - enabled" "0,1" textline " " bitfld.long 0x0 2. " P1_TS_LTYPE1_EN ,Port 1 Time Sync LTYPE 1 enable 0 - disabled 1 - enabled" "0,1" bitfld.long 0x0 3. " P1_TS_LTYPE2_EN ,Port 1 Time Sync LTYPE 2 enable 0 - disabled 1 - enabled" "0,1" textline " " bitfld.long 0x0 4. " P1_TS_ANNEX_D_EN ,Port 1 Time Sync Annex D enable 0 - Annex D disabled 1 - Annex D enabled" "0,1" bitfld.long 0x0 5. " P1_TS_ANNEX_E_EN ,Port 1 Time Sync Annex E enable 0  Annex E disabled 1  Annex E enabled" "0,1" textline " " bitfld.long 0x0 6. " P1_TS_ANNEX_F_EN ,Port 1 Time Sync Annex F enable 0  Annex F disabled 1  Annex F enabled" "0,1" bitfld.long 0x0 7. " P1_TS_UNI_EN ,Port 1 Time Sync Unicast Enable 0  Unicast disabled 1  Unicast enabled" "0,1" textline " " bitfld.long 0x0 8. " P1_TS_TTL_NONZERO ,Port 1 Time Sync Time To Live Non-zero enable. 0 = TTL must be zero. 1 = TTL may be any value." "0,1" bitfld.long 0x0 9. " P1_TS_129 ,Port 1 Time Sync Destination IP Address 129 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address number 129 (decimal) is enabled." "0,1" textline " " bitfld.long 0x0 10. " P1_TS_130 ,Port 1 Time Sync Destination IP Address 130 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address number 130 (decimal) is enabled." "0,1" bitfld.long 0x0 11. " P1_TS_131 ,Port 1 Time Sync Destination IP Address 131 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address number 131 (decimal) is enabled." "0,1" textline " " bitfld.long 0x0 12. " P1_TS_132 ,Port 1 Time Sync Destination IP Address 132 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address number 132 (decimal) is enabled." "0,1" bitfld.long 0x0 13. " P1_TS_319 ,Port 1 Time Sync Destination Port Number 319 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination port number 319 (decimal) is enabled." "0,1" textline " " bitfld.long 0x0 14. " P1_TS_320 ,Port 1 Time Sync Destination Port Number 320 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination port number 320 (decimal) is enabled." "0,1" bitfld.long 0x0 15. " P1_TS_107 ,Port 1 Time Sync Destination IP Address 107 enable 0  disabled 1  destination IP address (dec) 224.0.0.107 is enabled." "0,1" textline " " bitfld.long 0x0 16. " P1_DSCP_PRI_EN ,Port 1 DSCP Priority Enable 0 - DSCP priority disabled 1 - DSCP priority enabled. All non-tagged IPV4 packets have their received packet priority determined by mapping the 6 TOS bits through the port DSCP priority mapping registers." "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " P1_VLAN_LTYPE1_EN ,Port 1 VLAN LTYPE 1 enable 0 - disabled 1 - VLAN LTYPE1 enabled on transmit and receive" "0,1" bitfld.long 0x0 21. " P1_VLAN_LTYPE2_EN ,Port 1 VLAN LTYPE 2 enable 0 - disabled 1 - VLAN LTYPE2 enabled on transmit and receive" "0,1" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24. " P1_PASS_PRI_TAGGED ,Port 1 Pass Priority Tagged 0 - Priority tagged packets have the zero VID replaced with the input port P1_PORT_VLAN [11:0] 1 - Priority tagged packets are processed unchanged." "0,1" textline " " bitfld.long 0x0 25. " P1_TX_CLKSTOP_EN ,Port 1 Transmit clockstop enable 0  RGMII transmit clockstop not enabled 1  RGMII transmit clockstop enabled. The transmit clock will be stopped after the LPI state is entered (and indicated to the CPRGMII) and the P1_Idle2LPI time is counted (counter value reused). The P1_Idle2LPI counter value must be greater than 9 transmit clocks (slowest clock)" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x108++0x3 line.long 0x0 "P1_MAX_BLKS,CPSW PORT 1 maximum FIFO blocks register" bitfld.long 0x0 0.--3. " P1_RX_MAX_BLKS ,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue. This value must be greater than or equal to 0x3. It should be increased In fullduplex flow control mode to 0x5 or 0x6 depending on the required runout space. The P1_TX_MAX_BLKS value must be decreased by the amount of increase in P1_RX_MAX_BLKS. 0x6 is the maximum value for P1_RX_MAX_BLKS." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " P1_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues. 0x11 is the recommended value of P1_TX_MAX_BLKS unless the port is in fullduplex flow control mode. In flow control mode, the P1_RX_MAX_BLKS will need to increase in order to accept the required run out in fullduplex mode. This value will need to decrease by the amount of increase in P1_RX_MAX_BLKS. 0xE is the minimum value for P1_TX_MAX_BLKS." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "P1_BLK_CNT,CPSW PORT 1 FIFO block usage count (read only)" bitfld.long 0x0 0.--3. " P1_RX_BLK_CNT ,Port 1 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " P1_TX_BLK_CNT ,Port 1 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "P1_TX_IN_CTL,CPSW PORT 1 transmit FIFO control" hexmask.long.word 0x0 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--15. " TX_BLKS_REM ,Transmit FIFO Input blocks to subtract on non rate-limited traffic in rate limit mode." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select 0x0 - Normal priority mode 0x1 - reserved 0x2 - Rate Limit mode 0x3 - reserved" "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" bitfld.long 0x0 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HOST_BLKS_REM ,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x114++0x3 line.long 0x0 "P1_PORT_VLAN,CPSW PORT 1 VLAN register" hexmask.long.word 0x0 0.--11. 1. " PORT_VID ,Port VLAN ID" bitfld.long 0x0 12. " PORT_CFI ,Port CFI bit" "0,1" textline " " bitfld.long 0x0 13.--15. " PORT_PRI ,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x118++0x3 line.long 0x0 "P1_TX_PRI_MAP,CPSW PORT 1 TX header priority to switch priority mapping register" bitfld.long 0x0 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue priority" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue priority" "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue priority" "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue priority" "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue priority" "0,1,2,3" bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue priority" "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue priority" "0,1,2,3" bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue priority" "0,1,2,3" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x11C++0x3 line.long 0x0 "P1_TS_SEQ_MTYPE,CPSW PORT 1 time sync sequence ID offset and message type." hexmask.long.word 0x0 0.--15. 1. " P1_TS_MSG_TYPE_EN ,Port 1 Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)." bitfld.long 0x0 16.--21. " P1_TS_SEQ_ID_OFFSET ,Port 1 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header. The minimum value is 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x120++0x3 line.long 0x0 "P1_SA_LO,CPSW CPGMAC_SL1 source address low register" hexmask.long.byte 0x0 0.--7. 1. " MACSRCADDR_15_8 ,Source Address bits 15:8 (byte 1)" hexmask.long.byte 0x0 8.--15. 1. " MACSRCADDR_7_0 ,Source Address Lower 8 bits (byte 0)" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "P1_SA_HI,CPSW CPGMAC_SL1 source address high register" hexmask.long.byte 0x0 0.--7. 1. " MACSRCADDR_47_40 ,Source Address bits 47:40 (byte 5)" hexmask.long.byte 0x0 8.--15. 1. " MACSRCADDR_39_32 ,Source Address bits 39:32 (byte 4)" textline " " hexmask.long.byte 0x0 16.--23. 1. " MACSRCADDR_31_24 ,Source Address bits 31:24 (byte 3)" hexmask.long.byte 0x0 24.--31. 1. " MACSRCADDR_23_16 ,Source Address bits 23:16 (byte 2)" group.byte 0x128++0x3 line.long 0x0 "P1_SEND_PERCENT,CPSW PORT 1 transmit queue send percentages" hexmask.long.byte 0x0 0.--6. 1. " PRI1_SEND_PERCENT ,Priority 1 Transmit Percentage - This percentage value is sent from FIFO priority 1 (maximum) when theCPSW_PTYPE[16] P1_PRI1_SHAPE_EN is set (queue shaping enabled). This is the percentage of the wire that packets from priority 1 receive (which includes interpacket gap and preamble bytes). If shaping is enabled on this queue then this value must be between zero and 0d100 (not inclusive)." bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.byte 0x0 8.--14. 1. " PRI2_SEND_PERCENT ,Priority 2 Transmit Percentage - This percentage value is sent from FIFO priority 2 (maximum) whenCPSW_PTYPE[17] P1_PRI2_SHAPE_EN is set (queue shaping enabled). This is the percentage of the wire that packets from priority 2 receive (which includes interpacket gap and preamble bytes). If shaping is enabled on this queue then this value must be between zero and 0d100 (not inclusive)." bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.byte 0x0 16.--22. 1. " PRI3_SEND_PERCENT ,Priority 3 Transmit Percentage - This percentage value is sent from FIFO priority 3 (maximum) whenCPSW_PTYPE[18] P1_PRI3_SHAPE_EN is set (queue shaping enabled). This is the percentage of the wire that packets from priority 3 receive (which includes interpacket gap and preamble bytes). If shaping is enabled on this queue then this value must be between zero and 0d100 (not inclusive)." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "P1_RX_DSCP_PRI_MAP0,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 0" bitfld.long 0x0 0.--2. " PRI0 ,Priority 0 - A packet TOS of 0d0 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI1 ,Priority 1 - A packet TOS of 0d1 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI2 ,Priority 2 - A packet TOS of 0d2 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI3 ,Priority 3 - A packet TOS of 0d3 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI4 ,Priority 4 - A packet TOS of 0d4 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI5 ,Priority 5 - A packet TOS of 0d5 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI6 ,Priority 6 - A packet TOS of 0d6 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI7 ,Priority 7 - A packet TOS of 0d7 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x134++0x3 line.long 0x0 "P1_RX_DSCP_PRI_MAP1,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 1" bitfld.long 0x0 0.--2. " PRI8 ,Priority 8 - A packet TOS of 0d8 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI9 ,Priority 9 - A packet TOS of 0d9 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI10 ,Priority 10 - A packet TOS of 0d10 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI11 ,Priority 11 - A packet TOS of 0d11 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI12 ,Priority 12 - A packet TOS of 0d12 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI13 ,Priority 13 - A packet TOS of 0d13 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI14 ,Priority 14 - A packet TOS of 0d14 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI15 ,Priority 15 - A packet TOS of 0d15 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x138++0x3 line.long 0x0 "P1_RX_DSCP_PRI_MAP2,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 2" bitfld.long 0x0 0.--2. " PRI16 ,Priority 16 - A packet TOS of 0d16 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI17 ,Priority 17 - A packet TOS of 0d17 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI18 ,Priority 18 - A packet TOS of 0d18 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI19 ,Priority 19 - A packet TOS of 0d19 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI20 ,Priority 20 - A packet TOS of 0d20 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI21 ,Priority 21 - A packet TOS of 0d21 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI22 ,Priority 22 - A packet TOS of 0d22 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI23 ,Priority 23 - A packet TOS of 0d23 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x13C++0x3 line.long 0x0 "P1_RX_DSCP_PRI_MAP3,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 3" bitfld.long 0x0 0.--2. " PRI24 ,Priority 24 - A packet TOS of 0d24 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI25 ,Priority 25 - A packet TOS of 0d25 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI26 ,Priority 26 - A packet TOS of 0d26 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI27 ,Priority 27 - A packet TOS of 0d27 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI28 ,Priority 28 - A packet TOS of 0d28 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI29 ,Priority 29 - A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI30 ,Priority 30 - A packet TOS of 0d30 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI31 ,Priority 31 - A packet TOS of 0d31 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x140++0x3 line.long 0x0 "P1_RX_DSCP_PRI_MAP4,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 4" bitfld.long 0x0 0.--2. " PRI32 ,Priority 32 - A packet TOS of 0d32 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI33 ,Priority 33 - A packet TOS of 0d33 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI34 ,Priority 34 - A packet TOS of 0d34 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI35 ,Priority 35 - A packet TOS of 0d35 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI36 ,Priority 36 - A packet TOS of 0d36 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI37 ,Priority 37 - A packet TOS of 0d37 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI38 ,Priority 38 - A packet TOS of 0d38 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI39 ,Priority 39 - A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x144++0x3 line.long 0x0 "P1_RX_DSCP_PRI_MAP5,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 5" bitfld.long 0x0 0.--2. " PRI40 ,Priority 40 - A packet TOS of 0d40 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI41 ,Priority 41 - A packet TOS of 0d41 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI42 ,Priority 42 - A packet TOS of 0d42 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI43 ,Priority 43 - A packet TOS of 0d43 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI44 ,Priority 44 - A packet TOS of 0d44 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI45 ,Priority 45 - A packet TOS of 0d45 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI46 ,Priority 46 - A packet TOS of 0d46 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI47 ,Priority 47 - A packet TOS of 0d47 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x148++0x3 line.long 0x0 "P1_RX_DSCP_PRI_MAP6,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 6" bitfld.long 0x0 0.--2. " PRI48 ,Priority 48 - A packet TOS of 0d48 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI49 ,Priority 49 - A packet TOS of 0d49 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI50 ,Priority 50 - A packet TOS of 0d50 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI51 ,Priority 51 - A packet TOS of 0d51 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI52 ,Priority 52 - A packet TOS of 0d52 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI53 ,Priority 53 - A packet TOS of 0d53 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI54 ,Priority 54 - A packet TOS of 0d54 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI55 ,Priority 55 - A packet TOS of 0d55 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14C++0x3 line.long 0x0 "P1_RX_DSCP_PRI_MAP7,CPSW PORT 1 RX DSCP priority to RX packet mapping reg 7" bitfld.long 0x0 0.--2. " PRI56 ,Priority 56 - A packet TOS of 0d56 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI57 ,Priority 57 - A packet TOS of 0d57 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI58 ,Priority 58 - A packet TOS of 0d58 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI59 ,Priority 59 - A packet TOS of 0d59 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI60 ,Priority 60 - A packet TOS of 0d60 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI61 ,Priority 61 - A packet TOS of 0d61 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI62 ,Priority 62 - A packet TOS of 0d62 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI63 ,Priority 63 - A packet TOS of 0d63 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x150++0x3 line.long 0x0 "P1_IDLE2LPI,Port 1 EEE Idle to LPI Counter Load Value Register" hexmask.long.tbyte 0x0 0.--19. 1. " P1_IDLE2LPI ,Port 1 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted, this value is loaded into the port 1 idle to LPI counter on each clock that the port 1 transmit is not idle. Port 0 enters the transmit LPI state when this counter decrements to zero. This counter decrements each time the EEE prescale counter decrements to zero." hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x154++0x3 line.long 0x0 "P1_LPI2WAKE,Port 1 EEE LPI to Wake Counter Load Value Register" hexmask.long.tbyte 0x0 0.--19. 1. " P1_LPI2WAKE ,Port 1 EEE LPI to wake counter load value  When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted, this value is loaded into the port 1 LPI to wake counter. Transmit packet operations may begin (resume) when the LPI to wake count decrements to zero (on the pre-scale count). This is the time that the CPDMA transmit must wait before transmit (switch ingress) packet operations begin (resume after wakeup)." hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x200++0x3 line.long 0x0 "P2_CONTROL,CPSW_3GF PORT 2 control register" bitfld.long 0x0 0. " P2_TS_RX_EN ,Port 2 Time Sync Receive Enable 0 - Port 1 Receive Time Sync disabled 1 - Port 1 Receive Time Sync enabled" "0,1" bitfld.long 0x0 1. " P2_TS_TX_EN ,Port 2 Time Sync Transmit Enable 0 - disabled 1 - enabled" "0,1" textline " " bitfld.long 0x0 2. " P2_TS_LTYPE1_EN ,Port 2 Time Sync LTYPE 1 enable 0 - disabled 1 - enabled" "0,1" bitfld.long 0x0 3. " P2_TS_LTYPE2_EN ,Port 2 Time Sync LTYPE 2 enable 0 - disabled 1 - enabled" "0,1" textline " " bitfld.long 0x0 4. " P2_TS_ANNEX_D_EN ,Port 2 Time Sync Annex D enable 0 - Annex D disabled 1 - Annex D enabled" "0,1" bitfld.long 0x0 5. " P2_TS_ANNEX_E_EN ,Port 2 Time Sync Annex E enable 0  Annex E disabled 1  Annex E enabled" "0,1" textline " " bitfld.long 0x0 6. " P2_TS_ANNEX_F_EN ,Port 2 Time Sync Annex F enable 0  Annex F disabled 1  Annex F enabled" "0,1" bitfld.long 0x0 7. " P2_TS_UNI_EN ,Port 2 Time Sync Unicast Enable 0  Unicast disabled 1  Unicast enabled" "0,1" textline " " bitfld.long 0x0 8. " P2_TS_TTL_NONZERO ,Port 2 Time Sync Time To Live Non-zero enable. 0 = TTL must be zero. 1 = TTL may be any value." "0,1" bitfld.long 0x0 9. " P2_TS_129 ,Port 2 Time Sync Destination IP Address 129 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address number 129 (decimal) is enabled." "0,1" textline " " bitfld.long 0x0 10. " P2_TS_130 ,Port 2 Time Sync Destination IP Address 130 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address number 130 (decimal) is enabled." "0,1" bitfld.long 0x0 11. " P2_TS_131 ,Port 2 Time Sync Destination IP Address 131 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address number 131 (decimal) is enabled." "0,1" textline " " bitfld.long 0x0 12. " P2_TS_132 ,Port 2 Time Sync Destination IP Address 132 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination IP address number 132 (decimal) is enabled." "0,1" bitfld.long 0x0 13. " P2_TS_319 ,Port 2 Time Sync Destination Port Number 319 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination port number 319 (decimal) is enabled." "0,1" textline " " bitfld.long 0x0 14. " P2_TS_320 ,Port 2 Time Sync Destination Port Number 320 enable 0 - disabled 1 - Annex D (UDP/IPv4) time sync packet destination port number 320 (decimal) is enabled." "0,1" bitfld.long 0x0 15. " P2_TS_107 ,Port 2 Time Sync Destination IP Address 107 enable 0  disabled 1  destination IP address (dec) 224.0.0.107 is enabled." "0,1" textline " " bitfld.long 0x0 16. " P2_DSCP_PRI_EN ,Port 0 DSCP Priority Enable 0 - DSCP priority disabled 1 - DSCP priority enabled. All non-tagged IPV4 packets have their received packet priority determined by mapping the 6 TOS bits through the port DSCP priority mapping registers." "0,1" bitfld.long 0x0 17.--19. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 20. " P2_VLAN_LTYPE1_EN ,Port 2 VLAN LTYPE 1 enable 0 - disabled 1 - VLAN LTYPE1 enabled on transmit and receive" "0,1" bitfld.long 0x0 21. " P2_VLAN_LTYPE2_EN ,Port 2 VLAN LTYPE 2 enable 0 - disabled 1 - VLAN LTYPE2 enabled on transmit and receive" "0,1" textline " " bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" bitfld.long 0x0 24. " P2_PASS_PRI_TAGGED ,Port 2 Pass Priority Tagged 0 - Priority tagged packets have the zero VID replaced with the input port P2_PORT_VLAN [11:0] 1 - Priority tagged packets are processed unchanged." "0,1" textline " " bitfld.long 0x0 25. " P2_TX_CLKSTOP_EN ,Port 2 Transmit clockstop enable 0  RGMII transmit clockstop not enabled 1  RGMII transmit clockstop enabled. The transmit clock will be stopped after the LPI state is entered (and indicated to the CPRGMII) and the P2_Idle2LPI time is counted (counter value reused). The P2_Idle2LPI counter value must be greater than 9 transmit clocks (slowest clock)" "0,1" bitfld.long 0x0 26.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x208++0x3 line.long 0x0 "P2_MAX_BLKS,CPSW PORT 2 maximum FIFO blocks register" bitfld.long 0x0 0.--3. " P2_RX_MAX_BLKS ,Receive FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical receive queue. This value must be greater than or equal to 0x3. It should be increased In fullduplex flow control mode to 0x5 or 0x6 depending on the required runout space. The P2_TX_MAX_BLKS value must be decreased by the amount of increase in P2_RX_MAX_BLKS. 0x3 is the minimum value P2_RX_MAX_BLKS and 0x6 is the maximum value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " P2_TX_MAX_BLKS ,Transmit FIFO Maximum Blocks - This value is the maximum number of 1k memory blocks that may be allocated to the FIFO's logical transmit priority queues. 0x11 is the recommended value of P2_TX_MAX_BLKS unless the port is in fullduplex flow control mode. In flow control mode, the P2_RX_MAX_BLKS will need to increase in order to accept the required run out in fullduplex mode. This value will need to decrease by the amount of increase in P2_RX_MAX_BLKS. 0xE is the minimum value P2_TX_MAX_BLKS." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "P2_BLK_CNT,CPSW PORT 2 FIFO block usage count (read only)" bitfld.long 0x0 0.--3. " P2_RX_BLK_CNT ,Port 2 Receive Block Count Usage - This value is the number of blocks allocated to the FIFO logical receive queues." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--8. " P2_TX_BLK_CNT ,Port 2 Transmit Block Count Usage - This value is the number of blocks allocated to the FIFO logical transmit queues." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "P2_TX_IN_CTL,CPSW PORT 2 transmit FIFO control" hexmask.long.word 0x0 0.--9. 1. " TX_PRI_WDS ,Transmit FIFO Words in queue" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--15. " TX_BLKS_REM ,Transmit FIFO Input blocks to subtract on non rate-limited traffic in rate limit mode." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--17. " TX_IN_SEL ,Transmit FIFO Input Queue Type Select 0x0 - Normal priority mode 0x1 - reserved 0x2 - Rate Limit mode 0x3 - reserved" "0,1,2,3" textline " " bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" bitfld.long 0x0 20.--23. " TX_RATE_EN ,Transmit FIFO Input Rate Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HOST_BLKS_REM ,Transmit FIFO Blocks that must be free before a non rate-limited CPDMA channel can begin sending a packet to the FIFO." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x214++0x3 line.long 0x0 "P2_PORT_VLAN,CPSW PORT 2 VLAN register" hexmask.long.word 0x0 0.--11. 1. " PORT_VID ,Port VLAN ID" bitfld.long 0x0 12. " PORT_CFI ,Port CFI bit" "0,1" textline " " bitfld.long 0x0 13.--15. " PORT_PRI ,Port VLAN Priority (7 is highest priority)" "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x218++0x3 line.long 0x0 "P2_TX_PRI_MAP,CPSW PORT 2 TX header priority to switch priority mapping register" bitfld.long 0x0 0.--1. " PRI0 ,Priority 0 - A packet header priority of 0x0 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 4.--5. " PRI1 ,Priority 1 - A packet header priority of 0x1 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8.--9. " PRI2 ,Priority 2 - A packet header priority of 0x2 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 12.--13. " PRI3 ,Priority 3 - A packet header priority of 0x3 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 14.--15. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 16.--17. " PRI4 ,Priority 4 - A packet header priority of 0x4 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 18.--19. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 20.--21. " PRI5 ,Priority 5 - A packet header priority of 0x5 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 22.--23. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 24.--25. " PRI6 ,Priority 6 - A packet header priority of 0x6 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--29. " PRI7 ,Priority 7 - A packet header priority of 0x7 is given this switch queue priority." "0,1,2,3" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x21C++0x3 line.long 0x0 "P2_TS_SEQ_MTYPE,CPSW_3GF PORT 2 time sync sequence ID offset and message type." hexmask.long.word 0x0 0.--15. 1. " P2_TS_MSG_TYPE_EN ,Port 2 Time Sync Message Type Enable - Each bit in this field enables the corresponding message type in receive and transmit time sync messages (Bit 0 enables message type 0 etc.)." bitfld.long 0x0 16.--21. " P2_TS_SEQ_ID_OFFSET ,Port 2 Time Sync Sequence ID Offset This is the number of octets that the sequence ID is offset in the tx and rx time sync message header. The minimum value is 6." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x220++0x3 line.long 0x0 "P2_SA_LO,CPSW CPGMAC_SL2 source address low register" hexmask.long.byte 0x0 0.--7. 1. " MACSRCADDR_15_8 ,Source Address bits 15:8 (byte 1)" hexmask.long.byte 0x0 8.--15. 1. " MACSRCADDR_7_0 ,Source Address Lower 8 bits (byte 0)" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x224++0x3 line.long 0x0 "P2_SA_HI,CPSW CPGMAC_SL2 source address high register" hexmask.long.byte 0x0 0.--7. 1. " MACSRCADDR_47_40 ,Source Address bits 47:40 (byte 5)" hexmask.long.byte 0x0 8.--15. 1. " MACSRCADDR_39_32 ,Source Address bits 39:32 (byte 4)" textline " " hexmask.long.byte 0x0 16.--23. 1. " MACSRCADDR_31_23 ,Source Address bits 31:23 (byte 3)" hexmask.long.byte 0x0 24.--31. 1. " MACSRCADDR_23_16 ,Source Address bits 23:16 (byte 2)" group.byte 0x228++0x3 line.long 0x0 "P2_SEND_PERCENT,CPSW PORT 2 transmit queue send percentages" hexmask.long.byte 0x0 0.--6. 1. " PRI1_SEND_PERCENT ,Priority 1 Transmit Percentage - This percentage value is sent from FIFO priority 1 (maximum) when theCPSW_PTYPE[19] P2_PRI1_SHAPE_EN is set (queue shaping enabled). This is the percentage of the wire that packets from priority 1 receive (which includes interpacket gap and preamble bytes). If shaping is enabled on this queue then this value must be between zero and 0d100 (not inclusive)." bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " hexmask.long.byte 0x0 8.--14. 1. " PRI2_SEND_PERCENT ,Priority 2 Transmit Percentage - This percentage value is sent from FIFO priority 2 (maximum) when theCPSW_PTYPE[20] P2_PRI2_SHAPE_EN is set (queue shaping enabled). This is the percentage of the wire that packets from priority 2 receive (which includes interpacket gap and preamble bytes). If shaping is enabled on this queue then this value must be between zero and 0d100 (not inclusive)." bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " hexmask.long.byte 0x0 16.--22. 1. " PRI3_SEND_PERCENT ,Priority 3 Transmit Percentage - This percentage value is sent from FIFO priority 3 (maximum) when theCPSW_PTYPE[21] P2_PRI3_SHAPE_EN is set (queue shaping enabled). This is the percentage of the wire that packets from priority 3 receive (which includes interpacket gap and preamble bytes). If shaping is enabled on this queue then this value must be between zero and 0d100 (not inclusive)." hexmask.long.word 0x0 23.--31. 1. " RESERVED ," group.byte 0x230++0x3 line.long 0x0 "P2_RX_DSCP_PRI_MAP0,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 0" bitfld.long 0x0 0.--2. " PRI0 ,Priority 0 - A packet TOS of 0d0 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI1 ,Priority 1 - A packet TOS of 0d1 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI2 ,Priority 2 - A packet TOS of 0d2 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI3 ,Priority 3 - A packet TOS of 0d3 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI4 ,Priority 4 - A packet TOS of 0d4 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI5 ,Priority 5 - A packet TOS of 0d5 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI6 ,Priority 6 - A packet TOS of 0d6 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI7 ,Priority 7 - A packet TOS of 0d7 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x234++0x3 line.long 0x0 "P2_RX_DSCP_PRI_MAP1,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 1" bitfld.long 0x0 0.--2. " PRI8 ,Priority 8 - A packet TOS of 0d8 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI9 ,Priority 9 - A packet TOS of 0d9 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI10 ,Priority 10 - A packet TOS of 0d10 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI11 ,Priority 11 - A packet TOS of 0d11 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI12 ,Priority 12 - A packet TOS of 0d12 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI13 ,Priority 13 - A packet TOS of 0d13 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI14 ,Priority 14 - A packet TOS of 0d14 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI15 ,Priority 15 - A packet TOS of 0d15 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x238++0x3 line.long 0x0 "P2_RX_DSCP_PRI_MAP2,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 2" bitfld.long 0x0 0.--2. " PRI16 ,Priority 16 - A packet TOS of 0d16 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI17 ,Priority 17 - A packet TOS of 0d17 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI18 ,Priority 18 - A packet TOS of 0d18 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI19 ,Priority 19 - A packet TOS of 0d19 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI20 ,Priority 20 - A packet TOS of 0d20 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI21 ,Priority 21 - A packet TOS of 0d21 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI22 ,Priority 22 - A packet TOS of 0d22 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI23 ,Priority 23 - A packet TOS of 0d23 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x23C++0x3 line.long 0x0 "P2_RX_DSCP_PRI_MAP3,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 3" bitfld.long 0x0 0.--2. " PRI24 ,Priority 24 - A packet TOS of 0d24 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI25 ,Priority 25 - A packet TOS of 0d25 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI26 ,Priority 26 - A packet TOS of 0d26 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI27 ,Priority 27 - A packet TOS of 0d27 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI28 ,Priority 28 - A packet TOS of 0d28 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI29 ,Priority 29 - A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI30 ,Priority 30 - A packet TOS of 0d30 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI31 ,Priority 31 - A packet TOS of 0d31 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x240++0x3 line.long 0x0 "P2_RX_DSCP_PRI_MAP4,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 4" bitfld.long 0x0 0.--2. " PRI32 ,Priority 32 - A packet TOS of 0d32 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI33 ,Priority 33 - A packet TOS of 0d33 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI34 ,Priority 34 - A packet TOS of 0d34 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI35 ,Priority 35 - A packet TOS of 0d35 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI36 ,Priority 36 - A packet TOS of 0d36 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI37 ,Priority 37 - A packet TOS of 0d37 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI38 ,Priority 38 - A packet TOS of 0d38 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI39 ,Priority 39 - A packet TOS of 0d39 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x244++0x3 line.long 0x0 "P2_RX_DSCP_PRI_MAP5,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 5" bitfld.long 0x0 0.--2. " PRI40 ,Priority 40 - A packet TOS of 0d40 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI41 ,Priority 41 - A packet TOS of 0d41 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI42 ,Priority 42 - A packet TOS of 0d42 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI43 ,Priority 43 - A packet TOS of 0d43 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI44 ,Priority 44 - A packet TOS of 0d44 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI45 ,Priority 45 - A packet TOS of 0d45 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI46 ,Priority 46 - A packet TOS of 0d46 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI47 ,Priority 47 - A packet TOS of 0d47 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x248++0x3 line.long 0x0 "P2_RX_DSCP_PRI_MAP6,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 6" bitfld.long 0x0 0.--2. " PRI48 ,Priority 48 - A packet TOS of 0d48 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI49 ,Priority 49 - A packet TOS of 0d49 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI50 ,Priority 50 - A packet TOS of 0d50 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI51 ,Priority 51 - A packet TOS of 0d51 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI52 ,Priority 52 - A packet TOS of 0d52 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI53 ,Priority 53 - A packet TOS of 0d53 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI54 ,Priority 54 - A packet TOS of 0d54 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI55 ,Priority 55 - A packet TOS of 0d55 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x24C++0x3 line.long 0x0 "P2_RX_DSCP_PRI_MAP7,CPSW PORT 2 RX DSCP priority to RX packet mapping reg 7" bitfld.long 0x0 0.--2. " PRI56 ,Priority 56 - A packet TOS of 0d56 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--6. " PRI57 ,Priority 57 - A packet TOS of 0d57 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--10. " PRI58 ,Priority 58 - A packet TOS of 0d58 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11. " RESERVED ," "0,1" textline " " bitfld.long 0x0 12.--14. " PRI59 ,Priority 59 - A packet TOS of 0d59 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 15. " RESERVED ," "0,1" textline " " bitfld.long 0x0 16.--18. " PRI60 ,Priority 60 - A packet TOS of 0d60 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " RESERVED ," "0,1" textline " " bitfld.long 0x0 20.--22. " PRI61 ,Priority 61 - A packet TOS of 0d61 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24.--26. " PRI62 ,Priority 62 - A packet TOS of 0d62 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. " RESERVED ," "0,1" textline " " bitfld.long 0x0 28.--30. " PRI63 ,Priority 63 - A packet TOS of 0d63 is mapped to this received packet priority." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x250++0x3 line.long 0x0 "P2_IDLE2LPI,Port 2 EEE Idle to LPI Counter Load Value Register" hexmask.long.tbyte 0x0 0.--19. 1. " P2_IDLE2LPI ,Port 2 EEE Idle to LPI counter load value - After CLKSTOP_REQ is asserted, this value is loaded into the port 2 idle to LPI counter on each clock that the port 2 transmit is not idle. Port 2 enters the transmit LPI state when this counter decrements to zero. This counter decrements each time the EEE prescale counter decrements to zero." hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x254++0x3 line.long 0x0 "P2_LPI2WAKE,Port 2 EEE LPI to Wake Counter Load Value Register" hexmask.long.tbyte 0x0 0.--19. 1. " P2_LPI2WAKE ,Port 2 EEE LPI to wake counter load value  When the port is in the transmit LPI state and the CLKSTOP_REQ signal is deasserted, this value is loaded into the port 2 LPI to wake counter. Transmit packet operations may begin (resume) when the LPI to wake count decrements to zero (on the pre-scale count). This is the time that the CPDMA transmit must wait before transmit (switch ingress) packet operations begin (resume after wakeup)." hexmask.long.word 0x0 20.--31. 1. " RESERVED ," width 0x0B tree.end tree "MMC3" base ad:0x480AD000 width 21. group.byte 0x0++0x3 line.long 0x0 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration." bitfld.long 0x0 0. " MADMA_EN ,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA." "0,1" bitfld.long 0x0 1. " MERGE_MEM ,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing." "0,1" textline " " bitfld.long 0x0 2.--5. " MEM_SIZE ,Memory size for FIFO buffer:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " RETMODE ,Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "MMCHS_HL_SYSCONFIG,Clock Management Configuration Register" bitfld.long 0x0 0. " SOFTRESET ,Software reset. (Optional)" "0,1" bitfld.long 0x0 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS." "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" bitfld.long 0x0 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state." "0,1,2,3" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface." bitfld.long 0x0 0. " AUTOIDLE ,Internal Clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wakeup feature control" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Power management" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,This bit is initialized to zero, and writes to it are ignored. Reads return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock" "0,1,2,3" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12.--13. " STANDBYMODE ,Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a '0'." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x114++0x3 line.long 0x0 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "MMCHS_CSRE,Card Status Response Error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit [i] is set to 1, if the corresponding bit at the same position in the response MMCHS_RSP0[i] is set to 1, the host controller indicates a card error ([CERR]) interrupt status to avoid the host driver reading the response register (MMCHS_RSP0). Note: No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register (MMCHS_RESP76) for possible card errors." hexmask.long 0x0 0.--31. 1. " CSRE ,Card status response error" group.byte 0x128++0x3 line.long 0x0 "MMCHS_SYSTEST,System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into register will not start a transfer. The buffer behaves as a stack accessible only by the local host (push and pop operations). In this mode, the Transfer Block Size ([BLEN]) and the Blocks count for current transfer ([NBLK]) are needed to generate a Buffer write ready interrupt ([BWR]) or a Buffer read ready interrupt ([BRR]) and DMA requests if enabled." bitfld.long 0x0 0. " MCKD ,MMC clock output signal data value" "0,1" bitfld.long 0x0 1. " CDIR ,Control of the CMD pin direction." "0,1" textline " " bitfld.long 0x0 2. " CDAT ,CMD input/output signal data value" "0,1" bitfld.long 0x0 3. " DDIR ,Control of the DAT[7:0] pins direction." "0,1" textline " " bitfld.long 0x0 4. " D0D ,DAT0 input/output signal data value" "0,1" bitfld.long 0x0 5. " D1D ,DAT1 input/output signal data value" "0,1" textline " " bitfld.long 0x0 6. " D2D ,DAT2 input/output signal data value" "0,1" bitfld.long 0x0 7. " D3D ,DAT3 input/output signal data value" "0,1" textline " " bitfld.long 0x0 8. " D4D ,DAT4 input/output signal data value" "0,1" bitfld.long 0x0 9. " D5D ,DAT5 input/output signal data value" "0,1" textline " " bitfld.long 0x0 10. " D6D ,DAT6 input/output signal data value" "0,1" bitfld.long 0x0 11. " D7D ,DAT7 input/output signal data value" "0,1" textline " " bitfld.long 0x0 12. " SSB ,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT)." "0,1" bitfld.long 0x0 13. " WAKD ,Wake request output signal data value" "0,1" textline " " bitfld.long 0x0 14. " SDWP ,Write protect input signal (mmci_sdwp) data value" "0,1" bitfld.long 0x0 15. " SDCD ,Card detect input signal (mmci_sdcd) data value" "0,1" textline " " bitfld.long 0x0 16. " OBI ,Out-Of-Band Interrupt (OBI) data value" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x12C++0x3 line.long 0x0 "MMCHS_CON,Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and also to configure : - specific data and command transfers for MMC cards only. - the parameters related to the card detect and write protect input signals." bitfld.long 0x0 0. " OD ,Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode when the card is either in idle, ready or ident state. It is also necessary to set this bit to 1, for a broadcast host response (see Broadcast host response register MMCHS_CON[HR])" "0,1" bitfld.long 0x0 1. " INIT ,Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock cycles. The initialisation sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider (MMCHS_SYSCTL[CLKD]) should be set to ensure that 80 clock periods are greater than 1ms. (see section 9.3, 'Power-Up', in the MMC card specification, or section 6.4 in the SD card specification). Note: in this mode, there is no command sent to the card and no response is expected" "0,1" textline " " bitfld.long 0x0 2. " HR ,Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section 4.3, 'Interrupt Mode', in the MMC specification). In order to have the host response to be generated in open drain mode, the register MMCHS_CON[OD] must be set to 1. When MMCHS_CON[CEATA] is set to 1 and MMCHS_ARG set to 0x00000000 when writing 0x00000000 into MMCHS_CMD register, the host controller performs a 'command completion signal disable' token i.e. CMD line held to '0' during 47 cycles followed by a 1." "0,1" bitfld.long 0x0 3. " STR ,Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a class 3 command (CMD20: WRITE_DAT_UNTIL_STOP)." "0,1" textline " " bitfld.long 0x0 4. " MODE ,Mode select All cards This bit select between Functional mode and SYSTEST mode." "0,1" bitfld.long 0x0 5. " DW8 ,8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliancy with MMC standard specification 4.x (see section 3.6)." "0,1" textline " " bitfld.long 0x0 6. " MIT ,MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detection to be disabled for the command response." "0,1" bitfld.long 0x0 7. " CDP ,Card detect polarity All cards This bit selects the active level of the card detect input signal (mmci_sdcd). The usage of the card detect input signal (mmci_sdcd) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1" textline " " bitfld.long 0x0 8. " WPP ,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (mmci_sdwp). The usage of the write protect input signal (mmci_sdwp) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1" bitfld.long 0x0 9.--10. " DVAL ,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (mmci_sdcd). The usage of the card detect input signal (mmci_sdcd) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1,2,3" textline " " bitfld.long 0x0 11. " CTPL ,Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards: When this bit is set to 1, the host controller automatically disables all the input buffers except the buffer of DAT[1] outside of a transaction in order to detect asynchronous card interrupt on DAT[1] line and minimize the leakage current of the buffers." "0,1" bitfld.long 0x0 12. " CEATA ,CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is used to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features." "0,1" textline " " bitfld.long 0x0 13. " OBIP ,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration." "0,1" bitfld.long 0x0 14. " OBIE ,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration." "0,1" textline " " bitfld.long 0x0 15. " PADEN ,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also combine outside the module with the dedicated power control MMCHS_CON[CTPL] bit." "0,1" bitfld.long 0x0 16. " CLKEXTFREE ,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only if MMCHS_SYSCTL[CEN] is set." "0,1" textline " " bitfld.long 0x0 17. " BOOT_ACK ,Boot acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated." "0,1" bitfld.long 0x0 18. " BOOT_CF0 ,Boot status supported: This register is set when the CMD line need to be forced to '0' for a boot sequence. CMD line is driven to '0' after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer in case of a pending transaction." "0,1" textline " " bitfld.long 0x0 19. " DDR ,Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Data bytes and CRC, Start, end bits and CRC status are kept full cycle. This bit field is only meaningful and active for even clock divider ratio of MMCHS_SYSCTL[CLKD], it is insensitive to MMCHS_HCTL[HSPE] setting." "0,1" bitfld.long 0x0 20. " DMA_MNS ,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available if generic parameter MADMA_EN is asserted to '1'." "0,1" textline " " bitfld.long 0x0 21. " SDMA_LNE ,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data written into MMCHS_DATA." "0,1" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "MMCHS_PWCNT,Power Counter Register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage." hexmask.long.word 0x0 0.--15. 1. " PWRCNT ,Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x200++0x3 line.long 0x0 "MMCHS_SDMASA,SDMA System Address / Argument 2 Register" hexmask.long 0x0 0.--31. 1. " SDMA_ARG2 ,SDMA System Address / Argument 2 This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23. (1) SDMA System Address This register contains the system memory address for a SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (003h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume command or by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register. ADMA does not use this register. (2) Argument 2 This register is used with the Auto CMD23 to set a 32-bit block count value to the argument of the CMD23 while executing Auto CMD23. If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used. If Auto CMD23 is used without AMDA, the available block count value is limited by the Block Count register. 65535 blocks is the maximum value in this case." group.byte 0x204++0x3 line.long 0x0 "MMCHS_BLK,Transfer Length Configuration Register [BLEN] is the block size register. [NBLK] is the block count register. This register shall be used for any card." hexmask.long.word 0x0 0.--11. 1. " BLEN ,Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issued to stop the transfer, a read of the BLEN field after transfer completion (MMCHS_STAT[TC] set to 1) will not return the true byte number of data length while the stop occurs but the value written in this register before transfer is launched." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " NBLK ,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[BCE]) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note: The host controller decrements the block count after each block transfer and stops when the count reaches zero. This register can be accessed only if no transaction is executing (i.e, after a transaction has stopped). Read operations during transfers may return an invalid value and write operation will be ignored. In suspend context, the number of blocks yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, The local host shall restore the previously saved block count." group.byte 0x208++0x3 line.long 0x0 "MMCHS_ARG,Command Argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary." hexmask.long 0x0 0.--31. 1. " ARG ,Command argument bits [31:0]" group.byte 0x20C++0x3 line.long 0x0 "MMCHS_CMD,Command and Transfer Mode Register [31:16] = the command register [15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into [15:0] registers during data transfer has no effect. This register shall be used for any card. Note: In SYSTEST mode, a write into register will not start a transfer." bitfld.long 0x0 0. " DE ,DMA EnableThis bit is used to enable DMA mode for host data access. ." "0,1" bitfld.long 0x0 1. " BCE ,Block Count EnableMultiple block transfers only. . This bit is used to enable the block count register ([NBLK]). . When Block Count is disabled ([BCE] is set to 0) in Multiple block transfers ([MSBS] is set to 1), the module can perform infinite transfer. ." "0,1" textline " " bitfld.long 0x0 2.--3. " ACEN ,Auto CMD Enable - SD card only.This field determines use of auto command functions. . There are two methods to stop Multiple-block read and write operation .  Auto CMD23 Supported (Host Controller Version is 3.00 or later) .  A memory card that supports CMD23 (SCR[33]=1) .  If DMA is used, it shall be ADMA. . Only when CMD18 or CMD25 is issued . (Note: the Host Controller does not check command index.) . Auto CMD23 can be used with or without ADMA. By writing the Command register, the Host Controller issues a CMD23 first and then issues a command specified by the Command Index in Command register. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the Auto CMD Error Status register (). 32-bit block count value for CMD23 is set to SDMA System Address / Argument 2 register (). ." "0,1,2,3" bitfld.long 0x0 4. " DDIR ,Data transfer Direction SelectThis bit defines either data transfer will be a read or a write. ." "0,1" textline " " bitfld.long 0x0 5. " MSBS ,Multi/Single block selectThis bit must be set to 1 for data transfer in case of multi block command. . For any others command this bit shall be set to 0. . If this bit is 0, it is not necessary to set the register[NBLK]. enum=sgleblk . When Block Count is disabled ([BCE] is set to 0) in Multiple block transfers ([MSBS] is set to 1), the module can perform infinite transfer. enum=multiblk ." "0,1" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " RSP_TYPE ,Response typeThis bits defines the response type of the command ." "0,1,2,3" bitfld.long 0x0 18. " RESERVED ," "0,1" textline " " bitfld.long 0x0 19. " CCCE ,Command CRC check enableThis bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. . If an error is detected, it is reported as a command CRC error ([CCRC] set to 1). . Note: The register CCCE cannot be configured for an Auto CMD12, and then CRC check is automatically checked when this command is issued. ." "0,1" bitfld.long 0x0 20. " CICE ,Command Index check enableThis bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. . If the index is not the same in the response as in the command, it is reported as a command index error ([CIE] set to1). . Note:The register CICE cannot be configured for an Auto CMD12, then index check is automatically checked when this command is issued. ." "0,1" textline " " bitfld.long 0x0 21. " DP ,Data present selectThis register indicates that data is present and DAT line shall be used. . It must be set to 0 in the following conditions: . - command using only CMD line . - command with no data transfer but using busy signal on DAT[0] . - Resume command ." "0,1" bitfld.long 0x0 22.--23. " CMD_TYPE ,Command typeThis register specifies three types of special command: Suspend, Resume and Abort. . These bits shall be set to 00b for all other commands. ." "0,1,2,3" textline " " bitfld.long 0x0 24.--29. " INDX ,Command indexBinary encoded value from 0 to 63 specifying the command number send to card ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x210++0x3 line.long 0x0 "MMCHS_RSP10,Command Response[31:0] Register (bits [31:0] of the internal RSP register) This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6/R7" hexmask.long.word 0x0 0.--15. 1. " RSP0 ,Command Response [15:0]" hexmask.long.word 0x0 16.--31. 1. " RSP1 ,Command Response [31:16]" group.byte 0x214++0x3 line.long 0x0 "MMCHS_RSP32,Command Response[63:32] Register (bits [63:32] of the internal RSP register) This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x0 0.--15. 1. " RSP2 ,Command Response [47:32]" hexmask.long.word 0x0 16.--31. 1. " RSP3 ,Command Response [63:48]" group.byte 0x218++0x3 line.long 0x0 "MMCHS_RSP54,Command Response[95:64] Register (bits [95:64] of the internal RSP register) This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x0 0.--15. 1. " RSP4 ,Command Response [79:64]" hexmask.long.word 0x0 16.--31. 1. " RSP5 ,Command Response [95:80]" group.byte 0x21C++0x3 line.long 0x0 "MMCHS_RSP76,Command Response[127:96] Register (bits [127:96] of the internal RSP register) This 32-bit register holds bits positions [127:96] of command response type R1(Auto CMD23)/R1b(Auto CMD12)/R2" hexmask.long.word 0x0 0.--15. 1. " RSP6 ,Command Response [111:96]" hexmask.long.word 0x0 16.--31. 1. " RSP7 ,Command Response [127:112]" group.byte 0x220++0x3 line.long 0x0 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bits x256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register or on the most significant byte of the last word of block transfer. Example 1: Byte or 16-bit access Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad" hexmask.long 0x0 0.--31. 1. " DATA ,Data Register [31:0] In functional mode (MMCHS_CON[MODE] set to the default value 0) , A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCHS_PSTATE[BRE]), otherwise a bad access (MMCHS_STAT[BADA]) is signaled. A write access to this register is allowed only when the buffer write enable status is set to 1(MMCHS_STATE[BWE]), otherwise a bad access (MMCHS_STAT[BADA]) is signaled and the data is not written." group.byte 0x224++0x3 line.long 0x0 "MMCHS_PSTATE,Present State Register The Host can get status of the Host Controller from this 32-bit read only register." bitfld.long 0x0 0. " CMDI ,Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0 in either the following cases: - After the end bit of the command response, excepted if there is a command conflict error (MMCHS_STAT[CCRC] or MMCHS_STAT[CEB] set to 1) or a Auto CMD12 is not executed (MMCHS_AC12[ACNE]). - After the end bit of the command without response (MMCHS_CMD[RSP_TYPE] set to '00') In case of a command data error is detected (MMCHS_STAT[CTO] set to 1), this register is not automatically cleared." "0,1" bitfld.long 0x0 1. " DATI ,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[DLA]) or Read transfer is active (MMCHS_PSTATE[RTA]) or when a command with busy is issued. This bit prevents the local host to issue a command. A change of this bit from 1 to 0 generates a transfer complete interrupt (MMCHS_STAT[TC])." "0,1" textline " " bitfld.long 0x0 2. " DLA ,DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue request MMCHS_HCTL[CR]. This bit is set to 0 when the host controller received the end bit of the last data block or at the beginning of the read wait mode. In the case of write transactions (host to card): This bit is set to 1 after the end bit of write command or by activating continue request MMCHS_HCTL[CR]. This bit is set to 0 on the end of busy event for the last block; host controller must wait 8 clock cycles with line not busy to really consider not 'busy state' or after the busy block as a result of a stop at gap request." "0,1" bitfld.long 0x0 3. " RTR ,Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is cleared when a command is issued with setting MMCHS_AC12[22] ET. This bit isn't set to 1 if MMCHS_AC12[23] SCLK_SEL is set to 0 (using fixed sampling clock). Refer to MMCHS_CAPA2[15:14] RTM for more detail." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " WTA ,Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[CR]) following a stop at block gap request. This bit is set to 0 when CRC status has been received after last block or after a stop at block gap request." "0,1" textline " " bitfld.long 0x0 9. " RTA ,Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[CR]) following a stop at block gap request. This bit is set to 0 when all data have been read by the local host after last block or after a stop at block gap request." "0,1" bitfld.long 0x0 10. " BWE ,Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data." "0,1" textline " " bitfld.long 0x0 11. " BRE ,Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[BLEN] has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from the buffer. It is set to 1 when a block data is ready in the buffer and generates the Buffer read ready status of interrupt (MMCHS_STAT[BRR])." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " CINS ,Card inserted This bit is the debounced value of the card detect input pin (mmci_sdcd). An inactive to active transition of the card detect input pin (mmci_sdcd) will generate a card insertion interrupt (MMCHS_STAT[CINS]). A active to inactive transition of the card detect input pin (mmci_sdcd) will generate a card removal interrupt (MMCHS_STAT[REM]). This bit is not affected by a software reset." "0,1" bitfld.long 0x0 17. " CSS ,Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[CDPL]). Debouncing is performed on the card detect input pin (mmci_sdcd) to detect card stability. This bit is not affected by a software reset." "0,1" textline " " bitfld.long 0x0 18. " CDPL ,Card detect pin level This bit reflects the inverse value of the card detect input pin (mmci_sdcd), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTAE[CSS]) is set to 1. Use of this bit is limited to testing since it must be debounced y software. The value of this register after reset depends on the card detect input pin (mmci_sdcd) level at that time." "0,1" bitfld.long 0x0 19. " WP ,Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (mmci_sdwp) level. The value of this register after reset depends on the protect input pin (mmci_sdwp) level at that time." "0,1" textline " " bitfld.long 0x0 20.--23. " DLEV ,DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. The value of these registers after reset depends on the DAT lines level at that time." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " CLEV ,CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time." "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x228++0x3 line.long 0x0 "MMCHS_HCTL,Host Control Register This register defines the host controls to set power, wakeup and transfer parameters. [31:24] = Wakeup control [23:16] = Block gap control [15:8] = Power control [7:0] = Host control" bitfld.long 0x0 0. " LED ,Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored." "0,1" bitfld.long 0x0 1. " DTW ,Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliance with MMC standard specification 4.x (see section 3.6). This register has no effect when the MMC 8-bit mode is selected (register MMCHS_CON[DW8] set to1 ), For SD/SDIO cards, this bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument. Prior to this command, the SD card configuration register (SCR) must be verified for the supported bus width by the SD card." "0,1" textline " " bitfld.long 0x0 2. " HSPE ,Before setting this bit, the Host Driver shall check theMMCHS_CAPA[21] HSS. This bit shall not be set when dual data rate mode is activated in MMCHS_CON[DDR]." "0,1" bitfld.long 0x0 3.--4. " DMAS ,DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register MMCHS_CAPA . Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This register is only meaningful when MADMA_EN is set to 1. When MADMA_EN is set to 0 the bit field is read only and returned value is 0." "0,1,2,3" textline " " bitfld.long 0x0 5. " RESERVED ," "0,1" bitfld.long 0x0 6. " CDTL ,Card Detect Test Level: This bit is enabled while MMCHS_HCTL[7] CDSS is set to 1 and it indicates whether the card is inserted or not." "0,1" textline " " bitfld.long 0x0 7. " CDSS ,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in order to mask unexpected interrupts caused by the glitch. The Interrupt Status/Signal Enable should be disabled during over the period of debouncing." "0,1" bitfld.long 0x0 8. " SDBP ,SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[SDVS]). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in the command register (MMCHS_CMD) will not start the transfer. A write to this bit has no effect if the selected SD bus voltage MMCHS_HCTL[SDVS] is not supported according to capability register (MMCHS_CAPA[VS*])." "0,1" textline " " bitfld.long 0x0 9.--11. " SDVS ,SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[VS18,VS30,VS33]) before starting a transfer." "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " SBGR ,Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[CR]) or during a suspend/resume sequence. In case of read transfer, the card must support read wait control. In case of write transfer, the host driver shall set this bit after all block data written. Until the transfer completion (MMCHS_STAT[TC] set to 1), the host driver shall leave this bit set to 1. If this bit is set, the local host shall not write to the data register (MMCHS_DATA)." "0,1" bitfld.long 0x0 17. " CR ,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[SBGR]). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when transfer has restarted i.e DAT line is active (MMCHS_PSTATE[DLA]) or transferring data (MMCHS_PSTATE[WTA]). The Stop at block gap request must be disabled (MMCHS_HCTL[SBGR]=0) before setting this bit." "0,1" textline " " bitfld.long 0x0 18. " RWC ,Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[SBGR]) generates a read wait period after the current end of block. Be careful, if read wait is not supported it may cause a conflict on DAT line." "0,1" bitfld.long 0x0 19. " IBG ,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be set to 0." "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " IWE ,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" textline " " bitfld.long 0x0 25. " INS ,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" bitfld.long 0x0 26. " REM ,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" textline " " bitfld.long 0x0 27. " OBWE ,Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP]). The write to this register is ignored when MMCHS_CON[OBIE] is not set." "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "MMCHS_SYSCTL,SD System Control Register This register defines the system controls to set software resets, clock frequency management and data timeout. [31:24] = Software resets [23:16] = Timeout control [15:0] = Clock control" bitfld.long 0x0 0. " ICE ,Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface clock (used for reads and writes to the module register map) are not affected by this register." "0,1" bitfld.long 0x0 1. " ICS ,Internal clock stable (status) This bit indicates either the internal clock is stable or not." "0,1" textline " " bitfld.long 0x0 2. " CEN ,Clock enable This bit controls if the clock is provided to the card or not." "0,1" bitfld.long 0x0 3.--4. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 5. " CGS ,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit. This bit is used to select the clock generator mode in MMCHS_SYSCTL[15:6] CLKD. If the Programmable Clock Mode is supported (non-zero value is set to MMCHS_CAPA2[23:16] CM), this bit attribute is RW, and if not supported, this bit attribute is RO and zero is read. This bit depends on the setting of MMCHS_AC12[31] PV_ENABLE. If PV_ENABLE = 0, this bit is set by Host Driver. If PV_ENABLE = 1, this bit is automatically set to a value specified in one of Preset Value registers, see, ." "0,1" hexmask.long.word 0x0 6.--15. 1. " CLKD ,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO)." textline " " bitfld.long 0x0 16.--19. " DTO ,Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bitfield based on - the maximum read access time (NAC) (Refer to the SD Specification Part1 Physical Layer), - the data read access time values (TAAC and NSAC) in the card specific data register (CSD) of the card, - the timeout clock base frequency (MMCHS_CAPA[TCF]). If the card does not respond within the specified number of cycles, a data timeout error occurs (MMCHS_STA[DTO]). The MMCHS_SYSCTL[DTO] register is also used to check busy duration, to generate busy timeout for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SRA ,Software reset for all This bit is set to 1 for reset , and released to 0 when completed. This reset affects the entire host controller except for the capabilities registers (MMCHS_CAPA and MMCHS_CUR_CAPA)." "0,1" bitfld.long 0x0 25. " SRC ,Software reset for CMD line For more information about SRC bit manipulation, see CMD Line Reset Procedure. This bit is set to 1 for reset and released to 0 when completed. CMD finite state machine in both clock domain are also reset. Here below the registers cleared by MMCHS_SYSCTL[SRC]: - MMCHS_PSTATE: CMDI - MMCHS_STAT: CC Interconnect and MMC command status management is reinitialized." "0,1" textline " " bitfld.long 0x0 26. " SRD ,Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see DATA Lines Reset Procedure. DAT finite state machine in both clock domain are also reset. Here below are the registers cleared by MMCHS_SYSCTL[SRD]: - MMCHS_DATA - MMCHS_PSTATE: BRE, BWE, RTA, WTA, DLA and DATI - MMCHS_HCTL: SBGR and CR - MMCHS_STAT: BRR, BWR, BGE and TC Interconnect and MMC buffer data management is reinitialized." "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x230++0x3 line.long 0x0 "MMCHS_STAT,Interrupt Status Register The interrupt status regroups all the status of the module internal events that can generate an interrupt. [31:16] = Error Interrupt Status [15:0] = Normal Interrupt Status" bitfld.long 0x0 0. " CC ,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[CMDI]) If the command is a type for which no response is expected, then the command complete interrupt is generated at the end of the command. A command timeout error (MMCHS_STAT[CTO]) has higher priority than command complete (MMCHS_STAT[CC]). If a response is expected but none is received, then a command timeout error is detected and signaled instead of the command complete interrupt." "0,1" bitfld.long 0x0 1. " TC ,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[SBGR]). In Read mode: This bit is automatically set on completion of a read transfer (MMCHS_PSTATE[RTA]). In write mode: This bit is set automatically on completion of the DAT line use (MMCHS_PSTATE[DLA])." "0,1" textline " " bitfld.long 0x0 2. " BGE ,Block gap event When a stop at block gap is requested (MMCHS_HCTL[SBGR]), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap is requested on the last block. In read mode, a 1-to-0 transition of the DAT Line active status (MMCHS_PSTATE[DLA]) between data blocks generates a Block gap event interrupt." "0,1" bitfld.long 0x0 3. " DMA ,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion." "0,1" textline " " bitfld.long 0x0 4. " BWR ,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[BLEN]. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer. Note: If the DMA transmit mode is enabled, this bit is never set; instead, a DMA transmit request to the main DMA controller of the system is generated." "0,1" bitfld.long 0x0 5. " BRR ,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[BLEN] is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by reading it. Note: If the DMA receive-mode is enabled, this bit is never set; instead a DMA receive request to the main DMA controller of the system is generated." "0,1" textline " " bitfld.long 0x0 6. " CINS ,Card insertion This bit is set automatically when MMCHS_PSTATE[CINS] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[CINS])." "0,1" bitfld.long 0x0 7. " CREM ,Card removal This bit is set automatically when MMCHS_PSTATE[CINS] changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[CINS])." "0,1" textline " " bitfld.long 0x0 8. " CIRQ ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drives CMD line to zero during one cycle after data transmission end.All modes above are fully exclusive. The controller interrupt must be clear by setting MMCHS_IE[CIRQ] to 0, then the host driver must start the interrupt service with card (clearing card interrupt status) to remove card interrupt source. Otherwise the Controller interrupt will be reasserted as soon as MMCHS_IE[CIRQ] is set to 1. Writes to this bit are ignored." "0,1" bitfld.long 0x0 9. " OBI ,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[OBIE] is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[OBIP]. This interrupt is only useful for MMC card. The Out-of-Band interrupt signal is a system specific feature for future use, this signal is not required for existing specification implementation." "0,1" textline " " bitfld.long 0x0 10. " BSR ,Boot status received interrupt This bit is set automatically when MMCHS_CON[BOOT] is set 0x1 or 0x2 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " ERRI ,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[31:16]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored." "0,1" bitfld.long 0x0 16. " CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles." "0,1" textline " " bitfld.long 0x0 17. " CCRC ,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[CCCE] register." "0,1" bitfld.long 0x0 18. " CEB ,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response." "0,1" textline " " bitfld.long 0x0 19. " CIE ,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[CICE] register." "0,1" bitfld.long 0x0 20. " DTO ,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout" "0,1" textline " " bitfld.long 0x0 21. " DCRC ,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command." "0,1" bitfld.long 0x0 22. " DEB ,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode." "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE ,Auto CMD error Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register (MMCHS_AC12) has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to the previous command error." "0,1" textline " " bitfld.long 0x0 25. " ADMAE ,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller generates this interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state. The Host Driver may find that Valid bit is not set at the error descriptor." "0,1" bitfld.long 0x0 26. " TE ,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Select). By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. To reset tuning circuit, Sampling Clock shall be set to 0 before executing tuning procedure. The Tuning Error is higher priority than the other error interrupts generated during data transfer. By detecting Tuning Error, the Host Driver should discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from tuning circuit error. The bit is set if the lock is lost (but not during the tuning process) or if the lock counter expires without the lock being asserted. If the latter happens, the SW can decide to ignore the interrupt and wait some more for the lock to be set." "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR ,Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error MMCHS_CSRE in set. There is no card error detection for autoCMD12 command. The host driver shall read MMCHS_RSP76 register to detect error bits in the command response." "0,1" textline " " bitfld.long 0x0 29. " BADA ,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[BRE] =0) -This bit is set during a write access to the data register (MMCHS_DATA) while buffer writes are not allowed (MMCHS_STATE[BWE] =0)" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x234++0x3 line.long 0x0 "MMCHS_IE,Interrupt Status Enable Register This register allows to enable/disable the module to set status bits, on an event-by-event basis. [31:16] = Error Interrupt Status Enable [15:0] = Normal Interrupt Status Enable" bitfld.long 0x0 0. " CC_ENABLE ,Command Complete Status Enable" "0,1" bitfld.long 0x0 1. " TC_ENABLE ,Transfer Complete Status Enable" "0,1" textline " " bitfld.long 0x0 2. " BGE_ENABLE ,Block Gap Event Status Enable" "0,1" bitfld.long 0x0 3. " DMA_ENABLE ,DMA Status Enable" "0,1" textline " " bitfld.long 0x0 4. " BWR_ENABLE ,Buffer Write Ready Status Enable" "0,1" bitfld.long 0x0 5. " BRR_ENABLE ,Buffer Read Ready Status Enable" "0,1" textline " " bitfld.long 0x0 6. " CINS_ENABLE ,Card Insertion Status Enable" "0,1" bitfld.long 0x0 7. " CREM_ENABLE ,Card Removal Status Enable" "0,1" textline " " bitfld.long 0x0 8. " CIRQ_ENABLE ,Card Status Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1." "0,1" bitfld.long 0x0 9. " OBI_ENABLE ,Out-of-Band Status Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored." "0,1" textline " " bitfld.long 0x0 10. " BSR_ENABLE ,Boot Status Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x0 16. " CTO_ENABLE ,Command Timeout Error Status Enable" "0,1" textline " " bitfld.long 0x0 17. " CCRC_ENABLE ,Command CRC Error Status Enable" "0,1" bitfld.long 0x0 18. " CEB_ENABLE ,Command End Bit Error Status Enable" "0,1" textline " " bitfld.long 0x0 19. " CIE_ENABLE ,Command Index Error Status Enable" "0,1" bitfld.long 0x0 20. " DTO_ENABLE ,Data Timeout Error Status Enable" "0,1" textline " " bitfld.long 0x0 21. " DCRC_ENABLE ,Data CRC Error Status Enable" "0,1" bitfld.long 0x0 22. " DEB_ENABLE ,Data End Bit Error Status Enable" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE_ENABLE ,Auto CMD Error Status Enable" "0,1" textline " " bitfld.long 0x0 25. " ADMAE_ENABLE ,ADMA Error Status Enable" "0,1" bitfld.long 0x0 26. " TE_ENABLE ,Tuning Error Status Enable" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR_ENABLE ,Card Error Status Enable" "0,1" textline " " bitfld.long 0x0 29. " BADA_ENABLE ,Bad access to data space Status Enable" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x238++0x3 line.long 0x0 "MMCHS_ISE,Interrupt Signal Enable Register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. [31:16] = Error Interrupt Signal Enable [15:0] = Normal Interrupt Signal Enable" bitfld.long 0x0 0. " CC_SIGEN ,Command Complete Status Enable" "0,1" bitfld.long 0x0 1. " TC_SIGEN ,Transfer Completed Status Enable" "0,1" textline " " bitfld.long 0x0 2. " BGE_SIGEN ,Black Gap Event Signal Enable" "0,1" bitfld.long 0x0 3. " DMA_SIGEN ,DMA Interrupt Signal Enable" "0,1" textline " " bitfld.long 0x0 4. " BWR_SIGEN ,Buffer Write Ready Signal Enable" "0,1" bitfld.long 0x0 5. " BRR_SIGEN ,Buffer Read Ready Signal Enable" "0,1" textline " " bitfld.long 0x0 6. " CINS_SIGEN ,Card Insertion Signal Enable" "0,1" bitfld.long 0x0 7. " CREM_SIGEN ,Card Removal Signal Enable" "0,1" textline " " bitfld.long 0x0 8. " CIRQ_SIGEN ,Card Interrupt Signal Enable" "0,1" bitfld.long 0x0 9. " OBI_SIGEN ,Out-Of-Band Interrupt Signal Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored." "0,1" textline " " bitfld.long 0x0 10. " BSR_SIGEN ,Boot Status Signal Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x0 16. " CTO_SIGEN ,Command timeout Error Signal Enable" "0,1" textline " " bitfld.long 0x0 17. " CCRC_SIGEN ,Command CRC Error Signal Enable" "0,1" bitfld.long 0x0 18. " CEB_SIGEN ,Command End Bit Error Signal Enable" "0,1" textline " " bitfld.long 0x0 19. " CIE_SIGEN ,Command Index Error Signal Enable" "0,1" bitfld.long 0x0 20. " DTO_SIGEN ,Data Timeout Error Signal Enable" "0,1" textline " " bitfld.long 0x0 21. " DCRC_SIGEN ,Data CRC Error Signal Enable" "0,1" bitfld.long 0x0 22. " DEB_SIGEN ,Data End Bit Error Signal Enable" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE_SIGEN ,Auto CMD Error Signal Enable" "0,1" textline " " bitfld.long 0x0 25. " ADMAE_SIGEN ,ADMA Error Signal Enable" "0,1" bitfld.long 0x0 26. " TE_SIGEN ,Tuning Error Signal Enable" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR_SIGEN ,Card Error Interrupt Signal Enable" "0,1" textline " " bitfld.long 0x0 29. " BADA_SIGEN ,Bad access to data space Signal Enable" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x23C++0x3 line.long 0x0 "MMCHS_AC12,Host Control 2 Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12 / CMD23 errors occur by this register. Auto CMD23 errors are indicated only in bits[4:1]. Bits[7:0] are valid only when the [3:2] ACEN bitfield is configured to enable Auto CMD and the Auto CMD Error bit ([24]ACE) is set." bitfld.long 0x0 0. " ACNE ,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the Host Controller cannot issue Auto CMD12 to stop memory multiple block data transfer due to some error. If this bit is set to 1, other error status bits (D04-D01) are meaningless. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" bitfld.long 0x0 1. " ACTO ,Auto CMD Timeout Error - For Auto CMD12 and Auto CMD23 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command. If this bit is set to1, the other error status bits (D04-D02) are meaningless." "0,1" textline " " bitfld.long 0x0 2. " ACCE ,Auto CMD CRC Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting a CRC error in the command response." "0,1" bitfld.long 0x0 3. " ACEB ,Auto CMD End Bit Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting that the end bit of command response is 0." "0,1" textline " " bitfld.long 0x0 4. " ACIE ,Auto CMD Index Error - For Auto CMD12 and Auto CMD23 This bit is set if the Command Index error occurs in response to a command." "0,1" bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 7. " CNI ,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " UHSMS ,UHS Mode Select This field is used to select one of UHS-I modes or eMMC HS200 mode and is effective when 1.8V Signaling Enable is set to 1. If MMCHS_AC12[31] PV_ENABLE is set to 1, Host Controller sets MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL according to Preset Value registers, see, . In this case, one of preset value registers is selected by this field. Host Driver needs to reset MMCHS_SYSCTL[2] CEN before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets MMCHS_SYSCTL[2] CEN again. When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more detail." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " V1V8_SIGEN ,1.8V Signaling Enable This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails. Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V. 3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling (One of support bits is set to 1: SDR50, SDR104 or DDR50 in MMCHS_CAPA2 register) and the card or device supports UHS-I (S18A=1. Refer to Bus Signal Voltage Switch Sequence in the Physical Layer Specification Version 3.0x)." "0,1" textline " " bitfld.long 0x0 20.--21. " DS_SEL ,Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set depending on Driver Type A, C and D support bits (DTA, DTC and DTD respectively) in the MMCHS_CAPA2 register. This bit depends on setting of Preset Value Enable. If Preset Value Enable = 0, this field is set by Host Driver. If Preset Value Enable = 1, this field is automatically set by a value specified in the one of Preset Value registers, see, ." "0,1,2,3" bitfld.long 0x0 22. " ET ,Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to MMCHS_AC12[23] SCLK_SEL. Tuning procedure is aborted by writing 0. This is Read-Write with automatic clear register" "0,1" textline " " bitfld.long 0x0 23. " SCLK_SEL ,Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is set by tuning procedure and valid after the completion of tuning (when MMCHS_AC12[22] ET is cleared). Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Writing 1 to this bit is meaningless and ignored. A tuning circuit is reset by writing to 0. This bit can be cleared with setting MMCHS_AC12[22] ET. Once the tuning circuit is reset, it will take time to complete tuning sequence. Therefore, Host Driver should keep this bit to 1 to perform re-tuning sequence to compete re-tuning sequence in a short time. Change of this bit is not allowed while the Host Controller is receiving response or a read data block." "0,1" bitfld.long 0x0 24.--29. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " AI_ENABLE ,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and MMCHS_CAPA[29] AIS is set to 1. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver the Card Interrupt to the host when it is asserted by the Card." "0,1" bitfld.long 0x0 31. " PV_ENABLE ,Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When Preset Value Enable is set, automatic SDCLK frequency generation and driver strength selection is performed without considering system specific conditions. This bit enables the functions defined in the Preset Value registers, see, . If this bit is set to 0, MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL are set by Host Driver. If this bit is set to 1, MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL are set by Host Controller as specified in the Preset Value registers, see, ." "0,1" group.byte 0x240++0x3 line.long 0x0 "MMCHS_CAPA,Capabilities Register This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x0 0.--5. " TCF ,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[DTO])." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " RESERVED ," "0,1" textline " " bitfld.long 0x0 7. " TCU ,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[DTO])." "0,1" hexmask.long.byte 0x0 8.--15. 1. " BCF ,Base Clock Frequency For SD Clock This value indicates the base (maximum) clock frequency for the SD Clock. 8-bit Base Clock Frequency This mode is supported by the Host Controller Version 3.00. Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh : 255MHz .... : ....... 02h : 2MHz 01h : 1MHz 00h : Get information via another method If the real frequency is 16.5MHz, the lager value shall be set 0001 0001b (17MHz) because the Host Driver use this value to calculate the clock divider value (Refer to MMCHS_SYSCTL[15:6] CLKD) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method." textline " " bitfld.long 0x0 16.--17. " MBL ,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 bytes. The host controller supports 512 bytes and 1024 bytes block transfers." "0,1,2,3" bitfld.long 0x0 18. " RESERVED ," "0,1" textline " " bitfld.long 0x0 19. " AD2S ,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2. It depends on setting of generic parameter MADMA_EN" "0,1" bitfld.long 0x0 20. " RESERVED ," "0,1" textline " " bitfld.long 0x0 21. " HSS ,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency." "0,1" bitfld.long 0x0 22. " DS ,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly." "0,1" textline " " bitfld.long 0x0 23. " SRS ,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality." "0,1" bitfld.long 0x0 24. " VS33 ,Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" textline " " bitfld.long 0x0 25. " VS30 ,Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" bitfld.long 0x0 26. " VS18 ,Voltage support 1.8V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " BIT64 ,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus." "0,1" textline " " bitfld.long 0x0 29. " AIS ,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x244++0x3 line.long 0x0 "MMCHS_CAPA2,Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer to Software Reset For All in the Software Reset register for loading from flash memory and completion timing control." bitfld.long 0x0 0. " SDR50 ,SDR50 Support If SDR104 is supported, this bit shall be set to 1. Bit 13 indicates whether SDR50 requires tuning or not." "0,1" bitfld.long 0x0 1. " SDR104 ,SDR104 Support SDR104 requires tuning." "0,1" textline " " bitfld.long 0x0 2. " DDR50 ,DDR50 Support" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " DTA ,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling." "0,1" bitfld.long 0x0 5. " DTC ,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling." "0,1" textline " " bitfld.long 0x0 6. " DTD ,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling." "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--11. " TCRT ,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 0 disables Re-Tuning Timer." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13. " TSDR50 ,Use Tuning for SDR50 If this bit is set to 1, this Host Controller requires tuning to operate SDR50. (Tuning is always required to operate SDR104.)" "0,1" bitfld.long 0x0 14.--15. " RTM ,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length." "0,1,2,3" textline " " hexmask.long.byte 0x0 16.--23. 1. " CM ,Clock Multiplier This field indicates clock multiplier value of programmable clock generator. Refer to MMCHS_SYSCTL [15:0]. Setting 00h means that Host Controller does not support programmable clock generator. 00h : Clock Multiplier is Not Supported 01h : Clock Multiplier M = 2 02h : Clock Multiplier M = 3 .... : ...................... FFh : Clock Multiplier M = 256" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x248++0x3 line.long 0x0 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (). Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" hexmask.long.byte 0x0 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V" hexmask.long.byte 0x0 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V" textline " " hexmask.long.byte 0x0 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "MMCHS_FE,Force Event Register for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register. Rather, it is an address at which the Auto CMD Error Status Register () can be written. Writing 1 : set each bit of the Auto CMD Error Status Register Writing 0 : no effect Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register if the corresponding bit of the Error Interrupt Status Enable Register is set. Writing 1 : set each bit of the Error Interrupt Status Register Writing 0 : no effect Note: By setting this register, the Error Interrupt can be set in the Error Interrupt Status register. In order to generate interrupt signal, both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be set." bitfld.long 0x0 0. " FE_ACNE ,Force Event Auto CMD12 Not Executed" "0,1" bitfld.long 0x0 1. " FE_ACTO ,Force Event Auto CMD Timeout Error" "0,1" textline " " bitfld.long 0x0 2. " FE_ACCE ,Force Event Auto CMD CRC Error" "0,1" bitfld.long 0x0 3. " FE_ACEB ,Force Event Auto CMD End Bit Error" "0,1" textline " " bitfld.long 0x0 4. " FE_ACIE ,Force Event for Auto CMD Index Error - For Auto CMD12 and Auto CMD23" "0,1" bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error" "0,1" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " FE_CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles." "0,1" bitfld.long 0x0 17. " FE_CCRC ,Force Event Command CRC Error." "0,1" textline " " bitfld.long 0x0 18. " FE_CEB ,Force Event Command End Bit Error." "0,1" bitfld.long 0x0 19. " FE_CIE ,Force Event Command Index Error." "0,1" textline " " bitfld.long 0x0 20. " FE_DTO ,Force Event Data Timeout Error." "0,1" bitfld.long 0x0 21. " FE_DCRC ,Force Event Data CRC Error." "0,1" textline " " bitfld.long 0x0 22. " FE_DEB ,Force Event Data End Bit error." "0,1" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24. " FE_ACE ,Force Event for Auto CMD Error - For Auto CMD12 and Auto CMD23" "0,1" bitfld.long 0x0 25. " FE_ADMAE ,Force Event ADMA Error." "0,1" textline " " bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" bitfld.long 0x0 28. " FE_CERR ,Force Event Card error." "0,1" textline " " bitfld.long 0x0 29. " FE_BADA ,Force Event Bad access to data space." "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x254++0x3 line.long 0x0 "MMCHS_ADMAES,ADMA Error Status Register When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the error, the Host Driver requires the ADMA state to identify the error descriptor address as follows: ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address ST_FDS: Current location set in the ADMA System Address register is the error descriptor address ST_CADR: This sate is never set because do not generate ADMA error in this state. ST_TFR: Previous location set in the ADMA System Address register is the error descriptor address In case of write operation, the Host Driver should use ACMD22 to get the number of written block rather than using this information, since unwritten data may exist in the Host Controller. The Host Controller generates the ADMA Error Interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. In this case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host Driver may find that the Valid bit is not set in the error descriptor." bitfld.long 0x0 0.--1. " AES ,ADMA Error StateThis field indicates the state of ADMA when error occurred during ADMA data transfer. This field will never be 0x2 because ADMA never stops in that state.0x0: ST_STOP (STOP_ADMA). Previous SYS_ADR is the error descriptor address0x1: ST_FDS (Fetch Descriptor). Content of current SYS_ADR is the error descriptor address0x2: Not used. Error never set in this state0x3: ST_TFR (Transfer Data). Previous SYS_ADR is the error descriptor address" "0,1,2,3" bitfld.long 0x0 2. " LME ,ADMA Length Mismatch Error: (1) While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. (2) Total data length can not be divided by the block length." "0,1" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x258++0x3 line.long 0x0 "MMCHS_ADMASAL,ADMA System address Low bits" hexmask.long 0x0 0.--31. 1. " ADMA_A32B ,ADMA System address 32 bits.This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32-bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold valid Descriptor address depending on the ADMA state. The Host Driver shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. ADMA2 ignores lower 2-bit of this register and assumes it to be 00b." group.byte 0x260++0x3 line.long 0x0 "MMCHS_PVINITSD,Preset Value for Initialization and Default Speed modes" hexmask.long.word 0x0 0.--9. 1. " INITSDCLK_SEL ,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " INITCLKGEN_SEL ,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " INITDS_SEL ,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " DSSDCLK_SEL ,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " DSCLKGEN_SEL ,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " DSDS_SEL ,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x264++0x3 line.long 0x0 "MMCHS_PVHSSDR12,Preset Value for High Speed and SDR12 speed modes" hexmask.long.word 0x0 0.--9. 1. " HSSDCLK_SEL ,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " HSCLKGEN_SEL ,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " HSDS_SEL ,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " SDR12SDCLK_SEL ,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " SDR12CLKGEN_SEL ,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SDR12DS_SEL ,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x268++0x3 line.long 0x0 "MMCHS_PVSDR25SDR50,Preset Value for SDR25 and SDR50 speed modes" hexmask.long.word 0x0 0.--9. 1. " SDR25SDCLK_SEL ,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " SDR25CLKGEN_SEL ,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " SDR25DS_SEL ,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " SDR50SDCLK_SEL ,SDCLK Frequency Select Value - SDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " SDR50CLKGEN_SEL ,Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SDR50DS_SEL ,Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x26C++0x3 line.long 0x0 "MMCHS_PVSDR104DDR50,Preset Value for SDR104 and DDR50 speed modes" hexmask.long.word 0x0 0.--9. 1. " SDR104SDCLK_SEL ,SDCLK Frequency Select Value - SDR104 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " SDR104CLKGEN_SEL ,Clock Generator Select Value - SDR104 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " SDR104DS_SEL ,Driver Strength Select Value - SDR104 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " DDR50SDCLK_SEL ,SDCLK Frequency Select Value - DDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " DDR50CLKGEN_SEL ,Clock Generator Select Value - DDR50 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " DDR50DS_SEL ,Driver Strength Select Value - DDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x2FC++0x3 line.long 0x0 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. [31:16] = Host controller version [15:0] = Slot Interrupt Status" bitfld.long 0x0 0. " SIS ,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_HCTL[SRA]), the interrupt signal shall be de-asserted and this status shall read 0." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " SREV ,Specification Version Number This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version." hexmask.long.byte 0x0 24.--31. 1. " VREV ,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" width 0x0B tree.end tree "MMC4" base ad:0x480D1000 width 21. group.byte 0x0++0x3 line.long 0x0 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration." bitfld.long 0x0 0. " MADMA_EN ,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA." "0,1" bitfld.long 0x0 1. " MERGE_MEM ,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing." "0,1" textline " " bitfld.long 0x0 2.--5. " MEM_SIZE ,Memory size for FIFO buffer:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " RETMODE ,Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "MMCHS_HL_SYSCONFIG,Clock Management Configuration Register" bitfld.long 0x0 0. " SOFTRESET ,Software reset. (Optional)" "0,1" bitfld.long 0x0 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS." "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" bitfld.long 0x0 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state." "0,1,2,3" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface." bitfld.long 0x0 0. " AUTOIDLE ,Internal Clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wakeup feature control" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Power management" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,This bit is initialized to zero, and writes to it are ignored. Reads return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock" "0,1,2,3" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12.--13. " STANDBYMODE ,Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a '0'." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x114++0x3 line.long 0x0 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "MMCHS_CSRE,Card Status Response Error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit [i] is set to 1, if the corresponding bit at the same position in the response MMCHS_RSP0[i] is set to 1, the host controller indicates a card error ([CERR]) interrupt status to avoid the host driver reading the response register (MMCHS_RSP0). Note: No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register (MMCHS_RESP76) for possible card errors." hexmask.long 0x0 0.--31. 1. " CSRE ,Card status response error" group.byte 0x128++0x3 line.long 0x0 "MMCHS_SYSTEST,System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into register will not start a transfer. The buffer behaves as a stack accessible only by the local host (push and pop operations). In this mode, the Transfer Block Size ([BLEN]) and the Blocks count for current transfer ([NBLK]) are needed to generate a Buffer write ready interrupt ([BWR]) or a Buffer read ready interrupt ([BRR]) and DMA requests if enabled." bitfld.long 0x0 0. " MCKD ,MMC clock output signal data value" "0,1" bitfld.long 0x0 1. " CDIR ,Control of the CMD pin direction." "0,1" textline " " bitfld.long 0x0 2. " CDAT ,CMD input/output signal data value" "0,1" bitfld.long 0x0 3. " DDIR ,Control of the DAT[7:0] pins direction." "0,1" textline " " bitfld.long 0x0 4. " D0D ,DAT0 input/output signal data value" "0,1" bitfld.long 0x0 5. " D1D ,DAT1 input/output signal data value" "0,1" textline " " bitfld.long 0x0 6. " D2D ,DAT2 input/output signal data value" "0,1" bitfld.long 0x0 7. " D3D ,DAT3 input/output signal data value" "0,1" textline " " bitfld.long 0x0 8. " D4D ,DAT4 input/output signal data value" "0,1" bitfld.long 0x0 9. " D5D ,DAT5 input/output signal data value" "0,1" textline " " bitfld.long 0x0 10. " D6D ,DAT6 input/output signal data value" "0,1" bitfld.long 0x0 11. " D7D ,DAT7 input/output signal data value" "0,1" textline " " bitfld.long 0x0 12. " SSB ,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT)." "0,1" bitfld.long 0x0 13. " WAKD ,Wake request output signal data value" "0,1" textline " " bitfld.long 0x0 14. " SDWP ,Write protect input signal (mmci_sdwp) data value" "0,1" bitfld.long 0x0 15. " SDCD ,Card detect input signal (mmci_sdcd) data value" "0,1" textline " " bitfld.long 0x0 16. " OBI ,Out-Of-Band Interrupt (OBI) data value" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x12C++0x3 line.long 0x0 "MMCHS_CON,Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and also to configure : - specific data and command transfers for MMC cards only. - the parameters related to the card detect and write protect input signals." bitfld.long 0x0 0. " OD ,Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode when the card is either in idle, ready or ident state. It is also necessary to set this bit to 1, for a broadcast host response (see Broadcast host response register MMCHS_CON[HR])" "0,1" bitfld.long 0x0 1. " INIT ,Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock cycles. The initialisation sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider (MMCHS_SYSCTL[CLKD]) should be set to ensure that 80 clock periods are greater than 1ms. (see section 9.3, 'Power-Up', in the MMC card specification, or section 6.4 in the SD card specification). Note: in this mode, there is no command sent to the card and no response is expected" "0,1" textline " " bitfld.long 0x0 2. " HR ,Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section 4.3, 'Interrupt Mode', in the MMC specification). In order to have the host response to be generated in open drain mode, the register MMCHS_CON[OD] must be set to 1. When MMCHS_CON[CEATA] is set to 1 and MMCHS_ARG set to 0x00000000 when writing 0x00000000 into MMCHS_CMD register, the host controller performs a 'command completion signal disable' token i.e. CMD line held to '0' during 47 cycles followed by a 1." "0,1" bitfld.long 0x0 3. " STR ,Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a class 3 command (CMD20: WRITE_DAT_UNTIL_STOP)." "0,1" textline " " bitfld.long 0x0 4. " MODE ,Mode select All cards This bit select between Functional mode and SYSTEST mode." "0,1" bitfld.long 0x0 5. " DW8 ,8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliancy with MMC standard specification 4.x (see section 3.6)." "0,1" textline " " bitfld.long 0x0 6. " MIT ,MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detection to be disabled for the command response." "0,1" bitfld.long 0x0 7. " CDP ,Card detect polarity All cards This bit selects the active level of the card detect input signal (mmci_sdcd). The usage of the card detect input signal (mmci_sdcd) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1" textline " " bitfld.long 0x0 8. " WPP ,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (mmci_sdwp). The usage of the write protect input signal (mmci_sdwp) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1" bitfld.long 0x0 9.--10. " DVAL ,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (mmci_sdcd). The usage of the card detect input signal (mmci_sdcd) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1,2,3" textline " " bitfld.long 0x0 11. " CTPL ,Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards: When this bit is set to 1, the host controller automatically disables all the input buffers except the buffer of DAT[1] outside of a transaction in order to detect asynchronous card interrupt on DAT[1] line and minimize the leakage current of the buffers." "0,1" bitfld.long 0x0 12. " CEATA ,CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is used to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features." "0,1" textline " " bitfld.long 0x0 13. " OBIP ,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration." "0,1" bitfld.long 0x0 14. " OBIE ,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration." "0,1" textline " " bitfld.long 0x0 15. " PADEN ,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also combine outside the module with the dedicated power control MMCHS_CON[CTPL] bit." "0,1" bitfld.long 0x0 16. " CLKEXTFREE ,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only if MMCHS_SYSCTL[CEN] is set." "0,1" textline " " bitfld.long 0x0 17. " BOOT_ACK ,Boot acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated." "0,1" bitfld.long 0x0 18. " BOOT_CF0 ,Boot status supported: This register is set when the CMD line need to be forced to '0' for a boot sequence. CMD line is driven to '0' after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer in case of a pending transaction." "0,1" textline " " bitfld.long 0x0 19. " DDR ,Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Data bytes and CRC, Start, end bits and CRC status are kept full cycle. This bit field is only meaningful and active for even clock divider ratio of MMCHS_SYSCTL[CLKD], it is insensitive to MMCHS_HCTL[HSPE] setting." "0,1" bitfld.long 0x0 20. " DMA_MNS ,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available if generic parameter MADMA_EN is asserted to '1'." "0,1" textline " " bitfld.long 0x0 21. " SDMA_LNE ,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data written into MMCHS_DATA." "0,1" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "MMCHS_PWCNT,Power Counter Register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage." hexmask.long.word 0x0 0.--15. 1. " PWRCNT ,Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x200++0x3 line.long 0x0 "MMCHS_SDMASA,SDMA System Address / Argument 2 Register" hexmask.long 0x0 0.--31. 1. " SDMA_ARG2 ,SDMA System Address / Argument 2 This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23. (1) SDMA System Address This register contains the system memory address for a SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (003h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume command or by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register. ADMA does not use this register. (2) Argument 2 This register is used with the Auto CMD23 to set a 32-bit block count value to the argument of the CMD23 while executing Auto CMD23. If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used. If Auto CMD23 is used without AMDA, the available block count value is limited by the Block Count register. 65535 blocks is the maximum value in this case." group.byte 0x204++0x3 line.long 0x0 "MMCHS_BLK,Transfer Length Configuration Register [BLEN] is the block size register. [NBLK] is the block count register. This register shall be used for any card." hexmask.long.word 0x0 0.--11. 1. " BLEN ,Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issued to stop the transfer, a read of the BLEN field after transfer completion (MMCHS_STAT[TC] set to 1) will not return the true byte number of data length while the stop occurs but the value written in this register before transfer is launched." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " NBLK ,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[BCE]) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note: The host controller decrements the block count after each block transfer and stops when the count reaches zero. This register can be accessed only if no transaction is executing (i.e, after a transaction has stopped). Read operations during transfers may return an invalid value and write operation will be ignored. In suspend context, the number of blocks yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, The local host shall restore the previously saved block count." group.byte 0x208++0x3 line.long 0x0 "MMCHS_ARG,Command Argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary." hexmask.long 0x0 0.--31. 1. " ARG ,Command argument bits [31:0]" group.byte 0x20C++0x3 line.long 0x0 "MMCHS_CMD,Command and Transfer Mode Register [31:16] = the command register [15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into [15:0] registers during data transfer has no effect. This register shall be used for any card. Note: In SYSTEST mode, a write into register will not start a transfer." bitfld.long 0x0 0. " DE ,DMA EnableThis bit is used to enable DMA mode for host data access. ." "0,1" bitfld.long 0x0 1. " BCE ,Block Count EnableMultiple block transfers only. . This bit is used to enable the block count register ([NBLK]). . When Block Count is disabled ([BCE] is set to 0) in Multiple block transfers ([MSBS] is set to 1), the module can perform infinite transfer. ." "0,1" textline " " bitfld.long 0x0 2.--3. " ACEN ,Auto CMD Enable - SD card only.This field determines use of auto command functions. . There are two methods to stop Multiple-block read and write operation .  Auto CMD23 Supported (Host Controller Version is 3.00 or later) .  A memory card that supports CMD23 (SCR[33]=1) .  If DMA is used, it shall be ADMA. . Only when CMD18 or CMD25 is issued . (Note: the Host Controller does not check command index.) . Auto CMD23 can be used with or without ADMA. By writing the Command register, the Host Controller issues a CMD23 first and then issues a command specified by the Command Index in Command register. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the Auto CMD Error Status register (). 32-bit block count value for CMD23 is set to SDMA System Address / Argument 2 register (). ." "0,1,2,3" bitfld.long 0x0 4. " DDIR ,Data transfer Direction SelectThis bit defines either data transfer will be a read or a write. ." "0,1" textline " " bitfld.long 0x0 5. " MSBS ,Multi/Single block selectThis bit must be set to 1 for data transfer in case of multi block command. . For any others command this bit shall be set to 0. . If this bit is 0, it is not necessary to set the register[NBLK]. enum=sgleblk . When Block Count is disabled ([BCE] is set to 0) in Multiple block transfers ([MSBS] is set to 1), the module can perform infinite transfer. enum=multiblk ." "0,1" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " RSP_TYPE ,Response typeThis bits defines the response type of the command ." "0,1,2,3" bitfld.long 0x0 18. " RESERVED ," "0,1" textline " " bitfld.long 0x0 19. " CCCE ,Command CRC check enableThis bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. . If an error is detected, it is reported as a command CRC error ([CCRC] set to 1). . Note: The register CCCE cannot be configured for an Auto CMD12, and then CRC check is automatically checked when this command is issued. ." "0,1" bitfld.long 0x0 20. " CICE ,Command Index check enableThis bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. . If the index is not the same in the response as in the command, it is reported as a command index error ([CIE] set to1). . Note:The register CICE cannot be configured for an Auto CMD12, then index check is automatically checked when this command is issued. ." "0,1" textline " " bitfld.long 0x0 21. " DP ,Data present selectThis register indicates that data is present and DAT line shall be used. . It must be set to 0 in the following conditions: . - command using only CMD line . - command with no data transfer but using busy signal on DAT[0] . - Resume command ." "0,1" bitfld.long 0x0 22.--23. " CMD_TYPE ,Command typeThis register specifies three types of special command: Suspend, Resume and Abort. . These bits shall be set to 00b for all other commands. ." "0,1,2,3" textline " " bitfld.long 0x0 24.--29. " INDX ,Command indexBinary encoded value from 0 to 63 specifying the command number send to card ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x210++0x3 line.long 0x0 "MMCHS_RSP10,Command Response[31:0] Register (bits [31:0] of the internal RSP register) This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6/R7" hexmask.long.word 0x0 0.--15. 1. " RSP0 ,Command Response [15:0]" hexmask.long.word 0x0 16.--31. 1. " RSP1 ,Command Response [31:16]" group.byte 0x214++0x3 line.long 0x0 "MMCHS_RSP32,Command Response[63:32] Register (bits [63:32] of the internal RSP register) This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x0 0.--15. 1. " RSP2 ,Command Response [47:32]" hexmask.long.word 0x0 16.--31. 1. " RSP3 ,Command Response [63:48]" group.byte 0x218++0x3 line.long 0x0 "MMCHS_RSP54,Command Response[95:64] Register (bits [95:64] of the internal RSP register) This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x0 0.--15. 1. " RSP4 ,Command Response [79:64]" hexmask.long.word 0x0 16.--31. 1. " RSP5 ,Command Response [95:80]" group.byte 0x21C++0x3 line.long 0x0 "MMCHS_RSP76,Command Response[127:96] Register (bits [127:96] of the internal RSP register) This 32-bit register holds bits positions [127:96] of command response type R1(Auto CMD23)/R1b(Auto CMD12)/R2" hexmask.long.word 0x0 0.--15. 1. " RSP6 ,Command Response [111:96]" hexmask.long.word 0x0 16.--31. 1. " RSP7 ,Command Response [127:112]" group.byte 0x220++0x3 line.long 0x0 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bits x256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register or on the most significant byte of the last word of block transfer. Example 1: Byte or 16-bit access Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad" hexmask.long 0x0 0.--31. 1. " DATA ,Data Register [31:0] In functional mode (MMCHS_CON[MODE] set to the default value 0) , A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCHS_PSTATE[BRE]), otherwise a bad access (MMCHS_STAT[BADA]) is signaled. A write access to this register is allowed only when the buffer write enable status is set to 1(MMCHS_STATE[BWE]), otherwise a bad access (MMCHS_STAT[BADA]) is signaled and the data is not written." group.byte 0x224++0x3 line.long 0x0 "MMCHS_PSTATE,Present State Register The Host can get status of the Host Controller from this 32-bit read only register." bitfld.long 0x0 0. " CMDI ,Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0 in either the following cases: - After the end bit of the command response, excepted if there is a command conflict error (MMCHS_STAT[CCRC] or MMCHS_STAT[CEB] set to 1) or a Auto CMD12 is not executed (MMCHS_AC12[ACNE]). - After the end bit of the command without response (MMCHS_CMD[RSP_TYPE] set to '00') In case of a command data error is detected (MMCHS_STAT[CTO] set to 1), this register is not automatically cleared." "0,1" bitfld.long 0x0 1. " DATI ,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[DLA]) or Read transfer is active (MMCHS_PSTATE[RTA]) or when a command with busy is issued. This bit prevents the local host to issue a command. A change of this bit from 1 to 0 generates a transfer complete interrupt (MMCHS_STAT[TC])." "0,1" textline " " bitfld.long 0x0 2. " DLA ,DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue request MMCHS_HCTL[CR]. This bit is set to 0 when the host controller received the end bit of the last data block or at the beginning of the read wait mode. In the case of write transactions (host to card): This bit is set to 1 after the end bit of write command or by activating continue request MMCHS_HCTL[CR]. This bit is set to 0 on the end of busy event for the last block; host controller must wait 8 clock cycles with line not busy to really consider not 'busy state' or after the busy block as a result of a stop at gap request." "0,1" bitfld.long 0x0 3. " RTR ,Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is cleared when a command is issued with setting MMCHS_AC12[22] ET. This bit isn't set to 1 if MMCHS_AC12[23] SCLK_SEL is set to 0 (using fixed sampling clock). Refer to MMCHS_CAPA2[15:14] RTM for more detail." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " WTA ,Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[CR]) following a stop at block gap request. This bit is set to 0 when CRC status has been received after last block or after a stop at block gap request." "0,1" textline " " bitfld.long 0x0 9. " RTA ,Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[CR]) following a stop at block gap request. This bit is set to 0 when all data have been read by the local host after last block or after a stop at block gap request." "0,1" bitfld.long 0x0 10. " BWE ,Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data." "0,1" textline " " bitfld.long 0x0 11. " BRE ,Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[BLEN] has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from the buffer. It is set to 1 when a block data is ready in the buffer and generates the Buffer read ready status of interrupt (MMCHS_STAT[BRR])." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " CINS ,Card inserted This bit is the debounced value of the card detect input pin (mmci_sdcd). An inactive to active transition of the card detect input pin (mmci_sdcd) will generate a card insertion interrupt (MMCHS_STAT[CINS]). A active to inactive transition of the card detect input pin (mmci_sdcd) will generate a card removal interrupt (MMCHS_STAT[REM]). This bit is not affected by a software reset." "0,1" bitfld.long 0x0 17. " CSS ,Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[CDPL]). Debouncing is performed on the card detect input pin (mmci_sdcd) to detect card stability. This bit is not affected by a software reset." "0,1" textline " " bitfld.long 0x0 18. " CDPL ,Card detect pin level This bit reflects the inverse value of the card detect input pin (mmci_sdcd), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTAE[CSS]) is set to 1. Use of this bit is limited to testing since it must be debounced y software. The value of this register after reset depends on the card detect input pin (mmci_sdcd) level at that time." "0,1" bitfld.long 0x0 19. " WP ,Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (mmci_sdwp) level. The value of this register after reset depends on the protect input pin (mmci_sdwp) level at that time." "0,1" textline " " bitfld.long 0x0 20.--23. " DLEV ,DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. The value of these registers after reset depends on the DAT lines level at that time." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " CLEV ,CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time." "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x228++0x3 line.long 0x0 "MMCHS_HCTL,Host Control Register This register defines the host controls to set power, wakeup and transfer parameters. [31:24] = Wakeup control [23:16] = Block gap control [15:8] = Power control [7:0] = Host control" bitfld.long 0x0 0. " LED ,Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored." "0,1" bitfld.long 0x0 1. " DTW ,Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliance with MMC standard specification 4.x (see section 3.6). This register has no effect when the MMC 8-bit mode is selected (register MMCHS_CON[DW8] set to1 ), For SD/SDIO cards, this bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument. Prior to this command, the SD card configuration register (SCR) must be verified for the supported bus width by the SD card." "0,1" textline " " bitfld.long 0x0 2. " HSPE ,Before setting this bit, the Host Driver shall check theMMCHS_CAPA[21] HSS. This bit shall not be set when dual data rate mode is activated in MMCHS_CON[DDR]." "0,1" bitfld.long 0x0 3.--4. " DMAS ,DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register MMCHS_CAPA . Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This register is only meaningful when MADMA_EN is set to 1. When MADMA_EN is set to 0 the bit field is read only and returned value is 0." "0,1,2,3" textline " " bitfld.long 0x0 5. " RESERVED ," "0,1" bitfld.long 0x0 6. " CDTL ,Card Detect Test Level: This bit is enabled while MMCHS_HCTL[7] CDSS is set to 1 and it indicates whether the card is inserted or not." "0,1" textline " " bitfld.long 0x0 7. " CDSS ,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in order to mask unexpected interrupts caused by the glitch. The Interrupt Status/Signal Enable should be disabled during over the period of debouncing." "0,1" bitfld.long 0x0 8. " SDBP ,SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[SDVS]). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in the command register (MMCHS_CMD) will not start the transfer. A write to this bit has no effect if the selected SD bus voltage MMCHS_HCTL[SDVS] is not supported according to capability register (MMCHS_CAPA[VS*])." "0,1" textline " " bitfld.long 0x0 9.--11. " SDVS ,SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[VS18,VS30,VS33]) before starting a transfer." "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " SBGR ,Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[CR]) or during a suspend/resume sequence. In case of read transfer, the card must support read wait control. In case of write transfer, the host driver shall set this bit after all block data written. Until the transfer completion (MMCHS_STAT[TC] set to 1), the host driver shall leave this bit set to 1. If this bit is set, the local host shall not write to the data register (MMCHS_DATA)." "0,1" bitfld.long 0x0 17. " CR ,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[SBGR]). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when transfer has restarted i.e DAT line is active (MMCHS_PSTATE[DLA]) or transferring data (MMCHS_PSTATE[WTA]). The Stop at block gap request must be disabled (MMCHS_HCTL[SBGR]=0) before setting this bit." "0,1" textline " " bitfld.long 0x0 18. " RWC ,Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[SBGR]) generates a read wait period after the current end of block. Be careful, if read wait is not supported it may cause a conflict on DAT line." "0,1" bitfld.long 0x0 19. " IBG ,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be set to 0." "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " IWE ,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" textline " " bitfld.long 0x0 25. " INS ,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" bitfld.long 0x0 26. " REM ,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" textline " " bitfld.long 0x0 27. " OBWE ,Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP]). The write to this register is ignored when MMCHS_CON[OBIE] is not set." "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "MMCHS_SYSCTL,SD System Control Register This register defines the system controls to set software resets, clock frequency management and data timeout. [31:24] = Software resets [23:16] = Timeout control [15:0] = Clock control" bitfld.long 0x0 0. " ICE ,Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface clock (used for reads and writes to the module register map) are not affected by this register." "0,1" bitfld.long 0x0 1. " ICS ,Internal clock stable (status) This bit indicates either the internal clock is stable or not." "0,1" textline " " bitfld.long 0x0 2. " CEN ,Clock enable This bit controls if the clock is provided to the card or not." "0,1" bitfld.long 0x0 3.--4. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 5. " CGS ,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit. This bit is used to select the clock generator mode in MMCHS_SYSCTL[15:6] CLKD. If the Programmable Clock Mode is supported (non-zero value is set to MMCHS_CAPA2[23:16] CM), this bit attribute is RW, and if not supported, this bit attribute is RO and zero is read. This bit depends on the setting of MMCHS_AC12[31] PV_ENABLE. If PV_ENABLE = 0, this bit is set by Host Driver. If PV_ENABLE = 1, this bit is automatically set to a value specified in one of Preset Value registers, see, ." "0,1" hexmask.long.word 0x0 6.--15. 1. " CLKD ,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO)." textline " " bitfld.long 0x0 16.--19. " DTO ,Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bitfield based on - the maximum read access time (NAC) (Refer to the SD Specification Part1 Physical Layer), - the data read access time values (TAAC and NSAC) in the card specific data register (CSD) of the card, - the timeout clock base frequency (MMCHS_CAPA[TCF]). If the card does not respond within the specified number of cycles, a data timeout error occurs (MMCHS_STA[DTO]). The MMCHS_SYSCTL[DTO] register is also used to check busy duration, to generate busy timeout for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SRA ,Software reset for all This bit is set to 1 for reset , and released to 0 when completed. This reset affects the entire host controller except for the capabilities registers (MMCHS_CAPA and MMCHS_CUR_CAPA)." "0,1" bitfld.long 0x0 25. " SRC ,Software reset for CMD line For more information about SRC bit manipulation, see CMD Line Reset Procedure. This bit is set to 1 for reset and released to 0 when completed. CMD finite state machine in both clock domain are also reset. Here below the registers cleared by MMCHS_SYSCTL[SRC]: - MMCHS_PSTATE: CMDI - MMCHS_STAT: CC Interconnect and MMC command status management is reinitialized." "0,1" textline " " bitfld.long 0x0 26. " SRD ,Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see DATA Lines Reset Procedure. DAT finite state machine in both clock domain are also reset. Here below are the registers cleared by MMCHS_SYSCTL[SRD]: - MMCHS_DATA - MMCHS_PSTATE: BRE, BWE, RTA, WTA, DLA and DATI - MMCHS_HCTL: SBGR and CR - MMCHS_STAT: BRR, BWR, BGE and TC Interconnect and MMC buffer data management is reinitialized." "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x230++0x3 line.long 0x0 "MMCHS_STAT,Interrupt Status Register The interrupt status regroups all the status of the module internal events that can generate an interrupt. [31:16] = Error Interrupt Status [15:0] = Normal Interrupt Status" bitfld.long 0x0 0. " CC ,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[CMDI]) If the command is a type for which no response is expected, then the command complete interrupt is generated at the end of the command. A command timeout error (MMCHS_STAT[CTO]) has higher priority than command complete (MMCHS_STAT[CC]). If a response is expected but none is received, then a command timeout error is detected and signaled instead of the command complete interrupt." "0,1" bitfld.long 0x0 1. " TC ,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[SBGR]). In Read mode: This bit is automatically set on completion of a read transfer (MMCHS_PSTATE[RTA]). In write mode: This bit is set automatically on completion of the DAT line use (MMCHS_PSTATE[DLA])." "0,1" textline " " bitfld.long 0x0 2. " BGE ,Block gap event When a stop at block gap is requested (MMCHS_HCTL[SBGR]), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap is requested on the last block. In read mode, a 1-to-0 transition of the DAT Line active status (MMCHS_PSTATE[DLA]) between data blocks generates a Block gap event interrupt." "0,1" bitfld.long 0x0 3. " DMA ,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion." "0,1" textline " " bitfld.long 0x0 4. " BWR ,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[BLEN]. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer. Note: If the DMA transmit mode is enabled, this bit is never set; instead, a DMA transmit request to the main DMA controller of the system is generated." "0,1" bitfld.long 0x0 5. " BRR ,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[BLEN] is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by reading it. Note: If the DMA receive-mode is enabled, this bit is never set; instead a DMA receive request to the main DMA controller of the system is generated." "0,1" textline " " bitfld.long 0x0 6. " CINS ,Card insertion This bit is set automatically when MMCHS_PSTATE[CINS] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[CINS])." "0,1" bitfld.long 0x0 7. " CREM ,Card removal This bit is set automatically when MMCHS_PSTATE[CINS] changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[CINS])." "0,1" textline " " bitfld.long 0x0 8. " CIRQ ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drives CMD line to zero during one cycle after data transmission end.All modes above are fully exclusive. The controller interrupt must be clear by setting MMCHS_IE[CIRQ] to 0, then the host driver must start the interrupt service with card (clearing card interrupt status) to remove card interrupt source. Otherwise the Controller interrupt will be reasserted as soon as MMCHS_IE[CIRQ] is set to 1. Writes to this bit are ignored." "0,1" bitfld.long 0x0 9. " OBI ,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[OBIE] is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[OBIP]. This interrupt is only useful for MMC card. The Out-of-Band interrupt signal is a system specific feature for future use, this signal is not required for existing specification implementation." "0,1" textline " " bitfld.long 0x0 10. " BSR ,Boot status received interrupt This bit is set automatically when MMCHS_CON[BOOT] is set 0x1 or 0x2 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " ERRI ,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[31:16]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored." "0,1" bitfld.long 0x0 16. " CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles." "0,1" textline " " bitfld.long 0x0 17. " CCRC ,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[CCCE] register." "0,1" bitfld.long 0x0 18. " CEB ,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response." "0,1" textline " " bitfld.long 0x0 19. " CIE ,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[CICE] register." "0,1" bitfld.long 0x0 20. " DTO ,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout" "0,1" textline " " bitfld.long 0x0 21. " DCRC ,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command." "0,1" bitfld.long 0x0 22. " DEB ,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode." "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE ,Auto CMD error Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register (MMCHS_AC12) has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to the previous command error." "0,1" textline " " bitfld.long 0x0 25. " ADMAE ,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller generates this interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state. The Host Driver may find that Valid bit is not set at the error descriptor." "0,1" bitfld.long 0x0 26. " TE ,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Select). By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. To reset tuning circuit, Sampling Clock shall be set to 0 before executing tuning procedure. The Tuning Error is higher priority than the other error interrupts generated during data transfer. By detecting Tuning Error, the Host Driver should discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from tuning circuit error. The bit is set if the lock is lost (but not during the tuning process) or if the lock counter expires without the lock being asserted. If the latter happens, the SW can decide to ignore the interrupt and wait some more for the lock to be set." "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR ,Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error MMCHS_CSRE in set. There is no card error detection for autoCMD12 command. The host driver shall read MMCHS_RSP76 register to detect error bits in the command response." "0,1" textline " " bitfld.long 0x0 29. " BADA ,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[BRE] =0) -This bit is set during a write access to the data register (MMCHS_DATA) while buffer writes are not allowed (MMCHS_STATE[BWE] =0)" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x234++0x3 line.long 0x0 "MMCHS_IE,Interrupt Status Enable Register This register allows to enable/disable the module to set status bits, on an event-by-event basis. [31:16] = Error Interrupt Status Enable [15:0] = Normal Interrupt Status Enable" bitfld.long 0x0 0. " CC_ENABLE ,Command Complete Status Enable" "0,1" bitfld.long 0x0 1. " TC_ENABLE ,Transfer Complete Status Enable" "0,1" textline " " bitfld.long 0x0 2. " BGE_ENABLE ,Block Gap Event Status Enable" "0,1" bitfld.long 0x0 3. " DMA_ENABLE ,DMA Status Enable" "0,1" textline " " bitfld.long 0x0 4. " BWR_ENABLE ,Buffer Write Ready Status Enable" "0,1" bitfld.long 0x0 5. " BRR_ENABLE ,Buffer Read Ready Status Enable" "0,1" textline " " bitfld.long 0x0 6. " CINS_ENABLE ,Card Insertion Status Enable" "0,1" bitfld.long 0x0 7. " CREM_ENABLE ,Card Removal Status Enable" "0,1" textline " " bitfld.long 0x0 8. " CIRQ_ENABLE ,Card Status Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1." "0,1" bitfld.long 0x0 9. " OBI_ENABLE ,Out-of-Band Status Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored." "0,1" textline " " bitfld.long 0x0 10. " BSR_ENABLE ,Boot Status Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x0 16. " CTO_ENABLE ,Command Timeout Error Status Enable" "0,1" textline " " bitfld.long 0x0 17. " CCRC_ENABLE ,Command CRC Error Status Enable" "0,1" bitfld.long 0x0 18. " CEB_ENABLE ,Command End Bit Error Status Enable" "0,1" textline " " bitfld.long 0x0 19. " CIE_ENABLE ,Command Index Error Status Enable" "0,1" bitfld.long 0x0 20. " DTO_ENABLE ,Data Timeout Error Status Enable" "0,1" textline " " bitfld.long 0x0 21. " DCRC_ENABLE ,Data CRC Error Status Enable" "0,1" bitfld.long 0x0 22. " DEB_ENABLE ,Data End Bit Error Status Enable" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE_ENABLE ,Auto CMD Error Status Enable" "0,1" textline " " bitfld.long 0x0 25. " ADMAE_ENABLE ,ADMA Error Status Enable" "0,1" bitfld.long 0x0 26. " TE_ENABLE ,Tuning Error Status Enable" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR_ENABLE ,Card Error Status Enable" "0,1" textline " " bitfld.long 0x0 29. " BADA_ENABLE ,Bad access to data space Status Enable" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x238++0x3 line.long 0x0 "MMCHS_ISE,Interrupt Signal Enable Register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. [31:16] = Error Interrupt Signal Enable [15:0] = Normal Interrupt Signal Enable" bitfld.long 0x0 0. " CC_SIGEN ,Command Complete Status Enable" "0,1" bitfld.long 0x0 1. " TC_SIGEN ,Transfer Completed Status Enable" "0,1" textline " " bitfld.long 0x0 2. " BGE_SIGEN ,Black Gap Event Signal Enable" "0,1" bitfld.long 0x0 3. " DMA_SIGEN ,DMA Interrupt Signal Enable" "0,1" textline " " bitfld.long 0x0 4. " BWR_SIGEN ,Buffer Write Ready Signal Enable" "0,1" bitfld.long 0x0 5. " BRR_SIGEN ,Buffer Read Ready Signal Enable" "0,1" textline " " bitfld.long 0x0 6. " CINS_SIGEN ,Card Insertion Signal Enable" "0,1" bitfld.long 0x0 7. " CREM_SIGEN ,Card Removal Signal Enable" "0,1" textline " " bitfld.long 0x0 8. " CIRQ_SIGEN ,Card Interrupt Signal Enable" "0,1" bitfld.long 0x0 9. " OBI_SIGEN ,Out-Of-Band Interrupt Signal Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored." "0,1" textline " " bitfld.long 0x0 10. " BSR_SIGEN ,Boot Status Signal Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x0 16. " CTO_SIGEN ,Command timeout Error Signal Enable" "0,1" textline " " bitfld.long 0x0 17. " CCRC_SIGEN ,Command CRC Error Signal Enable" "0,1" bitfld.long 0x0 18. " CEB_SIGEN ,Command End Bit Error Signal Enable" "0,1" textline " " bitfld.long 0x0 19. " CIE_SIGEN ,Command Index Error Signal Enable" "0,1" bitfld.long 0x0 20. " DTO_SIGEN ,Data Timeout Error Signal Enable" "0,1" textline " " bitfld.long 0x0 21. " DCRC_SIGEN ,Data CRC Error Signal Enable" "0,1" bitfld.long 0x0 22. " DEB_SIGEN ,Data End Bit Error Signal Enable" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE_SIGEN ,Auto CMD Error Signal Enable" "0,1" textline " " bitfld.long 0x0 25. " ADMAE_SIGEN ,ADMA Error Signal Enable" "0,1" bitfld.long 0x0 26. " TE_SIGEN ,Tuning Error Signal Enable" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR_SIGEN ,Card Error Interrupt Signal Enable" "0,1" textline " " bitfld.long 0x0 29. " BADA_SIGEN ,Bad access to data space Signal Enable" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x23C++0x3 line.long 0x0 "MMCHS_AC12,Host Control 2 Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12 / CMD23 errors occur by this register. Auto CMD23 errors are indicated only in bits[4:1]. Bits[7:0] are valid only when the [3:2] ACEN bitfield is configured to enable Auto CMD and the Auto CMD Error bit ([24]ACE) is set." bitfld.long 0x0 0. " ACNE ,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the Host Controller cannot issue Auto CMD12 to stop memory multiple block data transfer due to some error. If this bit is set to 1, other error status bits (D04-D01) are meaningless. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" bitfld.long 0x0 1. " ACTO ,Auto CMD Timeout Error - For Auto CMD12 and Auto CMD23 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command. If this bit is set to1, the other error status bits (D04-D02) are meaningless." "0,1" textline " " bitfld.long 0x0 2. " ACCE ,Auto CMD CRC Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting a CRC error in the command response." "0,1" bitfld.long 0x0 3. " ACEB ,Auto CMD End Bit Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting that the end bit of command response is 0." "0,1" textline " " bitfld.long 0x0 4. " ACIE ,Auto CMD Index Error - For Auto CMD12 and Auto CMD23 This bit is set if the Command Index error occurs in response to a command." "0,1" bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 7. " CNI ,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " UHSMS ,UHS Mode Select This field is used to select one of UHS-I modes or eMMC HS200 mode and is effective when 1.8V Signaling Enable is set to 1. If MMCHS_AC12[31] PV_ENABLE is set to 1, Host Controller sets MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL according to Preset Value registers, see, . In this case, one of preset value registers is selected by this field. Host Driver needs to reset MMCHS_SYSCTL[2] CEN before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets MMCHS_SYSCTL[2] CEN again. When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more detail." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " V1V8_SIGEN ,1.8V Signaling Enable This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails. Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V. 3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling (One of support bits is set to 1: SDR50, SDR104 or DDR50 in MMCHS_CAPA2 register) and the card or device supports UHS-I (S18A=1. Refer to Bus Signal Voltage Switch Sequence in the Physical Layer Specification Version 3.0x)." "0,1" textline " " bitfld.long 0x0 20.--21. " DS_SEL ,Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set depending on Driver Type A, C and D support bits (DTA, DTC and DTD respectively) in the MMCHS_CAPA2 register. This bit depends on setting of Preset Value Enable. If Preset Value Enable = 0, this field is set by Host Driver. If Preset Value Enable = 1, this field is automatically set by a value specified in the one of Preset Value registers, see, ." "0,1,2,3" bitfld.long 0x0 22. " ET ,Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to MMCHS_AC12[23] SCLK_SEL. Tuning procedure is aborted by writing 0. This is Read-Write with automatic clear register" "0,1" textline " " bitfld.long 0x0 23. " SCLK_SEL ,Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is set by tuning procedure and valid after the completion of tuning (when MMCHS_AC12[22] ET is cleared). Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Writing 1 to this bit is meaningless and ignored. A tuning circuit is reset by writing to 0. This bit can be cleared with setting MMCHS_AC12[22] ET. Once the tuning circuit is reset, it will take time to complete tuning sequence. Therefore, Host Driver should keep this bit to 1 to perform re-tuning sequence to compete re-tuning sequence in a short time. Change of this bit is not allowed while the Host Controller is receiving response or a read data block." "0,1" bitfld.long 0x0 24.--29. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " AI_ENABLE ,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and MMCHS_CAPA[29] AIS is set to 1. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver the Card Interrupt to the host when it is asserted by the Card." "0,1" bitfld.long 0x0 31. " PV_ENABLE ,Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When Preset Value Enable is set, automatic SDCLK frequency generation and driver strength selection is performed without considering system specific conditions. This bit enables the functions defined in the Preset Value registers, see, . If this bit is set to 0, MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL are set by Host Driver. If this bit is set to 1, MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL are set by Host Controller as specified in the Preset Value registers, see, ." "0,1" group.byte 0x240++0x3 line.long 0x0 "MMCHS_CAPA,Capabilities Register This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x0 0.--5. " TCF ,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[DTO])." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " RESERVED ," "0,1" textline " " bitfld.long 0x0 7. " TCU ,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[DTO])." "0,1" hexmask.long.byte 0x0 8.--15. 1. " BCF ,Base Clock Frequency For SD Clock This value indicates the base (maximum) clock frequency for the SD Clock. 8-bit Base Clock Frequency This mode is supported by the Host Controller Version 3.00. Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh : 255MHz .... : ....... 02h : 2MHz 01h : 1MHz 00h : Get information via another method If the real frequency is 16.5MHz, the lager value shall be set 0001 0001b (17MHz) because the Host Driver use this value to calculate the clock divider value (Refer to MMCHS_SYSCTL[15:6] CLKD) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method." textline " " bitfld.long 0x0 16.--17. " MBL ,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 bytes. The host controller supports 512 bytes and 1024 bytes block transfers." "0,1,2,3" bitfld.long 0x0 18. " RESERVED ," "0,1" textline " " bitfld.long 0x0 19. " AD2S ,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2. It depends on setting of generic parameter MADMA_EN" "0,1" bitfld.long 0x0 20. " RESERVED ," "0,1" textline " " bitfld.long 0x0 21. " HSS ,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency." "0,1" bitfld.long 0x0 22. " DS ,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly." "0,1" textline " " bitfld.long 0x0 23. " SRS ,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality." "0,1" bitfld.long 0x0 24. " VS33 ,Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" textline " " bitfld.long 0x0 25. " VS30 ,Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" bitfld.long 0x0 26. " VS18 ,Voltage support 1.8V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " BIT64 ,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus." "0,1" textline " " bitfld.long 0x0 29. " AIS ,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x244++0x3 line.long 0x0 "MMCHS_CAPA2,Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer to Software Reset For All in the Software Reset register for loading from flash memory and completion timing control." bitfld.long 0x0 0. " SDR50 ,SDR50 Support If SDR104 is supported, this bit shall be set to 1. Bit 13 indicates whether SDR50 requires tuning or not." "0,1" bitfld.long 0x0 1. " SDR104 ,SDR104 Support SDR104 requires tuning." "0,1" textline " " bitfld.long 0x0 2. " DDR50 ,DDR50 Support" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " DTA ,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling." "0,1" bitfld.long 0x0 5. " DTC ,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling." "0,1" textline " " bitfld.long 0x0 6. " DTD ,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling." "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--11. " TCRT ,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 0 disables Re-Tuning Timer." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13. " TSDR50 ,Use Tuning for SDR50 If this bit is set to 1, this Host Controller requires tuning to operate SDR50. (Tuning is always required to operate SDR104.)" "0,1" bitfld.long 0x0 14.--15. " RTM ,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length." "0,1,2,3" textline " " hexmask.long.byte 0x0 16.--23. 1. " CM ,Clock Multiplier This field indicates clock multiplier value of programmable clock generator. Refer to MMCHS_SYSCTL [15:0]. Setting 00h means that Host Controller does not support programmable clock generator. 00h : Clock Multiplier is Not Supported 01h : Clock Multiplier M = 2 02h : Clock Multiplier M = 3 .... : ...................... FFh : Clock Multiplier M = 256" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x248++0x3 line.long 0x0 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (). Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" hexmask.long.byte 0x0 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V" hexmask.long.byte 0x0 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V" textline " " hexmask.long.byte 0x0 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "MMCHS_FE,Force Event Register for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register. Rather, it is an address at which the Auto CMD Error Status Register () can be written. Writing 1 : set each bit of the Auto CMD Error Status Register Writing 0 : no effect Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register if the corresponding bit of the Error Interrupt Status Enable Register is set. Writing 1 : set each bit of the Error Interrupt Status Register Writing 0 : no effect Note: By setting this register, the Error Interrupt can be set in the Error Interrupt Status register. In order to generate interrupt signal, both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be set." bitfld.long 0x0 0. " FE_ACNE ,Force Event Auto CMD12 Not Executed" "0,1" bitfld.long 0x0 1. " FE_ACTO ,Force Event Auto CMD Timeout Error" "0,1" textline " " bitfld.long 0x0 2. " FE_ACCE ,Force Event Auto CMD CRC Error" "0,1" bitfld.long 0x0 3. " FE_ACEB ,Force Event Auto CMD End Bit Error" "0,1" textline " " bitfld.long 0x0 4. " FE_ACIE ,Force Event for Auto CMD Index Error - For Auto CMD12 and Auto CMD23" "0,1" bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error" "0,1" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " FE_CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles." "0,1" bitfld.long 0x0 17. " FE_CCRC ,Force Event Command CRC Error." "0,1" textline " " bitfld.long 0x0 18. " FE_CEB ,Force Event Command End Bit Error." "0,1" bitfld.long 0x0 19. " FE_CIE ,Force Event Command Index Error." "0,1" textline " " bitfld.long 0x0 20. " FE_DTO ,Force Event Data Timeout Error." "0,1" bitfld.long 0x0 21. " FE_DCRC ,Force Event Data CRC Error." "0,1" textline " " bitfld.long 0x0 22. " FE_DEB ,Force Event Data End Bit error." "0,1" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24. " FE_ACE ,Force Event for Auto CMD Error - For Auto CMD12 and Auto CMD23" "0,1" bitfld.long 0x0 25. " FE_ADMAE ,Force Event ADMA Error." "0,1" textline " " bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" bitfld.long 0x0 28. " FE_CERR ,Force Event Card error." "0,1" textline " " bitfld.long 0x0 29. " FE_BADA ,Force Event Bad access to data space." "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x254++0x3 line.long 0x0 "MMCHS_ADMAES,ADMA Error Status Register When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the error, the Host Driver requires the ADMA state to identify the error descriptor address as follows: ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address ST_FDS: Current location set in the ADMA System Address register is the error descriptor address ST_CADR: This sate is never set because do not generate ADMA error in this state. ST_TFR: Previous location set in the ADMA System Address register is the error descriptor address In case of write operation, the Host Driver should use ACMD22 to get the number of written block rather than using this information, since unwritten data may exist in the Host Controller. The Host Controller generates the ADMA Error Interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. In this case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host Driver may find that the Valid bit is not set in the error descriptor." bitfld.long 0x0 0.--1. " AES ,ADMA Error StateThis field indicates the state of ADMA when error occurred during ADMA data transfer. This field will never be 0x2 because ADMA never stops in that state.0x0: ST_STOP (STOP_ADMA). Previous SYS_ADR is the error descriptor address0x1: ST_FDS (Fetch Descriptor). Content of current SYS_ADR is the error descriptor address0x2: Not used. Error never set in this state0x3: ST_TFR (Transfer Data). Previous SYS_ADR is the error descriptor address" "0,1,2,3" bitfld.long 0x0 2. " LME ,ADMA Length Mismatch Error: (1) While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. (2) Total data length can not be divided by the block length." "0,1" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x258++0x3 line.long 0x0 "MMCHS_ADMASAL,ADMA System address Low bits" hexmask.long 0x0 0.--31. 1. " ADMA_A32B ,ADMA System address 32 bits.This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32-bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold valid Descriptor address depending on the ADMA state. The Host Driver shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. ADMA2 ignores lower 2-bit of this register and assumes it to be 00b." group.byte 0x260++0x3 line.long 0x0 "MMCHS_PVINITSD,Preset Value for Initialization and Default Speed modes" hexmask.long.word 0x0 0.--9. 1. " INITSDCLK_SEL ,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " INITCLKGEN_SEL ,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " INITDS_SEL ,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " DSSDCLK_SEL ,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " DSCLKGEN_SEL ,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " DSDS_SEL ,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x264++0x3 line.long 0x0 "MMCHS_PVHSSDR12,Preset Value for High Speed and SDR12 speed modes" hexmask.long.word 0x0 0.--9. 1. " HSSDCLK_SEL ,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " HSCLKGEN_SEL ,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " HSDS_SEL ,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " SDR12SDCLK_SEL ,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " SDR12CLKGEN_SEL ,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SDR12DS_SEL ,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x268++0x3 line.long 0x0 "MMCHS_PVSDR25SDR50,Preset Value for SDR25 and SDR50 speed modes" hexmask.long.word 0x0 0.--9. 1. " SDR25SDCLK_SEL ,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " SDR25CLKGEN_SEL ,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " SDR25DS_SEL ,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " SDR50SDCLK_SEL ,SDCLK Frequency Select Value - SDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " SDR50CLKGEN_SEL ,Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SDR50DS_SEL ,Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x26C++0x3 line.long 0x0 "MMCHS_PVSDR104DDR50,Preset Value for SDR104 and DDR50 speed modes" hexmask.long.word 0x0 0.--9. 1. " SDR104SDCLK_SEL ,SDCLK Frequency Select Value - SDR104 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " SDR104CLKGEN_SEL ,Clock Generator Select Value - SDR104 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " SDR104DS_SEL ,Driver Strength Select Value - SDR104 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " DDR50SDCLK_SEL ,SDCLK Frequency Select Value - DDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " DDR50CLKGEN_SEL ,Clock Generator Select Value - DDR50 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " DDR50DS_SEL ,Driver Strength Select Value - DDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x2FC++0x3 line.long 0x0 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. [31:16] = Host controller version [15:0] = Slot Interrupt Status" bitfld.long 0x0 0. " SIS ,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_HCTL[SRA]), the interrupt signal shall be de-asserted and this status shall read 0." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " SREV ,Specification Version Number This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version." hexmask.long.byte 0x0 24.--31. 1. " VREV ,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" width 0x0B tree.end tree "MMC1" base ad:0x4809C000 width 21. group.byte 0x0++0x3 line.long 0x0 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration." bitfld.long 0x0 0. " MADMA_EN ,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA." "0,1" bitfld.long 0x0 1. " MERGE_MEM ,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing." "0,1" textline " " bitfld.long 0x0 2.--5. " MEM_SIZE ,Memory size for FIFO buffer:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " RETMODE ,Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "MMCHS_HL_SYSCONFIG,Clock Management Configuration Register" bitfld.long 0x0 0. " SOFTRESET ,Software reset. (Optional)" "0,1" bitfld.long 0x0 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS." "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" bitfld.long 0x0 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state." "0,1,2,3" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface." bitfld.long 0x0 0. " AUTOIDLE ,Internal Clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wakeup feature control" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Power management" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,This bit is initialized to zero, and writes to it are ignored. Reads return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock" "0,1,2,3" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12.--13. " STANDBYMODE ,Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a '0'." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x114++0x3 line.long 0x0 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "MMCHS_CSRE,Card Status Response Error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit [i] is set to 1, if the corresponding bit at the same position in the response MMCHS_RSP0[i] is set to 1, the host controller indicates a card error ([CERR]) interrupt status to avoid the host driver reading the response register (MMCHS_RSP0). Note: No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register (MMCHS_RESP76) for possible card errors." hexmask.long 0x0 0.--31. 1. " CSRE ,Card status response error" group.byte 0x128++0x3 line.long 0x0 "MMCHS_SYSTEST,System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into register will not start a transfer. The buffer behaves as a stack accessible only by the local host (push and pop operations). In this mode, the Transfer Block Size ([BLEN]) and the Blocks count for current transfer ([NBLK]) are needed to generate a Buffer write ready interrupt ([BWR]) or a Buffer read ready interrupt ([BRR]) and DMA requests if enabled." bitfld.long 0x0 0. " MCKD ,MMC clock output signal data value" "0,1" bitfld.long 0x0 1. " CDIR ,Control of the CMD pin direction." "0,1" textline " " bitfld.long 0x0 2. " CDAT ,CMD input/output signal data value" "0,1" bitfld.long 0x0 3. " DDIR ,Control of the DAT[7:0] pins direction." "0,1" textline " " bitfld.long 0x0 4. " D0D ,DAT0 input/output signal data value" "0,1" bitfld.long 0x0 5. " D1D ,DAT1 input/output signal data value" "0,1" textline " " bitfld.long 0x0 6. " D2D ,DAT2 input/output signal data value" "0,1" bitfld.long 0x0 7. " D3D ,DAT3 input/output signal data value" "0,1" textline " " bitfld.long 0x0 8. " D4D ,DAT4 input/output signal data value" "0,1" bitfld.long 0x0 9. " D5D ,DAT5 input/output signal data value" "0,1" textline " " bitfld.long 0x0 10. " D6D ,DAT6 input/output signal data value" "0,1" bitfld.long 0x0 11. " D7D ,DAT7 input/output signal data value" "0,1" textline " " bitfld.long 0x0 12. " SSB ,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT)." "0,1" bitfld.long 0x0 13. " WAKD ,Wake request output signal data value" "0,1" textline " " bitfld.long 0x0 14. " SDWP ,Write protect input signal (mmci_sdwp) data value" "0,1" bitfld.long 0x0 15. " SDCD ,Card detect input signal (mmci_sdcd) data value" "0,1" textline " " bitfld.long 0x0 16. " OBI ,Out-Of-Band Interrupt (OBI) data value" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x12C++0x3 line.long 0x0 "MMCHS_CON,Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and also to configure : - specific data and command transfers for MMC cards only. - the parameters related to the card detect and write protect input signals." bitfld.long 0x0 0. " OD ,Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode when the card is either in idle, ready or ident state. It is also necessary to set this bit to 1, for a broadcast host response (see Broadcast host response register MMCHS_CON[HR])" "0,1" bitfld.long 0x0 1. " INIT ,Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock cycles. The initialisation sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider (MMCHS_SYSCTL[CLKD]) should be set to ensure that 80 clock periods are greater than 1ms. (see section 9.3, 'Power-Up', in the MMC card specification, or section 6.4 in the SD card specification). Note: in this mode, there is no command sent to the card and no response is expected" "0,1" textline " " bitfld.long 0x0 2. " HR ,Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section 4.3, 'Interrupt Mode', in the MMC specification). In order to have the host response to be generated in open drain mode, the register MMCHS_CON[OD] must be set to 1. When MMCHS_CON[CEATA] is set to 1 and MMCHS_ARG set to 0x00000000 when writing 0x00000000 into MMCHS_CMD register, the host controller performs a 'command completion signal disable' token i.e. CMD line held to '0' during 47 cycles followed by a 1." "0,1" bitfld.long 0x0 3. " STR ,Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a class 3 command (CMD20: WRITE_DAT_UNTIL_STOP)." "0,1" textline " " bitfld.long 0x0 4. " MODE ,Mode select All cards This bit select between Functional mode and SYSTEST mode." "0,1" bitfld.long 0x0 5. " DW8 ,8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliancy with MMC standard specification 4.x (see section 3.6)." "0,1" textline " " bitfld.long 0x0 6. " MIT ,MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detection to be disabled for the command response." "0,1" bitfld.long 0x0 7. " CDP ,Card detect polarity All cards This bit selects the active level of the card detect input signal (mmci_sdcd). The usage of the card detect input signal (mmci_sdcd) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1" textline " " bitfld.long 0x0 8. " WPP ,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (mmci_sdwp). The usage of the write protect input signal (mmci_sdwp) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1" bitfld.long 0x0 9.--10. " DVAL ,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (mmci_sdcd). The usage of the card detect input signal (mmci_sdcd) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1,2,3" textline " " bitfld.long 0x0 11. " CTPL ,Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards: When this bit is set to 1, the host controller automatically disables all the input buffers except the buffer of DAT[1] outside of a transaction in order to detect asynchronous card interrupt on DAT[1] line and minimize the leakage current of the buffers." "0,1" bitfld.long 0x0 12. " CEATA ,CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is used to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features." "0,1" textline " " bitfld.long 0x0 13. " OBIP ,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration." "0,1" bitfld.long 0x0 14. " OBIE ,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration." "0,1" textline " " bitfld.long 0x0 15. " PADEN ,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also combine outside the module with the dedicated power control MMCHS_CON[CTPL] bit." "0,1" bitfld.long 0x0 16. " CLKEXTFREE ,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only if MMCHS_SYSCTL[CEN] is set." "0,1" textline " " bitfld.long 0x0 17. " BOOT_ACK ,Boot acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated." "0,1" bitfld.long 0x0 18. " BOOT_CF0 ,Boot status supported: This register is set when the CMD line need to be forced to '0' for a boot sequence. CMD line is driven to '0' after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer in case of a pending transaction." "0,1" textline " " bitfld.long 0x0 19. " DDR ,Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Data bytes and CRC, Start, end bits and CRC status are kept full cycle. This bit field is only meaningful and active for even clock divider ratio of MMCHS_SYSCTL[CLKD], it is insensitive to MMCHS_HCTL[HSPE] setting." "0,1" bitfld.long 0x0 20. " DMA_MNS ,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available if generic parameter MADMA_EN is asserted to '1'." "0,1" textline " " bitfld.long 0x0 21. " SDMA_LNE ,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data written into MMCHS_DATA." "0,1" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "MMCHS_PWCNT,Power Counter Register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage." hexmask.long.word 0x0 0.--15. 1. " PWRCNT ,Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x134++0x3 line.long 0x0 "MMCHS_DLL,DLL control and status register This register is used for tuning procedure required for SDR104/HS200 speed mode. It gives visibility and control on the DLL" bitfld.long 0x0 0. " DLL_LOCK ,Master DLL lock status." "0,1" bitfld.long 0x0 1. " DLL_CALIB ,Enables Slave DLL to update new delay values." "0,1" textline " " bitfld.long 0x0 2. " DLL_UNLOCK_STICKY ,Asserted when any single period measurement exceeds MAX_LOCK_DIFF." "0,1" bitfld.long 0x0 3. " DLL_UNLOCK_CLEAR ,Clears the phy_reg_status_mdll_unlock_sticky flags of the DLL." "0,1" textline " " bitfld.long 0x0 4.--5. " RESERVED ," "0,1,2,3" bitfld.long 0x0 6.--11. " SLAVE_RATIO ,Fraction of a clock cycle for the shift to be implemented, in units of 256ths of a clock cycle." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 12. " FORCE_VALUE ,Put forced values to slave DLL, ignoring master DLL output and ratio value." "0,1" hexmask.long.byte 0x0 13.--19. 1. " FORCE_SR_C ,Forced coarse delay value" textline " " bitfld.long 0x0 20. " SWT ,Software Tuning enable. The bit shall be set to manage the tuning sequence fully in software. NOTE: For proper operation when SDR104/HS200 mode is used this bit must be set to 0x1 which disables the Conflict Error (CFT Error) on the CMD line. 0x0: No software tuning sequence. 0x1: Execute software tuning sequence." "0,1" bitfld.long 0x0 21. " FORCE_SR_F ,Forced fine delay value." "0,1" textline " " hexmask.long.byte 0x0 22.--29. 1. " MAX_LOCK_DIFF ,Maximum number of taps that the master DLL clock period measurement can deviate without resulting in the master DLL losing lock." bitfld.long 0x0 30. " LOCK_TIMER ,Timer for the dll_lock signal to be asserted after reset." "0,1" textline " " bitfld.long 0x0 31. " DLL_SOFT_RESET ,Soft reset for DLL, active HIGH." "0,1" group.byte 0x200++0x3 line.long 0x0 "MMCHS_SDMASA,SDMA System Address / Argument 2 Register" hexmask.long 0x0 0.--31. 1. " SDMA_ARG2 ,SDMA System Address / Argument 2 This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23. (1) SDMA System Address This register contains the system memory address for a SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (003h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume command or by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register. ADMA does not use this register. (2) Argument 2 This register is used with the Auto CMD23 to set a 32-bit block count value to the argument of the CMD23 while executing Auto CMD23. If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used. If Auto CMD23 is used without AMDA, the available block count value is limited by the Block Count register. 65535 blocks is the maximum value in this case." group.byte 0x204++0x3 line.long 0x0 "MMCHS_BLK,Transfer Length Configuration Register [BLEN] is the block size register. [NBLK] is the block count register. This register shall be used for any card." hexmask.long.word 0x0 0.--11. 1. " BLEN ,Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issued to stop the transfer, a read of the BLEN field after transfer completion (MMCHS_STAT[TC] set to 1) will not return the true byte number of data length while the stop occurs but the value written in this register before transfer is launched." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " NBLK ,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[BCE]) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note: The host controller decrements the block count after each block transfer and stops when the count reaches zero. This register can be accessed only if no transaction is executing (i.e, after a transaction has stopped). Read operations during transfers may return an invalid value and write operation will be ignored. In suspend context, the number of blocks yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, The local host shall restore the previously saved block count." group.byte 0x208++0x3 line.long 0x0 "MMCHS_ARG,Command Argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary." hexmask.long 0x0 0.--31. 1. " ARG ,Command argument bits [31:0]" group.byte 0x20C++0x3 line.long 0x0 "MMCHS_CMD,Command and Transfer Mode Register [31:16] = the command register [15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into [15:0] registers during data transfer has no effect. This register shall be used for any card. Note: In SYSTEST mode, a write into register will not start a transfer." bitfld.long 0x0 0. " DE ,DMA EnableThis bit is used to enable DMA mode for host data access. ." "0,1" bitfld.long 0x0 1. " BCE ,Block Count EnableMultiple block transfers only. . This bit is used to enable the block count register ([NBLK]). . When Block Count is disabled ([BCE] is set to 0) in Multiple block transfers ([MSBS] is set to 1), the module can perform infinite transfer. ." "0,1" textline " " bitfld.long 0x0 2.--3. " ACEN ,Auto CMD Enable - SD card only.This field determines use of auto command functions. . There are two methods to stop Multiple-block read and write operation .  Auto CMD23 Supported (Host Controller Version is 3.00 or later) .  A memory card that supports CMD23 (SCR[33]=1) .  If DMA is used, it shall be ADMA. . Only when CMD18 or CMD25 is issued . (Note: the Host Controller does not check command index.) . Auto CMD23 can be used with or without ADMA. By writing the Command register, the Host Controller issues a CMD23 first and then issues a command specified by the Command Index in Command register. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the Auto CMD Error Status register (). 32-bit block count value for CMD23 is set to SDMA System Address / Argument 2 register (). ." "0,1,2,3" bitfld.long 0x0 4. " DDIR ,Data transfer Direction SelectThis bit defines either data transfer will be a read or a write. ." "0,1" textline " " bitfld.long 0x0 5. " MSBS ,Multi/Single block selectThis bit must be set to 1 for data transfer in case of multi block command. . For any others command this bit shall be set to 0. . If this bit is 0, it is not necessary to set the register[NBLK]. enum=sgleblk . When Block Count is disabled ([BCE] is set to 0) in Multiple block transfers ([MSBS] is set to 1), the module can perform infinite transfer. enum=multiblk ." "0,1" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " RSP_TYPE ,Response typeThis bits defines the response type of the command ." "0,1,2,3" bitfld.long 0x0 18. " RESERVED ," "0,1" textline " " bitfld.long 0x0 19. " CCCE ,Command CRC check enableThis bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. . If an error is detected, it is reported as a command CRC error ([CCRC] set to 1). . Note: The register CCCE cannot be configured for an Auto CMD12, and then CRC check is automatically checked when this command is issued. ." "0,1" bitfld.long 0x0 20. " CICE ,Command Index check enableThis bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. . If the index is not the same in the response as in the command, it is reported as a command index error ([CIE] set to1). . Note:The register CICE cannot be configured for an Auto CMD12, then index check is automatically checked when this command is issued. ." "0,1" textline " " bitfld.long 0x0 21. " DP ,Data present selectThis register indicates that data is present and DAT line shall be used. . It must be set to 0 in the following conditions: . - command using only CMD line . - command with no data transfer but using busy signal on DAT[0] . - Resume command ." "0,1" bitfld.long 0x0 22.--23. " CMD_TYPE ,Command typeThis register specifies three types of special command: Suspend, Resume and Abort. . These bits shall be set to 00b for all other commands. ." "0,1,2,3" textline " " bitfld.long 0x0 24.--29. " INDX ,Command indexBinary encoded value from 0 to 63 specifying the command number send to card ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x210++0x3 line.long 0x0 "MMCHS_RSP10,Command Response[31:0] Register (bits [31:0] of the internal RSP register) This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6/R7" hexmask.long.word 0x0 0.--15. 1. " RSP0 ,Command Response [15:0]" hexmask.long.word 0x0 16.--31. 1. " RSP1 ,Command Response [31:16]" group.byte 0x214++0x3 line.long 0x0 "MMCHS_RSP32,Command Response[63:32] Register (bits [63:32] of the internal RSP register) This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x0 0.--15. 1. " RSP2 ,Command Response [47:32]" hexmask.long.word 0x0 16.--31. 1. " RSP3 ,Command Response [63:48]" group.byte 0x218++0x3 line.long 0x0 "MMCHS_RSP54,Command Response[95:64] Register (bits [95:64] of the internal RSP register) This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x0 0.--15. 1. " RSP4 ,Command Response [79:64]" hexmask.long.word 0x0 16.--31. 1. " RSP5 ,Command Response [95:80]" group.byte 0x21C++0x3 line.long 0x0 "MMCHS_RSP76,Command Response[127:96] Register (bits [127:96] of the internal RSP register) This 32-bit register holds bits positions [127:96] of command response type R1(Auto CMD23)/R1b(Auto CMD12)/R2" hexmask.long.word 0x0 0.--15. 1. " RSP6 ,Command Response [111:96]" hexmask.long.word 0x0 16.--31. 1. " RSP7 ,Command Response [127:112]" group.byte 0x220++0x3 line.long 0x0 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bits x256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register or on the most significant byte of the last word of block transfer. Example 1: Byte or 16-bit access Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad" hexmask.long 0x0 0.--31. 1. " DATA ,Data Register [31:0] In functional mode (MMCHS_CON[MODE] set to the default value 0) , A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCHS_PSTATE[BRE]), otherwise a bad access (MMCHS_STAT[BADA]) is signaled. A write access to this register is allowed only when the buffer write enable status is set to 1(MMCHS_STATE[BWE]), otherwise a bad access (MMCHS_STAT[BADA]) is signaled and the data is not written." group.byte 0x224++0x3 line.long 0x0 "MMCHS_PSTATE,Present State Register The Host can get status of the Host Controller from this 32-bit read only register." bitfld.long 0x0 0. " CMDI ,Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0 in either the following cases: - After the end bit of the command response, excepted if there is a command conflict error (MMCHS_STAT[CCRC] or MMCHS_STAT[CEB] set to 1) or a Auto CMD12 is not executed (MMCHS_AC12[ACNE]). - After the end bit of the command without response (MMCHS_CMD[RSP_TYPE] set to '00') In case of a command data error is detected (MMCHS_STAT[CTO] set to 1), this register is not automatically cleared." "0,1" bitfld.long 0x0 1. " DATI ,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[DLA]) or Read transfer is active (MMCHS_PSTATE[RTA]) or when a command with busy is issued. This bit prevents the local host to issue a command. A change of this bit from 1 to 0 generates a transfer complete interrupt (MMCHS_STAT[TC])." "0,1" textline " " bitfld.long 0x0 2. " DLA ,DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue request MMCHS_HCTL[CR]. This bit is set to 0 when the host controller received the end bit of the last data block or at the beginning of the read wait mode. In the case of write transactions (host to card): This bit is set to 1 after the end bit of write command or by activating continue request MMCHS_HCTL[CR]. This bit is set to 0 on the end of busy event for the last block; host controller must wait 8 clock cycles with line not busy to really consider not 'busy state' or after the busy block as a result of a stop at gap request." "0,1" bitfld.long 0x0 3. " RTR ,Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is cleared when a command is issued with setting MMCHS_AC12[22] ET. This bit isn't set to 1 if MMCHS_AC12[23] SCLK_SEL is set to 0 (using fixed sampling clock). Refer to MMCHS_CAPA2[15:14] RTM for more detail." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " WTA ,Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[CR]) following a stop at block gap request. This bit is set to 0 when CRC status has been received after last block or after a stop at block gap request." "0,1" textline " " bitfld.long 0x0 9. " RTA ,Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[CR]) following a stop at block gap request. This bit is set to 0 when all data have been read by the local host after last block or after a stop at block gap request." "0,1" bitfld.long 0x0 10. " BWE ,Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data." "0,1" textline " " bitfld.long 0x0 11. " BRE ,Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[BLEN] has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from the buffer. It is set to 1 when a block data is ready in the buffer and generates the Buffer read ready status of interrupt (MMCHS_STAT[BRR])." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " CINS ,Card inserted This bit is the debounced value of the card detect input pin (mmci_sdcd). An inactive to active transition of the card detect input pin (mmci_sdcd) will generate a card insertion interrupt (MMCHS_STAT[CINS]). A active to inactive transition of the card detect input pin (mmci_sdcd) will generate a card removal interrupt (MMCHS_STAT[REM]). This bit is not affected by a software reset." "0,1" bitfld.long 0x0 17. " CSS ,Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[CDPL]). Debouncing is performed on the card detect input pin (mmci_sdcd) to detect card stability. This bit is not affected by a software reset." "0,1" textline " " bitfld.long 0x0 18. " CDPL ,Card detect pin level This bit reflects the inverse value of the card detect input pin (mmci_sdcd), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTAE[CSS]) is set to 1. Use of this bit is limited to testing since it must be debounced y software. The value of this register after reset depends on the card detect input pin (mmci_sdcd) level at that time." "0,1" bitfld.long 0x0 19. " WP ,Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (mmci_sdwp) level. The value of this register after reset depends on the protect input pin (mmci_sdwp) level at that time." "0,1" textline " " bitfld.long 0x0 20.--23. " DLEV ,DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. The value of these registers after reset depends on the DAT lines level at that time." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " CLEV ,CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time." "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x228++0x3 line.long 0x0 "MMCHS_HCTL,Host Control Register This register defines the host controls to set power, wakeup and transfer parameters. [31:24] = Wakeup control [23:16] = Block gap control [15:8] = Power control [7:0] = Host control" bitfld.long 0x0 0. " LED ,Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored." "0,1" bitfld.long 0x0 1. " DTW ,Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliance with MMC standard specification 4.x (see section 3.6). This register has no effect when the MMC 8-bit mode is selected (register MMCHS_CON[DW8] set to1 ), For SD/SDIO cards, this bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument. Prior to this command, the SD card configuration register (SCR) must be verified for the supported bus width by the SD card." "0,1" textline " " bitfld.long 0x0 2. " HSPE ,Before setting this bit, the Host Driver shall check theMMCHS_CAPA[21] HSS. This bit shall not be set when dual data rate mode is activated in MMCHS_CON[DDR]." "0,1" bitfld.long 0x0 3.--4. " DMAS ,DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register MMCHS_CAPA . Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This register is only meaningful when MADMA_EN is set to 1. When MADMA_EN is set to 0 the bit field is read only and returned value is 0." "0,1,2,3" textline " " bitfld.long 0x0 5. " RESERVED ," "0,1" bitfld.long 0x0 6. " CDTL ,Card Detect Test Level: This bit is enabled while MMCHS_HCTL[7] CDSS is set to 1 and it indicates whether the card is inserted or not." "0,1" textline " " bitfld.long 0x0 7. " CDSS ,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in order to mask unexpected interrupts caused by the glitch. The Interrupt Status/Signal Enable should be disabled during over the period of debouncing." "0,1" bitfld.long 0x0 8. " SDBP ,SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[SDVS]). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in the command register (MMCHS_CMD) will not start the transfer. A write to this bit has no effect if the selected SD bus voltage MMCHS_HCTL[SDVS] is not supported according to capability register (MMCHS_CAPA[VS*])." "0,1" textline " " bitfld.long 0x0 9.--11. " SDVS ,SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[VS18,VS30,VS33]) before starting a transfer." "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " SBGR ,Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[CR]) or during a suspend/resume sequence. In case of read transfer, the card must support read wait control. In case of write transfer, the host driver shall set this bit after all block data written. Until the transfer completion (MMCHS_STAT[TC] set to 1), the host driver shall leave this bit set to 1. If this bit is set, the local host shall not write to the data register (MMCHS_DATA)." "0,1" bitfld.long 0x0 17. " CR ,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[SBGR]). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when transfer has restarted i.e DAT line is active (MMCHS_PSTATE[DLA]) or transferring data (MMCHS_PSTATE[WTA]). The Stop at block gap request must be disabled (MMCHS_HCTL[SBGR]=0) before setting this bit." "0,1" textline " " bitfld.long 0x0 18. " RWC ,Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[SBGR]) generates a read wait period after the current end of block. Be careful, if read wait is not supported it may cause a conflict on DAT line." "0,1" bitfld.long 0x0 19. " IBG ,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be set to 0." "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " IWE ,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" textline " " bitfld.long 0x0 25. " INS ,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" bitfld.long 0x0 26. " REM ,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" textline " " bitfld.long 0x0 27. " OBWE ,Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP]). The write to this register is ignored when MMCHS_CON[OBIE] is not set." "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "MMCHS_SYSCTL,SD System Control Register This register defines the system controls to set software resets, clock frequency management and data timeout. [31:24] = Software resets [23:16] = Timeout control [15:0] = Clock control" bitfld.long 0x0 0. " ICE ,Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface clock (used for reads and writes to the module register map) are not affected by this register." "0,1" bitfld.long 0x0 1. " ICS ,Internal clock stable (status) This bit indicates either the internal clock is stable or not." "0,1" textline " " bitfld.long 0x0 2. " CEN ,Clock enable This bit controls if the clock is provided to the card or not." "0,1" bitfld.long 0x0 3.--4. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 5. " CGS ,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit. This bit is used to select the clock generator mode in MMCHS_SYSCTL[15:6] CLKD. If the Programmable Clock Mode is supported (non-zero value is set to MMCHS_CAPA2[23:16] CM), this bit attribute is RW, and if not supported, this bit attribute is RO and zero is read. This bit depends on the setting of MMCHS_AC12[31] PV_ENABLE. If PV_ENABLE = 0, this bit is set by Host Driver. If PV_ENABLE = 1, this bit is automatically set to a value specified in one of Preset Value registers, see, ." "0,1" hexmask.long.word 0x0 6.--15. 1. " CLKD ,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO)." textline " " bitfld.long 0x0 16.--19. " DTO ,Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bitfield based on - the maximum read access time (NAC) (Refer to the SD Specification Part1 Physical Layer), - the data read access time values (TAAC and NSAC) in the card specific data register (CSD) of the card, - the timeout clock base frequency (MMCHS_CAPA[TCF]). If the card does not respond within the specified number of cycles, a data timeout error occurs (MMCHS_STA[DTO]). The MMCHS_SYSCTL[DTO] register is also used to check busy duration, to generate busy timeout for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SRA ,Software reset for all This bit is set to 1 for reset , and released to 0 when completed. This reset affects the entire host controller except for the capabilities registers (MMCHS_CAPA and MMCHS_CUR_CAPA)." "0,1" bitfld.long 0x0 25. " SRC ,Software reset for CMD line For more information about SRC bit manipulation, see CMD Line Reset Procedure. This bit is set to 1 for reset and released to 0 when completed. CMD finite state machine in both clock domain are also reset. Here below the registers cleared by MMCHS_SYSCTL[SRC]: - MMCHS_PSTATE: CMDI - MMCHS_STAT: CC Interconnect and MMC command status management is reinitialized." "0,1" textline " " bitfld.long 0x0 26. " SRD ,Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see DATA Lines Reset Procedure. DAT finite state machine in both clock domain are also reset. Here below are the registers cleared by MMCHS_SYSCTL[SRD]: - MMCHS_DATA - MMCHS_PSTATE: BRE, BWE, RTA, WTA, DLA and DATI - MMCHS_HCTL: SBGR and CR - MMCHS_STAT: BRR, BWR, BGE and TC Interconnect and MMC buffer data management is reinitialized." "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x230++0x3 line.long 0x0 "MMCHS_STAT,Interrupt Status Register The interrupt status regroups all the status of the module internal events that can generate an interrupt. [31:16] = Error Interrupt Status [15:0] = Normal Interrupt Status" bitfld.long 0x0 0. " CC ,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[CMDI]) If the command is a type for which no response is expected, then the command complete interrupt is generated at the end of the command. A command timeout error (MMCHS_STAT[CTO]) has higher priority than command complete (MMCHS_STAT[CC]). If a response is expected but none is received, then a command timeout error is detected and signaled instead of the command complete interrupt." "0,1" bitfld.long 0x0 1. " TC ,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[SBGR]). In Read mode: This bit is automatically set on completion of a read transfer (MMCHS_PSTATE[RTA]). In write mode: This bit is set automatically on completion of the DAT line use (MMCHS_PSTATE[DLA])." "0,1" textline " " bitfld.long 0x0 2. " BGE ,Block gap event When a stop at block gap is requested (MMCHS_HCTL[SBGR]), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap is requested on the last block. In read mode, a 1-to-0 transition of the DAT Line active status (MMCHS_PSTATE[DLA]) between data blocks generates a Block gap event interrupt." "0,1" bitfld.long 0x0 3. " DMA ,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion." "0,1" textline " " bitfld.long 0x0 4. " BWR ,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[BLEN]. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer. Note: If the DMA transmit mode is enabled, this bit is never set; instead, a DMA transmit request to the main DMA controller of the system is generated." "0,1" bitfld.long 0x0 5. " BRR ,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[BLEN] is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by reading it. Note: If the DMA receive-mode is enabled, this bit is never set; instead a DMA receive request to the main DMA controller of the system is generated." "0,1" textline " " bitfld.long 0x0 6. " CINS ,Card insertion This bit is set automatically when MMCHS_PSTATE[CINS] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[CINS])." "0,1" bitfld.long 0x0 7. " CREM ,Card removal This bit is set automatically when MMCHS_PSTATE[CINS] changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[CINS])." "0,1" textline " " bitfld.long 0x0 8. " CIRQ ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drives CMD line to zero during one cycle after data transmission end.All modes above are fully exclusive. The controller interrupt must be clear by setting MMCHS_IE[CIRQ] to 0, then the host driver must start the interrupt service with card (clearing card interrupt status) to remove card interrupt source. Otherwise the Controller interrupt will be reasserted as soon as MMCHS_IE[CIRQ] is set to 1. Writes to this bit are ignored." "0,1" bitfld.long 0x0 9. " OBI ,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[OBIE] is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[OBIP]. This interrupt is only useful for MMC card. The Out-of-Band interrupt signal is a system specific feature for future use, this signal is not required for existing specification implementation." "0,1" textline " " bitfld.long 0x0 10. " BSR ,Boot status received interrupt This bit is set automatically when MMCHS_CON[BOOT] is set 0x1 or 0x2 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " ERRI ,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[31:16]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored." "0,1" bitfld.long 0x0 16. " CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles." "0,1" textline " " bitfld.long 0x0 17. " CCRC ,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[CCCE] register." "0,1" bitfld.long 0x0 18. " CEB ,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response." "0,1" textline " " bitfld.long 0x0 19. " CIE ,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[CICE] register." "0,1" bitfld.long 0x0 20. " DTO ,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout" "0,1" textline " " bitfld.long 0x0 21. " DCRC ,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command." "0,1" bitfld.long 0x0 22. " DEB ,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode." "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE ,Auto CMD error Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register (MMCHS_AC12) has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to the previous command error." "0,1" textline " " bitfld.long 0x0 25. " ADMAE ,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller generates this interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state. The Host Driver may find that Valid bit is not set at the error descriptor." "0,1" bitfld.long 0x0 26. " TE ,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Select). By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. To reset tuning circuit, Sampling Clock shall be set to 0 before executing tuning procedure. The Tuning Error is higher priority than the other error interrupts generated during data transfer. By detecting Tuning Error, the Host Driver should discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from tuning circuit error. The bit is set if the lock is lost (but not during the tuning process) or if the lock counter expires without the lock being asserted. If the latter happens, the SW can decide to ignore the interrupt and wait some more for the lock to be set." "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR ,Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error MMCHS_CSRE in set. There is no card error detection for autoCMD12 command. The host driver shall read MMCHS_RSP76 register to detect error bits in the command response." "0,1" textline " " bitfld.long 0x0 29. " BADA ,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[BRE] =0) -This bit is set during a write access to the data register (MMCHS_DATA) while buffer writes are not allowed (MMCHS_STATE[BWE] =0)" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x234++0x3 line.long 0x0 "MMCHS_IE,Interrupt Status Enable Register This register allows to enable/disable the module to set status bits, on an event-by-event basis. [31:16] = Error Interrupt Status Enable [15:0] = Normal Interrupt Status Enable" bitfld.long 0x0 0. " CC_ENABLE ,Command Complete Status Enable" "0,1" bitfld.long 0x0 1. " TC_ENABLE ,Transfer Complete Status Enable" "0,1" textline " " bitfld.long 0x0 2. " BGE_ENABLE ,Block Gap Event Status Enable" "0,1" bitfld.long 0x0 3. " DMA_ENABLE ,DMA Status Enable" "0,1" textline " " bitfld.long 0x0 4. " BWR_ENABLE ,Buffer Write Ready Status Enable" "0,1" bitfld.long 0x0 5. " BRR_ENABLE ,Buffer Read Ready Status Enable" "0,1" textline " " bitfld.long 0x0 6. " CINS_ENABLE ,Card Insertion Status Enable" "0,1" bitfld.long 0x0 7. " CREM_ENABLE ,Card Removal Status Enable" "0,1" textline " " bitfld.long 0x0 8. " CIRQ_ENABLE ,Card Status Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1." "0,1" bitfld.long 0x0 9. " OBI_ENABLE ,Out-of-Band Status Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored." "0,1" textline " " bitfld.long 0x0 10. " BSR_ENABLE ,Boot Status Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x0 16. " CTO_ENABLE ,Command Timeout Error Status Enable" "0,1" textline " " bitfld.long 0x0 17. " CCRC_ENABLE ,Command CRC Error Status Enable" "0,1" bitfld.long 0x0 18. " CEB_ENABLE ,Command End Bit Error Status Enable" "0,1" textline " " bitfld.long 0x0 19. " CIE_ENABLE ,Command Index Error Status Enable" "0,1" bitfld.long 0x0 20. " DTO_ENABLE ,Data Timeout Error Status Enable" "0,1" textline " " bitfld.long 0x0 21. " DCRC_ENABLE ,Data CRC Error Status Enable" "0,1" bitfld.long 0x0 22. " DEB_ENABLE ,Data End Bit Error Status Enable" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE_ENABLE ,Auto CMD Error Status Enable" "0,1" textline " " bitfld.long 0x0 25. " ADMAE_ENABLE ,ADMA Error Status Enable" "0,1" bitfld.long 0x0 26. " TE_ENABLE ,Tuning Error Status Enable" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR_ENABLE ,Card Error Status Enable" "0,1" textline " " bitfld.long 0x0 29. " BADA_ENABLE ,Bad access to data space Status Enable" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x238++0x3 line.long 0x0 "MMCHS_ISE,Interrupt Signal Enable Register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. [31:16] = Error Interrupt Signal Enable [15:0] = Normal Interrupt Signal Enable" bitfld.long 0x0 0. " CC_SIGEN ,Command Complete Status Enable" "0,1" bitfld.long 0x0 1. " TC_SIGEN ,Transfer Completed Status Enable" "0,1" textline " " bitfld.long 0x0 2. " BGE_SIGEN ,Black Gap Event Signal Enable" "0,1" bitfld.long 0x0 3. " DMA_SIGEN ,DMA Interrupt Signal Enable" "0,1" textline " " bitfld.long 0x0 4. " BWR_SIGEN ,Buffer Write Ready Signal Enable" "0,1" bitfld.long 0x0 5. " BRR_SIGEN ,Buffer Read Ready Signal Enable" "0,1" textline " " bitfld.long 0x0 6. " CINS_SIGEN ,Card Insertion Signal Enable" "0,1" bitfld.long 0x0 7. " CREM_SIGEN ,Card Removal Signal Enable" "0,1" textline " " bitfld.long 0x0 8. " CIRQ_SIGEN ,Card Interrupt Signal Enable" "0,1" bitfld.long 0x0 9. " OBI_SIGEN ,Out-Of-Band Interrupt Signal Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored." "0,1" textline " " bitfld.long 0x0 10. " BSR_SIGEN ,Boot Status Signal Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x0 16. " CTO_SIGEN ,Command timeout Error Signal Enable" "0,1" textline " " bitfld.long 0x0 17. " CCRC_SIGEN ,Command CRC Error Signal Enable" "0,1" bitfld.long 0x0 18. " CEB_SIGEN ,Command End Bit Error Signal Enable" "0,1" textline " " bitfld.long 0x0 19. " CIE_SIGEN ,Command Index Error Signal Enable" "0,1" bitfld.long 0x0 20. " DTO_SIGEN ,Data Timeout Error Signal Enable" "0,1" textline " " bitfld.long 0x0 21. " DCRC_SIGEN ,Data CRC Error Signal Enable" "0,1" bitfld.long 0x0 22. " DEB_SIGEN ,Data End Bit Error Signal Enable" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE_SIGEN ,Auto CMD Error Signal Enable" "0,1" textline " " bitfld.long 0x0 25. " ADMAE_SIGEN ,ADMA Error Signal Enable" "0,1" bitfld.long 0x0 26. " TE_SIGEN ,Tuning Error Signal Enable" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR_SIGEN ,Card Error Interrupt Signal Enable" "0,1" textline " " bitfld.long 0x0 29. " BADA_SIGEN ,Bad access to data space Signal Enable" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x23C++0x3 line.long 0x0 "MMCHS_AC12,Host Control 2 Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12 / CMD23 errors occur by this register. Auto CMD23 errors are indicated only in bits[4:1]. Bits[7:0] are valid only when the [3:2] ACEN bitfield is configured to enable Auto CMD and the Auto CMD Error bit ([24]ACE) is set." bitfld.long 0x0 0. " ACNE ,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the Host Controller cannot issue Auto CMD12 to stop memory multiple block data transfer due to some error. If this bit is set to 1, other error status bits (D04-D01) are meaningless. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" bitfld.long 0x0 1. " ACTO ,Auto CMD Timeout Error - For Auto CMD12 and Auto CMD23 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command. If this bit is set to1, the other error status bits (D04-D02) are meaningless." "0,1" textline " " bitfld.long 0x0 2. " ACCE ,Auto CMD CRC Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting a CRC error in the command response." "0,1" bitfld.long 0x0 3. " ACEB ,Auto CMD End Bit Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting that the end bit of command response is 0." "0,1" textline " " bitfld.long 0x0 4. " ACIE ,Auto CMD Index Error - For Auto CMD12 and Auto CMD23 This bit is set if the Command Index error occurs in response to a command." "0,1" bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 7. " CNI ,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " UHSMS ,UHS Mode Select This field is used to select one of UHS-I modes or eMMC HS200 mode and is effective when 1.8V Signaling Enable is set to 1. If MMCHS_AC12[31] PV_ENABLE is set to 1, Host Controller sets MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL according to Preset Value registers, see, . In this case, one of preset value registers is selected by this field. Host Driver needs to reset MMCHS_SYSCTL[2] CEN before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets MMCHS_SYSCTL[2] CEN again. When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more detail." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " V1V8_SIGEN ,1.8V Signaling Enable This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails. Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V. 3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling (One of support bits is set to 1: SDR50, SDR104 or DDR50 in MMCHS_CAPA2 register) and the card or device supports UHS-I (S18A=1. Refer to Bus Signal Voltage Switch Sequence in the Physical Layer Specification Version 3.0x)." "0,1" textline " " bitfld.long 0x0 20.--21. " DS_SEL ,Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set depending on Driver Type A, C and D support bits (DTA, DTC and DTD respectively) in the MMCHS_CAPA2 register. This bit depends on setting of Preset Value Enable. If Preset Value Enable = 0, this field is set by Host Driver. If Preset Value Enable = 1, this field is automatically set by a value specified in the one of Preset Value registers, see, ." "0,1,2,3" bitfld.long 0x0 22. " ET ,Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to MMCHS_AC12[23] SCLK_SEL. Tuning procedure is aborted by writing 0. This is Read-Write with automatic clear register" "0,1" textline " " bitfld.long 0x0 23. " SCLK_SEL ,Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is set by tuning procedure and valid after the completion of tuning (when MMCHS_AC12[22] ET is cleared). Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Writing 1 to this bit is meaningless and ignored. A tuning circuit is reset by writing to 0. This bit can be cleared with setting MMCHS_AC12[22] ET. Once the tuning circuit is reset, it will take time to complete tuning sequence. Therefore, Host Driver should keep this bit to 1 to perform re-tuning sequence to compete re-tuning sequence in a short time. Change of this bit is not allowed while the Host Controller is receiving response or a read data block." "0,1" bitfld.long 0x0 24.--29. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " AI_ENABLE ,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and MMCHS_CAPA[29] AIS is set to 1. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver the Card Interrupt to the host when it is asserted by the Card." "0,1" bitfld.long 0x0 31. " PV_ENABLE ,Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When Preset Value Enable is set, automatic SDCLK frequency generation and driver strength selection is performed without considering system specific conditions. This bit enables the functions defined in the Preset Value registers, see, . If this bit is set to 0, MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL are set by Host Driver. If this bit is set to 1, MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL are set by Host Controller as specified in the Preset Value registers, see, ." "0,1" group.byte 0x240++0x3 line.long 0x0 "MMCHS_CAPA,Capabilities Register This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x0 0.--5. " TCF ,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[DTO])." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " RESERVED ," "0,1" textline " " bitfld.long 0x0 7. " TCU ,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[DTO])." "0,1" hexmask.long.byte 0x0 8.--15. 1. " BCF ,Base Clock Frequency For SD Clock This value indicates the base (maximum) clock frequency for the SD Clock. 8-bit Base Clock Frequency This mode is supported by the Host Controller Version 3.00. Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh : 255MHz .... : ....... 02h : 2MHz 01h : 1MHz 00h : Get information via another method If the real frequency is 16.5MHz, the lager value shall be set 0001 0001b (17MHz) because the Host Driver use this value to calculate the clock divider value (Refer to MMCHS_SYSCTL[15:6] CLKD) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method." textline " " bitfld.long 0x0 16.--17. " MBL ,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 bytes. The host controller supports 512 bytes and 1024 bytes block transfers." "0,1,2,3" bitfld.long 0x0 18. " RESERVED ," "0,1" textline " " bitfld.long 0x0 19. " AD2S ,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2. It depends on setting of generic parameter MADMA_EN" "0,1" bitfld.long 0x0 20. " RESERVED ," "0,1" textline " " bitfld.long 0x0 21. " HSS ,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency." "0,1" bitfld.long 0x0 22. " DS ,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly." "0,1" textline " " bitfld.long 0x0 23. " SRS ,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality." "0,1" bitfld.long 0x0 24. " VS33 ,Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" textline " " bitfld.long 0x0 25. " VS30 ,Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" bitfld.long 0x0 26. " VS18 ,Voltage support 1.8V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " BIT64 ,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus." "0,1" textline " " bitfld.long 0x0 29. " AIS ,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x244++0x3 line.long 0x0 "MMCHS_CAPA2,Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer to Software Reset For All in the Software Reset register for loading from flash memory and completion timing control." bitfld.long 0x0 0. " SDR50 ,SDR50 Support If SDR104 is supported, this bit shall be set to 1. Bit 13 indicates whether SDR50 requires tuning or not." "0,1" bitfld.long 0x0 1. " SDR104 ,SDR104 Support SDR104 requires tuning." "0,1" textline " " bitfld.long 0x0 2. " DDR50 ,DDR50 Support" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " DTA ,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling." "0,1" bitfld.long 0x0 5. " DTC ,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling." "0,1" textline " " bitfld.long 0x0 6. " DTD ,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling." "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--11. " TCRT ,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 0 disables Re-Tuning Timer." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13. " TSDR50 ,Use Tuning for SDR50 If this bit is set to 1, this Host Controller requires tuning to operate SDR50. (Tuning is always required to operate SDR104.)" "0,1" bitfld.long 0x0 14.--15. " RTM ,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length." "0,1,2,3" textline " " hexmask.long.byte 0x0 16.--23. 1. " CM ,Clock Multiplier This field indicates clock multiplier value of programmable clock generator. Refer to MMCHS_SYSCTL [15:0]. Setting 00h means that Host Controller does not support programmable clock generator. 00h : Clock Multiplier is Not Supported 01h : Clock Multiplier M = 2 02h : Clock Multiplier M = 3 .... : ...................... FFh : Clock Multiplier M = 256" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x248++0x3 line.long 0x0 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (). Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" hexmask.long.byte 0x0 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V" hexmask.long.byte 0x0 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V" textline " " hexmask.long.byte 0x0 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "MMCHS_FE,Force Event Register for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register. Rather, it is an address at which the Auto CMD Error Status Register () can be written. Writing 1 : set each bit of the Auto CMD Error Status Register Writing 0 : no effect Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register if the corresponding bit of the Error Interrupt Status Enable Register is set. Writing 1 : set each bit of the Error Interrupt Status Register Writing 0 : no effect Note: By setting this register, the Error Interrupt can be set in the Error Interrupt Status register. In order to generate interrupt signal, both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be set." bitfld.long 0x0 0. " FE_ACNE ,Force Event Auto CMD12 Not Executed" "0,1" bitfld.long 0x0 1. " FE_ACTO ,Force Event Auto CMD Timeout Error" "0,1" textline " " bitfld.long 0x0 2. " FE_ACCE ,Force Event Auto CMD CRC Error" "0,1" bitfld.long 0x0 3. " FE_ACEB ,Force Event Auto CMD End Bit Error" "0,1" textline " " bitfld.long 0x0 4. " FE_ACIE ,Force Event for Auto CMD Index Error - For Auto CMD12 and Auto CMD23" "0,1" bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error" "0,1" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " FE_CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles." "0,1" bitfld.long 0x0 17. " FE_CCRC ,Force Event Command CRC Error." "0,1" textline " " bitfld.long 0x0 18. " FE_CEB ,Force Event Command End Bit Error." "0,1" bitfld.long 0x0 19. " FE_CIE ,Force Event Command Index Error." "0,1" textline " " bitfld.long 0x0 20. " FE_DTO ,Force Event Data Timeout Error." "0,1" bitfld.long 0x0 21. " FE_DCRC ,Force Event Data CRC Error." "0,1" textline " " bitfld.long 0x0 22. " FE_DEB ,Force Event Data End Bit error." "0,1" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24. " FE_ACE ,Force Event for Auto CMD Error - For Auto CMD12 and Auto CMD23" "0,1" bitfld.long 0x0 25. " FE_ADMAE ,Force Event ADMA Error." "0,1" textline " " bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" bitfld.long 0x0 28. " FE_CERR ,Force Event Card error." "0,1" textline " " bitfld.long 0x0 29. " FE_BADA ,Force Event Bad access to data space." "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x254++0x3 line.long 0x0 "MMCHS_ADMAES,ADMA Error Status Register When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the error, the Host Driver requires the ADMA state to identify the error descriptor address as follows: ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address ST_FDS: Current location set in the ADMA System Address register is the error descriptor address ST_CADR: This sate is never set because do not generate ADMA error in this state. ST_TFR: Previous location set in the ADMA System Address register is the error descriptor address In case of write operation, the Host Driver should use ACMD22 to get the number of written block rather than using this information, since unwritten data may exist in the Host Controller. The Host Controller generates the ADMA Error Interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. In this case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host Driver may find that the Valid bit is not set in the error descriptor." bitfld.long 0x0 0.--1. " AES ,ADMA Error StateThis field indicates the state of ADMA when error occurred during ADMA data transfer. This field will never be 0x2 because ADMA never stops in that state.0x0: ST_STOP (STOP_ADMA). Previous SYS_ADR is the error descriptor address0x1: ST_FDS (Fetch Descriptor). Content of current SYS_ADR is the error descriptor address0x2: Not used. Error never set in this state0x3: ST_TFR (Transfer Data). Previous SYS_ADR is the error descriptor address" "0,1,2,3" bitfld.long 0x0 2. " LME ,ADMA Length Mismatch Error: (1) While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. (2) Total data length can not be divided by the block length." "0,1" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x258++0x3 line.long 0x0 "MMCHS_ADMASAL,ADMA System address Low bits" hexmask.long 0x0 0.--31. 1. " ADMA_A32B ,ADMA System address 32 bits.This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32-bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold valid Descriptor address depending on the ADMA state. The Host Driver shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. ADMA2 ignores lower 2-bit of this register and assumes it to be 00b." group.byte 0x260++0x3 line.long 0x0 "MMCHS_PVINITSD,Preset Value for Initialization and Default Speed modes" hexmask.long.word 0x0 0.--9. 1. " INITSDCLK_SEL ,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " INITCLKGEN_SEL ,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " INITDS_SEL ,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " DSSDCLK_SEL ,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " DSCLKGEN_SEL ,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " DSDS_SEL ,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x264++0x3 line.long 0x0 "MMCHS_PVHSSDR12,Preset Value for High Speed and SDR12 speed modes" hexmask.long.word 0x0 0.--9. 1. " HSSDCLK_SEL ,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " HSCLKGEN_SEL ,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " HSDS_SEL ,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " SDR12SDCLK_SEL ,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " SDR12CLKGEN_SEL ,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SDR12DS_SEL ,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x268++0x3 line.long 0x0 "MMCHS_PVSDR25SDR50,Preset Value for SDR25 and SDR50 speed modes" hexmask.long.word 0x0 0.--9. 1. " SDR25SDCLK_SEL ,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " SDR25CLKGEN_SEL ,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " SDR25DS_SEL ,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " SDR50SDCLK_SEL ,SDCLK Frequency Select Value - SDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " SDR50CLKGEN_SEL ,Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SDR50DS_SEL ,Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x26C++0x3 line.long 0x0 "MMCHS_PVSDR104DDR50,Preset Value for SDR104 and DDR50 speed modes" hexmask.long.word 0x0 0.--9. 1. " SDR104SDCLK_SEL ,SDCLK Frequency Select Value - SDR104 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " SDR104CLKGEN_SEL ,Clock Generator Select Value - SDR104 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " SDR104DS_SEL ,Driver Strength Select Value - SDR104 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " DDR50SDCLK_SEL ,SDCLK Frequency Select Value - DDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " DDR50CLKGEN_SEL ,Clock Generator Select Value - DDR50 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " DDR50DS_SEL ,Driver Strength Select Value - DDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x2FC++0x3 line.long 0x0 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. [31:16] = Host controller version [15:0] = Slot Interrupt Status" bitfld.long 0x0 0. " SIS ,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_HCTL[SRA]), the interrupt signal shall be de-asserted and this status shall read 0." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " SREV ,Specification Version Number This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version." hexmask.long.byte 0x0 24.--31. 1. " VREV ,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" width 0x0B tree.end tree "MMC2" base ad:0x480B4000 width 21. group.byte 0x0++0x3 line.long 0x0 "MMCHS_HL_REV,IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "MMCHS_HL_HWINFO,Information about the IP module's hardware configuration." bitfld.long 0x0 0. " MADMA_EN ,Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA." "0,1" bitfld.long 0x0 1. " MERGE_MEM ,Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing." "0,1" textline " " bitfld.long 0x0 2.--5. " MEM_SIZE ,Memory size for FIFO buffer:" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 6. " RETMODE ,Retention Mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET." "0,1" textline " " hexmask.long 0x0 7.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "MMCHS_HL_SYSCONFIG,Clock Management Configuration Register" bitfld.long 0x0 0. " SOFTRESET ,Software reset. (Optional)" "0,1" bitfld.long 0x0 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS." "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" bitfld.long 0x0 4.--5. " STANDBYMODE ,Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state." "0,1,2,3" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "MMCHS_SYSCONFIG,System Configuration Register This register allows controlling various parameters of the Interconnect interface." bitfld.long 0x0 0. " AUTOIDLE ,Internal Clock gating strategy" "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wakeup feature control" "0,1" bitfld.long 0x0 3.--4. " SIDLEMODE ,Power management" "0,1,2,3" textline " " bitfld.long 0x0 5.--7. " RESERVED ,This bit is initialized to zero, and writes to it are ignored. Reads return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock" "0,1,2,3" textline " " bitfld.long 0x0 10.--11. " RESERVED ," "0,1,2,3" bitfld.long 0x0 12.--13. " STANDBYMODE ,Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a '0'." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," group.byte 0x114++0x3 line.long 0x0 "MMCHS_SYSSTATUS,System Status Register This register provides status information about the module excluding the interrupt status information" bitfld.long 0x0 0. " RESETDONE ,Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x124++0x3 line.long 0x0 "MMCHS_CSRE,Card Status Response Error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit [i] is set to 1, if the corresponding bit at the same position in the response MMCHS_RSP0[i] is set to 1, the host controller indicates a card error ([CERR]) interrupt status to avoid the host driver reading the response register (MMCHS_RSP0). Note: No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register (MMCHS_RESP76) for possible card errors." hexmask.long 0x0 0.--31. 1. " CSRE ,Card status response error" group.byte 0x128++0x3 line.long 0x0 "MMCHS_SYSTEST,System Test Register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into register will not start a transfer. The buffer behaves as a stack accessible only by the local host (push and pop operations). In this mode, the Transfer Block Size ([BLEN]) and the Blocks count for current transfer ([NBLK]) are needed to generate a Buffer write ready interrupt ([BWR]) or a Buffer read ready interrupt ([BRR]) and DMA requests if enabled." bitfld.long 0x0 0. " MCKD ,MMC clock output signal data value" "0,1" bitfld.long 0x0 1. " CDIR ,Control of the CMD pin direction." "0,1" textline " " bitfld.long 0x0 2. " CDAT ,CMD input/output signal data value" "0,1" bitfld.long 0x0 3. " DDIR ,Control of the DAT[7:0] pins direction." "0,1" textline " " bitfld.long 0x0 4. " D0D ,DAT0 input/output signal data value" "0,1" bitfld.long 0x0 5. " D1D ,DAT1 input/output signal data value" "0,1" textline " " bitfld.long 0x0 6. " D2D ,DAT2 input/output signal data value" "0,1" bitfld.long 0x0 7. " D3D ,DAT3 input/output signal data value" "0,1" textline " " bitfld.long 0x0 8. " D4D ,DAT4 input/output signal data value" "0,1" bitfld.long 0x0 9. " D5D ,DAT5 input/output signal data value" "0,1" textline " " bitfld.long 0x0 10. " D6D ,DAT6 input/output signal data value" "0,1" bitfld.long 0x0 11. " D7D ,DAT7 input/output signal data value" "0,1" textline " " bitfld.long 0x0 12. " SSB ,Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT)." "0,1" bitfld.long 0x0 13. " WAKD ,Wake request output signal data value" "0,1" textline " " bitfld.long 0x0 14. " SDWP ,Write protect input signal (mmci_sdwp) data value" "0,1" bitfld.long 0x0 15. " SDCD ,Card detect input signal (mmci_sdcd) data value" "0,1" textline " " bitfld.long 0x0 16. " OBI ,Out-Of-Band Interrupt (OBI) data value" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x12C++0x3 line.long 0x0 "MMCHS_CON,Configuration Register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and also to configure : - specific data and command transfers for MMC cards only. - the parameters related to the card detect and write protect input signals." bitfld.long 0x0 0. " OD ,Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode when the card is either in idle, ready or ident state. It is also necessary to set this bit to 1, for a broadcast host response (see Broadcast host response register MMCHS_CON[HR])" "0,1" bitfld.long 0x0 1. " INIT ,Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock cycles. The initialisation sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider (MMCHS_SYSCTL[CLKD]) should be set to ensure that 80 clock periods are greater than 1ms. (see section 9.3, 'Power-Up', in the MMC card specification, or section 6.4 in the SD card specification). Note: in this mode, there is no command sent to the card and no response is expected" "0,1" textline " " bitfld.long 0x0 2. " HR ,Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section 4.3, 'Interrupt Mode', in the MMC specification). In order to have the host response to be generated in open drain mode, the register MMCHS_CON[OD] must be set to 1. When MMCHS_CON[CEATA] is set to 1 and MMCHS_ARG set to 0x00000000 when writing 0x00000000 into MMCHS_CMD register, the host controller performs a 'command completion signal disable' token i.e. CMD line held to '0' during 47 cycles followed by a 1." "0,1" bitfld.long 0x0 3. " STR ,Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a class 3 command (CMD20: WRITE_DAT_UNTIL_STOP)." "0,1" textline " " bitfld.long 0x0 4. " MODE ,Mode select All cards This bit select between Functional mode and SYSTEST mode." "0,1" bitfld.long 0x0 5. " DW8 ,8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliancy with MMC standard specification 4.x (see section 3.6)." "0,1" textline " " bitfld.long 0x0 6. " MIT ,MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detection to be disabled for the command response." "0,1" bitfld.long 0x0 7. " CDP ,Card detect polarity All cards This bit selects the active level of the card detect input signal (mmci_sdcd). The usage of the card detect input signal (mmci_sdcd) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1" textline " " bitfld.long 0x0 8. " WPP ,Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (mmci_sdwp). The usage of the write protect input signal (mmci_sdwp) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1" bitfld.long 0x0 9.--10. " DVAL ,Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (mmci_sdcd). The usage of the card detect input signal (mmci_sdcd) is optional and depends on the system integration and the type of the connector housing that accommodates the card." "0,1,2,3" textline " " bitfld.long 0x0 11. " CTPL ,Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards: When this bit is set to 1, the host controller automatically disables all the input buffers except the buffer of DAT[1] outside of a transaction in order to detect asynchronous card interrupt on DAT[1] line and minimize the leakage current of the buffers." "0,1" bitfld.long 0x0 12. " CEATA ,CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is used to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features." "0,1" textline " " bitfld.long 0x0 13. " OBIP ,Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration." "0,1" bitfld.long 0x0 14. " OBIE ,Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration." "0,1" textline " " bitfld.long 0x0 15. " PADEN ,Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also combine outside the module with the dedicated power control MMCHS_CON[CTPL] bit." "0,1" bitfld.long 0x0 16. " CLKEXTFREE ,External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only if MMCHS_SYSCTL[CEN] is set." "0,1" textline " " bitfld.long 0x0 17. " BOOT_ACK ,Boot acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated." "0,1" bitfld.long 0x0 18. " BOOT_CF0 ,Boot status supported: This register is set when the CMD line need to be forced to '0' for a boot sequence. CMD line is driven to '0' after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer in case of a pending transaction." "0,1" textline " " bitfld.long 0x0 19. " DDR ,Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Data bytes and CRC, Start, end bits and CRC status are kept full cycle. This bit field is only meaningful and active for even clock divider ratio of MMCHS_SYSCTL[CLKD], it is insensitive to MMCHS_HCTL[HSPE] setting." "0,1" bitfld.long 0x0 20. " DMA_MNS ,DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available if generic parameter MADMA_EN is asserted to '1'." "0,1" textline " " bitfld.long 0x0 21. " SDMA_LNE ,Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data written into MMCHS_DATA." "0,1" hexmask.long.word 0x0 22.--31. 1. " RESERVED ," group.byte 0x130++0x3 line.long 0x0 "MMCHS_PWCNT,Power Counter Register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage." hexmask.long.word 0x0 0.--15. 1. " PWRCNT ,Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x134++0x3 line.long 0x0 "MMCHS_DLL,DLL control and status register This register is used for tuning procedure required for SDR104/HS200 speed mode. It gives visibility and control on the DLL" bitfld.long 0x0 0. " DLL_LOCK ,Master DLL lock status." "0,1" bitfld.long 0x0 1. " DLL_CALIB ,Enables Slave DLL to update new delay values." "0,1" textline " " bitfld.long 0x0 2. " DLL_UNLOCK_STICKY ,Asserted when any single period measurement exceeds MAX_LOCK_DIFF." "0,1" bitfld.long 0x0 3. " DLL_UNLOCK_CLEAR ,Clears the phy_reg_status_mdll_unlock_sticky flags of the DLL." "0,1" textline " " bitfld.long 0x0 4.--5. " RESERVED ," "0,1,2,3" bitfld.long 0x0 6.--11. " SLAVE_RATIO ,Fraction of a clock cycle for the shift to be implemented, in units of 256ths of a clock cycle." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 12. " FORCE_VALUE ,Put forced values to slave DLL, ignoring master DLL output and ratio value." "0,1" hexmask.long.byte 0x0 13.--19. 1. " FORCE_SR_C ,Forced coarse delay value" textline " " bitfld.long 0x0 20. " SWT ,Software Tuning enable. The bit shall be set to manage the tuning sequence fully in software. NOTE: For proper operation when SDR104/HS200 mode is used this bit must be set to 0x1 which disables the Conflict Error (CFT Error) on the CMD line. 0x0: No software tuning sequence. 0x1: Execute software tuning sequence." "0,1" bitfld.long 0x0 21. " FORCE_SR_F ,Forced fine delay value." "0,1" textline " " hexmask.long.byte 0x0 22.--29. 1. " MAX_LOCK_DIFF ,Maximum number of taps that the master DLL clock period measurement can deviate without resulting in the master DLL losing lock." bitfld.long 0x0 30. " LOCK_TIMER ,Timer for the dll_lock signal to be asserted after reset." "0,1" textline " " bitfld.long 0x0 31. " DLL_SOFT_RESET ,Soft reset for DLL, active HIGH." "0,1" group.byte 0x200++0x3 line.long 0x0 "MMCHS_SDMASA,SDMA System Address / Argument 2 Register" hexmask.long 0x0 0.--31. 1. " SDMA_ARG2 ,SDMA System Address / Argument 2 This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23. (1) SDMA System Address This register contains the system memory address for a SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point to the system address of the next contiguous data position. It can be accessed only if no transaction is executing (i.e., after a transaction has stopped). Read operations during transfers may return an invalid value. The Host Driver shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the Host SDMA Buffer Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (003h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume command or by setting Continue Request in the Block Gap Control register, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register. ADMA does not use this register. (2) Argument 2 This register is used with the Auto CMD23 to set a 32-bit block count value to the argument of the CMD23 while executing Auto CMD23. If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used. If Auto CMD23 is used without AMDA, the available block count value is limited by the Block Count register. 65535 blocks is the maximum value in this case." group.byte 0x204++0x3 line.long 0x0 "MMCHS_BLK,Transfer Length Configuration Register [BLEN] is the block size register. [NBLK] is the block count register. This register shall be used for any card." hexmask.long.word 0x0 0.--11. 1. " BLEN ,Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issued to stop the transfer, a read of the BLEN field after transfer completion (MMCHS_STAT[TC] set to 1) will not return the true byte number of data length while the stop occurs but the value written in this register before transfer is launched." bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " NBLK ,Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[BCE]) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note: The host controller decrements the block count after each block transfer and stops when the count reaches zero. This register can be accessed only if no transaction is executing (i.e, after a transaction has stopped). Read operations during transfers may return an invalid value and write operation will be ignored. In suspend context, the number of blocks yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, The local host shall restore the previously saved block count." group.byte 0x208++0x3 line.long 0x0 "MMCHS_ARG,Command Argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary." hexmask.long 0x0 0.--31. 1. " ARG ,Command argument bits [31:0]" group.byte 0x20C++0x3 line.long 0x0 "MMCHS_CMD,Command and Transfer Mode Register [31:16] = the command register [15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into [15:0] registers during data transfer has no effect. This register shall be used for any card. Note: In SYSTEST mode, a write into register will not start a transfer." bitfld.long 0x0 0. " DE ,DMA EnableThis bit is used to enable DMA mode for host data access. ." "0,1" bitfld.long 0x0 1. " BCE ,Block Count EnableMultiple block transfers only. . This bit is used to enable the block count register ([NBLK]). . When Block Count is disabled ([BCE] is set to 0) in Multiple block transfers ([MSBS] is set to 1), the module can perform infinite transfer. ." "0,1" textline " " bitfld.long 0x0 2.--3. " ACEN ,Auto CMD Enable - SD card only.This field determines use of auto command functions. . There are two methods to stop Multiple-block read and write operation .  Auto CMD23 Supported (Host Controller Version is 3.00 or later) .  A memory card that supports CMD23 (SCR[33]=1) .  If DMA is used, it shall be ADMA. . Only when CMD18 or CMD25 is issued . (Note: the Host Controller does not check command index.) . Auto CMD23 can be used with or without ADMA. By writing the Command register, the Host Controller issues a CMD23 first and then issues a command specified by the Command Index in Command register. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the Auto CMD Error Status register (). 32-bit block count value for CMD23 is set to SDMA System Address / Argument 2 register (). ." "0,1,2,3" bitfld.long 0x0 4. " DDIR ,Data transfer Direction SelectThis bit defines either data transfer will be a read or a write. ." "0,1" textline " " bitfld.long 0x0 5. " MSBS ,Multi/Single block selectThis bit must be set to 1 for data transfer in case of multi block command. . For any others command this bit shall be set to 0. . If this bit is 0, it is not necessary to set the register[NBLK]. enum=sgleblk . When Block Count is disabled ([BCE] is set to 0) in Multiple block transfers ([MSBS] is set to 1), the module can perform infinite transfer. enum=multiblk ." "0,1" hexmask.long.word 0x0 6.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--17. " RSP_TYPE ,Response typeThis bits defines the response type of the command ." "0,1,2,3" bitfld.long 0x0 18. " RESERVED ," "0,1" textline " " bitfld.long 0x0 19. " CCCE ,Command CRC check enableThis bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. . If an error is detected, it is reported as a command CRC error ([CCRC] set to 1). . Note: The register CCCE cannot be configured for an Auto CMD12, and then CRC check is automatically checked when this command is issued. ." "0,1" bitfld.long 0x0 20. " CICE ,Command Index check enableThis bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. . If the index is not the same in the response as in the command, it is reported as a command index error ([CIE] set to1). . Note:The register CICE cannot be configured for an Auto CMD12, then index check is automatically checked when this command is issued. ." "0,1" textline " " bitfld.long 0x0 21. " DP ,Data present selectThis register indicates that data is present and DAT line shall be used. . It must be set to 0 in the following conditions: . - command using only CMD line . - command with no data transfer but using busy signal on DAT[0] . - Resume command ." "0,1" bitfld.long 0x0 22.--23. " CMD_TYPE ,Command typeThis register specifies three types of special command: Suspend, Resume and Abort. . These bits shall be set to 00b for all other commands. ." "0,1,2,3" textline " " bitfld.long 0x0 24.--29. " INDX ,Command indexBinary encoded value from 0 to 63 specifying the command number send to card ." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x210++0x3 line.long 0x0 "MMCHS_RSP10,Command Response[31:0] Register (bits [31:0] of the internal RSP register) This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6/R7" hexmask.long.word 0x0 0.--15. 1. " RSP0 ,Command Response [15:0]" hexmask.long.word 0x0 16.--31. 1. " RSP1 ,Command Response [31:16]" group.byte 0x214++0x3 line.long 0x0 "MMCHS_RSP32,Command Response[63:32] Register (bits [63:32] of the internal RSP register) This 32-bit register holds bits positions [63:32] of command response type R2" hexmask.long.word 0x0 0.--15. 1. " RSP2 ,Command Response [47:32]" hexmask.long.word 0x0 16.--31. 1. " RSP3 ,Command Response [63:48]" group.byte 0x218++0x3 line.long 0x0 "MMCHS_RSP54,Command Response[95:64] Register (bits [95:64] of the internal RSP register) This 32-bit register holds bits positions [95:64] of command response type R2" hexmask.long.word 0x0 0.--15. 1. " RSP4 ,Command Response [79:64]" hexmask.long.word 0x0 16.--31. 1. " RSP5 ,Command Response [95:80]" group.byte 0x21C++0x3 line.long 0x0 "MMCHS_RSP76,Command Response[127:96] Register (bits [127:96] of the internal RSP register) This 32-bit register holds bits positions [127:96] of command response type R1(Auto CMD23)/R1b(Auto CMD12)/R2" hexmask.long.word 0x0 0.--15. 1. " RSP6 ,Command Response [111:96]" hexmask.long.word 0x0 16.--31. 1. " RSP7 ,Command Response [127:112]" group.byte 0x220++0x3 line.long 0x0 "MMCHS_DATA,Data Register This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bits x256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register or on the most significant byte of the last word of block transfer. Example 1: Byte or 16-bit access Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK Mbyteen[3:0]=0001 (1-byte) => Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad" hexmask.long 0x0 0.--31. 1. " DATA ,Data Register [31:0] In functional mode (MMCHS_CON[MODE] set to the default value 0) , A read access to this register is allowed only when the buffer read enable status is set to 1 (MMCHS_PSTATE[BRE]), otherwise a bad access (MMCHS_STAT[BADA]) is signaled. A write access to this register is allowed only when the buffer write enable status is set to 1(MMCHS_STATE[BWE]), otherwise a bad access (MMCHS_STAT[BADA]) is signaled and the data is not written." group.byte 0x224++0x3 line.long 0x0 "MMCHS_PSTATE,Present State Register The Host can get status of the Host Controller from this 32-bit read only register." bitfld.long 0x0 0. " CMDI ,Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0 in either the following cases: - After the end bit of the command response, excepted if there is a command conflict error (MMCHS_STAT[CCRC] or MMCHS_STAT[CEB] set to 1) or a Auto CMD12 is not executed (MMCHS_AC12[ACNE]). - After the end bit of the command without response (MMCHS_CMD[RSP_TYPE] set to '00') In case of a command data error is detected (MMCHS_STAT[CTO] set to 1), this register is not automatically cleared." "0,1" bitfld.long 0x0 1. " DATI ,Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[DLA]) or Read transfer is active (MMCHS_PSTATE[RTA]) or when a command with busy is issued. This bit prevents the local host to issue a command. A change of this bit from 1 to 0 generates a transfer complete interrupt (MMCHS_STAT[TC])." "0,1" textline " " bitfld.long 0x0 2. " DLA ,DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue request MMCHS_HCTL[CR]. This bit is set to 0 when the host controller received the end bit of the last data block or at the beginning of the read wait mode. In the case of write transactions (host to card): This bit is set to 1 after the end bit of write command or by activating continue request MMCHS_HCTL[CR]. This bit is set to 0 on the end of busy event for the last block; host controller must wait 8 clock cycles with line not busy to really consider not 'busy state' or after the busy block as a result of a stop at gap request." "0,1" bitfld.long 0x0 3. " RTR ,Re-Tuning Request Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data. This bit is cleared when a command is issued with setting MMCHS_AC12[22] ET. This bit isn't set to 1 if MMCHS_AC12[23] SCLK_SEL is set to 0 (using fixed sampling clock). Refer to MMCHS_CAPA2[15:14] RTM for more detail." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " WTA ,Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[CR]) following a stop at block gap request. This bit is set to 0 when CRC status has been received after last block or after a stop at block gap request." "0,1" textline " " bitfld.long 0x0 9. " RTA ,Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[CR]) following a stop at block gap request. This bit is set to 0 when all data have been read by the local host after last block or after a stop at block gap request." "0,1" bitfld.long 0x0 10. " BWE ,Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data." "0,1" textline " " bitfld.long 0x0 11. " BRE ,Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[BLEN] has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from the buffer. It is set to 1 when a block data is ready in the buffer and generates the Buffer read ready status of interrupt (MMCHS_STAT[BRR])." "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " CINS ,Card inserted This bit is the debounced value of the card detect input pin (mmci_sdcd). An inactive to active transition of the card detect input pin (mmci_sdcd) will generate a card insertion interrupt (MMCHS_STAT[CINS]). A active to inactive transition of the card detect input pin (mmci_sdcd) will generate a card removal interrupt (MMCHS_STAT[REM]). This bit is not affected by a software reset." "0,1" bitfld.long 0x0 17. " CSS ,Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[CDPL]). Debouncing is performed on the card detect input pin (mmci_sdcd) to detect card stability. This bit is not affected by a software reset." "0,1" textline " " bitfld.long 0x0 18. " CDPL ,Card detect pin level This bit reflects the inverse value of the card detect input pin (mmci_sdcd), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTAE[CSS]) is set to 1. Use of this bit is limited to testing since it must be debounced y software. The value of this register after reset depends on the card detect input pin (mmci_sdcd) level at that time." "0,1" bitfld.long 0x0 19. " WP ,Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (mmci_sdwp) level. The value of this register after reset depends on the protect input pin (mmci_sdwp) level at that time." "0,1" textline " " bitfld.long 0x0 20.--23. " DLEV ,DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. The value of these registers after reset depends on the DAT lines level at that time." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " CLEV ,CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time." "0,1" textline " " hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x228++0x3 line.long 0x0 "MMCHS_HCTL,Host Control Register This register defines the host controls to set power, wakeup and transfer parameters. [31:24] = Wakeup control [23:16] = Block gap control [15:8] = Power control [7:0] = Host control" bitfld.long 0x0 0. " LED ,Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored." "0,1" bitfld.long 0x0 1. " DTW ,Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliance with MMC standard specification 4.x (see section 3.6). This register has no effect when the MMC 8-bit mode is selected (register MMCHS_CON[DW8] set to1 ), For SD/SDIO cards, this bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument. Prior to this command, the SD card configuration register (SCR) must be verified for the supported bus width by the SD card." "0,1" textline " " bitfld.long 0x0 2. " HSPE ,Before setting this bit, the Host Driver shall check theMMCHS_CAPA[21] HSS. This bit shall not be set when dual data rate mode is activated in MMCHS_CON[DDR]." "0,1" bitfld.long 0x0 3.--4. " DMAS ,DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register MMCHS_CAPA . Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This register is only meaningful when MADMA_EN is set to 1. When MADMA_EN is set to 0 the bit field is read only and returned value is 0." "0,1,2,3" textline " " bitfld.long 0x0 5. " RESERVED ," "0,1" bitfld.long 0x0 6. " CDTL ,Card Detect Test Level: This bit is enabled while MMCHS_HCTL[7] CDSS is set to 1 and it indicates whether the card is inserted or not." "0,1" textline " " bitfld.long 0x0 7. " CDSS ,Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in order to mask unexpected interrupts caused by the glitch. The Interrupt Status/Signal Enable should be disabled during over the period of debouncing." "0,1" bitfld.long 0x0 8. " SDBP ,SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[SDVS]). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in the command register (MMCHS_CMD) will not start the transfer. A write to this bit has no effect if the selected SD bus voltage MMCHS_HCTL[SDVS] is not supported according to capability register (MMCHS_CAPA[VS*])." "0,1" textline " " bitfld.long 0x0 9.--11. " SDVS ,SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[VS18,VS30,VS33]) before starting a transfer." "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16. " SBGR ,Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[CR]) or during a suspend/resume sequence. In case of read transfer, the card must support read wait control. In case of write transfer, the host driver shall set this bit after all block data written. Until the transfer completion (MMCHS_STAT[TC] set to 1), the host driver shall leave this bit set to 1. If this bit is set, the local host shall not write to the data register (MMCHS_DATA)." "0,1" bitfld.long 0x0 17. " CR ,Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[SBGR]). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when transfer has restarted i.e DAT line is active (MMCHS_PSTATE[DLA]) or transferring data (MMCHS_PSTATE[WTA]). The Stop at block gap request must be disabled (MMCHS_HCTL[SBGR]=0) before setting this bit." "0,1" textline " " bitfld.long 0x0 18. " RWC ,Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[SBGR]) generates a read wait period after the current end of block. Be careful, if read wait is not supported it may cause a conflict on DAT line." "0,1" bitfld.long 0x0 19. " IBG ,Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be set to 0." "0,1" textline " " bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 24. " IWE ,Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" textline " " bitfld.long 0x0 25. " INS ,Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" bitfld.long 0x0 26. " REM ,Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP])." "0,1" textline " " bitfld.long 0x0 27. " OBWE ,Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[ENAWAKEUP]). The write to this register is ignored when MMCHS_CON[OBIE] is not set." "0,1" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x22C++0x3 line.long 0x0 "MMCHS_SYSCTL,SD System Control Register This register defines the system controls to set software resets, clock frequency management and data timeout. [31:24] = Software resets [23:16] = Timeout control [15:0] = Clock control" bitfld.long 0x0 0. " ICE ,Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface clock (used for reads and writes to the module register map) are not affected by this register." "0,1" bitfld.long 0x0 1. " ICS ,Internal clock stable (status) This bit indicates either the internal clock is stable or not." "0,1" textline " " bitfld.long 0x0 2. " CEN ,Clock enable This bit controls if the clock is provided to the card or not." "0,1" bitfld.long 0x0 3.--4. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 5. " CGS ,Clock Generator Select - For SD cards Host Controller Version 3.00 supports this bit. This bit is used to select the clock generator mode in MMCHS_SYSCTL[15:6] CLKD. If the Programmable Clock Mode is supported (non-zero value is set to MMCHS_CAPA2[23:16] CM), this bit attribute is RW, and if not supported, this bit attribute is RO and zero is read. This bit depends on the setting of MMCHS_AC12[31] PV_ENABLE. If PV_ENABLE = 0, this bit is set by Host Driver. If PV_ENABLE = 1, this bit is automatically set to a value specified in one of Preset Value registers, see, ." "0,1" hexmask.long.word 0x0 6.--15. 1. " CLKD ,Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO)." textline " " bitfld.long 0x0 16.--19. " DTO ,Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bitfield based on - the maximum read access time (NAC) (Refer to the SD Specification Part1 Physical Layer), - the data read access time values (TAAC and NSAC) in the card specific data register (CSD) of the card, - the timeout clock base frequency (MMCHS_CAPA[TCF]). If the card does not respond within the specified number of cycles, a data timeout error occurs (MMCHS_STA[DTO]). The MMCHS_SYSCTL[DTO] register is also used to check busy duration, to generate busy timeout for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24. " SRA ,Software reset for all This bit is set to 1 for reset , and released to 0 when completed. This reset affects the entire host controller except for the capabilities registers (MMCHS_CAPA and MMCHS_CUR_CAPA)." "0,1" bitfld.long 0x0 25. " SRC ,Software reset for CMD line For more information about SRC bit manipulation, see CMD Line Reset Procedure. This bit is set to 1 for reset and released to 0 when completed. CMD finite state machine in both clock domain are also reset. Here below the registers cleared by MMCHS_SYSCTL[SRC]: - MMCHS_PSTATE: CMDI - MMCHS_STAT: CC Interconnect and MMC command status management is reinitialized." "0,1" textline " " bitfld.long 0x0 26. " SRD ,Software reset for DAT line This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see DATA Lines Reset Procedure. DAT finite state machine in both clock domain are also reset. Here below are the registers cleared by MMCHS_SYSCTL[SRD]: - MMCHS_DATA - MMCHS_PSTATE: BRE, BWE, RTA, WTA, DLA and DATI - MMCHS_HCTL: SBGR and CR - MMCHS_STAT: BRR, BWR, BGE and TC Interconnect and MMC buffer data management is reinitialized." "0,1" bitfld.long 0x0 27.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x230++0x3 line.long 0x0 "MMCHS_STAT,Interrupt Status Register The interrupt status regroups all the status of the module internal events that can generate an interrupt. [31:16] = Error Interrupt Status [15:0] = Normal Interrupt Status" bitfld.long 0x0 0. " CC ,Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[CMDI]) If the command is a type for which no response is expected, then the command complete interrupt is generated at the end of the command. A command timeout error (MMCHS_STAT[CTO]) has higher priority than command complete (MMCHS_STAT[CC]). If a response is expected but none is received, then a command timeout error is detected and signaled instead of the command complete interrupt." "0,1" bitfld.long 0x0 1. " TC ,Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[SBGR]). In Read mode: This bit is automatically set on completion of a read transfer (MMCHS_PSTATE[RTA]). In write mode: This bit is set automatically on completion of the DAT line use (MMCHS_PSTATE[DLA])." "0,1" textline " " bitfld.long 0x0 2. " BGE ,Block gap event When a stop at block gap is requested (MMCHS_HCTL[SBGR]), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap is requested on the last block. In read mode, a 1-to-0 transition of the DAT Line active status (MMCHS_PSTATE[DLA]) between data blocks generates a Block gap event interrupt." "0,1" bitfld.long 0x0 3. " DMA ,DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion." "0,1" textline " " bitfld.long 0x0 4. " BWR ,Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[BLEN]. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer. Note: If the DMA transmit mode is enabled, this bit is never set; instead, a DMA transmit request to the main DMA controller of the system is generated." "0,1" bitfld.long 0x0 5. " BRR ,Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[BLEN] is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by reading it. Note: If the DMA receive-mode is enabled, this bit is never set; instead a DMA receive request to the main DMA controller of the system is generated." "0,1" textline " " bitfld.long 0x0 6. " CINS ,Card insertion This bit is set automatically when MMCHS_PSTATE[CINS] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[CINS])." "0,1" bitfld.long 0x0 7. " CREM ,Card removal This bit is set automatically when MMCHS_PSTATE[CINS] changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[CINS])." "0,1" textline " " bitfld.long 0x0 8. " CIRQ ,Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drives CMD line to zero during one cycle after data transmission end.All modes above are fully exclusive. The controller interrupt must be clear by setting MMCHS_IE[CIRQ] to 0, then the host driver must start the interrupt service with card (clearing card interrupt status) to remove card interrupt source. Otherwise the Controller interrupt will be reasserted as soon as MMCHS_IE[CIRQ] is set to 1. Writes to this bit are ignored." "0,1" bitfld.long 0x0 9. " OBI ,Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[OBIE] is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[OBIP]. This interrupt is only useful for MMC card. The Out-of-Band interrupt signal is a system specific feature for future use, this signal is not required for existing specification implementation." "0,1" textline " " bitfld.long 0x0 10. " BSR ,Boot status received interrupt This bit is set automatically when MMCHS_CON[BOOT] is set 0x1 or 0x2 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " ERRI ,Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[31:16]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored." "0,1" bitfld.long 0x0 16. " CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles." "0,1" textline " " bitfld.long 0x0 17. " CCRC ,Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[CCCE] register." "0,1" bitfld.long 0x0 18. " CEB ,Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response." "0,1" textline " " bitfld.long 0x0 19. " CIE ,Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[CICE] register." "0,1" bitfld.long 0x0 20. " DTO ,Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout" "0,1" textline " " bitfld.long 0x0 21. " DCRC ,Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command." "0,1" bitfld.long 0x0 22. " DEB ,Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode." "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE ,Auto CMD error Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register (MMCHS_AC12) has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to the previous command error." "0,1" textline " " bitfld.long 0x0 25. " ADMAE ,ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller generates this interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state. The Host Driver may find that Valid bit is not set at the error descriptor." "0,1" bitfld.long 0x0 26. " TE ,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure (Occurrence of an error during tuning procedure is indicated by Sampling Select). By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. To reset tuning circuit, Sampling Clock shall be set to 0 before executing tuning procedure. The Tuning Error is higher priority than the other error interrupts generated during data transfer. By detecting Tuning Error, the Host Driver should discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from tuning circuit error. The bit is set if the lock is lost (but not during the tuning process) or if the lock counter expires without the lock being asserted. If the latter happens, the SW can decide to ignore the interrupt and wait some more for the lock to be set." "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR ,Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error MMCHS_CSRE in set. There is no card error detection for autoCMD12 command. The host driver shall read MMCHS_RSP76 register to detect error bits in the command response." "0,1" textline " " bitfld.long 0x0 29. " BADA ,Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[BRE] =0) -This bit is set during a write access to the data register (MMCHS_DATA) while buffer writes are not allowed (MMCHS_STATE[BWE] =0)" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x234++0x3 line.long 0x0 "MMCHS_IE,Interrupt Status Enable Register This register allows to enable/disable the module to set status bits, on an event-by-event basis. [31:16] = Error Interrupt Status Enable [15:0] = Normal Interrupt Status Enable" bitfld.long 0x0 0. " CC_ENABLE ,Command Complete Status Enable" "0,1" bitfld.long 0x0 1. " TC_ENABLE ,Transfer Complete Status Enable" "0,1" textline " " bitfld.long 0x0 2. " BGE_ENABLE ,Block Gap Event Status Enable" "0,1" bitfld.long 0x0 3. " DMA_ENABLE ,DMA Status Enable" "0,1" textline " " bitfld.long 0x0 4. " BWR_ENABLE ,Buffer Write Ready Status Enable" "0,1" bitfld.long 0x0 5. " BRR_ENABLE ,Buffer Read Ready Status Enable" "0,1" textline " " bitfld.long 0x0 6. " CINS_ENABLE ,Card Insertion Status Enable" "0,1" bitfld.long 0x0 7. " CREM_ENABLE ,Card Removal Status Enable" "0,1" textline " " bitfld.long 0x0 8. " CIRQ_ENABLE ,Card Status Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1." "0,1" bitfld.long 0x0 9. " OBI_ENABLE ,Out-of-Band Status Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored." "0,1" textline " " bitfld.long 0x0 10. " BSR_ENABLE ,Boot Status Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x0 16. " CTO_ENABLE ,Command Timeout Error Status Enable" "0,1" textline " " bitfld.long 0x0 17. " CCRC_ENABLE ,Command CRC Error Status Enable" "0,1" bitfld.long 0x0 18. " CEB_ENABLE ,Command End Bit Error Status Enable" "0,1" textline " " bitfld.long 0x0 19. " CIE_ENABLE ,Command Index Error Status Enable" "0,1" bitfld.long 0x0 20. " DTO_ENABLE ,Data Timeout Error Status Enable" "0,1" textline " " bitfld.long 0x0 21. " DCRC_ENABLE ,Data CRC Error Status Enable" "0,1" bitfld.long 0x0 22. " DEB_ENABLE ,Data End Bit Error Status Enable" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE_ENABLE ,Auto CMD Error Status Enable" "0,1" textline " " bitfld.long 0x0 25. " ADMAE_ENABLE ,ADMA Error Status Enable" "0,1" bitfld.long 0x0 26. " TE_ENABLE ,Tuning Error Status Enable" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR_ENABLE ,Card Error Status Enable" "0,1" textline " " bitfld.long 0x0 29. " BADA_ENABLE ,Bad access to data space Status Enable" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x238++0x3 line.long 0x0 "MMCHS_ISE,Interrupt Signal Enable Register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. [31:16] = Error Interrupt Signal Enable [15:0] = Normal Interrupt Signal Enable" bitfld.long 0x0 0. " CC_SIGEN ,Command Complete Status Enable" "0,1" bitfld.long 0x0 1. " TC_SIGEN ,Transfer Completed Status Enable" "0,1" textline " " bitfld.long 0x0 2. " BGE_SIGEN ,Black Gap Event Signal Enable" "0,1" bitfld.long 0x0 3. " DMA_SIGEN ,DMA Interrupt Signal Enable" "0,1" textline " " bitfld.long 0x0 4. " BWR_SIGEN ,Buffer Write Ready Signal Enable" "0,1" bitfld.long 0x0 5. " BRR_SIGEN ,Buffer Read Ready Signal Enable" "0,1" textline " " bitfld.long 0x0 6. " CINS_SIGEN ,Card Insertion Signal Enable" "0,1" bitfld.long 0x0 7. " CREM_SIGEN ,Card Removal Signal Enable" "0,1" textline " " bitfld.long 0x0 8. " CIRQ_SIGEN ,Card Interrupt Signal Enable" "0,1" bitfld.long 0x0 9. " OBI_SIGEN ,Out-Of-Band Interrupt Signal Enable A write to this register when MMCHS_CON[OBIE] is set to '0' is ignored." "0,1" textline " " bitfld.long 0x0 10. " BSR_SIGEN ,Boot Status Signal Enable A write to this register when MMCHS_CON[BOOT_ACK] is set to 0x0 is ignored." "0,1" bitfld.long 0x0 11.--14. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 15. " NULL ,Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored" "0,1" bitfld.long 0x0 16. " CTO_SIGEN ,Command timeout Error Signal Enable" "0,1" textline " " bitfld.long 0x0 17. " CCRC_SIGEN ,Command CRC Error Signal Enable" "0,1" bitfld.long 0x0 18. " CEB_SIGEN ,Command End Bit Error Signal Enable" "0,1" textline " " bitfld.long 0x0 19. " CIE_SIGEN ,Command Index Error Signal Enable" "0,1" bitfld.long 0x0 20. " DTO_SIGEN ,Data Timeout Error Signal Enable" "0,1" textline " " bitfld.long 0x0 21. " DCRC_SIGEN ,Data CRC Error Signal Enable" "0,1" bitfld.long 0x0 22. " DEB_SIGEN ,Data End Bit Error Signal Enable" "0,1" textline " " bitfld.long 0x0 23. " RESERVED ," "0,1" bitfld.long 0x0 24. " ACE_SIGEN ,Auto CMD Error Signal Enable" "0,1" textline " " bitfld.long 0x0 25. " ADMAE_SIGEN ,ADMA Error Signal Enable" "0,1" bitfld.long 0x0 26. " TE_SIGEN ,Tuning Error Signal Enable" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " CERR_SIGEN ,Card Error Interrupt Signal Enable" "0,1" textline " " bitfld.long 0x0 29. " BADA_SIGEN ,Bad access to data space Signal Enable" "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x23C++0x3 line.long 0x0 "MMCHS_AC12,Host Control 2 Register and Auto CMD Error Status Register This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23. The Host driver can determine what kind of Auto CMD12 / CMD23 errors occur by this register. Auto CMD23 errors are indicated only in bits[4:1]. Bits[7:0] are valid only when the [3:2] ACEN bitfield is configured to enable Auto CMD and the Auto CMD Error bit ([24]ACE) is set." bitfld.long 0x0 0. " ACNE ,Auto CMD12 Not Executed If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the Host Controller cannot issue Auto CMD12 to stop memory multiple block data transfer due to some error. If this bit is set to 1, other error status bits (D04-D01) are meaningless. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" bitfld.long 0x0 1. " ACTO ,Auto CMD Timeout Error - For Auto CMD12 and Auto CMD23 This bit is set if no response is returned within 64 SDCLK cycles from the end bit of command. If this bit is set to1, the other error status bits (D04-D02) are meaningless." "0,1" textline " " bitfld.long 0x0 2. " ACCE ,Auto CMD CRC Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting a CRC error in the command response." "0,1" bitfld.long 0x0 3. " ACEB ,Auto CMD End Bit Error - For Auto CMD12 and Auto CMD23 This bit is set when detecting that the end bit of command response is 0." "0,1" textline " " bitfld.long 0x0 4. " ACIE ,Auto CMD Index Error - For Auto CMD12 and Auto CMD23 This bit is set if the Command Index error occurs in response to a command." "0,1" bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 7. " CNI ,Command Not Issued By Auto CMD12 Error Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23." "0,1" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16.--18. " UHSMS ,UHS Mode Select This field is used to select one of UHS-I modes or eMMC HS200 mode and is effective when 1.8V Signaling Enable is set to 1. If MMCHS_AC12[31] PV_ENABLE is set to 1, Host Controller sets MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL according to Preset Value registers, see, . In this case, one of preset value registers is selected by this field. Host Driver needs to reset MMCHS_SYSCTL[2] CEN before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets MMCHS_SYSCTL[2] CEN again. When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more detail." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19. " V1V8_SIGEN ,1.8V Signaling Enable This bit controls voltage regulator for I/O cell. 3.3V is supplied to the card regardless of signaling voltage. Setting this bit from 0 to 1 starts changing signal voltage from 3.3V to 1.8V. 1.8V regulator output shall be stable within 5ms. Host Controller clears this bit if switching to 1.8V signaling fails. Clearing this bit from 1 to 0 starts changing signal voltage from 1.8V to 3.3V. 3.3V regulator output shall be stable within 5ms. Host Driver can set this bit to 1 when Host Controller supports 1.8V signaling (One of support bits is set to 1: SDR50, SDR104 or DDR50 in MMCHS_CAPA2 register) and the card or device supports UHS-I (S18A=1. Refer to Bus Signal Voltage Switch Sequence in the Physical Layer Specification Version 3.0x)." "0,1" textline " " bitfld.long 0x0 20.--21. " DS_SEL ,Driver Strength Select Host Controller output driver in 1.8V signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can be set depending on Driver Type A, C and D support bits (DTA, DTC and DTD respectively) in the MMCHS_CAPA2 register. This bit depends on setting of Preset Value Enable. If Preset Value Enable = 0, this field is set by Host Driver. If Preset Value Enable = 1, this field is automatically set by a value specified in the one of Preset Value registers, see, ." "0,1,2,3" bitfld.long 0x0 22. " ET ,Execute Tuning This bit is set to 1 to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to MMCHS_AC12[23] SCLK_SEL. Tuning procedure is aborted by writing 0. This is Read-Write with automatic clear register" "0,1" textline " " bitfld.long 0x0 23. " SCLK_SEL ,Sampling Clock Select Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is set by tuning procedure and valid after the completion of tuning (when MMCHS_AC12[22] ET is cleared). Setting 1 means that tuning is completed successfully and setting 0 means that tuning is failed. Writing 1 to this bit is meaningless and ignored. A tuning circuit is reset by writing to 0. This bit can be cleared with setting MMCHS_AC12[22] ET. Once the tuning circuit is reset, it will take time to complete tuning sequence. Therefore, Host Driver should keep this bit to 1 to perform re-tuning sequence to compete re-tuning sequence in a short time. Change of this bit is not allowed while the Host Controller is receiving response or a read data block." "0,1" bitfld.long 0x0 24.--29. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 30. " AI_ENABLE ,Asynchronous Interrupt Enable This bit can be set to 1 if a card supports asynchronous interrupts and MMCHS_CAPA[29] AIS is set to 1. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver the Card Interrupt to the host when it is asserted by the Card." "0,1" bitfld.long 0x0 31. " PV_ENABLE ,Preset Value Enable Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When Preset Value Enable is set, automatic SDCLK frequency generation and driver strength selection is performed without considering system specific conditions. This bit enables the functions defined in the Preset Value registers, see, . If this bit is set to 0, MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL are set by Host Driver. If this bit is set to 1, MMCHS_SYSCTL[15:6] CLKD, MMCHS_SYSCTL[5] CGS and MMCHS_AC12[21:20] DS_SEL are set by Host Controller as specified in the Preset Value registers, see, ." "0,1" group.byte 0x240++0x3 line.long 0x0 "MMCHS_CAPA,Capabilities Register This register lists the capabilities of the MMC/SD/SDIO host controller." bitfld.long 0x0 0.--5. " TCF ,Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[DTO])." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " RESERVED ," "0,1" textline " " bitfld.long 0x0 7. " TCU ,Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[DTO])." "0,1" hexmask.long.byte 0x0 8.--15. 1. " BCF ,Base Clock Frequency For SD Clock This value indicates the base (maximum) clock frequency for the SD Clock. 8-bit Base Clock Frequency This mode is supported by the Host Controller Version 3.00. Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh : 255MHz .... : ....... 02h : 2MHz 01h : 1MHz 00h : Get information via another method If the real frequency is 16.5MHz, the lager value shall be set 0001 0001b (17MHz) because the Host Driver use this value to calculate the clock divider value (Refer to MMCHS_SYSCTL[15:6] CLKD) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method." textline " " bitfld.long 0x0 16.--17. " MBL ,Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 bytes. The host controller supports 512 bytes and 1024 bytes block transfers." "0,1,2,3" bitfld.long 0x0 18. " RESERVED ," "0,1" textline " " bitfld.long 0x0 19. " AD2S ,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2. It depends on setting of generic parameter MADMA_EN" "0,1" bitfld.long 0x0 20. " RESERVED ," "0,1" textline " " bitfld.long 0x0 21. " HSS ,High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency." "0,1" bitfld.long 0x0 22. " DS ,DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly." "0,1" textline " " bitfld.long 0x0 23. " SRS ,Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports Suspend/Resume functionality." "0,1" bitfld.long 0x0 24. " VS33 ,Voltage support 3.3V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" textline " " bitfld.long 0x0 25. " VS30 ,Voltage support 3.0V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" bitfld.long 0x0 26. " VS18 ,Voltage support 1.8V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" "0,1" textline " " bitfld.long 0x0 27. " RESERVED ," "0,1" bitfld.long 0x0 28. " BIT64 ,64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus." "0,1" textline " " bitfld.long 0x0 29. " AIS ,Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt." "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x244++0x3 line.long 0x0 "MMCHS_CAPA2,Capabilities 2 Register This register provides the Host Driver with information specific to the Host Controller implementation. The Host Controller may implement these values as fixed or loaded from flash memory during power on initialization. Refer to Software Reset For All in the Software Reset register for loading from flash memory and completion timing control." bitfld.long 0x0 0. " SDR50 ,SDR50 Support If SDR104 is supported, this bit shall be set to 1. Bit 13 indicates whether SDR50 requires tuning or not." "0,1" bitfld.long 0x0 1. " SDR104 ,SDR104 Support SDR104 requires tuning." "0,1" textline " " bitfld.long 0x0 2. " DDR50 ,DDR50 Support" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " DTA ,Driver Type A Support This bit indicates support of Driver Type A for 1.8 Signaling." "0,1" bitfld.long 0x0 5. " DTC ,Driver Type C Support This bit indicates support of Driver Type C for 1.8 Signaling." "0,1" textline " " bitfld.long 0x0 6. " DTD ,Driver Type D Support This bit indicates support of Driver Type D for 1.8 Signaling." "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8.--11. " TCRT ,Timer Count for Re-Tuning This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 0 disables Re-Tuning Timer." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12. " RESERVED ," "0,1" textline " " bitfld.long 0x0 13. " TSDR50 ,Use Tuning for SDR50 If this bit is set to 1, this Host Controller requires tuning to operate SDR50. (Tuning is always required to operate SDR104.)" "0,1" bitfld.long 0x0 14.--15. " RTM ,Re-Tuning Modes This field selects re-tuning method and limits the maximum data length." "0,1,2,3" textline " " hexmask.long.byte 0x0 16.--23. 1. " CM ,Clock Multiplier This field indicates clock multiplier value of programmable clock generator. Refer to MMCHS_SYSCTL [15:0]. Setting 00h means that Host Controller does not support programmable clock generator. 00h : Clock Multiplier is Not Supported 01h : Clock Multiplier M = 2 02h : Clock Multiplier M = 3 .... : ...................... FFh : Clock Multiplier M = 256" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x248++0x3 line.long 0x0 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (). Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" hexmask.long.byte 0x0 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V" hexmask.long.byte 0x0 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V" textline " " hexmask.long.byte 0x0 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V" hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x250++0x3 line.long 0x0 "MMCHS_FE,Force Event Register for Auto CMD Error Status and Error Interrupt status The Force Event Register is not a physically implemented register. Rather, it is an address at which the Auto CMD Error Status Register () can be written. Writing 1 : set each bit of the Auto CMD Error Status Register Writing 0 : no effect Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register if the corresponding bit of the Error Interrupt Status Enable Register is set. Writing 1 : set each bit of the Error Interrupt Status Register Writing 0 : no effect Note: By setting this register, the Error Interrupt can be set in the Error Interrupt Status register. In order to generate interrupt signal, both the Error Interrupt Status Enable and Error Interrupt Signal Enable shall be set." bitfld.long 0x0 0. " FE_ACNE ,Force Event Auto CMD12 Not Executed" "0,1" bitfld.long 0x0 1. " FE_ACTO ,Force Event Auto CMD Timeout Error" "0,1" textline " " bitfld.long 0x0 2. " FE_ACCE ,Force Event Auto CMD CRC Error" "0,1" bitfld.long 0x0 3. " FE_ACEB ,Force Event Auto CMD End Bit Error" "0,1" textline " " bitfld.long 0x0 4. " FE_ACIE ,Force Event for Auto CMD Index Error - For Auto CMD12 and Auto CMD23" "0,1" bitfld.long 0x0 5.--6. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 7. " FE_CNI ,Force Event Command not issue by Auto CMD12 error" "0,1" hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " FE_CTO ,Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles." "0,1" bitfld.long 0x0 17. " FE_CCRC ,Force Event Command CRC Error." "0,1" textline " " bitfld.long 0x0 18. " FE_CEB ,Force Event Command End Bit Error." "0,1" bitfld.long 0x0 19. " FE_CIE ,Force Event Command Index Error." "0,1" textline " " bitfld.long 0x0 20. " FE_DTO ,Force Event Data Timeout Error." "0,1" bitfld.long 0x0 21. " FE_DCRC ,Force Event Data CRC Error." "0,1" textline " " bitfld.long 0x0 22. " FE_DEB ,Force Event Data End Bit error." "0,1" bitfld.long 0x0 23. " RESERVED ," "0,1" textline " " bitfld.long 0x0 24. " FE_ACE ,Force Event for Auto CMD Error - For Auto CMD12 and Auto CMD23" "0,1" bitfld.long 0x0 25. " FE_ADMAE ,Force Event ADMA Error." "0,1" textline " " bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" bitfld.long 0x0 28. " FE_CERR ,Force Event Card error." "0,1" textline " " bitfld.long 0x0 29. " FE_BADA ,Force Event Bad access to data space." "0,1" bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x254++0x3 line.long 0x0 "MMCHS_ADMAES,ADMA Error Status Register When ADMA Error Interrupt is occurred, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. For recovering the error, the Host Driver requires the ADMA state to identify the error descriptor address as follows: ST_STOP: Previous location set in the ADMA System Address register is the error descriptor address ST_FDS: Current location set in the ADMA System Address register is the error descriptor address ST_CADR: This sate is never set because do not generate ADMA error in this state. ST_TFR: Previous location set in the ADMA System Address register is the error descriptor address In case of write operation, the Host Driver should use ACMD22 to get the number of written block rather than using this information, since unwritten data may exist in the Host Controller. The Host Controller generates the ADMA Error Interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. In this case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host Driver may find that the Valid bit is not set in the error descriptor." bitfld.long 0x0 0.--1. " AES ,ADMA Error StateThis field indicates the state of ADMA when error occurred during ADMA data transfer. This field will never be 0x2 because ADMA never stops in that state.0x0: ST_STOP (STOP_ADMA). Previous SYS_ADR is the error descriptor address0x1: ST_FDS (Fetch Descriptor). Content of current SYS_ADR is the error descriptor address0x2: Not used. Error never set in this state0x3: ST_TFR (Transfer Data). Previous SYS_ADR is the error descriptor address" "0,1,2,3" bitfld.long 0x0 2. " LME ,ADMA Length Mismatch Error: (1) While Block Count Enable being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. (2) Total data length can not be divided by the block length." "0,1" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x258++0x3 line.long 0x0 "MMCHS_ADMASAL,ADMA System address Low bits" hexmask.long 0x0 0.--31. 1. " ADMA_A32B ,ADMA System address 32 bits.This register holds byte address of executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32-bit of this register. At the start of ADMA, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold valid Descriptor address depending on the ADMA state. The Host Driver shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. ADMA2 ignores lower 2-bit of this register and assumes it to be 00b." group.byte 0x260++0x3 line.long 0x0 "MMCHS_PVINITSD,Preset Value for Initialization and Default Speed modes" hexmask.long.word 0x0 0.--9. 1. " INITSDCLK_SEL ,SDCLK Frequency Select Value - Initialization mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " INITCLKGEN_SEL ,Clock Generator Select Value - Initialization mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " INITDS_SEL ,Driver Strength Select Value - Initialization mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " DSSDCLK_SEL ,SDCLK Frequency Select Value - Default Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " DSCLKGEN_SEL ,Clock Generator Select Value - Default Speed mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " DSDS_SEL ,Driver Strength Select Value - Default Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x264++0x3 line.long 0x0 "MMCHS_PVHSSDR12,Preset Value for High Speed and SDR12 speed modes" hexmask.long.word 0x0 0.--9. 1. " HSSDCLK_SEL ,SDCLK Frequency Select Value - High Speed mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " HSCLKGEN_SEL ,Clock Generator Select Value - High Speed mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " HSDS_SEL ,Driver Strength Select Value - High Speed mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " SDR12SDCLK_SEL ,SDCLK Frequency Select Value - SDR12 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " SDR12CLKGEN_SEL ,Clock Generator Select Value - SDR12 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SDR12DS_SEL ,Driver Strength Select Value - SDR12 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x268++0x3 line.long 0x0 "MMCHS_PVSDR25SDR50,Preset Value for SDR25 and SDR50 speed modes" hexmask.long.word 0x0 0.--9. 1. " SDR25SDCLK_SEL ,SDCLK Frequency Select Value - SDR25 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " SDR25CLKGEN_SEL ,Clock Generator Select Value - SDR25 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " SDR25DS_SEL ,Driver Strength Select Value - SDR25 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " SDR50SDCLK_SEL ,SDCLK Frequency Select Value - SDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " SDR50CLKGEN_SEL ,Clock Generator Select Value - SDR50 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " SDR50DS_SEL ,Driver Strength Select Value - SDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x26C++0x3 line.long 0x0 "MMCHS_PVSDR104DDR50,Preset Value for SDR104 and DDR50 speed modes" hexmask.long.word 0x0 0.--9. 1. " SDR104SDCLK_SEL ,SDCLK Frequency Select Value - SDR104 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 10. " SDR104CLKGEN_SEL ,Clock Generator Select Value - SDR104 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 11.--13. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 14.--15. " SDR104DS_SEL ,Driver Strength Select Value - SDR104 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" textline " " hexmask.long.word 0x0 16.--25. 1. " DDR50SDCLK_SEL ,SDCLK Frequency Select Value - DDR50 mode 10-bit preset value to set MMCHS_SYSCTL[15:6] CLKD is described by a host system." bitfld.long 0x0 26. " DDR50CLKGEN_SEL ,Clock Generator Select Value - DDR50 mode This bit is effective when Host Controller supports programmable clock generator." "0,1" textline " " bitfld.long 0x0 27.--29. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 30.--31. " DDR50DS_SEL ,Driver Strength Select Value - DDR50 mode Driver Strength is supported by 1.8V signaling bus speed modes. This field is meaningless for 3.3V signaling." "0,1,2,3" group.byte 0x2FC++0x3 line.long 0x0 "MMCHS_REV,Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. [31:16] = Host controller version [15:0] = Slot Interrupt Status" bitfld.long 0x0 0. " SIS ,Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_HCTL[SRA]), the interrupt signal shall be de-asserted and this status shall read 0." "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " SREV ,Specification Version Number This status indicates the Host Controller Spec. Version. The upper and lower 4-bits indicate the version." hexmask.long.byte 0x0 24.--31. 1. " VREV ,Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1" width 0x0B tree.end tree "DPLLCTRL_USB_OTG_SS" base ad:0x4A084C00 width 24. group.byte 0x4++0x3 line.long 0x0 "PLL_STATUS,This register contains the status information" bitfld.long 0x0 0. " PLLCTRL_RESET_DONE ,PLLCTRL reset done status" "0,1" bitfld.long 0x0 1. " PLL_LOCK ,PLL Lock status See the programming guide for the use of this bit" "0,1" textline " " bitfld.long 0x0 2. " PLL_RECAL ,PLL re-calibration status If this bit is active, the PLL needs to be re-calibrated" "0,1" bitfld.long 0x0 3. " PLL_LOSSREF ,PLL Reference Loss status" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 5. " PLL_HIGHJITTER ,PLL High Jitter status" "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledge" "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ," "0,1,2,3" bitfld.long 0x0 15. " PLL_LDOPWDN ,PLL LDOPWDN status." "0,1" textline " " bitfld.long 0x0 16. " PLL_TICOPWDN ,PLL TICOPWDN status." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PLL_GO,This register contains the GO bit" bitfld.long 0x0 0. " PLL_GO ,Request (re-)locking sequence of the PLL." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return zero." group.byte 0xC++0x3 line.long 0x0 "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0 0. " RESERVED ,Read returns zero." "0,1" hexmask.long.byte 0x0 1.--8. 1. " PLL_REGN ,N Divider for PLL (Reference)" textline " " hexmask.long.word 0x0 9.--20. 1. " PLL_REGM ,M Divider for PLL" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0 0. " PLL_IDLE ,PLL IDLE:" "0,1" bitfld.long 0x0 1.--3. " PLL_SELFREQDCO ,DCO frequency range selector for DPLL_USB_OTG_SS / DPLLCTRL_SATA 0x2 Set if DCO frequency is between 750MHz and 1500MHz 0x4 Set if DCO frequency is between 1250MHz and 2500MHz Other values: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the PLLOther values: Reserved enum=SPARE ." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," hexmask.long.byte 0x0 10.--17. 1. " PLL_SD ,Sigma delta divider setting for DPLL_USB_OTG_SS based on the PLL lock configuration." textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x0 0. " EN_SSC ,Spread Spectrum Clocking enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION2,PLL_SSC_CONFIGURATION2" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAM ,DeltaM control for SSC." hexmask.long.word 0x0 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider control for SSC." textline " " bitfld.long 0x0 30. " DELTAM2 ,MSB of DeltaM control bus." "0,1" bitfld.long 0x0 31. " RESERVED ,Reads as zero" "0,1" group.byte 0x20++0x3 line.long 0x0 "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL." hexmask.long.tbyte 0x0 0.--17. 1. " PLL_REGM_F ,Fractional part of M divider." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reads as 0x1" width 0x0B tree.end tree "DPLLCTRL_SATA" base ad:0x4A096800 width 24. group.byte 0x4++0x3 line.long 0x0 "PLL_STATUS,This register contains the status information" bitfld.long 0x0 0. " PLLCTRL_RESET_DONE ,PLLCTRL reset done status" "0,1" bitfld.long 0x0 1. " PLL_LOCK ,PLL Lock status See the programming guide for the use of this bit" "0,1" textline " " bitfld.long 0x0 2. " PLL_RECAL ,PLL re-calibration status If this bit is active, the PLL needs to be re-calibrated" "0,1" bitfld.long 0x0 3. " PLL_LOSSREF ,PLL Reference Loss status" "0,1" textline " " bitfld.long 0x0 4. " RESERVED ,Read returns zero." "0,1" bitfld.long 0x0 5. " PLL_HIGHJITTER ,PLL High Jitter status" "0,1" textline " " bitfld.long 0x0 6.--11. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 12. " SSC_EN_ACK ,Spread Spectrum Clocking acknowledge" "0,1" textline " " bitfld.long 0x0 13.--14. " RESERVED ," "0,1,2,3" bitfld.long 0x0 15. " PLL_LDOPWDN ,PLL LDOPWDN status." "0,1" textline " " bitfld.long 0x0 16. " PLL_TICOPWDN ,PLL TICOPWDN status." "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PLL_GO,This register contains the GO bit" bitfld.long 0x0 0. " PLL_GO ,Request (re-)locking sequence of the PLL." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return zero." group.byte 0xC++0x3 line.long 0x0 "PLL_CONFIGURATION1,This register contains the latched PLL and HSDIVDER configuration bits" bitfld.long 0x0 0. " RESERVED ,Read returns zero." "0,1" hexmask.long.byte 0x0 1.--8. 1. " PLL_REGN ,N Divider for PLL (Reference)" textline " " hexmask.long.word 0x0 9.--20. 1. " PLL_REGM ,M Divider for PLL" hexmask.long.word 0x0 21.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PLL_CONFIGURATION2,This register contains the unlatched PLL and HSDIVDER configuration bits These bits are 'shadowed' when automatic mode is selected" bitfld.long 0x0 0. " PLL_IDLE ,PLL IDLE:" "0,1" bitfld.long 0x0 1.--3. " PLL_SELFREQDCO ,DCO frequency range selector for DPLL_USB_OTG_SS / DPLLCTRL_SATA 0x2 Set if DCO frequency is between 750MHz and 1500MHz 0x4 Set if DCO frequency is between 1250MHz and 2500MHz Other values: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--8. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 9.--10. " PLL_LOCKSEL ,Selects the lock criteria for the PLLOther values: Reserved enum=SPARE ." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 11.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PLL_CONFIGURATION3,HSDIVIDER configuration bits for the M5 and M6 dividers" hexmask.long.word 0x0 0.--9. 1. " RESERVED ," hexmask.long.byte 0x0 10.--17. 1. " PLL_SD ,Sigma delta divider setting for DPLL_USB_OTG_SS based on the PLL lock configuration." textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION1,Configuration for PLL Spread Spectrum Clocking modulation" bitfld.long 0x0 0. " EN_SSC ,Spread Spectrum Clocking enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " DOWNSPREAD ,Forces the clock spreading only in the down spectrum." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PLL_SSC_CONFIGURATION2,PLL_SSC_CONFIGURATION2" hexmask.long.tbyte 0x0 0.--19. 1. " DELTAM ,DeltaM control for SSC." hexmask.long.word 0x0 20.--29. 1. " MODFREQDIVIDER ,Modulation Frequency Divider control for SSC." textline " " bitfld.long 0x0 30. " DELTAM2 ,MSB of DeltaM control bus." "0,1" bitfld.long 0x0 31. " RESERVED ,Reads as zero" "0,1" group.byte 0x20++0x3 line.long 0x0 "PLL_CONFIGURATION4,Allows setting the fractional M divider and M2 divider for PLL." hexmask.long.tbyte 0x0 0.--17. 1. " PLL_REGM_F ,Fractional part of M divider." hexmask.long.word 0x0 18.--31. 1. " RESERVED ,Reads as 0x1" width 0x0B tree.end tree "OCP2SCP1" base ad:0x4A080000 width 19. group.byte 0x0++0x3 line.long 0x0 "OCP2SCP_REVISION,Revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,Module revision number" group.byte 0x10++0x3 line.long 0x0 "OCP2SCP_SYSCONFIG,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,OCP interface clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software Reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "OCP2SCP_SYSSTATUS,System Status register." bitfld.long 0x0 0. " RESETDONE ,Reset done" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "OCP2SCP_TIMING,Timing register" bitfld.long 0x0 0.--3. " SYNC2 ,Number of SCPclock cycles defining SYNC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " SYNC1 ,Number of SCPclock cycles defining SYNC1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7.--9. " DIVISIONRATIO ,Division Ration of the SCP clock in relation to OCP input clock." "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved." width 0x0B tree.end tree "OCP2SCP3" base ad:0x4A090000 width 19. group.byte 0x0++0x3 line.long 0x0 "OCP2SCP_REVISION,Revision register" hexmask.long 0x0 0.--31. 1. " REVISION ,Module revision number" group.byte 0x10++0x3 line.long 0x0 "OCP2SCP_SYSCONFIG,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,OCP interface clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software Reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Idle mode" "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "OCP2SCP_SYSSTATUS,System Status register." bitfld.long 0x0 0. " RESETDONE ,Reset done" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "OCP2SCP_TIMING,Timing register" bitfld.long 0x0 0.--3. " SYNC2 ,Number of SCPclock cycles defining SYNC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " SYNC1 ,Number of SCPclock cycles defining SYNC1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7.--9. " DIVISIONRATIO ,Division Ration of the SCP clock in relation to OCP input clock." "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved." width 0x0B tree.end tree "PCIe1_PHY_RX" base ad:0x4A094000 width 36. group.byte 0xC++0x3 line.long 0x0 "PCIEPHYRX_ANA_PROGRAMMABILITY_REG1,Programmability for different analog circuits in the PHY." bitfld.long 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5.--6. " MEM_PLLDIV ,This is a test mode. SoC Users are requested to leave this at default value. The input PLL_CLK (after being muxed with PLLBYPCLK) is divided by the following factors indicated by this register. 00=1 01=2 10=4 11=RESERVED. All references to PLL_CLK in this register descriptions are AFTER considering this division." "0,1,2,3" textline " " bitfld.long 0x0 7. " RESERVED ," "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " MEM_ANATESTMODE ,Programmability for Analog circuits in the PHY. The top 5 bits - MEM_ANATESTMODE[31:27] indicate the serial Interface using this PHY module. Bits [17:14] are used to control loss-of-signal detection (LOSD) threshold." group.byte 0x1C++0x3 line.long 0x0 "PCIEPHYRX_TRIM_REG4,The IP requires some values to be remembered in EFUSE. This register provides an alternative to EFUSE." hexmask.long 0x0 0.--29. 1. " RESERVED ," bitfld.long 0x0 30.--31. " MEM_DLL_TRIM_SEL ,Determines which of the 4 EFUSE registers EFUSE_dll_rateN_coarsetrim should be used as the trim code by the DLL. This feature is so that the user may find and store the trim codes corresponding to different (at most 4) DLL frequencies (pll_clk pll_clk (after the bypassing by MEM_en_pllbyp and the division by MEM_plldiv) frequencies) and at wake-up, instruct the IP to choose one of these available trim values depending on the Application's frequency requirement. 00 selects dll_rate0_coarsetrim 01 selects dll_rate1_coarsetrim 10 selects dll_rate2_coarsetrim 11 selects dll_rate3_coarsetrim." "0,1,2,3" group.byte 0x24++0x3 line.long 0x0 "PCIEPHYRX_DLL_REG1,This register is used to program DLL settings." hexmask.long 0x0 0.--29. 1. " RESERVED ," bitfld.long 0x0 30.--31. " MEM_DLL_PHINT_RATE ,Programs the DLL and the Phase Interpolator analog circuits to work with different clock frequencies. The frequency of pll_clk (after the bypassing by MEM_en_pllbyp and the division by MEM_plldiv) should be indicated by this register. 00=0.625GHz to 0.75GHz 01=RESERVED 10=1.25GHz to 1.5GHz 11=2.5GHz to 2.9GHz." "0,1,2,3" group.byte 0x28++0x3 line.long 0x0 "PCIEPHYRX_DIGITAL_MODES_REG1,This register contains control bits which affect different circuits in digital section" hexmask.long.word 0x0 0.--10. 1. " RESERVED ," bitfld.long 0x0 11. " MEM_CDR_2NDO_SDM_MODE ,If '1', the 2nd Order CDR block uses a 1st order Sigma Delta Modulator to accomplish frequency offset If '0', a simple rate transformer is used for the same purpose." "0,1" textline " " bitfld.long 0x0 12. " MEM_CDR_THR_MODE ,CDR 1st order threshold." "0,1" bitfld.long 0x0 13.--15. " MEM_CDR_THR ,CDR 1st order threshold. Determines how much early/late votes should differ by before a phase change in the receiver sampling clock is triggered." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 16.--18. " MEM_CDR_STL ,CDR settling time. Determines the number of vote clocks to blank ELV (Early-Late-Voter circuit) after update of phase." "0,1,2,3,4,5,6,7" bitfld.long 0x0 19.--20. " MEM_CDR_STEPCNT ,CDR 2nd order setting." "0,1,2,3" textline " " bitfld.long 0x0 21.--22. " MEM_CDR_LBW ,CDR band-width control." "0,1,2,3" bitfld.long 0x0 23. " MEM_CDR_FASTLOCK ,'1' to reduce lock time of CDR (clock-data-recovery circuit)." "0,1" textline " " bitfld.long 0x0 24.--25. " RESERVED ," "0,1,2,3" bitfld.long 0x0 26. " MEM_OVRD_HS_RATE ,Pin override control. See register bit MEM_hs_rate." "0,1" textline " " bitfld.long 0x0 27.--28. " MEM_HS_RATE ,Determines the ratio of pll_clk (after the bypassing by MEM_en_pllbyp and the division by MEM_plldiv) frequency and the output data rate. Full Rate means pll_clk (after the bypassing by MEM_en_pllbyp and the division by MEM_plldiv) frequency = Data Rate/2 00=Full Rate 01=Half Rate 10=Quarter Rate 11=RESERVED. This takes effect only if register bit MEM_ovrd_hs_rate is '1', else the same is controlled by input pins hs_rate." "0,1,2,3" bitfld.long 0x0 29. " RESERVED ," "0,1" textline " " bitfld.long 0x0 30. " MEM_OVRD_INV_RXPN_PAIR ,Pin override control. See register bit MEM_inv_rxpn_pair." "0,1" bitfld.long 0x0 31. " MEM_INV_RXPN_PAIR ,If '1', interchanges RXP and RXN effectively by inverting the received data samples." "0,1" group.byte 0x38++0x3 line.long 0x0 "PCIEPHYRX_EQUALIZER_REG1,The module has an Equalizer (with analog and digital parts) which addresses Inter Symbol Interference (ISI). The equalizer can be congured via the EQCTL bits. The options are: No adaptive equalization. The equalizer provides a at response at the maximum gain. This setting may be appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than frequency dependent loss. Fully adaptive equalization. Both the low frequency gain and zero position of the equalizer are determined algorithmically by analysing the data patterns and transition positions in the received data. This setting should be used for most applications. Partially adaptive equalization. The low frequency gain of the equalizer is determined algorithmically by analysing the data patterns and transition positions in the received data. The zero position is xed in one of eight zero positions. When enabled, the receiver equalization logic analyzes data patterns and transition times to determine whether the low frequency gain of the equalizer should be increased or decreased. For the fully adaptive setting (EQCTL = 0001), if the low frequency gain reaches the minimum value, the zero frequency is then reduced. Likewise, if it reaches the maximum value, the zero frequency is then increased." bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " MEM_OVRD_EQFTC ,Continuosly forces the Equalizer output with the MEM_EQFTC[4:0]." "0,1" textline " " bitfld.long 0x0 2. " MEM_OVRD_EQLEV ,Continuosly forces the Equalizer output with the MEM_EQLEV[15:0]." "0,1" bitfld.long 0x0 3.--6. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 7.--10. " MEM_EQCTL ,0000 - Equalizer disabled 0001 - Fully adaptive; FTC normal 0010 - Fully adaptive; FTC inverted 0011 - Hold equalizer state 01xx - Init equalizer to fully adaptive start/midpoint 1000 - Partially adaptive; zero=1084 MHz 1001 - Partially adaptive; zero= 805 MHz 1010 - Partially adaptive; zero= 573 MHz 1011 - Partially adaptive; zero= 402 MHZ 1100 - Partially adaptive; zero= 304 MHz 1101 - Partially adaptive; zero= 216 MHz 1110 - Partially adaptive; zero= 156 MHz 1111 - Partially adaptive; zero= 135 MHz" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 11.--15. " MEM_EQFTC ,Equalizer zero freq control." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--31. 1. " MEM_EQLEV ,Equalizer level control." width 0x0B tree.end tree "OCP2SCP3" base ad:0x4A090000 width 19. group.byte 0x0++0x3 line.long 0x0 "OCP2SCP_REVISION,IP Revision Identifier (X.Y.R)" bitfld.long 0x0 0.--5. " MINOR ,inor Revision This field changes when features are scaled up or down. This field does not change due to bug fix, or major feature change." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6.--7. " CUSTOM ,Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL)/Drivers. 0 if non-custom." "0,1,2,3" textline " " bitfld.long 0x0 8.--10. " MAJOR ,ajor Revision This field changes when there is a major feature change. This field does not change due to bug fix, or minor feature change." "0,1,2,3,4,5,6,7" bitfld.long 0x0 11.--15. " RTL ,RTL version This field changes on bug fix, and resets to" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 16.--27. 1. " FUNC ,Function: Indicates a software compatible module family" bitfld.long 0x0 28.--29. " RESERVED ,Reads return 0x1" "0,1,2,3" textline " " bitfld.long 0x0 30.--31. " SCHEME ,Used to distinguish between old Scheme and current. Spare bit to encode future schemes." "0,1,2,3" group.byte 0x10++0x3 line.long 0x0 "OCP2SCP_SYSCONFIG,SYSTEM CONFIGURATION REGISTER" bitfld.long 0x0 0. " AUTOIDLE ,OCP interface clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software Reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reserved." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ," "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "OCP2SCP_SYSSTATUS,System Status register." bitfld.long 0x0 0. " RESETDONE ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "OCP2SCP_TIMING,Interrupt Status Register (legacy) for first line of interrupt." bitfld.long 0x0 0.--3. " SYNC2 ,Number of SCPclock cycles defining SYNC2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " SYNC1 ,Number of SCPclock cycles defining SYNC1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7.--9. " DIVISIONRATIO ,Division Ration of the SCP clock in relation to OCP input clock." "0,1,2,3,4,5,6,7" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved." width 0x0B tree.end tree "PCIe1_PHY_TX" base ad:0x4A094400 width 31. group.byte 0xC++0x3 line.long 0x0 "PCIEPHYTX_FUNC_CONFIG_REG,Functional Configuration registers" hexmask.long 0x0 0.--30. 1. " RESERVED ," bitfld.long 0x0 31. " MEM_INVPAIR ,Invert polarity of TXP/TXN" "0,1" group.byte 0x10++0x3 line.long 0x0 "PCIEPHYTX_DRIVER_DATA_CONFIG1,Configures the Driver data pattern" bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " MEM_OVRD_HS_RATE_ANA_OVERRIDE ,Pin override for the hs_rate_ana_override" "0,1" textline " " bitfld.long 0x0 2.--3. " MEM_HS_RATE_ANA_OVERRIDE ,Override for the HS rate signal going to the AFE" "0,1,2,3" hexmask.long.byte 0x0 4.--10. 1. " MEM_ODD_OUT_CONFIG1 ,Overriding the odd TX data driver - to AFE" textline " " hexmask.long.byte 0x0 11.--17. 1. " MEM_EVEN_OUT_CONFIG1 ,Overriding the even TX data driver - to AFE" hexmask.long.byte 0x0 18.--24. 1. " MEM_ODD_OUT_CONFIG0 ,Overriding the odd TX data driver - to AFE" textline " " hexmask.long.byte 0x0 25.--31. 1. " MEM_EVEN_OUT_CONFIG0 ,Overriding the even TX data driver - to AFE" group.byte 0x2C++0x3 line.long 0x0 "PCIEPHYTX_TEST_CONFIG_REG,Test related configuration registers" hexmask.long 0x0 0.--25. 1. " RESERVED ," bitfld.long 0x0 26.--28. " MEM_TESTPATT ,Select the LFSR mode to generate the required pattern 000 - 31 bit LFSR mode 011 - 23 bit LFSR mode 010 - 7 bit LFSR mode 001 - generate 1010 pattern 100 - Fixed 31 bit value from pattgen_preload_val" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " MEM_ENTXPATT ,Enable Test pattern to input of the serializer instead of TD" "0,1" bitfld.long 0x0 30. " MEM_EN_LPBK ,Loopback enable for test" "0,1" textline " " bitfld.long 0x0 31. " RESERVED ,Keep at 0" "0,1" group.byte 0x30++0x3 line.long 0x0 "PCIEPHYTX_PATTGEN_PRELOAD,Pattern generator (31 bit) LFSR Seed or preload value" bitfld.long 0x0 0. " RESERVED ," "0,1" hexmask.long 0x0 1.--31. 1. " MEM_PATTGEN_PRELOAD_VAL ,Preload value to the LFSR pattern generator" width 0x0B tree.end tree "GPIO7" base ad:0x48051000 width 22. group.byte 0x0++0x3 line.long 0x0 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,OCP clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up control." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,0x0: Force-idle: An IDLE request is acknowledged unconditionally." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "GPIO_EOI,Software end of interrupt." bitfld.long 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line. Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x28++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x2C++0x3 line.long 0x0 "GPIO_IRQSTATUS_0,Per-event interrupt status vector, showing all active and enabled events (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x30++0x3 line.long 0x0 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector, showing all active and enabled events (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x34++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x38++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x3C++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x40++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x44++0x3 line.long 0x0 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x48++0x3 line.long 0x0 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x114++0x3 line.long 0x0 "GPIO_SYSSTATUS,System status register" bitfld.long 0x0 0. " RESETDONE ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "GPIO_CTRL,GPIO control register" bitfld.long 0x0 0. " DISABLEMODULE ," "0,1" bitfld.long 0x0 1.--2. " GATINGRATIO ,Clock gating ratio for event detection" "0,1,2,3" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "GPIO_OE,Output enable register. 0 = Output enabled ; 1 = Output disabled" hexmask.long 0x0 0.--31. 1. " OUTPUTEN ,Output enable" group.byte 0x138++0x3 line.long 0x0 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x0 0.--31. 1. " DATAIN ,Sampled input data" group.byte 0x13C++0x3 line.long 0x0 "GPIO_DATAOUT,Data-output register (data to set on output pins)" hexmask.long 0x0 0.--31. 1. " DATAOUT ,Data to set on output pins" group.byte 0x140++0x3 line.long 0x0 "GPIO_LEVELDETECT0,Detect low-level register. 0 = Low-level detection disabled; 1 = Low-level detection enabled" hexmask.long 0x0 0.--31. 1. " LEVELDETECT0 ,Low-level detection" group.byte 0x144++0x3 line.long 0x0 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x0 0.--31. 1. " LEVELDETECT1 ," group.byte 0x148++0x3 line.long 0x0 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x0 0.--31. 1. " RISINGDETECT ," group.byte 0x14C++0x3 line.long 0x0 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x0 0.--31. 1. " FALLINGDETECT ," group.byte 0x150++0x3 line.long 0x0 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x0 0.--31. 1. " DEBOUNCEENABLE ," group.byte 0x154++0x3 line.long 0x0 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x0 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time. It is n-periods of the muxed clock, which can come from either a true 32k oscillator/pad of from the system clock. It depends on which boot mode is selected. For more information see, Initialization." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "GPIO_CLEARDATAOUT,Clear data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," group.byte 0x194++0x3 line.long 0x0 "GPIO_SETDATAOUT,Set data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," width 0x0B tree.end tree "GPIO8" base ad:0x48053000 width 22. group.byte 0x0++0x3 line.long 0x0 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,OCP clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up control." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,0x0: Force-idle: An IDLE request is acknowledged unconditionally." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "GPIO_EOI,Software end of interrupt." bitfld.long 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line. Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x28++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x2C++0x3 line.long 0x0 "GPIO_IRQSTATUS_0,Per-event interrupt status vector, showing all active and enabled events (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x30++0x3 line.long 0x0 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector, showing all active and enabled events (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x34++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x38++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x3C++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x40++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x44++0x3 line.long 0x0 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x48++0x3 line.long 0x0 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x114++0x3 line.long 0x0 "GPIO_SYSSTATUS,System status register" bitfld.long 0x0 0. " RESETDONE ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "GPIO_CTRL,GPIO control register" bitfld.long 0x0 0. " DISABLEMODULE ," "0,1" bitfld.long 0x0 1.--2. " GATINGRATIO ,Clock gating ratio for event detection" "0,1,2,3" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "GPIO_OE,Output enable register. 0 = Output enabled ; 1 = Output disabled" hexmask.long 0x0 0.--31. 1. " OUTPUTEN ,Output enable" group.byte 0x138++0x3 line.long 0x0 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x0 0.--31. 1. " DATAIN ,Sampled input data" group.byte 0x13C++0x3 line.long 0x0 "GPIO_DATAOUT,Data-output register (data to set on output pins)" hexmask.long 0x0 0.--31. 1. " DATAOUT ,Data to set on output pins" group.byte 0x140++0x3 line.long 0x0 "GPIO_LEVELDETECT0,Detect low-level register. 0 = Low-level detection disabled; 1 = Low-level detection enabled" hexmask.long 0x0 0.--31. 1. " LEVELDETECT0 ,Low-level detection" group.byte 0x144++0x3 line.long 0x0 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x0 0.--31. 1. " LEVELDETECT1 ," group.byte 0x148++0x3 line.long 0x0 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x0 0.--31. 1. " RISINGDETECT ," group.byte 0x14C++0x3 line.long 0x0 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x0 0.--31. 1. " FALLINGDETECT ," group.byte 0x150++0x3 line.long 0x0 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x0 0.--31. 1. " DEBOUNCEENABLE ," group.byte 0x154++0x3 line.long 0x0 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x0 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time. It is n-periods of the muxed clock, which can come from either a true 32k oscillator/pad of from the system clock. It depends on which boot mode is selected. For more information see, Initialization." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "GPIO_CLEARDATAOUT,Clear data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," group.byte 0x194++0x3 line.long 0x0 "GPIO_SETDATAOUT,Set data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," width 0x0B tree.end tree "GPIO2" base ad:0x48055000 width 22. group.byte 0x0++0x3 line.long 0x0 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,OCP clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up control." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,0x0: Force-idle: An IDLE request is acknowledged unconditionally." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "GPIO_EOI,Software end of interrupt." bitfld.long 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line. Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x28++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x2C++0x3 line.long 0x0 "GPIO_IRQSTATUS_0,Per-event interrupt status vector, showing all active and enabled events (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x30++0x3 line.long 0x0 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector, showing all active and enabled events (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x34++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x38++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x3C++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x40++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x44++0x3 line.long 0x0 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x48++0x3 line.long 0x0 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x114++0x3 line.long 0x0 "GPIO_SYSSTATUS,System status register" bitfld.long 0x0 0. " RESETDONE ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "GPIO_CTRL,GPIO control register" bitfld.long 0x0 0. " DISABLEMODULE ," "0,1" bitfld.long 0x0 1.--2. " GATINGRATIO ,Clock gating ratio for event detection" "0,1,2,3" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "GPIO_OE,Output enable register. 0 = Output enabled ; 1 = Output disabled" hexmask.long 0x0 0.--31. 1. " OUTPUTEN ,Output enable" group.byte 0x138++0x3 line.long 0x0 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x0 0.--31. 1. " DATAIN ,Sampled input data" group.byte 0x13C++0x3 line.long 0x0 "GPIO_DATAOUT,Data-output register (data to set on output pins)" hexmask.long 0x0 0.--31. 1. " DATAOUT ,Data to set on output pins" group.byte 0x140++0x3 line.long 0x0 "GPIO_LEVELDETECT0,Detect low-level register. 0 = Low-level detection disabled; 1 = Low-level detection enabled" hexmask.long 0x0 0.--31. 1. " LEVELDETECT0 ,Low-level detection" group.byte 0x144++0x3 line.long 0x0 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x0 0.--31. 1. " LEVELDETECT1 ," group.byte 0x148++0x3 line.long 0x0 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x0 0.--31. 1. " RISINGDETECT ," group.byte 0x14C++0x3 line.long 0x0 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x0 0.--31. 1. " FALLINGDETECT ," group.byte 0x150++0x3 line.long 0x0 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x0 0.--31. 1. " DEBOUNCEENABLE ," group.byte 0x154++0x3 line.long 0x0 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x0 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time. It is n-periods of the muxed clock, which can come from either a true 32k oscillator/pad of from the system clock. It depends on which boot mode is selected. For more information see, Initialization." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "GPIO_CLEARDATAOUT,Clear data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," group.byte 0x194++0x3 line.long 0x0 "GPIO_SETDATAOUT,Set data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," width 0x0B tree.end tree "GPIO3" base ad:0x48057000 width 22. group.byte 0x0++0x3 line.long 0x0 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,OCP clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up control." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,0x0: Force-idle: An IDLE request is acknowledged unconditionally." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "GPIO_EOI,Software end of interrupt." bitfld.long 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line. Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x28++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x2C++0x3 line.long 0x0 "GPIO_IRQSTATUS_0,Per-event interrupt status vector, showing all active and enabled events (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x30++0x3 line.long 0x0 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector, showing all active and enabled events (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x34++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x38++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x3C++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x40++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x44++0x3 line.long 0x0 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x48++0x3 line.long 0x0 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x114++0x3 line.long 0x0 "GPIO_SYSSTATUS,System status register" bitfld.long 0x0 0. " RESETDONE ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "GPIO_CTRL,GPIO control register" bitfld.long 0x0 0. " DISABLEMODULE ," "0,1" bitfld.long 0x0 1.--2. " GATINGRATIO ,Clock gating ratio for event detection" "0,1,2,3" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "GPIO_OE,Output enable register. 0 = Output enabled ; 1 = Output disabled" hexmask.long 0x0 0.--31. 1. " OUTPUTEN ,Output enable" group.byte 0x138++0x3 line.long 0x0 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x0 0.--31. 1. " DATAIN ,Sampled input data" group.byte 0x13C++0x3 line.long 0x0 "GPIO_DATAOUT,Data-output register (data to set on output pins)" hexmask.long 0x0 0.--31. 1. " DATAOUT ,Data to set on output pins" group.byte 0x140++0x3 line.long 0x0 "GPIO_LEVELDETECT0,Detect low-level register. 0 = Low-level detection disabled; 1 = Low-level detection enabled" hexmask.long 0x0 0.--31. 1. " LEVELDETECT0 ,Low-level detection" group.byte 0x144++0x3 line.long 0x0 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x0 0.--31. 1. " LEVELDETECT1 ," group.byte 0x148++0x3 line.long 0x0 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x0 0.--31. 1. " RISINGDETECT ," group.byte 0x14C++0x3 line.long 0x0 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x0 0.--31. 1. " FALLINGDETECT ," group.byte 0x150++0x3 line.long 0x0 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x0 0.--31. 1. " DEBOUNCEENABLE ," group.byte 0x154++0x3 line.long 0x0 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x0 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time. It is n-periods of the muxed clock, which can come from either a true 32k oscillator/pad of from the system clock. It depends on which boot mode is selected. For more information see, Initialization." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "GPIO_CLEARDATAOUT,Clear data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," group.byte 0x194++0x3 line.long 0x0 "GPIO_SETDATAOUT,Set data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," width 0x0B tree.end tree "GPIO4" base ad:0x48059000 width 22. group.byte 0x0++0x3 line.long 0x0 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,OCP clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up control." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,0x0: Force-idle: An IDLE request is acknowledged unconditionally." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "GPIO_EOI,Software end of interrupt." bitfld.long 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line. Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x28++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x2C++0x3 line.long 0x0 "GPIO_IRQSTATUS_0,Per-event interrupt status vector, showing all active and enabled events (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x30++0x3 line.long 0x0 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector, showing all active and enabled events (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x34++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x38++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x3C++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x40++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x44++0x3 line.long 0x0 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x48++0x3 line.long 0x0 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x114++0x3 line.long 0x0 "GPIO_SYSSTATUS,System status register" bitfld.long 0x0 0. " RESETDONE ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "GPIO_CTRL,GPIO control register" bitfld.long 0x0 0. " DISABLEMODULE ," "0,1" bitfld.long 0x0 1.--2. " GATINGRATIO ,Clock gating ratio for event detection" "0,1,2,3" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "GPIO_OE,Output enable register. 0 = Output enabled ; 1 = Output disabled" hexmask.long 0x0 0.--31. 1. " OUTPUTEN ,Output enable" group.byte 0x138++0x3 line.long 0x0 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x0 0.--31. 1. " DATAIN ,Sampled input data" group.byte 0x13C++0x3 line.long 0x0 "GPIO_DATAOUT,Data-output register (data to set on output pins)" hexmask.long 0x0 0.--31. 1. " DATAOUT ,Data to set on output pins" group.byte 0x140++0x3 line.long 0x0 "GPIO_LEVELDETECT0,Detect low-level register. 0 = Low-level detection disabled; 1 = Low-level detection enabled" hexmask.long 0x0 0.--31. 1. " LEVELDETECT0 ,Low-level detection" group.byte 0x144++0x3 line.long 0x0 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x0 0.--31. 1. " LEVELDETECT1 ," group.byte 0x148++0x3 line.long 0x0 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x0 0.--31. 1. " RISINGDETECT ," group.byte 0x14C++0x3 line.long 0x0 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x0 0.--31. 1. " FALLINGDETECT ," group.byte 0x150++0x3 line.long 0x0 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x0 0.--31. 1. " DEBOUNCEENABLE ," group.byte 0x154++0x3 line.long 0x0 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x0 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time. It is n-periods of the muxed clock, which can come from either a true 32k oscillator/pad of from the system clock. It depends on which boot mode is selected. For more information see, Initialization." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "GPIO_CLEARDATAOUT,Clear data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," group.byte 0x194++0x3 line.long 0x0 "GPIO_SETDATAOUT,Set data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," width 0x0B tree.end tree "GPIO5" base ad:0x4805B000 width 22. group.byte 0x0++0x3 line.long 0x0 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,OCP clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up control." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,0x0: Force-idle: An IDLE request is acknowledged unconditionally." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "GPIO_EOI,Software end of interrupt." bitfld.long 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line. Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x28++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x2C++0x3 line.long 0x0 "GPIO_IRQSTATUS_0,Per-event interrupt status vector, showing all active and enabled events (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x30++0x3 line.long 0x0 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector, showing all active and enabled events (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x34++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x38++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x3C++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x40++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x44++0x3 line.long 0x0 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x48++0x3 line.long 0x0 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x114++0x3 line.long 0x0 "GPIO_SYSSTATUS,System status register" bitfld.long 0x0 0. " RESETDONE ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "GPIO_CTRL,GPIO control register" bitfld.long 0x0 0. " DISABLEMODULE ," "0,1" bitfld.long 0x0 1.--2. " GATINGRATIO ,Clock gating ratio for event detection" "0,1,2,3" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "GPIO_OE,Output enable register. 0 = Output enabled ; 1 = Output disabled" hexmask.long 0x0 0.--31. 1. " OUTPUTEN ,Output enable" group.byte 0x138++0x3 line.long 0x0 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x0 0.--31. 1. " DATAIN ,Sampled input data" group.byte 0x13C++0x3 line.long 0x0 "GPIO_DATAOUT,Data-output register (data to set on output pins)" hexmask.long 0x0 0.--31. 1. " DATAOUT ,Data to set on output pins" group.byte 0x140++0x3 line.long 0x0 "GPIO_LEVELDETECT0,Detect low-level register. 0 = Low-level detection disabled; 1 = Low-level detection enabled" hexmask.long 0x0 0.--31. 1. " LEVELDETECT0 ,Low-level detection" group.byte 0x144++0x3 line.long 0x0 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x0 0.--31. 1. " LEVELDETECT1 ," group.byte 0x148++0x3 line.long 0x0 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x0 0.--31. 1. " RISINGDETECT ," group.byte 0x14C++0x3 line.long 0x0 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x0 0.--31. 1. " FALLINGDETECT ," group.byte 0x150++0x3 line.long 0x0 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x0 0.--31. 1. " DEBOUNCEENABLE ," group.byte 0x154++0x3 line.long 0x0 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x0 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time. It is n-periods of the muxed clock, which can come from either a true 32k oscillator/pad of from the system clock. It depends on which boot mode is selected. For more information see, Initialization." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "GPIO_CLEARDATAOUT,Clear data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," group.byte 0x194++0x3 line.long 0x0 "GPIO_SETDATAOUT,Set data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," width 0x0B tree.end tree "GPIO6" base ad:0x4805D000 width 22. group.byte 0x0++0x3 line.long 0x0 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,OCP clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up control." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,0x0: Force-idle: An IDLE request is acknowledged unconditionally." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "GPIO_EOI,Software end of interrupt." bitfld.long 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line. Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x28++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x2C++0x3 line.long 0x0 "GPIO_IRQSTATUS_0,Per-event interrupt status vector, showing all active and enabled events (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x30++0x3 line.long 0x0 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector, showing all active and enabled events (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x34++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x38++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x3C++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x40++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x44++0x3 line.long 0x0 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x48++0x3 line.long 0x0 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x114++0x3 line.long 0x0 "GPIO_SYSSTATUS,System status register" bitfld.long 0x0 0. " RESETDONE ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "GPIO_CTRL,GPIO control register" bitfld.long 0x0 0. " DISABLEMODULE ," "0,1" bitfld.long 0x0 1.--2. " GATINGRATIO ,Clock gating ratio for event detection" "0,1,2,3" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "GPIO_OE,Output enable register. 0 = Output enabled ; 1 = Output disabled" hexmask.long 0x0 0.--31. 1. " OUTPUTEN ,Output enable" group.byte 0x138++0x3 line.long 0x0 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x0 0.--31. 1. " DATAIN ,Sampled input data" group.byte 0x13C++0x3 line.long 0x0 "GPIO_DATAOUT,Data-output register (data to set on output pins)" hexmask.long 0x0 0.--31. 1. " DATAOUT ,Data to set on output pins" group.byte 0x140++0x3 line.long 0x0 "GPIO_LEVELDETECT0,Detect low-level register. 0 = Low-level detection disabled; 1 = Low-level detection enabled" hexmask.long 0x0 0.--31. 1. " LEVELDETECT0 ,Low-level detection" group.byte 0x144++0x3 line.long 0x0 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x0 0.--31. 1. " LEVELDETECT1 ," group.byte 0x148++0x3 line.long 0x0 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x0 0.--31. 1. " RISINGDETECT ," group.byte 0x14C++0x3 line.long 0x0 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x0 0.--31. 1. " FALLINGDETECT ," group.byte 0x150++0x3 line.long 0x0 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x0 0.--31. 1. " DEBOUNCEENABLE ," group.byte 0x154++0x3 line.long 0x0 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x0 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time. It is n-periods of the muxed clock, which can come from either a true 32k oscillator/pad of from the system clock. It depends on which boot mode is selected. For more information see, Initialization." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "GPIO_CLEARDATAOUT,Clear data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," group.byte 0x194++0x3 line.long 0x0 "GPIO_SETDATAOUT,Set data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," width 0x0B tree.end tree "GPIO1" base ad:0x4AE10000 width 22. group.byte 0x0++0x3 line.long 0x0 "GPIO_REVISION,IP revision identifier (X.Y.R)" hexmask.long 0x0 0.--31. 1. " REVISION ,IP revision" group.byte 0x10++0x3 line.long 0x0 "GPIO_SYSCONFIG,System configuration register" bitfld.long 0x0 0. " AUTOIDLE ,OCP clock gating control." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reads, it always returns 0." "0,1" textline " " bitfld.long 0x0 2. " ENAWAKEUP ,Wake-up control." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,0x0: Force-idle: An IDLE request is acknowledged unconditionally." "0,1,2,3" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "GPIO_EOI,Software end of interrupt." bitfld.long 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_0,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line. Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x28++0x3 line.long 0x0 "GPIO_IRQSTATUS_RAW_1,Per-event raw interrupt status vector, showing all active events (enabled and not enabled), (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status raw for interrupt line Writing '1' to a bit will set it to '1.' Writing '0' has no effect" group.byte 0x2C++0x3 line.long 0x0 "GPIO_IRQSTATUS_0,Per-event interrupt status vector, showing all active and enabled events (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x30++0x3 line.long 0x0 "GPIO_IRQSTATUS_1,Per-event enabled interrupt status vector, showing all active and enabled events (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status for interrupt line Writing 1 to a bit will clear it to 0. Writing 0 has no effect." group.byte 0x34++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_0,Per-event interrupt-enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x38++0x3 line.long 0x0 "GPIO_IRQSTATUS_SET_1,Per-event enable set interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status set for interrupt line Writing 1 to a bit enables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x3C++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_0,Per-event interrupt-enable clear vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x40++0x3 line.long 0x0 "GPIO_IRQSTATUS_CLR_1,Per-event enable clear interrupt vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Status clear for interrupt line Writing 1 to a bit disables the corresponding interrupt event. Writing 0 has no effect." group.byte 0x44++0x3 line.long 0x0 "GPIO_IRQWAKEN_0,Per-event wake-up enable set vector (corresponding to first line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x48++0x3 line.long 0x0 "GPIO_IRQWAKEN_1,Per-event wake-up enable set vector (corresponding to second line of interrupt)" hexmask.long 0x0 0.--31. 1. " INTLINE ,Wakeup set for interrupt line Setting a bit to 1 will enable wakeup for the corresponding event. Setting a bit to 0 will disable wakeup for the corresponding event." group.byte 0x114++0x3 line.long 0x0 "GPIO_SYSSTATUS,System status register" bitfld.long 0x0 0. " RESETDONE ," "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x130++0x3 line.long 0x0 "GPIO_CTRL,GPIO control register" bitfld.long 0x0 0. " DISABLEMODULE ," "0,1" bitfld.long 0x0 1.--2. " GATINGRATIO ,Clock gating ratio for event detection" "0,1,2,3" textline " " hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x134++0x3 line.long 0x0 "GPIO_OE,Output enable register. 0 = Output enabled ; 1 = Output disabled" hexmask.long 0x0 0.--31. 1. " OUTPUTEN ,Output enable" group.byte 0x138++0x3 line.long 0x0 "GPIO_DATAIN,Data input register (with sampled input data)" hexmask.long 0x0 0.--31. 1. " DATAIN ,Sampled input data" group.byte 0x13C++0x3 line.long 0x0 "GPIO_DATAOUT,Data-output register (data to set on output pins)" hexmask.long 0x0 0.--31. 1. " DATAOUT ,Data to set on output pins" group.byte 0x140++0x3 line.long 0x0 "GPIO_LEVELDETECT0,Detect low-level register. 0 = Low-level detection disabled; 1 = Low-level detection enabled" hexmask.long 0x0 0.--31. 1. " LEVELDETECT0 ,Low-level detection" group.byte 0x144++0x3 line.long 0x0 "GPIO_LEVELDETECT1,Detect high-level register" hexmask.long 0x0 0.--31. 1. " LEVELDETECT1 ," group.byte 0x148++0x3 line.long 0x0 "GPIO_RISINGDETECT,Detect rising edge register" hexmask.long 0x0 0.--31. 1. " RISINGDETECT ," group.byte 0x14C++0x3 line.long 0x0 "GPIO_FALLINGDETECT,Detect falling edge register" hexmask.long 0x0 0.--31. 1. " FALLINGDETECT ," group.byte 0x150++0x3 line.long 0x0 "GPIO_DEBOUNCENABLE,Debouncing enable register" hexmask.long 0x0 0.--31. 1. " DEBOUNCEENABLE ," group.byte 0x154++0x3 line.long 0x0 "GPIO_DEBOUNCINGTIME,Debouncing value register" hexmask.long.byte 0x0 0.--7. 1. " DEBOUNCETIME ,8-bit values specifying the debouncing time. It is n-periods of the muxed clock, which can come from either a true 32k oscillator/pad of from the system clock. It depends on which boot mode is selected. For more information see, Initialization." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x190++0x3 line.long 0x0 "GPIO_CLEARDATAOUT,Clear data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," group.byte 0x194++0x3 line.long 0x0 "GPIO_SETDATAOUT,Set data-output register" hexmask.long 0x0 0.--31. 1. " INTLINE ," width 0x0B tree.end tree "KBD" base ad:0x4AE1C000 width 20. group.byte 0x0++0x3 line.long 0x0 "KBD_REVISION,This register contains the IP revision code. A write to this register has no effect." hexmask.long 0x0 0.--31. 1. " Reserved ,IP Revision" group.byte 0x10++0x3 line.long 0x0 "KBD_SYSCONFIG,This register controls the various parameters of the OCP interface" bitfld.long 0x0 0. " RESERVED ,Reads return 0." "0,1" bitfld.long 0x0 1. " SOFTRESET ,Software reset. Write: initiate software reset Read: Reset done (0) / Reset ongoing (1)" "0,1" textline " " bitfld.long 0x0 2. " RESERVED ,Reads return 0." "0,1" bitfld.long 0x0 3.--4. " IDLEMODE ,Power Management, req/ack control" "0,1,2,3" textline " " bitfld.long 0x0 5. " EMUFREE ,Emulation mode" "0,1" hexmask.long 0x0 6.--31. 1. " RESERVED ,Reads return 0." group.byte 0x1C++0x3 line.long 0x0 "KBD_EOI,Software End-Of-Interrupt: Allows the generation of further pulses on the interrupt line, if an new interrupt event is pending, when using the pulsed output. Unused when using the level interrupt line (depending on module integration)." bitfld.long 0x0 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control. Write number of interrupt output." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reads return 0." group.byte 0x20++0x3 line.long 0x0 "KBD_IRQSTATUS_RAW,Per-event raw interrupt status vector Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." bitfld.long 0x0 0. " IT_EVENT ,IRQ status for Event Read 0 : No event pending Write 0 : No action Read 1 : IRQ event pending Write 1 : Trigger IRQ event by software" "0,1" bitfld.long 0x0 1. " IT_LONG_KEY ,IRQ status for Long key Read 0 : No event pending Write 0 : No action Read 1 : IRQ event pending Write 1 : Trigger IRQ event by software" "0,1" textline " " bitfld.long 0x0 2. " IT_TIMEOUT ,IRQ status for Timeout Read 0 : No event pending Write 0 : No action Read 1 : IRQ event pending Write 1 : Trigger IRQ event by software" "0,1" bitfld.long 0x0 3. " MISS_EVENT ,IRQ status for Miss event Read 0 : No event pending Write 0 : No action Read 1 : IRQ event pending Write 1 : Trigger IRQ event by software" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reads return 0" group.byte 0x24++0x3 line.long 0x0 "KBD_IRQSTATUS,Per-event 'enabled' interrupt status vector. Enabled status isn't set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, i.e. even if not enabled)." bitfld.long 0x0 0. " IT_EVENT ,IRQ status for Event Read 0 : No event pending Write 0 : No action Read 1 : IRQ event pending Write 1 : Clear pending event, if any" "0,1" bitfld.long 0x0 1. " IT_LONG_KEY ,IRQ status for Long key Read 0 : No event pending Write 0 : No action Read 1 : IRQ event pending Write 1 : Clear pending event, if any" "0,1" textline " " bitfld.long 0x0 2. " IT_TIMEOUT ,IRQ status for Timeout Read 0 : No event pending Write 0 : No action Read 1 : IRQ event pending Write 1 : Clear pending event, if any" "0,1" bitfld.long 0x0 3. " MISS_EVENT ,IRQ status for Miss event Read always returns zero Write 0 : No action Write 1 : Clear pending event, if any" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reads return 0" group.byte 0x28++0x3 line.long 0x0 "KBD_IRQENABLE_SET,Per-event interrupt enable bit vector Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." bitfld.long 0x0 0. " IT_EVENT_EN ,IRQ enable for Event Read 0 : IRQ event is disabled Write 0 : No action Read 1 : IRQ event is enabled Write 1 : Set IRQ enable" "0,1" bitfld.long 0x0 1. " IT_LONG_KEY_EN ,IRQ enable for Long key Read 0 : IRQ event is disabled Write 0 : No action Read 1 : IRQ event is enabled Write 1 : Set IRQ enable" "0,1" textline " " bitfld.long 0x0 2. " IT_TIMEOUT_EN ,IRQ enable for Timeout Read 0 : IRQ event is disabled Write 0 : No action Read 1 : IRQ event is enabled Write 1 : Set IRQ enable" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reads return 0" group.byte 0x2C++0x3 line.long 0x0 "KBD_IRQENABLE_CLR,Per-event interrupt enable bit vector Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." bitfld.long 0x0 0. " IT_EVENT_EN ,IRQ enable for Event Read 0 : IRQ event is disabled Write 0 : No action Read 1 : IRQ event is enabled Write 1 : Clear IRQ enable" "0,1" bitfld.long 0x0 1. " IT_LONG_KEY_EN ,IRQ enable for Long key Read 0 : IRQ event is disabled Write 0 : No action Read 1 : IRQ event is enabled Write 1 : Clear IRQ enable" "0,1" textline " " bitfld.long 0x0 2. " IT_TIMEOUT_EN ,IRQ enable for Timeout Read 0 : IRQ event is disabled Write 0 : No action Read 1 : IRQ event is enabled Write 1 : Clear IRQ enable" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reads return 0" group.byte 0x30++0x3 line.long 0x0 "KBD_IRQWAKEEN,The Keyboard Wake-up Enable Register allows the user to mask the expected source of wake-up event that will generate a wake-up request. The is programmed synchronously with the interface clock before any idle mode request comes from the host processor." bitfld.long 0x0 0. " WUP_EVENT_ENA ,Event wakeup enable." "0,1" bitfld.long 0x0 1. " WUP_LONG_KEY_ENA ,Long key wakeup enable." "0,1" textline " " bitfld.long 0x0 2. " WUP_TIMEOUT_ENA ,Timeout wakeup enable." "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reads return 0." group.byte 0x34++0x3 line.long 0x0 "KBD_PENDING,The software must read the pending write bits to insure that following write access will not be discarded due to on going write synchronization process. These bits are automatically cleared by internal logic when the write to the corresponding register is acknowledged." bitfld.long 0x0 0. " PEND_CTRL ,Write pending bit forKBD_CTRL register" "0,1" bitfld.long 0x0 1. " PEND_DEBOUNCING ,Write pending bit forKBD_DEBOUNCINGTIME register" "0,1" textline " " bitfld.long 0x0 2. " PEND_LONG_KEY ,Write pending bit forKBD_KEYLONGTIME register" "0,1" bitfld.long 0x0 3. " PEND_TIMEOUT ,Write pending bit forKBD_TIMEOUT register" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reads return 0." group.byte 0x38++0x3 line.long 0x0 "KBD_CTRL,This register sets the functional configuration of the module." bitfld.long 0x0 0. " RESERVED ,Reads return 0." "0,1" bitfld.long 0x0 1. " NSOFTWARE_MODE ,Select hardware or software mode for key decoding." "0,1" textline " " bitfld.long 0x0 2.--4. " PTV ,Pre-scale clock timer value." "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " LONG_KEY ,Long key mode enable." "0,1" textline " " bitfld.long 0x0 6. " TIMEOUT_EMPTY ,Timeout empty mode enable." "0,1" bitfld.long 0x0 7. " TIMEOUT_LONG_KEY ,Timeout long key mode enable." "0,1" textline " " bitfld.long 0x0 8. " REPEAT_MODE ,Repeat mode enable." "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reads return 0." group.byte 0x3C++0x3 line.long 0x0 "KBD_DEBOUNCINGTIME,This register is used to filter glitches on the press key or release key." bitfld.long 0x0 0.--5. " DEBOUNCING_VALUE ,This value correspond to the desired value of debouncing time." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long 0x0 6.--31. 1. " RESERVED ,Reads return 0." group.byte 0x40++0x3 line.long 0x0 "KBD_KEYLONGTIME,This register is used to measure duration of a key press, to allow, shortcut detection." hexmask.long.word 0x0 0.--11. 1. " LONG_KEY_VALUE ,This value correspond to the desired value of the long key interrupt or repeat mode value." hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ,Reads return 0." group.byte 0x44++0x3 line.long 0x0 "KBD_TIMEOUT,This register is used to detect a long inactivity on the keyboard." hexmask.long.word 0x0 0.--15. 1. " TIMEOUT_VALUE ,This value correspond to the desired value of the time out interrupt." hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reads return 0." group.byte 0x48++0x3 line.long 0x0 "KBD_STATEMACHINE,This register indicates the state of the sequencer." bitfld.long 0x0 0.--3. " STATE_MACHINE ,The state of internal state machine." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long 0x0 4.--31. 1. " RESERVED ,Reads return 0" group.byte 0x4C++0x3 line.long 0x0 "KBD_ROWINPUTS,This register stores the value of the rows input." hexmask.long.word 0x0 0.--8. 1. " KBR_LATCH ,The value of the rows input." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reads return 0." group.byte 0x50++0x3 line.long 0x0 "KBD_COLUMNOUTPUTS,This register holds the value of the columns output." hexmask.long.word 0x0 0.--8. 1. " KBC_REG ,The value of the columns output." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reads return 0." group.byte 0x54++0x3 line.long 0x0 "KBD_FULLCODE31_0,The register codes the row 0, row 1, row 2 and row 3" hexmask.long 0x0 0.--31. 1. " FULL_CODE_31_0 ,A bit at one indicate that the corresponding key is pressed." group.byte 0x58++0x3 line.long 0x0 "KBD_FULLCODE63_32,The register codes the row 4, row 5, row 6 and row 7." hexmask.long 0x0 0.--31. 1. " FULL_CODE_63_32 ,A bit at one indicate that the corresponding key is pressed." group.byte 0x5C++0x3 line.long 0x0 "KBD_FULLCODE17_0,The register codes the row 0 and row 1. The row 0 is coded between bit 0 and 8, the row 1 is coded between bit 24 and" hexmask.long.word 0x0 0.--8. 1. " ROW0 ,A bit at one indicate that the corresponding key is pressed." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " ROW1 ,A bit at one indicate that the corresponding key is pressed." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x60++0x3 line.long 0x0 "KBD_FULLCODE35_18,The register codes the row 2 and row 3. The row 2 is coded between bit 0 and 8, the row 3 is coded between bit 24 and 16" hexmask.long.word 0x0 0.--8. 1. " ROW2 ,A bit at one indicate that the corresponding key is pressed." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " ROW3 ,A bit at one indicate that the corresponding key is pressed." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x64++0x3 line.long 0x0 "KBD_FULLCODE53_36,The register codes the row 4 and row 5. The row 4 is coded between bit 0 and 8, the row 5 is coded between bit 24 and 16." hexmask.long.word 0x0 0.--8. 1. " ROW4 ,A bit at one indicate that the corresponding key is pressed." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " ROW5 ,A bit at one indicate that the corresponding key is pressed." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x68++0x3 line.long 0x0 "KBD_FULLCODE71_54,The register codes the row 6 and row 7. The row 0 is coded between bit 0 and 8, the row 1 is coded between bit 24 and 16" hexmask.long.word 0x0 0.--8. 1. " ROW6 ,A bit at one indicate that the corresponding key is pressed." hexmask.long.byte 0x0 9.--15. 1. " RESERVED ," textline " " hexmask.long.word 0x0 16.--24. 1. " ROW7 ,A bit at one indicate that the corresponding key is pressed." hexmask.long.byte 0x0 25.--31. 1. " RESERVED ," group.byte 0x6C++0x3 line.long 0x0 "KBD_FULLCODE80_72,The register codes the row 8. The row 8 is coded between bit 0 and 8." hexmask.long.word 0x0 0.--8. 1. " ROW8 ,A bit at one indicate that the corresponding key is pressed." hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," width 0x0B tree.end tree "PWMSS1_CFG" base ad:0x4843E000 width 17. group.byte 0x0++0x3 line.long 0x0 "PWMSS_IDVER,IP Revision Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision value" group.byte 0x4++0x3 line.long 0x0 "PWMSS_SYSCONFIG,This register controls the PWMSSn (where n= 1 to 3) local Idle mode clock management and software reset" bitfld.long 0x0 0. " SOFTRESET ,Software reset : 0x0 : Software reset is completed 0x1: Software reset assertion" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, the target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSSn (where n = 1 to 3) for clkstop req and clk_en control to the ePWM/ eHRPWM, eCAP and eQEP submodules within the PWMSSn subsystem. Note: PWMSS Modules Local Clock Gating feature is not supported. This register should not be modified. Clock gating functionality is controlled by PRCM." bitfld.long 0x0 0. " ECAP_CLK_EN ,This bit controls the interface clock enable (clk_en) input to the eCAP module : 0: No effect 1: Enables the interface clock to the module" "0,1" bitfld.long 0x0 1. " ECAP_CLKSTOP_REQ ,This bit controls the clock stop input to the eCAP module : 0: No effect 1: A request to stop interface clock to the module is asserted" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " EQEP_CLK_EN ,This bit controls the interface clock enable (clk_en) input to the eQEP module : 0: No effect 1: Enables the interface clock to the module" "0,1" textline " " bitfld.long 0x0 5. " EQEP_CLKSTOP_REQ ,This bit controls the clock stop input to the eQEP module : 0: No effect 1: A request to stop interface clock to the module is asserted" "0,1" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8. " EPWM_CLK_EN ,This bit controls the interface clock enable (clk_en) input to the ePWM/eHRPWM module: 0: No effect 1: Enables the interface clock to the module" "0,1" bitfld.long 0x0 9. " EPWM_CLKSTOP_REQ ,This bit controls the clock stop input to the ePWM/eHRPWM module : 0: No effect 1: A request to stop interface clock to the module is asserted" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "PWMSS_CLKSTATUS,The clock status register is used in the PWMSSn (where n = 1 to 3) to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM, eCAP and eQEP submodules within the PWMSSn subsystem. Note:PWMSS Modules Local Clock Gating feature is not supported. Clock gating functionality is controlled by PRCM." bitfld.long 0x0 0. " ECAP_CLK_EN_ACK ,TThis bit is the clk_en status output of the eCAP module : 0: No clock enable request acknowledged 1: Interface clock enable request is acknowledged for the module" "0,1" bitfld.long 0x0 1. " ECAP_CLKSTOP_ACK ,TThis bit is the clkstop_req_ack status output of the eCAP module : 0: No interface clock stop acknowledged 1: Interface clock stop request is acknowledged for the module" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " EQEP_CLK_EN_ACK ,This bit is the clk_en status output of the eQEP module : 0: No clock enable request acknowledged 1: Interface clock enable request is acknowledged for the module" "0,1" textline " " bitfld.long 0x0 5. " EQEP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module : 0: No interface clock stop acknowledged 1: Interface clock stop request is acknowledged for the module" "0,1" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8. " EPWM_CLK_EN_ACK ,This bit is the clk_en status output of the ePWM/eHRPWM module : 0: No clock enable request acknowledged 1: Interface clock enable request is acknowledged for the module" "0,1" bitfld.long 0x0 9. " EPWM_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM/eHRPWM module : 0: No interface clock stop acknowledged 1: Interface clock stop request is acknowledged for the module" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "PWMSS2_CFG" base ad:0x48440000 width 17. group.byte 0x0++0x3 line.long 0x0 "PWMSS_IDVER,IP Revision Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision value" group.byte 0x4++0x3 line.long 0x0 "PWMSS_SYSCONFIG,This register controls the PWMSSn (where n= 1 to 3) local Idle mode clock management and software reset" bitfld.long 0x0 0. " SOFTRESET ,Software reset : 0x0 : Software reset is completed 0x1: Software reset assertion" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, the target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSSn (where n = 1 to 3) for clkstop req and clk_en control to the ePWM/ eHRPWM, eCAP and eQEP submodules within the PWMSSn subsystem. Note: PWMSS Modules Local Clock Gating feature is not supported. This register should not be modified. Clock gating functionality is controlled by PRCM." bitfld.long 0x0 0. " ECAP_CLK_EN ,This bit controls the interface clock enable (clk_en) input to the eCAP module : 0: No effect 1: Enables the interface clock to the module" "0,1" bitfld.long 0x0 1. " ECAP_CLKSTOP_REQ ,This bit controls the clock stop input to the eCAP module : 0: No effect 1: A request to stop interface clock to the module is asserted" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " EQEP_CLK_EN ,This bit controls the interface clock enable (clk_en) input to the eQEP module : 0: No effect 1: Enables the interface clock to the module" "0,1" textline " " bitfld.long 0x0 5. " EQEP_CLKSTOP_REQ ,This bit controls the clock stop input to the eQEP module : 0: No effect 1: A request to stop interface clock to the module is asserted" "0,1" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8. " EPWM_CLK_EN ,This bit controls the interface clock enable (clk_en) input to the ePWM/eHRPWM module: 0: No effect 1: Enables the interface clock to the module" "0,1" bitfld.long 0x0 9. " EPWM_CLKSTOP_REQ ,This bit controls the clock stop input to the ePWM/eHRPWM module : 0: No effect 1: A request to stop interface clock to the module is asserted" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "PWMSS_CLKSTATUS,The clock status register is used in the PWMSSn (where n = 1 to 3) to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM, eCAP and eQEP submodules within the PWMSSn subsystem. Note:PWMSS Modules Local Clock Gating feature is not supported. Clock gating functionality is controlled by PRCM." bitfld.long 0x0 0. " ECAP_CLK_EN_ACK ,TThis bit is the clk_en status output of the eCAP module : 0: No clock enable request acknowledged 1: Interface clock enable request is acknowledged for the module" "0,1" bitfld.long 0x0 1. " ECAP_CLKSTOP_ACK ,TThis bit is the clkstop_req_ack status output of the eCAP module : 0: No interface clock stop acknowledged 1: Interface clock stop request is acknowledged for the module" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " EQEP_CLK_EN_ACK ,This bit is the clk_en status output of the eQEP module : 0: No clock enable request acknowledged 1: Interface clock enable request is acknowledged for the module" "0,1" textline " " bitfld.long 0x0 5. " EQEP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module : 0: No interface clock stop acknowledged 1: Interface clock stop request is acknowledged for the module" "0,1" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8. " EPWM_CLK_EN_ACK ,This bit is the clk_en status output of the ePWM/eHRPWM module : 0: No clock enable request acknowledged 1: Interface clock enable request is acknowledged for the module" "0,1" bitfld.long 0x0 9. " EPWM_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM/eHRPWM module : 0: No interface clock stop acknowledged 1: Interface clock stop request is acknowledged for the module" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "PWMSS3_CFG" base ad:0x48442000 width 17. group.byte 0x0++0x3 line.long 0x0 "PWMSS_IDVER,IP Revision Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision value" group.byte 0x4++0x3 line.long 0x0 "PWMSS_SYSCONFIG,This register controls the PWMSSn (where n= 1 to 3) local Idle mode clock management and software reset" bitfld.long 0x0 0. " SOFTRESET ,Software reset : 0x0 : Software reset is completed 0x1: Software reset assertion" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2.--3. " IDLEMODE ,Configuration of the local target state management mode. By definition, the target can handle read/write transaction as long as it is out of IDLE state." "0,1,2,3" hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PWMSS_CLKCONFIG,The clock configuration register is used in the PWMSSn (where n = 1 to 3) for clkstop req and clk_en control to the ePWM/ eHRPWM, eCAP and eQEP submodules within the PWMSSn subsystem. Note: PWMSS Modules Local Clock Gating feature is not supported. This register should not be modified. Clock gating functionality is controlled by PRCM." bitfld.long 0x0 0. " ECAP_CLK_EN ,This bit controls the interface clock enable (clk_en) input to the eCAP module : 0: No effect 1: Enables the interface clock to the module" "0,1" bitfld.long 0x0 1. " ECAP_CLKSTOP_REQ ,This bit controls the clock stop input to the eCAP module : 0: No effect 1: A request to stop interface clock to the module is asserted" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " EQEP_CLK_EN ,This bit controls the interface clock enable (clk_en) input to the eQEP module : 0: No effect 1: Enables the interface clock to the module" "0,1" textline " " bitfld.long 0x0 5. " EQEP_CLKSTOP_REQ ,This bit controls the clock stop input to the eQEP module : 0: No effect 1: A request to stop interface clock to the module is asserted" "0,1" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8. " EPWM_CLK_EN ,This bit controls the interface clock enable (clk_en) input to the ePWM/eHRPWM module: 0: No effect 1: Enables the interface clock to the module" "0,1" bitfld.long 0x0 9. " EPWM_CLKSTOP_REQ ,This bit controls the clock stop input to the ePWM/eHRPWM module : 0: No effect 1: A request to stop interface clock to the module is asserted" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "PWMSS_CLKSTATUS,The clock status register is used in the PWMSSn (where n = 1 to 3) to indicate clock stop acknowledge (clkstop_ack) and clock enable (clk_en) acknowledge status for the ePWM/ eHRPWM, eCAP and eQEP submodules within the PWMSSn subsystem. Note:PWMSS Modules Local Clock Gating feature is not supported. Clock gating functionality is controlled by PRCM." bitfld.long 0x0 0. " ECAP_CLK_EN_ACK ,TThis bit is the clk_en status output of the eCAP module : 0: No clock enable request acknowledged 1: Interface clock enable request is acknowledged for the module" "0,1" bitfld.long 0x0 1. " ECAP_CLKSTOP_ACK ,TThis bit is the clkstop_req_ack status output of the eCAP module : 0: No interface clock stop acknowledged 1: Interface clock stop request is acknowledged for the module" "0,1" textline " " bitfld.long 0x0 2.--3. " RESERVED ," "0,1,2,3" bitfld.long 0x0 4. " EQEP_CLK_EN_ACK ,This bit is the clk_en status output of the eQEP module : 0: No clock enable request acknowledged 1: Interface clock enable request is acknowledged for the module" "0,1" textline " " bitfld.long 0x0 5. " EQEP_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the eQEP module : 0: No interface clock stop acknowledged 1: Interface clock stop request is acknowledged for the module" "0,1" bitfld.long 0x0 6.--7. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 8. " EPWM_CLK_EN_ACK ,This bit is the clk_en status output of the ePWM/eHRPWM module : 0: No clock enable request acknowledged 1: Interface clock enable request is acknowledged for the module" "0,1" bitfld.long 0x0 9. " EPWM_CLKSTOP_ACK ,This bit is the clkstop_req_ack status output of the ePWM/eHRPWM module : 0: No interface clock stop acknowledged 1: Interface clock stop request is acknowledged for the module" "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "PWMSS1_EPWM" base ad:0x4843E200 width 15. group.byte 0x0++0x1 line.word 0x0 "EPWM_TBCTL,EPWM_TBCTL" bitfld.word 0x0 0.--1. " CTRMODE ,Counter Mode. The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows: 0x0 = Up-count mode 0x1 = Down-count mode 0x2 = Up-down-count mode 0x3 = Stop-freeze counter operation (default on reset)" "0,1,2,3" bitfld.word 0x0 2. " PHSEN ,Counter Register Load From Phase Register Enable 0x0 = Do not load the time-base counter ( 0x1 = Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit." "0,1" textline " " bitfld.word 0x0 3. " PRDLD ,Active Period Register Load From Shadow Register Select 0x0 = The period register ( 0x1 = Load the" "0,1" bitfld.word 0x0 4.--5. " SYNCOSEL ,Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0x0 = EPWMxSYNC: 0x1 = TBCNT = 0: Time-base counter equal to zero ( 0x2 = TBCNT = CMPB : Time-base counter equal to counter-compare B ( 0x3 = Disable EPWMxSYNCO signal" "0,1,2,3" textline " " bitfld.word 0x0 6. " SWFSYNC ,Software Forced Synchronization Pulse. 0x0 = Writing a 0 has no effect and reads always return a 0. 0x1 = Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00." "0,1" bitfld.word 0x0 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value. 0x0 = /1 0x1 = /2 (default on reset) 0x2 = /4 0x3 = /6 0x4 = /8 0x5 = /10 0x6 = /12 0x7 = /14" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 10.--12. " CLKDIV ,Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value. 0x0 = /1 (default on reset) 0x1 = /2 0x2 = /4 0x3 = /8 0x4 = /16 0x5 = /32 0x6 = /64 0x7 = /128" "0,1,2,3,4,5,6,7" bitfld.word 0x0 13. " PHSDIR ,Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter ( 0x0 = Count down after the synchronization event. 0x1 = Count up after the synchronization event." "0,1" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0x0 = Stop after the next time-base counter increment or decrement 0x1 = Stop when counter completes a whole cycle. (a) Up-count mode: stop when the time-base counter = period ( 0x2 = Free run 0x3 = Free run" "0,1,2,3" group.byte 0x2++0x1 line.word 0x0 "EPWM_TBSTS,EPWM_TBSTS" bitfld.word 0x0 0. " CTRDIR ,Time-Base Counter Direction Status Bit. At reset, the counter is frozen, therefore, this bit has no meaning. To make this bit meaningful, you must first set the appropriate mode via 0x0 = Time-Base Counter is currently counting down. 0x1 = Time-Base Counter is currently counting up." "0,1" bitfld.word 0x0 1. " SYNCI ,Input Synchronization Latched Status Bit. 0x0 = Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 0x1 = Reading a 1 on this bit indicates that an external synchronization event has occurred (EPWMxSYNCI). Writing a 1 to this bit will clear the latched event." "0,1" textline " " bitfld.word 0x0 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit. 0x0 = Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 0x1 = Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF. Writing a 1 to this bit will clear the latched event." "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x4++0x1 line.word 0x0 "HRPWM_TBPHSHR,HRPWM_TBPHSHR" hexmask.word.byte 0x0 0.--7. 1. " RESERVED ," hexmask.word.byte 0x0 8.--15. 1. " TBPHSH ,Time-base phase high-resolution bits" group.byte 0x6++0x1 line.word 0x0 "EPWM_TBPHS,EPWM_TBPHS" hexmask.word 0x0 0.--15. 1. " TBPHS ,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. (a) If" group.byte 0x8++0x1 line.word 0x0 "EPWM_TBCNT,EPWM_TBCNT" hexmask.word 0x0 0.--15. 1. " TBCNT ,Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs. The write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed." group.byte 0xA++0x1 line.word 0x0 "EPWM_TBPRD,EPWM_TBPRD" hexmask.word 0x0 0.--15. 1. " TBPRD ,These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the" group.byte 0xE++0x1 line.word 0x0 "EPWM_CMPCTL,EPWM_CMPCTL" bitfld.word 0x0 0.--1. " LOADAMODE ,Active Counter-Compare A ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "0,1,2,3" bitfld.word 0x0 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode. This bit has no effect in immediate mode ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "0,1,2,3" textline " " bitfld.word 0x0 4. " SHDWAMODE ,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action" "0,1" bitfld.word 0x0 5. " RESERVED ," "0,1" textline " " bitfld.word 0x0 6. " SHDWBMODE ,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action." "0,1" bitfld.word 0x0 7. " RESERVED ," "0,1" textline " " bitfld.word 0x0 8. " SHDWAFULL ,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value." "0,1" bitfld.word 0x0 9. " SHDWBFULL ,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value." "0,1" textline " " bitfld.word 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x1 line.word 0x0 "HRPWM_CMPAHR,HRPWM_CMPAHR" hexmask.word.byte 0x0 0.--7. 1. " RESERVED ," hexmask.word.byte 0x0 8.--15. 1. " CMPAHR ,Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation 1-255h." group.byte 0x12++0x1 line.word 0x0 "EPWM_CMPA,EPWM_CMPA" hexmask.word 0x0 0.--15. 1. " CMPA ,The value in the active" group.byte 0x14++0x1 line.word 0x0 "EPWM_CMPB,EPWM_CMPB" hexmask.word 0x0 0.--15. 1. " CMPB ,The value in the active" group.byte 0x16++0x1 line.word 0x0 "EPWM_AQCTLA,EPWM_AQCTLA" bitfld.word 0x0 0.--1. " ZRO ,Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 2.--3. " PRD ,Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 4.--5. " CAU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 6.--7. " CAD ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 8.--9. " CBU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 10.--11. " CBD ,Action when the time-base counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x18++0x1 line.word 0x0 "EPWM_AQCTLB,EPWM_AQCTLB" bitfld.word 0x0 0.--1. " ZRO ,Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 2.--3. " PRD ,Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 4.--5. " CAU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 6.--7. " CAD ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 8.--9. " CBU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 10.--11. " CBD ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1A++0x1 line.word 0x0 "EPWM_AQSFRC,EPWM_AQSFRC" bitfld.word 0x0 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked. 0x0 = Does nothing (action disabled). 0x1 = Clear (low). 0x2 = Set (high). 0x3 = Toggle (Low -> High, High -> Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0x0 2. " OTSFA ,One-Time Software Forced Event on Output A. 0x0 = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated). 0x1 = Initiates a single software forced event." "0,1" textline " " bitfld.word 0x0 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked 0x0 = Does nothing (action disabled) 0x1 = Clear (low) 0x2 = Set (high) 0x3 = Toggle (Low -> High, High -> Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0x0 5. " OTSFB ,One-Time Software Forced Event on Output B. 0x0 = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete, that is, a forced event is initiated. This is a one-shot forced event. It can be overridden by another subsequent event on output B. 0x1 = Initiates a single s/w forced event" "0,1" textline " " bitfld.word 0x0 6.--7. " RLDCSF ,0x0 = Load on event counter equals zero 0x1 = Load on event counter equals period 0x2 = Load on event counter equals zero or counter equals period 0x3 = Load immediately (the active register is directly accessed by the CPU and is not loaded from the shadow register)." "0,1,2,3" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x1C++0x1 line.word 0x0 "EPWM_AQCSFRC,EPWM_AQCSFRC" bitfld.word 0x0 0.--1. " CSFA ,Continuous Software Force on Output A In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0x0 = Forcing disabled, that is, has no effect 0x1 = Forces a continuous low on output A 0x2 = Forces a continuous high on output A 0x3 = Software forcing is disabled and has no effect" "0,1,2,3" bitfld.word 0x0 2.--3. " CSFB ,Continuous Software Force on Output B. In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use 0x0 = Forcing disabled, that is, has no effect 0x1 = Forces a continuous low on output B 0x2 = Forces a continuous high on output B 0x3 = Software forcing is disabled and has no effect" "0,1,2,3" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x1E++0x1 line.word 0x0 "EPWM_DBCTL,EPWM_DBCTL" bitfld.word 0x0 0.--1. " OUT_MODE ,Dead-band Output Mode Control. Bit 1 controls the S1 switch and bit 0 controls the S0 switch. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0x0 = Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule. In this mode, the POLSEL and IN_MODE bits have no effect. 0x1 = Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to the EPWMxA input of the PWM-chopper submodule. The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined by 0x2 = Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to the EPWMxB input of the PWM-chopper submodule. The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined by 0x3 = Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by" "0,1,2,3" bitfld.word 0x0 2.--3. " POLSEL ,Polarity Select Control. Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that 0x0 = Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default). 0x1 = Active low complementary (ALC) mode. EPWMxA is inverted. 0x2 = Active high complementary (AHC). EPWMxB is inverted. 0x3 = Active low (AL) mode. Both EPWMxA and EPWMxB are inverted." "0,1,2,3" textline " " bitfld.word 0x0 4.--5. " IN_MODE ,Dead Band Input Mode Control. Bit 5 controls the S5 switch and bit 4 controls the S4 switch. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms, the default is EPWMxA In is the source for both falling and rising-edge delays. 0x0 = EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay. 0x1 = EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal. 0x2 = EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal. 0x3 = EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal." "0,1,2,3" hexmask.word 0x0 6.--15. 1. " RESERVED ," group.byte 0x20++0x1 line.word 0x0 "EPWM_DBRED,EPWM_DBRED" hexmask.word 0x0 0.--9. 1. " DEL ,Rising Edge Delay Count. 10 bit counter." bitfld.word 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x22++0x1 line.word 0x0 "EPWM_DBFED,EPWM_DBFED" hexmask.word 0x0 0.--9. 1. " DEL ,Falling Edge Delay Count. 10 bit counter" bitfld.word 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x24++0x1 line.word 0x0 "EPWM_TZSEL,EPWM_TZSEL" bitfld.word 0x0 0. " CBC0 ,Trip-zone 0 (TZ0) select. Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low, a cycle-by-cycle trip event occurs for this ePWM module. When the event occurs, the action defined in the 0x0 = Disable TZ0 as a CBC trip source for this ePWM module. 0x1 = Enable TZ0 as a CBC trip source for this ePWM module." "0,1" hexmask.word.byte 0x0 1.--7. 1. " RESERVED ," textline " " hexmask.word.byte 0x0 8.--15. 1. " OSHTN ,Trip-zone n (TZn) select. One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low, a one-shot trip event occurs for this ePWM module. When the event occurs, the action defined in the 0x0 = Disable TZn as a one-shot trip source for this ePWM module. 0x1 = Enable TZn as a one-shot trip source for this ePWM module." group.byte 0x28++0x1 line.word 0x0 "EPWM_TZCTL,EPWM_TZCTL" bitfld.word 0x0 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the 0x0 = High impedance (EPWMxA = High-impedance state) 0x1 = Force EPWMxA to a high state 0x2 = Force EPWMxA to a low state 0x3 = Do nothing, no action is taken on EPWMxA." "0,1,2,3" bitfld.word 0x0 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the 0x0 = High impedance (EPWMxB = High-impedance state) 0x1 = Force EPWMxB to a high state 0x2 = Force EPWMxB to a low state 0x3 = Do nothing, no action is taken on EPWMxB." "0,1,2,3" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x2A++0x1 line.word 0x0 "EPWM_TZEINT,EPWM_TZEINT" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable 0x0 = Disable cycle-by-cycle interrupt generation. 0x1 = Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMxTZINT interrupt." "0,1" textline " " bitfld.word 0x0 2. " OST ,Trip-zone One-Shot Interrupt Enable 0x0 = Disable one-shot interrupt generation 0x1 = Enable Interrupt generation; a one-shot trip event will cause a EPWMxTZINT interrupt." "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x2C++0x1 line.word 0x0 "EPWM_TZFLG,EPWM_TZFLG" bitfld.word 0x0 0. " INT ,Latched Trip Interrupt Status Flag 0x0 = Indicates no interrupt has been generated. 0x1 = Indicates an EPWMxTZINT interrupt was generated because of a trip condition. No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the" "0,1" bitfld.word 0x0 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event 0x0 = No cycle-by-cycle trip event has occurred. 0x1 = Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The" "0,1" textline " " bitfld.word 0x0 2. " OST ,Latched Status Flag for A One-Shot Trip Event. 0x0 = No one-shot trip event has occurred. 0x1 = Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the" "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "EPWM_TZCLR,EPWM_TZCLR" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Has no effect. Always reads back a 0. 0x1 = Clears the trip-interrupt flag for this ePWM module (" "0,1" bitfld.word 0x0 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0x0 = Has no effect. Always reads back a 0. 0x1 = Clears this Trip (set) condition." "0,1" textline " " bitfld.word 0x0 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch 0x0 = Has no effect. Always reads back a 0. 0x1 = Clears this Trip (set) condition." "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "EPWM_TZFRC,EPWM_TZFRC" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software 0x0 = Writing of 0 is ignored. Always reads back a 0. 0x1 = Forces a cycle-by-cycle trip event and sets the" "0,1" textline " " bitfld.word 0x0 2. " OST ,Force a One-Shot Trip Event via Software 0x0 = Writing of 0 is ignored. Always reads back a 0. 0x1 = Forces a one-shot trip event and sets the" "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x32++0x1 line.word 0x0 "EPWM_ETSEL,EPWM_ETSEL" bitfld.word 0x0 0.--2. " INTSEL ,ePWM Interrupt (EPWMx_INT) Selection Options 0x0 = Reserved 0x1 = Enable event time-base counter equal to zero. (TBCNT = 0000h) 0x2 = Enable event time-base counter equal to period (TBCNT = TBPRD) 0x3 = Reserved 0x4 = Enable event time-base counter equal to CMPA when the timer is incrementing. 0x5 = Enable event time-base counter equal to CMPA when the timer is decrementing. 0x6 = Enable event: time-base counter equal to CMPB when the timer is incrementing. 0x7 = Enable event: time-base counter equal to CMPB when the timer is decrementing." "0,1,2,3,4,5,6,7" bitfld.word 0x0 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation 0x0 = Disable EPWMx_INT generation 0x1 = Enable EPWMx_INT generation" "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x34++0x1 line.word 0x0 "EPWM_ETPS,EPWM_ETPS" bitfld.word 0x0 0.--1. " INTPRD ,ePWM Interrupt (EPWMx_INT) Period Select. These bits determine how many selected 0x0 = Disable the interrupt event counter. No interrupt will be generated and 0x1 = Generate an interrupt on the first event INTCNT = 01 (first event) 0x2 = Generate interrupt on 0x3 = Generate interrupt on" "0,1,2,3" bitfld.word 0x0 2.--3. " INTCNT ,ePWM Interrupt Event (EPWMx_INT) Counter Register. These bits indicate how many selected 0x0 = No events have occurred. 0x1 = 1 event has occurred. 0x2 = 2 events have occurred. 0x3 = 3 events have occurred." "0,1,2,3" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x36++0x1 line.word 0x0 "EPWM_ETFLG,EPWM_ETFLG" bitfld.word 0x0 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0x0 = Indicates no event occurred 0x1 = Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending while the" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ," group.byte 0x38++0x1 line.word 0x0 "EPWM_ETCLR,EPWM_ETCLR" bitfld.word 0x0 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing 1 clears the" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ," group.byte 0x3A++0x1 line.word 0x0 "EPWM_ETFRC,EPWM_ETFRC" bitfld.word 0x0 0. " INT ,INT Force Bit. The interrupt will only be generated if the event is enabled in the 0x0 = Writing 0 to this bit will be ignored. Always reads back a 0. 0x1 = Writing 1 generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ," group.byte 0x3C++0x1 line.word 0x0 "EPWM_PCCTL,EPWM_PCCTL" bitfld.word 0x0 0. " CHPEN ,PWM-chopping Enable 0x0 = Disable (bypass) PWM chopping function 0x1 = Enable chopping function" "0,1" bitfld.word 0x0 1.--4. " OSHTWTH ,One-Shot Pulse Width 0x0 = 1 - SYSCLKOUT/8 wide 0x1 = 2 - SYSCLKOUT/8 wide 0x2 = 3 - SYSCLKOUT/8 wide 0x3 = 4 - SYSCLKOUT/8 wide 0xF = 16 - SYSCLKOUT/8 wide" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0 5.--7. " CHPFREQ ,Chopping Clock Frequency 0x0 = Divide by 1 (no prescale). 0x1 = Divide by 2. 0x2 = Divide by 3. 0x3 = Divide by 4. 0x4 = Divide by 5. 0x5 = Divide by 6. 0x6 = Divide by 7. 0x7 = Divide by 8." "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle 0x0 = Duty = 1/8 (12.5%) 0x1 = Duty = 2/8 (25.0%) 0x2 = Duty = 3/8 (37.5%) 0x3 = Duty = 4/8 (50.0%) 0x4 = Duty = 5/8 (62.5%) 0x5 = Duty = 6/8 (75.0%) 0x6 = Duty = 7/8 (87.5%) 0x7 = Reserved." "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xC0++0x1 line.word 0x0 "HRPWM_HRCTL,HRPWM_HRCTL" bitfld.word 0x0 0.--1. " DELMODE ,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted. Note: When DELMODE = 0b00, the HRCALM[CALMODE] bits are ignored and the delay line is in by-pass mode. Additionally, DLYIN is connected to CALIN and a continuous low value is fed to the delay line to minimize activity in the module. 0x0 = No delay inserted (default on reset) 0x1 = Delay inserted rising edge 0x2 = Delay inserted falling edge 0x3 = Delay inserted on both edges" "0,1,2,3" bitfld.word 0x0 2. " DELBUSSEL ,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse. 0x0 = Select CMPAHR(8) bus from compare module of EPWM (default on reset). 0x1 = Select TBPHSHR(8) bus from time base module." "0,1" textline " " bitfld.word 0x0 3. " PULSESEL ,Pulse select bits. Selects which pulse to use for timing events in the HRPWM module. Note: The user needs to select the pulse to match the selection in the EPWM module. If TBPHSHR bus is selected, then CNT_zero pulse should be used. If COMPAHR bus is selected, then it should match the bit setting of the 0x0 = Select CNT_zero pulse 0x1 = Select PRD_eq pulse" "0,1" hexmask.word 0x0 4.--15. 1. " RESERVED ," width 0x0B tree.end tree "PWMSS2_EPWM" base ad:0x48440200 width 15. group.byte 0x0++0x1 line.word 0x0 "EPWM_TBCTL,EPWM_TBCTL" bitfld.word 0x0 0.--1. " CTRMODE ,Counter Mode. The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows: 0x0 = Up-count mode 0x1 = Down-count mode 0x2 = Up-down-count mode 0x3 = Stop-freeze counter operation (default on reset)" "0,1,2,3" bitfld.word 0x0 2. " PHSEN ,Counter Register Load From Phase Register Enable 0x0 = Do not load the time-base counter ( 0x1 = Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit." "0,1" textline " " bitfld.word 0x0 3. " PRDLD ,Active Period Register Load From Shadow Register Select 0x0 = The period register ( 0x1 = Load the" "0,1" bitfld.word 0x0 4.--5. " SYNCOSEL ,Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0x0 = EPWMxSYNC: 0x1 = TBCNT = 0: Time-base counter equal to zero ( 0x2 = TBCNT = CMPB : Time-base counter equal to counter-compare B ( 0x3 = Disable EPWMxSYNCO signal" "0,1,2,3" textline " " bitfld.word 0x0 6. " SWFSYNC ,Software Forced Synchronization Pulse. 0x0 = Writing a 0 has no effect and reads always return a 0. 0x1 = Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00." "0,1" bitfld.word 0x0 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value. 0x0 = /1 0x1 = /2 (default on reset) 0x2 = /4 0x3 = /6 0x4 = /8 0x5 = /10 0x6 = /12 0x7 = /14" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 10.--12. " CLKDIV ,Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value. 0x0 = /1 (default on reset) 0x1 = /2 0x2 = /4 0x3 = /8 0x4 = /16 0x5 = /32 0x6 = /64 0x7 = /128" "0,1,2,3,4,5,6,7" bitfld.word 0x0 13. " PHSDIR ,Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter ( 0x0 = Count down after the synchronization event. 0x1 = Count up after the synchronization event." "0,1" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0x0 = Stop after the next time-base counter increment or decrement 0x1 = Stop when counter completes a whole cycle. (a) Up-count mode: stop when the time-base counter = period ( 0x2 = Free run 0x3 = Free run" "0,1,2,3" group.byte 0x2++0x1 line.word 0x0 "EPWM_TBSTS,EPWM_TBSTS" bitfld.word 0x0 0. " CTRDIR ,Time-Base Counter Direction Status Bit. At reset, the counter is frozen, therefore, this bit has no meaning. To make this bit meaningful, you must first set the appropriate mode via 0x0 = Time-Base Counter is currently counting down. 0x1 = Time-Base Counter is currently counting up." "0,1" bitfld.word 0x0 1. " SYNCI ,Input Synchronization Latched Status Bit. 0x0 = Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 0x1 = Reading a 1 on this bit indicates that an external synchronization event has occurred (EPWMxSYNCI). Writing a 1 to this bit will clear the latched event." "0,1" textline " " bitfld.word 0x0 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit. 0x0 = Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 0x1 = Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF. Writing a 1 to this bit will clear the latched event." "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x4++0x1 line.word 0x0 "HRPWM_TBPHSHR,HRPWM_TBPHSHR" hexmask.word.byte 0x0 0.--7. 1. " RESERVED ," hexmask.word.byte 0x0 8.--15. 1. " TBPHSH ,Time-base phase high-resolution bits" group.byte 0x6++0x1 line.word 0x0 "EPWM_TBPHS,EPWM_TBPHS" hexmask.word 0x0 0.--15. 1. " TBPHS ,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. (a) If" group.byte 0x8++0x1 line.word 0x0 "EPWM_TBCNT,EPWM_TBCNT" hexmask.word 0x0 0.--15. 1. " TBCNT ,Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs. The write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed." group.byte 0xA++0x1 line.word 0x0 "EPWM_TBPRD,EPWM_TBPRD" hexmask.word 0x0 0.--15. 1. " TBPRD ,These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the" group.byte 0xE++0x1 line.word 0x0 "EPWM_CMPCTL,EPWM_CMPCTL" bitfld.word 0x0 0.--1. " LOADAMODE ,Active Counter-Compare A ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "0,1,2,3" bitfld.word 0x0 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode. This bit has no effect in immediate mode ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "0,1,2,3" textline " " bitfld.word 0x0 4. " SHDWAMODE ,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action" "0,1" bitfld.word 0x0 5. " RESERVED ," "0,1" textline " " bitfld.word 0x0 6. " SHDWBMODE ,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action." "0,1" bitfld.word 0x0 7. " RESERVED ," "0,1" textline " " bitfld.word 0x0 8. " SHDWAFULL ,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value." "0,1" bitfld.word 0x0 9. " SHDWBFULL ,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value." "0,1" textline " " bitfld.word 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x1 line.word 0x0 "HRPWM_CMPAHR,HRPWM_CMPAHR" hexmask.word.byte 0x0 0.--7. 1. " RESERVED ," hexmask.word.byte 0x0 8.--15. 1. " CMPAHR ,Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation 1-255h." group.byte 0x12++0x1 line.word 0x0 "EPWM_CMPA,EPWM_CMPA" hexmask.word 0x0 0.--15. 1. " CMPA ,The value in the active" group.byte 0x14++0x1 line.word 0x0 "EPWM_CMPB,EPWM_CMPB" hexmask.word 0x0 0.--15. 1. " CMPB ,The value in the active" group.byte 0x16++0x1 line.word 0x0 "EPWM_AQCTLA,EPWM_AQCTLA" bitfld.word 0x0 0.--1. " ZRO ,Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 2.--3. " PRD ,Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 4.--5. " CAU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 6.--7. " CAD ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 8.--9. " CBU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 10.--11. " CBD ,Action when the time-base counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x18++0x1 line.word 0x0 "EPWM_AQCTLB,EPWM_AQCTLB" bitfld.word 0x0 0.--1. " ZRO ,Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 2.--3. " PRD ,Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 4.--5. " CAU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 6.--7. " CAD ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 8.--9. " CBU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 10.--11. " CBD ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1A++0x1 line.word 0x0 "EPWM_AQSFRC,EPWM_AQSFRC" bitfld.word 0x0 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked. 0x0 = Does nothing (action disabled). 0x1 = Clear (low). 0x2 = Set (high). 0x3 = Toggle (Low -> High, High -> Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0x0 2. " OTSFA ,One-Time Software Forced Event on Output A. 0x0 = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated). 0x1 = Initiates a single software forced event." "0,1" textline " " bitfld.word 0x0 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked 0x0 = Does nothing (action disabled) 0x1 = Clear (low) 0x2 = Set (high) 0x3 = Toggle (Low -> High, High -> Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0x0 5. " OTSFB ,One-Time Software Forced Event on Output B. 0x0 = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete, that is, a forced event is initiated. This is a one-shot forced event. It can be overridden by another subsequent event on output B. 0x1 = Initiates a single s/w forced event" "0,1" textline " " bitfld.word 0x0 6.--7. " RLDCSF ,0x0 = Load on event counter equals zero 0x1 = Load on event counter equals period 0x2 = Load on event counter equals zero or counter equals period 0x3 = Load immediately (the active register is directly accessed by the CPU and is not loaded from the shadow register)." "0,1,2,3" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x1C++0x1 line.word 0x0 "EPWM_AQCSFRC,EPWM_AQCSFRC" bitfld.word 0x0 0.--1. " CSFA ,Continuous Software Force on Output A In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0x0 = Forcing disabled, that is, has no effect 0x1 = Forces a continuous low on output A 0x2 = Forces a continuous high on output A 0x3 = Software forcing is disabled and has no effect" "0,1,2,3" bitfld.word 0x0 2.--3. " CSFB ,Continuous Software Force on Output B. In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use 0x0 = Forcing disabled, that is, has no effect 0x1 = Forces a continuous low on output B 0x2 = Forces a continuous high on output B 0x3 = Software forcing is disabled and has no effect" "0,1,2,3" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x1E++0x1 line.word 0x0 "EPWM_DBCTL,EPWM_DBCTL" bitfld.word 0x0 0.--1. " OUT_MODE ,Dead-band Output Mode Control. Bit 1 controls the S1 switch and bit 0 controls the S0 switch. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0x0 = Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule. In this mode, the POLSEL and IN_MODE bits have no effect. 0x1 = Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to the EPWMxA input of the PWM-chopper submodule. The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined by 0x2 = Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to the EPWMxB input of the PWM-chopper submodule. The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined by 0x3 = Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by" "0,1,2,3" bitfld.word 0x0 2.--3. " POLSEL ,Polarity Select Control. Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that 0x0 = Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default). 0x1 = Active low complementary (ALC) mode. EPWMxA is inverted. 0x2 = Active high complementary (AHC). EPWMxB is inverted. 0x3 = Active low (AL) mode. Both EPWMxA and EPWMxB are inverted." "0,1,2,3" textline " " bitfld.word 0x0 4.--5. " IN_MODE ,Dead Band Input Mode Control. Bit 5 controls the S5 switch and bit 4 controls the S4 switch. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms, the default is EPWMxA In is the source for both falling and rising-edge delays. 0x0 = EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay. 0x1 = EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal. 0x2 = EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal. 0x3 = EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal." "0,1,2,3" hexmask.word 0x0 6.--15. 1. " RESERVED ," group.byte 0x20++0x1 line.word 0x0 "EPWM_DBRED,EPWM_DBRED" hexmask.word 0x0 0.--9. 1. " DEL ,Rising Edge Delay Count. 10 bit counter." bitfld.word 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x22++0x1 line.word 0x0 "EPWM_DBFED,EPWM_DBFED" hexmask.word 0x0 0.--9. 1. " DEL ,Falling Edge Delay Count. 10 bit counter" bitfld.word 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x24++0x1 line.word 0x0 "EPWM_TZSEL,EPWM_TZSEL" bitfld.word 0x0 0. " CBC0 ,Trip-zone 0 (TZ0) select. Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low, a cycle-by-cycle trip event occurs for this ePWM module. When the event occurs, the action defined in the 0x0 = Disable TZ0 as a CBC trip source for this ePWM module. 0x1 = Enable TZ0 as a CBC trip source for this ePWM module." "0,1" hexmask.word.byte 0x0 1.--7. 1. " RESERVED ," textline " " hexmask.word.byte 0x0 8.--15. 1. " OSHTN ,Trip-zone n (TZn) select. One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low, a one-shot trip event occurs for this ePWM module. When the event occurs, the action defined in the 0x0 = Disable TZn as a one-shot trip source for this ePWM module. 0x1 = Enable TZn as a one-shot trip source for this ePWM module." group.byte 0x28++0x1 line.word 0x0 "EPWM_TZCTL,EPWM_TZCTL" bitfld.word 0x0 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the 0x0 = High impedance (EPWMxA = High-impedance state) 0x1 = Force EPWMxA to a high state 0x2 = Force EPWMxA to a low state 0x3 = Do nothing, no action is taken on EPWMxA." "0,1,2,3" bitfld.word 0x0 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the 0x0 = High impedance (EPWMxB = High-impedance state) 0x1 = Force EPWMxB to a high state 0x2 = Force EPWMxB to a low state 0x3 = Do nothing, no action is taken on EPWMxB." "0,1,2,3" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x2A++0x1 line.word 0x0 "EPWM_TZEINT,EPWM_TZEINT" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable 0x0 = Disable cycle-by-cycle interrupt generation. 0x1 = Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMxTZINT interrupt." "0,1" textline " " bitfld.word 0x0 2. " OST ,Trip-zone One-Shot Interrupt Enable 0x0 = Disable one-shot interrupt generation 0x1 = Enable Interrupt generation; a one-shot trip event will cause a EPWMxTZINT interrupt." "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x2C++0x1 line.word 0x0 "EPWM_TZFLG,EPWM_TZFLG" bitfld.word 0x0 0. " INT ,Latched Trip Interrupt Status Flag 0x0 = Indicates no interrupt has been generated. 0x1 = Indicates an EPWMxTZINT interrupt was generated because of a trip condition. No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the" "0,1" bitfld.word 0x0 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event 0x0 = No cycle-by-cycle trip event has occurred. 0x1 = Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The" "0,1" textline " " bitfld.word 0x0 2. " OST ,Latched Status Flag for A One-Shot Trip Event. 0x0 = No one-shot trip event has occurred. 0x1 = Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the" "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "EPWM_TZCLR,EPWM_TZCLR" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Has no effect. Always reads back a 0. 0x1 = Clears the trip-interrupt flag for this ePWM module (" "0,1" bitfld.word 0x0 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0x0 = Has no effect. Always reads back a 0. 0x1 = Clears this Trip (set) condition." "0,1" textline " " bitfld.word 0x0 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch 0x0 = Has no effect. Always reads back a 0. 0x1 = Clears this Trip (set) condition." "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "EPWM_TZFRC,EPWM_TZFRC" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software 0x0 = Writing of 0 is ignored. Always reads back a 0. 0x1 = Forces a cycle-by-cycle trip event and sets the" "0,1" textline " " bitfld.word 0x0 2. " OST ,Force a One-Shot Trip Event via Software 0x0 = Writing of 0 is ignored. Always reads back a 0. 0x1 = Forces a one-shot trip event and sets the" "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x32++0x1 line.word 0x0 "EPWM_ETSEL,EPWM_ETSEL" bitfld.word 0x0 0.--2. " INTSEL ,ePWM Interrupt (EPWMx_INT) Selection Options 0x0 = Reserved 0x1 = Enable event time-base counter equal to zero. (TBCNT = 0000h) 0x2 = Enable event time-base counter equal to period (TBCNT = TBPRD) 0x3 = Reserved 0x4 = Enable event time-base counter equal to CMPA when the timer is incrementing. 0x5 = Enable event time-base counter equal to CMPA when the timer is decrementing. 0x6 = Enable event: time-base counter equal to CMPB when the timer is incrementing. 0x7 = Enable event: time-base counter equal to CMPB when the timer is decrementing." "0,1,2,3,4,5,6,7" bitfld.word 0x0 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation 0x0 = Disable EPWMx_INT generation 0x1 = Enable EPWMx_INT generation" "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x34++0x1 line.word 0x0 "EPWM_ETPS,EPWM_ETPS" bitfld.word 0x0 0.--1. " INTPRD ,ePWM Interrupt (EPWMx_INT) Period Select. These bits determine how many selected 0x0 = Disable the interrupt event counter. No interrupt will be generated and 0x1 = Generate an interrupt on the first event INTCNT = 01 (first event) 0x2 = Generate interrupt on 0x3 = Generate interrupt on" "0,1,2,3" bitfld.word 0x0 2.--3. " INTCNT ,ePWM Interrupt Event (EPWMx_INT) Counter Register. These bits indicate how many selected 0x0 = No events have occurred. 0x1 = 1 event has occurred. 0x2 = 2 events have occurred. 0x3 = 3 events have occurred." "0,1,2,3" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x36++0x1 line.word 0x0 "EPWM_ETFLG,EPWM_ETFLG" bitfld.word 0x0 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0x0 = Indicates no event occurred 0x1 = Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending while the" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ," group.byte 0x38++0x1 line.word 0x0 "EPWM_ETCLR,EPWM_ETCLR" bitfld.word 0x0 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing 1 clears the" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ," group.byte 0x3A++0x1 line.word 0x0 "EPWM_ETFRC,EPWM_ETFRC" bitfld.word 0x0 0. " INT ,INT Force Bit. The interrupt will only be generated if the event is enabled in the 0x0 = Writing 0 to this bit will be ignored. Always reads back a 0. 0x1 = Writing 1 generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ," group.byte 0x3C++0x1 line.word 0x0 "EPWM_PCCTL,EPWM_PCCTL" bitfld.word 0x0 0. " CHPEN ,PWM-chopping Enable 0x0 = Disable (bypass) PWM chopping function 0x1 = Enable chopping function" "0,1" bitfld.word 0x0 1.--4. " OSHTWTH ,One-Shot Pulse Width 0x0 = 1 - SYSCLKOUT/8 wide 0x1 = 2 - SYSCLKOUT/8 wide 0x2 = 3 - SYSCLKOUT/8 wide 0x3 = 4 - SYSCLKOUT/8 wide 0xF = 16 - SYSCLKOUT/8 wide" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0 5.--7. " CHPFREQ ,Chopping Clock Frequency 0x0 = Divide by 1 (no prescale). 0x1 = Divide by 2. 0x2 = Divide by 3. 0x3 = Divide by 4. 0x4 = Divide by 5. 0x5 = Divide by 6. 0x6 = Divide by 7. 0x7 = Divide by 8." "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle 0x0 = Duty = 1/8 (12.5%) 0x1 = Duty = 2/8 (25.0%) 0x2 = Duty = 3/8 (37.5%) 0x3 = Duty = 4/8 (50.0%) 0x4 = Duty = 5/8 (62.5%) 0x5 = Duty = 6/8 (75.0%) 0x6 = Duty = 7/8 (87.5%) 0x7 = Reserved." "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xC0++0x1 line.word 0x0 "HRPWM_HRCTL,HRPWM_HRCTL" bitfld.word 0x0 0.--1. " DELMODE ,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted. Note: When DELMODE = 0b00, the HRCALM[CALMODE] bits are ignored and the delay line is in by-pass mode. Additionally, DLYIN is connected to CALIN and a continuous low value is fed to the delay line to minimize activity in the module. 0x0 = No delay inserted (default on reset) 0x1 = Delay inserted rising edge 0x2 = Delay inserted falling edge 0x3 = Delay inserted on both edges" "0,1,2,3" bitfld.word 0x0 2. " DELBUSSEL ,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse. 0x0 = Select CMPAHR(8) bus from compare module of EPWM (default on reset). 0x1 = Select TBPHSHR(8) bus from time base module." "0,1" textline " " bitfld.word 0x0 3. " PULSESEL ,Pulse select bits. Selects which pulse to use for timing events in the HRPWM module. Note: The user needs to select the pulse to match the selection in the EPWM module. If TBPHSHR bus is selected, then CNT_zero pulse should be used. If COMPAHR bus is selected, then it should match the bit setting of the 0x0 = Select CNT_zero pulse 0x1 = Select PRD_eq pulse" "0,1" hexmask.word 0x0 4.--15. 1. " RESERVED ," width 0x0B tree.end tree "PWMSS3_EPWM" base ad:0x48442200 width 15. group.byte 0x0++0x1 line.word 0x0 "EPWM_TBCTL,EPWM_TBCTL" bitfld.word 0x0 0.--1. " CTRMODE ,Counter Mode. The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows: 0x0 = Up-count mode 0x1 = Down-count mode 0x2 = Up-down-count mode 0x3 = Stop-freeze counter operation (default on reset)" "0,1,2,3" bitfld.word 0x0 2. " PHSEN ,Counter Register Load From Phase Register Enable 0x0 = Do not load the time-base counter ( 0x1 = Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit." "0,1" textline " " bitfld.word 0x0 3. " PRDLD ,Active Period Register Load From Shadow Register Select 0x0 = The period register ( 0x1 = Load the" "0,1" bitfld.word 0x0 4.--5. " SYNCOSEL ,Synchronization Output Select. These bits select the source of the EPWMxSYNCO signal. 0x0 = EPWMxSYNC: 0x1 = TBCNT = 0: Time-base counter equal to zero ( 0x2 = TBCNT = CMPB : Time-base counter equal to counter-compare B ( 0x3 = Disable EPWMxSYNCO signal" "0,1,2,3" textline " " bitfld.word 0x0 6. " SWFSYNC ,Software Forced Synchronization Pulse. 0x0 = Writing a 0 has no effect and reads always return a 0. 0x1 = Writing a 1 forces a one-time synchronization pulse to be generated. This event is ORed with the EPWMxSYNCI input of the ePWM module. SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00." "0,1" bitfld.word 0x0 7.--9. " HSPCLKDIV ,High-Speed Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value. 0x0 = /1 0x1 = /2 (default on reset) 0x2 = /4 0x3 = /6 0x4 = /8 0x5 = /10 0x6 = /12 0x7 = /14" "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 10.--12. " CLKDIV ,Time-base Clock Prescale Bits. These bits determine part of the time-base clock prescale value. 0x0 = /1 (default on reset) 0x1 = /2 0x2 = /4 0x3 = /8 0x4 = /16 0x5 = /32 0x6 = /64 0x7 = /128" "0,1,2,3,4,5,6,7" bitfld.word 0x0 13. " PHSDIR ,Phase Direction Bit. This bit is only used when the time-base counter is configured in the up-down-count mode. The PHSDIR bit indicates the direction the time-base counter ( 0x0 = Count down after the synchronization event. 0x1 = Count up after the synchronization event." "0,1" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events: 0x0 = Stop after the next time-base counter increment or decrement 0x1 = Stop when counter completes a whole cycle. (a) Up-count mode: stop when the time-base counter = period ( 0x2 = Free run 0x3 = Free run" "0,1,2,3" group.byte 0x2++0x1 line.word 0x0 "EPWM_TBSTS,EPWM_TBSTS" bitfld.word 0x0 0. " CTRDIR ,Time-Base Counter Direction Status Bit. At reset, the counter is frozen, therefore, this bit has no meaning. To make this bit meaningful, you must first set the appropriate mode via 0x0 = Time-Base Counter is currently counting down. 0x1 = Time-Base Counter is currently counting up." "0,1" bitfld.word 0x0 1. " SYNCI ,Input Synchronization Latched Status Bit. 0x0 = Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred. 0x1 = Reading a 1 on this bit indicates that an external synchronization event has occurred (EPWMxSYNCI). Writing a 1 to this bit will clear the latched event." "0,1" textline " " bitfld.word 0x0 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit. 0x0 = Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect. 0x1 = Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF. Writing a 1 to this bit will clear the latched event." "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x4++0x1 line.word 0x0 "HRPWM_TBPHSHR,HRPWM_TBPHSHR" hexmask.word.byte 0x0 0.--7. 1. " RESERVED ," hexmask.word.byte 0x0 8.--15. 1. " TBPHSH ,Time-base phase high-resolution bits" group.byte 0x6++0x1 line.word 0x0 "EPWM_TBPHS,EPWM_TBPHS" hexmask.word 0x0 0.--15. 1. " TBPHS ,These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal. (a) If" group.byte 0x8++0x1 line.word 0x0 "EPWM_TBCNT,EPWM_TBCNT" hexmask.word 0x0 0.--15. 1. " TBCNT ,Reading these bits gives the current time-base counter value. Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs. The write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed." group.byte 0xA++0x1 line.word 0x0 "EPWM_TBPRD,EPWM_TBPRD" hexmask.word 0x0 0.--15. 1. " TBPRD ,These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the" group.byte 0xE++0x1 line.word 0x0 "EPWM_CMPCTL,EPWM_CMPCTL" bitfld.word 0x0 0.--1. " LOADAMODE ,Active Counter-Compare A ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "0,1,2,3" bitfld.word 0x0 2.--3. " LOADBMODE ,Active Counter-Compare B (CMPB) Load From Shadow Select Mode. This bit has no effect in immediate mode ( 0x0 = Load on TBCNT = 0: Time-base counter equal to zero ( 0x1 = Load on TBCNT = PRD: Time-base counter equal to period ( 0x2 = Load on either TBCNT = 0 or TBCNT = PRD 0x3 = Freeze (no loads possible)" "0,1,2,3" textline " " bitfld.word 0x0 4. " SHDWAMODE ,Counter-compare A ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action" "0,1" bitfld.word 0x0 5. " RESERVED ," "0,1" textline " " bitfld.word 0x0 6. " SHDWBMODE ,Counter-compare B ( 0x0 = Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register. 0x1 = Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action." "0,1" bitfld.word 0x0 7. " RESERVED ," "0,1" textline " " bitfld.word 0x0 8. " SHDWAFULL ,Counter-compare A ( 0x0 = CMPA shadow FIFO not full yet 0x1 = Indicates the CMPA shadow FIFO is full, a CPU write will overwrite the current shadow value." "0,1" bitfld.word 0x0 9. " SHDWBFULL ,Counter-compare B ( 0x0 = CMPB shadow FIFO not full yet 0x1 = Indicates the CMPB shadow FIFO is full. A CPU write will overwrite current shadow value." "0,1" textline " " bitfld.word 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x10++0x1 line.word 0x0 "HRPWM_CMPAHR,HRPWM_CMPAHR" hexmask.word.byte 0x0 0.--7. 1. " RESERVED ," hexmask.word.byte 0x0 8.--15. 1. " CMPAHR ,Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation 1-255h." group.byte 0x12++0x1 line.word 0x0 "EPWM_CMPA,EPWM_CMPA" hexmask.word 0x0 0.--15. 1. " CMPA ,The value in the active" group.byte 0x14++0x1 line.word 0x0 "EPWM_CMPB,EPWM_CMPB" hexmask.word 0x0 0.--15. 1. " CMPB ,The value in the active" group.byte 0x16++0x1 line.word 0x0 "EPWM_AQCTLA,EPWM_AQCTLA" bitfld.word 0x0 0.--1. " ZRO ,Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 2.--3. " PRD ,Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 4.--5. " CAU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 6.--7. " CAD ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 8.--9. " CBU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 10.--11. " CBD ,Action when the time-base counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxA output low. 0x2 = Set: force EPWMxA output high. 0x3 = Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x18++0x1 line.word 0x0 "EPWM_AQCTLB,EPWM_AQCTLB" bitfld.word 0x0 0.--1. " ZRO ,Action when counter equals zero. Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 2.--3. " PRD ,Action when the counter equals the period. Note: By definition, in count up-down mode when the counter equals period the direction is defined as 0 or counting down. 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 4.--5. " CAU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 6.--7. " CAD ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 8.--9. " CBU ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" bitfld.word 0x0 10.--11. " CBD ,Action when the counter equals the active 0x0 = Do nothing (action disabled) 0x1 = Clear: force EPWMxB output low. 0x2 = Set: force EPWMxB output high. 0x3 = Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low." "0,1,2,3" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x1A++0x1 line.word 0x0 "EPWM_AQSFRC,EPWM_AQSFRC" bitfld.word 0x0 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked. 0x0 = Does nothing (action disabled). 0x1 = Clear (low). 0x2 = Set (high). 0x3 = Toggle (Low -> High, High -> Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0x0 2. " OTSFA ,One-Time Software Forced Event on Output A. 0x0 = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (that is, a forced event is initiated). 0x1 = Initiates a single software forced event." "0,1" textline " " bitfld.word 0x0 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked 0x0 = Does nothing (action disabled) 0x1 = Clear (low) 0x2 = Set (high) 0x3 = Toggle (Low -> High, High -> Low). Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3" bitfld.word 0x0 5. " OTSFB ,One-Time Software Forced Event on Output B. 0x0 = Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete, that is, a forced event is initiated. This is a one-shot forced event. It can be overridden by another subsequent event on output B. 0x1 = Initiates a single s/w forced event" "0,1" textline " " bitfld.word 0x0 6.--7. " RLDCSF ,0x0 = Load on event counter equals zero 0x1 = Load on event counter equals period 0x2 = Load on event counter equals zero or counter equals period 0x3 = Load immediately (the active register is directly accessed by the CPU and is not loaded from the shadow register)." "0,1,2,3" hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x1C++0x1 line.word 0x0 "EPWM_AQCSFRC,EPWM_AQCSFRC" bitfld.word 0x0 0.--1. " CSFA ,Continuous Software Force on Output A In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. 0x0 = Forcing disabled, that is, has no effect 0x1 = Forces a continuous low on output A 0x2 = Forces a continuous high on output A 0x3 = Software forcing is disabled and has no effect" "0,1,2,3" bitfld.word 0x0 2.--3. " CSFB ,Continuous Software Force on Output B. In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use 0x0 = Forcing disabled, that is, has no effect 0x1 = Forces a continuous low on output B 0x2 = Forces a continuous high on output B 0x3 = Software forcing is disabled and has no effect" "0,1,2,3" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x1E++0x1 line.word 0x0 "EPWM_DBCTL,EPWM_DBCTL" bitfld.word 0x0 0.--1. " OUT_MODE ,Dead-band Output Mode Control. Bit 1 controls the S1 switch and bit 0 controls the S0 switch. This allows you to selectively enable or bypass the dead-band generation for the falling-edge and rising-edge delay. 0x0 = Dead-band generation is bypassed for both output signals. In this mode, both the EPWMxA and EPWMxB output signals from the action-qualifier are passed directly to the PWM-chopper submodule. In this mode, the POLSEL and IN_MODE bits have no effect. 0x1 = Disable rising-edge delay. The EPWMxA signal from the action-qualifier is passed straight through to the EPWMxA input of the PWM-chopper submodule. The falling-edge delayed signal is seen on output EPWMxB. The input signal for the delay is determined by 0x2 = Disable falling-edge delay. The EPWMxB signal from the action-qualifier is passed straight through to the EPWMxB input of the PWM-chopper submodule. The rising-edge delayed signal is seen on output EPWMxA. The input signal for the delay is determined by 0x3 = Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by" "0,1,2,3" bitfld.word 0x0 2.--3. " POLSEL ,Polarity Select Control. Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that 0x0 = Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default). 0x1 = Active low complementary (ALC) mode. EPWMxA is inverted. 0x2 = Active high complementary (AHC). EPWMxB is inverted. 0x3 = Active low (AL) mode. Both EPWMxA and EPWMxB are inverted." "0,1,2,3" textline " " bitfld.word 0x0 4.--5. " IN_MODE ,Dead Band Input Mode Control. Bit 5 controls the S5 switch and bit 4 controls the S4 switch. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms, the default is EPWMxA In is the source for both falling and rising-edge delays. 0x0 = EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay. 0x1 = EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal. 0x2 = EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal. EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal. 0x3 = EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal." "0,1,2,3" hexmask.word 0x0 6.--15. 1. " RESERVED ," group.byte 0x20++0x1 line.word 0x0 "EPWM_DBRED,EPWM_DBRED" hexmask.word 0x0 0.--9. 1. " DEL ,Rising Edge Delay Count. 10 bit counter." bitfld.word 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x22++0x1 line.word 0x0 "EPWM_DBFED,EPWM_DBFED" hexmask.word 0x0 0.--9. 1. " DEL ,Falling Edge Delay Count. 10 bit counter" bitfld.word 0x0 10.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x24++0x1 line.word 0x0 "EPWM_TZSEL,EPWM_TZSEL" bitfld.word 0x0 0. " CBC0 ,Trip-zone 0 (TZ0) select. Cycle-by-Cycle (CBC) trip-zone enable/disable. When any of the enabled pins go low, a cycle-by-cycle trip event occurs for this ePWM module. When the event occurs, the action defined in the 0x0 = Disable TZ0 as a CBC trip source for this ePWM module. 0x1 = Enable TZ0 as a CBC trip source for this ePWM module." "0,1" hexmask.word.byte 0x0 1.--7. 1. " RESERVED ," textline " " hexmask.word.byte 0x0 8.--15. 1. " OSHTN ,Trip-zone n (TZn) select. One-Shot (OSHT) trip-zone enable/disable. When any of the enabled pins go low, a one-shot trip event occurs for this ePWM module. When the event occurs, the action defined in the 0x0 = Disable TZn as a one-shot trip source for this ePWM module. 0x1 = Enable TZn as a one-shot trip source for this ePWM module." group.byte 0x28++0x1 line.word 0x0 "EPWM_TZCTL,EPWM_TZCTL" bitfld.word 0x0 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the 0x0 = High impedance (EPWMxA = High-impedance state) 0x1 = Force EPWMxA to a high state 0x2 = Force EPWMxA to a low state 0x3 = Do nothing, no action is taken on EPWMxA." "0,1,2,3" bitfld.word 0x0 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the 0x0 = High impedance (EPWMxB = High-impedance state) 0x1 = Force EPWMxB to a high state 0x2 = Force EPWMxB to a low state 0x3 = Do nothing, no action is taken on EPWMxB." "0,1,2,3" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x2A++0x1 line.word 0x0 "EPWM_TZEINT,EPWM_TZEINT" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CBC ,Trip-zone Cycle-by-Cycle Interrupt Enable 0x0 = Disable cycle-by-cycle interrupt generation. 0x1 = Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMxTZINT interrupt." "0,1" textline " " bitfld.word 0x0 2. " OST ,Trip-zone One-Shot Interrupt Enable 0x0 = Disable one-shot interrupt generation 0x1 = Enable Interrupt generation; a one-shot trip event will cause a EPWMxTZINT interrupt." "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x2C++0x1 line.word 0x0 "EPWM_TZFLG,EPWM_TZFLG" bitfld.word 0x0 0. " INT ,Latched Trip Interrupt Status Flag 0x0 = Indicates no interrupt has been generated. 0x1 = Indicates an EPWMxTZINT interrupt was generated because of a trip condition. No further EPWMxTZINT interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the" "0,1" bitfld.word 0x0 1. " CBC ,Latched Status Flag for Cycle-By-Cycle Trip Event 0x0 = No cycle-by-cycle trip event has occurred. 0x1 = Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The" "0,1" textline " " bitfld.word 0x0 2. " OST ,Latched Status Flag for A One-Shot Trip Event. 0x0 = No one-shot trip event has occurred. 0x1 = Indicates a trip event has occurred on a pin selected as a one-shot trip source. This bit is cleared by writing the appropriate value to the" "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "EPWM_TZCLR,EPWM_TZCLR" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Has no effect. Always reads back a 0. 0x1 = Clears the trip-interrupt flag for this ePWM module (" "0,1" bitfld.word 0x0 1. " CBC ,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0x0 = Has no effect. Always reads back a 0. 0x1 = Clears this Trip (set) condition." "0,1" textline " " bitfld.word 0x0 2. " OST ,Clear Flag for One-Shot Trip (OST) Latch 0x0 = Has no effect. Always reads back a 0. 0x1 = Clears this Trip (set) condition." "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "EPWM_TZFRC,EPWM_TZFRC" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software 0x0 = Writing of 0 is ignored. Always reads back a 0. 0x1 = Forces a cycle-by-cycle trip event and sets the" "0,1" textline " " bitfld.word 0x0 2. " OST ,Force a One-Shot Trip Event via Software 0x0 = Writing of 0 is ignored. Always reads back a 0. 0x1 = Forces a one-shot trip event and sets the" "0,1" hexmask.word 0x0 3.--15. 1. " RESERVED ," group.byte 0x32++0x1 line.word 0x0 "EPWM_ETSEL,EPWM_ETSEL" bitfld.word 0x0 0.--2. " INTSEL ,ePWM Interrupt (EPWMx_INT) Selection Options 0x0 = Reserved 0x1 = Enable event time-base counter equal to zero. (TBCNT = 0000h) 0x2 = Enable event time-base counter equal to period (TBCNT = TBPRD) 0x3 = Reserved 0x4 = Enable event time-base counter equal to CMPA when the timer is incrementing. 0x5 = Enable event time-base counter equal to CMPA when the timer is decrementing. 0x6 = Enable event: time-base counter equal to CMPB when the timer is incrementing. 0x7 = Enable event: time-base counter equal to CMPB when the timer is decrementing." "0,1,2,3,4,5,6,7" bitfld.word 0x0 3. " INTEN ,Enable ePWM Interrupt (EPWMx_INT) Generation 0x0 = Disable EPWMx_INT generation 0x1 = Enable EPWMx_INT generation" "0,1" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x34++0x1 line.word 0x0 "EPWM_ETPS,EPWM_ETPS" bitfld.word 0x0 0.--1. " INTPRD ,ePWM Interrupt (EPWMx_INT) Period Select. These bits determine how many selected 0x0 = Disable the interrupt event counter. No interrupt will be generated and 0x1 = Generate an interrupt on the first event INTCNT = 01 (first event) 0x2 = Generate interrupt on 0x3 = Generate interrupt on" "0,1,2,3" bitfld.word 0x0 2.--3. " INTCNT ,ePWM Interrupt Event (EPWMx_INT) Counter Register. These bits indicate how many selected 0x0 = No events have occurred. 0x1 = 1 event has occurred. 0x2 = 2 events have occurred. 0x3 = 3 events have occurred." "0,1,2,3" textline " " hexmask.word 0x0 4.--15. 1. " RESERVED ," group.byte 0x36++0x1 line.word 0x0 "EPWM_ETFLG,EPWM_ETFLG" bitfld.word 0x0 0. " INT ,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0x0 = Indicates no event occurred 0x1 = Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending while the" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ," group.byte 0x38++0x1 line.word 0x0 "EPWM_ETCLR,EPWM_ETCLR" bitfld.word 0x0 0. " INT ,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing 1 clears the" "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ," group.byte 0x3A++0x1 line.word 0x0 "EPWM_ETFRC,EPWM_ETFRC" bitfld.word 0x0 0. " INT ,INT Force Bit. The interrupt will only be generated if the event is enabled in the 0x0 = Writing 0 to this bit will be ignored. Always reads back a 0. 0x1 = Writing 1 generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes." "0,1" hexmask.word 0x0 1.--15. 1. " RESERVED ," group.byte 0x3C++0x1 line.word 0x0 "EPWM_PCCTL,EPWM_PCCTL" bitfld.word 0x0 0. " CHPEN ,PWM-chopping Enable 0x0 = Disable (bypass) PWM chopping function 0x1 = Enable chopping function" "0,1" bitfld.word 0x0 1.--4. " OSHTWTH ,One-Shot Pulse Width 0x0 = 1 - SYSCLKOUT/8 wide 0x1 = 2 - SYSCLKOUT/8 wide 0x2 = 3 - SYSCLKOUT/8 wide 0x3 = 4 - SYSCLKOUT/8 wide 0xF = 16 - SYSCLKOUT/8 wide" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.word 0x0 5.--7. " CHPFREQ ,Chopping Clock Frequency 0x0 = Divide by 1 (no prescale). 0x1 = Divide by 2. 0x2 = Divide by 3. 0x3 = Divide by 4. 0x4 = Divide by 5. 0x5 = Divide by 6. 0x6 = Divide by 7. 0x7 = Divide by 8." "0,1,2,3,4,5,6,7" bitfld.word 0x0 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle 0x0 = Duty = 1/8 (12.5%) 0x1 = Duty = 2/8 (25.0%) 0x2 = Duty = 3/8 (37.5%) 0x3 = Duty = 4/8 (50.0%) 0x4 = Duty = 5/8 (62.5%) 0x5 = Duty = 6/8 (75.0%) 0x6 = Duty = 7/8 (87.5%) 0x7 = Reserved." "0,1,2,3,4,5,6,7" textline " " bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0xC0++0x1 line.word 0x0 "HRPWM_HRCTL,HRPWM_HRCTL" bitfld.word 0x0 0.--1. " DELMODE ,Delay Mode Bits: Selects which edge of the PWM pulse the delay is inserted. Note: When DELMODE = 0b00, the HRCALM[CALMODE] bits are ignored and the delay line is in by-pass mode. Additionally, DLYIN is connected to CALIN and a continuous low value is fed to the delay line to minimize activity in the module. 0x0 = No delay inserted (default on reset) 0x1 = Delay inserted rising edge 0x2 = Delay inserted falling edge 0x3 = Delay inserted on both edges" "0,1,2,3" bitfld.word 0x0 2. " DELBUSSEL ,Delay Bus Select Bit: Selects which bus is used to select the delay for the PWM pulse. 0x0 = Select CMPAHR(8) bus from compare module of EPWM (default on reset). 0x1 = Select TBPHSHR(8) bus from time base module." "0,1" textline " " bitfld.word 0x0 3. " PULSESEL ,Pulse select bits. Selects which pulse to use for timing events in the HRPWM module. Note: The user needs to select the pulse to match the selection in the EPWM module. If TBPHSHR bus is selected, then CNT_zero pulse should be used. If COMPAHR bus is selected, then it should match the bit setting of the 0x0 = Select CNT_zero pulse 0x1 = Select PRD_eq pulse" "0,1" hexmask.word 0x0 4.--15. 1. " RESERVED ," width 0x0B tree.end tree "PWMSS1_ECAP" base ad:0x4843E100 width 19. group.byte 0x0++0x3 line.long 0x0 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" hexmask.long 0x0 0.--31. 1. " TSCNT ,Active 32 bit-counter register that is used as the capture time-base" group.byte 0x4++0x3 line.long 0x0 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" hexmask.long 0x0 0.--31. 1. " CNTPHS ,Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCNT and is loaded intoPWMSS_ECAP_TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM time-bases." group.byte 0x8++0x3 line.long 0x0 "PWMSS_ECAP_CAP1,Capture-1 Register" hexmask.long 0x0 0.--31. 1. " CAP1 ,This register can be loaded (written) by the following. (a) Time-Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0xC++0x3 line.long 0x0 "PWMSS_ECAP_CAP2,Capture-2 Register" hexmask.long 0x0 0.--31. 1. " CAP2 ,This register can be loaded (written) by the following. (a) Time- Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0x10++0x3 line.long 0x0 "PWMSS_ECAP_CAP3,Capture-3 Register" hexmask.long 0x0 0.--31. 1. " CAP3 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. User SW updates the PWM period value through this register. In this mode, CAP3 shadows CAP1." group.byte 0x14++0x3 line.long 0x0 "PWMSS_ECAP_CAP4,Capture-4 Register" hexmask.long 0x0 0.--31. 1. " CAP4 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow (ACMP) register. User SW updates the PWM compare value through this register. In this mode, CAP4 shadows CAP2." group.byte 0x28++0x1 line.word 0x0 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select 0x0 = Capture Event 1 triggered on a rising edge (RE) 0x1 = Capture Event 1 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1 0x0 = Do not reset counter on Capture Event 1 (absolute time stamp) 0x1 = Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select 0x0 = Capture Event 2 triggered on a rising edge (RE) 0x1 = Capture Event 2 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2 0x0 = Do not reset counter on Capture Event 2 (absolute time stamp) 0x1 = Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select 0x0 = Capture Event 3 triggered on a rising edge (RE) 0x1 = Capture Event 3 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3 0x0 = Do not reset counter on Capture Event 3 (absolute time stamp) 0x1 = Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select 0x0 = Capture Event 4 triggered on a rising edge (RE) 0x1 = Capture Event 4 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4 0x0 = Do not reset counter on Capture Event 4 (absolute time stamp operation) 0x1 = Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event 0x0 = Disable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register loads at capture event time. 0x1 = Enable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register loads at capture event time." "0,1" bitfld.word 0x0 9.--13. " EVTFLTPS ,Event Filter prescale select: 0x0 = Divide by 1 (i.e,. no prescale, by-pass the prescaler) 0x1 = Divide by 2 0x2 = Divide by 4 0x3 = Divide by 6 0x4 = Divide by 8 0x5 = Divide by 10 ... 0x1E = Divide by 60 0x1F = Divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control 0x0 = TSCNT counter stops immediately on emulation suspend. 0x1 = TSCNT counter runs until = 0. 0x2 = TSCNT counter is unaffected by emulation suspend (Run Free). 0x3 = TSCNT counter is unaffected by emulation suspend (Run Free)." "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x0 0. " CONTONESHT ,Continuous or one-shot mode control (applicable only in capture mode) 0x0 = Operate in continuous mode 0x1 = Operate in one-shot mode" "0,1" bitfld.word 0x0 1.--2. " STOPVALUE ,Stop value for one-shot mode. This is the number (between 1 and 4) of captures allowed to occur before the CAP (1 through 4) registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1 and 4) of the capture register in which the circular buffer wraps around and starts again. Notes: STOPVALUE is compared to Mod4 counter and, when equal, the following two actions occur. (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. In one-shot mode, further interrupt events are blocked until re-armed. 0x0 = Stop after Capture Event 1 in one-shot mode. Wrap after Capture Event 1 in continuous mode. 0x1 = Stop after Capture Event 2 in one-shot mode. Wrap after Capture Event 2 in continuous mode. 0x2 = Stop after Capture Event 3 in one-shot mode. Wrap after Capture Event 3 in continuous mode. 0x3 = Stop after Capture Event 4 in one-shot mode. Wrap after Capture Event 4 in continuous mode." "0,1,2,3" textline " " bitfld.word 0x0 3. " REARMRESET ,One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0x0 = Has no effect (reading always returns a 0) 0x1 = Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero. 2) Unfreezes the Mod4 counter. 3) Enables capture register loads." "0,1" bitfld.word 0x0 4. " TSCNTSTP ,Time Stamp (TSCNT) Counter Stop (freeze) Control 0x0 = TSCNT stopped 0x1 = TSCNT free-running" "0,1" textline " " bitfld.word 0x0 5. " SYNCI_EN ,Counter (TSCNT) Sync-In select mode 0x0 = Disable sync-in option 0x1 = Enable counter (TSCNT) to be loaded from" "0,1" bitfld.word 0x0 6.--7. " SYNCO_SEL ,Sync-Out Select 0x0 = Select sync-in event to be the sync-out signal (pass through) 0x1 = Select TSCNT = PRD event to be the sync-out signal 0x2 = Disable sync out signal 0x3 = Disable sync out signal" "0,1,2,3" textline " " bitfld.word 0x0 8. " SWSYNC ,Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via the TSCNT = PRD event. Note: Selection TSCNT = PRD is meaningful only in APWM mode. However, you can choose it in CAP mode if you find doing so useful. 0x0 = Writing a zero has no effect. Reading always returns a zero 0x1 = Writing a one forces a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 0b00. After writing a 1, this bit returns to a zero." "0,1" bitfld.word 0x0 9. " CAPAPWM ,CAP/APWM operating mode select" "0,1" textline " " bitfld.word 0x0 10. " APWMPOL ,APWM output polarity select. This is applicable only in APWM operating mode 0x0 = Output is active high (Compare value defines high time) 0x1 = Output is active low (Compare value defines low time)" "0,1" bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2C++0x1 line.word 0x0 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Interrupt Enable . 0x0 = Disable Capture Event 1 as an Interrupt source. 0x1 = Enable Capture Event 1 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Interrupt Enable. 0x0 = Disable Capture Event 2 as an Interrupt source. 0x1 = Enable Capture Event 2 as an Interrupt source." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Interrupt Enable. 0x0 = Disable Capture Event 3 as an Interrupt source. 0x1 = Enable Capture Event 3 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Interrupt Enable. 0x0 = Disable Capture Event 4 as an Interrupt source. 0x1 = Enable Capture Event 4 as an Interrupt source." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Interrupt Enable. 0x0 = Disable counter Overflow as an Interrupt source. 0x1 = Enable counter Overflow as an Interrupt source." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal 0x0 = Disable Period Equal as an Interrupt source. 0x1 = Enable Period Equal as an Interrupt source." "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal 0x0 = Disable Compare Equal as an Interrupt source. 0x1 = Enable Compare Equal as an Interrupt source." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag 0x0 = Indicates no interrupt generated. 0x1 = Indicates that an interrupt was generated." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the first event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the second event occurred at ECAPn pin." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the third event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag This flag is only active in CAP mode. 0x0 = Indicates no event occurred 0x1 = Indicates the fourth event occurred at ECAPn pin" "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the counter (TSCNT) has made the transition from 0xFFFFFFFF to 0x00000000" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the period register value (APRD) and was reset." "0,1" bitfld.word 0x0 7. " CMPEQ ,Compare Equal Compare Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the compare register value (ACMP)" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT1 flag condition." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT2 flag condition." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CNTOVF flag condition" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the TSCNT=PRD flag condition" "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal Compare Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the TSCNT=CMP flag condition" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x32++0x1 line.word 0x0 "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Always reads back a 0. Force Capture Event 1 0x0 = No effect. 0x1 = Writing a 1 sets the CEVT1 flag bit." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Force Capture Event 2 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT2 flag bit." "0,1" bitfld.word 0x0 3. " CEVT3 ,Force Capture Event 3 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT3 flag bit" "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Force Capture Event 4 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT4 flag bit" "0,1" bitfld.word 0x0 5. " CNTOVF ,Force Counter Overflow 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 to this bit sets the CNTOVF flag bit." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Force Counter Equal Period Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the TSCNT=PRD flag bit." "0,1" bitfld.word 0x0 7. " CMPEQ ,Force Counter Equal Compare Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the TSCNT=CMP flag bit." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "PWMSS_ECAP_PID,ECAP Revision ID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "PWMSS2_ECAP" base ad:0x48440100 width 19. group.byte 0x0++0x3 line.long 0x0 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" hexmask.long 0x0 0.--31. 1. " TSCNT ,Active 32 bit-counter register that is used as the capture time-base" group.byte 0x4++0x3 line.long 0x0 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" hexmask.long 0x0 0.--31. 1. " CNTPHS ,Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCNT and is loaded intoPWMSS_ECAP_TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM time-bases." group.byte 0x8++0x3 line.long 0x0 "PWMSS_ECAP_CAP1,Capture-1 Register" hexmask.long 0x0 0.--31. 1. " CAP1 ,This register can be loaded (written) by the following. (a) Time-Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0xC++0x3 line.long 0x0 "PWMSS_ECAP_CAP2,Capture-2 Register" hexmask.long 0x0 0.--31. 1. " CAP2 ,This register can be loaded (written) by the following. (a) Time- Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0x10++0x3 line.long 0x0 "PWMSS_ECAP_CAP3,Capture-3 Register" hexmask.long 0x0 0.--31. 1. " CAP3 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. User SW updates the PWM period value through this register. In this mode, CAP3 shadows CAP1." group.byte 0x14++0x3 line.long 0x0 "PWMSS_ECAP_CAP4,Capture-4 Register" hexmask.long 0x0 0.--31. 1. " CAP4 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow (ACMP) register. User SW updates the PWM compare value through this register. In this mode, CAP4 shadows CAP2." group.byte 0x28++0x1 line.word 0x0 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select 0x0 = Capture Event 1 triggered on a rising edge (RE) 0x1 = Capture Event 1 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1 0x0 = Do not reset counter on Capture Event 1 (absolute time stamp) 0x1 = Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select 0x0 = Capture Event 2 triggered on a rising edge (RE) 0x1 = Capture Event 2 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2 0x0 = Do not reset counter on Capture Event 2 (absolute time stamp) 0x1 = Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select 0x0 = Capture Event 3 triggered on a rising edge (RE) 0x1 = Capture Event 3 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3 0x0 = Do not reset counter on Capture Event 3 (absolute time stamp) 0x1 = Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select 0x0 = Capture Event 4 triggered on a rising edge (RE) 0x1 = Capture Event 4 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4 0x0 = Do not reset counter on Capture Event 4 (absolute time stamp operation) 0x1 = Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event 0x0 = Disable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register loads at capture event time. 0x1 = Enable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register loads at capture event time." "0,1" bitfld.word 0x0 9.--13. " EVTFLTPS ,Event Filter prescale select: 0x0 = Divide by 1 (i.e,. no prescale, by-pass the prescaler) 0x1 = Divide by 2 0x2 = Divide by 4 0x3 = Divide by 6 0x4 = Divide by 8 0x5 = Divide by 10 ... 0x1E = Divide by 60 0x1F = Divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control 0x0 = TSCNT counter stops immediately on emulation suspend. 0x1 = TSCNT counter runs until = 0. 0x2 = TSCNT counter is unaffected by emulation suspend (Run Free). 0x3 = TSCNT counter is unaffected by emulation suspend (Run Free)." "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x0 0. " CONTONESHT ,Continuous or one-shot mode control (applicable only in capture mode) 0x0 = Operate in continuous mode 0x1 = Operate in one-shot mode" "0,1" bitfld.word 0x0 1.--2. " STOPVALUE ,Stop value for one-shot mode. This is the number (between 1 and 4) of captures allowed to occur before the CAP (1 through 4) registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1 and 4) of the capture register in which the circular buffer wraps around and starts again. Notes: STOPVALUE is compared to Mod4 counter and, when equal, the following two actions occur. (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. In one-shot mode, further interrupt events are blocked until re-armed. 0x0 = Stop after Capture Event 1 in one-shot mode. Wrap after Capture Event 1 in continuous mode. 0x1 = Stop after Capture Event 2 in one-shot mode. Wrap after Capture Event 2 in continuous mode. 0x2 = Stop after Capture Event 3 in one-shot mode. Wrap after Capture Event 3 in continuous mode. 0x3 = Stop after Capture Event 4 in one-shot mode. Wrap after Capture Event 4 in continuous mode." "0,1,2,3" textline " " bitfld.word 0x0 3. " REARMRESET ,One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0x0 = Has no effect (reading always returns a 0) 0x1 = Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero. 2) Unfreezes the Mod4 counter. 3) Enables capture register loads." "0,1" bitfld.word 0x0 4. " TSCNTSTP ,Time Stamp (TSCNT) Counter Stop (freeze) Control 0x0 = TSCNT stopped 0x1 = TSCNT free-running" "0,1" textline " " bitfld.word 0x0 5. " SYNCI_EN ,Counter (TSCNT) Sync-In select mode 0x0 = Disable sync-in option 0x1 = Enable counter (TSCNT) to be loaded from" "0,1" bitfld.word 0x0 6.--7. " SYNCO_SEL ,Sync-Out Select 0x0 = Select sync-in event to be the sync-out signal (pass through) 0x1 = Select TSCNT = PRD event to be the sync-out signal 0x2 = Disable sync out signal 0x3 = Disable sync out signal" "0,1,2,3" textline " " bitfld.word 0x0 8. " SWSYNC ,Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via the TSCNT = PRD event. Note: Selection TSCNT = PRD is meaningful only in APWM mode. However, you can choose it in CAP mode if you find doing so useful. 0x0 = Writing a zero has no effect. Reading always returns a zero 0x1 = Writing a one forces a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 0b00. After writing a 1, this bit returns to a zero." "0,1" bitfld.word 0x0 9. " CAPAPWM ,CAP/APWM operating mode select" "0,1" textline " " bitfld.word 0x0 10. " APWMPOL ,APWM output polarity select. This is applicable only in APWM operating mode 0x0 = Output is active high (Compare value defines high time) 0x1 = Output is active low (Compare value defines low time)" "0,1" bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2C++0x1 line.word 0x0 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Interrupt Enable . 0x0 = Disable Capture Event 1 as an Interrupt source. 0x1 = Enable Capture Event 1 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Interrupt Enable. 0x0 = Disable Capture Event 2 as an Interrupt source. 0x1 = Enable Capture Event 2 as an Interrupt source." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Interrupt Enable. 0x0 = Disable Capture Event 3 as an Interrupt source. 0x1 = Enable Capture Event 3 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Interrupt Enable. 0x0 = Disable Capture Event 4 as an Interrupt source. 0x1 = Enable Capture Event 4 as an Interrupt source." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Interrupt Enable. 0x0 = Disable counter Overflow as an Interrupt source. 0x1 = Enable counter Overflow as an Interrupt source." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal 0x0 = Disable Period Equal as an Interrupt source. 0x1 = Enable Period Equal as an Interrupt source." "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal 0x0 = Disable Compare Equal as an Interrupt source. 0x1 = Enable Compare Equal as an Interrupt source." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag 0x0 = Indicates no interrupt generated. 0x1 = Indicates that an interrupt was generated." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the first event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the second event occurred at ECAPn pin." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the third event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag This flag is only active in CAP mode. 0x0 = Indicates no event occurred 0x1 = Indicates the fourth event occurred at ECAPn pin" "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the counter (TSCNT) has made the transition from 0xFFFFFFFF to 0x00000000" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the period register value (APRD) and was reset." "0,1" bitfld.word 0x0 7. " CMPEQ ,Compare Equal Compare Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the compare register value (ACMP)" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT1 flag condition." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT2 flag condition." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CNTOVF flag condition" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the TSCNT=PRD flag condition" "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal Compare Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the TSCNT=CMP flag condition" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x32++0x1 line.word 0x0 "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Always reads back a 0. Force Capture Event 1 0x0 = No effect. 0x1 = Writing a 1 sets the CEVT1 flag bit." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Force Capture Event 2 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT2 flag bit." "0,1" bitfld.word 0x0 3. " CEVT3 ,Force Capture Event 3 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT3 flag bit" "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Force Capture Event 4 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT4 flag bit" "0,1" bitfld.word 0x0 5. " CNTOVF ,Force Counter Overflow 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 to this bit sets the CNTOVF flag bit." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Force Counter Equal Period Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the TSCNT=PRD flag bit." "0,1" bitfld.word 0x0 7. " CMPEQ ,Force Counter Equal Compare Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the TSCNT=CMP flag bit." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "PWMSS_ECAP_PID,ECAP Revision ID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "PWMSS3_ECAP" base ad:0x48442100 width 19. group.byte 0x0++0x3 line.long 0x0 "PWMSS_ECAP_TSCNT,Time Stamp Counter Register" hexmask.long 0x0 0.--31. 1. " TSCNT ,Active 32 bit-counter register that is used as the capture time-base" group.byte 0x4++0x3 line.long 0x0 "PWMSS_ECAP_CNTPHS,Counter Phase Control Register" hexmask.long 0x0 0.--31. 1. " CNTPHS ,Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCNT and is loaded intoPWMSS_ECAP_TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM time-bases." group.byte 0x8++0x3 line.long 0x0 "PWMSS_ECAP_CAP1,Capture-1 Register" hexmask.long 0x0 0.--31. 1. " CAP1 ,This register can be loaded (written) by the following. (a) Time-Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0xC++0x3 line.long 0x0 "PWMSS_ECAP_CAP2,Capture-2 Register" hexmask.long 0x0 0.--31. 1. " CAP2 ,This register can be loaded (written) by the following. (a) Time- Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0x10++0x3 line.long 0x0 "PWMSS_ECAP_CAP3,Capture-3 Register" hexmask.long 0x0 0.--31. 1. " CAP3 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. User SW updates the PWM period value through this register. In this mode, CAP3 shadows CAP1." group.byte 0x14++0x3 line.long 0x0 "PWMSS_ECAP_CAP4,Capture-4 Register" hexmask.long 0x0 0.--31. 1. " CAP4 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow (ACMP) register. User SW updates the PWM compare value through this register. In this mode, CAP4 shadows CAP2." group.byte 0x28++0x1 line.word 0x0 "PWMSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select 0x0 = Capture Event 1 triggered on a rising edge (RE) 0x1 = Capture Event 1 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1 0x0 = Do not reset counter on Capture Event 1 (absolute time stamp) 0x1 = Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select 0x0 = Capture Event 2 triggered on a rising edge (RE) 0x1 = Capture Event 2 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2 0x0 = Do not reset counter on Capture Event 2 (absolute time stamp) 0x1 = Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select 0x0 = Capture Event 3 triggered on a rising edge (RE) 0x1 = Capture Event 3 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3 0x0 = Do not reset counter on Capture Event 3 (absolute time stamp) 0x1 = Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select 0x0 = Capture Event 4 triggered on a rising edge (RE) 0x1 = Capture Event 4 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4 0x0 = Do not reset counter on Capture Event 4 (absolute time stamp operation) 0x1 = Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading ofPWMSS_ECAP_CAP1 to PWMSS_ECAP_CAP4 registers on a capture event 0x0 = Disable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register loads at capture event time. 0x1 = Enable PWMSS_ECAP_CAP1-PWMSS_ECAP_CAP4 register loads at capture event time." "0,1" bitfld.word 0x0 9.--13. " EVTFLTPS ,Event Filter prescale select: 0x0 = Divide by 1 (i.e,. no prescale, by-pass the prescaler) 0x1 = Divide by 2 0x2 = Divide by 4 0x3 = Divide by 6 0x4 = Divide by 8 0x5 = Divide by 10 ... 0x1E = Divide by 60 0x1F = Divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control 0x0 = TSCNT counter stops immediately on emulation suspend. 0x1 = TSCNT counter runs until = 0. 0x2 = TSCNT counter is unaffected by emulation suspend (Run Free). 0x3 = TSCNT counter is unaffected by emulation suspend (Run Free)." "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "PWMSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x0 0. " CONTONESHT ,Continuous or one-shot mode control (applicable only in capture mode) 0x0 = Operate in continuous mode 0x1 = Operate in one-shot mode" "0,1" bitfld.word 0x0 1.--2. " STOPVALUE ,Stop value for one-shot mode. This is the number (between 1 and 4) of captures allowed to occur before the CAP (1 through 4) registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1 and 4) of the capture register in which the circular buffer wraps around and starts again. Notes: STOPVALUE is compared to Mod4 counter and, when equal, the following two actions occur. (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. In one-shot mode, further interrupt events are blocked until re-armed. 0x0 = Stop after Capture Event 1 in one-shot mode. Wrap after Capture Event 1 in continuous mode. 0x1 = Stop after Capture Event 2 in one-shot mode. Wrap after Capture Event 2 in continuous mode. 0x2 = Stop after Capture Event 3 in one-shot mode. Wrap after Capture Event 3 in continuous mode. 0x3 = Stop after Capture Event 4 in one-shot mode. Wrap after Capture Event 4 in continuous mode." "0,1,2,3" textline " " bitfld.word 0x0 3. " REARMRESET ,One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0x0 = Has no effect (reading always returns a 0) 0x1 = Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero. 2) Unfreezes the Mod4 counter. 3) Enables capture register loads." "0,1" bitfld.word 0x0 4. " TSCNTSTP ,Time Stamp (TSCNT) Counter Stop (freeze) Control 0x0 = TSCNT stopped 0x1 = TSCNT free-running" "0,1" textline " " bitfld.word 0x0 5. " SYNCI_EN ,Counter (TSCNT) Sync-In select mode 0x0 = Disable sync-in option 0x1 = Enable counter (TSCNT) to be loaded from" "0,1" bitfld.word 0x0 6.--7. " SYNCO_SEL ,Sync-Out Select 0x0 = Select sync-in event to be the sync-out signal (pass through) 0x1 = Select TSCNT = PRD event to be the sync-out signal 0x2 = Disable sync out signal 0x3 = Disable sync out signal" "0,1,2,3" textline " " bitfld.word 0x0 8. " SWSYNC ,Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via the TSCNT = PRD event. Note: Selection TSCNT = PRD is meaningful only in APWM mode. However, you can choose it in CAP mode if you find doing so useful. 0x0 = Writing a zero has no effect. Reading always returns a zero 0x1 = Writing a one forces a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 0b00. After writing a 1, this bit returns to a zero." "0,1" bitfld.word 0x0 9. " CAPAPWM ,CAP/APWM operating mode select" "0,1" textline " " bitfld.word 0x0 10. " APWMPOL ,APWM output polarity select. This is applicable only in APWM operating mode 0x0 = Output is active high (Compare value defines high time) 0x1 = Output is active low (Compare value defines low time)" "0,1" bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2C++0x1 line.word 0x0 "PWMSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Interrupt Enable . 0x0 = Disable Capture Event 1 as an Interrupt source. 0x1 = Enable Capture Event 1 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Interrupt Enable. 0x0 = Disable Capture Event 2 as an Interrupt source. 0x1 = Enable Capture Event 2 as an Interrupt source." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Interrupt Enable. 0x0 = Disable Capture Event 3 as an Interrupt source. 0x1 = Enable Capture Event 3 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Interrupt Enable. 0x0 = Disable Capture Event 4 as an Interrupt source. 0x1 = Enable Capture Event 4 as an Interrupt source." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Interrupt Enable. 0x0 = Disable counter Overflow as an Interrupt source. 0x1 = Enable counter Overflow as an Interrupt source." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal 0x0 = Disable Period Equal as an Interrupt source. 0x1 = Enable Period Equal as an Interrupt source." "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal 0x0 = Disable Compare Equal as an Interrupt source. 0x1 = Enable Compare Equal as an Interrupt source." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "PWMSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag 0x0 = Indicates no interrupt generated. 0x1 = Indicates that an interrupt was generated." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the first event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the second event occurred at ECAPn pin." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the third event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag This flag is only active in CAP mode. 0x0 = Indicates no event occurred 0x1 = Indicates the fourth event occurred at ECAPn pin" "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the counter (TSCNT) has made the transition from 0xFFFFFFFF to 0x00000000" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the period register value (APRD) and was reset." "0,1" bitfld.word 0x0 7. " CMPEQ ,Compare Equal Compare Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the compare register value (ACMP)" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "PWMSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT1 flag condition." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT2 flag condition." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CNTOVF flag condition" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the TSCNT=PRD flag condition" "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal Compare Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the TSCNT=CMP flag condition" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x32++0x1 line.word 0x0 "PWMSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Always reads back a 0. Force Capture Event 1 0x0 = No effect. 0x1 = Writing a 1 sets the CEVT1 flag bit." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Force Capture Event 2 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT2 flag bit." "0,1" bitfld.word 0x0 3. " CEVT3 ,Force Capture Event 3 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT3 flag bit" "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Force Capture Event 4 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT4 flag bit" "0,1" bitfld.word 0x0 5. " CNTOVF ,Force Counter Overflow 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 to this bit sets the CNTOVF flag bit." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Force Counter Equal Period Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the TSCNT=PRD flag bit." "0,1" bitfld.word 0x0 7. " CMPEQ ,Force Counter Equal Compare Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the TSCNT=CMP flag bit." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "PWMSS_ECAP_PID,ECAP Revision ID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "PWMSS1_EQEP" base ad:0x4843E180 width 15. group.byte 0x0++0x3 line.long 0x0 "EQEP_QPOSCNT,EQEP_QPOSCNT" hexmask.long 0x0 0.--31. 1. " QPOSCNT ,This 32 bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point." group.byte 0x4++0x3 line.long 0x0 "EQEP_QPOSINIT,EQEP_QPOSINIT" hexmask.long 0x0 0.--31. 1. " QPOSINIT ,This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software." group.byte 0x8++0x3 line.long 0x0 "EQEP_QPOSMAX,EQEP_QPOSMAX" hexmask.long 0x0 0.--31. 1. " QPOSMAX ,This register contains the maximum position counter value." group.byte 0xC++0x3 line.long 0x0 "EQEP_QPOSCMP,EQEP_QPOSCMP" hexmask.long 0x0 0.--31. 1. " QPOSCMP ,The position-compare value in this register is compared with the position counter (QPOSCNT field in" group.byte 0x10++0x3 line.long 0x0 "EQEP_QPOSILAT,EQEP_QPOSILAT" hexmask.long 0x0 0.--31. 1. " QPOSILAT ,The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." group.byte 0x14++0x3 line.long 0x0 "EQEP_QPOSSLAT,EQEP_QPOSSLAT" hexmask.long 0x0 0.--31. 1. " QPOSSLAT ,The position-counter value is latched into this register on strobe event as defined by the QEPCTL[SEL] bits." group.byte 0x18++0x3 line.long 0x0 "EQEP_QPOSLAT,EQEP_QPOSLAT" hexmask.long 0x0 0.--31. 1. " QPOSLAT ,The position-counter value is latched into this register on unit time out event." group.byte 0x1C++0x3 line.long 0x0 "EQEP_QUTMR,EQEP_QUTMR" hexmask.long 0x0 0.--31. 1. " QUTMR ,This register acts as time base for unit time event generation. When this timer value matches with unit time period value, unit time event is generated." group.byte 0x20++0x3 line.long 0x0 "EQEP_QUPRD,EQEP_QUPRD" hexmask.long 0x0 0.--31. 1. " QUPRD ,This register contains the period count for unit timer to generate periodic unit time events to latch the eQEP position information at periodic interval and optionally to generate interrupt." group.byte 0x24++0x1 line.word 0x0 "EQEP_QWDTMR,EQEP_QWDTMR" hexmask.word 0x0 0.--15. 1. " QWDTMR ,This register acts as time base for watch dog to detect motor stalls. When this timer value matches with watch dog period value, watch dog timeout interrupt is generated. This register is reset upon edge transition in quadrature-clock indicating the motion." group.byte 0x26++0x1 line.word 0x0 "EQEP_QWDPRD,EQEP_QWDPRD" hexmask.word 0x0 0.--15. 1. " QWDPRD ,This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value, a watchdog timeout interrupt is generated." group.byte 0x28++0x1 line.word 0x0 "EQEP_QDECCTL,EQEP_QDECCTL" bitfld.word 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x0 5. " QSP ,QEPS input polarity 0x0 = No effect 0x1 = Negates QEPS input" "0,1" textline " " bitfld.word 0x0 6. " QIP ,QEPI input polarity 0x0 = No effect 0x1 = Negates QEPI input" "0,1" bitfld.word 0x0 7. " QBP ,QEPB input polarity 0x0 = No effect 0x1 = Negates QEPB input" "0,1" textline " " bitfld.word 0x0 8. " QAP ,QEPA input polarity 0x0 = No effect 0x1 = Negates QEPA input" "0,1" bitfld.word 0x0 9. " IGATE ,Index pulse gating option 0x0 = Disable gating of Index pulse 0x1 = Gate the index pin with strobe" "0,1" textline " " bitfld.word 0x0 10. " SWAP ,Swap quadrature clock inputs. This swaps the input to the quadrature decoder, reversing the counting direction. 0x0 = Quadrature-clock inputs are not swapped 0x1 = Quadrature-clock inputs are swapped" "0,1" bitfld.word 0x0 11. " XCR ,External clock rate 0x0 = 2x resolution: Count the rising/falling edge 0x1 = 1x resolution: Count the rising edge only" "0,1" textline " " bitfld.word 0x0 12. " SPSEL ,Sync output pin selection 0x0 = Index pin is used for sync output 0x1 = Strobe pin is used for sync output" "0,1" bitfld.word 0x0 13. " SOEN ,Sync output-enable 0x0 = Disable position-compare sync output 0x1 = Enable position-compare sync output" "0,1" textline " " bitfld.word 0x0 14.--15. " QSRC ,Position-counter source selection. 0x0 = Quadrature count mode (QCLK = iCLK, QDIR = iDIR) 0x1 = Direction-count mode (QCLK = xCLK, QDIR = xDIR) 0x2 = UP count mode for frequency measurement (QCLK = xCLK, QDIR = 1) 0x3 = DOWN count mode for frequency measurement (QCLK = xCLK, QDIR = 0)" "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "EQEP_QEPCTL,EQEP_QEPCTL" bitfld.word 0x0 0. " WDE ,eQEP watchdog enable 0x0 = Disable the eQEP watchdog timer 0x1 = Enable the eQEP watchdog timer" "0,1" bitfld.word 0x0 1. " UTE ,eQEP unit timer enable 0x0 = Disable eQEP unit timer 0x1 = Enable unit timer" "0,1" textline " " bitfld.word 0x0 2. " QCLM ,eQEP capture latch mode 0x0 = Latch on position counter read by CPU. Capture timer and capture period values are latched into 0x1 = Latch on unit time out. Position counter, capture timer and capture period values are latched into" "0,1" bitfld.word 0x0 3. " PHEN ,Quadrature position counter enable/software reset 0x0 = Reset the eQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. 0x1 = eQEP position counter is enabled" "0,1" textline " " bitfld.word 0x0 4.--5. " IEL ,Index event latch of position counter (software index marker) 0x0 = Reserved 0x1 = Latches position counter on rising edge of the index signal 0x2 = Latches position counter on falling edge of the index signal 0x3 = Software index marker. Latches the position counter and quadrature direction flag on index event marker. The position counter is latched to the" "0,1,2,3" bitfld.word 0x0 6. " SEL ,Strobe event latch of position counter 0x0 = The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the 0x1 = Clockwise Direction: Position counter is latched on rising edge of QEPS strobe. Counter Clockwise Direction: Position counter is latched on falling edge of QEPS strobe." "0,1" textline " " bitfld.word 0x0 7. " SWI ,Software initialization of position counter 0x0 = Do nothing (action disabled) 0x1 = Initialize position counter, this bit is cleared automatically" "0,1" bitfld.word 0x0 8.--9. " IEI ,Index event initialization of position counter 0x0 = Do nothing (action disabled) 0x1 = Do nothing (action disabled) 0x2 = Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT) 0x3 = Initializes the position counter on the falling edge of QEPI signal (QPOSCNT = QPOSINIT)" "0,1,2,3" textline " " bitfld.word 0x0 10.--11. " SEI ,Strobe event initialization of position counter 0x0 = Does nothing (action disabled) 0x1 = Does nothing (action disabled) 0x2 = Initializes the position counter on rising edge of the QEPS signal 0x3 = Clockwise Direction: Initializes the position counter on the rising edge of QEPS strobe. Counter Clockwise Direction: Initializes the position counter on the falling edge of QEPS strobe" "0,1,2,3" bitfld.word 0x0 12.--13. " PCRM ,Position counter reset mode 0x0 = Position counter reset on an index event 0x1 = Position counter reset on the maximum position 0x2 = Position counter reset on the first index event 0x3 = Position counter reset on a unit time event" "0,1,2,3" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control Bits. In the values 0 through 3 listed below, x is different for the four following behaviors. 0x0 = x stops immediately. For QPOSCNT behavior, the stop is on emulation suspend. 0x1 = x continues to count until the rollover. 0x2 = x is unaffected by emulation suspend. 0x3 = x is unaffected by emulation suspend." "0,1,2,3" group.byte 0x2C++0x1 line.word 0x0 "EQEP_QCAPCTL,EQEP_QCAPCTL" bitfld.word 0x0 0.--3. " UPPS ,Unit position event prescaler 0x0 = UPEVNT = QCLK/1 0x1 = UPEVNT = QCLK/2 0x2 = UPEVNT = QCLK/4 0x3 = UPEVNT = QCLK/8 0x4 = UPEVNT = QCLK/16 0x5 = UPEVNT = QCLK/32 0x6 = UPEVNT = QCLK/64 0x7 = UPEVNT = QCLK/128 0x8 = UPEVNT = QCLK/256 0x9 = UPEVNT = QCLK/512 0xA = UPEVNT = QCLK/1024 0xB = UPEVNT = QCLK/2048 0xC = Reserved 0xD = Reserved 0xE = Reserved 0xF = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0 4.--6. " CCPS ,eQEP capture timer clock prescaler 0x0 = CAPCLK = SYSCLKOUT/1 0x1 = CAPCLK = SYSCLKOUT/2 0x2 = CAPCLK = SYSCLKOUT/4 0x3 = CAPCLK = SYSCLKOUT/8 0x4 = CAPCLK = SYSCLKOUT/16 0x5 = CAPCLK = SYSCLKOUT/32 0x6 = CAPCLK = SYSCLKOUT/64 0x7 = CAPCLK = SYSCLKOUT/128" "0,1,2,3,4,5,6,7" textline " " hexmask.word.byte 0x0 7.--14. 1. " RESERVED ," bitfld.word 0x0 15. " CEN ,Enable eQEP capture 0x0 = eQEP capture unit is disabled 0x1 = eQEP capture unit is enabled" "0,1" group.byte 0x2E++0x1 line.word 0x0 "EQEP_QPOSCTL,EQEP_QPOSCTL" hexmask.word 0x0 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width ... 0x0 = 1 x 4 x SYSCLKOUT cycles 0x1 = 2 x 4 x SYSCLKOUT cycles 0x2 = 3 x 4 x SYSCLKOUT cycles to 4096 x 4 x SYSCLKOUT cycles 0xFFF = 3 x 4 x SYSCLKOUT cycles to 4096 x 4 x SYSCLKOUT cycles" bitfld.word 0x0 12. " PCE ,Position-compare enable/disable 0x0 = Disable position compare unit 0x1 = Enable position compare unit" "0,1" textline " " bitfld.word 0x0 13. " PCPOL ,Polarity of sync output 0x0 = Active HIGH pulse output 0x1 = Active LOW pulse output" "0,1" bitfld.word 0x0 14. " PCLOAD ,Position-compare shadow load mode 0x0 = Load on QPOSCNT = 0 0x1 = Load when QPOSCNT = QPOSCMP" "0,1" textline " " bitfld.word 0x0 15. " PCSHDW ,Position-compare shadow enable 0x0 = Shadow disabled, load Immediate 0x1 = Shadow enabled" "0,1" group.byte 0x30++0x1 line.word 0x0 "EQEP_QEINT,EQEP_QEINT" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " PCE ,Position counter error interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Quadrature phase error interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 3. " QDC ,Quadrature direction change interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Watchdog time out interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 5. " PCU ,Position counter underflow interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 6. " PCO ,Position counter overflow interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 7. " PCR ,Position-compare ready interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 8. " PCM ,Position-compare match interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 9. " SEL ,Strobe event latch interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Index event latch interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 11. " UTO ,Unit time out interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x32++0x1 line.word 0x0 "EQEP_QFLG,EQEP_QFLG" bitfld.word 0x0 0. " INT ,Global interrupt status flag 0x0 = No interrupt generated 0x1 = Interrupt was generated" "0,1" bitfld.word 0x0 1. " PCE ,Position counter error interrupt flag 0x0 = No interrupt generated 0x1 = Position counter error" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Quadrature phase error interrupt flag 0x0 = No interrupt generated 0x1 = Set on simultaneous transition of QEPA and QEPB" "0,1" bitfld.word 0x0 3. " QDC ,Quadrature direction change interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set during change of direction" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Watchdog timeout interrupt flag 0x0 = No interrupt generated 0x1 = Set by watch dog timeout" "0,1" bitfld.word 0x0 5. " PCU ,Position counter underflow interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set on position counter underflow." "0,1" textline " " bitfld.word 0x0 6. " PCO ,Position counter overflow interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set on position counter overflow." "0,1" bitfld.word 0x0 7. " PCR ,Position-compare ready interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set after transferring the shadow register value to the active position compare register." "0,1" textline " " bitfld.word 0x0 8. " PCM ,eQEP compare match event interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set on position-compare match" "0,1" bitfld.word 0x0 9. " SEL ,Strobe event latch interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set after latching the QPOSCNT to" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Index event latch interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set after latching the QPOSCNT to QPOSILAT" "0,1" bitfld.word 0x0 11. " UTO ,Unit time out interrupt flag 0x0 = No interrupt generated 0x1 = Set by eQEP unit timer period match" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x34++0x1 line.word 0x0 "EQEP_QCLR,EQEP_QCLR" bitfld.word 0x0 0. " INT ,Global interrupt clear flag 0x0 = No effect 0x1 = Clears the interrupt flag and enables further interrupts to be generated if an event flags is set to 1." "0,1" bitfld.word 0x0 1. " PCE ,Clear position counter error interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Clear quadrature phase error interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 3. " QDC ,Clear quadrature direction change interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Clear watchdog timeout interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 5. " PCU ,Clear position counter underflow interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 6. " PCO ,Clear position counter overflow interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 7. " PCR ,Clear position-compare ready interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 8. " PCM ,Clear eQEP compare match event interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 9. " SEL ,Clear strobe event latch interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Clear index event latch interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 11. " UTO ,Clear unit time out interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x36++0x1 line.word 0x0 "EQEP_QFRC,EQEP_QFRC" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " PCE ,Force position counter error interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Force quadrature phase error interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 3. " QDC ,Force quadrature direction change interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Force watchdog time out interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 5. " PCU ,Force position counter underflow interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 6. " PCO ,Force position counter overflow interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 7. " PCR ,Force position-compare ready interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 8. " PCM ,Force position-compare match interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 9. " SEL ,Force strobe event latch interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Force index event latch interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 11. " UTO ,Force unit time out interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x38++0x1 line.word 0x0 "EQEP_QEPSTS,EQEP_QEPSTS" bitfld.word 0x0 0. " PCEF ,Position counter error flag. This bit is not sticky and it is updated for every index event. 0x0 = No error occurred during the last index transition. 0x1 = Position counter error" "0,1" bitfld.word 0x0 1. " FIMF ,First index marker flag 0x0 = Sticky bit, cleared by writing 1 0x1 = Set by first occurrence of index pulse" "0,1" textline " " bitfld.word 0x0 2. " CDEF ,Capture direction error flag 0x0 = Sticky bit, cleared by writing 1 0x1 = Direction change occurred between the capture position event." "0,1" bitfld.word 0x0 3. " COEF ,Capture overflow error flag 0x0 = Sticky bit, cleared by writing 1 0x1 = Overflow occurred in eQEP Capture timer (QEPCTMR)" "0,1" textline " " bitfld.word 0x0 4. " QDLF ,eQEP direction latch flag. Status of direction is latched on every index event marker. 0x0 = Counter-clockwise rotation (or reverse movement) on index event marker 0x1 = Clockwise rotation (or forward movement) on index event marker" "0,1" bitfld.word 0x0 5. " QDF ,Quadrature direction flag 0x0 = Counter-clockwise rotation (or reverse movement) 0x1 = Clockwise rotation (or forward movement)" "0,1" textline " " bitfld.word 0x0 6. " FDF ,Direction on the first index marker. Status of the direction is latched on the first index event marker. 0x0 = Counter-clockwise rotation (or reverse movement) on the first index event 0x1 = Clockwise rotation (or forward movement) on the first index event" "0,1" bitfld.word 0x0 7. " UPEVNT ,Unit position event flag 0x0 = No unit position event detected 0x1 = Unit position event detected. Write 1 to clear." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x3A++0x1 line.word 0x0 "EQEP_QCTMR,EQEP_QCTMR" hexmask.word 0x0 0.--15. 1. " QCTMR ,This register provides time base for edge capture unit." group.byte 0x3C++0x1 line.word 0x0 "EQEP_QCPRD,EQEP_QCPRD" hexmask.word 0x0 0.--15. 1. " QCPRD ,This register holds the period count value between the last successive eQEP position events" group.byte 0x3E++0x1 line.word 0x0 "EQEP_QCTMRLAT,EQEP_QCTMRLAT" hexmask.word 0x0 0.--15. 1. " QCTMRLAT ,The eQEP capture timer value can be latched into this register on two events, that is, unit timeout event, reading the eQEP position counter." group.byte 0x40++0x1 line.word 0x0 "EQEP_QCPRDLAT,EQEP_QCPRDLAT" hexmask.word 0x0 0.--15. 1. " QCPRDLAT ,eQEP capture period value can be latched into this register on two events, that is, unit timeout event, reading the eQEP position counter." group.byte 0x5C++0x3 line.long 0x0 "EQEP_REVID,EQEP_REVID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "PWMSS2_EQEP" base ad:0x48440180 width 15. group.byte 0x0++0x3 line.long 0x0 "EQEP_QPOSCNT,EQEP_QPOSCNT" hexmask.long 0x0 0.--31. 1. " QPOSCNT ,This 32 bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point." group.byte 0x4++0x3 line.long 0x0 "EQEP_QPOSINIT,EQEP_QPOSINIT" hexmask.long 0x0 0.--31. 1. " QPOSINIT ,This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software." group.byte 0x8++0x3 line.long 0x0 "EQEP_QPOSMAX,EQEP_QPOSMAX" hexmask.long 0x0 0.--31. 1. " QPOSMAX ,This register contains the maximum position counter value." group.byte 0xC++0x3 line.long 0x0 "EQEP_QPOSCMP,EQEP_QPOSCMP" hexmask.long 0x0 0.--31. 1. " QPOSCMP ,The position-compare value in this register is compared with the position counter (QPOSCNT field in" group.byte 0x10++0x3 line.long 0x0 "EQEP_QPOSILAT,EQEP_QPOSILAT" hexmask.long 0x0 0.--31. 1. " QPOSILAT ,The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." group.byte 0x14++0x3 line.long 0x0 "EQEP_QPOSSLAT,EQEP_QPOSSLAT" hexmask.long 0x0 0.--31. 1. " QPOSSLAT ,The position-counter value is latched into this register on strobe event as defined by the QEPCTL[SEL] bits." group.byte 0x18++0x3 line.long 0x0 "EQEP_QPOSLAT,EQEP_QPOSLAT" hexmask.long 0x0 0.--31. 1. " QPOSLAT ,The position-counter value is latched into this register on unit time out event." group.byte 0x1C++0x3 line.long 0x0 "EQEP_QUTMR,EQEP_QUTMR" hexmask.long 0x0 0.--31. 1. " QUTMR ,This register acts as time base for unit time event generation. When this timer value matches with unit time period value, unit time event is generated." group.byte 0x20++0x3 line.long 0x0 "EQEP_QUPRD,EQEP_QUPRD" hexmask.long 0x0 0.--31. 1. " QUPRD ,This register contains the period count for unit timer to generate periodic unit time events to latch the eQEP position information at periodic interval and optionally to generate interrupt." group.byte 0x24++0x1 line.word 0x0 "EQEP_QWDTMR,EQEP_QWDTMR" hexmask.word 0x0 0.--15. 1. " QWDTMR ,This register acts as time base for watch dog to detect motor stalls. When this timer value matches with watch dog period value, watch dog timeout interrupt is generated. This register is reset upon edge transition in quadrature-clock indicating the motion." group.byte 0x26++0x1 line.word 0x0 "EQEP_QWDPRD,EQEP_QWDPRD" hexmask.word 0x0 0.--15. 1. " QWDPRD ,This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value, a watchdog timeout interrupt is generated." group.byte 0x28++0x1 line.word 0x0 "EQEP_QDECCTL,EQEP_QDECCTL" bitfld.word 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x0 5. " QSP ,QEPS input polarity 0x0 = No effect 0x1 = Negates QEPS input" "0,1" textline " " bitfld.word 0x0 6. " QIP ,QEPI input polarity 0x0 = No effect 0x1 = Negates QEPI input" "0,1" bitfld.word 0x0 7. " QBP ,QEPB input polarity 0x0 = No effect 0x1 = Negates QEPB input" "0,1" textline " " bitfld.word 0x0 8. " QAP ,QEPA input polarity 0x0 = No effect 0x1 = Negates QEPA input" "0,1" bitfld.word 0x0 9. " IGATE ,Index pulse gating option 0x0 = Disable gating of Index pulse 0x1 = Gate the index pin with strobe" "0,1" textline " " bitfld.word 0x0 10. " SWAP ,Swap quadrature clock inputs. This swaps the input to the quadrature decoder, reversing the counting direction. 0x0 = Quadrature-clock inputs are not swapped 0x1 = Quadrature-clock inputs are swapped" "0,1" bitfld.word 0x0 11. " XCR ,External clock rate 0x0 = 2x resolution: Count the rising/falling edge 0x1 = 1x resolution: Count the rising edge only" "0,1" textline " " bitfld.word 0x0 12. " SPSEL ,Sync output pin selection 0x0 = Index pin is used for sync output 0x1 = Strobe pin is used for sync output" "0,1" bitfld.word 0x0 13. " SOEN ,Sync output-enable 0x0 = Disable position-compare sync output 0x1 = Enable position-compare sync output" "0,1" textline " " bitfld.word 0x0 14.--15. " QSRC ,Position-counter source selection. 0x0 = Quadrature count mode (QCLK = iCLK, QDIR = iDIR) 0x1 = Direction-count mode (QCLK = xCLK, QDIR = xDIR) 0x2 = UP count mode for frequency measurement (QCLK = xCLK, QDIR = 1) 0x3 = DOWN count mode for frequency measurement (QCLK = xCLK, QDIR = 0)" "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "EQEP_QEPCTL,EQEP_QEPCTL" bitfld.word 0x0 0. " WDE ,eQEP watchdog enable 0x0 = Disable the eQEP watchdog timer 0x1 = Enable the eQEP watchdog timer" "0,1" bitfld.word 0x0 1. " UTE ,eQEP unit timer enable 0x0 = Disable eQEP unit timer 0x1 = Enable unit timer" "0,1" textline " " bitfld.word 0x0 2. " QCLM ,eQEP capture latch mode 0x0 = Latch on position counter read by CPU. Capture timer and capture period values are latched into 0x1 = Latch on unit time out. Position counter, capture timer and capture period values are latched into" "0,1" bitfld.word 0x0 3. " PHEN ,Quadrature position counter enable/software reset 0x0 = Reset the eQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. 0x1 = eQEP position counter is enabled" "0,1" textline " " bitfld.word 0x0 4.--5. " IEL ,Index event latch of position counter (software index marker) 0x0 = Reserved 0x1 = Latches position counter on rising edge of the index signal 0x2 = Latches position counter on falling edge of the index signal 0x3 = Software index marker. Latches the position counter and quadrature direction flag on index event marker. The position counter is latched to the" "0,1,2,3" bitfld.word 0x0 6. " SEL ,Strobe event latch of position counter 0x0 = The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the 0x1 = Clockwise Direction: Position counter is latched on rising edge of QEPS strobe. Counter Clockwise Direction: Position counter is latched on falling edge of QEPS strobe." "0,1" textline " " bitfld.word 0x0 7. " SWI ,Software initialization of position counter 0x0 = Do nothing (action disabled) 0x1 = Initialize position counter, this bit is cleared automatically" "0,1" bitfld.word 0x0 8.--9. " IEI ,Index event initialization of position counter 0x0 = Do nothing (action disabled) 0x1 = Do nothing (action disabled) 0x2 = Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT) 0x3 = Initializes the position counter on the falling edge of QEPI signal (QPOSCNT = QPOSINIT)" "0,1,2,3" textline " " bitfld.word 0x0 10.--11. " SEI ,Strobe event initialization of position counter 0x0 = Does nothing (action disabled) 0x1 = Does nothing (action disabled) 0x2 = Initializes the position counter on rising edge of the QEPS signal 0x3 = Clockwise Direction: Initializes the position counter on the rising edge of QEPS strobe. Counter Clockwise Direction: Initializes the position counter on the falling edge of QEPS strobe" "0,1,2,3" bitfld.word 0x0 12.--13. " PCRM ,Position counter reset mode 0x0 = Position counter reset on an index event 0x1 = Position counter reset on the maximum position 0x2 = Position counter reset on the first index event 0x3 = Position counter reset on a unit time event" "0,1,2,3" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control Bits. In the values 0 through 3 listed below, x is different for the four following behaviors. 0x0 = x stops immediately. For QPOSCNT behavior, the stop is on emulation suspend. 0x1 = x continues to count until the rollover. 0x2 = x is unaffected by emulation suspend. 0x3 = x is unaffected by emulation suspend." "0,1,2,3" group.byte 0x2C++0x1 line.word 0x0 "EQEP_QCAPCTL,EQEP_QCAPCTL" bitfld.word 0x0 0.--3. " UPPS ,Unit position event prescaler 0x0 = UPEVNT = QCLK/1 0x1 = UPEVNT = QCLK/2 0x2 = UPEVNT = QCLK/4 0x3 = UPEVNT = QCLK/8 0x4 = UPEVNT = QCLK/16 0x5 = UPEVNT = QCLK/32 0x6 = UPEVNT = QCLK/64 0x7 = UPEVNT = QCLK/128 0x8 = UPEVNT = QCLK/256 0x9 = UPEVNT = QCLK/512 0xA = UPEVNT = QCLK/1024 0xB = UPEVNT = QCLK/2048 0xC = Reserved 0xD = Reserved 0xE = Reserved 0xF = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0 4.--6. " CCPS ,eQEP capture timer clock prescaler 0x0 = CAPCLK = SYSCLKOUT/1 0x1 = CAPCLK = SYSCLKOUT/2 0x2 = CAPCLK = SYSCLKOUT/4 0x3 = CAPCLK = SYSCLKOUT/8 0x4 = CAPCLK = SYSCLKOUT/16 0x5 = CAPCLK = SYSCLKOUT/32 0x6 = CAPCLK = SYSCLKOUT/64 0x7 = CAPCLK = SYSCLKOUT/128" "0,1,2,3,4,5,6,7" textline " " hexmask.word.byte 0x0 7.--14. 1. " RESERVED ," bitfld.word 0x0 15. " CEN ,Enable eQEP capture 0x0 = eQEP capture unit is disabled 0x1 = eQEP capture unit is enabled" "0,1" group.byte 0x2E++0x1 line.word 0x0 "EQEP_QPOSCTL,EQEP_QPOSCTL" hexmask.word 0x0 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width ... 0x0 = 1 x 4 x SYSCLKOUT cycles 0x1 = 2 x 4 x SYSCLKOUT cycles 0x2 = 3 x 4 x SYSCLKOUT cycles to 4096 x 4 x SYSCLKOUT cycles 0xFFF = 3 x 4 x SYSCLKOUT cycles to 4096 x 4 x SYSCLKOUT cycles" bitfld.word 0x0 12. " PCE ,Position-compare enable/disable 0x0 = Disable position compare unit 0x1 = Enable position compare unit" "0,1" textline " " bitfld.word 0x0 13. " PCPOL ,Polarity of sync output 0x0 = Active HIGH pulse output 0x1 = Active LOW pulse output" "0,1" bitfld.word 0x0 14. " PCLOAD ,Position-compare shadow load mode 0x0 = Load on QPOSCNT = 0 0x1 = Load when QPOSCNT = QPOSCMP" "0,1" textline " " bitfld.word 0x0 15. " PCSHDW ,Position-compare shadow enable 0x0 = Shadow disabled, load Immediate 0x1 = Shadow enabled" "0,1" group.byte 0x30++0x1 line.word 0x0 "EQEP_QEINT,EQEP_QEINT" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " PCE ,Position counter error interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Quadrature phase error interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 3. " QDC ,Quadrature direction change interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Watchdog time out interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 5. " PCU ,Position counter underflow interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 6. " PCO ,Position counter overflow interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 7. " PCR ,Position-compare ready interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 8. " PCM ,Position-compare match interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 9. " SEL ,Strobe event latch interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Index event latch interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 11. " UTO ,Unit time out interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x32++0x1 line.word 0x0 "EQEP_QFLG,EQEP_QFLG" bitfld.word 0x0 0. " INT ,Global interrupt status flag 0x0 = No interrupt generated 0x1 = Interrupt was generated" "0,1" bitfld.word 0x0 1. " PCE ,Position counter error interrupt flag 0x0 = No interrupt generated 0x1 = Position counter error" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Quadrature phase error interrupt flag 0x0 = No interrupt generated 0x1 = Set on simultaneous transition of QEPA and QEPB" "0,1" bitfld.word 0x0 3. " QDC ,Quadrature direction change interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set during change of direction" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Watchdog timeout interrupt flag 0x0 = No interrupt generated 0x1 = Set by watch dog timeout" "0,1" bitfld.word 0x0 5. " PCU ,Position counter underflow interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set on position counter underflow." "0,1" textline " " bitfld.word 0x0 6. " PCO ,Position counter overflow interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set on position counter overflow." "0,1" bitfld.word 0x0 7. " PCR ,Position-compare ready interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set after transferring the shadow register value to the active position compare register." "0,1" textline " " bitfld.word 0x0 8. " PCM ,eQEP compare match event interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set on position-compare match" "0,1" bitfld.word 0x0 9. " SEL ,Strobe event latch interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set after latching the QPOSCNT to" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Index event latch interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set after latching the QPOSCNT to QPOSILAT" "0,1" bitfld.word 0x0 11. " UTO ,Unit time out interrupt flag 0x0 = No interrupt generated 0x1 = Set by eQEP unit timer period match" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x34++0x1 line.word 0x0 "EQEP_QCLR,EQEP_QCLR" bitfld.word 0x0 0. " INT ,Global interrupt clear flag 0x0 = No effect 0x1 = Clears the interrupt flag and enables further interrupts to be generated if an event flags is set to 1." "0,1" bitfld.word 0x0 1. " PCE ,Clear position counter error interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Clear quadrature phase error interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 3. " QDC ,Clear quadrature direction change interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Clear watchdog timeout interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 5. " PCU ,Clear position counter underflow interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 6. " PCO ,Clear position counter overflow interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 7. " PCR ,Clear position-compare ready interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 8. " PCM ,Clear eQEP compare match event interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 9. " SEL ,Clear strobe event latch interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Clear index event latch interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 11. " UTO ,Clear unit time out interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x36++0x1 line.word 0x0 "EQEP_QFRC,EQEP_QFRC" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " PCE ,Force position counter error interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Force quadrature phase error interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 3. " QDC ,Force quadrature direction change interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Force watchdog time out interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 5. " PCU ,Force position counter underflow interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 6. " PCO ,Force position counter overflow interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 7. " PCR ,Force position-compare ready interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 8. " PCM ,Force position-compare match interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 9. " SEL ,Force strobe event latch interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Force index event latch interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 11. " UTO ,Force unit time out interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x38++0x1 line.word 0x0 "EQEP_QEPSTS,EQEP_QEPSTS" bitfld.word 0x0 0. " PCEF ,Position counter error flag. This bit is not sticky and it is updated for every index event. 0x0 = No error occurred during the last index transition. 0x1 = Position counter error" "0,1" bitfld.word 0x0 1. " FIMF ,First index marker flag 0x0 = Sticky bit, cleared by writing 1 0x1 = Set by first occurrence of index pulse" "0,1" textline " " bitfld.word 0x0 2. " CDEF ,Capture direction error flag 0x0 = Sticky bit, cleared by writing 1 0x1 = Direction change occurred between the capture position event." "0,1" bitfld.word 0x0 3. " COEF ,Capture overflow error flag 0x0 = Sticky bit, cleared by writing 1 0x1 = Overflow occurred in eQEP Capture timer (QEPCTMR)" "0,1" textline " " bitfld.word 0x0 4. " QDLF ,eQEP direction latch flag. Status of direction is latched on every index event marker. 0x0 = Counter-clockwise rotation (or reverse movement) on index event marker 0x1 = Clockwise rotation (or forward movement) on index event marker" "0,1" bitfld.word 0x0 5. " QDF ,Quadrature direction flag 0x0 = Counter-clockwise rotation (or reverse movement) 0x1 = Clockwise rotation (or forward movement)" "0,1" textline " " bitfld.word 0x0 6. " FDF ,Direction on the first index marker. Status of the direction is latched on the first index event marker. 0x0 = Counter-clockwise rotation (or reverse movement) on the first index event 0x1 = Clockwise rotation (or forward movement) on the first index event" "0,1" bitfld.word 0x0 7. " UPEVNT ,Unit position event flag 0x0 = No unit position event detected 0x1 = Unit position event detected. Write 1 to clear." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x3A++0x1 line.word 0x0 "EQEP_QCTMR,EQEP_QCTMR" hexmask.word 0x0 0.--15. 1. " QCTMR ,This register provides time base for edge capture unit." group.byte 0x3C++0x1 line.word 0x0 "EQEP_QCPRD,EQEP_QCPRD" hexmask.word 0x0 0.--15. 1. " QCPRD ,This register holds the period count value between the last successive eQEP position events" group.byte 0x3E++0x1 line.word 0x0 "EQEP_QCTMRLAT,EQEP_QCTMRLAT" hexmask.word 0x0 0.--15. 1. " QCTMRLAT ,The eQEP capture timer value can be latched into this register on two events, that is, unit timeout event, reading the eQEP position counter." group.byte 0x40++0x1 line.word 0x0 "EQEP_QCPRDLAT,EQEP_QCPRDLAT" hexmask.word 0x0 0.--15. 1. " QCPRDLAT ,eQEP capture period value can be latched into this register on two events, that is, unit timeout event, reading the eQEP position counter." group.byte 0x5C++0x3 line.long 0x0 "EQEP_REVID,EQEP_REVID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "PWMSS3_EQEP" base ad:0x48442180 width 15. group.byte 0x0++0x3 line.long 0x0 "EQEP_QPOSCNT,EQEP_QPOSCNT" hexmask.long 0x0 0.--31. 1. " QPOSCNT ,This 32 bit position counter register counts up/down on every eQEP pulse based on direction input. This counter acts as a position integrator whose count value is proportional to position from a give reference point." group.byte 0x4++0x3 line.long 0x0 "EQEP_QPOSINIT,EQEP_QPOSINIT" hexmask.long 0x0 0.--31. 1. " QPOSINIT ,This register contains the position value that is used to initialize the position counter based on external strobe or index event. The position counter can be initialized through software." group.byte 0x8++0x3 line.long 0x0 "EQEP_QPOSMAX,EQEP_QPOSMAX" hexmask.long 0x0 0.--31. 1. " QPOSMAX ,This register contains the maximum position counter value." group.byte 0xC++0x3 line.long 0x0 "EQEP_QPOSCMP,EQEP_QPOSCMP" hexmask.long 0x0 0.--31. 1. " QPOSCMP ,The position-compare value in this register is compared with the position counter (QPOSCNT field in" group.byte 0x10++0x3 line.long 0x0 "EQEP_QPOSILAT,EQEP_QPOSILAT" hexmask.long 0x0 0.--31. 1. " QPOSILAT ,The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits." group.byte 0x14++0x3 line.long 0x0 "EQEP_QPOSSLAT,EQEP_QPOSSLAT" hexmask.long 0x0 0.--31. 1. " QPOSSLAT ,The position-counter value is latched into this register on strobe event as defined by the QEPCTL[SEL] bits." group.byte 0x18++0x3 line.long 0x0 "EQEP_QPOSLAT,EQEP_QPOSLAT" hexmask.long 0x0 0.--31. 1. " QPOSLAT ,The position-counter value is latched into this register on unit time out event." group.byte 0x1C++0x3 line.long 0x0 "EQEP_QUTMR,EQEP_QUTMR" hexmask.long 0x0 0.--31. 1. " QUTMR ,This register acts as time base for unit time event generation. When this timer value matches with unit time period value, unit time event is generated." group.byte 0x20++0x3 line.long 0x0 "EQEP_QUPRD,EQEP_QUPRD" hexmask.long 0x0 0.--31. 1. " QUPRD ,This register contains the period count for unit timer to generate periodic unit time events to latch the eQEP position information at periodic interval and optionally to generate interrupt." group.byte 0x24++0x1 line.word 0x0 "EQEP_QWDTMR,EQEP_QWDTMR" hexmask.word 0x0 0.--15. 1. " QWDTMR ,This register acts as time base for watch dog to detect motor stalls. When this timer value matches with watch dog period value, watch dog timeout interrupt is generated. This register is reset upon edge transition in quadrature-clock indicating the motion." group.byte 0x26++0x1 line.word 0x0 "EQEP_QWDPRD,EQEP_QWDPRD" hexmask.word 0x0 0.--15. 1. " QWDPRD ,This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value, a watchdog timeout interrupt is generated." group.byte 0x28++0x1 line.word 0x0 "EQEP_QDECCTL,EQEP_QDECCTL" bitfld.word 0x0 0.--4. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.word 0x0 5. " QSP ,QEPS input polarity 0x0 = No effect 0x1 = Negates QEPS input" "0,1" textline " " bitfld.word 0x0 6. " QIP ,QEPI input polarity 0x0 = No effect 0x1 = Negates QEPI input" "0,1" bitfld.word 0x0 7. " QBP ,QEPB input polarity 0x0 = No effect 0x1 = Negates QEPB input" "0,1" textline " " bitfld.word 0x0 8. " QAP ,QEPA input polarity 0x0 = No effect 0x1 = Negates QEPA input" "0,1" bitfld.word 0x0 9. " IGATE ,Index pulse gating option 0x0 = Disable gating of Index pulse 0x1 = Gate the index pin with strobe" "0,1" textline " " bitfld.word 0x0 10. " SWAP ,Swap quadrature clock inputs. This swaps the input to the quadrature decoder, reversing the counting direction. 0x0 = Quadrature-clock inputs are not swapped 0x1 = Quadrature-clock inputs are swapped" "0,1" bitfld.word 0x0 11. " XCR ,External clock rate 0x0 = 2x resolution: Count the rising/falling edge 0x1 = 1x resolution: Count the rising edge only" "0,1" textline " " bitfld.word 0x0 12. " SPSEL ,Sync output pin selection 0x0 = Index pin is used for sync output 0x1 = Strobe pin is used for sync output" "0,1" bitfld.word 0x0 13. " SOEN ,Sync output-enable 0x0 = Disable position-compare sync output 0x1 = Enable position-compare sync output" "0,1" textline " " bitfld.word 0x0 14.--15. " QSRC ,Position-counter source selection. 0x0 = Quadrature count mode (QCLK = iCLK, QDIR = iDIR) 0x1 = Direction-count mode (QCLK = xCLK, QDIR = xDIR) 0x2 = UP count mode for frequency measurement (QCLK = xCLK, QDIR = 1) 0x3 = DOWN count mode for frequency measurement (QCLK = xCLK, QDIR = 0)" "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "EQEP_QEPCTL,EQEP_QEPCTL" bitfld.word 0x0 0. " WDE ,eQEP watchdog enable 0x0 = Disable the eQEP watchdog timer 0x1 = Enable the eQEP watchdog timer" "0,1" bitfld.word 0x0 1. " UTE ,eQEP unit timer enable 0x0 = Disable eQEP unit timer 0x1 = Enable unit timer" "0,1" textline " " bitfld.word 0x0 2. " QCLM ,eQEP capture latch mode 0x0 = Latch on position counter read by CPU. Capture timer and capture period values are latched into 0x1 = Latch on unit time out. Position counter, capture timer and capture period values are latched into" "0,1" bitfld.word 0x0 3. " PHEN ,Quadrature position counter enable/software reset 0x0 = Reset the eQEP peripheral internal operating flags/read-only registers. Control/configuration registers are not disturbed by a software reset. 0x1 = eQEP position counter is enabled" "0,1" textline " " bitfld.word 0x0 4.--5. " IEL ,Index event latch of position counter (software index marker) 0x0 = Reserved 0x1 = Latches position counter on rising edge of the index signal 0x2 = Latches position counter on falling edge of the index signal 0x3 = Software index marker. Latches the position counter and quadrature direction flag on index event marker. The position counter is latched to the" "0,1,2,3" bitfld.word 0x0 6. " SEL ,Strobe event latch of position counter 0x0 = The position counter is latched on the rising edge of QEPS strobe (QPOSSLAT = POSCCNT). Latching on the falling edge can be done by inverting the strobe input using the QSP bit in the 0x1 = Clockwise Direction: Position counter is latched on rising edge of QEPS strobe. Counter Clockwise Direction: Position counter is latched on falling edge of QEPS strobe." "0,1" textline " " bitfld.word 0x0 7. " SWI ,Software initialization of position counter 0x0 = Do nothing (action disabled) 0x1 = Initialize position counter, this bit is cleared automatically" "0,1" bitfld.word 0x0 8.--9. " IEI ,Index event initialization of position counter 0x0 = Do nothing (action disabled) 0x1 = Do nothing (action disabled) 0x2 = Initializes the position counter on the rising edge of the QEPI signal (QPOSCNT = QPOSINIT) 0x3 = Initializes the position counter on the falling edge of QEPI signal (QPOSCNT = QPOSINIT)" "0,1,2,3" textline " " bitfld.word 0x0 10.--11. " SEI ,Strobe event initialization of position counter 0x0 = Does nothing (action disabled) 0x1 = Does nothing (action disabled) 0x2 = Initializes the position counter on rising edge of the QEPS signal 0x3 = Clockwise Direction: Initializes the position counter on the rising edge of QEPS strobe. Counter Clockwise Direction: Initializes the position counter on the falling edge of QEPS strobe" "0,1,2,3" bitfld.word 0x0 12.--13. " PCRM ,Position counter reset mode 0x0 = Position counter reset on an index event 0x1 = Position counter reset on the maximum position 0x2 = Position counter reset on the first index event 0x3 = Position counter reset on a unit time event" "0,1,2,3" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control Bits. In the values 0 through 3 listed below, x is different for the four following behaviors. 0x0 = x stops immediately. For QPOSCNT behavior, the stop is on emulation suspend. 0x1 = x continues to count until the rollover. 0x2 = x is unaffected by emulation suspend. 0x3 = x is unaffected by emulation suspend." "0,1,2,3" group.byte 0x2C++0x1 line.word 0x0 "EQEP_QCAPCTL,EQEP_QCAPCTL" bitfld.word 0x0 0.--3. " UPPS ,Unit position event prescaler 0x0 = UPEVNT = QCLK/1 0x1 = UPEVNT = QCLK/2 0x2 = UPEVNT = QCLK/4 0x3 = UPEVNT = QCLK/8 0x4 = UPEVNT = QCLK/16 0x5 = UPEVNT = QCLK/32 0x6 = UPEVNT = QCLK/64 0x7 = UPEVNT = QCLK/128 0x8 = UPEVNT = QCLK/256 0x9 = UPEVNT = QCLK/512 0xA = UPEVNT = QCLK/1024 0xB = UPEVNT = QCLK/2048 0xC = Reserved 0xD = Reserved 0xE = Reserved 0xF = Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x0 4.--6. " CCPS ,eQEP capture timer clock prescaler 0x0 = CAPCLK = SYSCLKOUT/1 0x1 = CAPCLK = SYSCLKOUT/2 0x2 = CAPCLK = SYSCLKOUT/4 0x3 = CAPCLK = SYSCLKOUT/8 0x4 = CAPCLK = SYSCLKOUT/16 0x5 = CAPCLK = SYSCLKOUT/32 0x6 = CAPCLK = SYSCLKOUT/64 0x7 = CAPCLK = SYSCLKOUT/128" "0,1,2,3,4,5,6,7" textline " " hexmask.word.byte 0x0 7.--14. 1. " RESERVED ," bitfld.word 0x0 15. " CEN ,Enable eQEP capture 0x0 = eQEP capture unit is disabled 0x1 = eQEP capture unit is enabled" "0,1" group.byte 0x2E++0x1 line.word 0x0 "EQEP_QPOSCTL,EQEP_QPOSCTL" hexmask.word 0x0 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width ... 0x0 = 1 x 4 x SYSCLKOUT cycles 0x1 = 2 x 4 x SYSCLKOUT cycles 0x2 = 3 x 4 x SYSCLKOUT cycles to 4096 x 4 x SYSCLKOUT cycles 0xFFF = 3 x 4 x SYSCLKOUT cycles to 4096 x 4 x SYSCLKOUT cycles" bitfld.word 0x0 12. " PCE ,Position-compare enable/disable 0x0 = Disable position compare unit 0x1 = Enable position compare unit" "0,1" textline " " bitfld.word 0x0 13. " PCPOL ,Polarity of sync output 0x0 = Active HIGH pulse output 0x1 = Active LOW pulse output" "0,1" bitfld.word 0x0 14. " PCLOAD ,Position-compare shadow load mode 0x0 = Load on QPOSCNT = 0 0x1 = Load when QPOSCNT = QPOSCMP" "0,1" textline " " bitfld.word 0x0 15. " PCSHDW ,Position-compare shadow enable 0x0 = Shadow disabled, load Immediate 0x1 = Shadow enabled" "0,1" group.byte 0x30++0x1 line.word 0x0 "EQEP_QEINT,EQEP_QEINT" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " PCE ,Position counter error interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Quadrature phase error interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 3. " QDC ,Quadrature direction change interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Watchdog time out interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 5. " PCU ,Position counter underflow interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 6. " PCO ,Position counter overflow interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 7. " PCR ,Position-compare ready interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 8. " PCM ,Position-compare match interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 9. " SEL ,Strobe event latch interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Index event latch interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" bitfld.word 0x0 11. " UTO ,Unit time out interrupt enable 0x0 = Interrupt is disabled 0x1 = Interrupt is enabled" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x32++0x1 line.word 0x0 "EQEP_QFLG,EQEP_QFLG" bitfld.word 0x0 0. " INT ,Global interrupt status flag 0x0 = No interrupt generated 0x1 = Interrupt was generated" "0,1" bitfld.word 0x0 1. " PCE ,Position counter error interrupt flag 0x0 = No interrupt generated 0x1 = Position counter error" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Quadrature phase error interrupt flag 0x0 = No interrupt generated 0x1 = Set on simultaneous transition of QEPA and QEPB" "0,1" bitfld.word 0x0 3. " QDC ,Quadrature direction change interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set during change of direction" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Watchdog timeout interrupt flag 0x0 = No interrupt generated 0x1 = Set by watch dog timeout" "0,1" bitfld.word 0x0 5. " PCU ,Position counter underflow interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set on position counter underflow." "0,1" textline " " bitfld.word 0x0 6. " PCO ,Position counter overflow interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set on position counter overflow." "0,1" bitfld.word 0x0 7. " PCR ,Position-compare ready interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set after transferring the shadow register value to the active position compare register." "0,1" textline " " bitfld.word 0x0 8. " PCM ,eQEP compare match event interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set on position-compare match" "0,1" bitfld.word 0x0 9. " SEL ,Strobe event latch interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set after latching the QPOSCNT to" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Index event latch interrupt flag 0x0 = No interrupt generated 0x1 = This bit is set after latching the QPOSCNT to QPOSILAT" "0,1" bitfld.word 0x0 11. " UTO ,Unit time out interrupt flag 0x0 = No interrupt generated 0x1 = Set by eQEP unit timer period match" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x34++0x1 line.word 0x0 "EQEP_QCLR,EQEP_QCLR" bitfld.word 0x0 0. " INT ,Global interrupt clear flag 0x0 = No effect 0x1 = Clears the interrupt flag and enables further interrupts to be generated if an event flags is set to 1." "0,1" bitfld.word 0x0 1. " PCE ,Clear position counter error interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Clear quadrature phase error interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 3. " QDC ,Clear quadrature direction change interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Clear watchdog timeout interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 5. " PCU ,Clear position counter underflow interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 6. " PCO ,Clear position counter overflow interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 7. " PCR ,Clear position-compare ready interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 8. " PCM ,Clear eQEP compare match event interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 9. " SEL ,Clear strobe event latch interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Clear index event latch interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" bitfld.word 0x0 11. " UTO ,Clear unit time out interrupt flag 0x0 = No effect 0x1 = Clears the interrupt flag" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x36++0x1 line.word 0x0 "EQEP_QFRC,EQEP_QFRC" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " PCE ,Force position counter error interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 2. " PHE ,Force quadrature phase error interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 3. " QDC ,Force quadrature direction change interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 4. " WTO ,Force watchdog time out interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 5. " PCU ,Force position counter underflow interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 6. " PCO ,Force position counter overflow interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 7. " PCR ,Force position-compare ready interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 8. " PCM ,Force position-compare match interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 9. " SEL ,Force strobe event latch interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 10. " IEL ,Force index event latch interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" bitfld.word 0x0 11. " UTO ,Force unit time out interrupt 0x0 = No effect 0x1 = Force the interrupt" "0,1" textline " " bitfld.word 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x38++0x1 line.word 0x0 "EQEP_QEPSTS,EQEP_QEPSTS" bitfld.word 0x0 0. " PCEF ,Position counter error flag. This bit is not sticky and it is updated for every index event. 0x0 = No error occurred during the last index transition. 0x1 = Position counter error" "0,1" bitfld.word 0x0 1. " FIMF ,First index marker flag 0x0 = Sticky bit, cleared by writing 1 0x1 = Set by first occurrence of index pulse" "0,1" textline " " bitfld.word 0x0 2. " CDEF ,Capture direction error flag 0x0 = Sticky bit, cleared by writing 1 0x1 = Direction change occurred between the capture position event." "0,1" bitfld.word 0x0 3. " COEF ,Capture overflow error flag 0x0 = Sticky bit, cleared by writing 1 0x1 = Overflow occurred in eQEP Capture timer (QEPCTMR)" "0,1" textline " " bitfld.word 0x0 4. " QDLF ,eQEP direction latch flag. Status of direction is latched on every index event marker. 0x0 = Counter-clockwise rotation (or reverse movement) on index event marker 0x1 = Clockwise rotation (or forward movement) on index event marker" "0,1" bitfld.word 0x0 5. " QDF ,Quadrature direction flag 0x0 = Counter-clockwise rotation (or reverse movement) 0x1 = Clockwise rotation (or forward movement)" "0,1" textline " " bitfld.word 0x0 6. " FDF ,Direction on the first index marker. Status of the direction is latched on the first index event marker. 0x0 = Counter-clockwise rotation (or reverse movement) on the first index event 0x1 = Clockwise rotation (or forward movement) on the first index event" "0,1" bitfld.word 0x0 7. " UPEVNT ,Unit position event flag 0x0 = No unit position event detected 0x1 = Unit position event detected. Write 1 to clear." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x3A++0x1 line.word 0x0 "EQEP_QCTMR,EQEP_QCTMR" hexmask.word 0x0 0.--15. 1. " QCTMR ,This register provides time base for edge capture unit." group.byte 0x3C++0x1 line.word 0x0 "EQEP_QCPRD,EQEP_QCPRD" hexmask.word 0x0 0.--15. 1. " QCPRD ,This register holds the period count value between the last successive eQEP position events" group.byte 0x3E++0x1 line.word 0x0 "EQEP_QCTMRLAT,EQEP_QCTMRLAT" hexmask.word 0x0 0.--15. 1. " QCTMRLAT ,The eQEP capture timer value can be latched into this register on two events, that is, unit timeout event, reading the eQEP position counter." group.byte 0x40++0x1 line.word 0x0 "EQEP_QCPRDLAT,EQEP_QCPRDLAT" hexmask.word 0x0 0.--15. 1. " QCPRDLAT ,eQEP capture period value can be latched into this register on two events, that is, unit timeout event, reading the eQEP position counter." group.byte 0x5C++0x3 line.long 0x0 "EQEP_REVID,EQEP_REVID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "DRM" base ad:0x54160000 width 20. group.byte 0x200++0x3 line.long 0x0 "DRM_SUSPEND_CTRL0,DRM_SUSPEND_CTRL0" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x204++0x3 line.long 0x0 "DRM_SUSPEND_CTRL1,DRM_SUSPEND_CTRL1" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x208++0x3 line.long 0x0 "DRM_SUSPEND_CTRL2,DRM_SUSPEND_CTRL2" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x20C++0x3 line.long 0x0 "DRM_SUSPEND_CTRL3,DRM_SUSPEND_CTRL3" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x210++0x3 line.long 0x0 "DRM_SUSPEND_CTRL4,DRM_SUSPEND_CTRL4" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x214++0x3 line.long 0x0 "DRM_SUSPEND_CTRL5,DRM_SUSPEND_CTRL5" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x218++0x3 line.long 0x0 "DRM_SUSPEND_CTRL6,DRM_SUSPEND_CTRL6" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x21C++0x3 line.long 0x0 "DRM_SUSPEND_CTRL7,DRM_SUSPEND_CTRL7" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x220++0x3 line.long 0x0 "DRM_SUSPEND_CTRL8,DRM_SUSPEND_CTRL8" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x224++0x3 line.long 0x0 "DRM_SUSPEND_CTRL9,DRM_SUSPEND_CTRL9" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x228++0x3 line.long 0x0 "DRM_SUSPEND_CTRL10,DRM_SUSPEND_CTRL10" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x22C++0x3 line.long 0x0 "DRM_SUSPEND_CTRL11,DRM_SUSPEND_CTRL11" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x230++0x3 line.long 0x0 "DRM_SUSPEND_CTRL12,DRM_SUSPEND_CTRL12" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x234++0x3 line.long 0x0 "DRM_SUSPEND_CTRL13,DRM_SUSPEND_CTRL13" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x238++0x3 line.long 0x0 "DRM_SUSPEND_CTRL14,DRM_SUSPEND_CTRL14" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x23C++0x3 line.long 0x0 "DRM_SUSPEND_CTRL15,DRM_SUSPEND_CTRL15" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x240++0x3 line.long 0x0 "DRM_SUSPEND_CTRL16,DRM_SUSPEND_CTRL16" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x244++0x3 line.long 0x0 "DRM_SUSPEND_CTRL17,DRM_SUSPEND_CTRL17" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x248++0x3 line.long 0x0 "DRM_SUSPEND_CTRL18,DRM_SUSPEND_CTRL18" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x24C++0x3 line.long 0x0 "DRM_SUSPEND_CTRL19,DRM_SUSPEND_CTRL19" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x250++0x3 line.long 0x0 "DRM_SUSPEND_CTRL20,DRM_SUSPEND_CTRL20" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x254++0x3 line.long 0x0 "DRM_SUSPEND_CTRL21,DRM_SUSPEND_CTRL21" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x258++0x3 line.long 0x0 "DRM_SUSPEND_CTRL22,DRM_SUSPEND_CTRL22" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x25C++0x3 line.long 0x0 "DRM_SUSPEND_CTRL23,DRM_SUSPEND_CTRL23" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x260++0x3 line.long 0x0 "DRM_SUSPEND_CTRL24,DRM_SUSPEND_CTRL24" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x264++0x3 line.long 0x0 "DRM_SUSPEND_CTRL25,DRM_SUSPEND_CTRL25" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x268++0x3 line.long 0x0 "DRM_SUSPEND_CTRL26,DRM_SUSPEND_CTRL26" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x26C++0x3 line.long 0x0 "DRM_SUSPEND_CTRL27,DRM_SUSPEND_CTRL27" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x270++0x3 line.long 0x0 "DRM_SUSPEND_CTRL28,DRM_SUSPEND_CTRL28" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x274++0x3 line.long 0x0 "DRM_SUSPEND_CTRL29,DRM_SUSPEND_CTRL29" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x278++0x3 line.long 0x0 "DRM_SUSPEND_CTRL30,DRM_SUSPEND_CTRL30" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x27C++0x3 line.long 0x0 "DRM_SUSPEND_CTRL31,DRM_SUSPEND_CTRL31" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x280++0x3 line.long 0x0 "DRM_SUSPEND_CTRL32,DRM_SUSPEND_CTRL32" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x284++0x3 line.long 0x0 "DRM_SUSPEND_CTRL33,DRM_SUSPEND_CTRL33" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x288++0x3 line.long 0x0 "DRM_SUSPEND_CTRL34,DRM_SUSPEND_CTRL34" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x28C++0x3 line.long 0x0 "DRM_SUSPEND_CTRL35,DRM_SUSPEND_CTRL35" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x290++0x3 line.long 0x0 "DRM_SUSPEND_CTRL36,DRM_SUSPEND_CTRL36" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" group.byte 0x294++0x3 line.long 0x0 "DRM_SUSPEND_CTRL37,susp" bitfld.long 0x0 0. " SENSCTRL ,Sensitivity Control for suspend signals. When SUSPEND_DEFAULT_OVERRIDE=1, this bit is ignored and read as a 1. When SUSPEND_DEFAULT_OVERRIDE=0, 0: Suspend signal will not reach the peripheral. Peripheral will act as normal even during a debug halt. 1: Suspend signal will reach the peripheral. Peripheral will be suspended during debug halt." "0,1" bitfld.long 0x0 1.--2. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 3. " SUSPEND_DEFAULT_OVERRIDE ,Enable or disable the override value in SUSPEND_SEL. 0: SUSPEND_SEL field will select which suspend signal reaches the peripheral. 1: SUSPEND_SEL field ignored. Default suspend signal will reach the peripheral." "0,1" bitfld.long 0x0 4.--8. " SUSPEND_SEL ,Suspend signal selection. Selects which suspend signal affects the peripheral. Only valid when SUSPEND_DEFAULT_OVERRIDE=0 and SENSCTRL=1. When read, these bits reflect the default suspend signal. 0000b: CPU suspend signal. All other values are reserved." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "MPU_MA_WP" base ad:0x482AF200 width 32. group.byte 0x0++0x3 line.long 0x0 "DBG_HWWP_CAP,Debug Watchpoint Capabilities Register" bitfld.long 0x0 0.--3. " NUM_WP ,Number of Watchpoints supported (0-15)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--6. " ADDR_WIDTH ,Address Bus Width 0x0: 8 bits 0x1: 16 bits 0x2: 24 bits 0x3: 32 bits 0x4: 36 bits 0x5: 40 bits 0x6: 64 bits 0x7: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 7. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 8.--10. " DATA_WIDTH ,Data Bus Width 0x0: 8 bits 0x1: 16 bits 0x2: 32 bits 0x3: 64 bits 0x4: 128 bits All other values: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12. " HWWP_AUX_CNTL_REG_PRESENT ,Auxillary Control Register implementation 0x0: Not present 0x1: Present" "0,1" textline " " bitfld.long 0x0 13. " HWWP_TRANS_ATTR0_REG_PRESENT ,Transaction Attribute 0 Register implementation 0x0: Not present 0x1: Present" "0,1" bitfld.long 0x0 14. " HWWP_TRANS_ATTR1_REG_PRESENT ,Transaction Attribute 1 Register implementation 0x0: Not present 0x1: Present" "0,1" textline " " bitfld.long 0x0 15. " HWWP_MEM_CHAIN_REG_PRESENT ,Memory Barrier Chain Control Register implementation 0x0: Not present 0x1: Present" "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "TRIG_CTRL,Trigger Control Register" bitfld.long 0x0 0. " TRIG_EN ,0x0: Trigger disabled. Trigger output (MA_WP_TRIGGER) will not fire 0x1: Trigger enabled. Trigger output (MA_WP_TRIGGER) will fire" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "DBG_HWWP0_LW_ADDR0,Debug Watchpoint Addr0 Register (lower order bits 31:0). This register should be written only when WP_EN=0." hexmask.long 0x0 0.--31. 1. " LOWER_ORDER_WP_ADDR ,The byte-addressable lower order AXI-4 physical watchpoint address to monitor" group.byte 0xC++0x3 line.long 0x0 "DBG_HWWP0_HG_ADDR0,Debug Watchpoint Addr0 Register (higher order bits 39:32). This register should be written only when WP_EN=0." hexmask.long.byte 0x0 0.--7. 1. " HIGHER_ORDER_WP_ADDR ,The byte-addressable higher order AXI-4 physical watchpoint address to monitor" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "DBG_HWWP0_MAIN_CNTL,Debug Watchpoint Main Control Register" bitfld.long 0x0 0. " WP_EN ,Watchpoint enable 0x0: Disable the watchpoint 0x1: Enable the watchpoint" "0,1" bitfld.long 0x0 1.--3. " WP_LS_ACCESS ,Watchpoint Load/Store access 0x0: (Load) Load exclusive or swap 0x1: (Store) Store exclusive or swap (non-posted) 0x2: (Store) Store exclusive or swap (posted) 0x3: Any type of store 0x4, 0x5, 0x6: Reserved 0x7: No preference (valid only if CHAIN_WP_EN=0; otherwise, reserved) Note: In the case of CHAIN_WP_EN=1, both data and memory barrier watchpoints must have the same transaction type; that is, both must be read or both must be write" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4. " WP_MATCH_CRITERIA ,Watchpoint match criteria 0x0: Match if access within address range to include MIN and MAX 0x1: Match if access outside address range" "0,1" bitfld.long 0x0 5.--10. " WP_ADDR_MASK ,Watchpoint address mask (bits to ignore) 0x0: Ignore address bit 0 ..... 0x27: Ignore address bit 39 0x28  0x3F: Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 11. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 12.--13. " SECURE_ACCESS ,Secure/Non-secure access 0x0: Reserved 0x1: Non-secure 0x2: Secure. Not supported on GP device 0x3: No preference" "0,1,2,3" textline " " bitfld.long 0x0 14.--15. " SUPERVISOR_USER_ACCESS ,Supervisor/User access 0x0: Reserved 0x1: User 0x2: Supervisor 0x3: No preference" "0,1,2,3" bitfld.long 0x0 16. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 17.--19. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20.--23. " BEAT_SEL ,Beat Select (This parameter decides upon for which beat of the burst the data byte lanes should be captured data)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x0 24.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " TRIG ,Watchpoint trigger 0x0: Watchpoint not triggered 0x1: Watchpoint has triggered (Reset upon 0->1 transition of WP_EN)" "0,1" group.byte 0x14++0x3 line.long 0x0 "DBG_HWWP0_AUX_CNTL,Debug Watchpoint Auxilliary Control Register. This register should be written only when WP_EN=0." bitfld.long 0x0 0.--1. " ACCESS_TYPE ,Access type 0x0: Reserved 0x1: Instructions 0x2: Data/others 0x3: No preference" "0,1,2,3" bitfld.long 0x0 2.--3. " RESERVED ,Reserved" "0,1,2,3" textline " " bitfld.long 0x0 4.--6. " INITIATOR_ID ,Initiator ID 0x0: CPU_0 0x1: CPU_1 0x2: CPU_2. Not supported on this device 0x3: CPU_3. Not supported on this device 0x4: Unknown source (ACP, FEQ, etc) 0x5: CMU. Not supported on this device 0x6: Reserved 0x7: No preference" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 7.--13. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 14.--15. " MA_SPLIT_TARG ,MA splitter target 0x0: Reserved 0x1: AXI2OCP bridge 0x2: EMIF 0x3: No preference" "0,1,2,3" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "DBG_HWWP0_MEM_CNTL,Debug Watchpoint Memory Barrier Control Register. This register should be written only when WP_EN=0." bitfld.long 0x0 0. " MEM_BAR_WP_EN ,Memory barrier watchpoint enable 0x0: Disable the watchpoint 0x1: Enable the watchpoint" "0,1" bitfld.long 0x0 1.--2. " MEM_BAR_TYPE ,Memory barrier type 0x0: Reserved 0x1: DSB 0x2: DMB 0x3: No preference" "0,1,2,3" textline " " bitfld.long 0x0 3.--4. " MEM_BAR_ACCESS_TYPE ,Type of memory barrier access 0x0: Reserved 0x1: Read 0x2: Write 0x3: Don't care (only if CHAIN_WP_EN=0; otherwise, reserved) Note: In the case of CHAIN_WP_EN=1, both memory barrier and data watchpoint must have the same transaction types; that is, both must be read or both must be write" "0,1,2,3" hexmask.long 0x0 5.--30. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 31. " MEM_BAR_TRIG ,Memory barrier trigger 0x0: Memory Barrier Watchpoint not triggered 0x1: Memory Barrier Watchpoint has triggered (Reset upon 0->1 transition of MEM_BAR_WP_EN)" "0,1" group.byte 0x1C++0x3 line.long 0x0 "DBG_HWWP0_CHAIN_CNTL,Debug Watchpoint Data/Memory Barrier Chain Control Register. This register should be written only when WP_EN=0." bitfld.long 0x0 0. " CHAIN_WP_EN ,Chained watchpoints (memory barrier and data watchpoint) enable 0x0: Disable the chained watchpoints 0x1: Enable the chained watchpoints Note: Both the memory barrier and data watchpoint should be enabled subsequent to this to avoid partial match/race conditions" "0,1" bitfld.long 0x0 1. " CHAIN_TYPE ,Chain type 0x0: Watchpoint match then memory barrier match 0x1: Memory barrier match then watchpoint match" "0,1" textline " " hexmask.long 0x0 2.--30. 1. " RESERVED ,Reserved" bitfld.long 0x0 31. " CHAIN_WP_TRIG ,Chained watchpoints (memory barrier and data watchpoint) trigger 0x0: Chained Watchpoints not triggered 0x1: Chained Watchpoints have triggered (Reset upon 0->1 transition of CHAIN_WP_EN)" "0,1" group.byte 0x20++0x3 line.long 0x0 "DBG_HWWP0_LW_ADDR0_LOG,Debug Watchpoint Addr0 Log Register (lower order bits 31:0). This register should be read only when TRIG=1 or WP_EN=0. This register is reset upon 0->1 transition of WP_EN." hexmask.long 0x0 0.--31. 1. " WP_ADDR_LOWER_ORDER_BITS ,Watchpoint address lower order bits (bits 31:0) (The byte-addressable lower order AXI-4 physical watchpoint address bits which results in a match)" group.byte 0x24++0x3 line.long 0x0 "DBG_HWWP0_HG_ADDR0_LOG,Debug Watchpoint Addr0 Log Register (higher order bits 39:32). This register should be read only when TRIG=1 or WP_EN=0. This register is reset upon 0->1 transition of WP_EN." hexmask.long.byte 0x0 0.--7. 1. " WP_ADDR_HIGHER_ORDER_BITS ,Watchpoint address higher order bits (bits 39:32) (The byte-addressable higher order AXI-4 physical watchpoint address bits which results in a match)" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "DBG_HWWP0_DATA0_LOG,Debug Watchpoint Data Log Register (bits 31:0). This register should be read only when TRIG=1 or WP_EN=0. This register is reset upon 0->1 transition of WP_EN." hexmask.long 0x0 0.--31. 1. " DATA0_CAPTURE ,Data capture (bits 31:0) (32-bit data associated with the access which results in a watchpoint match)" group.byte 0x2C++0x3 line.long 0x0 "DBG_HWWP0_DATA1_LOG,Debug Watchpoint Data Log Register (bits 63:32). This register should be read only when TRIG=1 or WP_EN=0. This register is reset upon 0->1 transition of WP_EN." hexmask.long 0x0 0.--31. 1. " DATA1_CAPTURE ,Data capture (bits 63:32) (32-bit data associated with the access which results in a watchpoint match)" group.byte 0x30++0x3 line.long 0x0 "DBG_HWWP0_DATA2_LOG,Debug Watchpoint Data Log Register (bits 95:64). This register should be read only when TRIG=1 or WP_EN=0. This register is reset upon 0->1 transition of WP_EN." hexmask.long 0x0 0.--31. 1. " DATA2_CAPTURE ,Data capture (bits 95:64) (32-bit data associated with the access which results in a watchpoint match)" group.byte 0x34++0x3 line.long 0x0 "DBG_HWWP0_DATA3_LOG,Debug Watchpoint Data Log Register (bits 127:96). This register should be read only when TRIG=1 or WP_EN=0. This register is reset upon 0->1 transition of WP_EN." hexmask.long 0x0 0.--31. 1. " DATA3_CAPTURE ,Data capture (bits 127:96) (32-bit data associated with the access which results in a watchpoint match)" group.byte 0x38++0x3 line.long 0x0 "DBG_HWWP0_TRANS_ATTR0_LOG,Debug Watchpoint Transaction Attributes 0 Log Register. This register should be read only when TRIG=1 or WP_EN=0. This register is reset upon 0->1 transition of WP_EN." bitfld.long 0x0 0.--2. " BURST_TYPE ,Burst type 0x0: Incrementing 0x1: Wrapping 0x3: Fixed (streaming) All other values: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. " RESERVED ,Reserved" "0,1" textline " " bitfld.long 0x0 4.--9. " BURST_LENGTH ,Burst length (The length of the burst which results in a watchpoint match) 0x1: Burst length = 1 (min value) 0x2: Burst length = 2 ..... 0x3F: Burst length = 63 (max value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 10.--12. " TRANS_TYPE ,Transaction type (The type of transaction which results in a watchpoint match and is protocol independent. Not all protocols support all transaction types) 0x0: Reserved 0x1: Write posted 0x2: Read 0x3: Read exclusive 0x4: Read linked 0x5: Write non-posted 0x6: Write conditional 0x7: Broadcast" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 13.--15. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 16.--18. " TARGET_INFO ,Target info 0x0: AXI2OCP 0x1: EMIF All other values: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 19. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 20.--22. " INIT_INFO ,Initiator info 0x0: CPU_0 0x1: CPU_1 0x2: CPU_2. Not supported on this device 0x3: CPU_3. Not supported on this device 0x4: Unknown source (ACP, FEQ, etc) 0x5: CMU. Not supported on this device 0x6, 0x7: Reserved" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 23. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 24.--25. " RESP_INFO ,Response info 0x0: Reserved 0x1: Okay 0x2: Request failed 0x3: Request error" "0,1,2,3" textline " " bitfld.long 0x0 26.--31. " RESERVED ,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.byte 0x3C++0x3 line.long 0x0 "DBG_HWWP0_TRANS_ATTR1_LOG,Debug Watchpoint Transaction Attributes 1 Log Register. This register should be read only when TRIG=1 or WP_EN=0. This register is reset upon 0->1 transition of WP_EN." bitfld.long 0x0 0. " SECURE ,Secure/Non-secure access 0x0: Non-secure 0x1: Secure. Not supported on GP device" "0,1" bitfld.long 0x0 1. " SUPERVISOR ,Supervisor/User access 0x0: User 0x1: Supervisor" "0,1" textline " " bitfld.long 0x0 2. " DATA ,Data access/Instruction fetch 0x0: Other, data, PLE, eviction 0x1: Instruction" "0,1" hexmask.long 0x0 3.--31. 1. " RESERVED ,Reserved" group.byte 0x40++0x3 line.long 0x0 "DBG_HWWP0_DATA_TRANS_ATTR0_LOG,Debug Watchpoint Data Transaction Attributes 0 Log Register. This register should be read only when TRIG=1 or WP_EN=0. This register is reset upon 0->1 transition of WP_EN." hexmask.long.word 0x0 0.--15. 1. " BYTE_EN ,Byte enable (Byte enables for the 128-bit of data captured for the transaction match)" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "PRUSS1_CFG" base ad:0x4B226000 width 14. group.byte 0x0++0x3 line.long 0x0 "PRUSS_REVID,The Revision Register contains the ID and revision information." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "PRUSS_SYSCFG,The System Configuration Register defines the power IDLE and STANDBY modes." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0 = Force-idle mode 0x1 = No-idle mode 0x2 = Smart-idle mode 0x3 = Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " STANDBY_MODE ,0x0 = Force standby mode: Initiator unconditionally in standby (standby = 1) 0x1 = No standby mode: Initiator unconditionally out of standby (standby = 0) 0x2 = Smart standby mode: Standby requested by initiator depending on internal conditions 0x3 = Reserved" "0,1,2,3" textline " " bitfld.long 0x0 4. " STANDBY_INIT ,0x1 = Initiate standby sequence. 0x0 = Enable OCP master ports." "0,1" bitfld.long 0x0 5. " SUB_MWAIT ,Status bit for wait state. 0x0 = Ready for Transaction 0x1 = Wait until 0" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRUSS_GPCFG0,The General Purpose Configuration 0 Register defines the GPIO configuration for PRU0." bitfld.long 0x0 0.--1. " PRU0_GPI_MODE ,0x0 = Direct input mode 0x1 = 16-bit parallel capture mode 0x2 = 28-bit shift mode 0x3 = MII_RT mode" "0,1,2,3" bitfld.long 0x0 2. " PRU0_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0x0 = Use the positive edge of pru0_r31_status[16] 0x1 = Use the negative edge of pru0_r31_status[16]" "0,1" textline " " bitfld.long 0x0 3.--7. " PRU0_GPI_DIV0 ,Divisor value (divide by PRU0_GPI_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--12. " PRU0_GPI_DIV1 ,Divisor value (divide by PRU0_GPI_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13. " PRU0_GPI_SB ,Start Bit event for 28-bit shift mode. PRU0_GPI_SB (pru0_r31_status[29]) is set when first capture of a 1 on pru0_r31_status[0]. Read 1: Start Bit event occurred. Read 0: Start Bit event has not occurred. Write 1: Will clear PRU0_GPI_SB and clear the whole shift register. Write 0: No Effect." "0,1" bitfld.long 0x0 14. " PRU0_GPO_MODE ,0x0 = Direct output mode 0x1 = Serial output mode" "0,1" textline " " bitfld.long 0x0 15.--19. " PRU0_GPO_DIV0 ,Divisor value (divide by PRU0_GPO_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--24. " PRU0_GPO_DIV1 ,Divisor value (divide by PRU0_GPO_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25. " PRU0_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0x0 = gpo_sh0 is selected 0x1 = gpo_sh1 is selected" "0,1" bitfld.long 0x0 26.--29. " PR1_PRU0_GP_MUX_SEL ,Reserved. Keep at reset value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0xC++0x3 line.long 0x0 "PRUSS_GPCFG1,The General Purpose Configuration 1 Register defines the GPI O configuration for PRU1." bitfld.long 0x0 0.--1. " PRU1_GPI_MODE ,0x0 = Direct input mode 0x1 = 16-bit parallel capture mode 0x2 = 28-bit shift mode 0x3 = MII_RT mode" "0,1,2,3" bitfld.long 0x0 2. " PRU1_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0x0 = Use the positive edge of pru1_r31_status[16] 0x1 = Use the negative edge of pru1_r31_status[16]" "0,1" textline " " bitfld.long 0x0 3.--7. " PRU1_GPI_DIV0 ,Divisor value (divide by PRU1_GPI_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--12. " PRU1_GPI_DIV1 ,Divisor value (divide by PRU1_GPI_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13. " PRU1_GPI_SB ,28-bit shift mode Start Bit event. PRU1_GPI_SB (pru1_r31_status[29]) is set when first capture of a 1 on pru1_r31_status[0]. Read 1: Start Bit event occurred. Read 0: Start Bit event has not occurred. Write 1: Will clear PRU1_GPI_SB and clear the whole shift register. Write 0: No Effect." "0,1" bitfld.long 0x0 14. " PRU1_GPO_MODE ,0x0 = Direct output mode 0x1 = Serial output mode" "0,1" textline " " bitfld.long 0x0 15.--19. " PRU1_GPO_DIV0 ,Divisor value (divide by PRU1_GPO_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--24. " PRU1_GPO_DIV1 ,Divisor value (divide by PRU1_GPO_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25. " PRU1_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0x0 = gpo_sh0 is selected 0x1 = gpo_sh1 is selected" "0,1" bitfld.long 0x0 26.--29. " PR1_PRU1_GP_MUX_SEL ,Reserved. Keep at reset value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x10++0x3 line.long 0x0 "PRUSS_CGR,The Clock Gating Register controls the state of Clock Management of the different modules. Software should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x1." bitfld.long 0x0 0. " PRU0_CLK_STOP_REQ ,PRU0 request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 1. " PRU0_CLK_STOP_ACK ,Acknowledgement that PRU0 clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 2. " PRU0_CLK_EN ,PRU0 clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 3. " PRU1_CLK_STOP_REQ ,PRU1 request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 4. " PRU1_CLK_STOP_ACK ,Acknowledgement that PRU1 clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 5. " PRU1_CLK_EN ,PRU1 clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " bitfld.long 0x0 6. " PRUSS_INTC_CLK_STOP_REQ ,PRUSS_INTC request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 7. " PRUSS_INTC_CLK_STOP_ACK ,Acknowledgement that PRUSS_INTC clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 8. " PRUSS_INTC_CLK_EN ,PRUSS_INTC clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 9. " UART_CLK_STOP_REQ ,UART request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 10. " UART_CLK_STOP_ACK ,Acknowledgement that UART clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 11. " UART_CLK_EN ,UART clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " bitfld.long 0x0 12. " ECAP_CLK_STOP_REQ ,ECAP request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 13. " ECAP_CLK_STOP_ACK ,Acknowledgement that ECAP clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 14. " ECAP_CLK_EN ,ECAP clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 15. " IEP_CLK_STOP_REQ ,IEP request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 16. " IEP_CLK_STOP_ACK ,Acknowledgement that IEP clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 17. " IEP_CLK_EN ,IEP clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_ISRP,The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRUSS memory parity events. The raw status is set even if the event is not enabled." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_RAW ,PRU0 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_IRAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_RAW ,PRU0 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_RAW ,PRU1 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_RAW ,PRU1 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE_RAW ,RAM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRUSS_ISP,The IRQ Status Parity Register is a snapshot of the IRQ status for the PRUSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE ,PRU0 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE ,PRU0 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No(enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE ,PRU1 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE ,PRU1 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE ,RAM Parity Error for Byte3, Byte2, Byte1, Byte0. Note RAM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRUSS_IESP,The IRQ Enable Set Parity Register enables the IRQ PRUSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_SET ,PRU0 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_SET ,PRU0 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_SET ,PRU1 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_SET ,PRU1 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE_SET ,RAM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRUSS_IECP,The IRQ Enable Clear Parity Register disables the IRQ PRUSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_CLR ,PRU0 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_CLR ,PRU0 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_CLR ,PRU1 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_CLR ,PRU1 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_PMAO,The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at 0x0000_0000." bitfld.long 0x0 0. " PMAO_PRU0 ,PRU0 OCP Master Port Address Offset Enable. 0x0 = Disable address offset. 0x1 = Enable address offset of -0x0008_0000." "0,1" bitfld.long 0x0 1. " PMAO_PRU1 ,PRU1 OCP Master Port Address Offset Enable. 0x0 = Disable address offset. 0x1 = Enable address offset of -0x0008_0000." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_MII_RT,The MII_RT Event Enable Register enables MII_RT mode events to the PRUSS.PRUSS_INTC." bitfld.long 0x0 0. " OCP_EN ,IEP clock source 0x0 = IEP_CLK is the source 0x1 = ICLK is the source. While this is selected no transactions should be active. It can only be cleared by a hardware reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PRUSS_IEPCLK,The IEP Clock Source Register defines the source of the IEP clock." bitfld.long 0x0 0. " OCP_EN ,IEP clock source 0x0 = IEP_CLK is the source 0x1 = ICLK is the source. While this is selected no transactions should be active. It can only be cleared by a hardware reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_SPP,The Scratch Pad Priority and Configuration Register defines the access priority assigned to the PRU cores and configures the scratch pad XFR shift functionality." bitfld.long 0x0 0. " PRU1_PAD_HP_EN ,Defines which PRU wins write cycle arbitration to a common scratch pad bank. The PRU which has higher priority will always perform the write cycle with no wait states. The lower PRU will get stalled wait states until higher PRU is not performing write cycles. If the lower priority PRU writes to the same byte has the higher priority PRU, then the lower priority PRU will over write the bytes. 0x0 = PRU0 has highest priority. 0x1 = PRU1 has highest priority." "0,1" bitfld.long 0x0 1. " XFR_SHIFT_EN ,Enables XIN XOUT shift functionality. When enabled, R0[4:0] (internal to PRU) defines the 32-bit offset for XIN and XOUT operations with the scratch pad. 0x0 = Disabled. 0x1 = Enabled." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PRUSS_PIN_MX,The Pin Mux Select Register defines the state of the PRUSS internal pinmuxing." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Reserved" bitfld.long 0x0 8. " PWM0_REMAP_EN ,If enabled, host intr6 of PRUSS2 controls epwm_sync_in of PWMSS1 instead of ehrpwm1_synci device pin" "0,1" textline " " bitfld.long 0x0 9. " PWM3_REMAP_EN ,UNUSED IN THIS DEVICE" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved. Always write 0." width 0x0B tree.end tree "PRUSS2_CFG" base ad:0x4B2A6000 width 14. group.byte 0x0++0x3 line.long 0x0 "PRUSS_REVID,The Revision Register contains the ID and revision information." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "PRUSS_SYSCFG,The System Configuration Register defines the power IDLE and STANDBY modes." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0 = Force-idle mode 0x1 = No-idle mode 0x2 = Smart-idle mode 0x3 = Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " STANDBY_MODE ,0x0 = Force standby mode: Initiator unconditionally in standby (standby = 1) 0x1 = No standby mode: Initiator unconditionally out of standby (standby = 0) 0x2 = Smart standby mode: Standby requested by initiator depending on internal conditions 0x3 = Reserved" "0,1,2,3" textline " " bitfld.long 0x0 4. " STANDBY_INIT ,0x1 = Initiate standby sequence. 0x0 = Enable OCP master ports." "0,1" bitfld.long 0x0 5. " SUB_MWAIT ,Status bit for wait state. 0x0 = Ready for Transaction 0x1 = Wait until 0" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRUSS_GPCFG0,The General Purpose Configuration 0 Register defines the GPIO configuration for PRU0." bitfld.long 0x0 0.--1. " PRU0_GPI_MODE ,0x0 = Direct input mode 0x1 = 16-bit parallel capture mode 0x2 = 28-bit shift mode 0x3 = MII_RT mode" "0,1,2,3" bitfld.long 0x0 2. " PRU0_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0x0 = Use the positive edge of pru0_r31_status[16] 0x1 = Use the negative edge of pru0_r31_status[16]" "0,1" textline " " bitfld.long 0x0 3.--7. " PRU0_GPI_DIV0 ,Divisor value (divide by PRU0_GPI_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--12. " PRU0_GPI_DIV1 ,Divisor value (divide by PRU0_GPI_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13. " PRU0_GPI_SB ,Start Bit event for 28-bit shift mode. PRU0_GPI_SB (pru0_r31_status[29]) is set when first capture of a 1 on pru0_r31_status[0]. Read 1: Start Bit event occurred. Read 0: Start Bit event has not occurred. Write 1: Will clear PRU0_GPI_SB and clear the whole shift register. Write 0: No Effect." "0,1" bitfld.long 0x0 14. " PRU0_GPO_MODE ,0x0 = Direct output mode 0x1 = Serial output mode" "0,1" textline " " bitfld.long 0x0 15.--19. " PRU0_GPO_DIV0 ,Divisor value (divide by PRU0_GPO_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--24. " PRU0_GPO_DIV1 ,Divisor value (divide by PRU0_GPO_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25. " PRU0_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0x0 = gpo_sh0 is selected 0x1 = gpo_sh1 is selected" "0,1" bitfld.long 0x0 26.--29. " PR1_PRU0_GP_MUX_SEL ,Reserved. Keep at reset value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0xC++0x3 line.long 0x0 "PRUSS_GPCFG1,The General Purpose Configuration 1 Register defines the GPI O configuration for PRU1." bitfld.long 0x0 0.--1. " PRU1_GPI_MODE ,0x0 = Direct input mode 0x1 = 16-bit parallel capture mode 0x2 = 28-bit shift mode 0x3 = MII_RT mode" "0,1,2,3" bitfld.long 0x0 2. " PRU1_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0x0 = Use the positive edge of pru1_r31_status[16] 0x1 = Use the negative edge of pru1_r31_status[16]" "0,1" textline " " bitfld.long 0x0 3.--7. " PRU1_GPI_DIV0 ,Divisor value (divide by PRU1_GPI_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--12. " PRU1_GPI_DIV1 ,Divisor value (divide by PRU1_GPI_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13. " PRU1_GPI_SB ,28-bit shift mode Start Bit event. PRU1_GPI_SB (pru1_r31_status[29]) is set when first capture of a 1 on pru1_r31_status[0]. Read 1: Start Bit event occurred. Read 0: Start Bit event has not occurred. Write 1: Will clear PRU1_GPI_SB and clear the whole shift register. Write 0: No Effect." "0,1" bitfld.long 0x0 14. " PRU1_GPO_MODE ,0x0 = Direct output mode 0x1 = Serial output mode" "0,1" textline " " bitfld.long 0x0 15.--19. " PRU1_GPO_DIV0 ,Divisor value (divide by PRU1_GPO_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--24. " PRU1_GPO_DIV1 ,Divisor value (divide by PRU1_GPO_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25. " PRU1_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0x0 = gpo_sh0 is selected 0x1 = gpo_sh1 is selected" "0,1" bitfld.long 0x0 26.--29. " PR1_PRU1_GP_MUX_SEL ,Reserved. Keep at reset value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x10++0x3 line.long 0x0 "PRUSS_CGR,The Clock Gating Register controls the state of Clock Management of the different modules. Software should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x1." bitfld.long 0x0 0. " PRU0_CLK_STOP_REQ ,PRU0 request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 1. " PRU0_CLK_STOP_ACK ,Acknowledgement that PRU0 clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 2. " PRU0_CLK_EN ,PRU0 clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 3. " PRU1_CLK_STOP_REQ ,PRU1 request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 4. " PRU1_CLK_STOP_ACK ,Acknowledgement that PRU1 clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 5. " PRU1_CLK_EN ,PRU1 clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " bitfld.long 0x0 6. " PRUSS_INTC_CLK_STOP_REQ ,PRUSS_INTC request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 7. " PRUSS_INTC_CLK_STOP_ACK ,Acknowledgement that PRUSS_INTC clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 8. " PRUSS_INTC_CLK_EN ,PRUSS_INTC clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 9. " UART_CLK_STOP_REQ ,UART request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 10. " UART_CLK_STOP_ACK ,Acknowledgement that UART clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 11. " UART_CLK_EN ,UART clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " bitfld.long 0x0 12. " ECAP_CLK_STOP_REQ ,ECAP request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 13. " ECAP_CLK_STOP_ACK ,Acknowledgement that ECAP clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 14. " ECAP_CLK_EN ,ECAP clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 15. " IEP_CLK_STOP_REQ ,IEP request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 16. " IEP_CLK_STOP_ACK ,Acknowledgement that IEP clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 17. " IEP_CLK_EN ,IEP clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_ISRP,The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRUSS memory parity events. The raw status is set even if the event is not enabled." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_RAW ,PRU0 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_IRAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_RAW ,PRU0 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_RAW ,PRU1 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_RAW ,PRU1 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE_RAW ,RAM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRUSS_ISP,The IRQ Status Parity Register is a snapshot of the IRQ status for the PRUSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE ,PRU0 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE ,PRU0 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No(enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE ,PRU1 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE ,PRU1 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE ,RAM Parity Error for Byte3, Byte2, Byte1, Byte0. Note RAM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRUSS_IESP,The IRQ Enable Set Parity Register enables the IRQ PRUSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_SET ,PRU0 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_SET ,PRU0 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_SET ,PRU1 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_SET ,PRU1 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE_SET ,RAM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRUSS_IECP,The IRQ Enable Clear Parity Register disables the IRQ PRUSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_CLR ,PRU0 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_CLR ,PRU0 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_CLR ,PRU1 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_CLR ,PRU1 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_PMAO,The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at 0x0000_0000." bitfld.long 0x0 0. " PMAO_PRU0 ,PRU0 OCP Master Port Address Offset Enable. 0x0 = Disable address offset. 0x1 = Enable address offset of -0x0008_0000." "0,1" bitfld.long 0x0 1. " PMAO_PRU1 ,PRU1 OCP Master Port Address Offset Enable. 0x0 = Disable address offset. 0x1 = Enable address offset of -0x0008_0000." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_MII_RT,The MII_RT Event Enable Register enables MII_RT mode events to the PRUSS.PRUSS_INTC." bitfld.long 0x0 0. " OCP_EN ,IEP clock source 0x0 = IEP_CLK is the source 0x1 = ICLK is the source. While this is selected no transactions should be active. It can only be cleared by a hardware reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PRUSS_IEPCLK,The IEP Clock Source Register defines the source of the IEP clock." bitfld.long 0x0 0. " OCP_EN ,IEP clock source 0x0 = IEP_CLK is the source 0x1 = ICLK is the source. While this is selected no transactions should be active. It can only be cleared by a hardware reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_SPP,The Scratch Pad Priority and Configuration Register defines the access priority assigned to the PRU cores and configures the scratch pad XFR shift functionality." bitfld.long 0x0 0. " PRU1_PAD_HP_EN ,Defines which PRU wins write cycle arbitration to a common scratch pad bank. The PRU which has higher priority will always perform the write cycle with no wait states. The lower PRU will get stalled wait states until higher PRU is not performing write cycles. If the lower priority PRU writes to the same byte has the higher priority PRU, then the lower priority PRU will over write the bytes. 0x0 = PRU0 has highest priority. 0x1 = PRU1 has highest priority." "0,1" bitfld.long 0x0 1. " XFR_SHIFT_EN ,Enables XIN XOUT shift functionality. When enabled, R0[4:0] (internal to PRU) defines the 32-bit offset for XIN and XOUT operations with the scratch pad. 0x0 = Disabled. 0x1 = Enabled." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PRUSS_PIN_MX,The Pin Mux Select Register defines the state of the PRUSS internal pinmuxing." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Reserved" bitfld.long 0x0 8. " PWM0_REMAP_EN ,If enabled, host intr6 of PRUSS2 controls epwm_sync_in of PWMSS1 instead of ehrpwm1_synci device pin" "0,1" textline " " bitfld.long 0x0 9. " PWM3_REMAP_EN ,UNUSED IN THIS DEVICE" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved. Always write 0." width 0x0B tree.end tree "PRUSS1_PRU0_CTRL" base ad:0x4B222000 width 15. group.byte 0x0++0x3 line.long 0x0 "PRU_CONTROL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. 0 = PRU is disabled. 1 = PRU is enabled. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The pru_state bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1" textline " " bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x0 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. 0 = PRU will free run when enabled. 1 = PRU will execute a single instruction and then the pru_enable bit will be cleared. Note that this bit does not actually enable the PRU, it only sets the policy for how much code will be run after the PRU is enabled. The pru_enable bit must be explicitly asserted. It is legal to initialize both the single_step and pru_enable bits simultaneously. (Two independent writes are not required to cause the stated functionality.)" "0,1" textline " " bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 14. " BIG_ENDIAN ," "0,1" textline " " bitfld.long 0x0 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. 0 = PRU is halted and host has access to the instruction RAM and debug registers regions. 1 = PRU is currently running and the host is locked out of the instruction RAM and debug registers regions. This bit is used by an external debug agent to know when the PRU has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the pru_enable has been cleared." "0,1" hexmask.long.word 0x0 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.byte 0x4++0x3 line.long 0x0 "PRU_STATUS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter. Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20)." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRU_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core." group.byte 0xC++0x3 line.long 0x0 "PRU_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the COUNTENABLE bit in the PRU control register when the count reaches 0xFFFFFFFF. (Count does does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register." group.byte 0x10++0x3 line.long 0x0 "PRU_STALL,STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count." hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.byte 0x20++0x3 line.long 0x0 "PRU_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRU_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRU_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory." hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.byte 0x2C++0x3 line.long 0x0 "PRU_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table." hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0x0B tree.end tree "PRUSS1_PRU1_CTRL" base ad:0x4B224000 width 15. group.byte 0x0++0x3 line.long 0x0 "PRU_CONTROL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. 0 = PRU is disabled. 1 = PRU is enabled. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The pru_state bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1" textline " " bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x0 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. 0 = PRU will free run when enabled. 1 = PRU will execute a single instruction and then the pru_enable bit will be cleared. Note that this bit does not actually enable the PRU, it only sets the policy for how much code will be run after the PRU is enabled. The pru_enable bit must be explicitly asserted. It is legal to initialize both the single_step and pru_enable bits simultaneously. (Two independent writes are not required to cause the stated functionality.)" "0,1" textline " " bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 14. " BIG_ENDIAN ," "0,1" textline " " bitfld.long 0x0 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. 0 = PRU is halted and host has access to the instruction RAM and debug registers regions. 1 = PRU is currently running and the host is locked out of the instruction RAM and debug registers regions. This bit is used by an external debug agent to know when the PRU has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the pru_enable has been cleared." "0,1" hexmask.long.word 0x0 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.byte 0x4++0x3 line.long 0x0 "PRU_STATUS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter. Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20)." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRU_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core." group.byte 0xC++0x3 line.long 0x0 "PRU_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the COUNTENABLE bit in the PRU control register when the count reaches 0xFFFFFFFF. (Count does does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register." group.byte 0x10++0x3 line.long 0x0 "PRU_STALL,STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count." hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.byte 0x20++0x3 line.long 0x0 "PRU_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRU_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRU_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory." hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.byte 0x2C++0x3 line.long 0x0 "PRU_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table." hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0x0B tree.end tree "PRUSS2_PRU0_CTRL" base ad:0x4B2A2000 width 15. group.byte 0x0++0x3 line.long 0x0 "PRU_CONTROL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. 0 = PRU is disabled. 1 = PRU is enabled. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The pru_state bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1" textline " " bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x0 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. 0 = PRU will free run when enabled. 1 = PRU will execute a single instruction and then the pru_enable bit will be cleared. Note that this bit does not actually enable the PRU, it only sets the policy for how much code will be run after the PRU is enabled. The pru_enable bit must be explicitly asserted. It is legal to initialize both the single_step and pru_enable bits simultaneously. (Two independent writes are not required to cause the stated functionality.)" "0,1" textline " " bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 14. " BIG_ENDIAN ," "0,1" textline " " bitfld.long 0x0 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. 0 = PRU is halted and host has access to the instruction RAM and debug registers regions. 1 = PRU is currently running and the host is locked out of the instruction RAM and debug registers regions. This bit is used by an external debug agent to know when the PRU has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the pru_enable has been cleared." "0,1" hexmask.long.word 0x0 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.byte 0x4++0x3 line.long 0x0 "PRU_STATUS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter. Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20)." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRU_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core." group.byte 0xC++0x3 line.long 0x0 "PRU_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the COUNTENABLE bit in the PRU control register when the count reaches 0xFFFFFFFF. (Count does does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register." group.byte 0x10++0x3 line.long 0x0 "PRU_STALL,STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count." hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.byte 0x20++0x3 line.long 0x0 "PRU_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRU_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRU_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory." hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.byte 0x2C++0x3 line.long 0x0 "PRU_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table." hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0x0B tree.end tree "PRUSS2_PRU1_CTRL" base ad:0x4B2A4000 width 15. group.byte 0x0++0x3 line.long 0x0 "PRU_CONTROL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. 0 = PRU is disabled. 1 = PRU is enabled. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The pru_state bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1" textline " " bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x0 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. 0 = PRU will free run when enabled. 1 = PRU will execute a single instruction and then the pru_enable bit will be cleared. Note that this bit does not actually enable the PRU, it only sets the policy for how much code will be run after the PRU is enabled. The pru_enable bit must be explicitly asserted. It is legal to initialize both the single_step and pru_enable bits simultaneously. (Two independent writes are not required to cause the stated functionality.)" "0,1" textline " " bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 14. " BIG_ENDIAN ," "0,1" textline " " bitfld.long 0x0 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. 0 = PRU is halted and host has access to the instruction RAM and debug registers regions. 1 = PRU is currently running and the host is locked out of the instruction RAM and debug registers regions. This bit is used by an external debug agent to know when the PRU has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the pru_enable has been cleared." "0,1" hexmask.long.word 0x0 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.byte 0x4++0x3 line.long 0x0 "PRU_STATUS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter. Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20)." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRU_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core." group.byte 0xC++0x3 line.long 0x0 "PRU_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the COUNTENABLE bit in the PRU control register when the count reaches 0xFFFFFFFF. (Count does does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register." group.byte 0x10++0x3 line.long 0x0 "PRU_STALL,STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count." hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.byte 0x20++0x3 line.long 0x0 "PRU_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRU_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRU_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory." hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.byte 0x2C++0x3 line.long 0x0 "PRU_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table." hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0x0B tree.end tree "PRUSS1_INTC" base ad:0x4B220000 width 21. group.byte 0x0++0x3 line.long 0x0 "PRUSS_INTC_REVID,Revision ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "PRUSS_INTC_CR,The Control Register holds global control parameters and can forces a soft reset on the module." bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " WAKEUP_MODE ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " NEST_MODE ,The nesting mode. 0 = no nesting 1 = automatic individual nesting (per host interrupt) 2 = automatic global nesting (over all host interrupts) 3 = manual nesting" "0,1,2,3" bitfld.long 0x0 4. " PRIORITY_HOLD_MODE ,Reserved" "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PRUSS_INTC_GER,The Global Host Interrupt Enable Register enables all the host interrupts. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable." bitfld.long 0x0 0. " ENABLE_HINT_ANY ,The current global enable value when read. Writes set the global enable." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRUSS_INTC_GNLR,The Global Nesting Level Register allows the checking and setting of the global nesting level across all host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of lower priority) that are nested out because of a current interrupt. This register is only available when nesting is configured." hexmask.long.word 0x0 0.--8. 1. " GLB_NEST_LEVEL ,The current global nesting level (highest channel that is nested). Writes set the nesting level. In auto nesting mode this value is updated internally unless the auto_override bit is set." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Always read as 0. Writes of 1 override the automatic nesting and set the nesting_level to the written data." "0,1" group.byte 0x20++0x3 line.long 0x0 "PRUSS_INTC_SISR,The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to set is the index value written. This sets the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STATUS_SET_INDEX ,Writes set the status of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRUSS_INTC_SICR,The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STATUS_CLR_INDEX ,Writes clear the status of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_INTC_EISR,The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is the index value written. This sets the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " ENABLE_SET_INDEX ,Writes set the enable of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_INTC_EICR,The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable is the index value written. This clears the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " ENABLE_CLR_INDEX ,Writes clear the enable of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_INTC_HIEISR,The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if already enabled." hexmask.long.word 0x0 0.--9. 1. " HINT_ENABLE_SET_INDEX ,Writes set the enable of the host interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PRUSS_INTC_HIDISR,The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host interrupt to disable is the index value written. This disables the host interrupt output." hexmask.long.word 0x0 0.--9. 1. " HINT_ENABLE_CLR_INDEX ,Writes clear the enable of the host interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PRUSS_INTC_GPIR,The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts." hexmask.long.word 0x0 0.--9. 1. " GLB_PRI_INTR ,The currently highest priority interrupt index pending across all the host interrupts." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " GLB_NONE ,No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending." "0,1" group.byte 0x200++0x3 line.long 0x0 "PRUSS_INTC_SRSR0,The System Interrupt Status Raw Set Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " RAW_STATUS_31_0 ,System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.byte 0x204++0x3 line.long 0x0 "PRUSS_INTC_SRSR1,The System Interrupt Status Raw Set Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " RAW_STATUS_63_32 ,System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.byte 0x280++0x3 line.long 0x0 "PRUSS_INTC_SECR0,The System Interrupt Status Enabled Clear Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENA_STATUS_31_0 ,System interrupt enabled status and clearing of the system interrupts 0 to 31. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect." group.byte 0x284++0x3 line.long 0x0 "PRUSS_INTC_SECR1,The System Interrupt Status Enabled Clear Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENA_STATUS_63_32 ,System interrupt enabled status and clearing of the system interrupts 32 to 63. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect." group.byte 0x300++0x3 line.long 0x0 "PRUSS_INTC_ESR0,The System Interrupt Enable Set Register0 enables system interrupts 0 to 31 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_SET_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.byte 0x304++0x3 line.long 0x0 "PRUSS_INTC_ERS1,The System Interrupt Enable Set Register1 enables system interrupts 32 to 63 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_SET_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.byte 0x380++0x3 line.long 0x0 "PRUSS_INTC_ECR0,The System Interrupt Enable Clear Register0 disables system interrupts 0 to 31 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_CLR_31_0 ,System interrupt enables system interrupts 0 to 31. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.byte 0x384++0x3 line.long 0x0 "PRUSS_INTC_ECR1,The System Interrupt Enable Clear Register1 disables system interrupts 32 to 63 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_CLR_63_32 ,System interrupt enables system interrupts 32 to 63. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.byte 0x400++0x3 line.long 0x0 "PRUSS_INTC_CMRi_0,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x404++0x3 line.long 0x0 "PRUSS_INTC_CMRi_1,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x408++0x3 line.long 0x0 "PRUSS_INTC_CMRi_2,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_3,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x410++0x3 line.long 0x0 "PRUSS_INTC_CMRi_4,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x414++0x3 line.long 0x0 "PRUSS_INTC_CMRi_5,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x418++0x3 line.long 0x0 "PRUSS_INTC_CMRi_6,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x41C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_7,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x420++0x3 line.long 0x0 "PRUSS_INTC_CMRi_8,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x424++0x3 line.long 0x0 "PRUSS_INTC_CMRi_9,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x428++0x3 line.long 0x0 "PRUSS_INTC_CMRi_10,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x42C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_11,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x430++0x3 line.long 0x0 "PRUSS_INTC_CMRi_12,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x434++0x3 line.long 0x0 "PRUSS_INTC_CMRi_13,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x438++0x3 line.long 0x0 "PRUSS_INTC_CMRi_14,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x43C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_15,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x800++0x3 line.long 0x0 "PRUSS_INTC_HMR0,The Host Interrupt Map Register0 define the host interrupt for channels 0 to 3. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_0 ,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_1 ,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " HINT_MAP_2 ,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HINT_MAP_3 ,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x804++0x3 line.long 0x0 "PRUSS_INTC_HMR1,The Host Interrupt Map Register1 define the host interrupt for channels 4 to 7. There is one register per 4 channels. Chan_statusnels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_4 ,HOST INTERRUPT MAP FOR CHANNEL 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_5 ,HOST INTERRUPT MAP FOR CHANNEL 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " HINT_MAP_6 ,HOST INTERRUPT MAP FOR CHANNEL 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HINT_MAP_7 ,HOST INTERRUPT MAP FOR CHANNEL 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x808++0x3 line.long 0x0 "PRUSS_INTC_HMR2,The Host Interrupt Map Register2 define the host interrupt for channels 8 to 9. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_8 ,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_9 ,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x900++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_0,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x904++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_1,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x908++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_2,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x90C++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_3,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x910++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_4,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x914++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_5,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x918++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_6,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x91C++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_7,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x920++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_8,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x924++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_9,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0xD00++0x3 line.long 0x0 "PRUSS_INTC_SIPR0,The System Interrupt Polarity Register0 define the polarity of the system interrupts 0 to 31. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x0 0.--31. 1. " POLARITY_31_0 ,Interrupt polarity of the system interrupts 0 to 31. 0 = active low. 1 = active high." group.byte 0xD04++0x3 line.long 0x0 "PRUSS_INTC_SIPR1,The System Interrupt Polarity Register1 define the polarity of the system interrupts 32 to 63. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x0 0.--31. 1. " POLARITY_63_32 ,Interrupt polarity of the system interrupts 32 to 63. 0 = active low. 1 = active high." group.byte 0xD80++0x3 line.long 0x0 "PRUSS_INTC_SITR0,The System Interrupt Type Register0 define the type of the system interrupts 0 to 31. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_31_0 ,Interrupt type of the system interrupts 0 to 31. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.byte 0xD84++0x3 line.long 0x0 "PRUSS_INTC_SITR1,The System Interrupt Type Register1 define the type of the system interrupts 32 to 63. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_63_32 ,Interrupt type of the system interrupts 32 to 63. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.byte 0x1100++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_0,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1104++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_1,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1108++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_2,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x110C++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_3,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1110++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_4,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1114++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_5,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1118++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_6,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x111C++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_7,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1120++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_8,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1124++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_9,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1500++0x3 line.long 0x0 "PRUSS_INTC_HIER,The Host Interrupt Enable Registers enable or disable individual host interrupts. These work separately from the global enables. There is one bit per host interrupt. These bits are updated when writing to the Host Interrupt Enable Index Set and Host Interrupt Enable Index Clear registers." hexmask.long.word 0x0 0.--9. 1. " ENABLE_HINT ,The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS2_INTC" base ad:0x4B2A0000 width 21. group.byte 0x0++0x3 line.long 0x0 "PRUSS_INTC_REVID,Revision ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "PRUSS_INTC_CR,The Control Register holds global control parameters and can forces a soft reset on the module." bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " WAKEUP_MODE ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " NEST_MODE ,The nesting mode. 0 = no nesting 1 = automatic individual nesting (per host interrupt) 2 = automatic global nesting (over all host interrupts) 3 = manual nesting" "0,1,2,3" bitfld.long 0x0 4. " PRIORITY_HOLD_MODE ,Reserved" "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PRUSS_INTC_GER,The Global Host Interrupt Enable Register enables all the host interrupts. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable." bitfld.long 0x0 0. " ENABLE_HINT_ANY ,The current global enable value when read. Writes set the global enable." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRUSS_INTC_GNLR,The Global Nesting Level Register allows the checking and setting of the global nesting level across all host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of lower priority) that are nested out because of a current interrupt. This register is only available when nesting is configured." hexmask.long.word 0x0 0.--8. 1. " GLB_NEST_LEVEL ,The current global nesting level (highest channel that is nested). Writes set the nesting level. In auto nesting mode this value is updated internally unless the auto_override bit is set." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Always read as 0. Writes of 1 override the automatic nesting and set the nesting_level to the written data." "0,1" group.byte 0x20++0x3 line.long 0x0 "PRUSS_INTC_SISR,The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to set is the index value written. This sets the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STATUS_SET_INDEX ,Writes set the status of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRUSS_INTC_SICR,The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STATUS_CLR_INDEX ,Writes clear the status of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_INTC_EISR,The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is the index value written. This sets the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " ENABLE_SET_INDEX ,Writes set the enable of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_INTC_EICR,The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable is the index value written. This clears the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " ENABLE_CLR_INDEX ,Writes clear the enable of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_INTC_HIEISR,The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if already enabled." hexmask.long.word 0x0 0.--9. 1. " HINT_ENABLE_SET_INDEX ,Writes set the enable of the host interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PRUSS_INTC_HIDISR,The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host interrupt to disable is the index value written. This disables the host interrupt output." hexmask.long.word 0x0 0.--9. 1. " HINT_ENABLE_CLR_INDEX ,Writes clear the enable of the host interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PRUSS_INTC_GPIR,The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts." hexmask.long.word 0x0 0.--9. 1. " GLB_PRI_INTR ,The currently highest priority interrupt index pending across all the host interrupts." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " GLB_NONE ,No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending." "0,1" group.byte 0x200++0x3 line.long 0x0 "PRUSS_INTC_SRSR0,The System Interrupt Status Raw Set Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " RAW_STATUS_31_0 ,System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.byte 0x204++0x3 line.long 0x0 "PRUSS_INTC_SRSR1,The System Interrupt Status Raw Set Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " RAW_STATUS_63_32 ,System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.byte 0x280++0x3 line.long 0x0 "PRUSS_INTC_SECR0,The System Interrupt Status Enabled Clear Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENA_STATUS_31_0 ,System interrupt enabled status and clearing of the system interrupts 0 to 31. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect." group.byte 0x284++0x3 line.long 0x0 "PRUSS_INTC_SECR1,The System Interrupt Status Enabled Clear Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENA_STATUS_63_32 ,System interrupt enabled status and clearing of the system interrupts 32 to 63. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect." group.byte 0x300++0x3 line.long 0x0 "PRUSS_INTC_ESR0,The System Interrupt Enable Set Register0 enables system interrupts 0 to 31 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_SET_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.byte 0x304++0x3 line.long 0x0 "PRUSS_INTC_ERS1,The System Interrupt Enable Set Register1 enables system interrupts 32 to 63 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_SET_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.byte 0x380++0x3 line.long 0x0 "PRUSS_INTC_ECR0,The System Interrupt Enable Clear Register0 disables system interrupts 0 to 31 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_CLR_31_0 ,System interrupt enables system interrupts 0 to 31. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.byte 0x384++0x3 line.long 0x0 "PRUSS_INTC_ECR1,The System Interrupt Enable Clear Register1 disables system interrupts 32 to 63 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_CLR_63_32 ,System interrupt enables system interrupts 32 to 63. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.byte 0x400++0x3 line.long 0x0 "PRUSS_INTC_CMRi_0,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x404++0x3 line.long 0x0 "PRUSS_INTC_CMRi_1,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x408++0x3 line.long 0x0 "PRUSS_INTC_CMRi_2,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_3,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x410++0x3 line.long 0x0 "PRUSS_INTC_CMRi_4,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x414++0x3 line.long 0x0 "PRUSS_INTC_CMRi_5,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x418++0x3 line.long 0x0 "PRUSS_INTC_CMRi_6,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x41C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_7,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x420++0x3 line.long 0x0 "PRUSS_INTC_CMRi_8,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x424++0x3 line.long 0x0 "PRUSS_INTC_CMRi_9,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x428++0x3 line.long 0x0 "PRUSS_INTC_CMRi_10,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x42C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_11,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x430++0x3 line.long 0x0 "PRUSS_INTC_CMRi_12,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x434++0x3 line.long 0x0 "PRUSS_INTC_CMRi_13,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x438++0x3 line.long 0x0 "PRUSS_INTC_CMRi_14,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x43C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_15,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x800++0x3 line.long 0x0 "PRUSS_INTC_HMR0,The Host Interrupt Map Register0 define the host interrupt for channels 0 to 3. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_0 ,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_1 ,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " HINT_MAP_2 ,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HINT_MAP_3 ,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x804++0x3 line.long 0x0 "PRUSS_INTC_HMR1,The Host Interrupt Map Register1 define the host interrupt for channels 4 to 7. There is one register per 4 channels. Chan_statusnels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_4 ,HOST INTERRUPT MAP FOR CHANNEL 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_5 ,HOST INTERRUPT MAP FOR CHANNEL 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " HINT_MAP_6 ,HOST INTERRUPT MAP FOR CHANNEL 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HINT_MAP_7 ,HOST INTERRUPT MAP FOR CHANNEL 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x808++0x3 line.long 0x0 "PRUSS_INTC_HMR2,The Host Interrupt Map Register2 define the host interrupt for channels 8 to 9. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_8 ,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_9 ,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x900++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_0,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x904++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_1,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x908++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_2,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x90C++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_3,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x910++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_4,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x914++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_5,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x918++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_6,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x91C++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_7,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x920++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_8,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x924++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_9,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0xD00++0x3 line.long 0x0 "PRUSS_INTC_SIPR0,The System Interrupt Polarity Register0 define the polarity of the system interrupts 0 to 31. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x0 0.--31. 1. " POLARITY_31_0 ,Interrupt polarity of the system interrupts 0 to 31. 0 = active low. 1 = active high." group.byte 0xD04++0x3 line.long 0x0 "PRUSS_INTC_SIPR1,The System Interrupt Polarity Register1 define the polarity of the system interrupts 32 to 63. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x0 0.--31. 1. " POLARITY_63_32 ,Interrupt polarity of the system interrupts 32 to 63. 0 = active low. 1 = active high." group.byte 0xD80++0x3 line.long 0x0 "PRUSS_INTC_SITR0,The System Interrupt Type Register0 define the type of the system interrupts 0 to 31. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_31_0 ,Interrupt type of the system interrupts 0 to 31. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.byte 0xD84++0x3 line.long 0x0 "PRUSS_INTC_SITR1,The System Interrupt Type Register1 define the type of the system interrupts 32 to 63. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_63_32 ,Interrupt type of the system interrupts 32 to 63. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.byte 0x1100++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_0,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1104++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_1,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1108++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_2,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x110C++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_3,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1110++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_4,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1114++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_5,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1118++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_6,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x111C++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_7,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1120++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_8,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1124++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_9,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1500++0x3 line.long 0x0 "PRUSS_INTC_HIER,The Host Interrupt Enable Registers enable or disable individual host interrupts. These work separately from the global enables. There is one bit per host interrupt. These bits are updated when writing to the Host Interrupt Enable Index Set and Host Interrupt Enable Index Clear registers." hexmask.long.word 0x0 0.--9. 1. " ENABLE_HINT ,The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS1_UART" base ad:0x4B228000 width 68. group.byte 0x0++0x3 line.long 0x0 "PRUSS_UART_RBR_THR_REGISTERS,In the non-FIFO mode, when a character is placed in Receiver buffer register and the receiver data-ready interrupt is enabled (DR = 1 in Interrupt identification register), an interrupt is generated. This interrupt is cleared when the character is read from Receiver buffer register. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register, and it is cleared when the FIFO contents drop below the trigger level. In the non-FIFO mode, if Transmitter holding register is empty and the THR empty (THRE) interrupt is enabled (ETBEI = 1 in Interrupt enable register), an interrupt is generated. This interrupt is cleared when a character is loaded into Transmitter holding register or the Interrupt identification register is read. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or Interrupt identification register is read." hexmask.long.byte 0x0 0.--7. 1. " DATA ,Read: Read Receive Buffer RegisterWrite: Write Transmitter Holding Register ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "PRUSS_UART_INTERRUPT_ENABLE_REGISTER,The Interrupt enable register is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in Interrupt enable register is forwarded to the CPU." bitfld.long 0x0 0. " ERBI ,Receiver data available interrupt and character timeout indication interrupt enable." "0,1" bitfld.long 0x0 1. " ETBEI ,Transmitter holding register empty interrupt enable." "0,1" textline " " bitfld.long 0x0 2. " ELSI ,Receiver line status interrupt enable." "0,1" bitfld.long 0x0 3. " EDSSI ,Enable Modem Status Interrupt" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "PRUSS_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER,The Interrupt identification register is a read-only register at the same address as the FIFO control register, which is a write-only register. When an interrupt is generated and enabled in the Interrupt enable register, Interrupt identification register indicates that an interrupt is pending in the IPEND bit and encodes the type of interrupt in the INTID bits. Reading Interrupt identification register clears any THR empty (THRE) interrupts that are pending. The FIFOEN bit in Interrupt identification register can be checked to determine whether the UART is in the FIFO mode or the non-FIFO mode. Use FIFO control register to enable and clear the FIFOs and to select the receiver FIFO trigger level. The FIFOEN bit in FIFO control register must be set to 1 before other FIFO control register bits are written to or the FIFO control register bits are not programmed." bitfld.long 0x0 0. " IPEND_FIFOEN ,Read: Interrupt pending. When any UART interrupt is generated and is enabled in IER, IPEND is forced to 0. IPEND remains 0 until all pending interrupts are cleared or until a hardware reset occurs. If no interrupts are enabled, IPEND is never forced to 0.Write: Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to or the FCR bits are not programmed. Clearing this bit clears the FIFO counters. ." "0,1" bitfld.long 0x0 1.--3. " INTID ,Read: Interrupt type. See .0x4-0x5: Reserved . Write: . Bit 3: DMAMODE1: DMA MODE1 enable if FIFOs are enabled. Always write 1 to DMAMODE1. After a hardware reset, change DMAMODE1 from 0 to 1. DMAMODE1 = 1 is a requirement for proper communication between the UART and the EDMA controller. . Bit 2: TXCLR: Transmitter FIFO clear. Write a 1 to TXCLR to clear the bit. . Bit 1: RXCLR: Receiver FIFO clear. Write a 1 to RXCLR to clear the bit. ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 6.--7. " FIFOEN_RXFIFTL ,Read: FIFOs enabled.0x1-0x2: Reserved . Write: Receiver FIFO trigger level. RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the FIFO drops below the trigger level, the interrupt is cleared. ." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "PRUSS_UART_LINE_CONTROL_REGISTER,The system programmer controls the format of the asynchronous data communication exchange by using Line control register. In addition, the programmer can retrieve, inspect, and modify the content of line control register; this eliminates the need for separate storage of the line characteristics in system memory." bitfld.long 0x0 0.--1. " WLS ,Word length select. Number of bits in each transmitted or received serial character. When STB = 1, the WLS bit determines the number of STOP bits." "0,1,2,3" bitfld.long 0x0 2. " STB ,Number of STOP bits generated. STB specifies 1, 1.5, or 2 STOP bits in each transmitted character. When STB = 1, the WLS bit determines the number of STOP bits. The receiver clocks only the first STOP bit, regardless of the number of STOP bits selected. The number of STOP bits generated is summarized in." "0,1" textline " " bitfld.long 0x0 3. " PEN ,Parity enable. The PEN bit works in conjunction with the SP and EPS bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" bitfld.long 0x0 4. " EPS ,Even parity select. Selects the parity when parity is enabled (PEN = 1). The EPS bit works in conjunction with the SP and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" textline " " bitfld.long 0x0 5. " SP ,Stick parity. The SP bit works in conjunction with the EPS and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" bitfld.long 0x0 6. " BC ,Break control." "0,1" textline " " bitfld.long 0x0 7. " DLAB ,Divisor latch access bit. The divisor latch registers (DLL and DLH) can be accessed at dedicated addresses or at addresses shared by RBR, THR, and IER. Using the shared addresses requires toggling DLAB to change which registers are selected. If the dedicated addresses are used, keep DLAB = 0." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "PRUSS_UART_MODEM_CONTROL_REGISTER,The Modem control register provides the ability to enable/disable the autoflow functions, and enable/disable the loopback function for diagnostic purposes." bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " RTS ,RTS control. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0." "0,1" textline " " bitfld.long 0x0 2. " OUT1 ,OUT1 Control Bit" "0,1" bitfld.long 0x0 3. " OUT2 ,OUT2 Control Bit" "0,1" textline " " bitfld.long 0x0 4. " LOOP ,Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature." "0,1" bitfld.long 0x0 5. " AFE ,Autoflow control enable. Autoflow control allows the and signals to provide handshaking between UARTs during data transfer. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "PRUSS_UART_LINE_STATUS_REGISTER,The Line status register provides information to the CPU concerning the status of data transfers. Line status register is intended for read operations only; do not write to this register. Bits 1 through 4 record the error conditions that produce a receiver line status interrupt." bitfld.long 0x0 0. " DR ,Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 1. " OE ,Overrun error (OE) indicator. An overrun error in the non-FIFO mode is different from an overrun error in the FIFO mode. If the OE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 2. " PE ,Parity error (PE) indicator. A parity error occurs when the parity of the received character does not match the parity selected with the EPS bit in the line control register (LCR). If the PE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 3. " FE ,Framing error (FE) indicator. A framing error occurs when the received character does not have a valid STOP bit. In response to a framing error, the UART sets the FE bit and waits until the signal on the RX pin goes high. Once the RX signal goes high, the receiver is ready to detect a new START bit and receive new data. If the FE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 4. " BI ,Break indicator. The BI bit is set whenever the receive data input (UARTn_RXD) was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the START, data, PARITY, and STOP bits. If the BI bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 5. " THRE ,Transmitter holding register empty (THRE) indicator. If the THRE bit is set and the corresponding interrupt enable bit is set (ETBEI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 6. " TEMT ,Transmitter empty (TEMT) indicator. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 7. " RXFIFOE ,Receiver FIFO error. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "PRUSS_UART_MODEM_STATUS_REGISTER,The Modem status register provides information to the CPU concerning the status of modem control signals. Modem status register is intended for read operations only; do not write to this register." bitfld.long 0x0 0. " DCTS ,Change in CTS indicator bit. DCTS indicates that the CTS input has changed state since the last time it was read by the CPU. When DCTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled, no interrupt is generated." "0,1" bitfld.long 0x0 1. " DDSR ,Change in DSR indicator bit. DDSR indicates that the DSR input has changed state since the last time it was read by the CPU. When DDSR is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" textline " " bitfld.long 0x0 2. " TERI ,Trailing edge of RI (TERI) indicator bit. TERI indicates that the RI input has changed from a low to a high. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" bitfld.long 0x0 3. " DCD ,Change in DCD indicator bit. DCD indicates that the DCD input has changed state since the last time it was read by the CPU. When DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" textline " " bitfld.long 0x0 4. " CTS ,Complement of the Clear To Send input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 1 (RTS)." "0,1" bitfld.long 0x0 5. " DSR ,Complement of the Data Set Ready input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 0 (DTR)." "0,1" textline " " bitfld.long 0x0 6. " RI ,Complement of the Ring Indicator input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 2 (OUT1)." "0,1" bitfld.long 0x0 7. " CD ,Complement of the Carrier Detect input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 3 (OUT2)." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_UART_SCRATCH_REGISTER,The Scratch Pad register is intended for programmer's use as a scratch pad. It temporarily holds the programmer's data without affecting UART operation." hexmask.long.byte 0x0 0.--7. 1. " SCR ,These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "PRUSS_UART_DIVISOR_REGISTER_LSB_,Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value." hexmask.long.byte 0x0 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "PRUSS_UART_DIVISOR_REGISTER_MSB_,Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value." hexmask.long.byte 0x0 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "PRUSS_UART_PERIPHERAL_ID_REGISTER,Peripheral Identification register" hexmask.long 0x0 0.--31. 1. " PID ," group.byte 0x30++0x3 line.long 0x0 "PRUSS_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER,Power and emulation management register" bitfld.long 0x0 0. " FREE ,Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When halted, the UART can handle register read/write requests, but does not generate any transmission/reception, interrupts or events." "0,1" hexmask.long.word 0x0 1.--12. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 13. " URRST ,UART receiver reset. Resets and enables the receiver." "0,1" bitfld.long 0x0 14. " UTRST ,UART transmitter reset. Resets and enables the transmitter." "0,1" textline " " bitfld.long 0x0 15. " RESERVED ,Reserved. This bit must always be written with a 0." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "PRUSS_UART_MODE_DEFINITION_REGISTER,The Mode definition register determines the over-sampling mode for the UART." bitfld.long 0x0 0. " OSM_SEL ,Over-Sampling Mode Select." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "PRUSS2_UART" base ad:0x4B2A8000 width 68. group.byte 0x0++0x3 line.long 0x0 "PRUSS_UART_RBR_THR_REGISTERS,In the non-FIFO mode, when a character is placed in Receiver buffer register and the receiver data-ready interrupt is enabled (DR = 1 in Interrupt identification register), an interrupt is generated. This interrupt is cleared when the character is read from Receiver buffer register. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register, and it is cleared when the FIFO contents drop below the trigger level. In the non-FIFO mode, if Transmitter holding register is empty and the THR empty (THRE) interrupt is enabled (ETBEI = 1 in Interrupt enable register), an interrupt is generated. This interrupt is cleared when a character is loaded into Transmitter holding register or the Interrupt identification register is read. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or Interrupt identification register is read." hexmask.long.byte 0x0 0.--7. 1. " DATA ,Read: Read Receive Buffer RegisterWrite: Write Transmitter Holding Register ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "PRUSS_UART_INTERRUPT_ENABLE_REGISTER,The Interrupt enable register is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in Interrupt enable register is forwarded to the CPU." bitfld.long 0x0 0. " ERBI ,Receiver data available interrupt and character timeout indication interrupt enable." "0,1" bitfld.long 0x0 1. " ETBEI ,Transmitter holding register empty interrupt enable." "0,1" textline " " bitfld.long 0x0 2. " ELSI ,Receiver line status interrupt enable." "0,1" bitfld.long 0x0 3. " EDSSI ,Enable Modem Status Interrupt" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "PRUSS_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER,The Interrupt identification register is a read-only register at the same address as the FIFO control register, which is a write-only register. When an interrupt is generated and enabled in the Interrupt enable register, Interrupt identification register indicates that an interrupt is pending in the IPEND bit and encodes the type of interrupt in the INTID bits. Reading Interrupt identification register clears any THR empty (THRE) interrupts that are pending. The FIFOEN bit in Interrupt identification register can be checked to determine whether the UART is in the FIFO mode or the non-FIFO mode. Use FIFO control register to enable and clear the FIFOs and to select the receiver FIFO trigger level. The FIFOEN bit in FIFO control register must be set to 1 before other FIFO control register bits are written to or the FIFO control register bits are not programmed." bitfld.long 0x0 0. " IPEND_FIFOEN ,Read: Interrupt pending. When any UART interrupt is generated and is enabled in IER, IPEND is forced to 0. IPEND remains 0 until all pending interrupts are cleared or until a hardware reset occurs. If no interrupts are enabled, IPEND is never forced to 0.Write: Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to or the FCR bits are not programmed. Clearing this bit clears the FIFO counters. ." "0,1" bitfld.long 0x0 1.--3. " INTID ,Read: Interrupt type. See .0x4-0x5: Reserved . Write: . Bit 3: DMAMODE1: DMA MODE1 enable if FIFOs are enabled. Always write 1 to DMAMODE1. After a hardware reset, change DMAMODE1 from 0 to 1. DMAMODE1 = 1 is a requirement for proper communication between the UART and the EDMA controller. . Bit 2: TXCLR: Transmitter FIFO clear. Write a 1 to TXCLR to clear the bit. . Bit 1: RXCLR: Receiver FIFO clear. Write a 1 to RXCLR to clear the bit. ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 6.--7. " FIFOEN_RXFIFTL ,Read: FIFOs enabled.0x1-0x2: Reserved . Write: Receiver FIFO trigger level. RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the FIFO drops below the trigger level, the interrupt is cleared. ." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "PRUSS_UART_LINE_CONTROL_REGISTER,The system programmer controls the format of the asynchronous data communication exchange by using Line control register. In addition, the programmer can retrieve, inspect, and modify the content of line control register; this eliminates the need for separate storage of the line characteristics in system memory." bitfld.long 0x0 0.--1. " WLS ,Word length select. Number of bits in each transmitted or received serial character. When STB = 1, the WLS bit determines the number of STOP bits." "0,1,2,3" bitfld.long 0x0 2. " STB ,Number of STOP bits generated. STB specifies 1, 1.5, or 2 STOP bits in each transmitted character. When STB = 1, the WLS bit determines the number of STOP bits. The receiver clocks only the first STOP bit, regardless of the number of STOP bits selected. The number of STOP bits generated is summarized in." "0,1" textline " " bitfld.long 0x0 3. " PEN ,Parity enable. The PEN bit works in conjunction with the SP and EPS bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" bitfld.long 0x0 4. " EPS ,Even parity select. Selects the parity when parity is enabled (PEN = 1). The EPS bit works in conjunction with the SP and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" textline " " bitfld.long 0x0 5. " SP ,Stick parity. The SP bit works in conjunction with the EPS and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" bitfld.long 0x0 6. " BC ,Break control." "0,1" textline " " bitfld.long 0x0 7. " DLAB ,Divisor latch access bit. The divisor latch registers (DLL and DLH) can be accessed at dedicated addresses or at addresses shared by RBR, THR, and IER. Using the shared addresses requires toggling DLAB to change which registers are selected. If the dedicated addresses are used, keep DLAB = 0." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "PRUSS_UART_MODEM_CONTROL_REGISTER,The Modem control register provides the ability to enable/disable the autoflow functions, and enable/disable the loopback function for diagnostic purposes." bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " RTS ,RTS control. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0." "0,1" textline " " bitfld.long 0x0 2. " OUT1 ,OUT1 Control Bit" "0,1" bitfld.long 0x0 3. " OUT2 ,OUT2 Control Bit" "0,1" textline " " bitfld.long 0x0 4. " LOOP ,Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature." "0,1" bitfld.long 0x0 5. " AFE ,Autoflow control enable. Autoflow control allows the and signals to provide handshaking between UARTs during data transfer. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "PRUSS_UART_LINE_STATUS_REGISTER,The Line status register provides information to the CPU concerning the status of data transfers. Line status register is intended for read operations only; do not write to this register. Bits 1 through 4 record the error conditions that produce a receiver line status interrupt." bitfld.long 0x0 0. " DR ,Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 1. " OE ,Overrun error (OE) indicator. An overrun error in the non-FIFO mode is different from an overrun error in the FIFO mode. If the OE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 2. " PE ,Parity error (PE) indicator. A parity error occurs when the parity of the received character does not match the parity selected with the EPS bit in the line control register (LCR). If the PE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 3. " FE ,Framing error (FE) indicator. A framing error occurs when the received character does not have a valid STOP bit. In response to a framing error, the UART sets the FE bit and waits until the signal on the RX pin goes high. Once the RX signal goes high, the receiver is ready to detect a new START bit and receive new data. If the FE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 4. " BI ,Break indicator. The BI bit is set whenever the receive data input (UARTn_RXD) was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the START, data, PARITY, and STOP bits. If the BI bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 5. " THRE ,Transmitter holding register empty (THRE) indicator. If the THRE bit is set and the corresponding interrupt enable bit is set (ETBEI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 6. " TEMT ,Transmitter empty (TEMT) indicator. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 7. " RXFIFOE ,Receiver FIFO error. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "PRUSS_UART_MODEM_STATUS_REGISTER,The Modem status register provides information to the CPU concerning the status of modem control signals. Modem status register is intended for read operations only; do not write to this register." bitfld.long 0x0 0. " DCTS ,Change in CTS indicator bit. DCTS indicates that the CTS input has changed state since the last time it was read by the CPU. When DCTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled, no interrupt is generated." "0,1" bitfld.long 0x0 1. " DDSR ,Change in DSR indicator bit. DDSR indicates that the DSR input has changed state since the last time it was read by the CPU. When DDSR is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" textline " " bitfld.long 0x0 2. " TERI ,Trailing edge of RI (TERI) indicator bit. TERI indicates that the RI input has changed from a low to a high. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" bitfld.long 0x0 3. " DCD ,Change in DCD indicator bit. DCD indicates that the DCD input has changed state since the last time it was read by the CPU. When DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" textline " " bitfld.long 0x0 4. " CTS ,Complement of the Clear To Send input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 1 (RTS)." "0,1" bitfld.long 0x0 5. " DSR ,Complement of the Data Set Ready input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 0 (DTR)." "0,1" textline " " bitfld.long 0x0 6. " RI ,Complement of the Ring Indicator input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 2 (OUT1)." "0,1" bitfld.long 0x0 7. " CD ,Complement of the Carrier Detect input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 3 (OUT2)." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_UART_SCRATCH_REGISTER,The Scratch Pad register is intended for programmer's use as a scratch pad. It temporarily holds the programmer's data without affecting UART operation." hexmask.long.byte 0x0 0.--7. 1. " SCR ,These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "PRUSS_UART_DIVISOR_REGISTER_LSB_,Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value." hexmask.long.byte 0x0 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "PRUSS_UART_DIVISOR_REGISTER_MSB_,Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value." hexmask.long.byte 0x0 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "PRUSS_UART_PERIPHERAL_ID_REGISTER,Peripheral Identification register" hexmask.long 0x0 0.--31. 1. " PID ," group.byte 0x30++0x3 line.long 0x0 "PRUSS_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER,Power and emulation management register" bitfld.long 0x0 0. " FREE ,Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When halted, the UART can handle register read/write requests, but does not generate any transmission/reception, interrupts or events." "0,1" hexmask.long.word 0x0 1.--12. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 13. " URRST ,UART receiver reset. Resets and enables the receiver." "0,1" bitfld.long 0x0 14. " UTRST ,UART transmitter reset. Resets and enables the transmitter." "0,1" textline " " bitfld.long 0x0 15. " RESERVED ,Reserved. This bit must always be written with a 0." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "PRUSS_UART_MODE_DEFINITION_REGISTER,The Mode definition register determines the over-sampling mode for the UART." bitfld.long 0x0 0. " OSM_SEL ,Over-Sampling Mode Select." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "PRUSS1_ECAP" base ad:0x4B230000 width 19. group.byte 0x0++0x3 line.long 0x0 "PRUSS_ECAP_TSCNT,Time Stamp Counter Register" hexmask.long 0x0 0.--31. 1. " TSCNT ,Active 32 bit-counter register that is used as the capture time-base" group.byte 0x4++0x3 line.long 0x0 "PRUSS_ECAP_CNTPHS,Counter Phase Control Register" hexmask.long 0x0 0.--31. 1. " CNTPHS ,Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCNT and is loaded intoPRUSS_ECAP_TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM time-bases." group.byte 0x8++0x3 line.long 0x0 "PRUSS_ECAP_CAP1,Capture-1 Register" hexmask.long 0x0 0.--31. 1. " CAP1 ,This register can be loaded (written) by the following. (a) Time-Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0xC++0x3 line.long 0x0 "PRUSS_ECAP_CAP2,Capture-2 Register" hexmask.long 0x0 0.--31. 1. " CAP2 ,This register can be loaded (written) by the following. (a) Time- Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0x10++0x3 line.long 0x0 "PRUSS_ECAP_CAP3,Capture-3 Register" hexmask.long 0x0 0.--31. 1. " CAP3 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. User software updates the PWM period value through this register. In this mode, CAP3 shadows CAP1." group.byte 0x14++0x3 line.long 0x0 "PRUSS_ECAP_CAP4,Capture-4 Register" hexmask.long 0x0 0.--31. 1. " CAP4 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow (ACMP) register. User software updates the PWM compare value through this register. In this mode, CAP4 shadows CAP2." group.byte 0x28++0x1 line.word 0x0 "PRUSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select 0x0 = Capture Event 1 triggered on a rising edge (RE) 0x1 = Capture Event 1 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1 0x0 = Do not reset counter on Capture Event 1 (absolute time stamp) 0x1 = Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select 0x0 = Capture Event 2 triggered on a rising edge (RE) 0x1 = Capture Event 2 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2 0x0 = Do not reset counter on Capture Event 2 (absolute time stamp) 0x1 = Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select 0x0 = Capture Event 3 triggered on a rising edge (RE) 0x1 = Capture Event 3 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3 0x0 = Do not reset counter on Capture Event 3 (absolute time stamp) 0x1 = Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select 0x0 = Capture Event 4 triggered on a rising edge (RE) 0x1 = Capture Event 4 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4 0x0 = Do not reset counter on Capture Event 4 (absolute time stamp operation) 0x1 = Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading ofPRUSS_ECAP_CAP1 to PRUSS_ECAP_CAP4 registers on a capture event 0x0 = Disable PRUSS_ECAP_CAP1-PRUSS_ECAP_CAP4 register loads at capture event time. 0x1 = Enable PRUSS_ECAP_CAP1-PRUSS_ECAP_CAP4 register loads at capture event time." "0,1" bitfld.word 0x0 9.--13. " EVTFLTPS ,Event Filter prescale select: 0x0 = Divide by 1 (i.e,. no prescale, by-pass the prescaler) 0x1 = Divide by 2 0x2 = Divide by 4 0x3 = Divide by 6 0x4 = Divide by 8 0x5 = Divide by 10 0x1E = Divide by 60 0x1F = Divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control 0x0 = TSCNT counter stops immediately on emulation suspend. 0x1 = TSCNT counter runs until = 0. 0x2 = TSCNT counter is unaffected by emulation suspend (Run Free). 0x3 = TSCNT counter is unaffected by emulation suspend (Run Free)." "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "PRUSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x0 0. " CONTONESHT ,Continuous or one-shot mode control (applicable only in capture mode) 0x0 = Operate in continuous mode 0x1 = Operate in one-shot mode" "0,1" bitfld.word 0x0 1.--2. " STOPVALUE ,Stop value for one-shot mode. This is the number (between 1 and 4) of captures allowed to occur before the CAP (1 through 4) registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1 and 4) of the capture register in which the circular buffer wraps around and starts again. Notes: STOPVALUE is compared to Mod4 counter and, when equal, the following two actions occur. (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. In one-shot mode, further interrupt events are blocked until re-armed. 0x0 = Stop after Capture Event 1 in one-shot mode. Wrap after Capture Event 1 in continuous mode. 0x1 = Stop after Capture Event 2 in one-shot mode. Wrap after Capture Event 2 in continuous mode. 0x2 = Stop after Capture Event 3 in one-shot mode. Wrap after Capture Event 3 in continuous mode. 0x3 = Stop after Capture Event 4 in one-shot mode. Wrap after Capture Event 4 in continuous mode." "0,1,2,3" textline " " bitfld.word 0x0 3. " REARMRESET ,One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0x0 = Has no effect (reading always returns a 0) 0x1 = Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero. 2) Unfreezes the Mod4 counter. 3) Enables capture register loads." "0,1" bitfld.word 0x0 4. " TSCNTSTP ,Time Stamp (TSCNT) Counter Stop (freeze) Control 0x0 = TSCNT stopped 0x1 = TSCNT free-running" "0,1" textline " " bitfld.word 0x0 5. " SYNCI_EN ,Counter (TSCNT) Sync-In select mode 0x0 = Disable sync-in option 0x1 = Enable counter (TSCNT) to be loaded from" "0,1" bitfld.word 0x0 6.--7. " SYNCO_SEL ,Sync-Out Select 0x0 = Select sync-in event to be the sync-out signal (pass through) 0x1 = Select CTR = PRD event to be the sync-out signal 0x2 = Disable sync out signal 0x3 = Disable sync out signal" "0,1,2,3" textline " " bitfld.word 0x0 8. " SWSYNC ,Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via the CTR = PRD event. Note: Selection CTR = PRD is meaningful only in APWM mode. However, a choice of CAP mode is also available if it may be of use. 0x0 = Writing a zero has no effect. Reading always returns a zero 0x1 = Writing a one forces a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 1'b00. After writing a 1, this bit returns to a zero." "0,1" bitfld.word 0x0 9. " CAPAPWM ,CAP/APWM operating mode select 0x0 = ECAP module operates in capture mode. This mode forces the following configuration. 0x1 = ECAP module operates in APWM mode. This mode forces the following configuration." "0,1" textline " " bitfld.word 0x0 10. " APWMPOL ,APWM output polarity select. This is applicable only in APWM operating mode 0x0 = Output is active high (Compare value defines high time) 0x1 = Output is active low (Compare value defines low time)" "0,1" bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2C++0x1 line.word 0x0 "PRUSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Interrupt Enable. 0x0 = Disable Capture Event 1 as an Interrupt source. 0x1 = Enable Capture Event 1 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Interrupt Enable. 0x0 = Disable Capture Event 2 as an Interrupt source. 0x1 = Enable Capture Event 2 as an Interrupt source." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Interrupt Enable. 0x0 = Disable Capture Event 3 as an Interrupt source. 0x1 = Enable Capture Event 3 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Interrupt Enable. 0x0 = Disable Capture Event 4 as an Interrupt source. 0x1 = Enable Capture Event 4 as an Interrupt source." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Interrupt Enable. 0x0 = Disable counter Overflow as an Interrupt source. 0x1 = Enable counter Overflow as an Interrupt source." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal 0x0 = Disable Period Equal as an Interrupt source. 0x1 = Enable Period Equal as an Interrupt source." "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal 0x0 = Disable Compare Equal as an Interrupt source. 0x1 = Enable Compare Equal as an Interrupt source." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "PRUSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag 0x0 = Indicates no interrupt generated. 0x1 = Indicates that an interrupt was generated." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the first event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the second event occurred at ECAPn pin." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the third event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag This flag is only active in CAP mode. 0x0 = Indicates no event occurred 0x1 = Indicates the fourth event occurred at ECAPn pin" "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the counter (TSCNT) has made the transition from 0xFFFFFFFF to 0x00000000" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the period register value (APRD) and was reset." "0,1" bitfld.word 0x0 7. " CMPEQ ,Compare Equal Compare Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the compare register value (ACMP)" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "PRUSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT1 flag condition." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT2 flag condition." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CNTOVF flag condition" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CTR=PRD flag condition" "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal Compare Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CTR=CMP flag condition" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x34++0x1 line.word 0x0 "PRUSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Always reads back a 0. Force Capture Event 1 0x0 = No effect. 0x1 = Writing a 1 sets the CEVT1 flag bit." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Force Capture Event 2 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT2 flag bit." "0,1" bitfld.word 0x0 3. " CEVT3 ,Force Capture Event 3 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT3 flag bit" "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Force Capture Event 4 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT4 flag bit" "0,1" bitfld.word 0x0 5. " CNTOVF ,Force Counter Overflow 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 to this bit sets the CNTOVF flag bit." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Force Counter Equal Period Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CTR=PRD flag bit." "0,1" bitfld.word 0x0 7. " CMPEQ ,Force Counter Equal Compare Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CTR=CMP flag bit." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "PRUSS_ECAP_PID,ECAP Revision ID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "PRUSS2_ECAP" base ad:0x4B2B0000 width 19. group.byte 0x0++0x3 line.long 0x0 "PRUSS_ECAP_TSCNT,Time Stamp Counter Register" hexmask.long 0x0 0.--31. 1. " TSCNT ,Active 32 bit-counter register that is used as the capture time-base" group.byte 0x4++0x3 line.long 0x0 "PRUSS_ECAP_CNTPHS,Counter Phase Control Register" hexmask.long 0x0 0.--31. 1. " CNTPHS ,Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCNT and is loaded intoPRUSS_ECAP_TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM time-bases." group.byte 0x8++0x3 line.long 0x0 "PRUSS_ECAP_CAP1,Capture-1 Register" hexmask.long 0x0 0.--31. 1. " CAP1 ,This register can be loaded (written) by the following. (a) Time-Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0xC++0x3 line.long 0x0 "PRUSS_ECAP_CAP2,Capture-2 Register" hexmask.long 0x0 0.--31. 1. " CAP2 ,This register can be loaded (written) by the following. (a) Time- Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0x10++0x3 line.long 0x0 "PRUSS_ECAP_CAP3,Capture-3 Register" hexmask.long 0x0 0.--31. 1. " CAP3 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. User software updates the PWM period value through this register. In this mode, CAP3 shadows CAP1." group.byte 0x14++0x3 line.long 0x0 "PRUSS_ECAP_CAP4,Capture-4 Register" hexmask.long 0x0 0.--31. 1. " CAP4 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow (ACMP) register. User software updates the PWM compare value through this register. In this mode, CAP4 shadows CAP2." group.byte 0x28++0x1 line.word 0x0 "PRUSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select 0x0 = Capture Event 1 triggered on a rising edge (RE) 0x1 = Capture Event 1 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1 0x0 = Do not reset counter on Capture Event 1 (absolute time stamp) 0x1 = Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select 0x0 = Capture Event 2 triggered on a rising edge (RE) 0x1 = Capture Event 2 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2 0x0 = Do not reset counter on Capture Event 2 (absolute time stamp) 0x1 = Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select 0x0 = Capture Event 3 triggered on a rising edge (RE) 0x1 = Capture Event 3 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3 0x0 = Do not reset counter on Capture Event 3 (absolute time stamp) 0x1 = Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select 0x0 = Capture Event 4 triggered on a rising edge (RE) 0x1 = Capture Event 4 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4 0x0 = Do not reset counter on Capture Event 4 (absolute time stamp operation) 0x1 = Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading ofPRUSS_ECAP_CAP1 to PRUSS_ECAP_CAP4 registers on a capture event 0x0 = Disable PRUSS_ECAP_CAP1-PRUSS_ECAP_CAP4 register loads at capture event time. 0x1 = Enable PRUSS_ECAP_CAP1-PRUSS_ECAP_CAP4 register loads at capture event time." "0,1" bitfld.word 0x0 9.--13. " EVTFLTPS ,Event Filter prescale select: 0x0 = Divide by 1 (i.e,. no prescale, by-pass the prescaler) 0x1 = Divide by 2 0x2 = Divide by 4 0x3 = Divide by 6 0x4 = Divide by 8 0x5 = Divide by 10 0x1E = Divide by 60 0x1F = Divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control 0x0 = TSCNT counter stops immediately on emulation suspend. 0x1 = TSCNT counter runs until = 0. 0x2 = TSCNT counter is unaffected by emulation suspend (Run Free). 0x3 = TSCNT counter is unaffected by emulation suspend (Run Free)." "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "PRUSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x0 0. " CONTONESHT ,Continuous or one-shot mode control (applicable only in capture mode) 0x0 = Operate in continuous mode 0x1 = Operate in one-shot mode" "0,1" bitfld.word 0x0 1.--2. " STOPVALUE ,Stop value for one-shot mode. This is the number (between 1 and 4) of captures allowed to occur before the CAP (1 through 4) registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1 and 4) of the capture register in which the circular buffer wraps around and starts again. Notes: STOPVALUE is compared to Mod4 counter and, when equal, the following two actions occur. (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. In one-shot mode, further interrupt events are blocked until re-armed. 0x0 = Stop after Capture Event 1 in one-shot mode. Wrap after Capture Event 1 in continuous mode. 0x1 = Stop after Capture Event 2 in one-shot mode. Wrap after Capture Event 2 in continuous mode. 0x2 = Stop after Capture Event 3 in one-shot mode. Wrap after Capture Event 3 in continuous mode. 0x3 = Stop after Capture Event 4 in one-shot mode. Wrap after Capture Event 4 in continuous mode." "0,1,2,3" textline " " bitfld.word 0x0 3. " REARMRESET ,One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0x0 = Has no effect (reading always returns a 0) 0x1 = Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero. 2) Unfreezes the Mod4 counter. 3) Enables capture register loads." "0,1" bitfld.word 0x0 4. " TSCNTSTP ,Time Stamp (TSCNT) Counter Stop (freeze) Control 0x0 = TSCNT stopped 0x1 = TSCNT free-running" "0,1" textline " " bitfld.word 0x0 5. " SYNCI_EN ,Counter (TSCNT) Sync-In select mode 0x0 = Disable sync-in option 0x1 = Enable counter (TSCNT) to be loaded from" "0,1" bitfld.word 0x0 6.--7. " SYNCO_SEL ,Sync-Out Select 0x0 = Select sync-in event to be the sync-out signal (pass through) 0x1 = Select CTR = PRD event to be the sync-out signal 0x2 = Disable sync out signal 0x3 = Disable sync out signal" "0,1,2,3" textline " " bitfld.word 0x0 8. " SWSYNC ,Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via the CTR = PRD event. Note: Selection CTR = PRD is meaningful only in APWM mode. However, a choice of CAP mode is also available if it may be of use. 0x0 = Writing a zero has no effect. Reading always returns a zero 0x1 = Writing a one forces a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 1'b00. After writing a 1, this bit returns to a zero." "0,1" bitfld.word 0x0 9. " CAPAPWM ,CAP/APWM operating mode select 0x0 = ECAP module operates in capture mode. This mode forces the following configuration. 0x1 = ECAP module operates in APWM mode. This mode forces the following configuration." "0,1" textline " " bitfld.word 0x0 10. " APWMPOL ,APWM output polarity select. This is applicable only in APWM operating mode 0x0 = Output is active high (Compare value defines high time) 0x1 = Output is active low (Compare value defines low time)" "0,1" bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2C++0x1 line.word 0x0 "PRUSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Interrupt Enable. 0x0 = Disable Capture Event 1 as an Interrupt source. 0x1 = Enable Capture Event 1 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Interrupt Enable. 0x0 = Disable Capture Event 2 as an Interrupt source. 0x1 = Enable Capture Event 2 as an Interrupt source." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Interrupt Enable. 0x0 = Disable Capture Event 3 as an Interrupt source. 0x1 = Enable Capture Event 3 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Interrupt Enable. 0x0 = Disable Capture Event 4 as an Interrupt source. 0x1 = Enable Capture Event 4 as an Interrupt source." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Interrupt Enable. 0x0 = Disable counter Overflow as an Interrupt source. 0x1 = Enable counter Overflow as an Interrupt source." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal 0x0 = Disable Period Equal as an Interrupt source. 0x1 = Enable Period Equal as an Interrupt source." "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal 0x0 = Disable Compare Equal as an Interrupt source. 0x1 = Enable Compare Equal as an Interrupt source." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "PRUSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag 0x0 = Indicates no interrupt generated. 0x1 = Indicates that an interrupt was generated." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the first event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the second event occurred at ECAPn pin." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the third event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag This flag is only active in CAP mode. 0x0 = Indicates no event occurred 0x1 = Indicates the fourth event occurred at ECAPn pin" "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the counter (TSCNT) has made the transition from 0xFFFFFFFF to 0x00000000" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the period register value (APRD) and was reset." "0,1" bitfld.word 0x0 7. " CMPEQ ,Compare Equal Compare Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the compare register value (ACMP)" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "PRUSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT1 flag condition." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT2 flag condition." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CNTOVF flag condition" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CTR=PRD flag condition" "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal Compare Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CTR=CMP flag condition" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x34++0x1 line.word 0x0 "PRUSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Always reads back a 0. Force Capture Event 1 0x0 = No effect. 0x1 = Writing a 1 sets the CEVT1 flag bit." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Force Capture Event 2 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT2 flag bit." "0,1" bitfld.word 0x0 3. " CEVT3 ,Force Capture Event 3 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT3 flag bit" "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Force Capture Event 4 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT4 flag bit" "0,1" bitfld.word 0x0 5. " CNTOVF ,Force Counter Overflow 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 to this bit sets the CNTOVF flag bit." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Force Counter Equal Period Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CTR=PRD flag bit." "0,1" bitfld.word 0x0 7. " CMPEQ ,Force Counter Equal Compare Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CTR=CMP flag bit." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "PRUSS_ECAP_PID,ECAP Revision ID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "PRUSS1_MII_RT" base ad:0x4B232000 width 23. group.byte 0x0++0x3 line.long 0x0 "PRUSS_MII_RT_RXCFG0,MII RXCFG 0 REGISTER This register contains the PRU0 RXCFG configuration variables () for the RX path. is attached to PRU0. controls which RX port is attached to PRU0." bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0 Disable 0x1 Enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is DA" "0,1" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1)" "0,1" textline " " bitfld.long 0x0 4. " RX_L2_EN ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: that if TX_AUTO_SEQUENCE enabled, this bit cannot get enable since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received. Must be selected /updated when the port is disabled or no traffic It only effects R31 and RX L2 order" "0,1" textline " " bitfld.long 0x0 6. " RX_AUTO_FWD_PRE ,Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1:Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE." "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRUSS_MII_RT_RXCFG1,This register contains the PRU1 RXCFG configuration variables () for the RX path. is attached to PRU1. controls which RX port is attached to PRU1" bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is destination address." "0,1" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1)" "0,1" textline " " bitfld.long 0x0 4. " RX_L2_EN ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: If TX_AUTO_SEQUENCE is enabled, this bit cannot get enabled since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received." "0,1" textline " " bitfld.long 0x0 6. " RX_AUTO_FWD_PRE ,Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1: Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PRUSS_MII_RT_TXCFG0,This register contains the configuration variables for the transmit path on the MII interface port 0. is attached to Port TX0. controls which PRU is selected for TX0" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency." "0,1" textline " " bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event.Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself." "0,1" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0)" "0,1" textline " " bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter. Also, the masking logic is disabled and only the MII data is used." "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration." bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the PRUSS_GICLK clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "PRUSS_MII_RT_TXCFG1,MII TXCFG 1 REGISTER This register contains the configuration variables for the transmit path on the MII interface port 1. is attached to Port TX1. controls which PRU is selected for TX1" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency." "0,1" textline " " bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event.Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself." "0,1" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0)" "0,1" textline " " bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter.TX data from PRU1 is selected Also, the masking logic is disabled and only the MII data is used." "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration." bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the PRUSS_GICLK clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x20++0x3 line.long 0x0 "PRUSS_MII_RT_TX_CRC0,MII TXCRC 0 REGISTER It contains CRC32 which PRU0 reads" hexmask.long 0x0 0.--31. 1. " TX_CRC ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.byte 0x24++0x3 line.long 0x0 "PRUSS_MII_RT_TX_CRC1,MII TXCRC 1 REGISTER It contains CRC32 which PRU1 reads" hexmask.long 0x0 0.--31. 1. " TX_CRC ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.byte 0x30++0x3 line.long 0x0 "PRUSS_MII_RT_TX_IPG0,MII TXIPG 0 REGISTER" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_MII_RT_TX_IPG1,MII TXIPG 1 REGISTER" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PRUSS_MII_RT_PRS0,MII PORT STATUS 0 REGISTER" bitfld.long 0x0 0. " MII_COL ,Read the current state of pr1_mii0_col" "0,1" bitfld.long 0x0 1. " MII_CRS ,Read the current state of pr1_mii0_crs" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PRUSS_MII_RT_PRS1,MII PORT STATUS 1 REGISTER" bitfld.long 0x0 0. " MII_COL ,Read the current state of pr1_mii1_col" "0,1" bitfld.long 0x0 1. " MII_CRS ,Read the current state of pr1_mii1_crs" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PRUSS_MII_RT_RX_FRMS0,MII RXFRMS 0 REGISTER" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM ,Defines the maximum received frame count. If the total byte count of received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted." group.byte 0x44++0x3 line.long 0x0 "PRUSS_MII_RT_RX_FRMS1,MII RXFRMS 1 REGISTER" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM ,Defines the maximum received frame count. If the total byte count of the received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted." group.byte 0x48++0x3 line.long 0x0 "PRUSS_MII_RT_RX_PCNT0,MII RXPCNT 0 REGISTER" bitfld.long 0x0 0.--3. " RX_MIN_PCNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1 1 0x5 before 0xD5 0x2 2 0x5 before 0xD5 N min of N 0x5 before 0xD5 Note it does not need to be 0x5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_MAX_PCNT ,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted. Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "PRUSS_MII_RT_RX_PCNT1,MII RXPCNT 1 REGISTER" bitfld.long 0x0 0.--3. " RX_MIN_PCNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1: 1 0x5 before 0xD5 0x2: 2 0x5 before 0xD5 N: N 0x5 before 0xD5 Note it does not need to be 0x5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_MAX_PCNT ,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "PRUSS_MII_RT_RX_ERR0,MII RXERR 0 REGISTER" bitfld.long 0x0 0. " RX_MIN_PCNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 1. " RX_MAX_PCNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " bitfld.long 0x0 2. " RX_MIN_FRM_ERR ,Error status of received frame is less than the value of RX_MIN_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 3. " RX_MAX_FRM_ERR ,Error status of received frame is more than the value of RX_MAX_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "PRUSS_MII_RT_RX_ERR1,MII RXERR 1 REGISTER" bitfld.long 0x0 0. " RX_MIN_PCNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 1. " RX_MAX_PCNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " bitfld.long 0x0 2. " RX_MIN_FRM_ERR ,Error status of received frame is less than the value of RX_MIN_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 3. " RX_MAX_FRM_ERR ,Error status of received frame is more than the value of RX_MAX_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS2_MII_RT" base ad:0x4B2B2000 width 23. group.byte 0x0++0x3 line.long 0x0 "PRUSS_MII_RT_RXCFG0,MII RXCFG 0 REGISTER This register contains the PRU0 RXCFG configuration variables () for the RX path. is attached to PRU0. controls which RX port is attached to PRU0." bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0 Disable 0x1 Enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is DA" "0,1" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1)" "0,1" textline " " bitfld.long 0x0 4. " RX_L2_EN ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: that if TX_AUTO_SEQUENCE enabled, this bit cannot get enable since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received. Must be selected /updated when the port is disabled or no traffic It only effects R31 and RX L2 order" "0,1" textline " " bitfld.long 0x0 6. " RX_AUTO_FWD_PRE ,Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1:Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE." "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRUSS_MII_RT_RXCFG1,This register contains the PRU1 RXCFG configuration variables () for the RX path. is attached to PRU1. controls which RX port is attached to PRU1" bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is destination address." "0,1" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1)" "0,1" textline " " bitfld.long 0x0 4. " RX_L2_EN ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: If TX_AUTO_SEQUENCE is enabled, this bit cannot get enabled since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received." "0,1" textline " " bitfld.long 0x0 6. " RX_AUTO_FWD_PRE ,Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1: Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PRUSS_MII_RT_TXCFG0,This register contains the configuration variables for the transmit path on the MII interface port 0. is attached to Port TX0. controls which PRU is selected for TX0" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency." "0,1" textline " " bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event.Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself." "0,1" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0)" "0,1" textline " " bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter. Also, the masking logic is disabled and only the MII data is used." "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration." bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the PRUSS_GICLK clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "PRUSS_MII_RT_TXCFG1,MII TXCFG 1 REGISTER This register contains the configuration variables for the transmit path on the MII interface port 1. is attached to Port TX1. controls which PRU is selected for TX1" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency." "0,1" textline " " bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event.Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself." "0,1" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0)" "0,1" textline " " bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter.TX data from PRU1 is selected Also, the masking logic is disabled and only the MII data is used." "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration." bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the PRUSS_GICLK clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x20++0x3 line.long 0x0 "PRUSS_MII_RT_TX_CRC0,MII TXCRC 0 REGISTER It contains CRC32 which PRU0 reads" hexmask.long 0x0 0.--31. 1. " TX_CRC ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.byte 0x24++0x3 line.long 0x0 "PRUSS_MII_RT_TX_CRC1,MII TXCRC 1 REGISTER It contains CRC32 which PRU1 reads" hexmask.long 0x0 0.--31. 1. " TX_CRC ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.byte 0x30++0x3 line.long 0x0 "PRUSS_MII_RT_TX_IPG0,MII TXIPG 0 REGISTER" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_MII_RT_TX_IPG1,MII TXIPG 1 REGISTER" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PRUSS_MII_RT_PRS0,MII PORT STATUS 0 REGISTER" bitfld.long 0x0 0. " MII_COL ,Read the current state of pr1_mii0_col" "0,1" bitfld.long 0x0 1. " MII_CRS ,Read the current state of pr1_mii0_crs" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PRUSS_MII_RT_PRS1,MII PORT STATUS 1 REGISTER" bitfld.long 0x0 0. " MII_COL ,Read the current state of pr1_mii1_col" "0,1" bitfld.long 0x0 1. " MII_CRS ,Read the current state of pr1_mii1_crs" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PRUSS_MII_RT_RX_FRMS0,MII RXFRMS 0 REGISTER" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM ,Defines the maximum received frame count. If the total byte count of received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted." group.byte 0x44++0x3 line.long 0x0 "PRUSS_MII_RT_RX_FRMS1,MII RXFRMS 1 REGISTER" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM ,Defines the maximum received frame count. If the total byte count of the received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted." group.byte 0x48++0x3 line.long 0x0 "PRUSS_MII_RT_RX_PCNT0,MII RXPCNT 0 REGISTER" bitfld.long 0x0 0.--3. " RX_MIN_PCNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1 1 0x5 before 0xD5 0x2 2 0x5 before 0xD5 N min of N 0x5 before 0xD5 Note it does not need to be 0x5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_MAX_PCNT ,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted. Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "PRUSS_MII_RT_RX_PCNT1,MII RXPCNT 1 REGISTER" bitfld.long 0x0 0.--3. " RX_MIN_PCNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1: 1 0x5 before 0xD5 0x2: 2 0x5 before 0xD5 N: N 0x5 before 0xD5 Note it does not need to be 0x5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_MAX_PCNT ,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "PRUSS_MII_RT_RX_ERR0,MII RXERR 0 REGISTER" bitfld.long 0x0 0. " RX_MIN_PCNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 1. " RX_MAX_PCNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " bitfld.long 0x0 2. " RX_MIN_FRM_ERR ,Error status of received frame is less than the value of RX_MIN_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 3. " RX_MAX_FRM_ERR ,Error status of received frame is more than the value of RX_MAX_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "PRUSS_MII_RT_RX_ERR1,MII RXERR 1 REGISTER" bitfld.long 0x0 0. " RX_MIN_PCNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 1. " RX_MAX_PCNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " bitfld.long 0x0 2. " RX_MIN_FRM_ERR ,Error status of received frame is less than the value of RX_MIN_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 3. " RX_MAX_FRM_ERR ,Error status of received frame is more than the value of RX_MAX_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS1_MII_MDIO" base ad:0x4B232400 width 31. group.byte 0x0++0x3 line.long 0x0 "PRUSS_MII_MDIO_VER,MDIO MODULE VERSION REGISTER" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4++0x3 line.long 0x0 "PRUSS_MII_MDIO_CONTROL,MDIO MODULE CONTROL REGISTER" hexmask.long.word 0x0 0.--15. 1. " CLKDIV ,Clock Divider. This field specifies the division ratio between CLK and the frequency of MDCLK. MDCLK is disabled when clkdiv is set to 0. MDCLK frequency = clk frequency/(clkdiv+1)." bitfld.long 0x0 16. " RESERVED ," "0,1" textline " " bitfld.long 0x0 17. " INT_TEST_ENABLE ,Interrupt test enable. This bit can be set to 1 to enable the host to set the userint and linkint bits for test purposes." "0,1" bitfld.long 0x0 18. " FAULT_DETECT_ENABLE ,Fault detect enable. This bit has to be set to 1 to enable the physical layer fault detection." "0,1" textline " " bitfld.long 0x0 19. " FAULT ,Fault indicator. This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them. This indicates a physical layer fault and the module state machine is reset. Writing a 1 to it clears this bit." "0,1" bitfld.long 0x0 20. " PREAMBLE ,Preamble disable. Writing a 1 to this bit disables this device from sending MDIO frame preambles." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel. This field specifies the highest useraccess channel that is available in the module and is currently set to 1. This implies thatMDIOUserAccess1 is the highest available user access channel." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 29. " RESERVED ," "0,1" bitfld.long 0x0 30. " ENABLE ,Enable control. Writing a 1 to this bit enables the MDIO state machine, writing a 0 disables it. If the MDIO state machine is active at the time it is disabled, it will complete the current operation before halting and setting the idle bit. If using byte access, the enable bit has to be the last bit written in this register." "0,1" textline " " bitfld.long 0x0 31. " IDLE ,MDIO state machine IDLE. Set to 1 when the state machine is in the idle state." "0,1" group.byte 0x8++0x3 line.long 0x0 "PRUSS_MII_MDIO_ALIVE,PHY ACKNOWLEDGE STATUS REGISTER" hexmask.long 0x0 0.--31. 1. " ALIVE ,MDIO Alive bitfield. Each of the 32 bits of this register is set if the most recent access to the PHY with address corresponding to the register bit number was acknowledged by the PHY, the bit is reset if the PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause the corresponding alive bit to be updated. The alive bits are only meant to be used to give an indication of the presence or not of a PHY with the corresponding address. Writing a 1 to any bit will clear it, writing a 0 has no effect." group.byte 0xC++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINK,PHY LINK STATUS REGISTER" hexmask.long 0x0 0.--31. 1. " LINK ,MDIO Link state. This register is updated after a read of the Generic Status Register of a PHY. The bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge the read transaction. Writes to the register have no effect. In addition, the status of the two PHYs specified in theMDIOUserPhySel registers can be determined using the MLINK input pins. This is determined by the linksel bit in the MDIOUserPhySel register." group.byte 0x10++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINKINTRAW,LINK STATUS CHANGE INTERRUPT REGISTER (RAW VALUE)" bitfld.long 0x0 0.--1. " LINKINTRAW ,MDIO link change event, raw value. When asserted 1, a bit indicates that there was anMDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register. linkintraw[0] and linkintraw[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the event and writing 0 has no effect.If the int_test bit in the MDIOControl register is set, the host may set the linkintraw bits to a 1.This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINKINTMASKED,LINK STATUS CHANGE INTERRUPT REGISTER (MASKED VALUE)" bitfld.long 0x0 0.--1. " LINKINTMASKED ,MDIO link change interrupt, masked value. When asserted 1, a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register and the corresponding linkint_enable bit was set.. linkintmasked[0] and linkintmasked[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the interrupt and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the linkint bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTRAW,USER COMMAND COMPLETE INTERRUPT REGISTER (RAW VALUE)" bitfld.long 0x0 0.--1. " USERINTRAW ,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed. Writing a 1 will clear the event and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the userintraw bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKED,USER COMMAND COMPLETE INTERRUPT REGISTER (MASKED VALUE)" bitfld.long 0x0 0.--1. " USERINTMASKED ,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed and the corresponding userintmaskset bit is set to 1.Writing a 1 will clear the interrupt and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the userintmasked bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKSET,USER INTERRUPT MASK SET REGISTER" bitfld.long 0x0 0.--1. " USERINTMASKEDSET ,MDIO user interrupt mask set for userintmasked[1:0], respectively. Writing a bit to 1 will enable MDIO user command complete interrupts for that particular MDIOUserAccess register. MDIO user interrupt for a particular MDIOUserAccess register is disabled if the corresponding bit is 0. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKCLR,USER INTERRUPT MASK CLEAR REGISTER" bitfld.long 0x0 0.--1. " USERINTMASKEDCLR ,MDIO user command complete interrupt mask clear for userintmasked[1:0], respectively. Writing a bit to 1 will disable further user command complete interrupts for that particular MDIOUserAccess register. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERACCESS0,USER ACCESS REGISTER0" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. This field specifies the PHY to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. This field specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last." "0,1" group.byte 0x84++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERPHYSEL0,USER PHY SELECT REGISTER0" bitfld.long 0x0 0.--4. " PHYADR_MON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINT_ENABLE ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERACCESS1,USER ACCESS REGISTER1" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. This field specifies the PHY to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. This field specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last." "0,1" group.byte 0x8C++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERPHYSEL1,USER PHY SELECT REGISTER1" bitfld.long 0x0 0.--4. " PHYADR_MON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINT_ENABLE ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS2_MII_MDIO" base ad:0x4B2B2400 width 31. group.byte 0x0++0x3 line.long 0x0 "PRUSS_MII_MDIO_VER,MDIO MODULE VERSION REGISTER" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4++0x3 line.long 0x0 "PRUSS_MII_MDIO_CONTROL,MDIO MODULE CONTROL REGISTER" hexmask.long.word 0x0 0.--15. 1. " CLKDIV ,Clock Divider. This field specifies the division ratio between CLK and the frequency of MDCLK. MDCLK is disabled when clkdiv is set to 0. MDCLK frequency = clk frequency/(clkdiv+1)." bitfld.long 0x0 16. " RESERVED ," "0,1" textline " " bitfld.long 0x0 17. " INT_TEST_ENABLE ,Interrupt test enable. This bit can be set to 1 to enable the host to set the userint and linkint bits for test purposes." "0,1" bitfld.long 0x0 18. " FAULT_DETECT_ENABLE ,Fault detect enable. This bit has to be set to 1 to enable the physical layer fault detection." "0,1" textline " " bitfld.long 0x0 19. " FAULT ,Fault indicator. This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them. This indicates a physical layer fault and the module state machine is reset. Writing a 1 to it clears this bit." "0,1" bitfld.long 0x0 20. " PREAMBLE ,Preamble disable. Writing a 1 to this bit disables this device from sending MDIO frame preambles." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel. This field specifies the highest useraccess channel that is available in the module and is currently set to 1. This implies thatMDIOUserAccess1 is the highest available user access channel." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 29. " RESERVED ," "0,1" bitfld.long 0x0 30. " ENABLE ,Enable control. Writing a 1 to this bit enables the MDIO state machine, writing a 0 disables it. If the MDIO state machine is active at the time it is disabled, it will complete the current operation before halting and setting the idle bit. If using byte access, the enable bit has to be the last bit written in this register." "0,1" textline " " bitfld.long 0x0 31. " IDLE ,MDIO state machine IDLE. Set to 1 when the state machine is in the idle state." "0,1" group.byte 0x8++0x3 line.long 0x0 "PRUSS_MII_MDIO_ALIVE,PHY ACKNOWLEDGE STATUS REGISTER" hexmask.long 0x0 0.--31. 1. " ALIVE ,MDIO Alive bitfield. Each of the 32 bits of this register is set if the most recent access to the PHY with address corresponding to the register bit number was acknowledged by the PHY, the bit is reset if the PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause the corresponding alive bit to be updated. The alive bits are only meant to be used to give an indication of the presence or not of a PHY with the corresponding address. Writing a 1 to any bit will clear it, writing a 0 has no effect." group.byte 0xC++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINK,PHY LINK STATUS REGISTER" hexmask.long 0x0 0.--31. 1. " LINK ,MDIO Link state. This register is updated after a read of the Generic Status Register of a PHY. The bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge the read transaction. Writes to the register have no effect. In addition, the status of the two PHYs specified in theMDIOUserPhySel registers can be determined using the MLINK input pins. This is determined by the linksel bit in the MDIOUserPhySel register." group.byte 0x10++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINKINTRAW,LINK STATUS CHANGE INTERRUPT REGISTER (RAW VALUE)" bitfld.long 0x0 0.--1. " LINKINTRAW ,MDIO link change event, raw value. When asserted 1, a bit indicates that there was anMDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register. linkintraw[0] and linkintraw[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the event and writing 0 has no effect.If the int_test bit in the MDIOControl register is set, the host may set the linkintraw bits to a 1.This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINKINTMASKED,LINK STATUS CHANGE INTERRUPT REGISTER (MASKED VALUE)" bitfld.long 0x0 0.--1. " LINKINTMASKED ,MDIO link change interrupt, masked value. When asserted 1, a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register and the corresponding linkint_enable bit was set.. linkintmasked[0] and linkintmasked[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the interrupt and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the linkint bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTRAW,USER COMMAND COMPLETE INTERRUPT REGISTER (RAW VALUE)" bitfld.long 0x0 0.--1. " USERINTRAW ,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed. Writing a 1 will clear the event and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the userintraw bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKED,USER COMMAND COMPLETE INTERRUPT REGISTER (MASKED VALUE)" bitfld.long 0x0 0.--1. " USERINTMASKED ,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed and the corresponding userintmaskset bit is set to 1.Writing a 1 will clear the interrupt and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the userintmasked bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKSET,USER INTERRUPT MASK SET REGISTER" bitfld.long 0x0 0.--1. " USERINTMASKEDSET ,MDIO user interrupt mask set for userintmasked[1:0], respectively. Writing a bit to 1 will enable MDIO user command complete interrupts for that particular MDIOUserAccess register. MDIO user interrupt for a particular MDIOUserAccess register is disabled if the corresponding bit is 0. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKCLR,USER INTERRUPT MASK CLEAR REGISTER" bitfld.long 0x0 0.--1. " USERINTMASKEDCLR ,MDIO user command complete interrupt mask clear for userintmasked[1:0], respectively. Writing a bit to 1 will disable further user command complete interrupts for that particular MDIOUserAccess register. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERACCESS0,USER ACCESS REGISTER0" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. This field specifies the PHY to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. This field specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last." "0,1" group.byte 0x84++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERPHYSEL0,USER PHY SELECT REGISTER0" bitfld.long 0x0 0.--4. " PHYADR_MON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINT_ENABLE ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERACCESS1,USER ACCESS REGISTER1" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. This field specifies the PHY to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. This field specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last." "0,1" group.byte 0x8C++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERPHYSEL1,USER PHY SELECT REGISTER1" bitfld.long 0x0 0.--4. " PHYADR_MON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINT_ENABLE ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS1_IEP" base ad:0x4B22E000 width 29. group.byte 0x0++0x3 line.long 0x0 "PRUSS_IEP_GLOBAL_CFG,GLOBAL CFG" bitfld.long 0x0 0. " CNT_ENABLE ,Counter enable 0: Disables the counter. The counter maintains the current count. 1: Enables the counter." "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--7. " DEFAULT_INC ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 8.--19. 1. " CMP_INC ,Defines the increment value when compensation is active" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRUSS_IEP_GLOBAL_STATUS,STATUS" bitfld.long 0x0 0. " CNT_OVF ,Counter overflow status. 0: No overflow 1: Overflow occurred" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRUSS_IEP_COMPEN,COMPENSATION" hexmask.long.tbyte 0x0 0.--23. 1. " COMPEN_CNT ,Compensation counter. Read returns the current COMPEN_CNT value. 0: Compensation is disabled and counter will increment by DEFAULT_INC. n: Compensation is enabled until COMPEN_CNT decrements to 0. The COMPEN_CNT value decrements on every iep_clk cycle. When COMPEN_CNT is greater than 0, then count value increments by CMP_INC." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "PRUSS_IEP_COUNT,COUNTER" hexmask.long 0x0 0.--31. 1. " COUNT ,32-bit count value.t Increments by (DEFAULT_INC or CMP_INC) on every positive edge of PRUSS_IEP_CLK (200MHz) or PRUSS_GICLK." group.byte 0x10++0x3 line.long 0x0 "PRUSS_IEP_CAP_CFG,CAPTURE CFG" bitfld.long 0x0 0.--5. " CAP_1ST_EVENT_EN ,Capture 1-st Event Enable for n 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CAP6R_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[6] rise 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" textline " " bitfld.long 0x0 7. " CAP6F_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[6] fall 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" bitfld.long 0x0 8. " CAP7R_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[7] rise 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" textline " " bitfld.long 0x0 9. " CAP7F_1ST_EVENT_EN ,Capture 1st Event Enable for cap[7] fall 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" hexmask.long.byte 0x0 10.--17. 1. " CAP_ASYNC_EN ,Synchronization of the capture inputs to the PRUSS_IEP_CLK/PRUSS_GICLK enable. Note if input capture signal is asynchronous to PRUSS_IEP_CLK, enabling synchronization will cause the capture contents to be invalid. CAP_ASYNC_EN[n] maps to CAPR[n]. 0: Disable synchronization 1: Enable synchronization" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_IEP_CAP_STATUS,CAPTURE STATUS CFG" bitfld.long 0x0 0.--5. " CAPR_VALID ,Valid Status capr_valid<n> maps PRUSS_IEP_CAPR<n>_REG, where n=0 to 5, 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CAPR6_VALID ,Valid Status forPRUSS_IEP_CAPR6 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" textline " " bitfld.long 0x0 7. " CAPF6_VALID ,Valid Status forPRUSS_IEP_CAPF6 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" bitfld.long 0x0 8. " CAPR7_VALID ,Valid Status forPRUSS_IEP_CAPR7 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" textline " " bitfld.long 0x0 9. " CAPF7_VALID ,Valid Status forPRUSS_IEP_CAPF7 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" bitfld.long 0x0 10. " CAP_VALID ,Valid status for capture function. Reflects the ORed result from PRUSS_IEP_CAP_STATUS [9:0]. 0: No Hit for any capture event, i.e., there are all 0 in PRUSS_IEP_CAP_STATUS [9:0]. 1: Hit for 1 or more captures events is pending, i.e., there has at least one value equal to 1 in PRUSS_IEP_CAP_STATUS [9:0]." "0,1" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 16.--23. 1. " CAP_RAW ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]. 0: Current state is low for cap<n> 1: Current state is high for cap<n>" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_0,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_1,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x20++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_2,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x24++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_3,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x28++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_4,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_5,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x30++0x3 line.long 0x0 "PRUSS_IEP_CAPR6,CAPTURE RISE6" hexmask.long 0x0 0.--31. 1. " CAPR6 ,Capture Value for capr6 (rise) event" group.byte 0x34++0x3 line.long 0x0 "PRUSS_IEP_CAPF6,CAPTURE FALL6" hexmask.long 0x0 0.--31. 1. " CAPF6 ,Capture Value for capf6 (fall) event" group.byte 0x38++0x3 line.long 0x0 "PRUSS_IEP_CAPR7,CAPTURE RISE7" hexmask.long 0x0 0.--31. 1. " CAPR7 ,Capture Value for capr7 (rise) event" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_IEP_CAPF7,CAPTURE FALL7" hexmask.long 0x0 0.--31. 1. " CAPF7 ,Capture Value for capf7 (fall) event" group.byte 0x40++0x3 line.long 0x0 "PRUSS_IEP_CMP_CFG,COMPARE CFG" bitfld.long 0x0 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter 0: Disable 1: Enable the reset of the counter if a cmp0 event occurs" "0,1" hexmask.long.byte 0x0 1.--8. 1. " CMP_EN ,Enable bit for each of the compare registers cmp_en<n> =0: Disables CMP<n> Event cmp_en<n> =1: Enables CMP<n> Event cmp_en[0] maps to CMP0" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "PRUSS_IEP_CMP_STATUS,COMPARE STATUS" hexmask.long.byte 0x0 0.--7. 1. " CMP_HIT ,Status bit for each of the compare registers. 'Match' indicates the current counter is greater than or equal to the compare value. Note it is the firmware's responsibility to handle the IEP overflow. cmp_hit<n> = 0: No match has occured cmp_hit<n> = 1: A match occured. The associated hardware event signal will assert and remain high until the status is cleared." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "PRUSS_IEP_CMPj_0,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_IEP_CMPj_1,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x50++0x3 line.long 0x0 "PRUSS_IEP_CMPj_2,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x54++0x3 line.long 0x0 "PRUSS_IEP_CMPj_3,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x58++0x3 line.long 0x0 "PRUSS_IEP_CMPj_4,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_IEP_CMPj_5,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x60++0x3 line.long 0x0 "PRUSS_IEP_CMPj_6,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x64++0x3 line.long 0x0 "PRUSS_IEP_CMPj_7,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x80++0x3 line.long 0x0 "PRUSS_IEP_RXIPG0,RXIPG0This register can be used to determine the last RX IPG and the smallest RX IPG. RXIPG0 is the status for the RX port which is attached to PRU0." hexmask.long.word 0x0 0.--15. 1. " RX_IPG ,Records the current number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. Value is updated after RX_DV transitions from low to high. It will saturate at 0xffff." hexmask.long.word 0x0 16.--31. 1. " RX_MIN_IPG ,Defines the current minimum number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that is RXDV is sampled low. It stores the current smallest RX_IPG Read: The value can be read at any time. It gets updated after RX_IPG update if RX_MIN_IPG > RX_IPG. Write:Any write will reset this bitfield to 0xffff" group.byte 0x84++0x3 line.long 0x0 "PRUSS_IEP_RXIPG1,RXIPG1This register can be used to determine the last RX IPG and the smallest RX IPG. RXIPG1 is the status for the RX port which is attached to PRU1" hexmask.long.word 0x0 0.--15. 1. " RX_IPG ,Records the current number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. Value is updated after RX_DV transitions from low to high. It will saturate at 0xffff." hexmask.long.word 0x0 16.--31. 1. " RX_MIN_IPG ,Defines the current minimum number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. It stores the current smallest RX_IPG Read: The value can be read at any time. It gets updated after RX_IPG update if RX_MIN_IPG > RX_IPG. Write:Any write will reset this bitfield to 0xffff" group.byte 0x100++0x3 line.long 0x0 "PRUSS_IEP_SYNC_CTRL,SYNC CTRL" bitfld.long 0x0 0. " SYNC_EN ,SYNC generation enable 0: Disable the generation and clocking of SYNC0 and SYNC1 logic 1: Enables SYNC0 and SYNC1 generation" "0,1" bitfld.long 0x0 1. " SYNC0_EN ,SYNC0 generation enable 0: Disable SYNC0 generation 1: Enable SYNC0 generation" "0,1" textline " " bitfld.long 0x0 2. " SYNC1_EN ,SYNC1 generation enable 0: Disable SYNC1 generation 1: Enable SYNC1 generation" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " SYNC0_ACK_EN ,SYNC0 acknowledgement mode enable 0h: Disable, SYNC0 will go low after pulse width is met. 1: Enables acknowledge mode, when enabled SYNC0 will 1h: Enable, SYNC0 will remain asserted until receiving software acknowledges by reading PRUSS_IEP_SYNC0_STAT which clears on read." "0,1" bitfld.long 0x0 5. " SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable 0h: Disable, single shot mode 1h: Enable, cyclic generation mode" "0,1" textline " " bitfld.long 0x0 6. " SYNC1_ACK_EN ,SYNC1 acknowledgement mode enable 0h: Disable, SYNC1 will go low after pulse width is met. 1h: Enable, SYNC1 will remain asserted until receiving software acknowledges by reading PRUSS_IEP_SYNC1_ STAT which clears on read." "0,1" bitfld.long 0x0 7. " SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable 0: Disable, single shot mode 1:Enable, cyclic generation mode" "0,1" textline " " bitfld.long 0x0 8. " SYNC1_IND_EN ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0. 0: Dependent mode 1: Independent mode" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "PRUSS_IEP_SYNC_FIRST_STAT,SYNC CTRL" bitfld.long 0x0 0. " FIRST_SYNC0 ,SYNC0 First Event status 0: SYNC0 first event has not occurred 1: SYNC0 first event has occurred. This bits is cleared when sync0_en = 0" "0,1" bitfld.long 0x0 1. " FIRST_SYNC1 ,SYNC1 First Event status 0: SYNC1 first event has not occurred 1: SYNC1 first event has occurred. This bits is cleared when sync1_en = 0" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "PRUSS_IEP_SYNC0_STAT,SYNC CTRL" bitfld.long 0x0 0. " SYNC0_PEND ,SYNC0 pending state 0: SYNC0 is not pending 1 SYNC0 is pending or has occurred when SYNC0_ACK_EN = 0 (Disable). Write '1' to clear" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "PRUSS_IEP_SYNC1_STAT,SYNC CTRL" bitfld.long 0x0 0. " SYNC1_PEND ,SYNC1 pending state 0: SYNC1 is not pending 1 SYNC1 is pending or has occurred when SYNC1_ACK_EN = 0 (Disable). Write '1' to Clear" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "PRUSS_IEP_SYNC_PWIDTH,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC_HPW ,Defines the number of clock cycles SYNC0/1 will be high. Note if SYNC0/1 is disabled during pulse width time (that is, SYNC_CTRL[SYNC0_EN | SYNC1_EN | SYNC_EN] = 0), the ongoing pulse will be terminated. 0h: 1 clock cycle. 1h: 2 clock cycles. Nh: N+1 clock cycles." group.byte 0x114++0x3 line.long 0x0 "PRUSS_IEP_SYNC0_PERIOD,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC0_PERIOD ,Defines the period between the rising edges of SYNC0. 0x0: Reserved 0x1: 2 clk cycles period N: N+1 clk cycles period" group.byte 0x118++0x3 line.long 0x0 "PRUSS_IEP_SYNC1_DELAY,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC1_DELAY ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1. Note this is the delay before the start of SYNC1. 0h: No delay 1h: 1 clock cycle delay. Nh: N clock cycles delay. When SYNC1_IND_EN = 1, defines the period between the rising edges of SYNC1. 0h: Reserved. 1h: 2 clock cycles period. Nh: N+1 clock cycles period." group.byte 0x11C++0x3 line.long 0x0 "PRUSS_IEP_SYNC_START,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC_START ,Defines the start time after the activation event. 0h: 1 clock cycle delay. Nh: N+1 clock cycles delay." group.byte 0x200++0x3 line.long 0x0 "PRUSS_IEP_WD_PREDIV,WD" hexmask.long.word 0x0 0.--15. 1. " PRE_DIV ,Defines the number of iep_clk cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if iep_clk is 200 MHz. seconds/(WD event) = (clock cycles per WD event)/(clock cycles per second) = 20000/(200 x [10]^6 ) = 100 us" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x204++0x3 line.long 0x0 "PRUSS_IEP_PDI_WD_TIM,WD" hexmask.long.word 0x0 0.--15. 1. " PDI_WD_TIME ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRE_DIV is set to 100 us, then the value 0x03e8 (or 1000) provides a rate of 100ms. Read returns the current count. Counter is reset by software write to register or when Digital Data In capture occurs. WD is disabled if WD time is set to 0x0. Note when an expiration event occurs, the expiration counter (PDI_EXP_CNT) increments and status (PDI_WD_STAT) clears." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "PRUSS_IEP_PD_WD_TIM,WD" hexmask.long.word 0x0 0.--15. 1. " PD_WD_TIME ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRE_DIV is set to 100 us, then 0x03e8 (or 1000) provides a rate of 100ms Read returns the current count. Counter is reset by software write to register or every write access to Sync Managers with WD trigger enable bit set. WD is disabled if WD time is set to 0x0. Expiration actions: Increment expiration counter, clear status. Digital Data out forced to zero if pr1_edio_oe_ext = 1 and PRUSS_IEP_DIGIO_EXT.SW_DATA_OUT_UPDATE = 0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "PRUSS_IEP_WD_STATUS,WD" bitfld.long 0x0 0. " PD_WD_STAT ,WD PD status (triggered by Sync Mangers status). 0h: Expired (PD_WD_EXP event generated) 1h: Active or disabled" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " PDI_WD_STAT ,WD PDI status. 0h: Expired (PDI_WD_EXP event generated) 1h: Active or disabled" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "PRUSS_IEP_WD_EXP_CNT,WD" hexmask.long.byte 0x0 0.--7. 1. " PDI_EXP_CNT ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh." hexmask.long.byte 0x0 8.--15. 1. " PD_EXP_CNT ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "PRUSS_IEP_WD_CTRL,WD" bitfld.long 0x0 0. " PD_WD_EN ,Watchdog PD 0: Disable 1: Enable" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " PDI_WD_EN ,Watchdog PDI 0: Disable 1: Enable" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x300++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_CTRL,DIGIO" bitfld.long 0x0 0. " OUTVALID_POL ,Indicates OUTVALID polarity" "0,1" bitfld.long 0x0 1. " OUTVALID_MODE ,Defines OUTVALID mode" "0,1" textline " " bitfld.long 0x0 2. " BIDI_MODE ,Indicates the digital input/output direction. DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1" bitfld.long 0x0 3. " WD_MODE ,Defines Watchdog behavior" "0,1" textline " " bitfld.long 0x0 4.--5. " IN_MODE ,Defines event that triggers data in to be sampled 0b00: PRU0/1_RX_SOF 0b01: Rising edge of external pr<k>_edio_latch_in signal 0b10: DC rising edge of SYNC0 event 0b11: DC rising edge of SYNC1 event" "0,1,2,3" bitfld.long 0x0 6.--7. " OUT_MODE ,Defines event that triggers data out to be updated." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x308++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_IN,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_IN ,Data input. Digital inputs can be configured to be sampled in four ways. 1: Digital inputs are sampled at the start of each frame. The SOF signal can be used externally to update the input data, because the SOF is signaled before input data is sampled. 2: The sample time can be controlled externally by using the pr1_edio_latch_in signal. 3: Digital inputs are sampled at SYNC0 events. 4: Digital inputs are sampled at SYNC1 events. These can be configured by PRUSS_IEP_DIGIO_CTRL[5:4] IN_MODE. Only [7:0] are exported to device pins in this device." group.byte 0x30C++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_IN_RAW,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_IN_RAW ,Raw Data Input. Direct sample of EDIO_DATA_IN[31:0]. Only [7:0] are exported to device pins in this device." group.byte 0x310++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_OUT,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_OUT ,Data output. Digital outputs can be configured to be updated in four ways. 1: Digital outputs are updated at the end of each frame (EOF mode). 2: Digital outputs are updated with SYNC0 events 3: Digital outputs are updated SYNC1events. 4: Digital outputs are updated at the end of a frame which triggered the Process Data Watchdog. Digital Outputs are only updated if the frame was correct (WD_TRIG mode). These can be configured by out_mode." group.byte 0x314++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_OUT_EN,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_OUT_EN ,Enables tri-state control for pr<k>_edio_data_out[7:0]." group.byte 0x318++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_EXP,DIGIO" bitfld.long 0x0 0. " SW_DATA_OUT_UPDATE ,Defines the value of pr1_edio_data_out when OUTVALID_OVR_EN = 1. Read 1: Start bit event occurred Read 0: Start bit event has not occurred Write 1: pr1_edio_data_out by software data out. Write 0: No Effect" "0,1" bitfld.long 0x0 1. " OUTVALID_OVR_EN ,Enable software to control value of pr<k>_edio_data_out [7:0]. 0: Disable 1: Enable" "0,1" textline " " bitfld.long 0x0 2. " SW_OUTVALID ,pr1_edio_outvalid = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--7. " OUTVALID_DLY ,Define the number of iep_clk (PRUSS_IEP_CLK) cycle delay on assertion of PR1_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " SOF_DLY ,Define the number of iep_clk (PRUSS_IEP_CLK) cycle delay of SOF PR1_EDIO_DATA_IN[31:0] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12. " SOF_SEL ,Defines with RX_SOF is used for PR1_EDIO_DATA_IN[31:0] capture" "0,1" bitfld.long 0x0 13. " EOF_SEL ,Defines with RX_EOF is used for PR1_EDIO_DATA_IN[31:0] capture" "0,1" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS2_IEP" base ad:0x4B2AE000 width 29. group.byte 0x0++0x3 line.long 0x0 "PRUSS_IEP_GLOBAL_CFG,GLOBAL CFG" bitfld.long 0x0 0. " CNT_ENABLE ,Counter enable 0: Disables the counter. The counter maintains the current count. 1: Enables the counter." "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--7. " DEFAULT_INC ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 8.--19. 1. " CMP_INC ,Defines the increment value when compensation is active" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRUSS_IEP_GLOBAL_STATUS,STATUS" bitfld.long 0x0 0. " CNT_OVF ,Counter overflow status. 0: No overflow 1: Overflow occurred" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRUSS_IEP_COMPEN,COMPENSATION" hexmask.long.tbyte 0x0 0.--23. 1. " COMPEN_CNT ,Compensation counter. Read returns the current COMPEN_CNT value. 0: Compensation is disabled and counter will increment by DEFAULT_INC. n: Compensation is enabled until COMPEN_CNT decrements to 0. The COMPEN_CNT value decrements on every iep_clk cycle. When COMPEN_CNT is greater than 0, then count value increments by CMP_INC." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "PRUSS_IEP_COUNT,COUNTER" hexmask.long 0x0 0.--31. 1. " COUNT ,32-bit count value.t Increments by (DEFAULT_INC or CMP_INC) on every positive edge of PRUSS_IEP_CLK (200MHz) or PRUSS_GICLK." group.byte 0x10++0x3 line.long 0x0 "PRUSS_IEP_CAP_CFG,CAPTURE CFG" bitfld.long 0x0 0.--5. " CAP_1ST_EVENT_EN ,Capture 1-st Event Enable for n 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CAP6R_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[6] rise 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" textline " " bitfld.long 0x0 7. " CAP6F_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[6] fall 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" bitfld.long 0x0 8. " CAP7R_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[7] rise 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" textline " " bitfld.long 0x0 9. " CAP7F_1ST_EVENT_EN ,Capture 1st Event Enable for cap[7] fall 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" hexmask.long.byte 0x0 10.--17. 1. " CAP_ASYNC_EN ,Synchronization of the capture inputs to the PRUSS_IEP_CLK/PRUSS_GICLK enable. Note if input capture signal is asynchronous to PRUSS_IEP_CLK, enabling synchronization will cause the capture contents to be invalid. CAP_ASYNC_EN[n] maps to CAPR[n]. 0: Disable synchronization 1: Enable synchronization" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_IEP_CAP_STATUS,CAPTURE STATUS CFG" bitfld.long 0x0 0.--5. " CAPR_VALID ,Valid Status capr_valid<n> maps PRUSS_IEP_CAPR<n>_REG, where n=0 to 5, 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CAPR6_VALID ,Valid Status forPRUSS_IEP_CAPR6 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" textline " " bitfld.long 0x0 7. " CAPF6_VALID ,Valid Status forPRUSS_IEP_CAPF6 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" bitfld.long 0x0 8. " CAPR7_VALID ,Valid Status forPRUSS_IEP_CAPR7 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" textline " " bitfld.long 0x0 9. " CAPF7_VALID ,Valid Status forPRUSS_IEP_CAPF7 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" bitfld.long 0x0 10. " CAP_VALID ,Valid status for capture function. Reflects the ORed result from PRUSS_IEP_CAP_STATUS [9:0]. 0: No Hit for any capture event, i.e., there are all 0 in PRUSS_IEP_CAP_STATUS [9:0]. 1: Hit for 1 or more captures events is pending, i.e., there has at least one value equal to 1 in PRUSS_IEP_CAP_STATUS [9:0]." "0,1" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 16.--23. 1. " CAP_RAW ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]. 0: Current state is low for cap<n> 1: Current state is high for cap<n>" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_0,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_1,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x20++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_2,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x24++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_3,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x28++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_4,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_5,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x30++0x3 line.long 0x0 "PRUSS_IEP_CAPR6,CAPTURE RISE6" hexmask.long 0x0 0.--31. 1. " CAPR6 ,Capture Value for capr6 (rise) event" group.byte 0x34++0x3 line.long 0x0 "PRUSS_IEP_CAPF6,CAPTURE FALL6" hexmask.long 0x0 0.--31. 1. " CAPF6 ,Capture Value for capf6 (fall) event" group.byte 0x38++0x3 line.long 0x0 "PRUSS_IEP_CAPR7,CAPTURE RISE7" hexmask.long 0x0 0.--31. 1. " CAPR7 ,Capture Value for capr7 (rise) event" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_IEP_CAPF7,CAPTURE FALL7" hexmask.long 0x0 0.--31. 1. " CAPF7 ,Capture Value for capf7 (fall) event" group.byte 0x40++0x3 line.long 0x0 "PRUSS_IEP_CMP_CFG,COMPARE CFG" bitfld.long 0x0 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter 0: Disable 1: Enable the reset of the counter if a cmp0 event occurs" "0,1" hexmask.long.byte 0x0 1.--8. 1. " CMP_EN ,Enable bit for each of the compare registers cmp_en<n> =0: Disables CMP<n> Event cmp_en<n> =1: Enables CMP<n> Event cmp_en[0] maps to CMP0" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "PRUSS_IEP_CMP_STATUS,COMPARE STATUS" hexmask.long.byte 0x0 0.--7. 1. " CMP_HIT ,Status bit for each of the compare registers. 'Match' indicates the current counter is greater than or equal to the compare value. Note it is the firmware's responsibility to handle the IEP overflow. cmp_hit<n> = 0: No match has occured cmp_hit<n> = 1: A match occured. The associated hardware event signal will assert and remain high until the status is cleared." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "PRUSS_IEP_CMPj_0,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_IEP_CMPj_1,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x50++0x3 line.long 0x0 "PRUSS_IEP_CMPj_2,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x54++0x3 line.long 0x0 "PRUSS_IEP_CMPj_3,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x58++0x3 line.long 0x0 "PRUSS_IEP_CMPj_4,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_IEP_CMPj_5,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x60++0x3 line.long 0x0 "PRUSS_IEP_CMPj_6,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x64++0x3 line.long 0x0 "PRUSS_IEP_CMPj_7,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x80++0x3 line.long 0x0 "PRUSS_IEP_RXIPG0,RXIPG0This register can be used to determine the last RX IPG and the smallest RX IPG. RXIPG0 is the status for the RX port which is attached to PRU0." hexmask.long.word 0x0 0.--15. 1. " RX_IPG ,Records the current number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. Value is updated after RX_DV transitions from low to high. It will saturate at 0xffff." hexmask.long.word 0x0 16.--31. 1. " RX_MIN_IPG ,Defines the current minimum number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that is RXDV is sampled low. It stores the current smallest RX_IPG Read: The value can be read at any time. It gets updated after RX_IPG update if RX_MIN_IPG > RX_IPG. Write:Any write will reset this bitfield to 0xffff" group.byte 0x84++0x3 line.long 0x0 "PRUSS_IEP_RXIPG1,RXIPG1This register can be used to determine the last RX IPG and the smallest RX IPG. RXIPG1 is the status for the RX port which is attached to PRU1" hexmask.long.word 0x0 0.--15. 1. " RX_IPG ,Records the current number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. Value is updated after RX_DV transitions from low to high. It will saturate at 0xffff." hexmask.long.word 0x0 16.--31. 1. " RX_MIN_IPG ,Defines the current minimum number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. It stores the current smallest RX_IPG Read: The value can be read at any time. It gets updated after RX_IPG update if RX_MIN_IPG > RX_IPG. Write:Any write will reset this bitfield to 0xffff" group.byte 0x100++0x3 line.long 0x0 "PRUSS_IEP_SYNC_CTRL,SYNC CTRL" bitfld.long 0x0 0. " SYNC_EN ,SYNC generation enable 0: Disable the generation and clocking of SYNC0 and SYNC1 logic 1: Enables SYNC0 and SYNC1 generation" "0,1" bitfld.long 0x0 1. " SYNC0_EN ,SYNC0 generation enable 0: Disable SYNC0 generation 1: Enable SYNC0 generation" "0,1" textline " " bitfld.long 0x0 2. " SYNC1_EN ,SYNC1 generation enable 0: Disable SYNC1 generation 1: Enable SYNC1 generation" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " SYNC0_ACK_EN ,SYNC0 acknowledgement mode enable 0h: Disable, SYNC0 will go low after pulse width is met. 1: Enables acknowledge mode, when enabled SYNC0 will 1h: Enable, SYNC0 will remain asserted until receiving software acknowledges by reading PRUSS_IEP_SYNC0_STAT which clears on read." "0,1" bitfld.long 0x0 5. " SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable 0h: Disable, single shot mode 1h: Enable, cyclic generation mode" "0,1" textline " " bitfld.long 0x0 6. " SYNC1_ACK_EN ,SYNC1 acknowledgement mode enable 0h: Disable, SYNC1 will go low after pulse width is met. 1h: Enable, SYNC1 will remain asserted until receiving software acknowledges by reading PRUSS_IEP_SYNC1_ STAT which clears on read." "0,1" bitfld.long 0x0 7. " SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable 0: Disable, single shot mode 1:Enable, cyclic generation mode" "0,1" textline " " bitfld.long 0x0 8. " SYNC1_IND_EN ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0. 0: Dependent mode 1: Independent mode" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "PRUSS_IEP_SYNC_FIRST_STAT,SYNC CTRL" bitfld.long 0x0 0. " FIRST_SYNC0 ,SYNC0 First Event status 0: SYNC0 first event has not occurred 1: SYNC0 first event has occurred. This bits is cleared when sync0_en = 0" "0,1" bitfld.long 0x0 1. " FIRST_SYNC1 ,SYNC1 First Event status 0: SYNC1 first event has not occurred 1: SYNC1 first event has occurred. This bits is cleared when sync1_en = 0" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "PRUSS_IEP_SYNC0_STAT,SYNC CTRL" bitfld.long 0x0 0. " SYNC0_PEND ,SYNC0 pending state 0: SYNC0 is not pending 1 SYNC0 is pending or has occurred when SYNC0_ACK_EN = 0 (Disable). Write '1' to clear" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "PRUSS_IEP_SYNC1_STAT,SYNC CTRL" bitfld.long 0x0 0. " SYNC1_PEND ,SYNC1 pending state 0: SYNC1 is not pending 1 SYNC1 is pending or has occurred when SYNC1_ACK_EN = 0 (Disable). Write '1' to Clear" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "PRUSS_IEP_SYNC_PWIDTH,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC_HPW ,Defines the number of clock cycles SYNC0/1 will be high. Note if SYNC0/1 is disabled during pulse width time (that is, SYNC_CTRL[SYNC0_EN | SYNC1_EN | SYNC_EN] = 0), the ongoing pulse will be terminated. 0h: 1 clock cycle. 1h: 2 clock cycles. Nh: N+1 clock cycles." group.byte 0x114++0x3 line.long 0x0 "PRUSS_IEP_SYNC0_PERIOD,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC0_PERIOD ,Defines the period between the rising edges of SYNC0. 0x0: Reserved 0x1: 2 clk cycles period N: N+1 clk cycles period" group.byte 0x118++0x3 line.long 0x0 "PRUSS_IEP_SYNC1_DELAY,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC1_DELAY ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1. Note this is the delay before the start of SYNC1. 0h: No delay 1h: 1 clock cycle delay. Nh: N clock cycles delay. When SYNC1_IND_EN = 1, defines the period between the rising edges of SYNC1. 0h: Reserved. 1h: 2 clock cycles period. Nh: N+1 clock cycles period." group.byte 0x11C++0x3 line.long 0x0 "PRUSS_IEP_SYNC_START,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC_START ,Defines the start time after the activation event. 0h: 1 clock cycle delay. Nh: N+1 clock cycles delay." group.byte 0x200++0x3 line.long 0x0 "PRUSS_IEP_WD_PREDIV,WD" hexmask.long.word 0x0 0.--15. 1. " PRE_DIV ,Defines the number of iep_clk cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if iep_clk is 200 MHz. seconds/(WD event) = (clock cycles per WD event)/(clock cycles per second) = 20000/(200 x [10]^6 ) = 100 us" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x204++0x3 line.long 0x0 "PRUSS_IEP_PDI_WD_TIM,WD" hexmask.long.word 0x0 0.--15. 1. " PDI_WD_TIME ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRE_DIV is set to 100 us, then the value 0x03e8 (or 1000) provides a rate of 100ms. Read returns the current count. Counter is reset by software write to register or when Digital Data In capture occurs. WD is disabled if WD time is set to 0x0. Note when an expiration event occurs, the expiration counter (PDI_EXP_CNT) increments and status (PDI_WD_STAT) clears." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "PRUSS_IEP_PD_WD_TIM,WD" hexmask.long.word 0x0 0.--15. 1. " PD_WD_TIME ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRE_DIV is set to 100 us, then 0x03e8 (or 1000) provides a rate of 100ms Read returns the current count. Counter is reset by software write to register or every write access to Sync Managers with WD trigger enable bit set. WD is disabled if WD time is set to 0x0. Expiration actions: Increment expiration counter, clear status. Digital Data out forced to zero if pr1_edio_oe_ext = 1 and PRUSS_IEP_DIGIO_EXT.SW_DATA_OUT_UPDATE = 0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "PRUSS_IEP_WD_STATUS,WD" bitfld.long 0x0 0. " PD_WD_STAT ,WD PD status (triggered by Sync Mangers status). 0h: Expired (PD_WD_EXP event generated) 1h: Active or disabled" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " PDI_WD_STAT ,WD PDI status. 0h: Expired (PDI_WD_EXP event generated) 1h: Active or disabled" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "PRUSS_IEP_WD_EXP_CNT,WD" hexmask.long.byte 0x0 0.--7. 1. " PDI_EXP_CNT ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh." hexmask.long.byte 0x0 8.--15. 1. " PD_EXP_CNT ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "PRUSS_IEP_WD_CTRL,WD" bitfld.long 0x0 0. " PD_WD_EN ,Watchdog PD 0: Disable 1: Enable" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " PDI_WD_EN ,Watchdog PDI 0: Disable 1: Enable" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x300++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_CTRL,DIGIO" bitfld.long 0x0 0. " OUTVALID_POL ,Indicates OUTVALID polarity" "0,1" bitfld.long 0x0 1. " OUTVALID_MODE ,Defines OUTVALID mode" "0,1" textline " " bitfld.long 0x0 2. " BIDI_MODE ,Indicates the digital input/output direction. DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1" bitfld.long 0x0 3. " WD_MODE ,Defines Watchdog behavior" "0,1" textline " " bitfld.long 0x0 4.--5. " IN_MODE ,Defines event that triggers data in to be sampled 0b00: PRU0/1_RX_SOF 0b01: Rising edge of external pr<k>_edio_latch_in signal 0b10: DC rising edge of SYNC0 event 0b11: DC rising edge of SYNC1 event" "0,1,2,3" bitfld.long 0x0 6.--7. " OUT_MODE ,Defines event that triggers data out to be updated." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x308++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_IN,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_IN ,Data input. Digital inputs can be configured to be sampled in four ways. 1: Digital inputs are sampled at the start of each frame. The SOF signal can be used externally to update the input data, because the SOF is signaled before input data is sampled. 2: The sample time can be controlled externally by using the pr1_edio_latch_in signal. 3: Digital inputs are sampled at SYNC0 events. 4: Digital inputs are sampled at SYNC1 events. These can be configured by PRUSS_IEP_DIGIO_CTRL[5:4] IN_MODE. Only [7:0] are exported to device pins in this device." group.byte 0x30C++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_IN_RAW,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_IN_RAW ,Raw Data Input. Direct sample of EDIO_DATA_IN[31:0]. Only [7:0] are exported to device pins in this device." group.byte 0x310++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_OUT,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_OUT ,Data output. Digital outputs can be configured to be updated in four ways. 1: Digital outputs are updated at the end of each frame (EOF mode). 2: Digital outputs are updated with SYNC0 events 3: Digital outputs are updated SYNC1events. 4: Digital outputs are updated at the end of a frame which triggered the Process Data Watchdog. Digital Outputs are only updated if the frame was correct (WD_TRIG mode). These can be configured by out_mode." group.byte 0x314++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_OUT_EN,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_OUT_EN ,Enables tri-state control for pr<k>_edio_data_out[7:0]." group.byte 0x318++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_EXP,DIGIO" bitfld.long 0x0 0. " SW_DATA_OUT_UPDATE ,Defines the value of pr1_edio_data_out when OUTVALID_OVR_EN = 1. Read 1: Start bit event occurred Read 0: Start bit event has not occurred Write 1: pr1_edio_data_out by software data out. Write 0: No Effect" "0,1" bitfld.long 0x0 1. " OUTVALID_OVR_EN ,Enable software to control value of pr<k>_edio_data_out [7:0]. 0: Disable 1: Enable" "0,1" textline " " bitfld.long 0x0 2. " SW_OUTVALID ,pr1_edio_outvalid = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--7. " OUTVALID_DLY ,Define the number of iep_clk (PRUSS_IEP_CLK) cycle delay on assertion of PR1_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " SOF_DLY ,Define the number of iep_clk (PRUSS_IEP_CLK) cycle delay of SOF PR1_EDIO_DATA_IN[31:0] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12. " SOF_SEL ,Defines with RX_SOF is used for PR1_EDIO_DATA_IN[31:0] capture" "0,1" bitfld.long 0x0 13. " EOF_SEL ,Defines with RX_EOF is used for PR1_EDIO_DATA_IN[31:0] capture" "0,1" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS1_PRU0_DEBUG" base ad:0x20AA2400 width 20. group.byte 0x0++0x3 line.long 0x0 "PRUSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4++0x3 line.long 0x0 "PRUSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x8++0x3 line.long 0x0 "PRUSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0xC++0x3 line.long 0x0 "PRUSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x10++0x3 line.long 0x0 "PRUSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x14++0x3 line.long 0x0 "PRUSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x18++0x3 line.long 0x0 "PRUSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x20++0x3 line.long 0x0 "PRUSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x24++0x3 line.long 0x0 "PRUSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x28++0x3 line.long 0x0 "PRUSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x30++0x3 line.long 0x0 "PRUSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x34++0x3 line.long 0x0 "PRUSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x38++0x3 line.long 0x0 "PRUSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x40++0x3 line.long 0x0 "PRUSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x44++0x3 line.long 0x0 "PRUSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x48++0x3 line.long 0x0 "PRUSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x50++0x3 line.long 0x0 "PRUSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x54++0x3 line.long 0x0 "PRUSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x58++0x3 line.long 0x0 "PRUSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x60++0x3 line.long 0x0 "PRUSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x64++0x3 line.long 0x0 "PRUSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x68++0x3 line.long 0x0 "PRUSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x6C++0x3 line.long 0x0 "PRUSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x70++0x3 line.long 0x0 "PRUSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x74++0x3 line.long 0x0 "PRUSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x78++0x3 line.long 0x0 "PRUSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x7C++0x3 line.long 0x0 "PRUSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG31 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x80++0x3 line.long 0x0 "PRUSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x84++0x3 line.long 0x0 "PRUSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x88++0x3 line.long 0x0 "PRUSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x8C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x90++0x3 line.long 0x0 "PRUSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x94++0x3 line.long 0x0 "PRUSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x98++0x3 line.long 0x0 "PRUSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x9C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xAC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xBC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xCC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xDC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xE0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c24_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00000n00, n=c24_blk_index[3:0]." group.byte 0xE4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c25_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00002n00, n=c25_blk_index[3:0]." group.byte 0xE8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c26_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x0002En00, n=c26_blk_index[3:0]." group.byte 0xEC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c27_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00032n00, n=c27_blk_index[3:0]." group.byte 0xF0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c28_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x00nnnn00, nnnn=c28_pointer[15:0]." group.byte 0xF4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c29_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x49nnnn00, nnnn=c29_pointer[15:0]." group.byte 0xF8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c30_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x40nnnn00, nnnn=c30_pointer[15:0]." group.byte 0xFC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c31_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x80nnnn00, nnnn=c31_pointer[15:0]." width 0x0B tree.end tree "PRUSS1_PRU1_DEBUG" base ad:0x20AA4400 width 20. group.byte 0x0++0x3 line.long 0x0 "PRUSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4++0x3 line.long 0x0 "PRUSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x8++0x3 line.long 0x0 "PRUSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0xC++0x3 line.long 0x0 "PRUSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x10++0x3 line.long 0x0 "PRUSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x14++0x3 line.long 0x0 "PRUSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x18++0x3 line.long 0x0 "PRUSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x20++0x3 line.long 0x0 "PRUSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x24++0x3 line.long 0x0 "PRUSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x28++0x3 line.long 0x0 "PRUSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x30++0x3 line.long 0x0 "PRUSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x34++0x3 line.long 0x0 "PRUSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x38++0x3 line.long 0x0 "PRUSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x40++0x3 line.long 0x0 "PRUSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x44++0x3 line.long 0x0 "PRUSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x48++0x3 line.long 0x0 "PRUSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x50++0x3 line.long 0x0 "PRUSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x54++0x3 line.long 0x0 "PRUSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x58++0x3 line.long 0x0 "PRUSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x60++0x3 line.long 0x0 "PRUSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x64++0x3 line.long 0x0 "PRUSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x68++0x3 line.long 0x0 "PRUSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x6C++0x3 line.long 0x0 "PRUSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x70++0x3 line.long 0x0 "PRUSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x74++0x3 line.long 0x0 "PRUSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x78++0x3 line.long 0x0 "PRUSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x7C++0x3 line.long 0x0 "PRUSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG31 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x80++0x3 line.long 0x0 "PRUSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x84++0x3 line.long 0x0 "PRUSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x88++0x3 line.long 0x0 "PRUSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x8C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x90++0x3 line.long 0x0 "PRUSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x94++0x3 line.long 0x0 "PRUSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x98++0x3 line.long 0x0 "PRUSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x9C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xAC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xBC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xCC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xDC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xE0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c24_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00000n00, n=c24_blk_index[3:0]." group.byte 0xE4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c25_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00002n00, n=c25_blk_index[3:0]." group.byte 0xE8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c26_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x0002En00, n=c26_blk_index[3:0]." group.byte 0xEC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c27_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00032n00, n=c27_blk_index[3:0]." group.byte 0xF0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c28_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x00nnnn00, nnnn=c28_pointer[15:0]." group.byte 0xF4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c29_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x49nnnn00, nnnn=c29_pointer[15:0]." group.byte 0xF8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c30_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x40nnnn00, nnnn=c30_pointer[15:0]." group.byte 0xFC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c31_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x80nnnn00, nnnn=c31_pointer[15:0]." width 0x0B tree.end tree "PRUSS2_PRU0_DEBUG" base ad:0x20AE2400 width 20. group.byte 0x0++0x3 line.long 0x0 "PRUSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4++0x3 line.long 0x0 "PRUSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x8++0x3 line.long 0x0 "PRUSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0xC++0x3 line.long 0x0 "PRUSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x10++0x3 line.long 0x0 "PRUSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x14++0x3 line.long 0x0 "PRUSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x18++0x3 line.long 0x0 "PRUSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x20++0x3 line.long 0x0 "PRUSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x24++0x3 line.long 0x0 "PRUSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x28++0x3 line.long 0x0 "PRUSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x30++0x3 line.long 0x0 "PRUSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x34++0x3 line.long 0x0 "PRUSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x38++0x3 line.long 0x0 "PRUSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x40++0x3 line.long 0x0 "PRUSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x44++0x3 line.long 0x0 "PRUSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x48++0x3 line.long 0x0 "PRUSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x50++0x3 line.long 0x0 "PRUSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x54++0x3 line.long 0x0 "PRUSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x58++0x3 line.long 0x0 "PRUSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x60++0x3 line.long 0x0 "PRUSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x64++0x3 line.long 0x0 "PRUSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x68++0x3 line.long 0x0 "PRUSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x6C++0x3 line.long 0x0 "PRUSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x70++0x3 line.long 0x0 "PRUSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x74++0x3 line.long 0x0 "PRUSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x78++0x3 line.long 0x0 "PRUSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x7C++0x3 line.long 0x0 "PRUSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG31 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x80++0x3 line.long 0x0 "PRUSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x84++0x3 line.long 0x0 "PRUSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x88++0x3 line.long 0x0 "PRUSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x8C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x90++0x3 line.long 0x0 "PRUSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x94++0x3 line.long 0x0 "PRUSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x98++0x3 line.long 0x0 "PRUSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x9C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xAC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xBC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xCC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xDC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xE0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c24_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00000n00, n=c24_blk_index[3:0]." group.byte 0xE4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c25_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00002n00, n=c25_blk_index[3:0]." group.byte 0xE8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c26_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x0002En00, n=c26_blk_index[3:0]." group.byte 0xEC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c27_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00032n00, n=c27_blk_index[3:0]." group.byte 0xF0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c28_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x00nnnn00, nnnn=c28_pointer[15:0]." group.byte 0xF4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c29_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x49nnnn00, nnnn=c29_pointer[15:0]." group.byte 0xF8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c30_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x40nnnn00, nnnn=c30_pointer[15:0]." group.byte 0xFC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c31_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x80nnnn00, nnnn=c31_pointer[15:0]." width 0x0B tree.end tree "PRUSS2_PRU1_DEBUG" base ad:0x20AE4400 width 20. group.byte 0x0++0x3 line.long 0x0 "PRUSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4++0x3 line.long 0x0 "PRUSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x8++0x3 line.long 0x0 "PRUSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0xC++0x3 line.long 0x0 "PRUSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x10++0x3 line.long 0x0 "PRUSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x14++0x3 line.long 0x0 "PRUSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x18++0x3 line.long 0x0 "PRUSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x20++0x3 line.long 0x0 "PRUSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x24++0x3 line.long 0x0 "PRUSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x28++0x3 line.long 0x0 "PRUSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x30++0x3 line.long 0x0 "PRUSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x34++0x3 line.long 0x0 "PRUSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x38++0x3 line.long 0x0 "PRUSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x40++0x3 line.long 0x0 "PRUSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x44++0x3 line.long 0x0 "PRUSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x48++0x3 line.long 0x0 "PRUSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x50++0x3 line.long 0x0 "PRUSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x54++0x3 line.long 0x0 "PRUSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x58++0x3 line.long 0x0 "PRUSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x60++0x3 line.long 0x0 "PRUSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x64++0x3 line.long 0x0 "PRUSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x68++0x3 line.long 0x0 "PRUSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x6C++0x3 line.long 0x0 "PRUSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x70++0x3 line.long 0x0 "PRUSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x74++0x3 line.long 0x0 "PRUSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x78++0x3 line.long 0x0 "PRUSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x7C++0x3 line.long 0x0 "PRUSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG31 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x80++0x3 line.long 0x0 "PRUSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x84++0x3 line.long 0x0 "PRUSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x88++0x3 line.long 0x0 "PRUSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x8C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x90++0x3 line.long 0x0 "PRUSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x94++0x3 line.long 0x0 "PRUSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x98++0x3 line.long 0x0 "PRUSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x9C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xAC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xBC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xCC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xDC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xE0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c24_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00000n00, n=c24_blk_index[3:0]." group.byte 0xE4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c25_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00002n00, n=c25_blk_index[3:0]." group.byte 0xE8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c26_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x0002En00, n=c26_blk_index[3:0]." group.byte 0xEC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c27_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00032n00, n=c27_blk_index[3:0]." group.byte 0xF0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c28_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x00nnnn00, nnnn=c28_pointer[15:0]." group.byte 0xF4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c29_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x49nnnn00, nnnn=c29_pointer[15:0]." group.byte 0xF8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c30_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x40nnnn00, nnnn=c30_pointer[15:0]." group.byte 0xFC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c31_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x80nnnn00, nnnn=c31_pointer[15:0]." width 0x0B tree.end tree "PRUSS_CFG" base ad:0x00026000 width 14. group.byte 0x0++0x3 line.long 0x0 "PRUSS_REVID,The Revision Register contains the ID and revision information." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "PRUSS_SYSCFG,The System Configuration Register defines the power IDLE and STANDBY modes." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0 = Force-idle mode 0x1 = No-idle mode 0x2 = Smart-idle mode 0x3 = Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " STANDBY_MODE ,0x0 = Force standby mode: Initiator unconditionally in standby (standby = 1) 0x1 = No standby mode: Initiator unconditionally out of standby (standby = 0) 0x2 = Smart standby mode: Standby requested by initiator depending on internal conditions 0x3 = Reserved" "0,1,2,3" textline " " bitfld.long 0x0 4. " STANDBY_INIT ,0x1 = Initiate standby sequence. 0x0 = Enable OCP master ports." "0,1" bitfld.long 0x0 5. " SUB_MWAIT ,Status bit for wait state. 0x0 = Ready for Transaction 0x1 = Wait until 0" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRUSS_GPCFG0,The General Purpose Configuration 0 Register defines the GPIO configuration for PRU0." bitfld.long 0x0 0.--1. " PRU0_GPI_MODE ,0x0 = Direct input mode 0x1 = 16-bit parallel capture mode 0x2 = 28-bit shift mode 0x3 = MII_RT mode" "0,1,2,3" bitfld.long 0x0 2. " PRU0_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0x0 = Use the positive edge of pru0_r31_status[16] 0x1 = Use the negative edge of pru0_r31_status[16]" "0,1" textline " " bitfld.long 0x0 3.--7. " PRU0_GPI_DIV0 ,Divisor value (divide by PRU0_GPI_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--12. " PRU0_GPI_DIV1 ,Divisor value (divide by PRU0_GPI_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13. " PRU0_GPI_SB ,Start Bit event for 28-bit shift mode. PRU0_GPI_SB (pru0_r31_status[29]) is set when first capture of a 1 on pru0_r31_status[0]. Read 1: Start Bit event occurred. Read 0: Start Bit event has not occurred. Write 1: Will clear PRU0_GPI_SB and clear the whole shift register. Write 0: No Effect." "0,1" bitfld.long 0x0 14. " PRU0_GPO_MODE ,0x0 = Direct output mode 0x1 = Serial output mode" "0,1" textline " " bitfld.long 0x0 15.--19. " PRU0_GPO_DIV0 ,Divisor value (divide by PRU0_GPO_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--24. " PRU0_GPO_DIV1 ,Divisor value (divide by PRU0_GPO_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25. " PRU0_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0x0 = gpo_sh0 is selected 0x1 = gpo_sh1 is selected" "0,1" bitfld.long 0x0 26.--29. " PR1_PRU0_GP_MUX_SEL ,Reserved. Keep at reset value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0xC++0x3 line.long 0x0 "PRUSS_GPCFG1,The General Purpose Configuration 1 Register defines the GPI O configuration for PRU1." bitfld.long 0x0 0.--1. " PRU1_GPI_MODE ,0x0 = Direct input mode 0x1 = 16-bit parallel capture mode 0x2 = 28-bit shift mode 0x3 = MII_RT mode" "0,1,2,3" bitfld.long 0x0 2. " PRU1_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0x0 = Use the positive edge of pru1_r31_status[16] 0x1 = Use the negative edge of pru1_r31_status[16]" "0,1" textline " " bitfld.long 0x0 3.--7. " PRU1_GPI_DIV0 ,Divisor value (divide by PRU1_GPI_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--12. " PRU1_GPI_DIV1 ,Divisor value (divide by PRU1_GPI_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13. " PRU1_GPI_SB ,28-bit shift mode Start Bit event. PRU1_GPI_SB (pru1_r31_status[29]) is set when first capture of a 1 on pru1_r31_status[0]. Read 1: Start Bit event occurred. Read 0: Start Bit event has not occurred. Write 1: Will clear PRU1_GPI_SB and clear the whole shift register. Write 0: No Effect." "0,1" bitfld.long 0x0 14. " PRU1_GPO_MODE ,0x0 = Direct output mode 0x1 = Serial output mode" "0,1" textline " " bitfld.long 0x0 15.--19. " PRU1_GPO_DIV0 ,Divisor value (divide by PRU1_GPO_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--24. " PRU1_GPO_DIV1 ,Divisor value (divide by PRU1_GPO_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25. " PRU1_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0x0 = gpo_sh0 is selected 0x1 = gpo_sh1 is selected" "0,1" bitfld.long 0x0 26.--29. " PR1_PRU1_GP_MUX_SEL ,Reserved. Keep at reset value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x10++0x3 line.long 0x0 "PRUSS_CGR,The Clock Gating Register controls the state of Clock Management of the different modules. Software should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x1." bitfld.long 0x0 0. " PRU0_CLK_STOP_REQ ,PRU0 request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 1. " PRU0_CLK_STOP_ACK ,Acknowledgement that PRU0 clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 2. " PRU0_CLK_EN ,PRU0 clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 3. " PRU1_CLK_STOP_REQ ,PRU1 request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 4. " PRU1_CLK_STOP_ACK ,Acknowledgement that PRU1 clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 5. " PRU1_CLK_EN ,PRU1 clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " bitfld.long 0x0 6. " PRUSS_INTC_CLK_STOP_REQ ,PRUSS_INTC request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 7. " PRUSS_INTC_CLK_STOP_ACK ,Acknowledgement that PRUSS_INTC clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 8. " PRUSS_INTC_CLK_EN ,PRUSS_INTC clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 9. " UART_CLK_STOP_REQ ,UART request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 10. " UART_CLK_STOP_ACK ,Acknowledgement that UART clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 11. " UART_CLK_EN ,UART clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " bitfld.long 0x0 12. " ECAP_CLK_STOP_REQ ,ECAP request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 13. " ECAP_CLK_STOP_ACK ,Acknowledgement that ECAP clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 14. " ECAP_CLK_EN ,ECAP clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 15. " IEP_CLK_STOP_REQ ,IEP request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 16. " IEP_CLK_STOP_ACK ,Acknowledgement that IEP clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 17. " IEP_CLK_EN ,IEP clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_ISRP,The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRUSS memory parity events. The raw status is set even if the event is not enabled." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_RAW ,PRU0 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_IRAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_RAW ,PRU0 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_RAW ,PRU1 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_RAW ,PRU1 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE_RAW ,RAM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRUSS_ISP,The IRQ Status Parity Register is a snapshot of the IRQ status for the PRUSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE ,PRU0 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE ,PRU0 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No(enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE ,PRU1 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE ,PRU1 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE ,RAM Parity Error for Byte3, Byte2, Byte1, Byte0. Note RAM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRUSS_IESP,The IRQ Enable Set Parity Register enables the IRQ PRUSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_SET ,PRU0 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_SET ,PRU0 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_SET ,PRU1 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_SET ,PRU1 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE_SET ,RAM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRUSS_IECP,The IRQ Enable Clear Parity Register disables the IRQ PRUSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_CLR ,PRU0 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_CLR ,PRU0 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_CLR ,PRU1 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_CLR ,PRU1 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_PMAO,The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at 0x0000_0000." bitfld.long 0x0 0. " PMAO_PRU0 ,PRU0 OCP Master Port Address Offset Enable. 0x0 = Disable address offset. 0x1 = Enable address offset of -0x0008_0000." "0,1" bitfld.long 0x0 1. " PMAO_PRU1 ,PRU1 OCP Master Port Address Offset Enable. 0x0 = Disable address offset. 0x1 = Enable address offset of -0x0008_0000." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_MII_RT,The MII_RT Event Enable Register enables MII_RT mode events to the PRUSS.PRUSS_INTC." bitfld.long 0x0 0. " OCP_EN ,IEP clock source 0x0 = IEP_CLK is the source 0x1 = ICLK is the source. While this is selected no transactions should be active. It can only be cleared by a hardware reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PRUSS_IEPCLK,The IEP Clock Source Register defines the source of the IEP clock." bitfld.long 0x0 0. " OCP_EN ,IEP clock source 0x0 = IEP_CLK is the source 0x1 = ICLK is the source. While this is selected no transactions should be active. It can only be cleared by a hardware reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_SPP,The Scratch Pad Priority and Configuration Register defines the access priority assigned to the PRU cores and configures the scratch pad XFR shift functionality." bitfld.long 0x0 0. " PRU1_PAD_HP_EN ,Defines which PRU wins write cycle arbitration to a common scratch pad bank. The PRU which has higher priority will always perform the write cycle with no wait states. The lower PRU will get stalled wait states until higher PRU is not performing write cycles. If the lower priority PRU writes to the same byte has the higher priority PRU, then the lower priority PRU will over write the bytes. 0x0 = PRU0 has highest priority. 0x1 = PRU1 has highest priority." "0,1" bitfld.long 0x0 1. " XFR_SHIFT_EN ,Enables XIN XOUT shift functionality. When enabled, R0[4:0] (internal to PRU) defines the 32-bit offset for XIN and XOUT operations with the scratch pad. 0x0 = Disabled. 0x1 = Enabled." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PRUSS_PIN_MX,The Pin Mux Select Register defines the state of the PRUSS internal pinmuxing." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Reserved" bitfld.long 0x0 8. " PWM0_REMAP_EN ,If enabled, host intr6 of PRUSS2 controls epwm_sync_in of PWMSS1 instead of ehrpwm1_synci device pin" "0,1" textline " " bitfld.long 0x0 9. " PWM3_REMAP_EN ,UNUSED IN THIS DEVICE" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved. Always write 0." width 0x0B tree.end tree "PRUSS1_CTRL" base ad:0x00022000 width 15. group.byte 0x0++0x3 line.long 0x0 "PRU_CONTROL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. 0 = PRU is disabled. 1 = PRU is enabled. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The pru_state bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1" textline " " bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x0 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. 0 = PRU will free run when enabled. 1 = PRU will execute a single instruction and then the pru_enable bit will be cleared. Note that this bit does not actually enable the PRU, it only sets the policy for how much code will be run after the PRU is enabled. The pru_enable bit must be explicitly asserted. It is legal to initialize both the single_step and pru_enable bits simultaneously. (Two independent writes are not required to cause the stated functionality.)" "0,1" textline " " bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 14. " BIG_ENDIAN ," "0,1" textline " " bitfld.long 0x0 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. 0 = PRU is halted and host has access to the instruction RAM and debug registers regions. 1 = PRU is currently running and the host is locked out of the instruction RAM and debug registers regions. This bit is used by an external debug agent to know when the PRU has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the pru_enable has been cleared." "0,1" hexmask.long.word 0x0 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.byte 0x4++0x3 line.long 0x0 "PRU_STATUS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter. Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20)." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRU_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core." group.byte 0xC++0x3 line.long 0x0 "PRU_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the COUNTENABLE bit in the PRU control register when the count reaches 0xFFFFFFFF. (Count does does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register." group.byte 0x10++0x3 line.long 0x0 "PRU_STALL,STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count." hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.byte 0x20++0x3 line.long 0x0 "PRU_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRU_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRU_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory." hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.byte 0x2C++0x3 line.long 0x0 "PRU_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table." hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0x0B tree.end tree "PRUSS2_CTRL" base ad:0x00024000 width 15. group.byte 0x0++0x3 line.long 0x0 "PRU_CONTROL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. 0 = PRU is disabled. 1 = PRU is enabled. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The pru_state bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1" textline " " bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x0 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. 0 = PRU will free run when enabled. 1 = PRU will execute a single instruction and then the pru_enable bit will be cleared. Note that this bit does not actually enable the PRU, it only sets the policy for how much code will be run after the PRU is enabled. The pru_enable bit must be explicitly asserted. It is legal to initialize both the single_step and pru_enable bits simultaneously. (Two independent writes are not required to cause the stated functionality.)" "0,1" textline " " bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 14. " BIG_ENDIAN ," "0,1" textline " " bitfld.long 0x0 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. 0 = PRU is halted and host has access to the instruction RAM and debug registers regions. 1 = PRU is currently running and the host is locked out of the instruction RAM and debug registers regions. This bit is used by an external debug agent to know when the PRU has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the pru_enable has been cleared." "0,1" hexmask.long.word 0x0 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.byte 0x4++0x3 line.long 0x0 "PRU_STATUS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter. Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20)." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRU_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core." group.byte 0xC++0x3 line.long 0x0 "PRU_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the COUNTENABLE bit in the PRU control register when the count reaches 0xFFFFFFFF. (Count does does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register." group.byte 0x10++0x3 line.long 0x0 "PRU_STALL,STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count." hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.byte 0x20++0x3 line.long 0x0 "PRU_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRU_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRU_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory." hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.byte 0x2C++0x3 line.long 0x0 "PRU_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table." hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0x0B tree.end tree "PRUSS_INTC" base ad:0x00020000 width 21. group.byte 0x0++0x3 line.long 0x0 "PRUSS_INTC_REVID,Revision ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "PRUSS_INTC_CR,The Control Register holds global control parameters and can forces a soft reset on the module." bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " WAKEUP_MODE ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " NEST_MODE ,The nesting mode. 0 = no nesting 1 = automatic individual nesting (per host interrupt) 2 = automatic global nesting (over all host interrupts) 3 = manual nesting" "0,1,2,3" bitfld.long 0x0 4. " PRIORITY_HOLD_MODE ,Reserved" "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PRUSS_INTC_GER,The Global Host Interrupt Enable Register enables all the host interrupts. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable." bitfld.long 0x0 0. " ENABLE_HINT_ANY ,The current global enable value when read. Writes set the global enable." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRUSS_INTC_GNLR,The Global Nesting Level Register allows the checking and setting of the global nesting level across all host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of lower priority) that are nested out because of a current interrupt. This register is only available when nesting is configured." hexmask.long.word 0x0 0.--8. 1. " GLB_NEST_LEVEL ,The current global nesting level (highest channel that is nested). Writes set the nesting level. In auto nesting mode this value is updated internally unless the auto_override bit is set." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Always read as 0. Writes of 1 override the automatic nesting and set the nesting_level to the written data." "0,1" group.byte 0x20++0x3 line.long 0x0 "PRUSS_INTC_SISR,The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to set is the index value written. This sets the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STATUS_SET_INDEX ,Writes set the status of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRUSS_INTC_SICR,The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STATUS_CLR_INDEX ,Writes clear the status of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_INTC_EISR,The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is the index value written. This sets the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " ENABLE_SET_INDEX ,Writes set the enable of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_INTC_EICR,The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable is the index value written. This clears the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " ENABLE_CLR_INDEX ,Writes clear the enable of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_INTC_HIEISR,The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if already enabled." hexmask.long.word 0x0 0.--9. 1. " HINT_ENABLE_SET_INDEX ,Writes set the enable of the host interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PRUSS_INTC_HIDISR,The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host interrupt to disable is the index value written. This disables the host interrupt output." hexmask.long.word 0x0 0.--9. 1. " HINT_ENABLE_CLR_INDEX ,Writes clear the enable of the host interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PRUSS_INTC_GPIR,The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts." hexmask.long.word 0x0 0.--9. 1. " GLB_PRI_INTR ,The currently highest priority interrupt index pending across all the host interrupts." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " GLB_NONE ,No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending." "0,1" group.byte 0x200++0x3 line.long 0x0 "PRUSS_INTC_SRSR0,The System Interrupt Status Raw Set Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " RAW_STATUS_31_0 ,System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.byte 0x204++0x3 line.long 0x0 "PRUSS_INTC_SRSR1,The System Interrupt Status Raw Set Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " RAW_STATUS_63_32 ,System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.byte 0x280++0x3 line.long 0x0 "PRUSS_INTC_SECR0,The System Interrupt Status Enabled Clear Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENA_STATUS_31_0 ,System interrupt enabled status and clearing of the system interrupts 0 to 31. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect." group.byte 0x284++0x3 line.long 0x0 "PRUSS_INTC_SECR1,The System Interrupt Status Enabled Clear Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENA_STATUS_63_32 ,System interrupt enabled status and clearing of the system interrupts 32 to 63. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect." group.byte 0x300++0x3 line.long 0x0 "PRUSS_INTC_ESR0,The System Interrupt Enable Set Register0 enables system interrupts 0 to 31 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_SET_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.byte 0x304++0x3 line.long 0x0 "PRUSS_INTC_ERS1,The System Interrupt Enable Set Register1 enables system interrupts 32 to 63 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_SET_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.byte 0x380++0x3 line.long 0x0 "PRUSS_INTC_ECR0,The System Interrupt Enable Clear Register0 disables system interrupts 0 to 31 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_CLR_31_0 ,System interrupt enables system interrupts 0 to 31. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.byte 0x384++0x3 line.long 0x0 "PRUSS_INTC_ECR1,The System Interrupt Enable Clear Register1 disables system interrupts 32 to 63 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_CLR_63_32 ,System interrupt enables system interrupts 32 to 63. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.byte 0x400++0x3 line.long 0x0 "PRUSS_INTC_CMRi_0,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x404++0x3 line.long 0x0 "PRUSS_INTC_CMRi_1,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x408++0x3 line.long 0x0 "PRUSS_INTC_CMRi_2,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_3,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x410++0x3 line.long 0x0 "PRUSS_INTC_CMRi_4,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x414++0x3 line.long 0x0 "PRUSS_INTC_CMRi_5,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x418++0x3 line.long 0x0 "PRUSS_INTC_CMRi_6,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x41C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_7,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x420++0x3 line.long 0x0 "PRUSS_INTC_CMRi_8,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x424++0x3 line.long 0x0 "PRUSS_INTC_CMRi_9,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x428++0x3 line.long 0x0 "PRUSS_INTC_CMRi_10,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x42C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_11,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x430++0x3 line.long 0x0 "PRUSS_INTC_CMRi_12,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x434++0x3 line.long 0x0 "PRUSS_INTC_CMRi_13,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x438++0x3 line.long 0x0 "PRUSS_INTC_CMRi_14,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x43C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_15,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x800++0x3 line.long 0x0 "PRUSS_INTC_HMR0,The Host Interrupt Map Register0 define the host interrupt for channels 0 to 3. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_0 ,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_1 ,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " HINT_MAP_2 ,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HINT_MAP_3 ,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x804++0x3 line.long 0x0 "PRUSS_INTC_HMR1,The Host Interrupt Map Register1 define the host interrupt for channels 4 to 7. There is one register per 4 channels. Chan_statusnels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_4 ,HOST INTERRUPT MAP FOR CHANNEL 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_5 ,HOST INTERRUPT MAP FOR CHANNEL 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " HINT_MAP_6 ,HOST INTERRUPT MAP FOR CHANNEL 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HINT_MAP_7 ,HOST INTERRUPT MAP FOR CHANNEL 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x808++0x3 line.long 0x0 "PRUSS_INTC_HMR2,The Host Interrupt Map Register2 define the host interrupt for channels 8 to 9. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_8 ,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_9 ,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x900++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_0,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x904++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_1,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x908++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_2,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x90C++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_3,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x910++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_4,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x914++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_5,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x918++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_6,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x91C++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_7,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x920++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_8,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x924++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_9,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0xD00++0x3 line.long 0x0 "PRUSS_INTC_SIPR0,The System Interrupt Polarity Register0 define the polarity of the system interrupts 0 to 31. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x0 0.--31. 1. " POLARITY_31_0 ,Interrupt polarity of the system interrupts 0 to 31. 0 = active low. 1 = active high." group.byte 0xD04++0x3 line.long 0x0 "PRUSS_INTC_SIPR1,The System Interrupt Polarity Register1 define the polarity of the system interrupts 32 to 63. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x0 0.--31. 1. " POLARITY_63_32 ,Interrupt polarity of the system interrupts 32 to 63. 0 = active low. 1 = active high." group.byte 0xD80++0x3 line.long 0x0 "PRUSS_INTC_SITR0,The System Interrupt Type Register0 define the type of the system interrupts 0 to 31. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_31_0 ,Interrupt type of the system interrupts 0 to 31. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.byte 0xD84++0x3 line.long 0x0 "PRUSS_INTC_SITR1,The System Interrupt Type Register1 define the type of the system interrupts 32 to 63. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_63_32 ,Interrupt type of the system interrupts 32 to 63. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.byte 0x1100++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_0,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1104++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_1,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1108++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_2,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x110C++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_3,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1110++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_4,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1114++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_5,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1118++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_6,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x111C++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_7,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1120++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_8,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1124++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_9,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1500++0x3 line.long 0x0 "PRUSS_INTC_HIER,The Host Interrupt Enable Registers enable or disable individual host interrupts. These work separately from the global enables. There is one bit per host interrupt. These bits are updated when writing to the Host Interrupt Enable Index Set and Host Interrupt Enable Index Clear registers." hexmask.long.word 0x0 0.--9. 1. " ENABLE_HINT ,The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS_UART" base ad:0x00028000 width 68. group.byte 0x0++0x3 line.long 0x0 "PRUSS_UART_RBR_THR_REGISTERS,In the non-FIFO mode, when a character is placed in Receiver buffer register and the receiver data-ready interrupt is enabled (DR = 1 in Interrupt identification register), an interrupt is generated. This interrupt is cleared when the character is read from Receiver buffer register. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register, and it is cleared when the FIFO contents drop below the trigger level. In the non-FIFO mode, if Transmitter holding register is empty and the THR empty (THRE) interrupt is enabled (ETBEI = 1 in Interrupt enable register), an interrupt is generated. This interrupt is cleared when a character is loaded into Transmitter holding register or the Interrupt identification register is read. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or Interrupt identification register is read." hexmask.long.byte 0x0 0.--7. 1. " DATA ,Read: Read Receive Buffer RegisterWrite: Write Transmitter Holding Register ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "PRUSS_UART_INTERRUPT_ENABLE_REGISTER,The Interrupt enable register is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in Interrupt enable register is forwarded to the CPU." bitfld.long 0x0 0. " ERBI ,Receiver data available interrupt and character timeout indication interrupt enable." "0,1" bitfld.long 0x0 1. " ETBEI ,Transmitter holding register empty interrupt enable." "0,1" textline " " bitfld.long 0x0 2. " ELSI ,Receiver line status interrupt enable." "0,1" bitfld.long 0x0 3. " EDSSI ,Enable Modem Status Interrupt" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "PRUSS_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER,The Interrupt identification register is a read-only register at the same address as the FIFO control register, which is a write-only register. When an interrupt is generated and enabled in the Interrupt enable register, Interrupt identification register indicates that an interrupt is pending in the IPEND bit and encodes the type of interrupt in the INTID bits. Reading Interrupt identification register clears any THR empty (THRE) interrupts that are pending. The FIFOEN bit in Interrupt identification register can be checked to determine whether the UART is in the FIFO mode or the non-FIFO mode. Use FIFO control register to enable and clear the FIFOs and to select the receiver FIFO trigger level. The FIFOEN bit in FIFO control register must be set to 1 before other FIFO control register bits are written to or the FIFO control register bits are not programmed." bitfld.long 0x0 0. " IPEND_FIFOEN ,Read: Interrupt pending. When any UART interrupt is generated and is enabled in IER, IPEND is forced to 0. IPEND remains 0 until all pending interrupts are cleared or until a hardware reset occurs. If no interrupts are enabled, IPEND is never forced to 0.Write: Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to or the FCR bits are not programmed. Clearing this bit clears the FIFO counters. ." "0,1" bitfld.long 0x0 1.--3. " INTID ,Read: Interrupt type. See .0x4-0x5: Reserved . Write: . Bit 3: DMAMODE1: DMA MODE1 enable if FIFOs are enabled. Always write 1 to DMAMODE1. After a hardware reset, change DMAMODE1 from 0 to 1. DMAMODE1 = 1 is a requirement for proper communication between the UART and the EDMA controller. . Bit 2: TXCLR: Transmitter FIFO clear. Write a 1 to TXCLR to clear the bit. . Bit 1: RXCLR: Receiver FIFO clear. Write a 1 to RXCLR to clear the bit. ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 6.--7. " FIFOEN_RXFIFTL ,Read: FIFOs enabled.0x1-0x2: Reserved . Write: Receiver FIFO trigger level. RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the FIFO drops below the trigger level, the interrupt is cleared. ." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "PRUSS_UART_LINE_CONTROL_REGISTER,The system programmer controls the format of the asynchronous data communication exchange by using Line control register. In addition, the programmer can retrieve, inspect, and modify the content of line control register; this eliminates the need for separate storage of the line characteristics in system memory." bitfld.long 0x0 0.--1. " WLS ,Word length select. Number of bits in each transmitted or received serial character. When STB = 1, the WLS bit determines the number of STOP bits." "0,1,2,3" bitfld.long 0x0 2. " STB ,Number of STOP bits generated. STB specifies 1, 1.5, or 2 STOP bits in each transmitted character. When STB = 1, the WLS bit determines the number of STOP bits. The receiver clocks only the first STOP bit, regardless of the number of STOP bits selected. The number of STOP bits generated is summarized in." "0,1" textline " " bitfld.long 0x0 3. " PEN ,Parity enable. The PEN bit works in conjunction with the SP and EPS bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" bitfld.long 0x0 4. " EPS ,Even parity select. Selects the parity when parity is enabled (PEN = 1). The EPS bit works in conjunction with the SP and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" textline " " bitfld.long 0x0 5. " SP ,Stick parity. The SP bit works in conjunction with the EPS and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" bitfld.long 0x0 6. " BC ,Break control." "0,1" textline " " bitfld.long 0x0 7. " DLAB ,Divisor latch access bit. The divisor latch registers (DLL and DLH) can be accessed at dedicated addresses or at addresses shared by RBR, THR, and IER. Using the shared addresses requires toggling DLAB to change which registers are selected. If the dedicated addresses are used, keep DLAB = 0." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "PRUSS_UART_MODEM_CONTROL_REGISTER,The Modem control register provides the ability to enable/disable the autoflow functions, and enable/disable the loopback function for diagnostic purposes." bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " RTS ,RTS control. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0." "0,1" textline " " bitfld.long 0x0 2. " OUT1 ,OUT1 Control Bit" "0,1" bitfld.long 0x0 3. " OUT2 ,OUT2 Control Bit" "0,1" textline " " bitfld.long 0x0 4. " LOOP ,Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature." "0,1" bitfld.long 0x0 5. " AFE ,Autoflow control enable. Autoflow control allows the and signals to provide handshaking between UARTs during data transfer. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "PRUSS_UART_LINE_STATUS_REGISTER,The Line status register provides information to the CPU concerning the status of data transfers. Line status register is intended for read operations only; do not write to this register. Bits 1 through 4 record the error conditions that produce a receiver line status interrupt." bitfld.long 0x0 0. " DR ,Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 1. " OE ,Overrun error (OE) indicator. An overrun error in the non-FIFO mode is different from an overrun error in the FIFO mode. If the OE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 2. " PE ,Parity error (PE) indicator. A parity error occurs when the parity of the received character does not match the parity selected with the EPS bit in the line control register (LCR). If the PE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 3. " FE ,Framing error (FE) indicator. A framing error occurs when the received character does not have a valid STOP bit. In response to a framing error, the UART sets the FE bit and waits until the signal on the RX pin goes high. Once the RX signal goes high, the receiver is ready to detect a new START bit and receive new data. If the FE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 4. " BI ,Break indicator. The BI bit is set whenever the receive data input (UARTn_RXD) was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the START, data, PARITY, and STOP bits. If the BI bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 5. " THRE ,Transmitter holding register empty (THRE) indicator. If the THRE bit is set and the corresponding interrupt enable bit is set (ETBEI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 6. " TEMT ,Transmitter empty (TEMT) indicator. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 7. " RXFIFOE ,Receiver FIFO error. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "PRUSS_UART_MODEM_STATUS_REGISTER,The Modem status register provides information to the CPU concerning the status of modem control signals. Modem status register is intended for read operations only; do not write to this register." bitfld.long 0x0 0. " DCTS ,Change in CTS indicator bit. DCTS indicates that the CTS input has changed state since the last time it was read by the CPU. When DCTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled, no interrupt is generated." "0,1" bitfld.long 0x0 1. " DDSR ,Change in DSR indicator bit. DDSR indicates that the DSR input has changed state since the last time it was read by the CPU. When DDSR is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" textline " " bitfld.long 0x0 2. " TERI ,Trailing edge of RI (TERI) indicator bit. TERI indicates that the RI input has changed from a low to a high. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" bitfld.long 0x0 3. " DCD ,Change in DCD indicator bit. DCD indicates that the DCD input has changed state since the last time it was read by the CPU. When DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" textline " " bitfld.long 0x0 4. " CTS ,Complement of the Clear To Send input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 1 (RTS)." "0,1" bitfld.long 0x0 5. " DSR ,Complement of the Data Set Ready input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 0 (DTR)." "0,1" textline " " bitfld.long 0x0 6. " RI ,Complement of the Ring Indicator input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 2 (OUT1)." "0,1" bitfld.long 0x0 7. " CD ,Complement of the Carrier Detect input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 3 (OUT2)." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_UART_SCRATCH_REGISTER,The Scratch Pad register is intended for programmer's use as a scratch pad. It temporarily holds the programmer's data without affecting UART operation." hexmask.long.byte 0x0 0.--7. 1. " SCR ,These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "PRUSS_UART_DIVISOR_REGISTER_LSB_,Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value." hexmask.long.byte 0x0 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "PRUSS_UART_DIVISOR_REGISTER_MSB_,Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value." hexmask.long.byte 0x0 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "PRUSS_UART_PERIPHERAL_ID_REGISTER,Peripheral Identification register" hexmask.long 0x0 0.--31. 1. " PID ," group.byte 0x30++0x3 line.long 0x0 "PRUSS_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER,Power and emulation management register" bitfld.long 0x0 0. " FREE ,Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When halted, the UART can handle register read/write requests, but does not generate any transmission/reception, interrupts or events." "0,1" hexmask.long.word 0x0 1.--12. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 13. " URRST ,UART receiver reset. Resets and enables the receiver." "0,1" bitfld.long 0x0 14. " UTRST ,UART transmitter reset. Resets and enables the transmitter." "0,1" textline " " bitfld.long 0x0 15. " RESERVED ,Reserved. This bit must always be written with a 0." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "PRUSS_UART_MODE_DEFINITION_REGISTER,The Mode definition register determines the over-sampling mode for the UART." bitfld.long 0x0 0. " OSM_SEL ,Over-Sampling Mode Select." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "PRUSS_ECAP" base ad:0x00030000 width 19. group.byte 0x0++0x3 line.long 0x0 "PRUSS_ECAP_TSCNT,Time Stamp Counter Register" hexmask.long 0x0 0.--31. 1. " TSCNT ,Active 32 bit-counter register that is used as the capture time-base" group.byte 0x4++0x3 line.long 0x0 "PRUSS_ECAP_CNTPHS,Counter Phase Control Register" hexmask.long 0x0 0.--31. 1. " CNTPHS ,Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCNT and is loaded intoPRUSS_ECAP_TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM time-bases." group.byte 0x8++0x3 line.long 0x0 "PRUSS_ECAP_CAP1,Capture-1 Register" hexmask.long 0x0 0.--31. 1. " CAP1 ,This register can be loaded (written) by the following. (a) Time-Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0xC++0x3 line.long 0x0 "PRUSS_ECAP_CAP2,Capture-2 Register" hexmask.long 0x0 0.--31. 1. " CAP2 ,This register can be loaded (written) by the following. (a) Time- Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0x10++0x3 line.long 0x0 "PRUSS_ECAP_CAP3,Capture-3 Register" hexmask.long 0x0 0.--31. 1. " CAP3 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. User software updates the PWM period value through this register. In this mode, CAP3 shadows CAP1." group.byte 0x14++0x3 line.long 0x0 "PRUSS_ECAP_CAP4,Capture-4 Register" hexmask.long 0x0 0.--31. 1. " CAP4 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow (ACMP) register. User software updates the PWM compare value through this register. In this mode, CAP4 shadows CAP2." group.byte 0x28++0x1 line.word 0x0 "PRUSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select 0x0 = Capture Event 1 triggered on a rising edge (RE) 0x1 = Capture Event 1 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1 0x0 = Do not reset counter on Capture Event 1 (absolute time stamp) 0x1 = Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select 0x0 = Capture Event 2 triggered on a rising edge (RE) 0x1 = Capture Event 2 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2 0x0 = Do not reset counter on Capture Event 2 (absolute time stamp) 0x1 = Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select 0x0 = Capture Event 3 triggered on a rising edge (RE) 0x1 = Capture Event 3 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3 0x0 = Do not reset counter on Capture Event 3 (absolute time stamp) 0x1 = Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select 0x0 = Capture Event 4 triggered on a rising edge (RE) 0x1 = Capture Event 4 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4 0x0 = Do not reset counter on Capture Event 4 (absolute time stamp operation) 0x1 = Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading ofPRUSS_ECAP_CAP1 to PRUSS_ECAP_CAP4 registers on a capture event 0x0 = Disable PRUSS_ECAP_CAP1-PRUSS_ECAP_CAP4 register loads at capture event time. 0x1 = Enable PRUSS_ECAP_CAP1-PRUSS_ECAP_CAP4 register loads at capture event time." "0,1" bitfld.word 0x0 9.--13. " EVTFLTPS ,Event Filter prescale select: 0x0 = Divide by 1 (i.e,. no prescale, by-pass the prescaler) 0x1 = Divide by 2 0x2 = Divide by 4 0x3 = Divide by 6 0x4 = Divide by 8 0x5 = Divide by 10 0x1E = Divide by 60 0x1F = Divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control 0x0 = TSCNT counter stops immediately on emulation suspend. 0x1 = TSCNT counter runs until = 0. 0x2 = TSCNT counter is unaffected by emulation suspend (Run Free). 0x3 = TSCNT counter is unaffected by emulation suspend (Run Free)." "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "PRUSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x0 0. " CONTONESHT ,Continuous or one-shot mode control (applicable only in capture mode) 0x0 = Operate in continuous mode 0x1 = Operate in one-shot mode" "0,1" bitfld.word 0x0 1.--2. " STOPVALUE ,Stop value for one-shot mode. This is the number (between 1 and 4) of captures allowed to occur before the CAP (1 through 4) registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1 and 4) of the capture register in which the circular buffer wraps around and starts again. Notes: STOPVALUE is compared to Mod4 counter and, when equal, the following two actions occur. (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. In one-shot mode, further interrupt events are blocked until re-armed. 0x0 = Stop after Capture Event 1 in one-shot mode. Wrap after Capture Event 1 in continuous mode. 0x1 = Stop after Capture Event 2 in one-shot mode. Wrap after Capture Event 2 in continuous mode. 0x2 = Stop after Capture Event 3 in one-shot mode. Wrap after Capture Event 3 in continuous mode. 0x3 = Stop after Capture Event 4 in one-shot mode. Wrap after Capture Event 4 in continuous mode." "0,1,2,3" textline " " bitfld.word 0x0 3. " REARMRESET ,One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0x0 = Has no effect (reading always returns a 0) 0x1 = Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero. 2) Unfreezes the Mod4 counter. 3) Enables capture register loads." "0,1" bitfld.word 0x0 4. " TSCNTSTP ,Time Stamp (TSCNT) Counter Stop (freeze) Control 0x0 = TSCNT stopped 0x1 = TSCNT free-running" "0,1" textline " " bitfld.word 0x0 5. " SYNCI_EN ,Counter (TSCNT) Sync-In select mode 0x0 = Disable sync-in option 0x1 = Enable counter (TSCNT) to be loaded from" "0,1" bitfld.word 0x0 6.--7. " SYNCO_SEL ,Sync-Out Select 0x0 = Select sync-in event to be the sync-out signal (pass through) 0x1 = Select CTR = PRD event to be the sync-out signal 0x2 = Disable sync out signal 0x3 = Disable sync out signal" "0,1,2,3" textline " " bitfld.word 0x0 8. " SWSYNC ,Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via the CTR = PRD event. Note: Selection CTR = PRD is meaningful only in APWM mode. However, a choice of CAP mode is also available if it may be of use. 0x0 = Writing a zero has no effect. Reading always returns a zero 0x1 = Writing a one forces a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 1'b00. After writing a 1, this bit returns to a zero." "0,1" bitfld.word 0x0 9. " CAPAPWM ,CAP/APWM operating mode select 0x0 = ECAP module operates in capture mode. This mode forces the following configuration. 0x1 = ECAP module operates in APWM mode. This mode forces the following configuration." "0,1" textline " " bitfld.word 0x0 10. " APWMPOL ,APWM output polarity select. This is applicable only in APWM operating mode 0x0 = Output is active high (Compare value defines high time) 0x1 = Output is active low (Compare value defines low time)" "0,1" bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2C++0x1 line.word 0x0 "PRUSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Interrupt Enable. 0x0 = Disable Capture Event 1 as an Interrupt source. 0x1 = Enable Capture Event 1 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Interrupt Enable. 0x0 = Disable Capture Event 2 as an Interrupt source. 0x1 = Enable Capture Event 2 as an Interrupt source." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Interrupt Enable. 0x0 = Disable Capture Event 3 as an Interrupt source. 0x1 = Enable Capture Event 3 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Interrupt Enable. 0x0 = Disable Capture Event 4 as an Interrupt source. 0x1 = Enable Capture Event 4 as an Interrupt source." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Interrupt Enable. 0x0 = Disable counter Overflow as an Interrupt source. 0x1 = Enable counter Overflow as an Interrupt source." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal 0x0 = Disable Period Equal as an Interrupt source. 0x1 = Enable Period Equal as an Interrupt source." "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal 0x0 = Disable Compare Equal as an Interrupt source. 0x1 = Enable Compare Equal as an Interrupt source." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "PRUSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag 0x0 = Indicates no interrupt generated. 0x1 = Indicates that an interrupt was generated." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the first event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the second event occurred at ECAPn pin." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the third event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag This flag is only active in CAP mode. 0x0 = Indicates no event occurred 0x1 = Indicates the fourth event occurred at ECAPn pin" "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the counter (TSCNT) has made the transition from 0xFFFFFFFF to 0x00000000" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the period register value (APRD) and was reset." "0,1" bitfld.word 0x0 7. " CMPEQ ,Compare Equal Compare Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the compare register value (ACMP)" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "PRUSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT1 flag condition." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT2 flag condition." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CNTOVF flag condition" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CTR=PRD flag condition" "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal Compare Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CTR=CMP flag condition" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x34++0x1 line.word 0x0 "PRUSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Always reads back a 0. Force Capture Event 1 0x0 = No effect. 0x1 = Writing a 1 sets the CEVT1 flag bit." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Force Capture Event 2 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT2 flag bit." "0,1" bitfld.word 0x0 3. " CEVT3 ,Force Capture Event 3 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT3 flag bit" "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Force Capture Event 4 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT4 flag bit" "0,1" bitfld.word 0x0 5. " CNTOVF ,Force Counter Overflow 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 to this bit sets the CNTOVF flag bit." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Force Counter Equal Period Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CTR=PRD flag bit." "0,1" bitfld.word 0x0 7. " CMPEQ ,Force Counter Equal Compare Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CTR=CMP flag bit." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "PRUSS_ECAP_PID,ECAP Revision ID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "PRUSS_MII_RT" base ad:0x00032000 width 23. group.byte 0x0++0x3 line.long 0x0 "PRUSS_MII_RT_RXCFG0,MII RXCFG 0 REGISTER This register contains the PRU0 RXCFG configuration variables () for the RX path. is attached to PRU0. controls which RX port is attached to PRU0." bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0 Disable 0x1 Enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is DA" "0,1" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1)" "0,1" textline " " bitfld.long 0x0 4. " RX_L2_EN ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: that if TX_AUTO_SEQUENCE enabled, this bit cannot get enable since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received. Must be selected /updated when the port is disabled or no traffic It only effects R31 and RX L2 order" "0,1" textline " " bitfld.long 0x0 6. " RX_AUTO_FWD_PRE ,Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1:Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE." "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRUSS_MII_RT_RXCFG1,This register contains the PRU1 RXCFG configuration variables () for the RX path. is attached to PRU1. controls which RX port is attached to PRU1" bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is destination address." "0,1" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1)" "0,1" textline " " bitfld.long 0x0 4. " RX_L2_EN ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: If TX_AUTO_SEQUENCE is enabled, this bit cannot get enabled since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received." "0,1" textline " " bitfld.long 0x0 6. " RX_AUTO_FWD_PRE ,Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1: Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PRUSS_MII_RT_TXCFG0,This register contains the configuration variables for the transmit path on the MII interface port 0. is attached to Port TX0. controls which PRU is selected for TX0" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency." "0,1" textline " " bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event.Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself." "0,1" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0)" "0,1" textline " " bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter. Also, the masking logic is disabled and only the MII data is used." "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration." bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the PRUSS_GICLK clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "PRUSS_MII_RT_TXCFG1,MII TXCFG 1 REGISTER This register contains the configuration variables for the transmit path on the MII interface port 1. is attached to Port TX1. controls which PRU is selected for TX1" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency." "0,1" textline " " bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event.Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself." "0,1" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0)" "0,1" textline " " bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter.TX data from PRU1 is selected Also, the masking logic is disabled and only the MII data is used." "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration." bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the PRUSS_GICLK clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x20++0x3 line.long 0x0 "PRUSS_MII_RT_TX_CRC0,MII TXCRC 0 REGISTER It contains CRC32 which PRU0 reads" hexmask.long 0x0 0.--31. 1. " TX_CRC ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.byte 0x24++0x3 line.long 0x0 "PRUSS_MII_RT_TX_CRC1,MII TXCRC 1 REGISTER It contains CRC32 which PRU1 reads" hexmask.long 0x0 0.--31. 1. " TX_CRC ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.byte 0x30++0x3 line.long 0x0 "PRUSS_MII_RT_TX_IPG0,MII TXIPG 0 REGISTER" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_MII_RT_TX_IPG1,MII TXIPG 1 REGISTER" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PRUSS_MII_RT_PRS0,MII PORT STATUS 0 REGISTER" bitfld.long 0x0 0. " MII_COL ,Read the current state of pr1_mii0_col" "0,1" bitfld.long 0x0 1. " MII_CRS ,Read the current state of pr1_mii0_crs" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PRUSS_MII_RT_PRS1,MII PORT STATUS 1 REGISTER" bitfld.long 0x0 0. " MII_COL ,Read the current state of pr1_mii1_col" "0,1" bitfld.long 0x0 1. " MII_CRS ,Read the current state of pr1_mii1_crs" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PRUSS_MII_RT_RX_FRMS0,MII RXFRMS 0 REGISTER" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM ,Defines the maximum received frame count. If the total byte count of received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted." group.byte 0x44++0x3 line.long 0x0 "PRUSS_MII_RT_RX_FRMS1,MII RXFRMS 1 REGISTER" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM ,Defines the maximum received frame count. If the total byte count of the received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted." group.byte 0x48++0x3 line.long 0x0 "PRUSS_MII_RT_RX_PCNT0,MII RXPCNT 0 REGISTER" bitfld.long 0x0 0.--3. " RX_MIN_PCNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1 1 0x5 before 0xD5 0x2 2 0x5 before 0xD5 N min of N 0x5 before 0xD5 Note it does not need to be 0x5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_MAX_PCNT ,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted. Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "PRUSS_MII_RT_RX_PCNT1,MII RXPCNT 1 REGISTER" bitfld.long 0x0 0.--3. " RX_MIN_PCNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1: 1 0x5 before 0xD5 0x2: 2 0x5 before 0xD5 N: N 0x5 before 0xD5 Note it does not need to be 0x5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_MAX_PCNT ,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "PRUSS_MII_RT_RX_ERR0,MII RXERR 0 REGISTER" bitfld.long 0x0 0. " RX_MIN_PCNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 1. " RX_MAX_PCNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " bitfld.long 0x0 2. " RX_MIN_FRM_ERR ,Error status of received frame is less than the value of RX_MIN_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 3. " RX_MAX_FRM_ERR ,Error status of received frame is more than the value of RX_MAX_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "PRUSS_MII_RT_RX_ERR1,MII RXERR 1 REGISTER" bitfld.long 0x0 0. " RX_MIN_PCNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 1. " RX_MAX_PCNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " bitfld.long 0x0 2. " RX_MIN_FRM_ERR ,Error status of received frame is less than the value of RX_MIN_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 3. " RX_MAX_FRM_ERR ,Error status of received frame is more than the value of RX_MAX_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS_MII_MDIO" base ad:0x00032400 width 31. group.byte 0x0++0x3 line.long 0x0 "PRUSS_MII_MDIO_VER,MDIO MODULE VERSION REGISTER" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4++0x3 line.long 0x0 "PRUSS_MII_MDIO_CONTROL,MDIO MODULE CONTROL REGISTER" hexmask.long.word 0x0 0.--15. 1. " CLKDIV ,Clock Divider. This field specifies the division ratio between CLK and the frequency of MDCLK. MDCLK is disabled when clkdiv is set to 0. MDCLK frequency = clk frequency/(clkdiv+1)." bitfld.long 0x0 16. " RESERVED ," "0,1" textline " " bitfld.long 0x0 17. " INT_TEST_ENABLE ,Interrupt test enable. This bit can be set to 1 to enable the host to set the userint and linkint bits for test purposes." "0,1" bitfld.long 0x0 18. " FAULT_DETECT_ENABLE ,Fault detect enable. This bit has to be set to 1 to enable the physical layer fault detection." "0,1" textline " " bitfld.long 0x0 19. " FAULT ,Fault indicator. This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them. This indicates a physical layer fault and the module state machine is reset. Writing a 1 to it clears this bit." "0,1" bitfld.long 0x0 20. " PREAMBLE ,Preamble disable. Writing a 1 to this bit disables this device from sending MDIO frame preambles." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel. This field specifies the highest useraccess channel that is available in the module and is currently set to 1. This implies thatMDIOUserAccess1 is the highest available user access channel." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 29. " RESERVED ," "0,1" bitfld.long 0x0 30. " ENABLE ,Enable control. Writing a 1 to this bit enables the MDIO state machine, writing a 0 disables it. If the MDIO state machine is active at the time it is disabled, it will complete the current operation before halting and setting the idle bit. If using byte access, the enable bit has to be the last bit written in this register." "0,1" textline " " bitfld.long 0x0 31. " IDLE ,MDIO state machine IDLE. Set to 1 when the state machine is in the idle state." "0,1" group.byte 0x8++0x3 line.long 0x0 "PRUSS_MII_MDIO_ALIVE,PHY ACKNOWLEDGE STATUS REGISTER" hexmask.long 0x0 0.--31. 1. " ALIVE ,MDIO Alive bitfield. Each of the 32 bits of this register is set if the most recent access to the PHY with address corresponding to the register bit number was acknowledged by the PHY, the bit is reset if the PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause the corresponding alive bit to be updated. The alive bits are only meant to be used to give an indication of the presence or not of a PHY with the corresponding address. Writing a 1 to any bit will clear it, writing a 0 has no effect." group.byte 0xC++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINK,PHY LINK STATUS REGISTER" hexmask.long 0x0 0.--31. 1. " LINK ,MDIO Link state. This register is updated after a read of the Generic Status Register of a PHY. The bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge the read transaction. Writes to the register have no effect. In addition, the status of the two PHYs specified in theMDIOUserPhySel registers can be determined using the MLINK input pins. This is determined by the linksel bit in the MDIOUserPhySel register." group.byte 0x10++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINKINTRAW,LINK STATUS CHANGE INTERRUPT REGISTER (RAW VALUE)" bitfld.long 0x0 0.--1. " LINKINTRAW ,MDIO link change event, raw value. When asserted 1, a bit indicates that there was anMDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register. linkintraw[0] and linkintraw[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the event and writing 0 has no effect.If the int_test bit in the MDIOControl register is set, the host may set the linkintraw bits to a 1.This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINKINTMASKED,LINK STATUS CHANGE INTERRUPT REGISTER (MASKED VALUE)" bitfld.long 0x0 0.--1. " LINKINTMASKED ,MDIO link change interrupt, masked value. When asserted 1, a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register and the corresponding linkint_enable bit was set.. linkintmasked[0] and linkintmasked[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the interrupt and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the linkint bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTRAW,USER COMMAND COMPLETE INTERRUPT REGISTER (RAW VALUE)" bitfld.long 0x0 0.--1. " USERINTRAW ,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed. Writing a 1 will clear the event and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the userintraw bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKED,USER COMMAND COMPLETE INTERRUPT REGISTER (MASKED VALUE)" bitfld.long 0x0 0.--1. " USERINTMASKED ,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed and the corresponding userintmaskset bit is set to 1.Writing a 1 will clear the interrupt and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the userintmasked bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKSET,USER INTERRUPT MASK SET REGISTER" bitfld.long 0x0 0.--1. " USERINTMASKEDSET ,MDIO user interrupt mask set for userintmasked[1:0], respectively. Writing a bit to 1 will enable MDIO user command complete interrupts for that particular MDIOUserAccess register. MDIO user interrupt for a particular MDIOUserAccess register is disabled if the corresponding bit is 0. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKCLR,USER INTERRUPT MASK CLEAR REGISTER" bitfld.long 0x0 0.--1. " USERINTMASKEDCLR ,MDIO user command complete interrupt mask clear for userintmasked[1:0], respectively. Writing a bit to 1 will disable further user command complete interrupts for that particular MDIOUserAccess register. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERACCESS0,USER ACCESS REGISTER0" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. This field specifies the PHY to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. This field specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last." "0,1" group.byte 0x84++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERPHYSEL0,USER PHY SELECT REGISTER0" bitfld.long 0x0 0.--4. " PHYADR_MON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINT_ENABLE ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERACCESS1,USER ACCESS REGISTER1" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. This field specifies the PHY to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. This field specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last." "0,1" group.byte 0x8C++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERPHYSEL1,USER PHY SELECT REGISTER1" bitfld.long 0x0 0.--4. " PHYADR_MON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINT_ENABLE ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS_IEP" base ad:0x0002E000 width 29. group.byte 0x0++0x3 line.long 0x0 "PRUSS_IEP_GLOBAL_CFG,GLOBAL CFG" bitfld.long 0x0 0. " CNT_ENABLE ,Counter enable 0: Disables the counter. The counter maintains the current count. 1: Enables the counter." "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--7. " DEFAULT_INC ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 8.--19. 1. " CMP_INC ,Defines the increment value when compensation is active" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRUSS_IEP_GLOBAL_STATUS,STATUS" bitfld.long 0x0 0. " CNT_OVF ,Counter overflow status. 0: No overflow 1: Overflow occurred" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRUSS_IEP_COMPEN,COMPENSATION" hexmask.long.tbyte 0x0 0.--23. 1. " COMPEN_CNT ,Compensation counter. Read returns the current COMPEN_CNT value. 0: Compensation is disabled and counter will increment by DEFAULT_INC. n: Compensation is enabled until COMPEN_CNT decrements to 0. The COMPEN_CNT value decrements on every iep_clk cycle. When COMPEN_CNT is greater than 0, then count value increments by CMP_INC." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "PRUSS_IEP_COUNT,COUNTER" hexmask.long 0x0 0.--31. 1. " COUNT ,32-bit count value.t Increments by (DEFAULT_INC or CMP_INC) on every positive edge of PRUSS_IEP_CLK (200MHz) or PRUSS_GICLK." group.byte 0x10++0x3 line.long 0x0 "PRUSS_IEP_CAP_CFG,CAPTURE CFG" bitfld.long 0x0 0.--5. " CAP_1ST_EVENT_EN ,Capture 1-st Event Enable for n 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CAP6R_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[6] rise 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" textline " " bitfld.long 0x0 7. " CAP6F_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[6] fall 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" bitfld.long 0x0 8. " CAP7R_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[7] rise 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" textline " " bitfld.long 0x0 9. " CAP7F_1ST_EVENT_EN ,Capture 1st Event Enable for cap[7] fall 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" hexmask.long.byte 0x0 10.--17. 1. " CAP_ASYNC_EN ,Synchronization of the capture inputs to the PRUSS_IEP_CLK/PRUSS_GICLK enable. Note if input capture signal is asynchronous to PRUSS_IEP_CLK, enabling synchronization will cause the capture contents to be invalid. CAP_ASYNC_EN[n] maps to CAPR[n]. 0: Disable synchronization 1: Enable synchronization" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_IEP_CAP_STATUS,CAPTURE STATUS CFG" bitfld.long 0x0 0.--5. " CAPR_VALID ,Valid Status capr_valid<n> maps PRUSS_IEP_CAPR<n>_REG, where n=0 to 5, 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CAPR6_VALID ,Valid Status forPRUSS_IEP_CAPR6 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" textline " " bitfld.long 0x0 7. " CAPF6_VALID ,Valid Status forPRUSS_IEP_CAPF6 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" bitfld.long 0x0 8. " CAPR7_VALID ,Valid Status forPRUSS_IEP_CAPR7 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" textline " " bitfld.long 0x0 9. " CAPF7_VALID ,Valid Status forPRUSS_IEP_CAPF7 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" bitfld.long 0x0 10. " CAP_VALID ,Valid status for capture function. Reflects the ORed result from PRUSS_IEP_CAP_STATUS [9:0]. 0: No Hit for any capture event, i.e., there are all 0 in PRUSS_IEP_CAP_STATUS [9:0]. 1: Hit for 1 or more captures events is pending, i.e., there has at least one value equal to 1 in PRUSS_IEP_CAP_STATUS [9:0]." "0,1" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 16.--23. 1. " CAP_RAW ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]. 0: Current state is low for cap<n> 1: Current state is high for cap<n>" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_0,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_1,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x20++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_2,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x24++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_3,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x28++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_4,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_5,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x30++0x3 line.long 0x0 "PRUSS_IEP_CAPR6,CAPTURE RISE6" hexmask.long 0x0 0.--31. 1. " CAPR6 ,Capture Value for capr6 (rise) event" group.byte 0x34++0x3 line.long 0x0 "PRUSS_IEP_CAPF6,CAPTURE FALL6" hexmask.long 0x0 0.--31. 1. " CAPF6 ,Capture Value for capf6 (fall) event" group.byte 0x38++0x3 line.long 0x0 "PRUSS_IEP_CAPR7,CAPTURE RISE7" hexmask.long 0x0 0.--31. 1. " CAPR7 ,Capture Value for capr7 (rise) event" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_IEP_CAPF7,CAPTURE FALL7" hexmask.long 0x0 0.--31. 1. " CAPF7 ,Capture Value for capf7 (fall) event" group.byte 0x40++0x3 line.long 0x0 "PRUSS_IEP_CMP_CFG,COMPARE CFG" bitfld.long 0x0 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter 0: Disable 1: Enable the reset of the counter if a cmp0 event occurs" "0,1" hexmask.long.byte 0x0 1.--8. 1. " CMP_EN ,Enable bit for each of the compare registers cmp_en<n> =0: Disables CMP<n> Event cmp_en<n> =1: Enables CMP<n> Event cmp_en[0] maps to CMP0" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "PRUSS_IEP_CMP_STATUS,COMPARE STATUS" hexmask.long.byte 0x0 0.--7. 1. " CMP_HIT ,Status bit for each of the compare registers. 'Match' indicates the current counter is greater than or equal to the compare value. Note it is the firmware's responsibility to handle the IEP overflow. cmp_hit<n> = 0: No match has occured cmp_hit<n> = 1: A match occured. The associated hardware event signal will assert and remain high until the status is cleared." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "PRUSS_IEP_CMPj_0,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_IEP_CMPj_1,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x50++0x3 line.long 0x0 "PRUSS_IEP_CMPj_2,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x54++0x3 line.long 0x0 "PRUSS_IEP_CMPj_3,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x58++0x3 line.long 0x0 "PRUSS_IEP_CMPj_4,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_IEP_CMPj_5,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x60++0x3 line.long 0x0 "PRUSS_IEP_CMPj_6,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x64++0x3 line.long 0x0 "PRUSS_IEP_CMPj_7,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x80++0x3 line.long 0x0 "PRUSS_IEP_RXIPG0,RXIPG0This register can be used to determine the last RX IPG and the smallest RX IPG. RXIPG0 is the status for the RX port which is attached to PRU0." hexmask.long.word 0x0 0.--15. 1. " RX_IPG ,Records the current number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. Value is updated after RX_DV transitions from low to high. It will saturate at 0xffff." hexmask.long.word 0x0 16.--31. 1. " RX_MIN_IPG ,Defines the current minimum number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that is RXDV is sampled low. It stores the current smallest RX_IPG Read: The value can be read at any time. It gets updated after RX_IPG update if RX_MIN_IPG > RX_IPG. Write:Any write will reset this bitfield to 0xffff" group.byte 0x84++0x3 line.long 0x0 "PRUSS_IEP_RXIPG1,RXIPG1This register can be used to determine the last RX IPG and the smallest RX IPG. RXIPG1 is the status for the RX port which is attached to PRU1" hexmask.long.word 0x0 0.--15. 1. " RX_IPG ,Records the current number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. Value is updated after RX_DV transitions from low to high. It will saturate at 0xffff." hexmask.long.word 0x0 16.--31. 1. " RX_MIN_IPG ,Defines the current minimum number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. It stores the current smallest RX_IPG Read: The value can be read at any time. It gets updated after RX_IPG update if RX_MIN_IPG > RX_IPG. Write:Any write will reset this bitfield to 0xffff" group.byte 0x100++0x3 line.long 0x0 "PRUSS_IEP_SYNC_CTRL,SYNC CTRL" bitfld.long 0x0 0. " SYNC_EN ,SYNC generation enable 0: Disable the generation and clocking of SYNC0 and SYNC1 logic 1: Enables SYNC0 and SYNC1 generation" "0,1" bitfld.long 0x0 1. " SYNC0_EN ,SYNC0 generation enable 0: Disable SYNC0 generation 1: Enable SYNC0 generation" "0,1" textline " " bitfld.long 0x0 2. " SYNC1_EN ,SYNC1 generation enable 0: Disable SYNC1 generation 1: Enable SYNC1 generation" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " SYNC0_ACK_EN ,SYNC0 acknowledgement mode enable 0h: Disable, SYNC0 will go low after pulse width is met. 1: Enables acknowledge mode, when enabled SYNC0 will 1h: Enable, SYNC0 will remain asserted until receiving software acknowledges by reading PRUSS_IEP_SYNC0_STAT which clears on read." "0,1" bitfld.long 0x0 5. " SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable 0h: Disable, single shot mode 1h: Enable, cyclic generation mode" "0,1" textline " " bitfld.long 0x0 6. " SYNC1_ACK_EN ,SYNC1 acknowledgement mode enable 0h: Disable, SYNC1 will go low after pulse width is met. 1h: Enable, SYNC1 will remain asserted until receiving software acknowledges by reading PRUSS_IEP_SYNC1_ STAT which clears on read." "0,1" bitfld.long 0x0 7. " SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable 0: Disable, single shot mode 1:Enable, cyclic generation mode" "0,1" textline " " bitfld.long 0x0 8. " SYNC1_IND_EN ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0. 0: Dependent mode 1: Independent mode" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "PRUSS_IEP_SYNC_FIRST_STAT,SYNC CTRL" bitfld.long 0x0 0. " FIRST_SYNC0 ,SYNC0 First Event status 0: SYNC0 first event has not occurred 1: SYNC0 first event has occurred. This bits is cleared when sync0_en = 0" "0,1" bitfld.long 0x0 1. " FIRST_SYNC1 ,SYNC1 First Event status 0: SYNC1 first event has not occurred 1: SYNC1 first event has occurred. This bits is cleared when sync1_en = 0" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "PRUSS_IEP_SYNC0_STAT,SYNC CTRL" bitfld.long 0x0 0. " SYNC0_PEND ,SYNC0 pending state 0: SYNC0 is not pending 1 SYNC0 is pending or has occurred when SYNC0_ACK_EN = 0 (Disable). Write '1' to clear" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "PRUSS_IEP_SYNC1_STAT,SYNC CTRL" bitfld.long 0x0 0. " SYNC1_PEND ,SYNC1 pending state 0: SYNC1 is not pending 1 SYNC1 is pending or has occurred when SYNC1_ACK_EN = 0 (Disable). Write '1' to Clear" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "PRUSS_IEP_SYNC_PWIDTH,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC_HPW ,Defines the number of clock cycles SYNC0/1 will be high. Note if SYNC0/1 is disabled during pulse width time (that is, SYNC_CTRL[SYNC0_EN | SYNC1_EN | SYNC_EN] = 0), the ongoing pulse will be terminated. 0h: 1 clock cycle. 1h: 2 clock cycles. Nh: N+1 clock cycles." group.byte 0x114++0x3 line.long 0x0 "PRUSS_IEP_SYNC0_PERIOD,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC0_PERIOD ,Defines the period between the rising edges of SYNC0. 0x0: Reserved 0x1: 2 clk cycles period N: N+1 clk cycles period" group.byte 0x118++0x3 line.long 0x0 "PRUSS_IEP_SYNC1_DELAY,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC1_DELAY ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1. Note this is the delay before the start of SYNC1. 0h: No delay 1h: 1 clock cycle delay. Nh: N clock cycles delay. When SYNC1_IND_EN = 1, defines the period between the rising edges of SYNC1. 0h: Reserved. 1h: 2 clock cycles period. Nh: N+1 clock cycles period." group.byte 0x11C++0x3 line.long 0x0 "PRUSS_IEP_SYNC_START,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC_START ,Defines the start time after the activation event. 0h: 1 clock cycle delay. Nh: N+1 clock cycles delay." group.byte 0x200++0x3 line.long 0x0 "PRUSS_IEP_WD_PREDIV,WD" hexmask.long.word 0x0 0.--15. 1. " PRE_DIV ,Defines the number of iep_clk cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if iep_clk is 200 MHz. seconds/(WD event) = (clock cycles per WD event)/(clock cycles per second) = 20000/(200 x [10]^6 ) = 100 us" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x204++0x3 line.long 0x0 "PRUSS_IEP_PDI_WD_TIM,WD" hexmask.long.word 0x0 0.--15. 1. " PDI_WD_TIME ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRE_DIV is set to 100 us, then the value 0x03e8 (or 1000) provides a rate of 100ms. Read returns the current count. Counter is reset by software write to register or when Digital Data In capture occurs. WD is disabled if WD time is set to 0x0. Note when an expiration event occurs, the expiration counter (PDI_EXP_CNT) increments and status (PDI_WD_STAT) clears." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "PRUSS_IEP_PD_WD_TIM,WD" hexmask.long.word 0x0 0.--15. 1. " PD_WD_TIME ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRE_DIV is set to 100 us, then 0x03e8 (or 1000) provides a rate of 100ms Read returns the current count. Counter is reset by software write to register or every write access to Sync Managers with WD trigger enable bit set. WD is disabled if WD time is set to 0x0. Expiration actions: Increment expiration counter, clear status. Digital Data out forced to zero if pr1_edio_oe_ext = 1 and PRUSS_IEP_DIGIO_EXT.SW_DATA_OUT_UPDATE = 0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "PRUSS_IEP_WD_STATUS,WD" bitfld.long 0x0 0. " PD_WD_STAT ,WD PD status (triggered by Sync Mangers status). 0h: Expired (PD_WD_EXP event generated) 1h: Active or disabled" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " PDI_WD_STAT ,WD PDI status. 0h: Expired (PDI_WD_EXP event generated) 1h: Active or disabled" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "PRUSS_IEP_WD_EXP_CNT,WD" hexmask.long.byte 0x0 0.--7. 1. " PDI_EXP_CNT ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh." hexmask.long.byte 0x0 8.--15. 1. " PD_EXP_CNT ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "PRUSS_IEP_WD_CTRL,WD" bitfld.long 0x0 0. " PD_WD_EN ,Watchdog PD 0: Disable 1: Enable" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " PDI_WD_EN ,Watchdog PDI 0: Disable 1: Enable" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x300++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_CTRL,DIGIO" bitfld.long 0x0 0. " OUTVALID_POL ,Indicates OUTVALID polarity" "0,1" bitfld.long 0x0 1. " OUTVALID_MODE ,Defines OUTVALID mode" "0,1" textline " " bitfld.long 0x0 2. " BIDI_MODE ,Indicates the digital input/output direction. DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1" bitfld.long 0x0 3. " WD_MODE ,Defines Watchdog behavior" "0,1" textline " " bitfld.long 0x0 4.--5. " IN_MODE ,Defines event that triggers data in to be sampled 0b00: PRU0/1_RX_SOF 0b01: Rising edge of external pr<k>_edio_latch_in signal 0b10: DC rising edge of SYNC0 event 0b11: DC rising edge of SYNC1 event" "0,1,2,3" bitfld.long 0x0 6.--7. " OUT_MODE ,Defines event that triggers data out to be updated." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x308++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_IN,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_IN ,Data input. Digital inputs can be configured to be sampled in four ways. 1: Digital inputs are sampled at the start of each frame. The SOF signal can be used externally to update the input data, because the SOF is signaled before input data is sampled. 2: The sample time can be controlled externally by using the pr1_edio_latch_in signal. 3: Digital inputs are sampled at SYNC0 events. 4: Digital inputs are sampled at SYNC1 events. These can be configured by PRUSS_IEP_DIGIO_CTRL[5:4] IN_MODE. Only [7:0] are exported to device pins in this device." group.byte 0x30C++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_IN_RAW,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_IN_RAW ,Raw Data Input. Direct sample of EDIO_DATA_IN[31:0]. Only [7:0] are exported to device pins in this device." group.byte 0x310++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_OUT,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_OUT ,Data output. Digital outputs can be configured to be updated in four ways. 1: Digital outputs are updated at the end of each frame (EOF mode). 2: Digital outputs are updated with SYNC0 events 3: Digital outputs are updated SYNC1events. 4: Digital outputs are updated at the end of a frame which triggered the Process Data Watchdog. Digital Outputs are only updated if the frame was correct (WD_TRIG mode). These can be configured by out_mode." group.byte 0x314++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_OUT_EN,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_OUT_EN ,Enables tri-state control for pr<k>_edio_data_out[7:0]." group.byte 0x318++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_EXP,DIGIO" bitfld.long 0x0 0. " SW_DATA_OUT_UPDATE ,Defines the value of pr1_edio_data_out when OUTVALID_OVR_EN = 1. Read 1: Start bit event occurred Read 0: Start bit event has not occurred Write 1: pr1_edio_data_out by software data out. Write 0: No Effect" "0,1" bitfld.long 0x0 1. " OUTVALID_OVR_EN ,Enable software to control value of pr<k>_edio_data_out [7:0]. 0: Disable 1: Enable" "0,1" textline " " bitfld.long 0x0 2. " SW_OUTVALID ,pr1_edio_outvalid = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--7. " OUTVALID_DLY ,Define the number of iep_clk (PRUSS_IEP_CLK) cycle delay on assertion of PR1_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " SOF_DLY ,Define the number of iep_clk (PRUSS_IEP_CLK) cycle delay of SOF PR1_EDIO_DATA_IN[31:0] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12. " SOF_SEL ,Defines with RX_SOF is used for PR1_EDIO_DATA_IN[31:0] capture" "0,1" bitfld.long 0x0 13. " EOF_SEL ,Defines with RX_EOF is used for PR1_EDIO_DATA_IN[31:0] capture" "0,1" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," width 0x0B tree.end else tree.open "ICSS_0" tree "CFG" base ad:0x4B226000 width 14. group.byte 0x0++0x3 line.long 0x0 "PRUSS_REVID,The Revision Register contains the ID and revision information." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "PRUSS_SYSCFG,The System Configuration Register defines the power IDLE and STANDBY modes." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0 = Force-idle mode 0x1 = No-idle mode 0x2 = Smart-idle mode 0x3 = Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " STANDBY_MODE ,0x0 = Force standby mode: Initiator unconditionally in standby (standby = 1) 0x1 = No standby mode: Initiator unconditionally out of standby (standby = 0) 0x2 = Smart standby mode: Standby requested by initiator depending on internal conditions 0x3 = Reserved" "0,1,2,3" textline " " bitfld.long 0x0 4. " STANDBY_INIT ,0x1 = Initiate standby sequence. 0x0 = Enable OCP master ports." "0,1" bitfld.long 0x0 5. " SUB_MWAIT ,Status bit for wait state. 0x0 = Ready for Transaction 0x1 = Wait until 0" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRUSS_GPCFG0,The General Purpose Configuration 0 Register defines the GPIO configuration for PRU0." bitfld.long 0x0 0.--1. " PRU0_GPI_MODE ,0x0 = Direct input mode 0x1 = 16-bit parallel capture mode 0x2 = 28-bit shift mode 0x3 = MII_RT mode" "0,1,2,3" bitfld.long 0x0 2. " PRU0_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0x0 = Use the positive edge of pru0_r31_status[16] 0x1 = Use the negative edge of pru0_r31_status[16]" "0,1" textline " " bitfld.long 0x0 3.--7. " PRU0_GPI_DIV0 ,Divisor value (divide by PRU0_GPI_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--12. " PRU0_GPI_DIV1 ,Divisor value (divide by PRU0_GPI_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13. " PRU0_GPI_SB ,Start Bit event for 28-bit shift mode. PRU0_GPI_SB (pru0_r31_status[29]) is set when first capture of a 1 on pru0_r31_status[0]. Read 1: Start Bit event occurred. Read 0: Start Bit event has not occurred. Write 1: Will clear PRU0_GPI_SB and clear the whole shift register. Write 0: No Effect." "0,1" bitfld.long 0x0 14. " PRU0_GPO_MODE ,0x0 = Direct output mode 0x1 = Serial output mode" "0,1" textline " " bitfld.long 0x0 15.--19. " PRU0_GPO_DIV0 ,Divisor value (divide by PRU0_GPO_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--24. " PRU0_GPO_DIV1 ,Divisor value (divide by PRU0_GPO_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25. " PRU0_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0x0 = gpo_sh0 is selected 0x1 = gpo_sh1 is selected" "0,1" bitfld.long 0x0 26.--29. " PR1_PRU0_GP_MUX_SEL ,Reserved. Keep at reset value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0xC++0x3 line.long 0x0 "PRUSS_GPCFG1,The General Purpose Configuration 1 Register defines the GPI O configuration for PRU1." bitfld.long 0x0 0.--1. " PRU1_GPI_MODE ,0x0 = Direct input mode 0x1 = 16-bit parallel capture mode 0x2 = 28-bit shift mode 0x3 = MII_RT mode" "0,1,2,3" bitfld.long 0x0 2. " PRU1_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0x0 = Use the positive edge of pru1_r31_status[16] 0x1 = Use the negative edge of pru1_r31_status[16]" "0,1" textline " " bitfld.long 0x0 3.--7. " PRU1_GPI_DIV0 ,Divisor value (divide by PRU1_GPI_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--12. " PRU1_GPI_DIV1 ,Divisor value (divide by PRU1_GPI_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13. " PRU1_GPI_SB ,28-bit shift mode Start Bit event. PRU1_GPI_SB (pru1_r31_status[29]) is set when first capture of a 1 on pru1_r31_status[0]. Read 1: Start Bit event occurred. Read 0: Start Bit event has not occurred. Write 1: Will clear PRU1_GPI_SB and clear the whole shift register. Write 0: No Effect." "0,1" bitfld.long 0x0 14. " PRU1_GPO_MODE ,0x0 = Direct output mode 0x1 = Serial output mode" "0,1" textline " " bitfld.long 0x0 15.--19. " PRU1_GPO_DIV0 ,Divisor value (divide by PRU1_GPO_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--24. " PRU1_GPO_DIV1 ,Divisor value (divide by PRU1_GPO_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25. " PRU1_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0x0 = gpo_sh0 is selected 0x1 = gpo_sh1 is selected" "0,1" bitfld.long 0x0 26.--29. " PR1_PRU1_GP_MUX_SEL ,Reserved. Keep at reset value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x10++0x3 line.long 0x0 "PRUSS_CGR,The Clock Gating Register controls the state of Clock Management of the different modules. Software should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x1." bitfld.long 0x0 0. " PRU0_CLK_STOP_REQ ,PRU0 request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 1. " PRU0_CLK_STOP_ACK ,Acknowledgement that PRU0 clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 2. " PRU0_CLK_EN ,PRU0 clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 3. " PRU1_CLK_STOP_REQ ,PRU1 request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 4. " PRU1_CLK_STOP_ACK ,Acknowledgement that PRU1 clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 5. " PRU1_CLK_EN ,PRU1 clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " bitfld.long 0x0 6. " PRUSS_INTC_CLK_STOP_REQ ,PRUSS_INTC request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 7. " PRUSS_INTC_CLK_STOP_ACK ,Acknowledgement that PRUSS_INTC clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 8. " PRUSS_INTC_CLK_EN ,PRUSS_INTC clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 9. " UART_CLK_STOP_REQ ,UART request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 10. " UART_CLK_STOP_ACK ,Acknowledgement that UART clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 11. " UART_CLK_EN ,UART clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " bitfld.long 0x0 12. " ECAP_CLK_STOP_REQ ,ECAP request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 13. " ECAP_CLK_STOP_ACK ,Acknowledgement that ECAP clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 14. " ECAP_CLK_EN ,ECAP clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 15. " IEP_CLK_STOP_REQ ,IEP request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 16. " IEP_CLK_STOP_ACK ,Acknowledgement that IEP clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 17. " IEP_CLK_EN ,IEP clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_ISRP,The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRUSS memory parity events. The raw status is set even if the event is not enabled." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_RAW ,PRU0 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_IRAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_RAW ,PRU0 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_RAW ,PRU1 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_RAW ,PRU1 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE_RAW ,RAM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRUSS_ISP,The IRQ Status Parity Register is a snapshot of the IRQ status for the PRUSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE ,PRU0 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE ,PRU0 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No(enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE ,PRU1 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE ,PRU1 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE ,RAM Parity Error for Byte3, Byte2, Byte1, Byte0. Note RAM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRUSS_IESP,The IRQ Enable Set Parity Register enables the IRQ PRUSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_SET ,PRU0 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_SET ,PRU0 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_SET ,PRU1 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_SET ,PRU1 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE_SET ,RAM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRUSS_IECP,The IRQ Enable Clear Parity Register disables the IRQ PRUSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_CLR ,PRU0 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_CLR ,PRU0 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_CLR ,PRU1 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_CLR ,PRU1 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_PMAO,The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at 0x0000_0000." bitfld.long 0x0 0. " PMAO_PRU0 ,PRU0 OCP Master Port Address Offset Enable. 0x0 = Disable address offset. 0x1 = Enable address offset of -0x0008_0000." "0,1" bitfld.long 0x0 1. " PMAO_PRU1 ,PRU1 OCP Master Port Address Offset Enable. 0x0 = Disable address offset. 0x1 = Enable address offset of -0x0008_0000." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_MII_RT,The MII_RT Event Enable Register enables MII_RT mode events to the PRUSS.PRUSS_INTC." bitfld.long 0x0 0. " OCP_EN ,IEP clock source 0x0 = IEP_CLK is the source 0x1 = ICLK is the source. While this is selected no transactions should be active. It can only be cleared by a hardware reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PRUSS_IEPCLK,The IEP Clock Source Register defines the source of the IEP clock." bitfld.long 0x0 0. " OCP_EN ,IEP clock source 0x0 = IEP_CLK is the source 0x1 = ICLK is the source. While this is selected no transactions should be active. It can only be cleared by a hardware reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_SPP,The Scratch Pad Priority and Configuration Register defines the access priority assigned to the PRU cores and configures the scratch pad XFR shift functionality." bitfld.long 0x0 0. " PRU1_PAD_HP_EN ,Defines which PRU wins write cycle arbitration to a common scratch pad bank. The PRU which has higher priority will always perform the write cycle with no wait states. The lower PRU will get stalled wait states until higher PRU is not performing write cycles. If the lower priority PRU writes to the same byte has the higher priority PRU, then the lower priority PRU will over write the bytes. 0x0 = PRU0 has highest priority. 0x1 = PRU1 has highest priority." "0,1" bitfld.long 0x0 1. " XFR_SHIFT_EN ,Enables XIN XOUT shift functionality. When enabled, R0[4:0] (internal to PRU) defines the 32-bit offset for XIN and XOUT operations with the scratch pad. 0x0 = Disabled. 0x1 = Enabled." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PRUSS_PIN_MX,The Pin Mux Select Register defines the state of the PRUSS internal pinmuxing." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Reserved" bitfld.long 0x0 8. " PWM0_REMAP_EN ,If enabled, host intr6 of PRUSS2 controls epwm_sync_in of PWMSS1 instead of ehrpwm1_synci device pin" "0,1" textline " " bitfld.long 0x0 9. " PWM3_REMAP_EN ,UNUSED IN THIS DEVICE" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved. Always write 0." width 0x0B tree.end tree "PRUSS1_CTRL" base ad:0x4B222000 width 15. group.byte 0x0++0x3 line.long 0x0 "PRU_CONTROL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. 0 = PRU is disabled. 1 = PRU is enabled. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The pru_state bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1" textline " " bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x0 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. 0 = PRU will free run when enabled. 1 = PRU will execute a single instruction and then the pru_enable bit will be cleared. Note that this bit does not actually enable the PRU, it only sets the policy for how much code will be run after the PRU is enabled. The pru_enable bit must be explicitly asserted. It is legal to initialize both the single_step and pru_enable bits simultaneously. (Two independent writes are not required to cause the stated functionality.)" "0,1" textline " " bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 14. " BIG_ENDIAN ," "0,1" textline " " bitfld.long 0x0 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. 0 = PRU is halted and host has access to the instruction RAM and debug registers regions. 1 = PRU is currently running and the host is locked out of the instruction RAM and debug registers regions. This bit is used by an external debug agent to know when the PRU has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the pru_enable has been cleared." "0,1" hexmask.long.word 0x0 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.byte 0x4++0x3 line.long 0x0 "PRU_STATUS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter. Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20)." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRU_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core." group.byte 0xC++0x3 line.long 0x0 "PRU_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the COUNTENABLE bit in the PRU control register when the count reaches 0xFFFFFFFF. (Count does does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register." group.byte 0x10++0x3 line.long 0x0 "PRU_STALL,STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count." hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.byte 0x20++0x3 line.long 0x0 "PRU_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRU_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRU_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory." hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.byte 0x2C++0x3 line.long 0x0 "PRU_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table." hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0x0B tree.end tree "PRUSS2_CTRL" base ad:0x4B2A2000 width 15. group.byte 0x0++0x3 line.long 0x0 "PRU_CONTROL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. 0 = PRU is disabled. 1 = PRU is enabled. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The pru_state bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1" textline " " bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x0 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. 0 = PRU will free run when enabled. 1 = PRU will execute a single instruction and then the pru_enable bit will be cleared. Note that this bit does not actually enable the PRU, it only sets the policy for how much code will be run after the PRU is enabled. The pru_enable bit must be explicitly asserted. It is legal to initialize both the single_step and pru_enable bits simultaneously. (Two independent writes are not required to cause the stated functionality.)" "0,1" textline " " bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 14. " BIG_ENDIAN ," "0,1" textline " " bitfld.long 0x0 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. 0 = PRU is halted and host has access to the instruction RAM and debug registers regions. 1 = PRU is currently running and the host is locked out of the instruction RAM and debug registers regions. This bit is used by an external debug agent to know when the PRU has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the pru_enable has been cleared." "0,1" hexmask.long.word 0x0 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.byte 0x4++0x3 line.long 0x0 "PRU_STATUS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter. Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20)." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRU_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core." group.byte 0xC++0x3 line.long 0x0 "PRU_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the COUNTENABLE bit in the PRU control register when the count reaches 0xFFFFFFFF. (Count does does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register." group.byte 0x10++0x3 line.long 0x0 "PRU_STALL,STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count." hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.byte 0x20++0x3 line.long 0x0 "PRU_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRU_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRU_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory." hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.byte 0x2C++0x3 line.long 0x0 "PRU_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table." hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0x0B tree.end tree "INTC" base ad:0x4B220000 width 21. group.byte 0x0++0x3 line.long 0x0 "PRUSS_INTC_REVID,Revision ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "PRUSS_INTC_CR,The Control Register holds global control parameters and can forces a soft reset on the module." bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " WAKEUP_MODE ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " NEST_MODE ,The nesting mode. 0 = no nesting 1 = automatic individual nesting (per host interrupt) 2 = automatic global nesting (over all host interrupts) 3 = manual nesting" "0,1,2,3" bitfld.long 0x0 4. " PRIORITY_HOLD_MODE ,Reserved" "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PRUSS_INTC_GER,The Global Host Interrupt Enable Register enables all the host interrupts. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable." bitfld.long 0x0 0. " ENABLE_HINT_ANY ,The current global enable value when read. Writes set the global enable." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRUSS_INTC_GNLR,The Global Nesting Level Register allows the checking and setting of the global nesting level across all host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of lower priority) that are nested out because of a current interrupt. This register is only available when nesting is configured." hexmask.long.word 0x0 0.--8. 1. " GLB_NEST_LEVEL ,The current global nesting level (highest channel that is nested). Writes set the nesting level. In auto nesting mode this value is updated internally unless the auto_override bit is set." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Always read as 0. Writes of 1 override the automatic nesting and set the nesting_level to the written data." "0,1" group.byte 0x20++0x3 line.long 0x0 "PRUSS_INTC_SISR,The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to set is the index value written. This sets the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STATUS_SET_INDEX ,Writes set the status of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRUSS_INTC_SICR,The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STATUS_CLR_INDEX ,Writes clear the status of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_INTC_EISR,The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is the index value written. This sets the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " ENABLE_SET_INDEX ,Writes set the enable of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_INTC_EICR,The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable is the index value written. This clears the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " ENABLE_CLR_INDEX ,Writes clear the enable of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_INTC_HIEISR,The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if already enabled." hexmask.long.word 0x0 0.--9. 1. " HINT_ENABLE_SET_INDEX ,Writes set the enable of the host interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PRUSS_INTC_HIDISR,The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host interrupt to disable is the index value written. This disables the host interrupt output." hexmask.long.word 0x0 0.--9. 1. " HINT_ENABLE_CLR_INDEX ,Writes clear the enable of the host interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PRUSS_INTC_GPIR,The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts." hexmask.long.word 0x0 0.--9. 1. " GLB_PRI_INTR ,The currently highest priority interrupt index pending across all the host interrupts." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " GLB_NONE ,No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending." "0,1" group.byte 0x200++0x3 line.long 0x0 "PRUSS_INTC_SRSR0,The System Interrupt Status Raw Set Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " RAW_STATUS_31_0 ,System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.byte 0x204++0x3 line.long 0x0 "PRUSS_INTC_SRSR1,The System Interrupt Status Raw Set Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " RAW_STATUS_63_32 ,System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.byte 0x280++0x3 line.long 0x0 "PRUSS_INTC_SECR0,The System Interrupt Status Enabled Clear Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENA_STATUS_31_0 ,System interrupt enabled status and clearing of the system interrupts 0 to 31. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect." group.byte 0x284++0x3 line.long 0x0 "PRUSS_INTC_SECR1,The System Interrupt Status Enabled Clear Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENA_STATUS_63_32 ,System interrupt enabled status and clearing of the system interrupts 32 to 63. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect." group.byte 0x300++0x3 line.long 0x0 "PRUSS_INTC_ESR0,The System Interrupt Enable Set Register0 enables system interrupts 0 to 31 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_SET_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.byte 0x304++0x3 line.long 0x0 "PRUSS_INTC_ERS1,The System Interrupt Enable Set Register1 enables system interrupts 32 to 63 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_SET_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.byte 0x380++0x3 line.long 0x0 "PRUSS_INTC_ECR0,The System Interrupt Enable Clear Register0 disables system interrupts 0 to 31 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_CLR_31_0 ,System interrupt enables system interrupts 0 to 31. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.byte 0x384++0x3 line.long 0x0 "PRUSS_INTC_ECR1,The System Interrupt Enable Clear Register1 disables system interrupts 32 to 63 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_CLR_63_32 ,System interrupt enables system interrupts 32 to 63. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.byte 0x400++0x3 line.long 0x0 "PRUSS_INTC_CMRi_0,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x404++0x3 line.long 0x0 "PRUSS_INTC_CMRi_1,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x408++0x3 line.long 0x0 "PRUSS_INTC_CMRi_2,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_3,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x410++0x3 line.long 0x0 "PRUSS_INTC_CMRi_4,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x414++0x3 line.long 0x0 "PRUSS_INTC_CMRi_5,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x418++0x3 line.long 0x0 "PRUSS_INTC_CMRi_6,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x41C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_7,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x420++0x3 line.long 0x0 "PRUSS_INTC_CMRi_8,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x424++0x3 line.long 0x0 "PRUSS_INTC_CMRi_9,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x428++0x3 line.long 0x0 "PRUSS_INTC_CMRi_10,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x42C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_11,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x430++0x3 line.long 0x0 "PRUSS_INTC_CMRi_12,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x434++0x3 line.long 0x0 "PRUSS_INTC_CMRi_13,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x438++0x3 line.long 0x0 "PRUSS_INTC_CMRi_14,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x43C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_15,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x800++0x3 line.long 0x0 "PRUSS_INTC_HMR0,The Host Interrupt Map Register0 define the host interrupt for channels 0 to 3. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_0 ,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_1 ,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " HINT_MAP_2 ,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HINT_MAP_3 ,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x804++0x3 line.long 0x0 "PRUSS_INTC_HMR1,The Host Interrupt Map Register1 define the host interrupt for channels 4 to 7. There is one register per 4 channels. Chan_statusnels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_4 ,HOST INTERRUPT MAP FOR CHANNEL 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_5 ,HOST INTERRUPT MAP FOR CHANNEL 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " HINT_MAP_6 ,HOST INTERRUPT MAP FOR CHANNEL 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HINT_MAP_7 ,HOST INTERRUPT MAP FOR CHANNEL 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x808++0x3 line.long 0x0 "PRUSS_INTC_HMR2,The Host Interrupt Map Register2 define the host interrupt for channels 8 to 9. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_8 ,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_9 ,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x900++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_0,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x904++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_1,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x908++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_2,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x90C++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_3,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x910++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_4,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x914++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_5,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x918++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_6,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x91C++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_7,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x920++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_8,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x924++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_9,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0xD00++0x3 line.long 0x0 "PRUSS_INTC_SIPR0,The System Interrupt Polarity Register0 define the polarity of the system interrupts 0 to 31. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x0 0.--31. 1. " POLARITY_31_0 ,Interrupt polarity of the system interrupts 0 to 31. 0 = active low. 1 = active high." group.byte 0xD04++0x3 line.long 0x0 "PRUSS_INTC_SIPR1,The System Interrupt Polarity Register1 define the polarity of the system interrupts 32 to 63. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x0 0.--31. 1. " POLARITY_63_32 ,Interrupt polarity of the system interrupts 32 to 63. 0 = active low. 1 = active high." group.byte 0xD80++0x3 line.long 0x0 "PRUSS_INTC_SITR0,The System Interrupt Type Register0 define the type of the system interrupts 0 to 31. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_31_0 ,Interrupt type of the system interrupts 0 to 31. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.byte 0xD84++0x3 line.long 0x0 "PRUSS_INTC_SITR1,The System Interrupt Type Register1 define the type of the system interrupts 32 to 63. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_63_32 ,Interrupt type of the system interrupts 32 to 63. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.byte 0x1100++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_0,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1104++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_1,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1108++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_2,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x110C++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_3,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1110++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_4,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1114++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_5,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1118++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_6,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x111C++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_7,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1120++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_8,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1124++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_9,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1500++0x3 line.long 0x0 "PRUSS_INTC_HIER,The Host Interrupt Enable Registers enable or disable individual host interrupts. These work separately from the global enables. There is one bit per host interrupt. These bits are updated when writing to the Host Interrupt Enable Index Set and Host Interrupt Enable Index Clear registers." hexmask.long.word 0x0 0.--9. 1. " ENABLE_HINT ,The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "UART" base ad:0x4B228000 width 68. group.byte 0x0++0x3 line.long 0x0 "PRUSS_UART_RBR_THR_REGISTERS,In the non-FIFO mode, when a character is placed in Receiver buffer register and the receiver data-ready interrupt is enabled (DR = 1 in Interrupt identification register), an interrupt is generated. This interrupt is cleared when the character is read from Receiver buffer register. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register, and it is cleared when the FIFO contents drop below the trigger level. In the non-FIFO mode, if Transmitter holding register is empty and the THR empty (THRE) interrupt is enabled (ETBEI = 1 in Interrupt enable register), an interrupt is generated. This interrupt is cleared when a character is loaded into Transmitter holding register or the Interrupt identification register is read. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or Interrupt identification register is read." hexmask.long.byte 0x0 0.--7. 1. " DATA ,Read: Read Receive Buffer RegisterWrite: Write Transmitter Holding Register ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "PRUSS_UART_INTERRUPT_ENABLE_REGISTER,The Interrupt enable register is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in Interrupt enable register is forwarded to the CPU." bitfld.long 0x0 0. " ERBI ,Receiver data available interrupt and character timeout indication interrupt enable." "0,1" bitfld.long 0x0 1. " ETBEI ,Transmitter holding register empty interrupt enable." "0,1" textline " " bitfld.long 0x0 2. " ELSI ,Receiver line status interrupt enable." "0,1" bitfld.long 0x0 3. " EDSSI ,Enable Modem Status Interrupt" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "PRUSS_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER,The Interrupt identification register is a read-only register at the same address as the FIFO control register, which is a write-only register. When an interrupt is generated and enabled in the Interrupt enable register, Interrupt identification register indicates that an interrupt is pending in the IPEND bit and encodes the type of interrupt in the INTID bits. Reading Interrupt identification register clears any THR empty (THRE) interrupts that are pending. The FIFOEN bit in Interrupt identification register can be checked to determine whether the UART is in the FIFO mode or the non-FIFO mode. Use FIFO control register to enable and clear the FIFOs and to select the receiver FIFO trigger level. The FIFOEN bit in FIFO control register must be set to 1 before other FIFO control register bits are written to or the FIFO control register bits are not programmed." bitfld.long 0x0 0. " IPEND_FIFOEN ,Read: Interrupt pending. When any UART interrupt is generated and is enabled in IER, IPEND is forced to 0. IPEND remains 0 until all pending interrupts are cleared or until a hardware reset occurs. If no interrupts are enabled, IPEND is never forced to 0.Write: Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to or the FCR bits are not programmed. Clearing this bit clears the FIFO counters. ." "0,1" bitfld.long 0x0 1.--3. " INTID ,Read: Interrupt type. See .0x4-0x5: Reserved . Write: . Bit 3: DMAMODE1: DMA MODE1 enable if FIFOs are enabled. Always write 1 to DMAMODE1. After a hardware reset, change DMAMODE1 from 0 to 1. DMAMODE1 = 1 is a requirement for proper communication between the UART and the EDMA controller. . Bit 2: TXCLR: Transmitter FIFO clear. Write a 1 to TXCLR to clear the bit. . Bit 1: RXCLR: Receiver FIFO clear. Write a 1 to RXCLR to clear the bit. ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 6.--7. " FIFOEN_RXFIFTL ,Read: FIFOs enabled.0x1-0x2: Reserved . Write: Receiver FIFO trigger level. RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the FIFO drops below the trigger level, the interrupt is cleared. ." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "PRUSS_UART_LINE_CONTROL_REGISTER,The system programmer controls the format of the asynchronous data communication exchange by using Line control register. In addition, the programmer can retrieve, inspect, and modify the content of line control register; this eliminates the need for separate storage of the line characteristics in system memory." bitfld.long 0x0 0.--1. " WLS ,Word length select. Number of bits in each transmitted or received serial character. When STB = 1, the WLS bit determines the number of STOP bits." "0,1,2,3" bitfld.long 0x0 2. " STB ,Number of STOP bits generated. STB specifies 1, 1.5, or 2 STOP bits in each transmitted character. When STB = 1, the WLS bit determines the number of STOP bits. The receiver clocks only the first STOP bit, regardless of the number of STOP bits selected. The number of STOP bits generated is summarized in." "0,1" textline " " bitfld.long 0x0 3. " PEN ,Parity enable. The PEN bit works in conjunction with the SP and EPS bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" bitfld.long 0x0 4. " EPS ,Even parity select. Selects the parity when parity is enabled (PEN = 1). The EPS bit works in conjunction with the SP and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" textline " " bitfld.long 0x0 5. " SP ,Stick parity. The SP bit works in conjunction with the EPS and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" bitfld.long 0x0 6. " BC ,Break control." "0,1" textline " " bitfld.long 0x0 7. " DLAB ,Divisor latch access bit. The divisor latch registers (DLL and DLH) can be accessed at dedicated addresses or at addresses shared by RBR, THR, and IER. Using the shared addresses requires toggling DLAB to change which registers are selected. If the dedicated addresses are used, keep DLAB = 0." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "PRUSS_UART_MODEM_CONTROL_REGISTER,The Modem control register provides the ability to enable/disable the autoflow functions, and enable/disable the loopback function for diagnostic purposes." bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " RTS ,RTS control. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0." "0,1" textline " " bitfld.long 0x0 2. " OUT1 ,OUT1 Control Bit" "0,1" bitfld.long 0x0 3. " OUT2 ,OUT2 Control Bit" "0,1" textline " " bitfld.long 0x0 4. " LOOP ,Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature." "0,1" bitfld.long 0x0 5. " AFE ,Autoflow control enable. Autoflow control allows the and signals to provide handshaking between UARTs during data transfer. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "PRUSS_UART_LINE_STATUS_REGISTER,The Line status register provides information to the CPU concerning the status of data transfers. Line status register is intended for read operations only; do not write to this register. Bits 1 through 4 record the error conditions that produce a receiver line status interrupt." bitfld.long 0x0 0. " DR ,Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 1. " OE ,Overrun error (OE) indicator. An overrun error in the non-FIFO mode is different from an overrun error in the FIFO mode. If the OE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 2. " PE ,Parity error (PE) indicator. A parity error occurs when the parity of the received character does not match the parity selected with the EPS bit in the line control register (LCR). If the PE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 3. " FE ,Framing error (FE) indicator. A framing error occurs when the received character does not have a valid STOP bit. In response to a framing error, the UART sets the FE bit and waits until the signal on the RX pin goes high. Once the RX signal goes high, the receiver is ready to detect a new START bit and receive new data. If the FE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 4. " BI ,Break indicator. The BI bit is set whenever the receive data input (UARTn_RXD) was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the START, data, PARITY, and STOP bits. If the BI bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 5. " THRE ,Transmitter holding register empty (THRE) indicator. If the THRE bit is set and the corresponding interrupt enable bit is set (ETBEI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 6. " TEMT ,Transmitter empty (TEMT) indicator. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 7. " RXFIFOE ,Receiver FIFO error. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "PRUSS_UART_MODEM_STATUS_REGISTER,The Modem status register provides information to the CPU concerning the status of modem control signals. Modem status register is intended for read operations only; do not write to this register." bitfld.long 0x0 0. " DCTS ,Change in CTS indicator bit. DCTS indicates that the CTS input has changed state since the last time it was read by the CPU. When DCTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled, no interrupt is generated." "0,1" bitfld.long 0x0 1. " DDSR ,Change in DSR indicator bit. DDSR indicates that the DSR input has changed state since the last time it was read by the CPU. When DDSR is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" textline " " bitfld.long 0x0 2. " TERI ,Trailing edge of RI (TERI) indicator bit. TERI indicates that the RI input has changed from a low to a high. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" bitfld.long 0x0 3. " DCD ,Change in DCD indicator bit. DCD indicates that the DCD input has changed state since the last time it was read by the CPU. When DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" textline " " bitfld.long 0x0 4. " CTS ,Complement of the Clear To Send input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 1 (RTS)." "0,1" bitfld.long 0x0 5. " DSR ,Complement of the Data Set Ready input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 0 (DTR)." "0,1" textline " " bitfld.long 0x0 6. " RI ,Complement of the Ring Indicator input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 2 (OUT1)." "0,1" bitfld.long 0x0 7. " CD ,Complement of the Carrier Detect input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 3 (OUT2)." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_UART_SCRATCH_REGISTER,The Scratch Pad register is intended for programmer's use as a scratch pad. It temporarily holds the programmer's data without affecting UART operation." hexmask.long.byte 0x0 0.--7. 1. " SCR ,These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "PRUSS_UART_DIVISOR_REGISTER_LSB_,Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value." hexmask.long.byte 0x0 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "PRUSS_UART_DIVISOR_REGISTER_MSB_,Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value." hexmask.long.byte 0x0 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "PRUSS_UART_PERIPHERAL_ID_REGISTER,Peripheral Identification register" hexmask.long 0x0 0.--31. 1. " PID ," group.byte 0x30++0x3 line.long 0x0 "PRUSS_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER,Power and emulation management register" bitfld.long 0x0 0. " FREE ,Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When halted, the UART can handle register read/write requests, but does not generate any transmission/reception, interrupts or events." "0,1" hexmask.long.word 0x0 1.--12. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 13. " URRST ,UART receiver reset. Resets and enables the receiver." "0,1" bitfld.long 0x0 14. " UTRST ,UART transmitter reset. Resets and enables the transmitter." "0,1" textline " " bitfld.long 0x0 15. " RESERVED ,Reserved. This bit must always be written with a 0." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "PRUSS_UART_MODE_DEFINITION_REGISTER,The Mode definition register determines the over-sampling mode for the UART." bitfld.long 0x0 0. " OSM_SEL ,Over-Sampling Mode Select." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "ECAP" base ad:0x4B230000 width 19. group.byte 0x0++0x3 line.long 0x0 "PRUSS_ECAP_TSCNT,Time Stamp Counter Register" hexmask.long 0x0 0.--31. 1. " TSCNT ,Active 32 bit-counter register that is used as the capture time-base" group.byte 0x4++0x3 line.long 0x0 "PRUSS_ECAP_CNTPHS,Counter Phase Control Register" hexmask.long 0x0 0.--31. 1. " CNTPHS ,Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCNT and is loaded intoPRUSS_ECAP_TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM time-bases." group.byte 0x8++0x3 line.long 0x0 "PRUSS_ECAP_CAP1,Capture-1 Register" hexmask.long 0x0 0.--31. 1. " CAP1 ,This register can be loaded (written) by the following. (a) Time-Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0xC++0x3 line.long 0x0 "PRUSS_ECAP_CAP2,Capture-2 Register" hexmask.long 0x0 0.--31. 1. " CAP2 ,This register can be loaded (written) by the following. (a) Time- Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0x10++0x3 line.long 0x0 "PRUSS_ECAP_CAP3,Capture-3 Register" hexmask.long 0x0 0.--31. 1. " CAP3 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. User software updates the PWM period value through this register. In this mode, CAP3 shadows CAP1." group.byte 0x14++0x3 line.long 0x0 "PRUSS_ECAP_CAP4,Capture-4 Register" hexmask.long 0x0 0.--31. 1. " CAP4 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow (ACMP) register. User software updates the PWM compare value through this register. In this mode, CAP4 shadows CAP2." group.byte 0x28++0x1 line.word 0x0 "PRUSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select 0x0 = Capture Event 1 triggered on a rising edge (RE) 0x1 = Capture Event 1 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1 0x0 = Do not reset counter on Capture Event 1 (absolute time stamp) 0x1 = Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select 0x0 = Capture Event 2 triggered on a rising edge (RE) 0x1 = Capture Event 2 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2 0x0 = Do not reset counter on Capture Event 2 (absolute time stamp) 0x1 = Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select 0x0 = Capture Event 3 triggered on a rising edge (RE) 0x1 = Capture Event 3 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3 0x0 = Do not reset counter on Capture Event 3 (absolute time stamp) 0x1 = Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select 0x0 = Capture Event 4 triggered on a rising edge (RE) 0x1 = Capture Event 4 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4 0x0 = Do not reset counter on Capture Event 4 (absolute time stamp operation) 0x1 = Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading ofPRUSS_ECAP_CAP1 to PRUSS_ECAP_CAP4 registers on a capture event 0x0 = Disable PRUSS_ECAP_CAP1-PRUSS_ECAP_CAP4 register loads at capture event time. 0x1 = Enable PRUSS_ECAP_CAP1-PRUSS_ECAP_CAP4 register loads at capture event time." "0,1" bitfld.word 0x0 9.--13. " EVTFLTPS ,Event Filter prescale select: 0x0 = Divide by 1 (i.e,. no prescale, by-pass the prescaler) 0x1 = Divide by 2 0x2 = Divide by 4 0x3 = Divide by 6 0x4 = Divide by 8 0x5 = Divide by 10 0x1E = Divide by 60 0x1F = Divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control 0x0 = TSCNT counter stops immediately on emulation suspend. 0x1 = TSCNT counter runs until = 0. 0x2 = TSCNT counter is unaffected by emulation suspend (Run Free). 0x3 = TSCNT counter is unaffected by emulation suspend (Run Free)." "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "PRUSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x0 0. " CONTONESHT ,Continuous or one-shot mode control (applicable only in capture mode) 0x0 = Operate in continuous mode 0x1 = Operate in one-shot mode" "0,1" bitfld.word 0x0 1.--2. " STOPVALUE ,Stop value for one-shot mode. This is the number (between 1 and 4) of captures allowed to occur before the CAP (1 through 4) registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1 and 4) of the capture register in which the circular buffer wraps around and starts again. Notes: STOPVALUE is compared to Mod4 counter and, when equal, the following two actions occur. (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. In one-shot mode, further interrupt events are blocked until re-armed. 0x0 = Stop after Capture Event 1 in one-shot mode. Wrap after Capture Event 1 in continuous mode. 0x1 = Stop after Capture Event 2 in one-shot mode. Wrap after Capture Event 2 in continuous mode. 0x2 = Stop after Capture Event 3 in one-shot mode. Wrap after Capture Event 3 in continuous mode. 0x3 = Stop after Capture Event 4 in one-shot mode. Wrap after Capture Event 4 in continuous mode." "0,1,2,3" textline " " bitfld.word 0x0 3. " REARMRESET ,One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0x0 = Has no effect (reading always returns a 0) 0x1 = Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero. 2) Unfreezes the Mod4 counter. 3) Enables capture register loads." "0,1" bitfld.word 0x0 4. " TSCNTSTP ,Time Stamp (TSCNT) Counter Stop (freeze) Control 0x0 = TSCNT stopped 0x1 = TSCNT free-running" "0,1" textline " " bitfld.word 0x0 5. " SYNCI_EN ,Counter (TSCNT) Sync-In select mode 0x0 = Disable sync-in option 0x1 = Enable counter (TSCNT) to be loaded from" "0,1" bitfld.word 0x0 6.--7. " SYNCO_SEL ,Sync-Out Select 0x0 = Select sync-in event to be the sync-out signal (pass through) 0x1 = Select CTR = PRD event to be the sync-out signal 0x2 = Disable sync out signal 0x3 = Disable sync out signal" "0,1,2,3" textline " " bitfld.word 0x0 8. " SWSYNC ,Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via the CTR = PRD event. Note: Selection CTR = PRD is meaningful only in APWM mode. However, a choice of CAP mode is also available if it may be of use. 0x0 = Writing a zero has no effect. Reading always returns a zero 0x1 = Writing a one forces a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 1'b00. After writing a 1, this bit returns to a zero." "0,1" bitfld.word 0x0 9. " CAPAPWM ,CAP/APWM operating mode select 0x0 = ECAP module operates in capture mode. This mode forces the following configuration. 0x1 = ECAP module operates in APWM mode. This mode forces the following configuration." "0,1" textline " " bitfld.word 0x0 10. " APWMPOL ,APWM output polarity select. This is applicable only in APWM operating mode 0x0 = Output is active high (Compare value defines high time) 0x1 = Output is active low (Compare value defines low time)" "0,1" bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2C++0x1 line.word 0x0 "PRUSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Interrupt Enable. 0x0 = Disable Capture Event 1 as an Interrupt source. 0x1 = Enable Capture Event 1 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Interrupt Enable. 0x0 = Disable Capture Event 2 as an Interrupt source. 0x1 = Enable Capture Event 2 as an Interrupt source." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Interrupt Enable. 0x0 = Disable Capture Event 3 as an Interrupt source. 0x1 = Enable Capture Event 3 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Interrupt Enable. 0x0 = Disable Capture Event 4 as an Interrupt source. 0x1 = Enable Capture Event 4 as an Interrupt source." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Interrupt Enable. 0x0 = Disable counter Overflow as an Interrupt source. 0x1 = Enable counter Overflow as an Interrupt source." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal 0x0 = Disable Period Equal as an Interrupt source. 0x1 = Enable Period Equal as an Interrupt source." "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal 0x0 = Disable Compare Equal as an Interrupt source. 0x1 = Enable Compare Equal as an Interrupt source." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "PRUSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag 0x0 = Indicates no interrupt generated. 0x1 = Indicates that an interrupt was generated." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the first event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the second event occurred at ECAPn pin." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the third event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag This flag is only active in CAP mode. 0x0 = Indicates no event occurred 0x1 = Indicates the fourth event occurred at ECAPn pin" "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the counter (TSCNT) has made the transition from 0xFFFFFFFF to 0x00000000" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the period register value (APRD) and was reset." "0,1" bitfld.word 0x0 7. " CMPEQ ,Compare Equal Compare Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the compare register value (ACMP)" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "PRUSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT1 flag condition." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT2 flag condition." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CNTOVF flag condition" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CTR=PRD flag condition" "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal Compare Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CTR=CMP flag condition" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x34++0x1 line.word 0x0 "PRUSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Always reads back a 0. Force Capture Event 1 0x0 = No effect. 0x1 = Writing a 1 sets the CEVT1 flag bit." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Force Capture Event 2 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT2 flag bit." "0,1" bitfld.word 0x0 3. " CEVT3 ,Force Capture Event 3 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT3 flag bit" "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Force Capture Event 4 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT4 flag bit" "0,1" bitfld.word 0x0 5. " CNTOVF ,Force Counter Overflow 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 to this bit sets the CNTOVF flag bit." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Force Counter Equal Period Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CTR=PRD flag bit." "0,1" bitfld.word 0x0 7. " CMPEQ ,Force Counter Equal Compare Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CTR=CMP flag bit." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "PRUSS_ECAP_PID,ECAP Revision ID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "MII_RT" base ad:0x4B232000 width 23. group.byte 0x0++0x3 line.long 0x0 "PRUSS_MII_RT_RXCFG0,MII RXCFG 0 REGISTER This register contains the PRU0 RXCFG configuration variables () for the RX path. is attached to PRU0. controls which RX port is attached to PRU0." bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0 Disable 0x1 Enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is DA" "0,1" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1)" "0,1" textline " " bitfld.long 0x0 4. " RX_L2_EN ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: that if TX_AUTO_SEQUENCE enabled, this bit cannot get enable since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received. Must be selected /updated when the port is disabled or no traffic It only effects R31 and RX L2 order" "0,1" textline " " bitfld.long 0x0 6. " RX_AUTO_FWD_PRE ,Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1:Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE." "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRUSS_MII_RT_RXCFG1,This register contains the PRU1 RXCFG configuration variables () for the RX path. is attached to PRU1. controls which RX port is attached to PRU1" bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is destination address." "0,1" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1)" "0,1" textline " " bitfld.long 0x0 4. " RX_L2_EN ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: If TX_AUTO_SEQUENCE is enabled, this bit cannot get enabled since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received." "0,1" textline " " bitfld.long 0x0 6. " RX_AUTO_FWD_PRE ,Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1: Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PRUSS_MII_RT_TXCFG0,This register contains the configuration variables for the transmit path on the MII interface port 0. is attached to Port TX0. controls which PRU is selected for TX0" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency." "0,1" textline " " bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event.Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself." "0,1" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0)" "0,1" textline " " bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter. Also, the masking logic is disabled and only the MII data is used." "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration." bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the PRUSS_GICLK clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "PRUSS_MII_RT_TXCFG1,MII TXCFG 1 REGISTER This register contains the configuration variables for the transmit path on the MII interface port 1. is attached to Port TX1. controls which PRU is selected for TX1" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency." "0,1" textline " " bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event.Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself." "0,1" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0)" "0,1" textline " " bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter.TX data from PRU1 is selected Also, the masking logic is disabled and only the MII data is used." "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration." bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the PRUSS_GICLK clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x20++0x3 line.long 0x0 "PRUSS_MII_RT_TX_CRC0,MII TXCRC 0 REGISTER It contains CRC32 which PRU0 reads" hexmask.long 0x0 0.--31. 1. " TX_CRC ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.byte 0x24++0x3 line.long 0x0 "PRUSS_MII_RT_TX_CRC1,MII TXCRC 1 REGISTER It contains CRC32 which PRU1 reads" hexmask.long 0x0 0.--31. 1. " TX_CRC ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.byte 0x30++0x3 line.long 0x0 "PRUSS_MII_RT_TX_IPG0,MII TXIPG 0 REGISTER" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_MII_RT_TX_IPG1,MII TXIPG 1 REGISTER" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PRUSS_MII_RT_PRS0,MII PORT STATUS 0 REGISTER" bitfld.long 0x0 0. " MII_COL ,Read the current state of pr1_mii0_col" "0,1" bitfld.long 0x0 1. " MII_CRS ,Read the current state of pr1_mii0_crs" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PRUSS_MII_RT_PRS1,MII PORT STATUS 1 REGISTER" bitfld.long 0x0 0. " MII_COL ,Read the current state of pr1_mii1_col" "0,1" bitfld.long 0x0 1. " MII_CRS ,Read the current state of pr1_mii1_crs" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PRUSS_MII_RT_RX_FRMS0,MII RXFRMS 0 REGISTER" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM ,Defines the maximum received frame count. If the total byte count of received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted." group.byte 0x44++0x3 line.long 0x0 "PRUSS_MII_RT_RX_FRMS1,MII RXFRMS 1 REGISTER" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM ,Defines the maximum received frame count. If the total byte count of the received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted." group.byte 0x48++0x3 line.long 0x0 "PRUSS_MII_RT_RX_PCNT0,MII RXPCNT 0 REGISTER" bitfld.long 0x0 0.--3. " RX_MIN_PCNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1 1 0x5 before 0xD5 0x2 2 0x5 before 0xD5 N min of N 0x5 before 0xD5 Note it does not need to be 0x5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_MAX_PCNT ,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted. Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "PRUSS_MII_RT_RX_PCNT1,MII RXPCNT 1 REGISTER" bitfld.long 0x0 0.--3. " RX_MIN_PCNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1: 1 0x5 before 0xD5 0x2: 2 0x5 before 0xD5 N: N 0x5 before 0xD5 Note it does not need to be 0x5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_MAX_PCNT ,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "PRUSS_MII_RT_RX_ERR0,MII RXERR 0 REGISTER" bitfld.long 0x0 0. " RX_MIN_PCNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 1. " RX_MAX_PCNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " bitfld.long 0x0 2. " RX_MIN_FRM_ERR ,Error status of received frame is less than the value of RX_MIN_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 3. " RX_MAX_FRM_ERR ,Error status of received frame is more than the value of RX_MAX_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "PRUSS_MII_RT_RX_ERR1,MII RXERR 1 REGISTER" bitfld.long 0x0 0. " RX_MIN_PCNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 1. " RX_MAX_PCNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " bitfld.long 0x0 2. " RX_MIN_FRM_ERR ,Error status of received frame is less than the value of RX_MIN_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 3. " RX_MAX_FRM_ERR ,Error status of received frame is more than the value of RX_MAX_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," width 0x0B tree.end tree "MII_MDIO" base ad:0x4B232400 width 31. group.byte 0x0++0x3 line.long 0x0 "PRUSS_MII_MDIO_VER,MDIO MODULE VERSION REGISTER" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4++0x3 line.long 0x0 "PRUSS_MII_MDIO_CONTROL,MDIO MODULE CONTROL REGISTER" hexmask.long.word 0x0 0.--15. 1. " CLKDIV ,Clock Divider. This field specifies the division ratio between CLK and the frequency of MDCLK. MDCLK is disabled when clkdiv is set to 0. MDCLK frequency = clk frequency/(clkdiv+1)." bitfld.long 0x0 16. " RESERVED ," "0,1" textline " " bitfld.long 0x0 17. " INT_TEST_ENABLE ,Interrupt test enable. This bit can be set to 1 to enable the host to set the userint and linkint bits for test purposes." "0,1" bitfld.long 0x0 18. " FAULT_DETECT_ENABLE ,Fault detect enable. This bit has to be set to 1 to enable the physical layer fault detection." "0,1" textline " " bitfld.long 0x0 19. " FAULT ,Fault indicator. This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them. This indicates a physical layer fault and the module state machine is reset. Writing a 1 to it clears this bit." "0,1" bitfld.long 0x0 20. " PREAMBLE ,Preamble disable. Writing a 1 to this bit disables this device from sending MDIO frame preambles." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel. This field specifies the highest useraccess channel that is available in the module and is currently set to 1. This implies thatMDIOUserAccess1 is the highest available user access channel." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 29. " RESERVED ," "0,1" bitfld.long 0x0 30. " ENABLE ,Enable control. Writing a 1 to this bit enables the MDIO state machine, writing a 0 disables it. If the MDIO state machine is active at the time it is disabled, it will complete the current operation before halting and setting the idle bit. If using byte access, the enable bit has to be the last bit written in this register." "0,1" textline " " bitfld.long 0x0 31. " IDLE ,MDIO state machine IDLE. Set to 1 when the state machine is in the idle state." "0,1" group.byte 0x8++0x3 line.long 0x0 "PRUSS_MII_MDIO_ALIVE,PHY ACKNOWLEDGE STATUS REGISTER" hexmask.long 0x0 0.--31. 1. " ALIVE ,MDIO Alive bitfield. Each of the 32 bits of this register is set if the most recent access to the PHY with address corresponding to the register bit number was acknowledged by the PHY, the bit is reset if the PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause the corresponding alive bit to be updated. The alive bits are only meant to be used to give an indication of the presence or not of a PHY with the corresponding address. Writing a 1 to any bit will clear it, writing a 0 has no effect." group.byte 0xC++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINK,PHY LINK STATUS REGISTER" hexmask.long 0x0 0.--31. 1. " LINK ,MDIO Link state. This register is updated after a read of the Generic Status Register of a PHY. The bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge the read transaction. Writes to the register have no effect. In addition, the status of the two PHYs specified in theMDIOUserPhySel registers can be determined using the MLINK input pins. This is determined by the linksel bit in the MDIOUserPhySel register." group.byte 0x10++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINKINTRAW,LINK STATUS CHANGE INTERRUPT REGISTER (RAW VALUE)" bitfld.long 0x0 0.--1. " LINKINTRAW ,MDIO link change event, raw value. When asserted 1, a bit indicates that there was anMDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register. linkintraw[0] and linkintraw[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the event and writing 0 has no effect.If the int_test bit in the MDIOControl register is set, the host may set the linkintraw bits to a 1.This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINKINTMASKED,LINK STATUS CHANGE INTERRUPT REGISTER (MASKED VALUE)" bitfld.long 0x0 0.--1. " LINKINTMASKED ,MDIO link change interrupt, masked value. When asserted 1, a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register and the corresponding linkint_enable bit was set.. linkintmasked[0] and linkintmasked[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the interrupt and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the linkint bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTRAW,USER COMMAND COMPLETE INTERRUPT REGISTER (RAW VALUE)" bitfld.long 0x0 0.--1. " USERINTRAW ,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed. Writing a 1 will clear the event and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the userintraw bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKED,USER COMMAND COMPLETE INTERRUPT REGISTER (MASKED VALUE)" bitfld.long 0x0 0.--1. " USERINTMASKED ,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed and the corresponding userintmaskset bit is set to 1.Writing a 1 will clear the interrupt and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the userintmasked bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKSET,USER INTERRUPT MASK SET REGISTER" bitfld.long 0x0 0.--1. " USERINTMASKEDSET ,MDIO user interrupt mask set for userintmasked[1:0], respectively. Writing a bit to 1 will enable MDIO user command complete interrupts for that particular MDIOUserAccess register. MDIO user interrupt for a particular MDIOUserAccess register is disabled if the corresponding bit is 0. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKCLR,USER INTERRUPT MASK CLEAR REGISTER" bitfld.long 0x0 0.--1. " USERINTMASKEDCLR ,MDIO user command complete interrupt mask clear for userintmasked[1:0], respectively. Writing a bit to 1 will disable further user command complete interrupts for that particular MDIOUserAccess register. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERACCESS0,USER ACCESS REGISTER0" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. This field specifies the PHY to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. This field specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last." "0,1" group.byte 0x84++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERPHYSEL0,USER PHY SELECT REGISTER0" bitfld.long 0x0 0.--4. " PHYADR_MON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINT_ENABLE ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERACCESS1,USER ACCESS REGISTER1" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. This field specifies the PHY to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. This field specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last." "0,1" group.byte 0x8C++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERPHYSEL1,USER PHY SELECT REGISTER1" bitfld.long 0x0 0.--4. " PHYADR_MON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINT_ENABLE ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," width 0x0B tree.end tree "IEP" base ad:0x4B22E000 width 29. group.byte 0x0++0x3 line.long 0x0 "PRUSS_IEP_GLOBAL_CFG,GLOBAL CFG" bitfld.long 0x0 0. " CNT_ENABLE ,Counter enable 0: Disables the counter. The counter maintains the current count. 1: Enables the counter." "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--7. " DEFAULT_INC ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 8.--19. 1. " CMP_INC ,Defines the increment value when compensation is active" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRUSS_IEP_GLOBAL_STATUS,STATUS" bitfld.long 0x0 0. " CNT_OVF ,Counter overflow status. 0: No overflow 1: Overflow occurred" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRUSS_IEP_COMPEN,COMPENSATION" hexmask.long.tbyte 0x0 0.--23. 1. " COMPEN_CNT ,Compensation counter. Read returns the current COMPEN_CNT value. 0: Compensation is disabled and counter will increment by DEFAULT_INC. n: Compensation is enabled until COMPEN_CNT decrements to 0. The COMPEN_CNT value decrements on every iep_clk cycle. When COMPEN_CNT is greater than 0, then count value increments by CMP_INC." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "PRUSS_IEP_COUNT,COUNTER" hexmask.long 0x0 0.--31. 1. " COUNT ,32-bit count value.t Increments by (DEFAULT_INC or CMP_INC) on every positive edge of PRUSS_IEP_CLK (200MHz) or PRUSS_GICLK." group.byte 0x10++0x3 line.long 0x0 "PRUSS_IEP_CAP_CFG,CAPTURE CFG" bitfld.long 0x0 0.--5. " CAP_1ST_EVENT_EN ,Capture 1-st Event Enable for n 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CAP6R_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[6] rise 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" textline " " bitfld.long 0x0 7. " CAP6F_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[6] fall 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" bitfld.long 0x0 8. " CAP7R_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[7] rise 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" textline " " bitfld.long 0x0 9. " CAP7F_1ST_EVENT_EN ,Capture 1st Event Enable for cap[7] fall 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" hexmask.long.byte 0x0 10.--17. 1. " CAP_ASYNC_EN ,Synchronization of the capture inputs to the PRUSS_IEP_CLK/PRUSS_GICLK enable. Note if input capture signal is asynchronous to PRUSS_IEP_CLK, enabling synchronization will cause the capture contents to be invalid. CAP_ASYNC_EN[n] maps to CAPR[n]. 0: Disable synchronization 1: Enable synchronization" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_IEP_CAP_STATUS,CAPTURE STATUS CFG" bitfld.long 0x0 0.--5. " CAPR_VALID ,Valid Status capr_valid<n> maps PRUSS_IEP_CAPR<n>_REG, where n=0 to 5, 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CAPR6_VALID ,Valid Status forPRUSS_IEP_CAPR6 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" textline " " bitfld.long 0x0 7. " CAPF6_VALID ,Valid Status forPRUSS_IEP_CAPF6 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" bitfld.long 0x0 8. " CAPR7_VALID ,Valid Status forPRUSS_IEP_CAPR7 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" textline " " bitfld.long 0x0 9. " CAPF7_VALID ,Valid Status forPRUSS_IEP_CAPF7 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" bitfld.long 0x0 10. " CAP_VALID ,Valid status for capture function. Reflects the ORed result from PRUSS_IEP_CAP_STATUS [9:0]. 0: No Hit for any capture event, i.e., there are all 0 in PRUSS_IEP_CAP_STATUS [9:0]. 1: Hit for 1 or more captures events is pending, i.e., there has at least one value equal to 1 in PRUSS_IEP_CAP_STATUS [9:0]." "0,1" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 16.--23. 1. " CAP_RAW ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]. 0: Current state is low for cap<n> 1: Current state is high for cap<n>" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_0,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_1,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x20++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_2,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x24++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_3,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x28++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_4,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_5,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x30++0x3 line.long 0x0 "PRUSS_IEP_CAPR6,CAPTURE RISE6" hexmask.long 0x0 0.--31. 1. " CAPR6 ,Capture Value for capr6 (rise) event" group.byte 0x34++0x3 line.long 0x0 "PRUSS_IEP_CAPF6,CAPTURE FALL6" hexmask.long 0x0 0.--31. 1. " CAPF6 ,Capture Value for capf6 (fall) event" group.byte 0x38++0x3 line.long 0x0 "PRUSS_IEP_CAPR7,CAPTURE RISE7" hexmask.long 0x0 0.--31. 1. " CAPR7 ,Capture Value for capr7 (rise) event" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_IEP_CAPF7,CAPTURE FALL7" hexmask.long 0x0 0.--31. 1. " CAPF7 ,Capture Value for capf7 (fall) event" group.byte 0x40++0x3 line.long 0x0 "PRUSS_IEP_CMP_CFG,COMPARE CFG" bitfld.long 0x0 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter 0: Disable 1: Enable the reset of the counter if a cmp0 event occurs" "0,1" hexmask.long.byte 0x0 1.--8. 1. " CMP_EN ,Enable bit for each of the compare registers cmp_en<n> =0: Disables CMP<n> Event cmp_en<n> =1: Enables CMP<n> Event cmp_en[0] maps to CMP0" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "PRUSS_IEP_CMP_STATUS,COMPARE STATUS" hexmask.long.byte 0x0 0.--7. 1. " CMP_HIT ,Status bit for each of the compare registers. 'Match' indicates the current counter is greater than or equal to the compare value. Note it is the firmware's responsibility to handle the IEP overflow. cmp_hit<n> = 0: No match has occured cmp_hit<n> = 1: A match occured. The associated hardware event signal will assert and remain high until the status is cleared." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "PRUSS_IEP_CMPj_0,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_IEP_CMPj_1,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x50++0x3 line.long 0x0 "PRUSS_IEP_CMPj_2,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x54++0x3 line.long 0x0 "PRUSS_IEP_CMPj_3,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x58++0x3 line.long 0x0 "PRUSS_IEP_CMPj_4,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_IEP_CMPj_5,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x60++0x3 line.long 0x0 "PRUSS_IEP_CMPj_6,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x64++0x3 line.long 0x0 "PRUSS_IEP_CMPj_7,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x80++0x3 line.long 0x0 "PRUSS_IEP_RXIPG0,RXIPG0This register can be used to determine the last RX IPG and the smallest RX IPG. RXIPG0 is the status for the RX port which is attached to PRU0." hexmask.long.word 0x0 0.--15. 1. " RX_IPG ,Records the current number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. Value is updated after RX_DV transitions from low to high. It will saturate at 0xffff." hexmask.long.word 0x0 16.--31. 1. " RX_MIN_IPG ,Defines the current minimum number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that is RXDV is sampled low. It stores the current smallest RX_IPG Read: The value can be read at any time. It gets updated after RX_IPG update if RX_MIN_IPG > RX_IPG. Write:Any write will reset this bitfield to 0xffff" group.byte 0x84++0x3 line.long 0x0 "PRUSS_IEP_RXIPG1,RXIPG1This register can be used to determine the last RX IPG and the smallest RX IPG. RXIPG1 is the status for the RX port which is attached to PRU1" hexmask.long.word 0x0 0.--15. 1. " RX_IPG ,Records the current number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. Value is updated after RX_DV transitions from low to high. It will saturate at 0xffff." hexmask.long.word 0x0 16.--31. 1. " RX_MIN_IPG ,Defines the current minimum number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. It stores the current smallest RX_IPG Read: The value can be read at any time. It gets updated after RX_IPG update if RX_MIN_IPG > RX_IPG. Write:Any write will reset this bitfield to 0xffff" group.byte 0x100++0x3 line.long 0x0 "PRUSS_IEP_SYNC_CTRL,SYNC CTRL" bitfld.long 0x0 0. " SYNC_EN ,SYNC generation enable 0: Disable the generation and clocking of SYNC0 and SYNC1 logic 1: Enables SYNC0 and SYNC1 generation" "0,1" bitfld.long 0x0 1. " SYNC0_EN ,SYNC0 generation enable 0: Disable SYNC0 generation 1: Enable SYNC0 generation" "0,1" textline " " bitfld.long 0x0 2. " SYNC1_EN ,SYNC1 generation enable 0: Disable SYNC1 generation 1: Enable SYNC1 generation" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " SYNC0_ACK_EN ,SYNC0 acknowledgement mode enable 0h: Disable, SYNC0 will go low after pulse width is met. 1: Enables acknowledge mode, when enabled SYNC0 will 1h: Enable, SYNC0 will remain asserted until receiving software acknowledges by reading PRUSS_IEP_SYNC0_STAT which clears on read." "0,1" bitfld.long 0x0 5. " SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable 0h: Disable, single shot mode 1h: Enable, cyclic generation mode" "0,1" textline " " bitfld.long 0x0 6. " SYNC1_ACK_EN ,SYNC1 acknowledgement mode enable 0h: Disable, SYNC1 will go low after pulse width is met. 1h: Enable, SYNC1 will remain asserted until receiving software acknowledges by reading PRUSS_IEP_SYNC1_ STAT which clears on read." "0,1" bitfld.long 0x0 7. " SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable 0: Disable, single shot mode 1:Enable, cyclic generation mode" "0,1" textline " " bitfld.long 0x0 8. " SYNC1_IND_EN ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0. 0: Dependent mode 1: Independent mode" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "PRUSS_IEP_SYNC_FIRST_STAT,SYNC CTRL" bitfld.long 0x0 0. " FIRST_SYNC0 ,SYNC0 First Event status 0: SYNC0 first event has not occurred 1: SYNC0 first event has occurred. This bits is cleared when sync0_en = 0" "0,1" bitfld.long 0x0 1. " FIRST_SYNC1 ,SYNC1 First Event status 0: SYNC1 first event has not occurred 1: SYNC1 first event has occurred. This bits is cleared when sync1_en = 0" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "PRUSS_IEP_SYNC0_STAT,SYNC CTRL" bitfld.long 0x0 0. " SYNC0_PEND ,SYNC0 pending state 0: SYNC0 is not pending 1 SYNC0 is pending or has occurred when SYNC0_ACK_EN = 0 (Disable). Write '1' to clear" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "PRUSS_IEP_SYNC1_STAT,SYNC CTRL" bitfld.long 0x0 0. " SYNC1_PEND ,SYNC1 pending state 0: SYNC1 is not pending 1 SYNC1 is pending or has occurred when SYNC1_ACK_EN = 0 (Disable). Write '1' to Clear" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "PRUSS_IEP_SYNC_PWIDTH,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC_HPW ,Defines the number of clock cycles SYNC0/1 will be high. Note if SYNC0/1 is disabled during pulse width time (that is, SYNC_CTRL[SYNC0_EN | SYNC1_EN | SYNC_EN] = 0), the ongoing pulse will be terminated. 0h: 1 clock cycle. 1h: 2 clock cycles. Nh: N+1 clock cycles." group.byte 0x114++0x3 line.long 0x0 "PRUSS_IEP_SYNC0_PERIOD,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC0_PERIOD ,Defines the period between the rising edges of SYNC0. 0x0: Reserved 0x1: 2 clk cycles period N: N+1 clk cycles period" group.byte 0x118++0x3 line.long 0x0 "PRUSS_IEP_SYNC1_DELAY,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC1_DELAY ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1. Note this is the delay before the start of SYNC1. 0h: No delay 1h: 1 clock cycle delay. Nh: N clock cycles delay. When SYNC1_IND_EN = 1, defines the period between the rising edges of SYNC1. 0h: Reserved. 1h: 2 clock cycles period. Nh: N+1 clock cycles period." group.byte 0x11C++0x3 line.long 0x0 "PRUSS_IEP_SYNC_START,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC_START ,Defines the start time after the activation event. 0h: 1 clock cycle delay. Nh: N+1 clock cycles delay." group.byte 0x200++0x3 line.long 0x0 "PRUSS_IEP_WD_PREDIV,WD" hexmask.long.word 0x0 0.--15. 1. " PRE_DIV ,Defines the number of iep_clk cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if iep_clk is 200 MHz. seconds/(WD event) = (clock cycles per WD event)/(clock cycles per second) = 20000/(200 x [10]^6 ) = 100 us" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x204++0x3 line.long 0x0 "PRUSS_IEP_PDI_WD_TIM,WD" hexmask.long.word 0x0 0.--15. 1. " PDI_WD_TIME ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRE_DIV is set to 100 us, then the value 0x03e8 (or 1000) provides a rate of 100ms. Read returns the current count. Counter is reset by software write to register or when Digital Data In capture occurs. WD is disabled if WD time is set to 0x0. Note when an expiration event occurs, the expiration counter (PDI_EXP_CNT) increments and status (PDI_WD_STAT) clears." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "PRUSS_IEP_PD_WD_TIM,WD" hexmask.long.word 0x0 0.--15. 1. " PD_WD_TIME ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRE_DIV is set to 100 us, then 0x03e8 (or 1000) provides a rate of 100ms Read returns the current count. Counter is reset by software write to register or every write access to Sync Managers with WD trigger enable bit set. WD is disabled if WD time is set to 0x0. Expiration actions: Increment expiration counter, clear status. Digital Data out forced to zero if pr1_edio_oe_ext = 1 and PRUSS_IEP_DIGIO_EXT.SW_DATA_OUT_UPDATE = 0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "PRUSS_IEP_WD_STATUS,WD" bitfld.long 0x0 0. " PD_WD_STAT ,WD PD status (triggered by Sync Mangers status). 0h: Expired (PD_WD_EXP event generated) 1h: Active or disabled" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " PDI_WD_STAT ,WD PDI status. 0h: Expired (PDI_WD_EXP event generated) 1h: Active or disabled" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "PRUSS_IEP_WD_EXP_CNT,WD" hexmask.long.byte 0x0 0.--7. 1. " PDI_EXP_CNT ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh." hexmask.long.byte 0x0 8.--15. 1. " PD_EXP_CNT ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "PRUSS_IEP_WD_CTRL,WD" bitfld.long 0x0 0. " PD_WD_EN ,Watchdog PD 0: Disable 1: Enable" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " PDI_WD_EN ,Watchdog PDI 0: Disable 1: Enable" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x300++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_CTRL,DIGIO" bitfld.long 0x0 0. " OUTVALID_POL ,Indicates OUTVALID polarity" "0,1" bitfld.long 0x0 1. " OUTVALID_MODE ,Defines OUTVALID mode" "0,1" textline " " bitfld.long 0x0 2. " BIDI_MODE ,Indicates the digital input/output direction. DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1" bitfld.long 0x0 3. " WD_MODE ,Defines Watchdog behavior" "0,1" textline " " bitfld.long 0x0 4.--5. " IN_MODE ,Defines event that triggers data in to be sampled 0b00: PRU0/1_RX_SOF 0b01: Rising edge of external pr<k>_edio_latch_in signal 0b10: DC rising edge of SYNC0 event 0b11: DC rising edge of SYNC1 event" "0,1,2,3" bitfld.long 0x0 6.--7. " OUT_MODE ,Defines event that triggers data out to be updated." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x308++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_IN,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_IN ,Data input. Digital inputs can be configured to be sampled in four ways. 1: Digital inputs are sampled at the start of each frame. The SOF signal can be used externally to update the input data, because the SOF is signaled before input data is sampled. 2: The sample time can be controlled externally by using the pr1_edio_latch_in signal. 3: Digital inputs are sampled at SYNC0 events. 4: Digital inputs are sampled at SYNC1 events. These can be configured by PRUSS_IEP_DIGIO_CTRL[5:4] IN_MODE. Only [7:0] are exported to device pins in this device." group.byte 0x30C++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_IN_RAW,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_IN_RAW ,Raw Data Input. Direct sample of EDIO_DATA_IN[31:0]. Only [7:0] are exported to device pins in this device." group.byte 0x310++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_OUT,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_OUT ,Data output. Digital outputs can be configured to be updated in four ways. 1: Digital outputs are updated at the end of each frame (EOF mode). 2: Digital outputs are updated with SYNC0 events 3: Digital outputs are updated SYNC1events. 4: Digital outputs are updated at the end of a frame which triggered the Process Data Watchdog. Digital Outputs are only updated if the frame was correct (WD_TRIG mode). These can be configured by out_mode." group.byte 0x314++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_OUT_EN,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_OUT_EN ,Enables tri-state control for pr<k>_edio_data_out[7:0]." group.byte 0x318++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_EXP,DIGIO" bitfld.long 0x0 0. " SW_DATA_OUT_UPDATE ,Defines the value of pr1_edio_data_out when OUTVALID_OVR_EN = 1. Read 1: Start bit event occurred Read 0: Start bit event has not occurred Write 1: pr1_edio_data_out by software data out. Write 0: No Effect" "0,1" bitfld.long 0x0 1. " OUTVALID_OVR_EN ,Enable software to control value of pr<k>_edio_data_out [7:0]. 0: Disable 1: Enable" "0,1" textline " " bitfld.long 0x0 2. " SW_OUTVALID ,pr1_edio_outvalid = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--7. " OUTVALID_DLY ,Define the number of iep_clk (PRUSS_IEP_CLK) cycle delay on assertion of PR1_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " SOF_DLY ,Define the number of iep_clk (PRUSS_IEP_CLK) cycle delay of SOF PR1_EDIO_DATA_IN[31:0] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12. " SOF_SEL ,Defines with RX_SOF is used for PR1_EDIO_DATA_IN[31:0] capture" "0,1" bitfld.long 0x0 13. " EOF_SEL ,Defines with RX_EOF is used for PR1_EDIO_DATA_IN[31:0] capture" "0,1" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS1_DEBUG" base ad:0x20AA2400 width 20. group.byte 0x0++0x3 line.long 0x0 "PRUSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4++0x3 line.long 0x0 "PRUSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x8++0x3 line.long 0x0 "PRUSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0xC++0x3 line.long 0x0 "PRUSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x10++0x3 line.long 0x0 "PRUSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x14++0x3 line.long 0x0 "PRUSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x18++0x3 line.long 0x0 "PRUSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x20++0x3 line.long 0x0 "PRUSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x24++0x3 line.long 0x0 "PRUSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x28++0x3 line.long 0x0 "PRUSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x30++0x3 line.long 0x0 "PRUSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x34++0x3 line.long 0x0 "PRUSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x38++0x3 line.long 0x0 "PRUSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x40++0x3 line.long 0x0 "PRUSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x44++0x3 line.long 0x0 "PRUSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x48++0x3 line.long 0x0 "PRUSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x50++0x3 line.long 0x0 "PRUSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x54++0x3 line.long 0x0 "PRUSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x58++0x3 line.long 0x0 "PRUSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x60++0x3 line.long 0x0 "PRUSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x64++0x3 line.long 0x0 "PRUSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x68++0x3 line.long 0x0 "PRUSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x6C++0x3 line.long 0x0 "PRUSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x70++0x3 line.long 0x0 "PRUSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x74++0x3 line.long 0x0 "PRUSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x78++0x3 line.long 0x0 "PRUSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x7C++0x3 line.long 0x0 "PRUSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG31 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x80++0x3 line.long 0x0 "PRUSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x84++0x3 line.long 0x0 "PRUSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x88++0x3 line.long 0x0 "PRUSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x8C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x90++0x3 line.long 0x0 "PRUSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x94++0x3 line.long 0x0 "PRUSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x98++0x3 line.long 0x0 "PRUSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x9C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xAC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xBC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xCC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xDC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xE0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c24_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00000n00, n=c24_blk_index[3:0]." group.byte 0xE4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c25_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00002n00, n=c25_blk_index[3:0]." group.byte 0xE8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c26_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x0002En00, n=c26_blk_index[3:0]." group.byte 0xEC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c27_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00032n00, n=c27_blk_index[3:0]." group.byte 0xF0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c28_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x00nnnn00, nnnn=c28_pointer[15:0]." group.byte 0xF4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c29_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x49nnnn00, nnnn=c29_pointer[15:0]." group.byte 0xF8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c30_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x40nnnn00, nnnn=c30_pointer[15:0]." group.byte 0xFC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c31_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x80nnnn00, nnnn=c31_pointer[15:0]." width 0x0B tree.end tree "PRUSS2_DEBUG" base ad:0x20AE2400 width 20. group.byte 0x0++0x3 line.long 0x0 "PRUSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4++0x3 line.long 0x0 "PRUSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x8++0x3 line.long 0x0 "PRUSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0xC++0x3 line.long 0x0 "PRUSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x10++0x3 line.long 0x0 "PRUSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x14++0x3 line.long 0x0 "PRUSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x18++0x3 line.long 0x0 "PRUSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x20++0x3 line.long 0x0 "PRUSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x24++0x3 line.long 0x0 "PRUSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x28++0x3 line.long 0x0 "PRUSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x30++0x3 line.long 0x0 "PRUSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x34++0x3 line.long 0x0 "PRUSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x38++0x3 line.long 0x0 "PRUSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x40++0x3 line.long 0x0 "PRUSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x44++0x3 line.long 0x0 "PRUSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x48++0x3 line.long 0x0 "PRUSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x50++0x3 line.long 0x0 "PRUSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x54++0x3 line.long 0x0 "PRUSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x58++0x3 line.long 0x0 "PRUSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x60++0x3 line.long 0x0 "PRUSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x64++0x3 line.long 0x0 "PRUSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x68++0x3 line.long 0x0 "PRUSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x6C++0x3 line.long 0x0 "PRUSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x70++0x3 line.long 0x0 "PRUSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x74++0x3 line.long 0x0 "PRUSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x78++0x3 line.long 0x0 "PRUSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x7C++0x3 line.long 0x0 "PRUSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG31 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x80++0x3 line.long 0x0 "PRUSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x84++0x3 line.long 0x0 "PRUSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x88++0x3 line.long 0x0 "PRUSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x8C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x90++0x3 line.long 0x0 "PRUSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x94++0x3 line.long 0x0 "PRUSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x98++0x3 line.long 0x0 "PRUSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x9C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xAC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xBC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xCC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xDC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xE0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c24_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00000n00, n=c24_blk_index[3:0]." group.byte 0xE4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c25_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00002n00, n=c25_blk_index[3:0]." group.byte 0xE8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c26_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x0002En00, n=c26_blk_index[3:0]." group.byte 0xEC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c27_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00032n00, n=c27_blk_index[3:0]." group.byte 0xF0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c28_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x00nnnn00, nnnn=c28_pointer[15:0]." group.byte 0xF4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c29_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x49nnnn00, nnnn=c29_pointer[15:0]." group.byte 0xF8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c30_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x40nnnn00, nnnn=c30_pointer[15:0]." group.byte 0xFC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c31_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x80nnnn00, nnnn=c31_pointer[15:0]." width 0x0B tree.end tree.end tree.open "ICSS_1" tree "CFG" base eahb:0x4B2A6000 width 14. group.byte 0x0++0x3 line.long 0x0 "PRUSS_REVID,The Revision Register contains the ID and revision information." hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "PRUSS_SYSCFG,The System Configuration Register defines the power IDLE and STANDBY modes." bitfld.long 0x0 0.--1. " IDLE_MODE ,0x0 = Force-idle mode 0x1 = No-idle mode 0x2 = Smart-idle mode 0x3 = Reserved" "0,1,2,3" bitfld.long 0x0 2.--3. " STANDBY_MODE ,0x0 = Force standby mode: Initiator unconditionally in standby (standby = 1) 0x1 = No standby mode: Initiator unconditionally out of standby (standby = 0) 0x2 = Smart standby mode: Standby requested by initiator depending on internal conditions 0x3 = Reserved" "0,1,2,3" textline " " bitfld.long 0x0 4. " STANDBY_INIT ,0x1 = Initiate standby sequence. 0x0 = Enable OCP master ports." "0,1" bitfld.long 0x0 5. " SUB_MWAIT ,Status bit for wait state. 0x0 = Ready for Transaction 0x1 = Wait until 0" "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRUSS_GPCFG0,The General Purpose Configuration 0 Register defines the GPIO configuration for PRU0." bitfld.long 0x0 0.--1. " PRU0_GPI_MODE ,0x0 = Direct input mode 0x1 = 16-bit parallel capture mode 0x2 = 28-bit shift mode 0x3 = MII_RT mode" "0,1,2,3" bitfld.long 0x0 2. " PRU0_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0x0 = Use the positive edge of pru0_r31_status[16] 0x1 = Use the negative edge of pru0_r31_status[16]" "0,1" textline " " bitfld.long 0x0 3.--7. " PRU0_GPI_DIV0 ,Divisor value (divide by PRU0_GPI_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--12. " PRU0_GPI_DIV1 ,Divisor value (divide by PRU0_GPI_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13. " PRU0_GPI_SB ,Start Bit event for 28-bit shift mode. PRU0_GPI_SB (pru0_r31_status[29]) is set when first capture of a 1 on pru0_r31_status[0]. Read 1: Start Bit event occurred. Read 0: Start Bit event has not occurred. Write 1: Will clear PRU0_GPI_SB and clear the whole shift register. Write 0: No Effect." "0,1" bitfld.long 0x0 14. " PRU0_GPO_MODE ,0x0 = Direct output mode 0x1 = Serial output mode" "0,1" textline " " bitfld.long 0x0 15.--19. " PRU0_GPO_DIV0 ,Divisor value (divide by PRU0_GPO_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--24. " PRU0_GPO_DIV1 ,Divisor value (divide by PRU0_GPO_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25. " PRU0_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0x0 = gpo_sh0 is selected 0x1 = gpo_sh1 is selected" "0,1" bitfld.long 0x0 26.--29. " PR1_PRU0_GP_MUX_SEL ,Reserved. Keep at reset value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0xC++0x3 line.long 0x0 "PRUSS_GPCFG1,The General Purpose Configuration 1 Register defines the GPI O configuration for PRU1." bitfld.long 0x0 0.--1. " PRU1_GPI_MODE ,0x0 = Direct input mode 0x1 = 16-bit parallel capture mode 0x2 = 28-bit shift mode 0x3 = MII_RT mode" "0,1,2,3" bitfld.long 0x0 2. " PRU1_GPI_CLK_MODE ,Parallel 16-bit capture mode clock edge. 0x0 = Use the positive edge of pru1_r31_status[16] 0x1 = Use the negative edge of pru1_r31_status[16]" "0,1" textline " " bitfld.long 0x0 3.--7. " PRU1_GPI_DIV0 ,Divisor value (divide by PRU1_GPI_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 8.--12. " PRU1_GPI_DIV1 ,Divisor value (divide by PRU1_GPI_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 13. " PRU1_GPI_SB ,28-bit shift mode Start Bit event. PRU1_GPI_SB (pru1_r31_status[29]) is set when first capture of a 1 on pru1_r31_status[0]. Read 1: Start Bit event occurred. Read 0: Start Bit event has not occurred. Write 1: Will clear PRU1_GPI_SB and clear the whole shift register. Write 0: No Effect." "0,1" bitfld.long 0x0 14. " PRU1_GPO_MODE ,0x0 = Direct output mode 0x1 = Serial output mode" "0,1" textline " " bitfld.long 0x0 15.--19. " PRU1_GPO_DIV0 ,Divisor value (divide by PRU1_GPO_DIV0 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 20.--24. " PRU1_GPO_DIV1 ,Divisor value (divide by PRU1_GPO_DIV1 + 1). 0x00 = div 1.0 0x01 = div 1.5 0x02 = div 2.0 .. 0x1e = div 16.0 0x1f = reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 25. " PRU1_GPO_SH_SEL ,Defines which shadow register is currently getting used for GPO shifting. 0x0 = gpo_sh0 is selected 0x1 = gpo_sh1 is selected" "0,1" bitfld.long 0x0 26.--29. " PR1_PRU1_GP_MUX_SEL ,Reserved. Keep at reset value." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 30.--31. " RESERVED ," "0,1,2,3" group.byte 0x10++0x3 line.long 0x0 "PRUSS_CGR,The Clock Gating Register controls the state of Clock Management of the different modules. Software should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x1." bitfld.long 0x0 0. " PRU0_CLK_STOP_REQ ,PRU0 request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 1. " PRU0_CLK_STOP_ACK ,Acknowledgement that PRU0 clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 2. " PRU0_CLK_EN ,PRU0 clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 3. " PRU1_CLK_STOP_REQ ,PRU1 request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 4. " PRU1_CLK_STOP_ACK ,Acknowledgement that PRU1 clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 5. " PRU1_CLK_EN ,PRU1 clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " bitfld.long 0x0 6. " PRUSS_INTC_CLK_STOP_REQ ,PRUSS_INTC request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 7. " PRUSS_INTC_CLK_STOP_ACK ,Acknowledgement that PRUSS_INTC clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 8. " PRUSS_INTC_CLK_EN ,PRUSS_INTC clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 9. " UART_CLK_STOP_REQ ,UART request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 10. " UART_CLK_STOP_ACK ,Acknowledgement that UART clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 11. " UART_CLK_EN ,UART clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " bitfld.long 0x0 12. " ECAP_CLK_STOP_REQ ,ECAP request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" bitfld.long 0x0 13. " ECAP_CLK_STOP_ACK ,Acknowledgement that ECAP clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" textline " " bitfld.long 0x0 14. " ECAP_CLK_EN ,ECAP clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" bitfld.long 0x0 15. " IEP_CLK_STOP_REQ ,IEP request to stop clock. 0x0 = do not request to stop Clock 0x1 = request to stop Clock" "0,1" textline " " bitfld.long 0x0 16. " IEP_CLK_STOP_ACK ,Acknowledgement that IEP clock can be stopped. 0x0 = Not Ready to Gate Clock 0x1 = Ready to Gate Clock" "0,1" bitfld.long 0x0 17. " IEP_CLK_EN ,IEP clock enable. 0x0 = Disable Clock 0x1 = Enable Clock" "0,1" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_ISRP,The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRUSS memory parity events. The raw status is set even if the event is not enabled." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_RAW ,PRU0 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_IRAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_RAW ,PRU0 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_RAW ,PRU1 IMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_RAW ,PRU1 DMEM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE_RAW ,RAM Parity Error RAW for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_RAW[0] maps to Byte0. Write 0: No action. Read 0: No event pending. Read 1: Event pending. Write 1: Set event (debug)." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRUSS_ISP,The IRQ Status Parity Register is a snapshot of the IRQ status for the PRUSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE ,PRU0 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE ,PRU0 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No(enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE ,PRU1 IMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE ,PRU1 DMEM Parity Error for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE ,RAM Parity Error for Byte3, Byte2, Byte1, Byte0. Note RAM_PE[0] maps to Byte0. Write 0: No action. Read 0: No (enabled) event pending. Read 1: Event pending. Write 1: Clear event." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRUSS_IESP,The IRQ Enable Set Parity Register enables the IRQ PRUSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_SET ,PRU0 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_SET ,PRU0 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_SET ,PRU1 IMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_SET ,PRU1 DMEM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " RAM_PE_SET ,RAM Parity Error Set Enable for Byte3, Byte2, Byte1, Byte0. Note RAM_PE_SET[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Enable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRUSS_IECP,The IRQ Enable Clear Parity Register disables the IRQ PRUSS memory parity events." bitfld.long 0x0 0.--3. " PRU0_IMEM_PE_CLR ,PRU0 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " PRU0_DMEM_PE_CLR ,PRU0 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU0_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " PRU1_IMEM_PE_CLR ,PRU1 IMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_IMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " PRU1_DMEM_PE_CLR ,PRU1 DMEM Parity Error Clear Enable for Byte3, Byte2, Byte1, Byte0. Note PRU1_DMEM_PE_CLR[0] maps to Byte0. Write 0: No action. Read 0: Interrupt disabled (masked). Read 1: Interrupt enabled. Write 1: Disable interrupt." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_PMAO,The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at 0x0000_0000." bitfld.long 0x0 0. " PMAO_PRU0 ,PRU0 OCP Master Port Address Offset Enable. 0x0 = Disable address offset. 0x1 = Enable address offset of -0x0008_0000." "0,1" bitfld.long 0x0 1. " PMAO_PRU1 ,PRU1 OCP Master Port Address Offset Enable. 0x0 = Disable address offset. 0x1 = Enable address offset of -0x0008_0000." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_MII_RT,The MII_RT Event Enable Register enables MII_RT mode events to the PRUSS.PRUSS_INTC." bitfld.long 0x0 0. " OCP_EN ,IEP clock source 0x0 = IEP_CLK is the source 0x1 = ICLK is the source. While this is selected no transactions should be active. It can only be cleared by a hardware reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x30++0x3 line.long 0x0 "PRUSS_IEPCLK,The IEP Clock Source Register defines the source of the IEP clock." bitfld.long 0x0 0. " OCP_EN ,IEP clock source 0x0 = IEP_CLK is the source 0x1 = ICLK is the source. While this is selected no transactions should be active. It can only be cleared by a hardware reset." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_SPP,The Scratch Pad Priority and Configuration Register defines the access priority assigned to the PRU cores and configures the scratch pad XFR shift functionality." bitfld.long 0x0 0. " PRU1_PAD_HP_EN ,Defines which PRU wins write cycle arbitration to a common scratch pad bank. The PRU which has higher priority will always perform the write cycle with no wait states. The lower PRU will get stalled wait states until higher PRU is not performing write cycles. If the lower priority PRU writes to the same byte has the higher priority PRU, then the lower priority PRU will over write the bytes. 0x0 = PRU0 has highest priority. 0x1 = PRU1 has highest priority." "0,1" bitfld.long 0x0 1. " XFR_SHIFT_EN ,Enables XIN XOUT shift functionality. When enabled, R0[4:0] (internal to PRU) defines the 32-bit offset for XIN and XOUT operations with the scratch pad. 0x0 = Disabled. 0x1 = Enabled." "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PRUSS_PIN_MX,The Pin Mux Select Register defines the state of the PRUSS internal pinmuxing." hexmask.long.byte 0x0 0.--7. 1. " RESERVED ,Reserved" bitfld.long 0x0 8. " PWM0_REMAP_EN ,If enabled, host intr6 of PRUSS2 controls epwm_sync_in of PWMSS1 instead of ehrpwm1_synci device pin" "0,1" textline " " bitfld.long 0x0 9. " PWM3_REMAP_EN ,UNUSED IN THIS DEVICE" "0,1" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ,Reserved. Always write 0." width 0x0B tree.end tree "PRUSS1_CTRL" base eahb:0x4B2A2000 width 15. group.byte 0x0++0x3 line.long 0x0 "PRU_CONTROL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. 0 = PRU is disabled. 1 = PRU is enabled. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The pru_state bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1" textline " " bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x0 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. 0 = PRU will free run when enabled. 1 = PRU will execute a single instruction and then the pru_enable bit will be cleared. Note that this bit does not actually enable the PRU, it only sets the policy for how much code will be run after the PRU is enabled. The pru_enable bit must be explicitly asserted. It is legal to initialize both the single_step and pru_enable bits simultaneously. (Two independent writes are not required to cause the stated functionality.)" "0,1" textline " " bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 14. " BIG_ENDIAN ," "0,1" textline " " bitfld.long 0x0 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. 0 = PRU is halted and host has access to the instruction RAM and debug registers regions. 1 = PRU is currently running and the host is locked out of the instruction RAM and debug registers regions. This bit is used by an external debug agent to know when the PRU has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the pru_enable has been cleared." "0,1" hexmask.long.word 0x0 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.byte 0x4++0x3 line.long 0x0 "PRU_STATUS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter. Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20)." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRU_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core." group.byte 0xC++0x3 line.long 0x0 "PRU_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the COUNTENABLE bit in the PRU control register when the count reaches 0xFFFFFFFF. (Count does does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register." group.byte 0x10++0x3 line.long 0x0 "PRU_STALL,STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count." hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.byte 0x20++0x3 line.long 0x0 "PRU_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRU_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRU_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory." hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.byte 0x2C++0x3 line.long 0x0 "PRU_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table." hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0x0B tree.end tree "PRUSS2_CTRL" base eahb:0x4B2A4000 width 15. group.byte 0x0++0x3 line.long 0x0 "PRU_CONTROL,CONTROL REGISTER" bitfld.long 0x0 0. " SOFT_RST_N ,Soft Reset: When this bit is cleared, the PRU will be reset. This bit is set back to 1 on the next cycle after it has been cleared." "0,1" bitfld.long 0x0 1. " ENABLE ,Processor Enable: This bit controls whether or not the PRU is allowed to fetch new instructions. 0 = PRU is disabled. 1 = PRU is enabled. If this bit is de-asserted while the PRU is currently running and has completed the initial cycle of a multi-cycle instruction (LBxO,SBxO,SCAN, etc.), the current instruction will be allowed to complete before the PRU pauses execution. Otherwise, the PRU will halt immediately. Because of the unpredictability timing sensitivity of the instruction execution loop, this bit is not a reliable indication of whether or not the PRU is currently running. The pru_state bit should be consulted for an absolute indication of the run state of the core. When the PRU is halted, its internal state remains coherent therefore this bit can be reasserted without issuing a software reset and the PRU will resume processing exactly where it left off in the instruction stream." "0,1" textline " " bitfld.long 0x0 2. " SLEEPING ,PRU Sleep Indicator: This bit indicates whether or not the PRU is currently asleep. 0 = PRU is not asleep 1 = PRU is asleep If this bit is written to a 0, the PRU will be forced to power up from sleep mode." "0,1" bitfld.long 0x0 3. " COUNTER_ENABLE ,PRU Cycle Counter Enable: Enables PRU cycle counters. 0 = Counters not enabled 1 = Counters enabled" "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " SINGLE_STEP ,Single Step Enable: This bit controls whether or not the PRU will only execute a single instruction when enabled. 0 = PRU will free run when enabled. 1 = PRU will execute a single instruction and then the pru_enable bit will be cleared. Note that this bit does not actually enable the PRU, it only sets the policy for how much code will be run after the PRU is enabled. The pru_enable bit must be explicitly asserted. It is legal to initialize both the single_step and pru_enable bits simultaneously. (Two independent writes are not required to cause the stated functionality.)" "0,1" textline " " bitfld.long 0x0 9.--13. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 14. " BIG_ENDIAN ," "0,1" textline " " bitfld.long 0x0 15. " RUNSTATE ,Run State: This bit indicates whether the PRU is currently executing an instruction or is halted. 0 = PRU is halted and host has access to the instruction RAM and debug registers regions. 1 = PRU is currently running and the host is locked out of the instruction RAM and debug registers regions. This bit is used by an external debug agent to know when the PRU has actually halted when waiting for a HALT instruction to execute, a single step to finish, or any other time when the pru_enable has been cleared." "0,1" hexmask.long.word 0x0 16.--31. 1. " PCOUNTER_RST_VAL ,Program Counter Reset Value: This field controls the address where the PRU will start executing code from after it is taken out of reset." group.byte 0x4++0x3 line.long 0x0 "PRU_STATUS,STATUS REGISTER" hexmask.long.word 0x0 0.--15. 1. " PCOUNTER ,Program Counter: This field is a registered (1 cycle delayed) reflection of the PRU program counter. Note that the PC is an instruction address where each instruction is a 32 bit word. This is not a byte address and to compute the byte address just multiply the PC by 4 (PC of 2 = byte address of 0x8, or PC of 8 = byte address of 0x20)." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRU_WAKEUP_EN,WAKEUP ENABLE REGISTER" hexmask.long 0x0 0.--31. 1. " BITWISE_ENABLES ,Wakeup Enables: This field is ANDed with the incoming R31 status inputs (whose bit positions were specified in the stmap parameter) to produce a vector which is unary ORed to produce the status_wakeup source for the core. Setting any bit in this vector will allow the corresponding status input to wake up the core when it is asserted high. The PRU should set this enable vector prior to executing a SLP (sleep) instruction to ensure that the desired sources can wake up the core." group.byte 0xC++0x3 line.long 0x0 "PRU_CYCLE,CYCLE COUNT. This register counts the number of cycles for which the PRU has been enabled." hexmask.long 0x0 0.--31. 1. " CYCLECOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register). Counting halts while the PRU is disabled or counter is disabled, and resumes when re-eneabled. Counter clears the COUNTENABLE bit in the PRU control register when the count reaches 0xFFFFFFFF. (Count does does not wrap). The register can be read at any time. The register can be cleared when the counter or PRU is disabled. Clearing this register also clears the PRU Stall Count Register." group.byte 0x10++0x3 line.long 0x0 "PRU_STALL,STALL COUNT. This register counts the number of cycles for which the PRU has been enabled, but unable to fetch a new instruction. It is linked to the Cycle Count Register (0x0C) such that this register reflects the stall cycles measured over the same cycles as counted by the cycle count register. Thus the value of this register is always less than or equal to cycle count." hexmask.long 0x0 0.--31. 1. " STALLCOUNT ,This value is incremented by 1 for every cycle during which the PRU is enabled and the counter is enabled (both bits ENABLE and COUNTENABLE set in the PRU control register), and the PRU was unable to fetch a new instruction for any reason." group.byte 0x20++0x3 line.long 0x0 "PRU_CTBIR0,CONSTANT TABLE BLOCK INDEX REGISTER 0. This register is used to set the block indices which are used to modify entries 24 and 25 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C24_BLK_INDEX ,PRU Constant Entry 24 Block Index: This field sets the value that will appear in bits 11:8 of entry 24 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C25_BLK_INDEX ,PRU Constant Entry 25 Block Index: This field sets the value that will appear in bits 11:8 of entry 25 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRU_CTBIR1,CONSTANT TABLE BLOCK INDEX REGISTER 1. This register is used to set the block indices which are used to modify entries 26 and 27 in the PRU Constant Table. This register can be written by the PRU whenever it needs to change to a new base pointer for a block in the State Scratchpad RAM. This function is useful since the PRU is often processing multiple processing threads which require it to change contexts. The PRU can use this register to avoid requiring excessive amounts of code for repetitive context switching." hexmask.long.byte 0x0 0.--7. 1. " C26_BLK_INDEX ,PRU Constant Entry 26 Block Index: This field sets the value that will appear in bits 11:8 of entry 26 in the PRU Constant Table." hexmask.long.byte 0x0 8.--15. 1. " RESERVED ," textline " " hexmask.long.byte 0x0 16.--23. 1. " C27_BLK_INDEX ,PRU Constant Entry 27 Block Index: This field sets the value that will appear in bits 11:8 of entry 27 in the PRU Constant Table." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRU_CTPPR0,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 0. This register allows the PRU to set up the 256-byte page index for entries 28 and 29 in the PRU Constant Table which serve as general purpose pointers which can be configured to point to any locations inside the session router address map. This register is useful when the PRU needs to frequently access certain structures inside the session router address space whose locations are not hard coded such as tables in scratchpad memory." hexmask.long.word 0x0 0.--15. 1. " C28_POINTER ,PRU Constant Entry 28 Pointer: This field sets the value that will appear in bits 23:8 of entry 28 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C29_POINTER ,PRU Constant Entry 29 Pointer: This field sets the value that will appear in bits 23:8 of entry 29 in the PRU Constant Table." group.byte 0x2C++0x3 line.long 0x0 "PRU_CTPPR1,CONSTANT TABLE PROGRAMMABLE POINTER REGISTER 1. This register functions the same as the PRU Constant Table Programmable Pointer Register 0 but allows the PRU to control entries 30 and 31 in the PRU Constant Table." hexmask.long.word 0x0 0.--15. 1. " C30_POINTER ,PRU Constant Entry 30 Pointer: This field sets the value that will appear in bits 23:8 of entry 30 in the PRU Constant Table." hexmask.long.word 0x0 16.--31. 1. " C31_POINTER ,PRU Constant Entry 31 Pointer: This field sets the value that will appear in bits 23:8 of entry 31 in the PRU Constant Table." width 0x0B tree.end tree "INTC" base eahb:0x4B2A0000 width 21. group.byte 0x0++0x3 line.long 0x0 "PRUSS_INTC_REVID,Revision ID Register" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" group.byte 0x4++0x3 line.long 0x0 "PRUSS_INTC_CR,The Control Register holds global control parameters and can forces a soft reset on the module." bitfld.long 0x0 0. " RESERVED ," "0,1" bitfld.long 0x0 1. " WAKEUP_MODE ,Reserved" "0,1" textline " " bitfld.long 0x0 2.--3. " NEST_MODE ,The nesting mode. 0 = no nesting 1 = automatic individual nesting (per host interrupt) 2 = automatic global nesting (over all host interrupts) 3 = manual nesting" "0,1,2,3" bitfld.long 0x0 4. " PRIORITY_HOLD_MODE ,Reserved" "0,1" textline " " hexmask.long 0x0 5.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PRUSS_INTC_GER,The Global Host Interrupt Enable Register enables all the host interrupts. Individual host interrupts are still enabled or disabled from their individual enables and are not overridden by the global enable." bitfld.long 0x0 0. " ENABLE_HINT_ANY ,The current global enable value when read. Writes set the global enable." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x1C++0x3 line.long 0x0 "PRUSS_INTC_GNLR,The Global Nesting Level Register allows the checking and setting of the global nesting level across all host interrupts when automatic global nesting mode is set. The nesting level is the channel (and all of lower priority) that are nested out because of a current interrupt. This register is only available when nesting is configured." hexmask.long.word 0x0 0.--8. 1. " GLB_NEST_LEVEL ,The current global nesting level (highest channel that is nested). Writes set the nesting level. In auto nesting mode this value is updated internally unless the auto_override bit is set." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Always read as 0. Writes of 1 override the automatic nesting and set the nesting_level to the written data." "0,1" group.byte 0x20++0x3 line.long 0x0 "PRUSS_INTC_SISR,The System Interrupt Status Indexed Set Register allows setting the status of an interrupt. The interrupt to set is the index value written. This sets the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STATUS_SET_INDEX ,Writes set the status of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRUSS_INTC_SICR,The System Interrupt Status Indexed Clear Register allows clearing the status of an interrupt. The interrupt to clear is the index value written. This clears the Raw Status Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " STATUS_CLR_INDEX ,Writes clear the status of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_INTC_EISR,The System Interrupt Enable Indexed Set Register allows enabling an interrupt. The interrupt to enable is the index value written. This sets the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " ENABLE_SET_INDEX ,Writes set the enable of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_INTC_EICR,The System Interrupt Enable Indexed Clear Register allows disabling an interrupt. The interrupt to disable is the index value written. This clears the Enable Register bit of the given index." hexmask.long.word 0x0 0.--9. 1. " ENABLE_CLR_INDEX ,Writes clear the enable of the interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_INTC_HIEISR,The Host Interrupt Enable Indexed Set Register allows enabling a host interrupt output. The host interrupt to enable is the index value written. This enables the host interrupt output or triggers the output again if already enabled." hexmask.long.word 0x0 0.--9. 1. " HINT_ENABLE_SET_INDEX ,Writes set the enable of the host interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PRUSS_INTC_HIDISR,The Host Interrupt Enable Indexed Clear Register allows disabling a host interrupt output. The host interrupt to disable is the index value written. This disables the host interrupt output." hexmask.long.word 0x0 0.--9. 1. " HINT_ENABLE_CLR_INDEX ,Writes clear the enable of the host interrupt given in the index value. Reads return 0." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PRUSS_INTC_GPIR,The Global Prioritized Index Register shows the interrupt number of the highest priority interrupt pending across all the host interrupts." hexmask.long.word 0x0 0.--9. 1. " GLB_PRI_INTR ,The currently highest priority interrupt index pending across all the host interrupts." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " GLB_NONE ,No Interrupt is pending. Can be used by host to test for a negative value to see if no interrupts are pending." "0,1" group.byte 0x200++0x3 line.long 0x0 "PRUSS_INTC_SRSR0,The System Interrupt Status Raw Set Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " RAW_STATUS_31_0 ,System interrupt raw status and setting of the system interrupts 0 to 31. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.byte 0x204++0x3 line.long 0x0 "PRUSS_INTC_SRSR1,The System Interrupt Status Raw Set Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Set Registers to set a system interrupt without a hardware trigger. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " RAW_STATUS_63_32 ,System interrupt raw status and setting of the system interrupts 32 to 63. Reads return the raw status. Write a 1 in a bit position to set the status of the system interrupt. Writing a 0 has no effect." group.byte 0x280++0x3 line.long 0x0 "PRUSS_INTC_SECR0,The System Interrupt Status Enabled Clear Register0 show the pending enabled status of the system interrupts 0 to 31. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENA_STATUS_31_0 ,System interrupt enabled status and clearing of the system interrupts 0 to 31. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect." group.byte 0x284++0x3 line.long 0x0 "PRUSS_INTC_SECR1,The System Interrupt Status Enabled Clear Register1 show the pending enabled status of the system interrupts 32 to 63. Software can write to the Status Clear Registers to clear a system interrupt after it has been serviced. If a system interrupt status is not cleared then another host interrupt may not be triggered or another host interrupt may be triggered incorrectly. There is one bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENA_STATUS_63_32 ,System interrupt enabled status and clearing of the system interrupts 32 to 63. Reads return the enabled status (before enabling with the Enable Registers). Write a 1 in a bit position to clear the status of the system interrupt. Writing a 0 has no effect." group.byte 0x300++0x3 line.long 0x0 "PRUSS_INTC_ESR0,The System Interrupt Enable Set Register0 enables system interrupts 0 to 31 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_SET_31_0 ,System interrupt enables system interrupts 0 to 31. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.byte 0x304++0x3 line.long 0x0 "PRUSS_INTC_ERS1,The System Interrupt Enable Set Register1 enables system interrupts 32 to 63 to trigger outputs. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_SET_63_32 ,System interrupt enables system interrupts 32 to 63. Read returns the enable value (0 = disabled, 1 = enabled). Write a 1 in a bit position to set that enable. Writing a 0 has no effect." group.byte 0x380++0x3 line.long 0x0 "PRUSS_INTC_ECR0,The System Interrupt Enable Clear Register0 disables system interrupts 0 to 31 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_CLR_31_0 ,System interrupt enables system interrupts 0 to 31. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.byte 0x384++0x3 line.long 0x0 "PRUSS_INTC_ECR1,The System Interrupt Enable Clear Register1 disables system interrupts 32 to 63 to map to channels. System interrupts that are not enabled do not interrupt the host. There is a bit per system interrupt." hexmask.long 0x0 0.--31. 1. " ENABLE_CLR_63_32 ,System interrupt enables system interrupts 32 to 63. Write a 1 in a bit position to clear that enable. Writing a 0 has no effect." group.byte 0x400++0x3 line.long 0x0 "PRUSS_INTC_CMRi_0,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x404++0x3 line.long 0x0 "PRUSS_INTC_CMRi_1,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x408++0x3 line.long 0x0 "PRUSS_INTC_CMRi_2,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x40C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_3,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x410++0x3 line.long 0x0 "PRUSS_INTC_CMRi_4,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x414++0x3 line.long 0x0 "PRUSS_INTC_CMRi_5,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x418++0x3 line.long 0x0 "PRUSS_INTC_CMRi_6,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x41C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_7,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x420++0x3 line.long 0x0 "PRUSS_INTC_CMRi_8,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x424++0x3 line.long 0x0 "PRUSS_INTC_CMRi_9,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x428++0x3 line.long 0x0 "PRUSS_INTC_CMRi_10,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x42C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_11,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x430++0x3 line.long 0x0 "PRUSS_INTC_CMRi_12,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x434++0x3 line.long 0x0 "PRUSS_INTC_CMRi_13,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x438++0x3 line.long 0x0 "PRUSS_INTC_CMRi_14,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x43C++0x3 line.long 0x0 "PRUSS_INTC_CMRi_15,There are 16 identical CMR registers (i=0 to 15). The Channel Map Register_i specify the channel for the system interrupts k to k+3, where k=4*i. There is one register per 4 system interrupts." bitfld.long 0x0 0.--3. " CH_MAP_0 ,Sets the channel for the system interrupt k. Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " CH_MAP_1 ,Sets the channel for the system interrupt (k+1). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " CH_MAP_2 ,Sets the channel for the system interrupt (k+2). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " CH_MAP_3 ,Sets the channel for the system interrupt (k+3). Where k=i*4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x800++0x3 line.long 0x0 "PRUSS_INTC_HMR0,The Host Interrupt Map Register0 define the host interrupt for channels 0 to 3. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_0 ,HOST INTERRUPT MAP FOR CHANNEL 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_1 ,HOST INTERRUPT MAP FOR CHANNEL 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " HINT_MAP_2 ,HOST INTERRUPT MAP FOR CHANNEL 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HINT_MAP_3 ,HOST INTERRUPT MAP FOR CHANNEL 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x804++0x3 line.long 0x0 "PRUSS_INTC_HMR1,The Host Interrupt Map Register1 define the host interrupt for channels 4 to 7. There is one register per 4 channels. Chan_statusnels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_4 ,HOST INTERRUPT MAP FOR CHANNEL 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_5 ,HOST INTERRUPT MAP FOR CHANNEL 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 16.--19. " HINT_MAP_6 ,HOST INTERRUPT MAP FOR CHANNEL 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--23. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 24.--27. " HINT_MAP_7 ,HOST INTERRUPT MAP FOR CHANNEL 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 28.--31. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0x808++0x3 line.long 0x0 "PRUSS_INTC_HMR2,The Host Interrupt Map Register2 define the host interrupt for channels 8 to 9. There is one register per 4 channels. Channels with forced host interrupt mappings will have their fields read-only." bitfld.long 0x0 0.--3. " HINT_MAP_8 ,HOST INTERRUPT MAP FOR CHANNEL 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 8.--11. " HINT_MAP_9 ,HOST INTERRUPT MAP FOR CHANNEL 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0 12.--31. 1. " RESERVED ," group.byte 0x900++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_0,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x904++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_1,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x908++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_2,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x90C++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_3,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x910++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_4,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x914++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_5,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x918++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_6,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x91C++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_7,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x920++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_8,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0x924++0x3 line.long 0x0 "PRUSS_INTC_HIPIRj_9,The Host Interrupt Prioritized Index Register_j (where j=0 to 9) shows the highest priority current pending interrupt for the host interrupt j. There is one register per host interrupt." hexmask.long.word 0x0 0.--9. 1. " PRI_HINT ,HOST INT j PRIORITIZED INTERRUPT. Interrupt number of the highest priority pending interrupt for this host interrupt." hexmask.long.tbyte 0x0 10.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " NONE_HINT ,No pending interrupt." "0,1" group.byte 0xD00++0x3 line.long 0x0 "PRUSS_INTC_SIPR0,The System Interrupt Polarity Register0 define the polarity of the system interrupts 0 to 31. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x0 0.--31. 1. " POLARITY_31_0 ,Interrupt polarity of the system interrupts 0 to 31. 0 = active low. 1 = active high." group.byte 0xD04++0x3 line.long 0x0 "PRUSS_INTC_SIPR1,The System Interrupt Polarity Register1 define the polarity of the system interrupts 32 to 63. There is a polarity for each system interrupt. The polarity of all system interrupts is active high; always write 1 to the bits of this register." hexmask.long 0x0 0.--31. 1. " POLARITY_63_32 ,Interrupt polarity of the system interrupts 32 to 63. 0 = active low. 1 = active high." group.byte 0xD80++0x3 line.long 0x0 "PRUSS_INTC_SITR0,The System Interrupt Type Register0 define the type of the system interrupts 0 to 31. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_31_0 ,Interrupt type of the system interrupts 0 to 31. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.byte 0xD84++0x3 line.long 0x0 "PRUSS_INTC_SITR1,The System Interrupt Type Register1 define the type of the system interrupts 32 to 63. There is a type for each system interrupt. The type of all system interrupts is pulse; always write 0 to the bits of this register." hexmask.long 0x0 0.--31. 1. " TYPE_63_32 ,Interrupt type of the system interrupts 32 to 63. 0 = level or pulse interrupt. 1 = edge interrupt (required edge detect)." group.byte 0x1100++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_0,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1104++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_1,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1108++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_2,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x110C++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_3,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1110++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_4,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1114++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_5,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1118++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_6,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x111C++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_7,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1120++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_8,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1124++0x3 line.long 0x0 "PRUSS_INTC_HINLRj_9,The Host Interrupt Nesting Level Register_j (where j=0 to 9) display and control the nesting level for host interrupt j. The nesting level controls which channel and lower priority channels are nested. There is one register per host interrupt." hexmask.long.word 0x0 0.--8. 1. " NEST_HINT ,Reads return the current nesting level for the host interrupt. Writes set the nesting level for the host interrupt. In auto mode the value is updated internally unless the auto_override is set and then the write data is used." hexmask.long.tbyte 0x0 9.--30. 1. " RESERVED ," textline " " bitfld.long 0x0 31. " AUTO_OVERRIDE ,Reads return 0. Writes of a 1 override the auto updating of the nesting_level and use the write data." "0,1" group.byte 0x1500++0x3 line.long 0x0 "PRUSS_INTC_HIER,The Host Interrupt Enable Registers enable or disable individual host interrupts. These work separately from the global enables. There is one bit per host interrupt. These bits are updated when writing to the Host Interrupt Enable Index Set and Host Interrupt Enable Index Clear registers." hexmask.long.word 0x0 0.--9. 1. " ENABLE_HINT ,The enable of the host interrupts (one per bit). 0 = disabled 1 = enabled" hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," width 0x0B tree.end tree "UART" base eahb:0x4B2A8000 width 68. group.byte 0x0++0x3 line.long 0x0 "PRUSS_UART_RBR_THR_REGISTERS,In the non-FIFO mode, when a character is placed in Receiver buffer register and the receiver data-ready interrupt is enabled (DR = 1 in Interrupt identification register), an interrupt is generated. This interrupt is cleared when the character is read from Receiver buffer register. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register, and it is cleared when the FIFO contents drop below the trigger level. In the non-FIFO mode, if Transmitter holding register is empty and the THR empty (THRE) interrupt is enabled (ETBEI = 1 in Interrupt enable register), an interrupt is generated. This interrupt is cleared when a character is loaded into Transmitter holding register or the Interrupt identification register is read. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or Interrupt identification register is read." hexmask.long.byte 0x0 0.--7. 1. " DATA ,Read: Read Receive Buffer RegisterWrite: Write Transmitter Holding Register ." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x4++0x3 line.long 0x0 "PRUSS_UART_INTERRUPT_ENABLE_REGISTER,The Interrupt enable register is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in Interrupt enable register is forwarded to the CPU." bitfld.long 0x0 0. " ERBI ,Receiver data available interrupt and character timeout indication interrupt enable." "0,1" bitfld.long 0x0 1. " ETBEI ,Transmitter holding register empty interrupt enable." "0,1" textline " " bitfld.long 0x0 2. " ELSI ,Receiver line status interrupt enable." "0,1" bitfld.long 0x0 3. " EDSSI ,Enable Modem Status Interrupt" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ,Reserved" group.byte 0x8++0x3 line.long 0x0 "PRUSS_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER,The Interrupt identification register is a read-only register at the same address as the FIFO control register, which is a write-only register. When an interrupt is generated and enabled in the Interrupt enable register, Interrupt identification register indicates that an interrupt is pending in the IPEND bit and encodes the type of interrupt in the INTID bits. Reading Interrupt identification register clears any THR empty (THRE) interrupts that are pending. The FIFOEN bit in Interrupt identification register can be checked to determine whether the UART is in the FIFO mode or the non-FIFO mode. Use FIFO control register to enable and clear the FIFOs and to select the receiver FIFO trigger level. The FIFOEN bit in FIFO control register must be set to 1 before other FIFO control register bits are written to or the FIFO control register bits are not programmed." bitfld.long 0x0 0. " IPEND_FIFOEN ,Read: Interrupt pending. When any UART interrupt is generated and is enabled in IER, IPEND is forced to 0. IPEND remains 0 until all pending interrupts are cleared or until a hardware reset occurs. If no interrupts are enabled, IPEND is never forced to 0.Write: Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to or the FCR bits are not programmed. Clearing this bit clears the FIFO counters. ." "0,1" bitfld.long 0x0 1.--3. " INTID ,Read: Interrupt type. See .0x4-0x5: Reserved . Write: . Bit 3: DMAMODE1: DMA MODE1 enable if FIFOs are enabled. Always write 1 to DMAMODE1. After a hardware reset, change DMAMODE1 from 0 to 1. DMAMODE1 = 1 is a requirement for proper communication between the UART and the EDMA controller. . Bit 2: TXCLR: Transmitter FIFO clear. Write a 1 to TXCLR to clear the bit. . Bit 1: RXCLR: Receiver FIFO clear. Write a 1 to RXCLR to clear the bit. ." "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--5. " RESERVED ,Reserved" "0,1,2,3" bitfld.long 0x0 6.--7. " FIFOEN_RXFIFTL ,Read: FIFOs enabled.0x1-0x2: Reserved . Write: Receiver FIFO trigger level. RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the FIFO drops below the trigger level, the interrupt is cleared. ." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0xC++0x3 line.long 0x0 "PRUSS_UART_LINE_CONTROL_REGISTER,The system programmer controls the format of the asynchronous data communication exchange by using Line control register. In addition, the programmer can retrieve, inspect, and modify the content of line control register; this eliminates the need for separate storage of the line characteristics in system memory." bitfld.long 0x0 0.--1. " WLS ,Word length select. Number of bits in each transmitted or received serial character. When STB = 1, the WLS bit determines the number of STOP bits." "0,1,2,3" bitfld.long 0x0 2. " STB ,Number of STOP bits generated. STB specifies 1, 1.5, or 2 STOP bits in each transmitted character. When STB = 1, the WLS bit determines the number of STOP bits. The receiver clocks only the first STOP bit, regardless of the number of STOP bits selected. The number of STOP bits generated is summarized in." "0,1" textline " " bitfld.long 0x0 3. " PEN ,Parity enable. The PEN bit works in conjunction with the SP and EPS bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" bitfld.long 0x0 4. " EPS ,Even parity select. Selects the parity when parity is enabled (PEN = 1). The EPS bit works in conjunction with the SP and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" textline " " bitfld.long 0x0 5. " SP ,Stick parity. The SP bit works in conjunction with the EPS and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in." "0,1" bitfld.long 0x0 6. " BC ,Break control." "0,1" textline " " bitfld.long 0x0 7. " DLAB ,Divisor latch access bit. The divisor latch registers (DLL and DLH) can be accessed at dedicated addresses or at addresses shared by RBR, THR, and IER. Using the shared addresses requires toggling DLAB to change which registers are selected. If the dedicated addresses are used, keep DLAB = 0." "0,1" hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x10++0x3 line.long 0x0 "PRUSS_UART_MODEM_CONTROL_REGISTER,The Modem control register provides the ability to enable/disable the autoflow functions, and enable/disable the loopback function for diagnostic purposes." bitfld.long 0x0 0. " RESERVED ,Reserved" "0,1" bitfld.long 0x0 1. " RTS ,RTS control. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0." "0,1" textline " " bitfld.long 0x0 2. " OUT1 ,OUT1 Control Bit" "0,1" bitfld.long 0x0 3. " OUT2 ,OUT2 Control Bit" "0,1" textline " " bitfld.long 0x0 4. " LOOP ,Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature." "0,1" bitfld.long 0x0 5. " AFE ,Autoflow control enable. Autoflow control allows the and signals to provide handshaking between UARTs during data transfer. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0." "0,1" textline " " hexmask.long 0x0 6.--31. 1. " RESERVED ,Reserved" group.byte 0x14++0x3 line.long 0x0 "PRUSS_UART_LINE_STATUS_REGISTER,The Line status register provides information to the CPU concerning the status of data transfers. Line status register is intended for read operations only; do not write to this register. Bits 1 through 4 record the error conditions that produce a receiver line status interrupt." bitfld.long 0x0 0. " DR ,Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 1. " OE ,Overrun error (OE) indicator. An overrun error in the non-FIFO mode is different from an overrun error in the FIFO mode. If the OE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 2. " PE ,Parity error (PE) indicator. A parity error occurs when the parity of the received character does not match the parity selected with the EPS bit in the line control register (LCR). If the PE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 3. " FE ,Framing error (FE) indicator. A framing error occurs when the received character does not have a valid STOP bit. In response to a framing error, the UART sets the FE bit and waits until the signal on the RX pin goes high. Once the RX signal goes high, the receiver is ready to detect a new START bit and receive new data. If the FE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 4. " BI ,Break indicator. The BI bit is set whenever the receive data input (UARTn_RXD) was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the START, data, PARITY, and STOP bits. If the BI bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 5. " THRE ,Transmitter holding register empty (THRE) indicator. If the THRE bit is set and the corresponding interrupt enable bit is set (ETBEI = 1 in IER), an interrupt request is generated. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " bitfld.long 0x0 6. " TEMT ,Transmitter empty (TEMT) indicator. In non-FIFO mode:In FIFO mode: ." "0,1" bitfld.long 0x0 7. " RXFIFOE ,Receiver FIFO error. In non-FIFO mode:In FIFO mode: ." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x18++0x3 line.long 0x0 "PRUSS_UART_MODEM_STATUS_REGISTER,The Modem status register provides information to the CPU concerning the status of modem control signals. Modem status register is intended for read operations only; do not write to this register." bitfld.long 0x0 0. " DCTS ,Change in CTS indicator bit. DCTS indicates that the CTS input has changed state since the last time it was read by the CPU. When DCTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled, no interrupt is generated." "0,1" bitfld.long 0x0 1. " DDSR ,Change in DSR indicator bit. DDSR indicates that the DSR input has changed state since the last time it was read by the CPU. When DDSR is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" textline " " bitfld.long 0x0 2. " TERI ,Trailing edge of RI (TERI) indicator bit. TERI indicates that the RI input has changed from a low to a high. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" bitfld.long 0x0 3. " DCD ,Change in DCD indicator bit. DCD indicates that the DCD input has changed state since the last time it was read by the CPU. When DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated." "0,1" textline " " bitfld.long 0x0 4. " CTS ,Complement of the Clear To Send input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 1 (RTS)." "0,1" bitfld.long 0x0 5. " DSR ,Complement of the Data Set Ready input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 0 (DTR)." "0,1" textline " " bitfld.long 0x0 6. " RI ,Complement of the Ring Indicator input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 2 (OUT1)." "0,1" bitfld.long 0x0 7. " CD ,Complement of the Carrier Detect input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 3 (OUT2)." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_UART_SCRATCH_REGISTER,The Scratch Pad register is intended for programmer's use as a scratch pad. It temporarily holds the programmer's data without affecting UART operation." hexmask.long.byte 0x0 0.--7. 1. " SCR ,These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x20++0x3 line.long 0x0 "PRUSS_UART_DIVISOR_REGISTER_LSB_,Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value." hexmask.long.byte 0x0 0.--7. 1. " DLL ,The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x24++0x3 line.long 0x0 "PRUSS_UART_DIVISOR_REGISTER_MSB_,Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value." hexmask.long.byte 0x0 0.--7. 1. " DLH ,The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ,Reserved" group.byte 0x28++0x3 line.long 0x0 "PRUSS_UART_PERIPHERAL_ID_REGISTER,Peripheral Identification register" hexmask.long 0x0 0.--31. 1. " PID ," group.byte 0x30++0x3 line.long 0x0 "PRUSS_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER,Power and emulation management register" bitfld.long 0x0 0. " FREE ,Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When halted, the UART can handle register read/write requests, but does not generate any transmission/reception, interrupts or events." "0,1" hexmask.long.word 0x0 1.--12. 1. " RESERVED ,Reserved" textline " " bitfld.long 0x0 13. " URRST ,UART receiver reset. Resets and enables the receiver." "0,1" bitfld.long 0x0 14. " UTRST ,UART transmitter reset. Resets and enables the transmitter." "0,1" textline " " bitfld.long 0x0 15. " RESERVED ,Reserved. This bit must always be written with a 0." "0,1" hexmask.long.word 0x0 16.--31. 1. " RESERVED ,Reserved" group.byte 0x34++0x3 line.long 0x0 "PRUSS_UART_MODE_DEFINITION_REGISTER,The Mode definition register determines the over-sampling mode for the UART." bitfld.long 0x0 0. " OSM_SEL ,Over-Sampling Mode Select." "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ,Reserved" width 0x0B tree.end tree "ECAP" base eahb:0x4B2B0000 width 19. group.byte 0x0++0x3 line.long 0x0 "PRUSS_ECAP_TSCNT,Time Stamp Counter Register" hexmask.long 0x0 0.--31. 1. " TSCNT ,Active 32 bit-counter register that is used as the capture time-base" group.byte 0x4++0x3 line.long 0x0 "PRUSS_ECAP_CNTPHS,Counter Phase Control Register" hexmask.long 0x0 0.--31. 1. " CNTPHS ,Counter phase value register that can be programmed for phase lag/lead. This register shadows TSCNT and is loaded intoPRUSS_ECAP_TSCNT upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM time-bases." group.byte 0x8++0x3 line.long 0x0 "PRUSS_ECAP_CAP1,Capture-1 Register" hexmask.long 0x0 0.--31. 1. " CAP1 ,This register can be loaded (written) by the following. (a) Time-Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0xC++0x3 line.long 0x0 "PRUSS_ECAP_CAP2,Capture-2 Register" hexmask.long 0x0 0.--31. 1. " CAP2 ,This register can be loaded (written) by the following. (a) Time- Stamp (that is, counter value) during a capture event. (b) Software may be useful for test purposes. (c) APRD active register when used in APWM mode." group.byte 0x10++0x3 line.long 0x0 "PRUSS_ECAP_CAP3,Capture-3 Register" hexmask.long 0x0 0.--31. 1. " CAP3 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. User software updates the PWM period value through this register. In this mode, CAP3 shadows CAP1." group.byte 0x14++0x3 line.long 0x0 "PRUSS_ECAP_CAP4,Capture-4 Register" hexmask.long 0x0 0.--31. 1. " CAP4 ,In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare shadow (ACMP) register. User software updates the PWM compare value through this register. In this mode, CAP4 shadows CAP2." group.byte 0x28++0x1 line.word 0x0 "PRUSS_ECAP_ECCTL1,ECAP Control Register1" bitfld.word 0x0 0. " CAP1POL ,Capture Event 1 Polarity select 0x0 = Capture Event 1 triggered on a rising edge (RE) 0x1 = Capture Event 1 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 1. " CTRRST1 ,Counter Reset on Capture Event 1 0x0 = Do not reset counter on Capture Event 1 (absolute time stamp) 0x1 = Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 2. " CAP2POL ,Capture Event 2 Polarity select 0x0 = Capture Event 2 triggered on a rising edge (RE) 0x1 = Capture Event 2 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 3. " CTRRST2 ,Counter Reset on Capture Event 2 0x0 = Do not reset counter on Capture Event 2 (absolute time stamp) 0x1 = Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 4. " CAP3POL ,Capture Event 3 Polarity select 0x0 = Capture Event 3 triggered on a rising edge (RE) 0x1 = Capture Event 3 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 5. " CTRRST3 ,Counter Reset on Capture Event 3 0x0 = Do not reset counter on Capture Event 3 (absolute time stamp) 0x1 = Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 6. " CAP4POL ,Capture Event 4 Polarity select 0x0 = Capture Event 4 triggered on a rising edge (RE) 0x1 = Capture Event 4 triggered on a falling edge (FE)" "0,1" bitfld.word 0x0 7. " CTRRST4 ,Counter Reset on Capture Event 4 0x0 = Do not reset counter on Capture Event 4 (absolute time stamp operation) 0x1 = Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode operation)" "0,1" textline " " bitfld.word 0x0 8. " CAPLDEN ,Enable Loading ofPRUSS_ECAP_CAP1 to PRUSS_ECAP_CAP4 registers on a capture event 0x0 = Disable PRUSS_ECAP_CAP1-PRUSS_ECAP_CAP4 register loads at capture event time. 0x1 = Enable PRUSS_ECAP_CAP1-PRUSS_ECAP_CAP4 register loads at capture event time." "0,1" bitfld.word 0x0 9.--13. " EVTFLTPS ,Event Filter prescale select: 0x0 = Divide by 1 (i.e,. no prescale, by-pass the prescaler) 0x1 = Divide by 2 0x2 = Divide by 4 0x3 = Divide by 6 0x4 = Divide by 8 0x5 = Divide by 10 0x1E = Divide by 60 0x1F = Divide by 62" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.word 0x0 14.--15. " FREE_SOFT ,Emulation Control 0x0 = TSCNT counter stops immediately on emulation suspend. 0x1 = TSCNT counter runs until = 0. 0x2 = TSCNT counter is unaffected by emulation suspend (Run Free). 0x3 = TSCNT counter is unaffected by emulation suspend (Run Free)." "0,1,2,3" group.byte 0x2A++0x1 line.word 0x0 "PRUSS_ECAP_ECCTL2,ECAP Control Register 2" bitfld.word 0x0 0. " CONTONESHT ,Continuous or one-shot mode control (applicable only in capture mode) 0x0 = Operate in continuous mode 0x1 = Operate in one-shot mode" "0,1" bitfld.word 0x0 1.--2. " STOPVALUE ,Stop value for one-shot mode. This is the number (between 1 and 4) of captures allowed to occur before the CAP (1 through 4) registers are frozen, that is, capture sequence is stopped. Wrap value for continuous mode. This is the number (between 1 and 4) of the capture register in which the circular buffer wraps around and starts again. Notes: STOPVALUE is compared to Mod4 counter and, when equal, the following two actions occur. (1) Mod4 counter is stopped (frozen). (2) Capture register loads are inhibited. In one-shot mode, further interrupt events are blocked until re-armed. 0x0 = Stop after Capture Event 1 in one-shot mode. Wrap after Capture Event 1 in continuous mode. 0x1 = Stop after Capture Event 2 in one-shot mode. Wrap after Capture Event 2 in continuous mode. 0x2 = Stop after Capture Event 3 in one-shot mode. Wrap after Capture Event 3 in continuous mode. 0x3 = Stop after Capture Event 4 in one-shot mode. Wrap after Capture Event 4 in continuous mode." "0,1,2,3" textline " " bitfld.word 0x0 3. " REARMRESET ,One-Shot Re-Arming Control, that is, wait for stop trigger. Note: The re-arm function is valid in one shot or continuous mode. 0x0 = Has no effect (reading always returns a 0) 0x1 = Arms the one-shot sequence as follows: 1) Resets the Mod4 counter to zero. 2) Unfreezes the Mod4 counter. 3) Enables capture register loads." "0,1" bitfld.word 0x0 4. " TSCNTSTP ,Time Stamp (TSCNT) Counter Stop (freeze) Control 0x0 = TSCNT stopped 0x1 = TSCNT free-running" "0,1" textline " " bitfld.word 0x0 5. " SYNCI_EN ,Counter (TSCNT) Sync-In select mode 0x0 = Disable sync-in option 0x1 = Enable counter (TSCNT) to be loaded from" "0,1" bitfld.word 0x0 6.--7. " SYNCO_SEL ,Sync-Out Select 0x0 = Select sync-in event to be the sync-out signal (pass through) 0x1 = Select CTR = PRD event to be the sync-out signal 0x2 = Disable sync out signal 0x3 = Disable sync out signal" "0,1,2,3" textline " " bitfld.word 0x0 8. " SWSYNC ,Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing can also be done via the CTR = PRD event. Note: Selection CTR = PRD is meaningful only in APWM mode. However, a choice of CAP mode is also available if it may be of use. 0x0 = Writing a zero has no effect. Reading always returns a zero 0x1 = Writing a one forces a TSCNT shadow load of current ECAP module and any ECAP modules down-stream providing the SYNCO_SEL bits are 1'b00. After writing a 1, this bit returns to a zero." "0,1" bitfld.word 0x0 9. " CAPAPWM ,CAP/APWM operating mode select 0x0 = ECAP module operates in capture mode. This mode forces the following configuration. 0x1 = ECAP module operates in APWM mode. This mode forces the following configuration." "0,1" textline " " bitfld.word 0x0 10. " APWMPOL ,APWM output polarity select. This is applicable only in APWM operating mode 0x0 = Output is active high (Compare value defines high time) 0x1 = Output is active low (Compare value defines low time)" "0,1" bitfld.word 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.byte 0x2C++0x1 line.word 0x0 "PRUSS_ECAP_ECEINT,ECAP Interrupt Enable Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Interrupt Enable. 0x0 = Disable Capture Event 1 as an Interrupt source. 0x1 = Enable Capture Event 1 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Interrupt Enable. 0x0 = Disable Capture Event 2 as an Interrupt source. 0x1 = Enable Capture Event 2 as an Interrupt source." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Interrupt Enable. 0x0 = Disable Capture Event 3 as an Interrupt source. 0x1 = Enable Capture Event 3 as an Interrupt source." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Interrupt Enable. 0x0 = Disable Capture Event 4 as an Interrupt source. 0x1 = Enable Capture Event 4 as an Interrupt source." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Interrupt Enable. 0x0 = Disable counter Overflow as an Interrupt source. 0x1 = Enable counter Overflow as an Interrupt source." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal 0x0 = Disable Period Equal as an Interrupt source. 0x1 = Enable Period Equal as an Interrupt source." "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal 0x0 = Disable Compare Equal as an Interrupt source. 0x1 = Enable Compare Equal as an Interrupt source." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x2E++0x1 line.word 0x0 "PRUSS_ECAP_ECFLG,ECAP Interrupt Flag Register" bitfld.word 0x0 0. " INT ,Global Interrupt Status Flag 0x0 = Indicates no interrupt generated. 0x1 = Indicates that an interrupt was generated." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the first event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag. This flag is only active in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the second event occurred at ECAPn pin." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag. This flag is active only in CAP mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the third event occurred at ECAPn pin." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag This flag is only active in CAP mode. 0x0 = Indicates no event occurred 0x1 = Indicates the fourth event occurred at ECAPn pin" "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag. This flag is active in CAP and APWM mode. 0x0 = Indicates no event occurred. 0x1 = Indicates the counter (TSCNT) has made the transition from 0xFFFFFFFF to 0x00000000" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the period register value (APRD) and was reset." "0,1" bitfld.word 0x0 7. " CMPEQ ,Compare Equal Compare Status Flag. This flag is only active in APWM mode. 0x0 = Indicates no event occurred 0x1 = Indicates the counter (TSCNT) reached the compare register value (ACMP)" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x30++0x1 line.word 0x0 "PRUSS_ECAP_ECCLR,ECAP Interrupt Clear Register" bitfld.word 0x0 0. " INT ,Global Interrupt Clear Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1." "0,1" bitfld.word 0x0 1. " CEVT1 ,Capture Event 1 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT1 flag condition." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Capture Event 2 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT2 flag condition." "0,1" bitfld.word 0x0 3. " CEVT3 ,Capture Event 3 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Capture Event 4 Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0. 0x1 = Writing a 1 clears the CEVT3 flag condition." "0,1" bitfld.word 0x0 5. " CNTOVF ,Counter Overflow Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CNTOVF flag condition" "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Counter Equal Period Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CTR=PRD flag condition" "0,1" bitfld.word 0x0 7. " CMPEQ ,Counter Equal Compare Status Flag 0x0 = Writing a 0 has no effect. Always reads back a 0 0x1 = Writing a 1 clears the CTR=CMP flag condition" "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x34++0x1 line.word 0x0 "PRUSS_ECAP_ECFRC,ECAP Interrupt Forcing Register" bitfld.word 0x0 0. " RESERVED ," "0,1" bitfld.word 0x0 1. " CEVT1 ,Always reads back a 0. Force Capture Event 1 0x0 = No effect. 0x1 = Writing a 1 sets the CEVT1 flag bit." "0,1" textline " " bitfld.word 0x0 2. " CEVT2 ,Force Capture Event 2 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT2 flag bit." "0,1" bitfld.word 0x0 3. " CEVT3 ,Force Capture Event 3 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT3 flag bit" "0,1" textline " " bitfld.word 0x0 4. " CEVT4 ,Force Capture Event 4 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CEVT4 flag bit" "0,1" bitfld.word 0x0 5. " CNTOVF ,Force Counter Overflow 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 to this bit sets the CNTOVF flag bit." "0,1" textline " " bitfld.word 0x0 6. " PRDEQ ,Force Counter Equal Period Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CTR=PRD flag bit." "0,1" bitfld.word 0x0 7. " CMPEQ ,Force Counter Equal Compare Interrupt 0x0 = No effect. Always reads back a 0. 0x1 = Writing a 1 sets the CTR=CMP flag bit." "0,1" textline " " hexmask.word.byte 0x0 8.--15. 1. " RESERVED ," group.byte 0x5C++0x3 line.long 0x0 "PRUSS_ECAP_PID,ECAP Revision ID" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision" width 0x0B tree.end tree "MII_RT" base eahb:0x4B2B2000 width 23. group.byte 0x0++0x3 line.long 0x0 "PRUSS_MII_RT_RXCFG0,MII RXCFG 0 REGISTER This register contains the PRU0 RXCFG configuration variables () for the RX path. is attached to PRU0. controls which RX port is attached to PRU0." bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0 Disable 0x1 Enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is DA" "0,1" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1)" "0,1" textline " " bitfld.long 0x0 4. " RX_L2_EN ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: that if TX_AUTO_SEQUENCE enabled, this bit cannot get enable since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received. Must be selected /updated when the port is disabled or no traffic It only effects R31 and RX L2 order" "0,1" textline " " bitfld.long 0x0 6. " RX_AUTO_FWD_PRE ,Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1:Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE." "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRUSS_MII_RT_RXCFG1,This register contains the PRU1 RXCFG configuration variables () for the RX path. is attached to PRU1. controls which RX port is attached to PRU1" bitfld.long 0x0 0. " RX_ENABLE ,Enables the receive traffic currently selected by RX_MUX_SELECT. 0x0: Disable 0x1: Enable" "0,1" bitfld.long 0x0 1. " RESERVED ," "0,1" textline " " bitfld.long 0x0 2. " RX_CUT_PREAMBLE ,Removes received preamble. 0x0: All data from Ethernet PHY are passed on to PRU register. This assumes Ethernet PHY which does not shorten the preamble. 0x1: MII interface suppresses preamble and sync frame delimiter. First data byte seen by PRU register is destination address." "0,1" bitfld.long 0x0 3. " RX_MUX_SEL ,Selects receive data source. Typically, the setting for this will not be identical for the two MII receive configuration registers. 0x0: MII RX Data from Port 0 (default for PRUSS_MII_RT_RXCFG0) 0x1: MII RX Data from Port 1 (default for PRUSS_MII_RT_RXCFG1)" "0,1" textline " " bitfld.long 0x0 4. " RX_L2_EN ,Enables RX L2 buffer. 0x0: Disable (RX L2 can function as generic scratch pad) 0x1: Enable" "0,1" bitfld.long 0x0 5. " RX_BYTE_SWAP ,Defines the order of Byte0/1 placement for RX R31 and RX L2. Note: If TX_AUTO_SEQUENCE is enabled, this bit cannot get enabled since TX_BYTE_SWAP on swaps the PRU output. This bit must be selected/updated when the port is disabled or there is no traffic. 0x0: R31 [15:8]/RXL2 [15:8] = Byte1{Nibble3,Nibble2} R31[ 7:0]/RXL2 [7:0] = Byte0{Nibble1,Nibble0} 0x1: R31 [15:8]/RXL2 [15:8] = Byte0{Nibble1,Nibble0} R31[ 7:0]/RXL2 [7:0] = Byte1{Nibble3,Nibble2} Nibble0 is the first nibble received." "0,1" textline " " bitfld.long 0x0 6. " RX_AUTO_FWD_PRE ,Enables auto-forward of received preamble. When enabled, this will forward the preamble nibbles including the SFD to the TX L1 FIFO that is attached to the PRU. First data byte seen by PRU R31 and/or RX L2 is destination address (DA). Note: Odd number of preamble nibbles is supported in this mode. For example, 0x55D Note that new RX should only occur after the current TX completes 0x0: Disable 0x1: Enable, it must disable RX_CUT_PREAMBLE and TX_AUTO_PREAMBLE" "0,1" bitfld.long 0x0 7. " RESERVED ," "0,1" textline " " bitfld.long 0x0 8. " RESERVED ," "0,1" bitfld.long 0x0 9. " RESERVED ," "0,1" textline " " hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x10++0x3 line.long 0x0 "PRUSS_MII_RT_TXCFG0,This register contains the configuration variables for the transmit path on the MII interface port 0. is attached to Port TX0. controls which PRU is selected for TX0" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency." "0,1" textline " " bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event.Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself." "0,1" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0)" "0,1" textline " " bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter. Also, the masking logic is disabled and only the MII data is used." "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration." bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the PRUSS_GICLK clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x14++0x3 line.long 0x0 "PRUSS_MII_RT_TXCFG1,MII TXCFG 1 REGISTER This register contains the configuration variables for the transmit path on the MII interface port 1. is attached to Port TX1. controls which PRU is selected for TX1" bitfld.long 0x0 0. " TX_ENABLE ,Enables transmit traffic on TX PORT. If TX_EN_MODE is set, then TX_ENABLE will self clear during a TX_EOF event. Note Software can use this to pre-fill the TX FIFO and then start the TX frame during non-ECS operations. 0x0: TX PORT is disabled/stopped immediately 0x1: TX PORT is enabled and the frame will start once the IPG counter expired and TX Start Delay counter has expired" "0,1" bitfld.long 0x0 1. " TX_AUTO_PREAMBLE ,Transmit data auto-preamble. 0x0: PRU will provide full preamble 0x1: TX FIFO will insert pre-amble automatically Note: the TX FIFO does not get preloaded with the preamble until the first write occurs. This can cause the latency to be larger the min latency." "0,1" textline " " bitfld.long 0x0 2. " TX_EN_MODE ,Enables transmit self clear on TX_EOF event.Note that iep.cmp[3] must be set before transmission will start for TX0, and iep_cmp[4] for TX1. This is a new dependency, in addition to TX L1 FIFO not empty and TX_START_DELAY expiration, to start transmission. 0x0: Disable 0x1: Enable, TX_ENABLE will be clear for a TX_EOF event by itself." "0,1" bitfld.long 0x0 3. " TX_BYTE_SWAP ,Defines the order of Byte0/1 placement for TX R30. This bit must be selected/updated when the port is disabled or there is no traffic." "0,1" textline " " bitfld.long 0x0 4.--7. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8. " TX_MUX_SEL ,Selects transmit data source. The default/reset setting for TX Port 0 is 1. This setting permits MII TX Port 0 to receive data from PRU1 and the MII TX Port 1 which is connected to PRU0 by default. 0x0: Data from PRU0 (default for PRUSS_MII_RT_TXCFG1) 0x1: Data from PRU1 (default for PRUSS_MII_RT_TXCFG0)" "0,1" textline " " bitfld.long 0x0 9. " TX_AUTO_SEQUENCE ,Enables transmit auto-sequence. Note the transmit data source is determined by TX_MUX_SEL setting. 0x0: Disable 0x1: Enable, transmit state machine based on events on receiver path that is connected to the respective transmitter.TX data from PRU1 is selected Also, the masking logic is disabled and only the MII data is used." "0,1" bitfld.long 0x0 10. " RESERVED ," "0,1" textline " " bitfld.long 0x0 11. " RESERVED ," "0,1" bitfld.long 0x0 12.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 16.--25. 1. " TX_START_DELAY ,Defines the minimum time interval (delay) between receiving the RXDV for the current frame and the start of the transmit interface sending data to the MII interface. Delay value is in units of MII_RT clock cycles, which uses the PRUSS_GICLK (default is 200MHz, or 5ns). Default TX_START_DELAY value is 320ns, which is optimized for minimum latency at 16 bit processing. Counter is started with RX_DV signal going active. Transmit interface stops sending data when no more data is written into transmit interface by PRU along with TX_EOF marker bit set. If the TX FIFO has data when the delay expires, then TX will start sending data. But if the TX FIFO is empty, it will not start until the TX FIFO is not empty. It is possible to overflow the TX FIFO with the max delay setting when auto-forwarding is enabled since the time delay is larger than the amount of data it needs to store. As long as TX L1 FIFO overflows, software will need to issue a TX_RESET to reset the TX FIFO. The total delay is 64-byte times (size of TX FIFO), but delays for synchronization need to be allowed. Do to this fact, the maximum delay should be 80ns less when auto forwarding is enabled. Therefore, 0x3F0 is the maximum in this configuration." bitfld.long 0x0 26.--27. " RESERVED ," "0,1,2,3" textline " " bitfld.long 0x0 28.--30. " TX_CLK_DELAY ,In order to guarantee the MII_RT IO timing values published in the device data manual, the PRUSS_GICLK clock must be configured for 200MHz and TX_CLK_DELAY must be set to 6h." "0,1,2,3,4,5,6,7" bitfld.long 0x0 31. " RESERVED ," "0,1" group.byte 0x20++0x3 line.long 0x0 "PRUSS_MII_RT_TX_CRC0,MII TXCRC 0 REGISTER It contains CRC32 which PRU0 reads" hexmask.long 0x0 0.--31. 1. " TX_CRC ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.byte 0x24++0x3 line.long 0x0 "PRUSS_MII_RT_TX_CRC1,MII TXCRC 1 REGISTER It contains CRC32 which PRU1 reads" hexmask.long 0x0 0.--31. 1. " TX_CRC ,FCS (CRC32) data can be read by PRU for diagnostics. It is only valid after 6 clocks after a TX_CRC_HIGH command is given." group.byte 0x30++0x3 line.long 0x0 "PRUSS_MII_RT_TX_IPG0,MII TXIPG 0 REGISTER" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x34++0x3 line.long 0x0 "PRUSS_MII_RT_TX_IPG1,MII TXIPG 1 REGISTER" hexmask.long.word 0x0 0.--9. 1. " TX_IPG ,Defines the minimum of transmit Inter Packet Gap (IPG) which is the number of PRUSS_GICLK cycles between the de-assertion of TX_EN and the assertion of TX_EN. The start of the TX will get delayed when the incoming packet IPG is less than defined minimum value. In general, software should program in increments of 8, 40ns to insure the extra delays takes effect." hexmask.long.tbyte 0x0 10.--31. 1. " RESERVED ," group.byte 0x38++0x3 line.long 0x0 "PRUSS_MII_RT_PRS0,MII PORT STATUS 0 REGISTER" bitfld.long 0x0 0. " MII_COL ,Read the current state of pr1_mii0_col" "0,1" bitfld.long 0x0 1. " MII_CRS ,Read the current state of pr1_mii0_crs" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x3C++0x3 line.long 0x0 "PRUSS_MII_RT_PRS1,MII PORT STATUS 1 REGISTER" bitfld.long 0x0 0. " MII_COL ,Read the current state of pr1_mii1_col" "0,1" bitfld.long 0x0 1. " MII_CRS ,Read the current state of pr1_mii1_crs" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x40++0x3 line.long 0x0 "PRUSS_MII_RT_RX_FRMS0,MII RXFRMS 0 REGISTER" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM ,Defines the maximum received frame count. If the total byte count of received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted." group.byte 0x44++0x3 line.long 0x0 "PRUSS_MII_RT_RX_FRMS1,MII RXFRMS 1 REGISTER" hexmask.long.word 0x0 0.--15. 1. " RX_MIN_FRM ,Defines the minimum received frame count. If the total byte count of received frame is less than defined value, RX_MIN_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N=N+1 bytes after SFD and including CRC" hexmask.long.word 0x0 16.--31. 1. " RX_MAX_FRM ,Defines the maximum received frame count. If the total byte count of the received frame is more than defined value, RX_MAX_FRM_ERR will get set. 0x0 = 1 byte after SFD and including CRC N= N+1 bytes after SFD and including CRC Note if the incoming frame is truncated at the marker, RX_CRC and RX_NIBBLE_ODD will not get asserted." group.byte 0x48++0x3 line.long 0x0 "PRUSS_MII_RT_RX_PCNT0,MII RXPCNT 0 REGISTER" bitfld.long 0x0 0.--3. " RX_MIN_PCNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1 1 0x5 before 0xD5 0x2 2 0x5 before 0xD5 N min of N 0x5 before 0xD5 Note it does not need to be 0x5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_MAX_PCNT ,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted. Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x4C++0x3 line.long 0x0 "PRUSS_MII_RT_RX_PCNT1,MII RXPCNT 1 REGISTER" bitfld.long 0x0 0.--3. " RX_MIN_PCNT ,Defines the minimum number of nibbles until the start of frame delimiter (SFD) event occurred, which is matched the value 0xD5. RX_MIN_PRE_COUNT_ERR will be set if the preamble counts less than the value of RX_MIN_PCNT. 0x0 Disabled 0x1: 1 0x5 before 0xD5 0x2: 2 0x5 before 0xD5 N: N 0x5 before 0xD5 Note it does not need to be 0x5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 4.--7. " RX_MAX_PCNT ,Defines the maximum number of nibbles until the start of frame delimiter (SFD) event occurred (i.e. matches 0xD5). RX_MAX_PRE_COUNT_ERR will be set if the preamble counts more than the value of RX_MAX_PCNT. If the SFD does not occur within 16 nibbles, the error will assert and the incoming frame will be truncated. 0x0: Disabled 0x1: Reserved 0x2: 4th nibble needs to have built 0xD5 0xe: 16th nibble needs to have built 0xD5 Note the 16th nibble is transmitted Note for firmware enabling preamble error detection, it is recommended to keep RX_MAX_PCNT disabled (0x0). Otherwise, hardware can truncate a valid frame with too long of a preamble." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x50++0x3 line.long 0x0 "PRUSS_MII_RT_RX_ERR0,MII RXERR 0 REGISTER" bitfld.long 0x0 0. " RX_MIN_PCNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 1. " RX_MAX_PCNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " bitfld.long 0x0 2. " RX_MIN_FRM_ERR ,Error status of received frame is less than the value of RX_MIN_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 3. " RX_MAX_FRM_ERR ,Error status of received frame is more than the value of RX_MAX_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," group.byte 0x54++0x3 line.long 0x0 "PRUSS_MII_RT_RX_ERR1,MII RXERR 1 REGISTER" bitfld.long 0x0 0. " RX_MIN_PCNT_ERR ,Error status of received preamble nibble is less than the value of RX_MIN_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 1. " RX_MAX_PCNT_ERR ,Error status of received preamble nibble is more than the value of RX_MAX_PCNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " bitfld.long 0x0 2. " RX_MIN_FRM_ERR ,Error status of received frame is less than the value of RX_MIN_FRM. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" bitfld.long 0x0 3. " RX_MAX_FRM_ERR ,Error status of received frame is more than the value of RX_MAX_FRM_CNT. 0x0: No error occurred 0x1: Error occurred Write 1 to Clear" "0,1" textline " " hexmask.long 0x0 4.--31. 1. " RESERVED ," width 0x0B tree.end tree "MII_MDIO" base eahb:0x4B2B2400 width 31. group.byte 0x0++0x3 line.long 0x0 "PRUSS_MII_MDIO_VER,MDIO MODULE VERSION REGISTER" hexmask.long 0x0 0.--31. 1. " REVISION ,IP Revision." group.byte 0x4++0x3 line.long 0x0 "PRUSS_MII_MDIO_CONTROL,MDIO MODULE CONTROL REGISTER" hexmask.long.word 0x0 0.--15. 1. " CLKDIV ,Clock Divider. This field specifies the division ratio between CLK and the frequency of MDCLK. MDCLK is disabled when clkdiv is set to 0. MDCLK frequency = clk frequency/(clkdiv+1)." bitfld.long 0x0 16. " RESERVED ," "0,1" textline " " bitfld.long 0x0 17. " INT_TEST_ENABLE ,Interrupt test enable. This bit can be set to 1 to enable the host to set the userint and linkint bits for test purposes." "0,1" bitfld.long 0x0 18. " FAULT_DETECT_ENABLE ,Fault detect enable. This bit has to be set to 1 to enable the physical layer fault detection." "0,1" textline " " bitfld.long 0x0 19. " FAULT ,Fault indicator. This bit is set to 1 if the MDIO pins fail to read back what the device is driving onto them. This indicates a physical layer fault and the module state machine is reset. Writing a 1 to it clears this bit." "0,1" bitfld.long 0x0 20. " PREAMBLE ,Preamble disable. Writing a 1 to this bit disables this device from sending MDIO frame preambles." "0,1" textline " " bitfld.long 0x0 21.--23. " RESERVED ," "0,1,2,3,4,5,6,7" bitfld.long 0x0 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel. This field specifies the highest useraccess channel that is available in the module and is currently set to 1. This implies thatMDIOUserAccess1 is the highest available user access channel." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 29. " RESERVED ," "0,1" bitfld.long 0x0 30. " ENABLE ,Enable control. Writing a 1 to this bit enables the MDIO state machine, writing a 0 disables it. If the MDIO state machine is active at the time it is disabled, it will complete the current operation before halting and setting the idle bit. If using byte access, the enable bit has to be the last bit written in this register." "0,1" textline " " bitfld.long 0x0 31. " IDLE ,MDIO state machine IDLE. Set to 1 when the state machine is in the idle state." "0,1" group.byte 0x8++0x3 line.long 0x0 "PRUSS_MII_MDIO_ALIVE,PHY ACKNOWLEDGE STATUS REGISTER" hexmask.long 0x0 0.--31. 1. " ALIVE ,MDIO Alive bitfield. Each of the 32 bits of this register is set if the most recent access to the PHY with address corresponding to the register bit number was acknowledged by the PHY, the bit is reset if the PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause the corresponding alive bit to be updated. The alive bits are only meant to be used to give an indication of the presence or not of a PHY with the corresponding address. Writing a 1 to any bit will clear it, writing a 0 has no effect." group.byte 0xC++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINK,PHY LINK STATUS REGISTER" hexmask.long 0x0 0.--31. 1. " LINK ,MDIO Link state. This register is updated after a read of the Generic Status Register of a PHY. The bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge the read transaction. Writes to the register have no effect. In addition, the status of the two PHYs specified in theMDIOUserPhySel registers can be determined using the MLINK input pins. This is determined by the linksel bit in the MDIOUserPhySel register." group.byte 0x10++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINKINTRAW,LINK STATUS CHANGE INTERRUPT REGISTER (RAW VALUE)" bitfld.long 0x0 0.--1. " LINKINTRAW ,MDIO link change event, raw value. When asserted 1, a bit indicates that there was anMDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register. linkintraw[0] and linkintraw[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the event and writing 0 has no effect.If the int_test bit in the MDIOControl register is set, the host may set the linkintraw bits to a 1.This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_MII_MDIO_LINKINTMASKED,LINK STATUS CHANGE INTERRUPT REGISTER (MASKED VALUE)" bitfld.long 0x0 0.--1. " LINKINTMASKED ,MDIO link change interrupt, masked value. When asserted 1, a bit indicates that there was an MDIO link change event (i.e. change in the MDIOLink register) corresponding to the PHY address in the MDIOUserPhySel register and the corresponding linkint_enable bit was set.. linkintmasked[0] and linkintmasked[1] correspond to MDIOUserPhySel0 and MDIOUserPhysel1, respectively. Writing a 1 will clear the interrupt and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the linkint bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x20++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTRAW,USER COMMAND COMPLETE INTERRUPT REGISTER (RAW VALUE)" bitfld.long 0x0 0.--1. " USERINTRAW ,Raw value of MDIO user command complete event for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed. Writing a 1 will clear the event and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the userintraw bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x24++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKED,USER COMMAND COMPLETE INTERRUPT REGISTER (MASKED VALUE)" bitfld.long 0x0 0.--1. " USERINTMASKED ,Masked value of MDIO user command complete interrupt for MDIOUserAccess1 through MDIOUserAccess0, respectively. When asserted 1, a bit indicates that the previously scheduled PHY read or write command using that particular MDIOUserAccess register has completed and the corresponding userintmaskset bit is set to 1.Writing a 1 will clear the interrupt and writing 0 has no effect. If the int_test bit in the MDIOControl register is set, the host may set the userintmasked bits to a 1. This mode may be used for test purposes." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x28++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKSET,USER INTERRUPT MASK SET REGISTER" bitfld.long 0x0 0.--1. " USERINTMASKEDSET ,MDIO user interrupt mask set for userintmasked[1:0], respectively. Writing a bit to 1 will enable MDIO user command complete interrupts for that particular MDIOUserAccess register. MDIO user interrupt for a particular MDIOUserAccess register is disabled if the corresponding bit is 0. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x2C++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERINTMASKCLR,USER INTERRUPT MASK CLEAR REGISTER" bitfld.long 0x0 0.--1. " USERINTMASKEDCLR ,MDIO user command complete interrupt mask clear for userintmasked[1:0], respectively. Writing a bit to 1 will disable further user command complete interrupts for that particular MDIOUserAccess register. Writing a 0 to this register has no effect." "0,1,2,3" hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x80++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERACCESS0,USER ACCESS REGISTER0" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. This field specifies the PHY to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. This field specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last." "0,1" group.byte 0x84++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERPHYSEL0,USER PHY SELECT REGISTER0" bitfld.long 0x0 0.--4. " PHYADR_MON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINT_ENABLE ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x88++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERACCESS1,USER ACCESS REGISTER1" hexmask.long.word 0x0 0.--15. 1. " DATA ,User data. The data value read from or to be written to the specified PHY register." bitfld.long 0x0 16.--20. " PHYADR ,PHY address. This field specifies the PHY to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 21.--25. " REGADR ,Register address. This field specifies the PHY register to be accessed for this transaction." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 26.--28. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 29. " ACK ,Acknowledge. This bit is set if the PHY acknowledged the read transaction." "0,1" bitfld.long 0x0 30. " WRITE ,Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read." "0,1" textline " " bitfld.long 0x0 31. " GO ,Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last." "0,1" group.byte 0x8C++0x3 line.long 0x0 "PRUSS_MII_MDIO_USERPHYSEL1,USER PHY SELECT REGISTER1" bitfld.long 0x0 0.--4. " PHYADR_MON ,PHY address whose link status is to be monitored." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0 5. " RESERVED ," "0,1" textline " " bitfld.long 0x0 6. " LINKINT_ENABLE ,Link change interrupt enable. Set to 1 to enable link change status interrupts for PHY address specified in phyadr_mon. Link change interrupts are disabled if this bit is set to 0." "0,1" bitfld.long 0x0 7. " LINKSEL ,Link status determination select. Set to 1 to determine link status using the MLINK pin. Default value is 0 which implies that the link status is determined by the MDIO state machine." "0,1" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," width 0x0B tree.end tree "IEP" base eahb:0x4B2AE000 width 29. group.byte 0x0++0x3 line.long 0x0 "PRUSS_IEP_GLOBAL_CFG,GLOBAL CFG" bitfld.long 0x0 0. " CNT_ENABLE ,Counter enable 0: Disables the counter. The counter maintains the current count. 1: Enables the counter." "0,1" bitfld.long 0x0 1.--3. " RESERVED ," "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 4.--7. " DEFAULT_INC ,Defines the default increment value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x0 8.--19. 1. " CMP_INC ,Defines the increment value when compensation is active" textline " " hexmask.long.word 0x0 20.--31. 1. " RESERVED ," group.byte 0x4++0x3 line.long 0x0 "PRUSS_IEP_GLOBAL_STATUS,STATUS" bitfld.long 0x0 0. " CNT_OVF ,Counter overflow status. 0: No overflow 1: Overflow occurred" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x8++0x3 line.long 0x0 "PRUSS_IEP_COMPEN,COMPENSATION" hexmask.long.tbyte 0x0 0.--23. 1. " COMPEN_CNT ,Compensation counter. Read returns the current COMPEN_CNT value. 0: Compensation is disabled and counter will increment by DEFAULT_INC. n: Compensation is enabled until COMPEN_CNT decrements to 0. The COMPEN_CNT value decrements on every iep_clk cycle. When COMPEN_CNT is greater than 0, then count value increments by CMP_INC." hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0xC++0x3 line.long 0x0 "PRUSS_IEP_COUNT,COUNTER" hexmask.long 0x0 0.--31. 1. " COUNT ,32-bit count value.t Increments by (DEFAULT_INC or CMP_INC) on every positive edge of PRUSS_IEP_CLK (200MHz) or PRUSS_GICLK." group.byte 0x10++0x3 line.long 0x0 "PRUSS_IEP_CAP_CFG,CAPTURE CFG" bitfld.long 0x0 0.--5. " CAP_1ST_EVENT_EN ,Capture 1-st Event Enable for n 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CAP6R_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[6] rise 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" textline " " bitfld.long 0x0 7. " CAP6F_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[6] fall 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" bitfld.long 0x0 8. " CAP7R_1ST_EVENT_EN ,Capture 1-st Event Enable for cap[7] rise 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" textline " " bitfld.long 0x0 9. " CAP7F_1ST_EVENT_EN ,Capture 1st Event Enable for cap[7] fall 0: Continues mode. The capture status is not set when events occur. 1: First Event mode. The capture status is set when the first event occurs and must be cleared before new data will fill buffer. Time value is captured when first event occurs and held until time is read." "0,1" hexmask.long.byte 0x0 10.--17. 1. " CAP_ASYNC_EN ,Synchronization of the capture inputs to the PRUSS_IEP_CLK/PRUSS_GICLK enable. Note if input capture signal is asynchronous to PRUSS_IEP_CLK, enabling synchronization will cause the capture contents to be invalid. CAP_ASYNC_EN[n] maps to CAPR[n]. 0: Disable synchronization 1: Enable synchronization" textline " " hexmask.long.word 0x0 18.--31. 1. " RESERVED ," group.byte 0x14++0x3 line.long 0x0 "PRUSS_IEP_CAP_STATUS,CAPTURE STATUS CFG" bitfld.long 0x0 0.--5. " CAPR_VALID ,Valid Status capr_valid<n> maps PRUSS_IEP_CAPR<n>_REG, where n=0 to 5, 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 6. " CAPR6_VALID ,Valid Status forPRUSS_IEP_CAPR6 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" textline " " bitfld.long 0x0 7. " CAPF6_VALID ,Valid Status forPRUSS_IEP_CAPF6 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" bitfld.long 0x0 8. " CAPR7_VALID ,Valid Status forPRUSS_IEP_CAPR7 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" textline " " bitfld.long 0x0 9. " CAPF7_VALID ,Valid Status forPRUSS_IEP_CAPF7 0: No Hit, no capture event occurred 1: Hit, capture event occurred. Clear on read when its Capture Value is read CAP*_REG" "0,1" bitfld.long 0x0 10. " CAP_VALID ,Valid status for capture function. Reflects the ORed result from PRUSS_IEP_CAP_STATUS [9:0]. 0: No Hit for any capture event, i.e., there are all 0 in PRUSS_IEP_CAP_STATUS [9:0]. 1: Hit for 1 or more captures events is pending, i.e., there has at least one value equal to 1 in PRUSS_IEP_CAP_STATUS [9:0]." "0,1" textline " " bitfld.long 0x0 11.--15. " RESERVED ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0 16.--23. 1. " CAP_RAW ,Raw/Current status bit for each of the capture registers, where CAP_RAW[n] maps to CAPR[n]. 0: Current state is low for cap<n> 1: Current state is high for cap<n>" textline " " hexmask.long.byte 0x0 24.--31. 1. " RESERVED ," group.byte 0x18++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_0,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_1,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x20++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_2,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x24++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_3,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x28++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_4,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_IEP_CAPRi_5,CAPTURE RISE(i), for i = 0 to 5" hexmask.long 0x0 0.--31. 1. " CAPR ,Capture Value for capr i event" group.byte 0x30++0x3 line.long 0x0 "PRUSS_IEP_CAPR6,CAPTURE RISE6" hexmask.long 0x0 0.--31. 1. " CAPR6 ,Capture Value for capr6 (rise) event" group.byte 0x34++0x3 line.long 0x0 "PRUSS_IEP_CAPF6,CAPTURE FALL6" hexmask.long 0x0 0.--31. 1. " CAPF6 ,Capture Value for capf6 (fall) event" group.byte 0x38++0x3 line.long 0x0 "PRUSS_IEP_CAPR7,CAPTURE RISE7" hexmask.long 0x0 0.--31. 1. " CAPR7 ,Capture Value for capr7 (rise) event" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_IEP_CAPF7,CAPTURE FALL7" hexmask.long 0x0 0.--31. 1. " CAPF7 ,Capture Value for capf7 (fall) event" group.byte 0x40++0x3 line.long 0x0 "PRUSS_IEP_CMP_CFG,COMPARE CFG" bitfld.long 0x0 0. " CMP0_RST_CNT_EN ,Enable the reset of the counter 0: Disable 1: Enable the reset of the counter if a cmp0 event occurs" "0,1" hexmask.long.byte 0x0 1.--8. 1. " CMP_EN ,Enable bit for each of the compare registers cmp_en<n> =0: Disables CMP<n> Event cmp_en<n> =1: Enables CMP<n> Event cmp_en[0] maps to CMP0" textline " " hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x44++0x3 line.long 0x0 "PRUSS_IEP_CMP_STATUS,COMPARE STATUS" hexmask.long.byte 0x0 0.--7. 1. " CMP_HIT ,Status bit for each of the compare registers. 'Match' indicates the current counter is greater than or equal to the compare value. Note it is the firmware's responsibility to handle the IEP overflow. cmp_hit<n> = 0: No match has occured cmp_hit<n> = 1: A match occured. The associated hardware event signal will assert and remain high until the status is cleared." hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x48++0x3 line.long 0x0 "PRUSS_IEP_CMPj_0,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_IEP_CMPj_1,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x50++0x3 line.long 0x0 "PRUSS_IEP_CMPj_2,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x54++0x3 line.long 0x0 "PRUSS_IEP_CMPj_3,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x58++0x3 line.long 0x0 "PRUSS_IEP_CMPj_4,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_IEP_CMPj_5,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x60++0x3 line.long 0x0 "PRUSS_IEP_CMPj_6,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x64++0x3 line.long 0x0 "PRUSS_IEP_CMPj_7,COMPARE(j), where j=0 to 7" hexmask.long 0x0 0.--31. 1. " CMP ,Compare j value" group.byte 0x80++0x3 line.long 0x0 "PRUSS_IEP_RXIPG0,RXIPG0This register can be used to determine the last RX IPG and the smallest RX IPG. RXIPG0 is the status for the RX port which is attached to PRU0." hexmask.long.word 0x0 0.--15. 1. " RX_IPG ,Records the current number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. Value is updated after RX_DV transitions from low to high. It will saturate at 0xffff." hexmask.long.word 0x0 16.--31. 1. " RX_MIN_IPG ,Defines the current minimum number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that is RXDV is sampled low. It stores the current smallest RX_IPG Read: The value can be read at any time. It gets updated after RX_IPG update if RX_MIN_IPG > RX_IPG. Write:Any write will reset this bitfield to 0xffff" group.byte 0x84++0x3 line.long 0x0 "PRUSS_IEP_RXIPG1,RXIPG1This register can be used to determine the last RX IPG and the smallest RX IPG. RXIPG1 is the status for the RX port which is attached to PRU1" hexmask.long.word 0x0 0.--15. 1. " RX_IPG ,Records the current number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. Value is updated after RX_DV transitions from low to high. It will saturate at 0xffff." hexmask.long.word 0x0 16.--31. 1. " RX_MIN_IPG ,Defines the current minimum number of PRUSS_GICLK/PRUSS_IEP_CLK cycles that RXDV is sampled low. It stores the current smallest RX_IPG Read: The value can be read at any time. It gets updated after RX_IPG update if RX_MIN_IPG > RX_IPG. Write:Any write will reset this bitfield to 0xffff" group.byte 0x100++0x3 line.long 0x0 "PRUSS_IEP_SYNC_CTRL,SYNC CTRL" bitfld.long 0x0 0. " SYNC_EN ,SYNC generation enable 0: Disable the generation and clocking of SYNC0 and SYNC1 logic 1: Enables SYNC0 and SYNC1 generation" "0,1" bitfld.long 0x0 1. " SYNC0_EN ,SYNC0 generation enable 0: Disable SYNC0 generation 1: Enable SYNC0 generation" "0,1" textline " " bitfld.long 0x0 2. " SYNC1_EN ,SYNC1 generation enable 0: Disable SYNC1 generation 1: Enable SYNC1 generation" "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4. " SYNC0_ACK_EN ,SYNC0 acknowledgement mode enable 0h: Disable, SYNC0 will go low after pulse width is met. 1: Enables acknowledge mode, when enabled SYNC0 will 1h: Enable, SYNC0 will remain asserted until receiving software acknowledges by reading PRUSS_IEP_SYNC0_STAT which clears on read." "0,1" bitfld.long 0x0 5. " SYNC0_CYCLIC_EN ,SYNC0 single shot or cyclic/auto generation mode enable 0h: Disable, single shot mode 1h: Enable, cyclic generation mode" "0,1" textline " " bitfld.long 0x0 6. " SYNC1_ACK_EN ,SYNC1 acknowledgement mode enable 0h: Disable, SYNC1 will go low after pulse width is met. 1h: Enable, SYNC1 will remain asserted until receiving software acknowledges by reading PRUSS_IEP_SYNC1_ STAT which clears on read." "0,1" bitfld.long 0x0 7. " SYNC1_CYCLIC_EN ,SYNC1 single shot or cyclic/auto generation mode enable 0: Disable, single shot mode 1:Enable, cyclic generation mode" "0,1" textline " " bitfld.long 0x0 8. " SYNC1_IND_EN ,SYNC1 independent mode enable. Independent mode means the SYNC1 signal can be different from SYNC0. 0: Dependent mode 1: Independent mode" "0,1" hexmask.long.tbyte 0x0 9.--31. 1. " RESERVED ," group.byte 0x104++0x3 line.long 0x0 "PRUSS_IEP_SYNC_FIRST_STAT,SYNC CTRL" bitfld.long 0x0 0. " FIRST_SYNC0 ,SYNC0 First Event status 0: SYNC0 first event has not occurred 1: SYNC0 first event has occurred. This bits is cleared when sync0_en = 0" "0,1" bitfld.long 0x0 1. " FIRST_SYNC1 ,SYNC1 First Event status 0: SYNC1 first event has not occurred 1: SYNC1 first event has occurred. This bits is cleared when sync1_en = 0" "0,1" textline " " hexmask.long 0x0 2.--31. 1. " RESERVED ," group.byte 0x108++0x3 line.long 0x0 "PRUSS_IEP_SYNC0_STAT,SYNC CTRL" bitfld.long 0x0 0. " SYNC0_PEND ,SYNC0 pending state 0: SYNC0 is not pending 1 SYNC0 is pending or has occurred when SYNC0_ACK_EN = 0 (Disable). Write '1' to clear" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x10C++0x3 line.long 0x0 "PRUSS_IEP_SYNC1_STAT,SYNC CTRL" bitfld.long 0x0 0. " SYNC1_PEND ,SYNC1 pending state 0: SYNC1 is not pending 1 SYNC1 is pending or has occurred when SYNC1_ACK_EN = 0 (Disable). Write '1' to Clear" "0,1" hexmask.long 0x0 1.--31. 1. " RESERVED ," group.byte 0x110++0x3 line.long 0x0 "PRUSS_IEP_SYNC_PWIDTH,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC_HPW ,Defines the number of clock cycles SYNC0/1 will be high. Note if SYNC0/1 is disabled during pulse width time (that is, SYNC_CTRL[SYNC0_EN | SYNC1_EN | SYNC_EN] = 0), the ongoing pulse will be terminated. 0h: 1 clock cycle. 1h: 2 clock cycles. Nh: N+1 clock cycles." group.byte 0x114++0x3 line.long 0x0 "PRUSS_IEP_SYNC0_PERIOD,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC0_PERIOD ,Defines the period between the rising edges of SYNC0. 0x0: Reserved 0x1: 2 clk cycles period N: N+1 clk cycles period" group.byte 0x118++0x3 line.long 0x0 "PRUSS_IEP_SYNC1_DELAY,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC1_DELAY ,When SYNC1_IND_EN = 0, defines number of clock cycles from the start of SYNC0 to the start of SYNC1. Note this is the delay before the start of SYNC1. 0h: No delay 1h: 1 clock cycle delay. Nh: N clock cycles delay. When SYNC1_IND_EN = 1, defines the period between the rising edges of SYNC1. 0h: Reserved. 1h: 2 clock cycles period. Nh: N+1 clock cycles period." group.byte 0x11C++0x3 line.long 0x0 "PRUSS_IEP_SYNC_START,SYNC CTRL" hexmask.long 0x0 0.--31. 1. " SYNC_START ,Defines the start time after the activation event. 0h: 1 clock cycle delay. Nh: N+1 clock cycles delay." group.byte 0x200++0x3 line.long 0x0 "PRUSS_IEP_WD_PREDIV,WD" hexmask.long.word 0x0 0.--15. 1. " PRE_DIV ,Defines the number of iep_clk cycles per WD clock event. Note that the WD clock is a free-running clock. The value 0x4e20 (or 20000) generates a rate of 100 us if iep_clk is 200 MHz. seconds/(WD event) = (clock cycles per WD event)/(clock cycles per second) = 20000/(200 x [10]^6 ) = 100 us" hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x204++0x3 line.long 0x0 "PRUSS_IEP_PDI_WD_TIM,WD" hexmask.long.word 0x0 0.--15. 1. " PDI_WD_TIME ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRE_DIV is set to 100 us, then the value 0x03e8 (or 1000) provides a rate of 100ms. Read returns the current count. Counter is reset by software write to register or when Digital Data In capture occurs. WD is disabled if WD time is set to 0x0. Note when an expiration event occurs, the expiration counter (PDI_EXP_CNT) increments and status (PDI_WD_STAT) clears." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x208++0x3 line.long 0x0 "PRUSS_IEP_PD_WD_TIM,WD" hexmask.long.word 0x0 0.--15. 1. " PD_WD_TIME ,Defines the number of WD ticks (or increments) for PDI WD, that is, the number of WD increments. If PRE_DIV is set to 100 us, then 0x03e8 (or 1000) provides a rate of 100ms Read returns the current count. Counter is reset by software write to register or every write access to Sync Managers with WD trigger enable bit set. WD is disabled if WD time is set to 0x0. Expiration actions: Increment expiration counter, clear status. Digital Data out forced to zero if pr1_edio_oe_ext = 1 and PRUSS_IEP_DIGIO_EXT.SW_DATA_OUT_UPDATE = 0." hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x20C++0x3 line.long 0x0 "PRUSS_IEP_WD_STATUS,WD" bitfld.long 0x0 0. " PD_WD_STAT ,WD PD status (triggered by Sync Mangers status). 0h: Expired (PD_WD_EXP event generated) 1h: Active or disabled" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " PDI_WD_STAT ,WD PDI status. 0h: Expired (PDI_WD_EXP event generated) 1h: Active or disabled" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x210++0x3 line.long 0x0 "PRUSS_IEP_WD_EXP_CNT,WD" hexmask.long.byte 0x0 0.--7. 1. " PDI_EXP_CNT ,WD PDI expiration counter. Counter increments on every PDI time out and stops at FFh." hexmask.long.byte 0x0 8.--15. 1. " PD_EXP_CNT ,WD PD expiration counter. Counter increments on every PD time out and stops at FFh" textline " " hexmask.long.word 0x0 16.--31. 1. " RESERVED ," group.byte 0x214++0x3 line.long 0x0 "PRUSS_IEP_WD_CTRL,WD" bitfld.long 0x0 0. " PD_WD_EN ,Watchdog PD 0: Disable 1: Enable" "0,1" hexmask.long.word 0x0 1.--15. 1. " RESERVED ," textline " " bitfld.long 0x0 16. " PDI_WD_EN ,Watchdog PDI 0: Disable 1: Enable" "0,1" hexmask.long.word 0x0 17.--31. 1. " RESERVED ," group.byte 0x300++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_CTRL,DIGIO" bitfld.long 0x0 0. " OUTVALID_POL ,Indicates OUTVALID polarity" "0,1" bitfld.long 0x0 1. " OUTVALID_MODE ,Defines OUTVALID mode" "0,1" textline " " bitfld.long 0x0 2. " BIDI_MODE ,Indicates the digital input/output direction. DUE TO INTEGRATION, ACTUAL MODE IS UNIDIRECTIONAL IN THIS DEVICE." "0,1" bitfld.long 0x0 3. " WD_MODE ,Defines Watchdog behavior" "0,1" textline " " bitfld.long 0x0 4.--5. " IN_MODE ,Defines event that triggers data in to be sampled 0b00: PRU0/1_RX_SOF 0b01: Rising edge of external pr<k>_edio_latch_in signal 0b10: DC rising edge of SYNC0 event 0b11: DC rising edge of SYNC1 event" "0,1,2,3" bitfld.long 0x0 6.--7. " OUT_MODE ,Defines event that triggers data out to be updated." "0,1,2,3" textline " " hexmask.long.tbyte 0x0 8.--31. 1. " RESERVED ," group.byte 0x308++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_IN,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_IN ,Data input. Digital inputs can be configured to be sampled in four ways. 1: Digital inputs are sampled at the start of each frame. The SOF signal can be used externally to update the input data, because the SOF is signaled before input data is sampled. 2: The sample time can be controlled externally by using the pr1_edio_latch_in signal. 3: Digital inputs are sampled at SYNC0 events. 4: Digital inputs are sampled at SYNC1 events. These can be configured by PRUSS_IEP_DIGIO_CTRL[5:4] IN_MODE. Only [7:0] are exported to device pins in this device." group.byte 0x30C++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_IN_RAW,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_IN_RAW ,Raw Data Input. Direct sample of EDIO_DATA_IN[31:0]. Only [7:0] are exported to device pins in this device." group.byte 0x310++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_OUT,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_OUT ,Data output. Digital outputs can be configured to be updated in four ways. 1: Digital outputs are updated at the end of each frame (EOF mode). 2: Digital outputs are updated with SYNC0 events 3: Digital outputs are updated SYNC1events. 4: Digital outputs are updated at the end of a frame which triggered the Process Data Watchdog. Digital Outputs are only updated if the frame was correct (WD_TRIG mode). These can be configured by out_mode." group.byte 0x314++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_DATA_OUT_EN,DIGIO" hexmask.long 0x0 0.--31. 1. " DATA_OUT_EN ,Enables tri-state control for pr<k>_edio_data_out[7:0]." group.byte 0x318++0x3 line.long 0x0 "PRUSS_IEP_DIGIO_EXP,DIGIO" bitfld.long 0x0 0. " SW_DATA_OUT_UPDATE ,Defines the value of pr1_edio_data_out when OUTVALID_OVR_EN = 1. Read 1: Start bit event occurred Read 0: Start bit event has not occurred Write 1: pr1_edio_data_out by software data out. Write 0: No Effect" "0,1" bitfld.long 0x0 1. " OUTVALID_OVR_EN ,Enable software to control value of pr<k>_edio_data_out [7:0]. 0: Disable 1: Enable" "0,1" textline " " bitfld.long 0x0 2. " SW_OUTVALID ,pr1_edio_outvalid = SW_OUTVALID, only if OUTVALID_OVR_EN is set." "0,1" bitfld.long 0x0 3. " RESERVED ," "0,1" textline " " bitfld.long 0x0 4.--7. " OUTVALID_DLY ,Define the number of iep_clk (PRUSS_IEP_CLK) cycle delay on assertion of PR1_EDIO_OUTVALID. Min is 2 clock cycles. Max is 16 clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 8.--11. " SOF_DLY ,Define the number of iep_clk (PRUSS_IEP_CLK) cycle delay of SOF PR1_EDIO_DATA_IN[31:0] capture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 12. " SOF_SEL ,Defines with RX_SOF is used for PR1_EDIO_DATA_IN[31:0] capture" "0,1" bitfld.long 0x0 13. " EOF_SEL ,Defines with RX_EOF is used for PR1_EDIO_DATA_IN[31:0] capture" "0,1" textline " " hexmask.long.tbyte 0x0 14.--31. 1. " RESERVED ," width 0x0B tree.end tree "PRUSS1_DEBUG" base eahb:0x4B2A2400 width 20. group.byte 0x0++0x3 line.long 0x0 "PRUSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4++0x3 line.long 0x0 "PRUSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x8++0x3 line.long 0x0 "PRUSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0xC++0x3 line.long 0x0 "PRUSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x10++0x3 line.long 0x0 "PRUSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x14++0x3 line.long 0x0 "PRUSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x18++0x3 line.long 0x0 "PRUSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x20++0x3 line.long 0x0 "PRUSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x24++0x3 line.long 0x0 "PRUSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x28++0x3 line.long 0x0 "PRUSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x30++0x3 line.long 0x0 "PRUSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x34++0x3 line.long 0x0 "PRUSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x38++0x3 line.long 0x0 "PRUSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x40++0x3 line.long 0x0 "PRUSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x44++0x3 line.long 0x0 "PRUSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x48++0x3 line.long 0x0 "PRUSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x50++0x3 line.long 0x0 "PRUSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x54++0x3 line.long 0x0 "PRUSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x58++0x3 line.long 0x0 "PRUSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x60++0x3 line.long 0x0 "PRUSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x64++0x3 line.long 0x0 "PRUSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x68++0x3 line.long 0x0 "PRUSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x6C++0x3 line.long 0x0 "PRUSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x70++0x3 line.long 0x0 "PRUSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x74++0x3 line.long 0x0 "PRUSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x78++0x3 line.long 0x0 "PRUSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x7C++0x3 line.long 0x0 "PRUSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG31 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x80++0x3 line.long 0x0 "PRUSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x84++0x3 line.long 0x0 "PRUSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x88++0x3 line.long 0x0 "PRUSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x8C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x90++0x3 line.long 0x0 "PRUSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x94++0x3 line.long 0x0 "PRUSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x98++0x3 line.long 0x0 "PRUSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x9C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xAC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xBC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xCC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xDC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xE0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c24_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00000n00, n=c24_blk_index[3:0]." group.byte 0xE4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c25_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00002n00, n=c25_blk_index[3:0]." group.byte 0xE8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c26_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x0002En00, n=c26_blk_index[3:0]." group.byte 0xEC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c27_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00032n00, n=c27_blk_index[3:0]." group.byte 0xF0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c28_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x00nnnn00, nnnn=c28_pointer[15:0]." group.byte 0xF4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c29_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x49nnnn00, nnnn=c29_pointer[15:0]." group.byte 0xF8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c30_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x40nnnn00, nnnn=c30_pointer[15:0]." group.byte 0xFC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c31_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x80nnnn00, nnnn=c31_pointer[15:0]." width 0x0B tree.end tree "PRUSS2_DEBUG" base eahb:0x4B2A4400 width 20. group.byte 0x0++0x3 line.long 0x0 "PRUSS_DBG_GPREG0,DEBUG PRU GENERAL PURPOSE REGISTER 0. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG0 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4++0x3 line.long 0x0 "PRUSS_DBG_GPREG1,DEBUG PRU GENERAL PURPOSE REGISTER 1. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG1 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x8++0x3 line.long 0x0 "PRUSS_DBG_GPREG2,DEBUG PRU GENERAL PURPOSE REGISTER 2. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG2 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0xC++0x3 line.long 0x0 "PRUSS_DBG_GPREG3,DEBUG PRU GENERAL PURPOSE REGISTER 3. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG3 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x10++0x3 line.long 0x0 "PRUSS_DBG_GPREG4,DEBUG PRU GENERAL PURPOSE REGISTER 4. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG4 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x14++0x3 line.long 0x0 "PRUSS_DBG_GPREG5,DEBUG PRU GENERAL PURPOSE REGISTER 5. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG5 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x18++0x3 line.long 0x0 "PRUSS_DBG_GPREG6,DEBUG PRU GENERAL PURPOSE REGISTER 6. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG6 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x1C++0x3 line.long 0x0 "PRUSS_DBG_GPREG7,DEBUG PRU GENERAL PURPOSE REGISTER 7. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG7 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x20++0x3 line.long 0x0 "PRUSS_DBG_GPREG8,DEBUG PRU GENERAL PURPOSE REGISTER 8. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG8 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x24++0x3 line.long 0x0 "PRUSS_DBG_GPREG9,DEBUG PRU GENERAL PURPOSE REGISTER 9. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG9 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x28++0x3 line.long 0x0 "PRUSS_DBG_GPREG10,DEBUG PRU GENERAL PURPOSE REGISTER 10. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG10 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x2C++0x3 line.long 0x0 "PRUSS_DBG_GPREG11,DEBUG PRU GENERAL PURPOSE REGISTER 11. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG11 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x30++0x3 line.long 0x0 "PRUSS_DBG_GPREG12,DEBUG PRU GENERAL PURPOSE REGISTER 12. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG12 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x34++0x3 line.long 0x0 "PRUSS_DBG_GPREG13,DEBUG PRU GENERAL PURPOSE REGISTER 13. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG13 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x38++0x3 line.long 0x0 "PRUSS_DBG_GPREG14,DEBUG PRU GENERAL PURPOSE REGISTER 14. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG14 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x3C++0x3 line.long 0x0 "PRUSS_DBG_GPREG15,DEBUG PRU GENERAL PURPOSE REGISTER 15. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG15 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x40++0x3 line.long 0x0 "PRUSS_DBG_GPREG16,DEBUG PRU GENERAL PURPOSE REGISTER 16. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG16 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x44++0x3 line.long 0x0 "PRUSS_DBG_GPREG17,DEBUG PRU GENERAL PURPOSE REGISTER 17. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG17 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x48++0x3 line.long 0x0 "PRUSS_DBG_GPREG18,DEBUG PRU GENERAL PURPOSE REGISTER 18. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG18 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x4C++0x3 line.long 0x0 "PRUSS_DBG_GPREG19,DEBUG PRU GENERAL PURPOSE REGISTER 19. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG19 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x50++0x3 line.long 0x0 "PRUSS_DBG_GPREG20,DEBUG PRU GENERAL PURPOSE REGISTER 20. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG20 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x54++0x3 line.long 0x0 "PRUSS_DBG_GPREG21,DEBUG PRU GENERAL PURPOSE REGISTER 21. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG21 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x58++0x3 line.long 0x0 "PRUSS_DBG_GPREG22,DEBUG PRU GENERAL PURPOSE REGISTER 22. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG22 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x5C++0x3 line.long 0x0 "PRUSS_DBG_GPREG23,DEBUG PRU GENERAL PURPOSE REGISTER 23. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG23 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x60++0x3 line.long 0x0 "PRUSS_DBG_GPREG24,DEBUG PRU GENERAL PURPOSE REGISTER 24. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG24 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x64++0x3 line.long 0x0 "PRUSS_DBG_GPREG25,DEBUG PRU GENERAL PURPOSE REGISTER 25. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG25 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x68++0x3 line.long 0x0 "PRUSS_DBG_GPREG26,DEBUG PRU GENERAL PURPOSE REGISTER 26. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG26 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x6C++0x3 line.long 0x0 "PRUSS_DBG_GPREG27,DEBUG PRU GENERAL PURPOSE REGISTER 27. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG27 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x70++0x3 line.long 0x0 "PRUSS_DBG_GPREG28,DEBUG PRU GENERAL PURPOSE REGISTER 28. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG28 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x74++0x3 line.long 0x0 "PRUSS_DBG_GPREG29,DEBUG PRU GENERAL PURPOSE REGISTER 29. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG29 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x78++0x3 line.long 0x0 "PRUSS_DBG_GPREG30,DEBUG PRU GENERAL PURPOSE REGISTER 30. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG30 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x7C++0x3 line.long 0x0 "PRUSS_DBG_GPREG31,DEBUG PRU GENERAL PURPOSE REGISTER 31. This register allows an external agent to debug the PRU while it is disabled. Reading or writing to these registers will have the same effect as a read or write to these registers from an internal instruction in the PRU. For R30, this includes generation of the pulse outputs whenever the register is written." hexmask.long 0x0 0.--31. 1. " GP_REG31 ,PRU Internal GP Register n: Reading / writing this field directly inspects/modifies the corresponding internal register in the PRU internal regfile" group.byte 0x80++0x3 line.long 0x0 "PRUSS_DBG_CT_REG0,DEBUG PRU CONSTANTS TABLE ENTRY 0. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG0 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x84++0x3 line.long 0x0 "PRUSS_DBG_CT_REG1,DEBUG PRU CONSTANTS TABLE ENTRY 1. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG1 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x88++0x3 line.long 0x0 "PRUSS_DBG_CT_REG2,DEBUG PRU CONSTANTS TABLE ENTRY 2. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG2 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x8C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG3,DEBUG PRU CONSTANTS TABLE ENTRY 3. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG3 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x90++0x3 line.long 0x0 "PRUSS_DBG_CT_REG4,DEBUG PRU CONSTANTS TABLE ENTRY 4. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG4 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x94++0x3 line.long 0x0 "PRUSS_DBG_CT_REG5,DEBUG PRU CONSTANTS TABLE ENTRY 5. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG5 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x98++0x3 line.long 0x0 "PRUSS_DBG_CT_REG6,DEBUG PRU CONSTANTS TABLE ENTRY 6. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG6 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0x9C++0x3 line.long 0x0 "PRUSS_DBG_CT_REG7,DEBUG PRU CONSTANTS TABLE ENTRY 7. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG7 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG8,DEBUG PRU CONSTANTS TABLE ENTRY 8. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG8 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG9,DEBUG PRU CONSTANTS TABLE ENTRY 9. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG9 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xA8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG10,DEBUG PRU CONSTANTS TABLE ENTRY 10. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG10 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xAC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG11,DEBUG PRU CONSTANTS TABLE ENTRY 11. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG11 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG12,DEBUG PRU CONSTANTS TABLE ENTRY 12. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG12 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG13,DEBUG PRU CONSTANTS TABLE ENTRY 13. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG13 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xB8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG14,DEBUG PRU CONSTANTS TABLE ENTRY 14. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG14 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xBC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG15,DEBUG PRU CONSTANTS TABLE ENTRY 15. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG15 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG16,DEBUG PRU CONSTANTS TABLE ENTRY 16. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG16 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG17,DEBUG PRU CONSTANTS TABLE ENTRY 17. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG17 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xC8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG18,DEBUG PRU CONSTANTS TABLE ENTRY 18. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG18 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xCC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG19,DEBUG PRU CONSTANTS TABLE ENTRY 19. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG19 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG20,DEBUG PRU CONSTANTS TABLE ENTRY 20. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG20 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG21,DEBUG PRU CONSTANTS TABLE ENTRY 21. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG21 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xD8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG22,DEBUG PRU CONSTANTS TABLE ENTRY 22. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG22 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xDC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG23,DEBUG PRU CONSTANTS TABLE ENTRY 23. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG23 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table." group.byte 0xE0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG24,DEBUG PRU CONSTANTS TABLE ENTRY 24. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG24 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c24_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00000n00, n=c24_blk_index[3:0]." group.byte 0xE4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG25,DEBUG PRU CONSTANTS TABLE ENTRY 25. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG25 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c25_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00002n00, n=c25_blk_index[3:0]." group.byte 0xE8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG26,DEBUG PRU CONSTANTS TABLE ENTRY 26. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG26 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c26_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x0002En00, n=c26_blk_index[3:0]." group.byte 0xEC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG27,DEBUG PRU CONSTANTS TABLE ENTRY 27. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG27 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c27_blk_index in the PRU Control register. The reset value for this Constant Table Entry is 0x00032n00, n=c27_blk_index[3:0]." group.byte 0xF0++0x3 line.long 0x0 "PRUSS_DBG_CT_REG28,DEBUG PRU CONSTANTS TABLE ENTRY 28. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG28 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c28_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x00nnnn00, nnnn=c28_pointer[15:0]." group.byte 0xF4++0x3 line.long 0x0 "PRUSS_DBG_CT_REG29,DEBUG PRU CONSTANTS TABLE ENTRY 29. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG29 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c29_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x49nnnn00, nnnn=c29_pointer[15:0]." group.byte 0xF8++0x3 line.long 0x0 "PRUSS_DBG_CT_REG30,DEBUG PRU CONSTANTS TABLE ENTRY 30. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG30 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c30_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x40nnnn00, nnnn=c30_pointer[15:0]." group.byte 0xFC++0x3 line.long 0x0 "PRUSS_DBG_CT_REG31,DEBUG PRU CONSTANTS TABLE ENTRY 31. This register allows an external agent to debug the PRU while it is disabled. Since some of the constants table entries may actually depend on system inputs / and or the internal state of the PRU, these registers are provided to allow an external agent to easily determine the state of the constants table." hexmask.long 0x0 0.--31. 1. " CT_REG31 ,PRU Internal Constants Table Entry n: Reading this field directly inspects the corresponding entry in the PRU internal constants table. This entry is partially programmable through the c31_pointer in the PRU Control register. The reset value for this Constant Table Entry is 0x80nnnn00, nnnn=c31_pointer[15:0]." width 0x0B tree.end tree.end endif textline ""